82a834rv100.pdf

HT82A834R
USB Audio MCU
Features
· Operating voltage: fSYS = 6M/12MHz: 3.3V~5.5V
· Two hardware implemented Isochronous transfers
· 24 bidirectional I/O lines (max.)
· Total FIFO size: 496 bytes
(8, 8, 384, 64, 32 for EP0~EP4)
· Two 16-bit programmable timer/event counters and
· Programmable frequency divider (PFD)
overflow interrupts
· 4096´15 program memory ROM
· Integrated SPI hardware circuit
· 192´8 data memory RAM (Bank 0)
· Play/Record Interrupt
· USB 2.0 full speed compatible
· HALT and wake-up features reduce power
consumption
· USB spec V1.1 full speed operation and USB audio
· Watchdog Timer
device class spec V1.0
· Embedded high-performance 16 bit PCM ADC
· 16-level subroutine nesting
· Built-in Digital PGA (Programmable Gain Amplifier)
· Bit manipulation instruction
· 48kHz/8kHz sampling rate for audio playback
· 15-bit table read instruction
· 63 powerful instructions
controlled by software option
· 8kHz/16kHz audio recording sampling rate
· All instructions executed within one or two machine
· Embedded class AB speaker driver power amplifier
cycles
· Embedded High Performance 16 bit audio DAC
· Low voltage reset function (3.0V±0.3V)
· Supports audio playback digital volume control
· 48-pin SSOP/LQFP package
· 5 endpoints supported (endpoint 0 included)
· Supports 1 Control, 2 Interrupt, 2 Isochronous
transfer
General Description
sampling rate of 48kHz/8kHz and the 16-bit PCM ADC
operates at 8/16kHz for the Microphone input. For the
DAC, the HT82A834R has a digital programmable gain
amplifier. The gain range is from -32dB to +6dB. For the
ADC input, the digital gain range is from 0dB to 19.5dB.
The HT82A834R is an 8-bit high performance RISC-like
microcontroller designed for USB Phone product
applications. The HT82A834R combines a 16-bit PCM
ADC, USB transceiver, SIE (Serial Interface Engine),
audio class processing unit, FIFO and an 8-bit MCU into
a single chip. The DAC in the HT82A834R operates at a
Rev. 1.00
1
August 27, 2007
HT82A834R
Block Diagram
S T A C K 0
B P
S T A C K 1
S T A C K 2
P ro g ra m
C o u n te r
M
S T A C K 1 5
M
T M R 0 C
M
M P
U
X
/4
Y S
P C 1 /T M R 0
IN T C
T M R 0
In s tr u c tio n
R e g is te r
U
T M R 1
S T A C K 1 4
P ro g ra m
R O M
fS
T M R 1 C
In te rru p t
C ir c u it
fS
U
X
D A T A
M e m o ry
X
E N /D IS
W D T P r e s c a le r
P A C
P O R T A
P A
S T A T U S
A L U
S h ifte r
P B C
P O R T B
P B
O S C I
U S B D P
U S B D N
V 3 3 O
V A G
T G
T IT I+
A V D D 3
P C C
A C C
U S B 1 .1 X C V R
3 .3 V R e g u la to r
1 6 - b it P C M
A /D C o n v e rte r
U
fS
X
/4
Y S
W D T O S C
U
R e c o rd
W r ite
D a ta
P A 0 ~ P A 7
P B 0 ~ P B 7
P C 3
M
S e r ia l
In te rfa c e
F IF O
M
P O R T C
P C
U S B 1 .1
F u ll S p e e d E n g in e
D ig ita l
P G A
A V S S 3
V A G R e f
M
W D T
M U X
In s tr u c tio n
D e c o d e r
O S C O
/4
P C 2 /T M R 1
W D T S
T im in g
G e n e ra to r
Y S
IS O
P ro c e s s
P F D
U
X
P C 4 ~ P C 7
(S D O , S D I, S C S , S C K )
P C 0 /B Z
D ig ita l
V o lu m e
C o n tro l
X
D A C
W r ite
D a ta
M U X
M
1 6 - b it
D /A
U
X
P o w e r
A m p
L O U T
R O U T
M U S IC _ IN
Rev. 1.00
2
August 27, 2007
HT82A834R
Pin Assignment
P A 3
1
4 8
P A 4
P A 2
2
4 7
P A 5
U S B D P
4 1
U S B D N
A V S S 1
9
4 0
D V D D 1
B IA S
1 0
3 9
R E S E T
M U S IC _ IN
1 1
3 8
O S C O
A V D D 1
1 2
3 7
O S C I
A V D D 3
1 3
3 6
P C 0 /B Z
V A G R e f
1 4
3 5
P C 1 /T M R 0
V A G
1 5
3 4
P C 2 /T M R 1
T I+
1 6
3 3
P C 3
T I-
1 7
3 2
P C 4 /S D O
3 1
P C 5 /S D I
1 9
3 0
P C 6 /S C S
P B 7
2 0
2 9
P C 7 /S C K
P B 6
2 1
2 8
P B 0
P B 1
P B 5
2 2
2 7
P B 4
2 3
2 6
P B 2
D V S S 2
2 4
2 5
P B 3
4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7
1
3 6
2
3 5
4
3 3
3 4
3
5
H T 8 2 A 8 3 4 R
4 8 L Q F P -A
6
7
8
3 1
3 0
2 9
2 8
9
2 7
1 0
2 6
1 1
1 2
3 2
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
2 5
U S B D N
D V D D 1
R E S E T
O S C O
O S C I
P C 0 /B Z
P C 1 /T M
P C 2 /T M
P C 3
P C 4 /S D
P C 5 /S D
P C 6 /S C
S
R 0
R 1
I
O
7 /S C K
0
1
2
3
S S 2
4
5
6
7
S S 3
1 8
R O U T
L O U T
A V S S 2
A V S S 1
B IA S
M U S IC _ IN
A V D D 1
A V D D 3
V A G R e f
V A G
T I+
T I-
P C
P B
P B
P B
P B
D V
P B
P B
P B
P B
A V
T G
T G
A V S S 3
P
4 2
8
1
7
O
L O U T
A V S S 2
7
V 3 3 O
6
D V S S 1
4 3
5
4 4
6
4
5
R O U T
3
A V D D 2
2
P A 7
1
P A 6
4 5
0
4 6
4
2
3
U S B D
V 3 3
D V S S
P A
P A
P A
P A
P A
P A
P A
P A
A V D D
P A 1
P A 0
H T 8 2 A 8 3 4 R
4 8 S S O P -A
Pin Description
Pin Name
I/O
Description
PA0~PA7
I/O
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by a
configuration option. Software instructions determine if the pin is a CMOS output or Schmitt
trigger input with or without a pull-high resistor (by configuration option).
AVDD2
¾
Audio power amplifier positive power supply
ROUT
O
Right driver analog output
LOUT
O
Left driver analog output
AVSS2
¾
Audio power amplifier negative power supply, ground
AVSS1
¾
Audio DAC negative power supply, ground
BIAS
¾
A capacitor should be connected to ground to increase half-supply stability
MUSIC_IN
I
Power amplifier signal source if register bit SELW =²1². The analog signal input will amplify by
the power amp then output to ROUT and LOUT at the same time.
AVDD1
¾
Audio DAC positive power supply
AVDD3
¾
ADC positive power supply
VAGRef
O
ADC analog ground reference voltage (should left open or connect a bypass capacitor
(Ex:100 pF) to ground)
VAG
O
ADC analog ground voltage (should connect a bypass capacitor (Ex:1 uF) to ground)
TI+
I
OP AMP non-inverting input
TI-
I
OP AMP inverting input
TG
O
OP AMP gain setting output
Rev. 1.00
3
August 27, 2007
HT82A834R
Pin Name
I/O
Description
AVSS3
¾
ADC negative power supply, ground
PB7~PB0
I/O
Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output
or Schmitt trigger input with pull-high resistor (determined by pull-high options, bit option).
DVSS2
¾
Negative digital & I/O power supply, ground
PC7/SCK
I/O
Can be software optioned as a bidirectional input/output or serial interface clock signal.
PC6/SCS
I/O
Can be software optioned as a bidirectional input/output or serial interface slave select signal.
PC5/SDI
I/O
or I
Can be software optioned as a bidirectional input/output or serial data input.
PC4/SDO
I/O
Can be software optioned as a bidirectional input/output or serial data output.
or O
PC3
I/O
Bidirectional I/O lines. Software instructions determine if the pin is a CMOS output or Schmitt
trigger input with pull-high resistor (determined by configuration option).
PC2/TMR1,
PC1/TMR0
I/O
Software instructions determine if the pin is a CMOS output or Schmitt trigger input with pull-high
resistor. TMR0, TMR1 are pin shared with PC1, PC2 respectively
PC0/BZ
I/O
Can be software optioned as a bidirectional input/output or as a PFD output.
or O
OSCI
OSCO
I
O
OSCI, OSCO are connected to an 6MHz or 12MHz crystal/resonator (determined by software
instructions) for the internal system clock
RESET
I
Schmitt trigger reset input, active low
DVDD1
¾
Positive digital power supply
USBDN
I/O
USBD- line. The USB function is controlled by a software control register
USBDP
I/O
USBD+ line. The USB function is controlled by a software control register
V33O
O
3.3V regulator output
DVSS1
¾
Negative digital power supply, ground
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
IOL Total ..............................................................150mA
IOH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device
reliability.
Rev. 1.00
4
August 27, 2007
HT82A834R
D.C. Characteristics
Symbol
VDD
IDD
Parameter
Operating Voltage
Ta=25°C
Test Conditions
VDD
Conditions
¾
5V
Min.
Typ.
Max.
Unit
3.3
5.0
5.5
V
5V
No load, fSYS=12MHz,
ADC On, DAC On
¾
12
¾
mA
5V
No load, fSYS=12MHz,
ADC Off, DAC Off
¾
8
¾
mA
Operating Current
ISUS
Suspend Current
5V
No load, system HALT,
USB transceiver and 3.3V
regulator on
¾
330
¾
mA
VIL1
Input Low Voltage for I/O Ports
5V
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports
5V
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RESET)
5V
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RESET)
5V
¾
0.9VDD
¾
VDD
V
IOL
I/O Port Sink Current
5V
VOL=0.1VDD
¾
5
¾
mA
IOH
I/O Port Source Current
5V
VOH=0.7VDD
¾
-5
¾
mA
RPH
Pull-high Resistance
5V
30
40
80
kW
VLVR
Low Voltage Reset
5V
VV33O
3.3V Regulator Output
5V
¾
¾
IV33O=-5mA
2.7
3.0
3.3
V
3.0
3.3
3.6
V
DAC+Power Amp:
Test condition: Measurement bandwidth 20Hz to 20kHz, fS= 48kHz. Line output series capacitor with 220mF.
THD+N
THD+NNote1
SNRDA
Signal to Noise RatioNote1
DR
Dynamic Range
POUT
Output Power
5V
5V
5V
5V
4W load
¾
-30
¾
8W load
¾
-35
¾
4W load
¾
81
¾
8W load
¾
82
¾
4W load
¾
87
¾
8W load
¾
88
¾
4W load, THD=10%
¾
400
¾
8W load, THD=10%
¾
200
¾
dB
dB
dB
mW/ch
PCM ADC
Signal to Noise Ratio
5V
¾
¾
77
¾
dB
VAG
Reference Voltage
5V
¾
¾
2
¾
V
VPEAK
Peak Single Frequency Tone
Amplitude without Clipping
5V
¾
¾
1.575
¾
VPK
SNRAD
Note.1: Sine wave input at 1kHz, -6dB
A.C. Characteristics
Symbol
fSYS
Parameter
System Clock (Crystal OSC)
Ta=25°C
Test Conditions
Min.
Typ.
Max.
Unit
¾
0.4
¾
12
MHz
VDD
Conditions
5V
tWDTOSC Watchdog Oscillator Period
5V
¾
¾
100
¾
ms
tRES
RESET Input Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
Note: tSYS=1/fSYS
Rev. 1.00
5
August 27, 2007
HT82A834R
Functional Description
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
Execution Flow
The system clock for the microcontroller is sourced from
a crystal oscillator. The system clock is internally divided
into four non-overlapping clocks. One instruction cycle
consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading to the PCL register, performing a subroutine call or return from subroutine, initial reset,
internal interrupt, external interrupt or return from interrupts, the PC manipulates the program transfer by loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to be effectively executed in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of program memory.
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
USB Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
1
1
0
0
Play Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
Serial Interface Interrupt
0
0
0
0
0
0
0
1
0
1
0
0
Record Interrupt
0
0
0
0
0
0
0
1
1
0
0
0
Skip
Program Counter+2
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *11~*0: Program counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
Rev. 1.00
@[email protected]: PCL bits
6
August 27, 2007
HT82A834R
· Location 018H
within the current program ROM page.
This area is reserved for the record interrupt service
program. If the record data valid, the interrupt is enabled and the stack is not full, the program begins execution at location 018H.
When a control transfer takes place, an additional
dummy cycle is required.
Program Memory - PROM
· Table location
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
4096´15 bits, addressed by the program counter and table pointer.
Any location in the program memory can be used as a
look-up table. There are three methods to read the
ROM data using two table read instructions:
²TABRDC² and ²TABRDL², transfer the contents of
the lower-order byte to the specified data memory,
and the higher-order byte to TBLH (08H).
The three methods are shown as follows:
Certain locations in the program memory are reserved
for special usage:
¨
The instruction ²TABRDC [m]² (the current page,
one page=256 words), where the table location is
defined by TBLP (07H) in the current page. The
configuration option, TBHP, is disabled (default).
¨
The instruction ²TABRDC [m]², where the table location is defined by registers TBLP (07H) and
TBHP (01FH). The configuration option, TBHP, is
enabled.
¨
The instruction ²TABRDL [m]², where the table locations is defined by register TBLP (07H) in the last
page (0F00H~0FFFH).
· Location 000H
This area is reserved for program initialization. After a
chip reset, the program always begins execution at location 000H.
· Location 004H
This area is reserved for the USB interrupt service
program. If the USB interrupt is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
· Location 008H
0 0 0 H
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program
begins execution at location 008H.
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
0 0 8 H
0 0 C H
· Location 00CH
This area is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and the interrupt is enabled and the stack is not full, the program
begins execution at location 00CH.
U S B In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e
0 1 0 H
0 1 4 H
P la y In te r r u p t S u b r o u tin e
S e r ia l In te r fa c e In te r r u p t S u b r o u tin e
0 1 8 H
P ro g ra m
M e m o ry
R e c o r d In te r r u p t S u b r o u tin e
· Location 010H
This area is reserved for the play interrupt service program. If play data is valid, and the interrupt is enabled
and the stack is not full, the program begins execution
at location 010H.
n 0 0 H
· Location 014H
F 0 0 H
This area is reserved for when 8 bits of data have
been received or transmitted successfully from the serial interface. If the related interrupts are enabled, and
the stack is not full, the program begins execution at
location 014H.
Instruction
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
L o o k - u p T a b le ( 2 5 6 w o r d s )
F F F H
1 5 b its
N o te : n ra n g e s fro m
1 to F
Program Memory
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *11~*0: Table location bits
P11~P8: Current program counter bits when TBHP is disabled
P11~P8: Current program counter bits
@[email protected]: Table pointer bits
TBHP register bit3~bit0 when TBHP is enabled
Rev. 1.00
7
August 27, 2007
HT82A834R
Data Memory - RAM
Only the destination of the lower-order byte in the table is
well-defined, the other bits of the table word are
transferred to the lower portion of TBLH, and the
remaining 1-bit words are read as ²0². The Table
Higher-order byte register (TBLH) is read only. The table
pointer (TBLP, TBHP) is a read/write register (07H, 1FH),
which indicates the table location. Before accessing the
table, the location must be placed in the TBLP and TBHP
registers. (If the configuration option TBHP is disabled,
the value in TBHP has no effect). TBLH is read only and
cannot be restored. If the main routine and the ISR
(Interrupt Service Routine) both employ the table read
instruction, the contents of the TBLH in the main routine
is likely to be changed by the table read instruction used
in the ISR. As a result errors may occur. In other words,
using the table read instruction in the main routine and in
the ISR simultaneously should be avoided. However, if
the table read instruction has to be applied in both the
main routine and the ISR, the interrupt should be
disabled prior to the table read instruction.
The data memory is divided into two functional groups:
namely; special function registers and general purpose
data memory, Bank 0: 192´8 bits. Most are read/write,
but some are read only.
The special function registers include the indirect
addressing registers (R0;00H, R1;02H), Bank register
(BP;04H), Timer/Event Counter 0 higher order byte
register (TMR0H;0CH), Timer/Event Counter 0 lower
order byte register (TMR0L;0DH), Timer/Event Counter
0 control register (TMR0C;0EH), Timer/Event Counter 1
higher order byte register (TMR1H;0FH), Timer/Event
Counter 1 lower order byte register (TMR1L;10H),
Timer/Event Counter 1 control register (TMR1C;11H),
program counter lower-order byte register (PCL;06H),
memory pointer registers (MP0;01H, MP1;03H),
accumulator (ACC;05H), table pointer (TBLP;07H,
TBHP;1FH), table higher-order byte register
(TBLH;08H), status register (STATUS;0AH), interrupt
control register0 (INTC0;0BH), Watchdog Timer option
setting register (WDTS;09H), I/O registers (PA;12H,
PB;14H, PC;16H), I/O control registers (PAC;13H,
PBC;15H, PCC;17H). Digital Volume Control Register
(USVC;1CH).
It will not be enabled until the TBLH has been backed
up. All table related instructions require two cycles to
complete the operation. These areas may function as
normal program memory depending on the
requirements.
USB status and control register (USC;20H), USB
endpoint interrupt status register (USR;21H), system
clock control register (UCC;22H). Address and remote
wakeup register (AWR;23H), STALL register (24H),
SIES register (25H), MISC register (26H), SETIO
register (27H). FIFO0~FIFO4 register (28H~2CH).
DAC_Limit_L register (2DH), DAC_Limit_H register
(2EH), DAC_WR register (2FH). PGA_CTRL register
(30H). PFD control register (PFDC;31H). PFD data
register (PFDD;32H). MODE_CTRL register (34H).
Serial bus control register (SBCR;35H), serial bus data
register (SBDR;36H). Play data left channel
(PLAY_DATAL_L;3AH, PLAY_DATAL_H;3BH), play
data right channel (PLAY_DATAR_L;3CH, PLAY_
DATAR_H;3DH). Record data (RECORD_DATA_L;
3EH, RECORD_DATA_H; 3FH).
Once the TBHP is enabled, the instruction ²TABRDC
[m]² reads the ROM data as defined by the TBLP and
TBHP register value. Otherwise, if the configuration
option TBHP is disabled, the instruction ²TABRDC [m]²
reads the ROM data as defined by TBLP and the current
program counter bits.
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 16 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the stack pointer will point to
the top of the stack.
The remaining space before the 40H is reserved for
future expanded usage, reading these locations will
return a result of ²00H². The general purpose data
memory, addressed from 40H to FFH, is used for data
and control information under instruction commands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations
directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0 or MP1).
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 16 return addresses are stored).
Rev. 1.00
8
August 27, 2007
HT82A834R
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 8 H
2 9 H
2 A H
2 B H
2 C H
2 D H
2 E H
2 F H
3 0 H
3 1 H
3 2 H
3 3 H
3 4 H
3 5 H
3 6 H
3 7 H
3 8 H
3 9 H
3 A H
3 B H
3 C H
3 D H
3 E H
3 F H
4 0 H
F F H
B a n k 0 S p e c ia l R e g is te r
In d ir e c t A d d r e s s in g R e g is te r 0
M P 0
In d ir e c t A d d r e s s in g R e g is te r 1
M P 1
B P
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C 0
T M R 0 H
T M R 0 L
T M R 0 C
T M R 1 H
T M R 1 L
T M R 1 C
P A
P A C
P B
P B C
P C
P C C
U S V C
U S B _ S T A T
IN T C 1
T B H P
U S C
U S R
U C C
A W R
S T A L L
S IE S
M IS C
S E T IO
F IF O 0
F IF O 1
F IF O 2
F IF O 3
F IF O 4
D A C _ L IM IT
D A C _ L IM IT
D A C _ W R
P G A _ C T R
P F D C
P F D D
M O D E
S B
S B
R E C O R
R E C O R
P L A Y
P L A Y
P L A Y
P L A Y
R E C O
R E C O
_ D
_ D
_ D
_ D
R D
R D
Indirect Addressing Register
Locations 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write
operation on [00H] ([02H]) will access the data memory
pointed to by MP0 (MP1). Reading location 00H (02H)
indirectly will return the result 00H. Writing indirectly results in no operation.
The function of data movement between two indirect addressing registers is not supported. The memory pointer
registers (MP0 and MP1) are 8-bit registers used to access the RAM by combining corresponding indirect addressing registers.
Bank Pointer
The bank pointer is used to assign the accessed RAM
bank. When the users want to access the RAM bank 0, a
²0² should be loaded onto BP. RAM locations before
40H in any bank are overlapped.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
E
S p e c ia l P u r p o s e
D a ta M e m o ry
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
_ L
_ H
Status Register - STATUS
L
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
_ C T R L
C R
D R
D _ IN _ L
D _ IN _ H
A T
A T
A T
A T
_ D
_ D
A L
A L
A R
A R
A T
A T
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results from those intended.
_ L
_ H
_ L
_ H
A _ L
A _ H
G e n e ra l P u rp o s e
D a ta R A M
(1 9 2 B y te s )
The TO flag can be affected only by a system power-up,
a WDT time-out or executing the ²CLR WDT² or ²HALT²
instruction. The Z, OV, AC and C flags generally reflect
the status of the latest operations.
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
Rev. 1.00
9
August 27, 2007
HT82A834R
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by
executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
The USB interrupts are triggered by the following USB
events and the related interrupt request flag (USBF; bit
4 of the INTC0) will be set.
In addition, upon entering the interrupt sequence or executing a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
· Accessing the corresponding USB FIFO from the PC
· The USB suspend signal from the PC
· The USB resume signal from the PC
· USB Reset signal
Interrupt
When the interrupt is enabled, the stack is not full and
the USB interrupt is active, a subroutine call to location
04H will occur. The interrupt request flag (USBF) and
EMI bits will be cleared to disable other interrupts.
The device provides a USB interrupt, internal
timer/event counter interrupts, play/record data valid
interrupt and a serial interface interrupt. The Interrupt
Control Register0 (INTC0;0BH) and interrupt control
register1 (INTC1;1EH) both contain the interrupt control
bits that are used to set the enable/disable status and
interrupt request flags.
When the PC Host accesses the FIFO of the
HT82A834R, the corresponding request bit of the USR
is set, and a USB interrupt is triggered. So the user can
easily determine which FIFO has been accessed. When
the interrupt has been served, the corresponding bit
should be cleared by firmware. When the HT82A834R
receives a USB Suspend signal from the Host PC, the
suspend line (bit0 of USC) of the HT82A834R is set and
a USB interrupt is also triggered.
Once an interrupt subroutine is serviced, all the other
interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain
interrupt requires servicing within the service routine,
the EMI bit and the corresponding bit of the INTC0 or
INTC1 may be set to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged,
even if the related interrupt is enabled, until the stack
pointer is decremented. If immediate service is desired,
the stack must be prevented from becoming full.
Also when the HT82A834R receives a Resume signal
from the Host PC, the resume line (bit3 of USC) of the
HT82A834R is set and a USB interrupt is triggered.
The internal Timer/Event Counter 0 interrupt is
initialized by setting the Timer/Event Counter 0 interrupt
request flag (bit 5 of INTC0), caused by a timer 0
overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further
interrupts.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register or status
register (STATUS) are altered by the interrupt service
program which corrupts the desired control sequence,
the contents should be saved in advance.
Rev. 1.00
The internal Timer/Event counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
flag (bit 6 of INTC0), caused by a timer 1 overflow. When
the interrupt is enabled, the stack is not full and T1F is
set, a subroutine call to location 0CH will occur. The
10
August 27, 2007
HT82A834R
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enable; 0=disable)
1
EUI
Controls the USB interrupt (1=enable; 0=disable)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)
4
USBF
5
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
7
¾
USB interrupt request flag (1=active; 0=inactive)
Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No.
Label
0
EPLAYI
1
ESII
2
RECI
3, 7
¾
4
PLAYF
5
SIF
6
RECF
Function
Play interrupt (1=enable; 0=disable)
Control Serial interface interrupt (1=enable; 0=disable)
Record interrupt (1=enable; 0=disable)
Unused bit, read as ²0²
Play interrupt request flag (1=active; 0=inactive)
Serial interface interrupt request flag (1=active; 0=inactive)
Record interrupt request flag (1=active; 0=inactive)
INTC1 (1EH) Register
During the execution of an interrupt subroutine, other
interrupt acknowledge signals are held until the ²RETI²
instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
related interrupt request flag (T1F) will be reset and the
EMI bit cleared to disable further interrupts.
The play interrupt is initialized by setting the play
interrupt request flag (bit 4 of INTC1), caused by a play
data valid. When the interrupt is enabled, the stack is not
full and the PLAYF is set, a subroutine call to location
10H will occur. The related interrupt request flag
(PLAYF) will be reset and the EMI bit cleared to disable
further interrupts. If PLAY_MODE (bit 3 of MODE_CTRL
register) is set to ²1², the play interrupt frequency will
change to 8KHz, otherwise the interrupt frequency is
48kHz.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding
interrupts are enabled. In the case of simultaneous
requests the following table shows the priority that is
applied. These can be masked by resetting the EMI bit.
The serial interface interrupt is indicated by the interrupt
flag (SIF; bit 5 of INTC1), that is generated by the
reception or transfer of a complete 8-bits of data
between the HT82A834R and the external device. The
serial interface interrupt is controlled by setting the
Serial interface interrupt control bit (ESII; bit 1 of
INTC1). After the interrupt is enabled (by setting SBEN;
bit 4 of SBCR), and the stack is not full and the SIF is set,
a subroutine call to location 14H occurs.
Interrupt Source
The record interrupt is initialized by setting the record
interrupt request flag (bit 6 of INTC1), caused by a
record data valid. When the interrupt is enabled, the
stack is not full and RECF is set, a subroutine call to
location 18H will occur. The related interrupt request flag
(RECF) will be reset and the EMI bit cleared to disable
further interrupts. If ADC powered down (AD_ENB =1)
or USB clock disabled (USBCKEN=0), the record
interrupt will be disabled.
Rev. 1.00
Priority
Vector
USB interrupt
1
04H
Timer/Event Counter 0 overflow
2
08H
Timer/Event Counter 1 overflow
3
0CH
Play Interrupt
4
10H
Serial Interface Interrupt
5
14H
Record Interrupt
6
18H
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be
damaged once the ²CALL² operates in the interrupt
subroutine.
11
August 27, 2007
HT82A834R
Oscillator Configuration
(system clock/4). The timer is designed to prevent a
software malfunction or sequence from jumping to an
unknown location with unpredictable results. The WDT
can be disabled by a configuration option. However, if
the WDT is disabled, all executions related to the WDT
lead to no operation.
The microcontroller contains an integrated oscillator circuit.
O S C I
When the WDT clock source is selected, it will be first
divided by 256 (8-stage) to get the nominal time-out
period. By invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2, WS1,
WS0 can give different time-out periods.
O S C O
C r y s ta l O s c illa to r
System Oscillator
This oscillator is designed for the system clock. The
HALT mode stops the system oscillator and ignores any
external signals to conserve power.
The WDT OSC period is typically 65ms. This time-out
period may vary with temperature, VDD and process
variations. The WDT OSC always keeps running in any
operation mode.
A crystal across OSCI and OSCO is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. If preferred,
a resonator can also be connected between OSCI and
OSCO for oscillation to occur, but two external
capacitors connected between OSCI, OSCO and
ground are required.
If the instruction clock is selected as the WDT clock
source, the WDT operates in the same manner except in
the HALT mode. In the HALT mode, the WDT stops
counting and lose its protecting purpose. In this situation
the logic can only be re-started by external logic. The
high nibble of the WDTS is reserved for the DAC write
mode.
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock stops running, but the WDT oscillator still
continues to run. The WDT oscillator can be disabled by
a configuration option to conserve power.
The WDT overflow under normal operation initializes a
²chip reset² and sets the status bit ²TO². In the HALT
mode, the overflow initializes a ²warm reset², and only
the program counter and stack pointer are reset to zero.
To clear the contents of the WDT, there are three methods to be adopted, i.e., an external reset (a low level to
RESET), a software instruction, and a ²HALT² instruction. There are two types of software instructions; ²CLR
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or the instruction clock
Bit No.
0
1
2
Label
WS0
WS1
WS2
Watchdog Timer division ratio selection bits
Bit 2,1,0 = 000, Division Ratio = 1:1
Bit 2,1,0 = 001, Division Ratio = 1:2
Bit 2,1,0 = 010, Division Ratio = 1:4
Bit 2,1,0 = 011, Division Ratio = 1:8
Bit 2,1,0 = 100, Division Ratio = 1:16
Bit 2,1,0 = 101, Division Ratio = 1:32
Bit 2,1,0 = 110, Division Ratio = 1:64
Bit 2,1,0 = 111, Division Ratio = 1:128
Unused bit, read as ²0²
3
7~4
Function
T3~T0
Test mode setting bits
(T3,T2,T1,T0) = (0,1,0,1), enter DAC write mode. Otherwise normal operation.
WDTS (09H) Register
W D T O S C
S y s te m C lo c k /4
M a s k
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
W S 0 ~ W S 2
7 - b it C o u n te r
8 -to -1 M U X
W D T T im e - o u t
Watchdog Timer
Rev. 1.00
12
August 27, 2007
HT82A834R
WDT² and the other set ²CLR WDT1² and ²CLR
WDT2². Of these two types of instruction, only one type
of instruction can be active at a time depending on the
configuration option ²CLR WDT² times selection option.
If the ²CLR WDT² is selected (i.e., CLR WDT times
equal one), any execution of the ²CLR WDT² instruction
clears the WDT. In the case that ²CLR WDT1² and ²CLR
WDT2² are chosen (i.e., CLR WDT times equal two),
these two instructions have to be executed to clear the
WDT; otherwise, the WDT may reset the chip due to a
time-out.
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
Power Down Operation - HALT
· RES reset during HALT
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
The ADC, DAC and PA will all be powered down when in
the HALT mode.
Reset
There are four ways in which a reset can occur:
· RES reset during normal operation
· WDT time-out reset during normal operation
The HALT mode is initialized by the ²HALT² instruction
and results in the following:
· USB reset
The
time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the program counter and stack
pointer, leaving the other circuits in their original state.
Some registers remain unchanged during other reset
conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. By examining
the PDF and TO flags, the program can distinguish between different ²chip resets².
· The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is selected).
· The contents of the on-chip RAM and registers remain
unchanged.
· The WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator).
· All of the I/O ports remain in their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PDF flags are
examined, the cause for chip reset can be determined.
The PDF flag is cleared by a system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the program counter and stack pointer; the others
remain in their original status.
PDF
0
0
RESET reset during power-up
RESET Conditions
u
u
RESET reset during normal operation
0
1
RESET wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the system resets (power-up, WDT time-out or RES reset) or
the system awakes from the HALT state.
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by configuration option. Awakening from an I/O
port stimulus, the program will resume execution of the
next instruction. If it awakens from an interrupt, two sequence may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is
set to ²1² before entering the HALT mode, the wake-up
function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
Rev. 1.00
TO
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay.
The functional unit chip reset status are shown below.
Program Counter
000H
Interrupt
Disable
WDT
Clear. After master reset,
WDT begins counting
Timer/event Counter Off
13
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
August 27, 2007
HT82A834R
V
H A L T
D D
W a rm
R e s e t
W D T
1 0 0 k W
0 .0 1 m F
R E S E T
R E S E T
C o ld
R e s e t
1 0 k W
0 .1 m F
S S T
1 0 - b it R ip p le
C o u n te r
O S C I
Reset Circuit
S y s te m
V D D
R e s e t
Reset Configuration
R E S
tS
S T
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
The registers status are summarized in the following table.
Register
Reset
(Power-on)
WDT
RES Reset
Time-out
RES Reset
(Normal
(Normal
(HALT)
Operation)
Operation)
WDT
Time-Out
(HALT)*
USB Reset USB Reset
(Normal)
(HALT)
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
000H
000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
0000 0111
0000 0111
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
--uu uuuu
--01 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
-000 0000
-000 0000
TMR0H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
00-0 1000
00-0 1000
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
00-0 1---
00-0 1---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
Program
Counter
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
USVC
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
USB_STATE
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
INTC1
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
-000 0000
-000 0000
Rev. 1.00
14
August 27, 2007
HT82A834R
Register
Reset
(Power-on)
WDT
RES Reset
Time-out
RES Reset
(Normal
(Normal
(HALT)
Operation)
Operation)
WDT
Time-Out
(HALT)*
USB Reset USB Reset
(Normal)
(HALT)
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
USC
1000 0000
uuxx uuuu
10xx 0000
10xx 0000
10xx uuuu
1000 0u00
1000 0u00
USR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
00uu 0000
00uu 0000
UCC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0u00 u000
0u00 u000
AWR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
STALL
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
SIES
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0u00 u000
0u00 u000
MISC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
SETIO
xxxx x010
xxxx x010
xxxx x010
xxxx x010
xxxx x010
xxxx x010
xxxx x010
FIFO0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO3
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO4
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
DAC_LIMIT_L
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
DAC_LIMIT_H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
DAC_WR
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
PGA_CTRL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
00uu uuuu
00uu uuuu
PFDC
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0uuu 0000
0uuu 0000
PFDD
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0uuu 0000
0uuu 0000
MODE_CTRL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0uuu
0000 0uuu
0000 0uuu
SBCR
0110 0000
0110 0000
0110 0000
0110 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
SBDR
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
RECORD_IN_L
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
RECORD_IN_H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
PLAY_DATAL_L
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
PLAY_DATAL_H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
PLAY_DATAR_L
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
PLAY_DATAR_H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
RECORD_DATA_L
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
RECORD_DATA_H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
Note: ²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
²-² stands for ²undefined²
Rev. 1.00
15
August 27, 2007
HT82A834R
timer/event counter preload register, and generates an
interrupt request flag (T0F; bit 5 of INTC0, T1F; bit 6 of
INTC0). In the pulse width measurement mode with the
values of the TON and TE bits equal to 1, after the TMR0
(TMR1) has received a transient from low to high (or
high to low if the TE bit is ²0²), it will start counting until
the TMR0 (TMR1) returns to the original level and resets
TON. The measured result remains in the timer/event
counter even if the activated transient occurs again. In
other words, only 1-cycle measurement can be made
until TON is set. The cycle measurement will re-function
as long as it receives further transient pulse. In this
operation mode, the timer/event counter begins
counting not according to the logic level but to the
transient edges. In the case of counter overflows, the
counter is reloaded from the timer/event counter
register and issues an interrupt request, as in the other
two modes, i.e., event and timer modes.
Timer/Event Counter
Two timer/event counters (TMR0, TMR1) are
implemented in the microcontroller. The Timer/Event
Counter 0/1 contains a 16-bit programmable count-up
counter and the clock may come from an external
source or an internal clock source. An internal clock
source comes from fSYS/4. The external clock input
allows the user to count external events, measure time
intervals or pulse widths, or to generate an accurate
time base. There are six registers related to the
Timer/Event Counter 0; TMR0H (0CH), TMR0L (0DH),
TMR0C (0EH) and the Timer/Event Counter 1; TMR1H
(0FH), TMR1L (10H), TMR1C (11H). For 16-bit timer to
write data to TMR0/1L will only put the written data to an
internal lower-order byte buffer (8-bit) and writing
TMR0/1H will transfer the specified data and the
contents of the lower-order byte buffer to TMR0/1H and
TMR0/1L registers. The Timer/Event Counter 0/1
preload register is changed by each writing TMR0/1H
operations. Reading TMR0/1H will latch the contents of
TMR0/1H and TMR0/1L counters to the destination and
the lower-order byte buffer, respectively. Reading the
TMR0/1L will read the contents of the lower-order byte
buffer. The TMR0C (TMR1C) is the Timer/Event
Counter 0 (1) control register, which defines the
operating mode, counting enable or disable and an
active edge.
To enable the counting operation, the Timer ON bit
(TON; bit 4 of TMR0C or TMR1C) should be set to 1. In
the pulse width measurement mode, TON is
automatically cleared after the measurement cycle is
completed. But in the other two modes, TON can only be
reset by instructions. The overflow of the Timer/Event
Counter 0/1 is one of the wake-up sources. No matter
what the operation mode is, writing a 0 to ET0I or ET1I
disables the related interrupt service.
The TM0 and TM1 bits define the operation mode. The
event count mode is used to count external events,
which means that the clock source is from an external
(TMR0, TMR1) pin. The timer mode functions as a
normal timer with the clock source coming from the
internal clock source. Finally, the pulse width
measurement mode can be used to count the high level
or low level duration of the external signal (TMR0,
TMR1), and the counting is based on the internal clock
source.
In the case of timer/event counter off condition, writing
data to the timer/event counter preload register also
reloads that data to the timer/event counter. But if the
timer/event counter is turn on, data written to the
timer/event counter is kept only in the timer/event
counter preload register. The timer/event counter still
continues its operation until an overflow occurs.
When the timer/event counter (reading TMR0/TMR1) is
read, the clock is blocked to avoid errors, as this may
results in a counting error. Blocking of the clock should
be taken into account by the programmer.
In the event count or timer mode, the timer/event
counter starts counting at the current contents in the
timer/event counter and ends at FFFFH. Once an
overflow occurs, the counter is reloaded from the
fS
Y S /4
f IN
D a ta B u s
T
T M 1
T M 0
T M R 0 /1
1 6 B its
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
1 6 B its
T im e r /E v e n t C o u n te r
(T M R 0 /1 )
O v e r flo w
to In te rru p t
Timer/Event Counter 0/1
Rev. 1.00
16
August 27, 2007
HT82A834R
Bit No.
Label
0~2, 5
¾
Unused bit, read as ²0²
3
TE
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1=count on falling edge;
0=count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1=start counting on the rising edge, stop on the falling edge;
0=start counting on the falling edge, stop on the rising edge
4
TON
Enable/disable the timer counting (0=disable; 1=enable)
TM0
TM1
Defines the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
6
7
Function
TMR0C (0EH), TMR1C (11H) Register
Input/Output Ports
with or without pull-high resistor structures can be
reconfigured dynamically (i.e. on-the-fly) under software
control. To function as an input, the corresponding latch
of the control register must write ²1². The input source
also depends on the control register. If the control
register bit is ²1² the input will read the pad state. If the
control register bit is ²0² the contents of the latches will
move to the internal bus. The latter is possible in the
²Read-modify-write² instruction. For output function,
CMOS configurations can be selected. These control
registers are mapped to locations 13H, 15H, 17H.
There are 24 bidirectional input/output lines in the
micro-controller, labeled from PA to PC, which are
mapped to the data memory of [12H], [14H], [16H]
respectively. All of these I/O ports can be used for input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H,
16H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC) to control the input/output configuration. With this
control register, CMOS output or Schmitt trigger input
After a chip reset, these input/output lines remain at high
levels or floating state (depending on the pull-high
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
Q
D
C K
V
P A
P B
P C
P C
P C
P C
P C
P C
P C
P C
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
D a ta B it
Q
D
C K
S
Q
M
R e a d D a ta R e g is te r
S y s te m
U
0 ~ P
0 ~ P
0 /B
1 /T
2 /T
3
4 /S
5 /S
6 /S
7 /S
A 7
B 7
Z
M R 0
M R 1
D O
D I
C S
C K
X
W a k e - u p ( P A o n ly )
B Z fo r P
T M R 0 fo r P
T M R 1 fo r P
P
S D O fo r P
S D I fo r P
S C S fo r P
S C K fo r P
D D
C o n fig u r a tio n O p tio n
C 0
C 1
C 2
C 3
C 4
C 5
C 6
C 7
Input/Output Ports
Rev. 1.00
17
August 27, 2007
HT82A834R
options). Each bit of these input/output latches can be
set or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H,
14H, 16H ) instructions.
(bit4 of the UCC). Since the Resume signal will be
cleared before the Idle signal is sent out by the host and
the Suspend line (bit 0 of USC) will go to ²0². So when
the MCU is detecting the Suspend line (bit0 of USC), the
condition of the Resume line should be noted and taken
into consideration.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
The following is the timing diagram:
S U S P E N D
Each line of port A has the capability of waking-up the
device.
U S B R e s u m e S ig n a l
Low Voltage Reset - LVR (by Configuration Option)
U S B _ IN T
The LVR option is 3.0V.
The device with remote wake up function can wake-up
the USB Host by sending a wake-up pulse through
RMWK (bit 1 of USC). Once the USB Host receives the
wake-up signal from the HT82A834R, it will send a
Resume signal to the device. The timing is as follows:
The microcontroller provides a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, the LVR will automatically reset the device
internally.
The LVR includes the following specifications:
S U S P E N D
· The low voltage (0.9V~VLVR) condition has to remain
in its condition for a time exceeding 1ms. If the low
voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function.
R M W K
M in . 1
U S B C L K
M in . 2 .5 m s
· The LVR uses the ²OR² function with the external
U S B R e s u m e S ig n a l
RESET signal to perform a chip reset.
U S B _ IN T
Suspend Wake-Up and Remote Wake-Up
If there is no signal on the USB bus for over 3ms, the
HT82A834R will go into a suspend mode. The Suspend
line (bit 0 of the USC) will be set to ²1² and a USB
interrupt is triggered to indicate that the HT82A834R
should jump to the suspend state to meet the
requirements of the USB suspend current spec.
USB Interface
The HT82A834R device has 5 Endpoints (EP0~EP4).
EP0 supports Control transfer. EP1 and EP4 support
Interrupt transfer. EP2 supports Isochronous out
transfer. EP3 supports Isochronous in transfer.
In order to meet the requirements of the suspend
current, the firmware should disable the USB clock by
clearing USBCKEN (bit3 of UCC) to ²0².
These registers, including USC (20H), USR (21H), UCC
(22H), AWR (23H), STALL (24H), SIES (25H), MISC
(26H), FIFO0 (28H), FIFO1 (29H), FIFO2 (2AH), FIFO3
(2BH), FIFO4 (2CH) are used for the USB function.
Also the user can further decrease the suspend current
by setting SUSP2 (bit4 of the UCC).
The FIFO size of each FIFO is 8 bytes (FIFO0), 8 bytes
(FIFO1), 384 bytes (FIFO2), 64 bytes (FIFO3), 32 bytes
(FIFO4). The total is 496 bytes.
When the resume signal is sent out by the host, the
HT82A834R will be woken up by the USB interrupt and
the Resume line (bit 3 of USC) will be set. In order to
make the HT82A834R work properly, the firmware must
set USBCKEN (bit 3 of UCC) to ²1² and clear SUSP2
Rev. 1.00
URD (bit7 of USC) is the USB reset signal control
function definition bit.
18
August 27, 2007
HT82A834R
Bit No.
Label
R/W
Reset
Functions
0
SUSP
R
0
Read only, USB suspend indication. When this bit is set to ²1² (set
by SIE), it indicates that the USB bus has entered the suspend
mode. The USB interrupt is also triggered when this bit changes
from low to high.
1
RMWK
R/W
0
USB remote wake-up command. It is set by MCU to force the USB
host to leave the suspend mode.
0
USB reset indication. This bit is set/cleared by the USB SIE. This bit
is used to detect a USB reset event on the USB bus. When this bit is
set to ²1², this indicates that a USB reset has occurred and that a
USB interrupt will be initialized.
2
URST
R/W
3
RESUME
R
0
USB resume indication. When the USB leaves the suspend mode,
this bit is set to ²1² (set by SIE). When the RESUME is set by SIE, an
interrupt will be generated to wake-up the MCU. In order to detect
the suspend state, the MCU should set USBCKEN and clear
SUSP2 (in the UCC register) to enable the SIE detect function.
RESUME will be cleared when the SUSP goes to ²0². When the
MCU is detecting the SUSP, the condition of RESUME (causes the
MCU to wake-up) should be noted and taken into consideration.
4
V33C
R/W
0
0/1: Turn-off/on V33O output
5
PLLEN
R/W
0
0: Turn on PLL (default mode)
1: Turn off PLL
6
CRCFG
R/W
0
CRC error condition failure flag. CRCFG will be set by hardware and
the CRCFG need to be cleared by firmware.
7
URD
R/W
1
USB reset signal control function definition
1: USB reset signal will reset MCU
0: USB reset signal cannot reset MCU
USC (20H) Register
The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select
the serial bus (USB). The endpoint request flags (EP0F, EP1F, EP2F, EP3F, EP4F) are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to ²1² and the USB interrupt will occur (if the USB interrupt is enabled and the stack is not full). When the active endpoint request flag is
serviced, the endpoint request flag has to be cleared to ²0² by software.
Bit No.
Label
R/W
Reset
Functions
0
EP0F
R/W
0
When this bit is set to ²1² (set by SIE), it indicates that endpoint 0
has been accessed and a USB interrupt will occur. When the
interrupt has been serviced, this bit should be cleared by software.
1
EP1F
R/W
0
When this bit is set to ²1² (set by SIE), it indicates that endpoint 1
has been accessed and a USB interrupt will occur. When the
interrupt has been serviced, this bit should be cleared by software.
2
EP2F
R/W
0
When this bit is set to ²1² (set by SIE), it indicates that endpoint 2
has been accessed and a USB interrupt will occur. When the
interrupt has been serviced, this bit should be cleared by software.
3
EP3F
R/W
0
When this bit is set to ²1² (set by SIE), it indicates that endpoint 3
has been accessed and a USB interrupt will occur. When the
interrupt has been serviced, this bit should be cleared by software.
4
EP4F
R/W
0
When this bit is set to ²1² (set by SIE), it indicates that endpoint 4
has been accessed and a USB interrupt will occur. When the
interrupt has been serviced, this bit should be cleared by software.
5~7
¾
¾
¾
Undefined bit, read as ²0².
USR (21H) Register
Rev. 1.00
19
August 27, 2007
HT82A834R
There is a system clock control register implemented to select the clock used in the MCU. This register consists of a
USB clock control bit (USBCKEN), a second suspend mode control bit (SUSP2) and a system clock selection bit
(SYSCLK).
The endpoint selection is determined by EPS2, EPS1 and EPS0.
Bit No.
Label
R/W
Reset
Functions
0~2
EPS0~
EPS2
R/W
0
Accessing endpoint FIFO selection, EPS2, EPS1, EPS0:
000: Select endpoint 0 FIFO
001: Select endpoint 1 FIFO
010: Select endpoint 2 FIFO
011: Select endpoint 3 FIFO
100: Select endpoint 4 FIFO
101: reserved for future expansion, cannot be used
110: reserved for future expansion, cannot be used
111: reserved for future expansion, cannot be used
If the selected endpoints do not exist, the related function will be absent.
3
USBCKEN
R/W
0
USB clock control bit. When this bit is set to ²1², it indicates that the USB
clock is enabled. Otherwise, the USB clock is turned-off.
4
SUSP2
R/W
0
This bit is used for reducing power consumption in the suspend mode.
In normal mode, clear this bit to ²0²
In the HALT mode, set this bit to ²1² to reducing power consumption.
5
fSYS16MHz
R/W
0
This bit is used to define if the MCU system clock comes from an external
OSC or comes from the PLL output 16MHz clock.
0: system clock sourced from OSC
1: system clock sourced from the PLL output 16MHz
6
SYSCLK
R/W
0
This bit is used to specify the MCU system clock oscillator frequency.
For a 6MHz crystal oscillator or resonator, set this bit to ²1².
For a 12MHz crystal oscillator or resonator, clear this bit to ²0².
Note: Isochronous endpoint 2 and endpoint 3 are implemented by hardware, so FIFO2 and FIFO3 cannot read/write
via firmware.
UCC (22H) Register
The AWR register contains the current address and a remote wake up function control bit. The initial value of AWR is
²00H². The address value extracted from the the USB command has not to be loaded into this register until the SETUP
stage has finished.
Bit No.
Label
R/W
Power-on
0
WKEN
R/W
0
1~7
AD0~AD6
R/W
0000000
Functions
USB remote-wake-up enable/disable (1/0)
USB device address
AWR (23H) Register
The STALL register shows if the corresponding endpoint works properly or not. As soon as the endpoint works improperly, the related bit in the STALL has to be set to ²1². The STALL register will be cleared by a USB reset signal.
Bit No.
Label
R/W
Power-on
Functions
0~4
STL0~STL4
R/W
00000
Set by the user when related USB endpoints were stalled.
Cleared by a USB reset and a Setup Token event.
5~7
STL5~STL7
¾
000
Undefined bit, read as ²0².
STALL (24H) Register
Rev. 1.00
20
August 27, 2007
HT82A834R
Bit No.
Label
R/W
Power-on
Functions
0
ASET
R/W
0
This bit is used to configure the SIE to automatically change the device
address by the value stored in the AWR register. When this bit is set to
²1² by firmware, the SIE will update the device address by the value
stored in the AWR register after the PC host has successfully read the
data from the device by an IN operation. Otherwise, when this bit is
cleared to ²0², the SIE will update the device address immediately after
an address is written to the AWR register. So, in order to work properly,
the firmware has to clear this bit after a next valid SETUP token is
received.
1
ERR
R/W
0
This bit is used to indicate that some errors have occurred when the
FIFO is accessed. This bit is set by SIE and should be cleared by
firmware. This bit is used for all endpoint.
2
OUT
R/W
0
This bit is used to indicate the OUT token (except the OUT zero length
token) has been received. The firmware clears this bit after the OUT
data has been read. Also, this bit will be cleared by SIE after the next
valid SETUP token is received.
3
IN
R
0
This bit is used to indicate the current USB receiving signal from PC
host is an IN token.
4
NAK
R
0
This bit is used to indicate the SIE is a transmitted NAK signal to the host
in response to the PC host IN or OUT token.
5
CRCF
R/W
0
Error condition failure flag include CRC, PID, no integrate token error,
CRCF will be set by hardware and the CRCF need to be cleared by
firmware.
6
EOT
R
1
Token package active flag, low active.
0
NAK token interrupt mask flag. If this bit set, when the device sent a
NAK token to the host, an interrupt will be disabled. Otherwise if this bit
is cleared, when the device sends a NAK token to the host, it will enter
the interrupt sub-routine.
7
NMI
R/W
SIES (25H) Register
The MISC register combines command and status to control the desired endpoint FIFO action and to show the status of
the desired endpoint FIFO. MISC will be cleared by a USB reset signal.
Bit No.
Label
R/W
Power-on
Functions
0
REQUEST
R/W
0
After setting the status of the desired one, FIFO can be requested by
setting this bit high . After finishing, this bit must be set low.
1
TX
R/W
0
To represent the direction and transition end MCU access. When set to
logic 1, the MCU desires to write data to the FIFO. After finishing, this bit
must be set to logic 0 before terminating request to represent transition
end. For an MCU read operation, this bit must be set to logic 0 and set to
logic 1 after finishing.
2
CLEAR
R/W
0
MCU requests to clear the FIFO, even if the FIFO is not ready. After
clearing the FIFO, the USB interface will send force_tx_err to tell the
Host that data under-run if the Host wants to read data.
3
ISO_IN_EN
R/W
0
Enables the isochronous in pipe interrupt.
4
ISO_OUT_EN
R/W
0
Enables the isochronous out pipe interrupt.
5
SETCMD
R/W
0
To show that the data in the FIFO is a setup command. This bit will
remain in this state until the next one enters the FIFO.
6
READY
R
0
To show that the desired FIFO is ready
7
LEN0
R
0
To show that the host sent a 0-sized packet to the MCU. This bit must be
cleared by a read action to the corresponding FIFO.
MISC (26H) Register
Rev. 1.00
21
August 27, 2007
HT82A834R
Bit No.
Label
R/W
Power-on
Functions
0~1, 6~7
¾
R
0
Undefined bit, read as ²0²
2
SE0
R/W
0
This bit is used to indicate the SIE has detected a SE0 noise in the
USB bus.
This bit is set by SIE and cleared by firmware.
3
SE1
R/W
0
This bit is used to indicate the SIE has detected a SE1 noise in the
USB bus.
This bit is set by SIE and cleared by firmware.
4
USBDN
R
0
USBD- input
5
USBDP
R
0
USBD+ input
USB_STATE (1DH) Register
Bit No.
Label
R/W
Power-on
0
1
Functions
DATATG*
R/W
0
DATA token toggle bit
SETIO1**
R/W
1
Set endpoint1 input or output pipe (1/0), default input pipe(1)
2
SETIO2**
R/W
0
Set endpoint2 input or output pipe (1/0), default output pipe(0)
3
SETIO3**
R/W
1
Set endpoint3 input or output pipe (1/0), default input pipe(1)
4
SETIO4**
R/W
1
Set endpoint4 input or output pipe (1/0), default input pipe(1)
5~7
¾
¾
¾
Undefined bit, read as ²0²
Note: *USB definition: when the host sends a ²set Configuration², the Data pipe should send the DATA0 (about the
Data toggle) first. So, when the Device receives a ²set configuration² setup command, the user needs to toggle
this bit as the following data will send a Data0 first.
**It is only required to set the data pipe as an input pile or output pile. The purpose of this function is to avoid the
host sending a abnormal IN or OUT token and disabling the endpoint.
SETIO (27H) Register, USB Endpoint 1 ~ Endpoint 4 Set IN/OUT Pipe Register
The speaker output volume and speaker mute/un-mute are controlled by the USB Speaker Volume Control register.
The range of the volume is set from 6 dB to -32 dB by software.
Speaker mute control:
MUTEB=0: Mute speaker output (DAC and PA will be mute)
MUTEB=1: Normal
Bit No.
Label
R/W
Power-on
Functions
0~6
USVC0~
USVC6
R/W
0
Volume control Bit0~Bit6
7
MUTE
R/W
0
Mute control, low active.
USB Speaker Volume Control (1CH) Register
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August 27, 2007
HT82A834R
Result (dB)
USVC
Result (dB)
USVC
Result (dB)
USVC
Result (dB)
USVC
6
000_1100
-2
111_1100
-10
110_1100
-24
101_1100
5.5
000_1011
-2.5
111_1011
-10.5
110_1011
-25
101_1011
5
000_1010
-3
111_1010
-11
110_1010
-26
101_1010
4.5
000_1001
-3.5
111_1001
-11.5
110_1001
-27
101_1001
4
000_1000
-4
111_1000
-12
110_1000
-28
101_1000
3.5
000_0111
-4.5
111_0111
-13
110_0111
-29
101_0111
3
000_0110
-5
111_0110
-14
110_0110
-30
101_0110
2.5
000_0101
-5.5
111_0101
-15
110_0101
-31
101_0101
2
000_0100
-6
111_0100
-16
110_0100
-32
101_0100
1.5
000_0011
-6.5
111_0011
-17
110_0011
1
000_0010
-7
111_0010
-18
110_0010
0.5
000_0001
-7.5
111_0001
-19
110_0001
0
000_0000
-8
111_0000
-20
110_0000
-0.5
111_1111
-8.5
110_1111
-21
101_1111
-1
111_1110
-9
110_1110
-22
101_1110
-1.5
111_1101
-9.5
110_1101
-23
101_1101
Speaker Volume Control Table
Label
R/W
Power-on
Functions
FIFO0~
FIFO4
R/W
xxH
EPi accessing register (i = 0~4). When an endpoint is disabled, the corresponding
accessing register should be disabled.
FIFO0~4 (28H~2CH) USB Endpoint Accessing Register Definitions
DAC_Limit_L and DAC_Limit_H are used to define the 16-bit DAC output limit. DAC_Limit_L and DAC_Limit_H are unsigned value. If the 16-bit data from the Host over the range defined by DAC_Limit_L and DAC_Limit_H, the output digital code to DAC will be clamped.
DAC_Limit_L
DAC output limit low byte
DAC_Limit_H
DAC output limit high byte
Example to set the DAC output limit value:
;----------------------------------------------------------; Set DAC Limit Value=FF00H
;----------------------------------------------------------clr
[02DH]
; Set DAC Limit low byte=00H
set
[02EH]
; Set DAC Limit high byte=FFH
;----------------------------------------------------------In order to prevent a popping noise from the speaker output, the power amplifier should output a value of VDD/2 (send
8000H to DAC) during the initial power on state. If the software is set high then clear the bit DAC_WR_TRIG (bit 3 of
DAC_WR register), the value on the DAC_Limit_L and DAC_Limit_H registers will write to the DAC.
Bit No.
Label
R/W
Power-on
Functions
The bit will determine the record source.
REC_MODE=²1²: Record data comes from the
RECORD_IN_H and RECORD_IN_L registers.
REC_MODE=²0²: Record data comes from the PCM
ADC (Default=0)
0
REC_MODE
R/W
0
1~2, 4~7
¾
R
0
Undefined bit, read as ²0².
3
DAC_WR_TRIG
R/W
0
DAC write trigger bit
DAC_WR (2FH) Register
Rev. 1.00
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HT82A834R
Note: REC_MODE=1: Writing to RECORD_IN_L register will only put the written data to an internal lower-order byte
buffer (8-bit) and writing RECORD_IN_H will transfer the RECORD_IN_L and RECORD_IN_H registers content to isochronous in buffer. When record interrupt happened, firmware should write 16-bit 2's complement
value to RECORD_IN_L and RECORD_IN_H registers.
Example to avoid popping noise:
System_Initial:
;----------------------------------------------------------; Avoid Pop Noise
;----------------------------------------------------------mov
a,WDTS
mov
FIFO_TEMP,a
;Save WDTS value
mov
a,00001111b
andm
a,WDTS
mov
a,01010000b
orm
a,WDTS
;Enter DAC Write Data mode, high nibble of WDTS=0101b
clr
[02DH]
;Set DAC data low byte=00H
mov
a,80H
mov
[02EH],a
;Set DAC data high byte=80H
nop
;Write 8000H to DAC
set
[02FH].3
nop
clr
[02FH].3
nop
;----------------------------------------------------------mov
a,FIFO_TEMP
;Restore WDTS value
mov
WDTS,a
;Quit DAC Write Data mode
;----------------------------------------------------------Note: At DAC write data mode (high nibble of WDTS register is 0101b), DAC_Limit_L and DAC_Limit_H registers will
be the 16-bit DAC input data register at falling edge of DAC_WR_TRIG. Otherwise, these two registers are
used to define the 16-bit DAC output limit.
Digital PGA
Bit No.
0~5
Label
Functions
There are six bits to control the digital PGA (0~19.5 dB). The PGA is a digital amplifier
used to amplify the 16-bit data that comes from the PCM ADC
PGA0~PGA5 (REC_MODE(2FH.0=0)=0) or from the RECORD_IN_H and RECORD_IN_L
(REC_MODE(2FH.0)=1). The PGA value versus gain relationship is shown in the follow
table.
6
ADC_RESET= 1: PCM ADC at reset condition
ADC_RESET= 0: PCM ADC during normal operation (default=0)
ADC_RESET The following conditions will reset the ADC:
MCU Reset or USB Reset
Set ADC_RESET to 1
7
MUTE_MKB
Microphone mute Control:
MUTE_MKB= 0: Mute microphone input.
MUTE_MKB= 1: Normal.
PGA_CTRL (30H) Register
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August 27, 2007
HT82A834R
PGA_CRTL Value (PGA5~PGA0)
Gain (dB)
»0
000000
000001
» 0.5
:
:
:
:
100111
» 19.5
101000
» 19.5
:
:
:
:
111111
» 19.5
PFD Control
Label
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PFDC
0
PRES1
PRES0
PFDEN
0
0
PFD_IO
SELW
PFDD
PFDD7
PFDD6
PFDD5
PFDD4
PFDD3
PFDD2
PFDD1
PFDD0
The PFD (programmable frequency divider) is implemented in the HT82A834R. It is composed of two portions: a
prescaler and a general counter.
The prescaler is controlled by the register bits, PRES0 and PRES1. The 4-stage prescaler is divided by 16. The general
counter is programmed by an 8-bit register PFDD.
The PFDD is inhibited to write while the PFD is disabled. To modify the PFDD contents, the PFD must be enabled.
When the generator is disabled, the PFDD is cleared by hardware.
PFD prescaler selection:
PRES1
PRES0
0
0
PFD frequency source ¸ 1
Prescaler Output
0
1
PFD frequency source ¸ 2
1
0
PFD frequency source ¸ 4
1
1
PFD frequency source ¸ 8
The bit PFD_IO is used to determine whether PC0 is a general purpose I/O port or a PFD output.
Label
Functions
PFD_IO=1
²PC0² is PFD output
PFD_IO=0
²PC0² is a general purpose IO Port (Default =0)
The SELW bit is used to control the power amplifier input source. The software should set SELW= ²1² when the power
amplifier signal come from MUSIC_IN, otherwise the speaker output will come from USB Audio data.
Label
Functions
SELW=1
Power amplifier signal is sourced from MUSIC_IN pin
SELW=0
Power amplifier signal is sourced from USB Audio data (default =0)
fS
Y S
/4
4 - S ta g e P r e s c a le r
(1 /1 6 )
P F D
F re q u e n c y
P r e s c a le r
P r e s c a le r
O u tp u t
P F D E N
P R E S 1 , P R E S 0
N o te : P F D
Rev. 1.00
O u tp u t F re q u e n c y =
P r e s c a le r O u tp u t
2 ´ (N + 1 )
P F D D
P F D
O u tp u t
, w h e re N
25
= th e v a lu e o f th e P F D
d a ta
August 27, 2007
HT82A834R
SPI
The serial interface function similar to SPI (Motorola), where four basic signals are included. They are SDI (Serial Data
Input), SDO (Serial Data Output), SCK (serial clock) and SCS (slave select pin).
S C S
S C K
S D I
S D O
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SPI Timing
Label
SBCR
Default
SBDR
Default
Functions
D7
D6
D5
D4
D3
D2
D1
D0
Serial Bus
Control Register
CKS
M1
M0
SBEN
MLS
CSEN
WCOL
TRF
Serial Bus
Data Register
0
1
1
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
U
U
U
U
U
U
U
U
Note: ²U² unchanged
Two registers (SBCR & SBDR) unique to the serial interface provide control, status and data storage.
· SBCR: Serial bus control register
¨
¨
Bit7 (CKS): clock source selection: fSIO=fSYS/2, select as 0; fSIO=fSYS, select as 1
Bit6 (M1), Bit5 (M0): master/slave mode and baud rate selection
-
¨
M1, M0=
00: Master mode, baud rate = fSIO
01: Master mode, baud rate = fSIO/4
10: Master mode, baud rate = fSIO/16
11: Slave mode
Bit4 (SBEN): Serial bus enable/disable (1/0)
-
Enable: (SCS dependent on CSEN bit)
Disable ® enable: SCK, SDI, SDO, SCS =0 (SCK=²0²) and wait to write data to SBDR (TXRX buffer)
Master mode: write data to SBDR (TXRX buffer) ® start transmission/reception automatically
Master mode: when data has been transferred ® set TRF
Slave mode: when a SCK (and SCS dependent on CSEN) is received, data in TXRX buffer is shifted-out and
data on SDI is shifted-in.
-
Disable: SCK (SCK), SDI, SDO, SCS floating and related pins are IO ports.
Label
Functions
SBEN=1
PC4~PC7 are SPI function pins (pin SCS will go low if CSEN=1).
SBEN=0
PC4~PC7 are general purpose I/O Port pins (Default)
Note: 1. If SBEN=²1², the pull-high resistors on PC4~PC7 will be disabled. When this happens the user should
add external pull-high resistors to the SPI related pins if necessary (EX: pin SCS).
2. If CSEN=²0², the SCS pin will enter a floating state.
¨
Bit3 (MLS): MSB or LSB (1/0) shift first control bit
¨
Bit2 (CSEN): serial bus selection signal enable/disable (SCS), when CSEN=0, SCS is floating
¨
Bit1 (WCOL): this bit is set to 1 if data is written to SBDR (TXRX buffer) when a data is transferring
-
¨
writing will be ignored if data is written to SBDR (TXRX buffer) when a data is transferring
WCOL will be set by hardware and clear by software.
Bit 0 (TRF): data transferred or data received ® used to generate interrupt
Note: data receiving is still working when MCU enters HALT mode
Rev. 1.00
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HT82A834R
· SBDR: Serial bus data register
Data written to SBDR ® write data to TXRX buffer only
Data read from SBDR ® read from SBDR only
¨
Operating Mode description:
Master transmitter: clock sending and data I/O started by writing SBDR
Master clock sending started by writing SBDR
Slave transmitter: data I/O started by clock received
Slave receiver: data I/O started by clock received
· Clock polarity = rising (CLK) or falling (CLK): 1 or 0 (software option)
Operation of Serial Interface:
Label
Functions
· Select CKS and select M1,M0 = 00, 01, 10
· Select CSEN, MLS (same as slave)
· Set SBEN
· Writing data to SBDR ® data is stored in TXRX buffer ® output CLK (and SCS) signals ® go to
Master
·
·
·
·
·
step 5 ® (SIO internal operation ® data stored in TXRX buffer, and SDI data is shifted into
TXRX buffer ® data transferred, data in TXRX buffer is latched into SBDR)
Check WCOL; WCOL = 1 ® clear WCOL and go to step 4; WCOL = 0 ® go to step 6
Check TRF or waiting for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
· CKS don¢t care and select M1, M0 = 11
· Select CSEN, MLS (same as master)
· Set SBEN
· Writing data to SBDR ® data is store in TXRX buffer ® waiting for master clock signal (and
Slave
·
·
·
·
·
SCS): CLK ® go to step 5 ® (SIO internal operations ® CLK (SCS) received ® output data in
TXRX buffer and SDI data is shifted into TXRX buffer ® data transferred, data in TXRX buffer is
latched into SBDR)
Check WCOL; WCOL = 1 ® clear WCOL, go to step 4; WCOL = 0 ® go to step 6
Check TRF or waiting for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
· WCOL: master/slave mode, set if writing to SBDR when data is transferring (transmitting or receiving) and this writing
will be ignored. WCOL function can be enabled/disabled by software option (SIO_WCOL bit of MODE_CTRL register). WCOL is set by SIO and cleared by users.
Data transmission and reception are still workable when MCU enters HALT mode.
CPOL is used to select the clock polarity of CLK. It is a software option (SIO_CPOL bit of MODE_CTRL register).
· MLS: MSB or LSB first selection
· CSEN: chip select function enable/disable, CSEN = 1 ® SCS signal function is active. Master should output SCS sig-
nal before CLK signal is setting and slave data transferring should be disabled(enabled) before(after) SCS signal received. CSEN = 0, SCS signal is not needed, SCS pin (master and slave) should be floating.
· CSEN: CSEN software option (SIO_CSEN bit of MODE_CTRL register) is used to enable/disable software CSEN
function. If CSEN software option is disable, software CSEN always disabled. If CSEN software option is enabled,
software CSEN function can be used.
· SBEN = 1 ® serial bus standby; SCS (CSEN = 1) = 1; SCS = floating (CSEN = 0); SDI = floating; SDO = 1; master
CLK = output 1/0 (dependent on CPOL software option), slave CLK = floating
· SBEN = 0 ® serial bus disable; SCS = SDI = SDO = CLK = floating
· TRF is set by SIO and cleared by users. When data transferring (transmission and reception) is complete, TRF is set
to generate SBI (serial bus interrupt).
Rev. 1.00
27
August 27, 2007
HT82A834R
S B E N = 1 , C S E N = 1 a n d w r ite d a ta to S B D R
( if p u ll- h ig h e d )
S C S
C L K
S D I
S D O
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
C L K
SIO Timing
Label
SBCR
Default
SBDR
Functions
D7
D6
D5
D4
D3
D2
D1
D0
Serial Bus
Control Register
CKS
M1
M0
SBEN
MLS
CSEN
WCOL
TRF
0
1
1
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
U
U
U
U
U
U
U
U
Serial Bus
Data Register
Default
D a ta B u s
S B D R
D 7
( R e c e iv e d D a ta R e g is te r )
D 6
D 5
D 4
D 3
D 2
D 1
D 0
M
U
S D O
X
M L S
A n d , S ta rt
E N
S C K
M
U
X
C 0
A n d , S ta rt
C 1
U
X
S D I
T R F
C 2
A N D
C lo c k
P o la r ity
M a s te r o r
S la v e
S B E N
S D O
S B E N
M
In te rn a l B a u d
R a te C lo c k
B u ffe r
W C O L F la g
In te r n a l B u s y F la g
W r ite S B D R
S B E N
W r ite S B D R E n a b le /D is a b le
W r ite S B D R
A n d , S ta rt
S C S
E N
M a s te r o r S la v e
S B E N
C S E N
Block Diagram of SIO
Rev. 1.00
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August 27, 2007
HT82A834R
Label
Functions
WCOL
set by SIO cleared by users
CESN
Enable or disable chip selection function pin
Master mode: 1/0=with/without SCS output control
Slave mode: 1/0= with/without SCS input control
SBEN
Enable or disable serial bus (0= initialize all status flags)
When SBEN=0, all status flags should be initialized
When SBEN=0, all SIO related function pins should stay at floating state
TRF
1= data transmitted or received
0= data is transmitting or still not received
If clock polarity set to rising edge (SIO_CPOL=1), serial clock timing follow CLK, otherwise (SIO_CPOL=0) CLK is the
serial clock timing.
Mode Control
The MODE_CTRL register is used to control DAC and ADC operation mode and SPI function.
Bit No.
Label
0
DA_L_ENB
DAC enable/disable control (left channel)
1= DAC Left Channel disable
0= DAC Left Channel enable (default)
1
DA_R_ENB
DAC enable/disable control (right channel)
1= DAC Right Channel disable
0= DAC Right Channel enable (default)
2
AD_ENB
3
Functions
ADC enable/disable control
1= ADC power down
0= ADC power on (default)
DAC play mode control
PLAY_MODE 1= 8kHz/16-bit
0= 48kHz/16-bit (default)
4
SIO_CPOL
There are three bits used to control the mode of SPI operation.
1= clock polarity rising edge
0= clock polarity falling edge (default)
5
SIO_WCOL
1= WCOL bit of SBCR register enable
0= WCOL bit of SBCR register disable (default)
6
SIO_CSEN
1= CSEN bit of SBCR register enable
0= CSEN bit of SBCR register disable (default)
7
Record_Freq
1= Record frequency is 16kHz
0= Record frequency is 8 kHz (default)
MODE_CTRL (34H) Register
SPI Usage Example
SPI_Test:
clr
UCC.@UCC_SYSCLK
set
SIO_CSEN
clr
SIO_CPOL
;Master Mode, SCLK=fSIO
clr
M1
clr
M0
;-------------clr
CKS
clr
TRF
clr
TRF_INT
set
MLS
set
CSEN
set
SBEN
Rev. 1.00
;12MHz SYSCLK
;SPI Chip Select Function Enable
;falling edge change data
;fSIO=fsys/2
;clear TRF flag
;clear Interrupt SPI flag
;MSB shift first
;Chip Select Enable
;SPI Enable, SCS will go low
29
August 27, 2007
HT82A834R
if POLLING_MODE
clr
ESII
;SPI Interrupt Disable
;WRITE INTO "WRITE ENABLE" INSTRUCTION
MOV
A,OP_WREN
MOV
SBDR,A
$0:
snz
TRF
jmp
$0
clr
TRF
else
set
ESII
;SPI Interrupt Enable
;WRITE INTO "WRITE ENABLE" INSTRUCTION
MOV
A,OP_WREN
MOV
SBDR,A
$0:
snz
TRF_INT
;set at SPI Interrupt
jmp
$0
clr
TRF_INT
endif
Play/Record Data
The play/record interrupt will be activated when play/record data is valid on PLAY_DATA/ RECORD_DATA registers.
The PLAY_DATA/RECORD_DATA registers will latch data until next interrupt happen. The PLAY_DATA is unsigned
value (0~FFFFH). RECORD_DATA is 2¢s complement value (8000H~7FFFH).
The update rate of RECORD_DATA is 8kHz (Record_Freq=0) or 16kHz (Record_Freq=1). The update rate of
PLAY_DATA is 48KHz (PLAY_MODE=0) or 8KHz (PLAY_MODE=1). All these registers (3AH~3FH) are read only.
Address
Label
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PL_D6
PL_D5
PL_D4
PL_D3
3AH
PLAY_DATAL_L
PL_D7
PL_D2
PL_D1
PL_D0
3BH
PLAY_DATAL_H
PL_D15 PL_D14 PL_D13 PL_D12 PL_D11 PL_D10
PL_D9
PL_D8
3CH
PLAY_DATAR_L
PR_D7
PR_D2
PR_D1
PR_D0
3DH
PLAY_DATAR_H
PR_D15 PR_D14 PR_D13 PR_D12 PR_D11 PR_D10
PR_D9
PR_D8
3EH
RECORD_DATA_L
R_D7
R_D6
R_D5
R_D4
R_D3
R_D2
R_D1
R_D0
3FH
RECORD_DATA_H
R_D15
R_D14
R_D13
R_D12
R_D11
R_D10
R_D9
R_D8
PR_D6
PR_D5
PR_D4
PR_D3
Configuration Options
The following table shows all of the configuration options in the microcontroller. All of the OTP options must be defined
to ensure proper system functioning.
No.
Option
1
PA0~PA7 pull-high resistor enabled or disabled (by bit)
2
LVR enable or disable
3
WDT enable or disable
4
WDT clock source: fSYS/4 or WDTOSC
5
CLRWDT instruction(s): 1 or 2
6
PA0~PA7 wake-up enabled or disabled (by bit)
7
PB0~PB7 pull-high resistor enabled or disabled (by bit)
8
PC0~PC7 pull-high resistor enabled or disabled (by nibble)
9
TBHP enable or disable (default disable)
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Application Circuits
U S B
V
C O N
1
D D
V D D
V D D
J P 5
2
0 .1 m F
U S B +
3
U S B -
1 .5 k W
3 3 W
4
V S S
V
V S S
1
3 3 W
B e a d
U S B D N
4 7 p F
2
V 3 3 O
0 .1 m F
4 7 p F
1 0 m F
L O U T
1 0 0 m F
R O U T
S p e a k e r
A V S S 2
D D
1
V
3 3 0 W
D D
2
1 0 m F
0 .1 m F
B e a d F e r r ite
B e a d F e r r ite
1
2
1 0 m F
V
D D
V
1 0 m F
D D
1
2
0 .1 m F
A V S S 3
1 0 0 k W
1 0 m F
3 .3 k W
V A G
1 0 k W
0 .1 m F
3 0 0 p F
T I+
P A 2
2
P A 1
3
P A 0
4
A V D D 2
5
R O U T
6
L O U T
7
A V S S 2
8
9
B IA S
1 0
1 1
1 0 m F
2
F e r r ite
B e a d
1
M U S IC _ IN
1 m F
1
A V D D 3
1 k W
A V S S 3
P A 3
A V S S 1
B e a d F e r r ite
1
2
0 .1 m F
5
4
7
A V D D 1
1 2
A V D D 3
1 3
V A G R e f
1 4
V A G
1 5
T I+
1 6
T I-
1 7
T G
1 8
A V S S 3
1 9
P B 7
2 0
P B 6
2 1
P B 5
2 2
P B 4
2 3
D V S S 2
2 4
P A 4
P A 2
P A 5
P A 1
P A 6
P A 0
P A 7
A V D D 2
D V S S 1
R O U T
V 3 3 O
L O U T
U S B D P
A V S S 2
U S B D N
A V S S 1
D V D D 1
B IA S
R E S E T
M U S IC _ IN
H E A D E R
S C S
M IS O
M O S I
S C K
4 5
P A 7
4 4
D V S S 1
4 3
V 3 3 O
4 2
U S B D P
4 1
U S B D N
4 0
D V D D
O S C I 3 7
3 6
P C 0
3 5
P C 1
V A G
P C 2 /T M R 1
P C 3
T I-
P C 4 /S D O
3 4
P C 2
3 3
P C 3
3 2
P C 4
P C 5 /S D I 3 1
P C 6 /S C S 3 0
P C 7 /S C K 2 9
P C 5
P B 6
P B 0
P B 5
P B 1
P B 4
P B 2
D V S S 2
P B 3
H T 8 2 A 8 3 4 R
T I-
P A 6
O S C I
T I+
A V S S 3
P A 5
4 6
R E S E T
P C 1 /T M R 0
P B 7
4 7
O S C O
V A G R e f
3 0 0 p F
V
P C 6
P C 7
2 8
P B 0
2 7
P B 1
2 6
P B 2
2 5
P B 3
D D
1 k W
B u z z e r
0 .1 m F
V
D D
1 0 W
0 .1 m F
0 .1 m F
1 0 0 k W
Y 1
D V D D
0 .1 m F
1 2 M H z
P A 7
P A 6
P A 5
P A 4
P B 0
P B 1
P B 2
P B 3
P B 4
A V S S 3
1 0 0 p F
P A 4
3 8
P C 0 /B Z
T G
4 8
M U S IC _ IN
1 M W
2
4 7 W
3 9
O S C O
A V D D 1
A V D D 3
1 0 0 k W
1 0 k W
6
P A 3
0 .1 m F
M ic r o p h o n e
S P I L C D
P C
P C
P C
P C
P C 0
1
P C 0
1 0 0 m F
V
5 0 k W
U S B D P
2
D D
S 1 1
S 2 1
S 1 3
S 1 4
S 2 1
S 2 2
S 2 3
S 2 4
S 3 1
S 3 2
S 3 3
S 3 4
S 4 1
S 4 2
S 4 3
S 4 4
S 5 1
S 5 2
S 5 3
S 5 4
S 6 1
S 6 2
S 6 3
S 6 4
P B 5
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Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
Central to the successful operation of any
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.00
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC). If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine
will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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HT82A834R
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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HT82A834R
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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HT82A834R
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
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SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
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HT82A834R
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.00
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HT82A834R
Package Information
48-pin SSOP (300mil) Outline Dimensions
4 8
2 5
A
B
2 4
1
C
C '
G
H
D
Symbol
Rev. 1.00
a
F
E
Dimensions in mil
Min.
Nom.
Max.
A
395
¾
420
B
291
¾
299
C
8
¾
12
C¢
613
¾
637
D
85
¾
99
E
¾
25
¾
F
4
¾
10
G
25
¾
35
H
4
¾
12
a
0°
¾
8°
45
August 27, 2007
HT82A834R
48-pin LQFP (7´7) Outline Dimensions
C
H
D
3 6
G
2 5
I
3 7
2 4
F
A
B
E
4 8
1 3
K
a
J
1
Symbol
Rev. 1.00
1 2
Dimensions in mm
Min.
Nom.
Max.
A
8.9
¾
9.1
B
6.9
¾
7.1
C
8.9
¾
9.1
D
6.9
¾
7.1
E
¾
0.5
¾
F
¾
0.2
¾
G
1.35
¾
1.45
H
¾
¾
1.6
I
¾
0.1
¾
J
0.45
¾
0.75
K
0.1
¾
0.2
a
0°
¾
7°
46
August 27, 2007
HT82A834R
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SSOP 48W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1
B
Reel Inner Diameter
100±0.1
C
Spindle Hole Diameter
13+0.5
-0.2
D
Key Slit Width
2±0.5
T1
Space Between Flange
32.2+0.3
-0.2
T2
Reel Thickness
38.2±0.2
Rev. 1.00
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August 27, 2007
HT82A834R
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
D 1
C
B 0
K 1
P
K 2
A 0
SSOP 48W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
32±0.3
P
Cavity Pitch
16±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
14.2±0.1
D
Perforation Diameter
2 Min.
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4±0.1
P1
Cavity to Perforation (Length Direction)
2±0.1
A0
Cavity Length
12±0.1
B0
Cavity Width
16.2±0.1
K1
Cavity Depth
2.4±0.1
K2
Cavity Depth
3.2±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
Rev. 1.00
0.35±0.05
25.5
48
August 27, 2007
HT82A834R
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (China) Inc. (Dongguan Sales Office)
Building No. 10, Xinzhu Court, (No. 1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2007 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
49
August 27, 2007
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