Data Sheet

PBSS5440D
40 V PNP low VCEsat (BISS) transistor
Rev. 02 — 14 December 2009
Product data sheet
1. Product profile
1.1 General description
PNP low VCEsat Breakthrough in Small Signal (BISS) single bipolar PNP transistor in a
SOT457 (SC-74) SMD plastic package.
NPN complement: PBSS4440D.
1.2 Features
„
„
„
„
„
Ultra low collector-emitter saturation voltage VCEsat
4 A continuous collector current capability IC (DC)
Up to 15 A peak current
Very low collector-emitter saturation resistance
High efficiency due to less heat generation
1.3 Applications
„
„
„
„
„
„
Power management functions
Charging circuits
DC-to-DC conversion
MOSFET gate driving
Power switches (e.g. motors, fans)
Thin Film Transistor (TFT) backlight inverter
1.4 Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
VCEO
collector-emitter voltage
open base
[1]
IC
collector current (DC)
ICM
peak collector current
t = 1 ms or limited by
Tj(max)
RCEsat
collector-emitter saturation
resistance
IC = −6 A;
IB = −600 mA
[2]
Min
Typ
Max
Unit
-
-
−40
V
-
-
−4
A
-
-
−15
A
-
55
75
mΩ
[1]
Device mounted on a ceramic Printed-Circuit Board (PCB), AL2O3, standard footprint.
[2]
Pulse test: tp ≤ 300 μs; δ ≤ 0.02.
PBSS5440D
NXP Semiconductors
40 V PNP low VCEsat (BISS) transistor
2. Pinning information
Table 2.
Pinning
Pin
Description
1
collector
2
collector
3
base
4
emitter
5
collector
6
collector
Simplified outline
6
5
Symbol
4
1, 2, 5, 6
3
1
2
3
4
sym030
3. Ordering information
Table 3.
Ordering information
Type number
PBSS5440D
Package
Name
Description
Version
SC-74
plastic surface mounted package; 6 leads
SOT457
4. Marking
Table 4.
Marking codes
Type number
Marking code
PBSS5440D
71
5. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VCBO
collector-base voltage
VCEO
collector-emitter voltage
open emitter
-
−40
V
open base
-
−40
V
VEBO
emitter-base voltage
open collector
-
−5
V
-
−4
A
-
−15
A
-
−0.8
A
[1]
IC
collector current (DC)
ICM
peak collector current
IB
base current (DC)
IBM
peak base current
tp ≤ 300 μs
total power dissipation
Tamb ≤ 25 °C
Ptot
t = 1 ms or limited
by Tj(max)
PBSS5440D_2
Product data sheet
-
−2
A
[2]
-
360
mW
[3]
-
600
mW
[4]
-
750
mW
[1]
-
1.1
W
[2][5]
-
2.5
W
© NXP B.V. 2010. All rights reserved.
Rev. 02 — 14 December 2009
2 of 13
PBSS5440D
NXP Semiconductors
40 V PNP low VCEsat (BISS) transistor
Table 5.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Tstg
Conditions
Min
Max
Unit
storage temperature
−65
+150
°C
Tj
junction temperature
-
150
°C
Tamb
ambient temperature
−65
+150
°C
[1]
Device mounted on a ceramic PCB, AL2O3, standard footprint.
[2]
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[3]
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2.
[4]
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 6 cm2.
[5]
Operated under pulsed conditions: Duty cycle δ ≤ 10% and pulse width tp ≤ 10 ms.
006aaa270
1600
Ptot
(mW)
1200
800
(1)
(2)
(3)
400
0
−75
(4)
−25
25
75
125
175
Tamb (°C)
(1) Ceramic PCB, AL2O3, standard footprint
(2) FR4 PCB, mounting pad for collector 6 cm2
(3) FR4 PCB, mounting pad for collector 1 cm2
(4) FR4 PCB, standard footprint
Fig 1.
Power derating curves
PBSS5440D_2
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 02 — 14 December 2009
3 of 13
PBSS5440D
NXP Semiconductors
40 V PNP low VCEsat (BISS) transistor
6. Thermal characteristics
Table 6.
Thermal characteristics
Symbol
Parameter
Conditions
thermal resistance from
junction to ambient
Rth(j-a)
in free air
thermal resistance from
junction to solder point
Rth(j-sp)
Min
Typ
Max
Unit
[1]
-
-
350
K/W
[2]
-
-
208
K/W
[3]
-
-
160
K/W
[4]
-
-
113
K/W
[1][5]
-
-
50
K/W
-
-
45
K/W
[1]
Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2]
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2.
[3]
Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 6 cm2.
[4]
Device mounted on a ceramic PCB, AL2O3, standard footprint.
[5]
Operated under pulsed conditions: Duty cycle δ ≤ 10% and pulse width tp ≤ 10 ms.
006aaa271
103
Zth(j-a)
(K/W)
102
duty cycle =
1
0.75
0.5
0.33
0.2
0.1
0.05
10
0.02
0.01
1
0
10−1
10−5
10−4
10−3
10−2
10−1
1
10
102
103
tp (s)
FR4 PCB, standard footprint
Fig 2.
Transient thermal impedance from junction to ambient as a function of pulse time; typical values
PBSS5440D_2
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 02 — 14 December 2009
4 of 13
PBSS5440D
NXP Semiconductors
40 V PNP low VCEsat (BISS) transistor
006aaa272
103
Zth(j-a)
(K/W)
102
duty cycle =
1
0.75
0.5
0.33
0.2
0.1
10
0.05
0.02
0.01
1
0
10−1
10−5
10−4
10−3
10−2
10−1
1
10
102
103
tp (s)
FR4 PCB, mounting pad for collector 1 cm2
Fig 3.
Transient thermal impedance from junction to ambient as a function of pulse time; typical values
006aaa273
103
Zth(j-a)
(K/W)
102
duty cycle =
1
0.75
0.5
0.33
0.2
0.1
10
0.05
0.02
0.01
1
0
10−1
10−5
10−4
10−3
10−2
10−1
1
10
102
103
tp (s)
FR4 PCB, mounting pad for collector 6 cm2
Fig 4.
Transient thermal impedance from junction to ambient as a function of pulse time; typical values
PBSS5440D_2
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 02 — 14 December 2009
5 of 13
PBSS5440D
NXP Semiconductors
40 V PNP low VCEsat (BISS) transistor
7. Characteristics
Table 7.
Characteristics
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
ICBO
collector-base cut-off
current
Conditions
Min
Typ
Max
Unit
VCB = −30 V; IE = 0 A
-
-
−0.1
μA
VCB = −30 V; IE = 0 A; Tj = 150 °C
-
-
−50
μA
ICES
collector-emitter
cut-off current
VCE = −30 V; VBE = 0 V
-
-
−0.1
μA
IEBO
emitter-base cut-off
current
VEB = −5 V; IC = 0 A
-
-
−0.1
μA
hFE
DC current gain
VCE = −2 V; IC = −0.5 A
VCEsat
collector-emitter
saturation voltage
200
-
-
VCE = −2 V; IC = −1 A
[1]
200
-
-
VCE = −2 V; IC = −2 A
[1]
175
-
-
VCE = −2 V; IC = −4 A
[1]
80
-
-
VCE = −2 V; IC = −6 A
[1]
30
-
-
IC = −0.5 A; IB = −50 mA
-
−46
−60
mV
IC = −1 A; IB = −50 mA
-
−70
−110
mV
IC = −2 A; IB = −200 mA
-
−120
−180
mV
IC = −4 A; IB = −400 mA
[1]
-
−220
−300
mV
IC = −6 A; IB = −600 mA
[1]
-
−320
−450
mV
[1]
-
55
75
mΩ
-
−0.8
−0.85
V
RCEsat
collector-emitter
saturation resistance
IC = −6 A; IB = −600 mA
VBEsat
base-emitter
saturation voltage
IC = −0.5 A; IB = −50 mA
IC = −1 A; IB = −50 mA
-
−0.84
−0.9
V
IC = −1 A; IB = −100 mA
[1]
-
−0.84
−1
V
IC = −4 A; IB = −400 mA
[1]
-
−1.0
−1.1
V
VBEon
base-emitter turn-on
voltage
VCE = −2 V; IC = −2 A
-
−0.8
−1.0
V
VCC = −10 V; IC = −2 A;
IBon = −0.1 A; IBoff = 0.1 A
-
12
-
ns
-
43
-
ns
td
delay time
tr
rise time
ton
turn-on time
-
55
-
ns
ts
storage time
-
240
-
ns
tf
fall time
-
80
-
ns
toff
turn-off time
-
320
-
ns
fT
transition frequency
VCE = −10 V; IC = −0.1 A;
f = 100 MHz
-
110
-
MHz
Cc
collector capacitance
VCB = −10 V; IE = ie = 0 A;
f = 1 MHz
-
50
-
pF
[1]
Pulse test: tp ≤ 300 μs; δ ≤ 0.02.
PBSS5440D_2
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 02 — 14 December 2009
6 of 13
PBSS5440D
NXP Semiconductors
40 V PNP low VCEsat (BISS) transistor
006aaa282
600
VBE
(V)
(1)
hFE
006aaa283
−1.6
−1.2
400
(2)
−0.8
(3)
200
−0.4
0
−10−1
−1
−10
−102
−103
0
−10−1
−104
−105
IC (mA)
VCE = −2 V
−1
−10
−102
−103
−104
−105
IC (mA)
VCE = −2 V
(1) Tamb = 100 °C
Tamb = 25 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig 5.
DC current gain as a function of collector
current; typical values
Fig 6.
006aaa284
−1
VCEsat
(V)
Base-emitter voltage as a function of collector
current; typical values
006aaa285
−1
VCEsat
(V)
(1)
−10−1
−10−1
(2)
(3)
(1)
(2)
−10−2
−10−2
−10−3
−10−1
−1
−10
−102
−103
−104
IC (mA)
(3)
−10−3
−10−1
−1
(1) IC/IB = 100
(2) Tamb = 25 °C
(2) IC/IB = 50
(3) Tamb = −55 °C
−103
−104
−105
IC (mA)
(3) IC/IB = 10
Collector-emitter saturation voltage as a
function of collector current; typical values
Fig 8.
Collector-emitter saturation voltage as a
function of collector current; typical values
PBSS5440D_2
Product data sheet
−102
Tamb = 25 °C
IC/IB = 20
(1) Tamb = 100 °C
Fig 7.
−10
© NXP B.V. 2010. All rights reserved.
Rev. 02 — 14 December 2009
7 of 13
PBSS5440D
NXP Semiconductors
40 V PNP low VCEsat (BISS) transistor
006aaa287
−1.3
006aaa327
103
RCEsat
(Ω)
VBEsat
(V)
102
(1)
−0.9
(1)
(2)
10
(3)
(2)
1
(3)
−0.5
10−1
−0.1
−10−1
−1
−10
−102
−103
−104
−105
IC (mA)
10−2
−10−1
−1
−102
−103
−104
IC (A)
Tamb = 25 °C
IC/IB = 20
(1) Tamb = −55 °C
(1) IC/IB = 100
(2) Tamb = 25 °C
(2) IC/IB = 50
(3) Tamb = 100 °C
(3) IC/IB = 10
Fig 9.
−10
Base-emitter saturation voltage as a function
of collector current; typical values
006aaa288
−12
−8
006aaa289
102
RCEsat
(Ω)
IB (mA) = −400
−360
−320
−280
−240
−200
−160
−120
−80
IC
(A)
Fig 10. Collector-emitter saturation resistance as a
function of collector current; typical values
10
1
−40
−4
(1)
(2)
10−1
0
0
−0.4
−0.8
−1.2
−1.6
−2.0
VCE (V)
Tamb = 25 °C
(3)
10−2
−10−1
−1
−10
−102
−103
−104
IC (mA)
IC/IB = 20
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Fig 11. Collector current as a function of
collector-emitter voltage; typical values
Fig 12. Collector-emitter saturation resistance as a
function of collector current; typical values
PBSS5440D_2
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 02 — 14 December 2009
8 of 13
PBSS5440D
NXP Semiconductors
40 V PNP low VCEsat (BISS) transistor
8. Test information
− IB
input pulse
(idealized waveform)
90 %
− I Bon (100 %)
10 %
− I Boff
output pulse
(idealized waveform)
− IC
90 %
− I C (100 %)
10 %
t
td
ts
tr
t on
tf
t off
006aaa266
Fig 13. BISS transistor switching time definition
VBB
RB
VCC
RC
Vo
(probe)
oscilloscope
450 Ω
(probe)
450 Ω
oscilloscope
R2
VI
DUT
R1
mgd624
(1) VCC = −10 V; IC = −2 A; IBon = −0.1 A; IBoff = 0.1 A
Fig 14. Test circuit for switching times
PBSS5440D_2
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 02 — 14 December 2009
9 of 13
PBSS5440D
NXP Semiconductors
40 V PNP low VCEsat (BISS) transistor
9. Package outline
3.1
2.7
6
3.0
2.5
1.7
1.3
1.1
0.9
5
4
2
3
0.6
0.2
pin 1 index
1
0.26
0.10
0.40
0.25
0.95
1.9
Dimensions in mm
04-11-08
Fig 15. Package outline SOT457 (SC-74)
10. Packing information
Table 8.
Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.[1]
Type number
Package
Description
Packing quantity
3000
PBSS5440D
SOT457
10000
4 mm pitch, 8 mm tape and reel; T1
-115
-
-135
4 mm pitch, 8 mm tape and reel; T2
[3]
-125
-
-165
[1]
For further information and the availability of packing methods, see Section 13.
[2]
T1: normal taping
[3]
T2: reverse taping
PBSS5440D_2
Product data sheet
5000
[2]
© NXP B.V. 2010. All rights reserved.
Rev. 02 — 14 December 2009
10 of 13
PBSS5440D
NXP Semiconductors
40 V PNP low VCEsat (BISS) transistor
11. Revision history
Table 9.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PBSS5440D_2
20091214
Product data sheet
-
PBSS5440D_1
Modifications:
PBSS5440D_1
•
This data sheet was changed to reflect the new company name NXP Semiconductors,
including new legal definitions and disclaimers. No changes were made to the technical
content.
•
Figure 2 “Transient thermal impedance from junction to ambient as a function of pulse time;
typical values”: updated
•
Figure 3 “Transient thermal impedance from junction to ambient as a function of pulse time;
typical values”: updated
•
Figure 4 “Transient thermal impedance from junction to ambient as a function of pulse time;
typical values”: updated
•
•
Figure 6 “Base-emitter voltage as a function of collector current; typical values”: updated
Figure 11 “Collector current as a function of collector-emitter voltage; typical values”:
updated
20050427
Product data sheet
-
PBSS5440D_2
Product data sheet
-
© NXP B.V. 2010. All rights reserved.
Rev. 02 — 14 December 2009
11 of 13
PBSS5440D
NXP Semiconductors
40 V PNP low VCEsat (BISS) transistor
12. Legal information
12.1 Data sheet status
Document status[1][2]
Product status[3]
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
Definition
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
12.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
12.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PBSS5440D_2
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 02 — 14 December 2009
12 of 13
PBSS5440D
NXP Semiconductors
40 V PNP low VCEsat (BISS) transistor
14. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
10
11
12
12.1
12.2
12.3
12.4
13
14
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Thermal characteristics . . . . . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test information . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Packing information . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 14 December 2009
Document identifier: PBSS5440D_2