CrossLink sysI/O Usage Guide

CrossLink sysI/O Usage Guide
Preliminary Technical Note
TN1305 Version 1.0
May 2016
CrossLink sysI/O Usage Guide
Preliminary Technical Note
Contents
Acronyms in This Document .................................................................................................................................................4
1. Introduction ..................................................................................................................................................................5
2. sysI/O Buffer Overview .................................................................................................................................................5
3. Supported sysI/O Standards .........................................................................................................................................5
4. sysI/O Banking Scheme .................................................................................................................................................6
4.1.
VCC (1.2 V) ............................................................................................................................................................6
4.2.
VCCIO (1.2 V/1.8 V/2.5 V/3.3 V) .............................................................................................................................6
4.3.
VCCAUX25VPP (2.5 V) ........................................................................................................................................6
4.4.
D-PHY External Power Supplies (1.2 V) ...............................................................................................................7
5. sysI/O Buffer Configurations .........................................................................................................................................8
5.1.
Programmable PULLMODE Settings ....................................................................................................................8
5.2.
Output Drive Strength .........................................................................................................................................8
5.3.
Open-Drain Control .............................................................................................................................................8
5.4.
Differential I/O Support.......................................................................................................................................8
5.5.
Complementary Outputs .....................................................................................................................................8
5.6.
On-Chip Termination ...........................................................................................................................................9
5.7.
Programmable Input Delay .................................................................................................................................9
5.8.
Standby................................................................................................................................................................9
5.9.
MIPI D-PHY Support ............................................................................................................................................9
6. Software sysI/O Attributes .........................................................................................................................................11
6.1.
IO_TYPE .............................................................................................................................................................11
6.2.
PULLMODE ........................................................................................................................................................11
6.3.
OPENDRAIN .......................................................................................................................................................12
6.4.
DIFFRESISTOR ....................................................................................................................................................12
6.5.
HYSTERESIS ........................................................................................................................................................12
6.6.
DIN/DOUT..........................................................................................................................................................12
6.7.
LOC ....................................................................................................................................................................12
7. Design Recommendations ..........................................................................................................................................13
7.1.
Banking Rules ....................................................................................................................................................13
Appendix A. HDL Attributes ................................................................................................................................................14
VHDL Synplify Pro and LSE ..............................................................................................................................................14
Verilog Synplify Pro and LSE ...........................................................................................................................................16
Appendix B. sysI/O Attributes Using Spreadsheet View User Interface .............................................................................17
References ..........................................................................................................................................................................18
Technical Support Assistance .............................................................................................................................................18
Revision History ..................................................................................................................................................................18
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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TN1305-1.0
CrossLink sysI/O Usage Guide
Preliminary Technical Note
Figures
Figure 4.1. sysI/O Banking .................................................................................................................................................... 6
Figure 5.1. MIPI Primitive Symbol......................................................................................................................................... 9
Figure B.1. Port Attributes Tab of Spreadsheet View ......................................................................................................... 17
Tables
Table 3.1. Single-Ended I/O Standards ................................................................................................................................. 5
Table 3.2. Differential I/O Standards .................................................................................................................................... 5
Table 4.1. CrossLink FPGA Power Supplies ........................................................................................................................... 7
Table 4.2. I/O Standards Supported by Various Banks ......................................................................................................... 7
Table 5.1. LVCMOS Drive Values .......................................................................................................................................... 8
Table 5.2. MIPI Port List ...................................................................................................................................................... 10
Table 6.1. IO_TYPE Attribute Values ................................................................................................................................... 11
Table 6.2. PULLMODE Settings ........................................................................................................................................... 11
Table 6.3. PULLMODE Settings ........................................................................................................................................... 11
Table 6.4. Open Drain Attribute Values .............................................................................................................................. 12
Table 6.5. DIFFRESISTOR Values ......................................................................................................................................... 12
Table 6.6. Hysteresis Attribute Values ................................................................................................................................ 12
Table A.1. VHDL Attribute Syntax for Synplify .................................................................................................................... 14
Table A.2. Verilog Synplify Attribute Syntax ....................................................................................................................... 16
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
TN1305-1.0
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CrossLink sysI/O Usage Guide
Preliminary Technical Note
Acronyms in This Document
A list of acronyms used in this document.
Acronym
DRC
DDR
GPIO
GUI
HDL
2
IC
LSE
LVCMOS
LVDS
LVTTL
PIO
VHDL
VHSIC
WLCSP
Definition
Design Rule Check
Double Data Rate
General Purpose Input/Output
Graphical User Interface
Hardware Description Language
Inter-Integrated Circuit
Lattice Synthesis Engine
Low Voltage Complementary Metal Oxide Semiconductor
Low-Voltage Differential Signaling
Low Voltage Transistor-Transistor Logic
Programmable Input/Output
VHSIC Hardware Description Language
Very High Speed Integrated Circuit
Wafer Level Chip Scale Package
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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TN1305-1.0
CrossLink sysI/O Usage Guide
Preliminary Technical Note
1. Introduction
TM
The Lattice Semiconductor CrossLink device family features programmable sysI/O™ buffer that support a wide range
of interfaces. The sysI/O buffer gives the designer the ability to easily interface with other devices using advanced
system I/O standards.
This technical note describes the sysI/O standards that are available and how they can be implemented using Lattice
Diamond® design software.
2. sysI/O Buffer Overview
The key features of the sysI/O block are:
 Support for both differential and single-ended standards.
 Programmable weak pull-up on all banks.
2
 Support for on-chip programmable pull-up resistor for I C. (3.3 kΩ, 6.8 kΩ, 10 kΩ) in Bank 0.
 Support for on-chip dynamic differential input terminations on Bank 1 and Bank 2.
 Input Hysteresis on all LVCMOS33/LVTTL33, LVCMOS25, and LVCMOS18
 Programmable Open Drain on all outputs.

Bank 1 and Bank 2 are in groups of 16 I/Os or eight LVDS I/O pairs that support True-LVDS output driver,
differential input comparator and differential termination resistor per I/O pair. Both single-ended and differential
LVDS drivers can be tri-stated.
3. Supported sysI/O Standards
The CrossLink sysI/O buffer supports both single-ended and differential standards on Bank 1 and Bank 2. Bank 0
supports all the configuration pins and general purpose single-ended I/O. Table 3.1 lists the sysI/O standards supported
in CrossLink devices.
Table 3.1. Single-Ended I/O Standards
Standard
LVTTL33
VCCIO
3.3
Input
Yes
Output
Yes
Bi-directional
Yes
LVCMOS33
LVCMOS25
3.3
2.5
Yes
Yes
Yes
Yes
Yes
Yes
LVCMOS18
LVCMOS12
1.8
1.2
Yes
Yes
Yes
Yes
Yes
Yes
Table 3.2. Differential I/O Standards
Standard
Input
Output
Bi-directional
LVDS
subLVDS
Yes
Yes
Yes
No
No
No
MIPI (D-PHY)
SLVS
LVCMOS25D
Yes (HS-RX, LP-RX)
Yes
Yes
No*
No*
Yes
Yes (LP)
No
Yes
LVCMOS33D
No
Yes
No
LVTTL33D
No
Yes
No
*Note: These output standards are supported by the hard MIPI D-PHY blocks on CrossLink, but not the programmable I/O.
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
TN1305-1.0
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CrossLink sysI/O Usage Guide
Preliminary Technical Note
4. sysI/O Banking Scheme
CrossLink devices have three banks at the bottom and two MIPI ® D-PHY banks at the top of the device as shown in
Figure 4.1.
CrossLink supports single-ended buffers on all banks (0, 1 and 2.) Differential I/O is supported on Bank 1 and Bank 2.
There are eight differential I/O pairs on each bank (1 and 2.) There are a total of 16 pairs of differential I/Os which are
all True-LVDS. All the configuration ports are located at Bank 0.
TOP
MIPI D-PHY 0
MIPI D-PHY 1
Bank 2
Bank 1
Bank 0
VCCIO0
GND
VCCIO1
GND
VCCIO2
GND
BOTTOM
Figure 4.1. sysI/O Banking
4.1. VCC (1.2 V)
CrossLink devices have VCC core supply. This VCC supply is also used to power the control logic of the sysI/O buffers. The
control signals and data signals from the I/O logic are translated to the higher supply of the I/O buffers. When the
internal VCC core is powered down during sleep mode, VCC is still powered ON in I/O to maintain I/O personality.
4.2. VCCIO (1.2 V/1.8 V/2.5 V/3.3 V)
Each bank has a separate VCCIO supply that powers the single-ended output drivers and the non-referenced, ratioed
input buffers such as LVTTL, LVCMOS.
LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 also have fixed threshold options allowing them to be placed in any
bank. The VCCIO voltage applied to the bank determines the ratioed input standards that can be supported in that bank.
It is also used to power the differential output drivers. In addition, V CCIO of Bank 0 is used to supply power to the
sysCONFIG signals. When VCCIO = 2.5 V, it should be tied to VCCAUX25VPP.
4.3. VCCAUX25VPP (2.5 V)
In addition to the bank VCCIO supplies and a VCC core logic power supply, CrossLink devices have a VCCAUX25VPP auxiliary
supply that powers the differential and referenced input buffers. The VCCAUX25VPP supply is used for differential
receivers and 100 Ω termination blocks inside I/O.
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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CrossLink sysI/O Usage Guide
Preliminary Technical Note
4.4. D-PHY External Power Supplies (1.2 V)
VCC_DPHY, VCCA_DPHY, VCCPLL_DPHY, VCCMU_DPHY are supplies used to power the D-PHY.
Table 4.1 shows a summary of all the required power supplies.
Table 4.1. CrossLink FPGA Power Supplies
Voltage
2
(Nominal Value )
Supply
Description
VCC
1.2 V
FPGA core power supply
VCCGPLL
1.2 V
General Purpose PLL Supply Voltage. Should be isolated from excessive noise.
VCCAUX25VPP
2.5 V
Auxiliary Supply Voltage for Bank 1, 2 and NVCM programming.
VCCIO[2, 1, 0]
1.2 V to 3.3 V
VCC_DPHYx
1
VCCA_DPHYx
1
VCCPLL_DPHYx
1.2 V
I/O Driver Supply Voltage for Bank 0, 1, or 2. Each bank has its own VCCIO supply: VCCIO0 is
used in conjunction with pins dedicated and shared with device configuration.
Digital Supply Voltage for D-PHY. Should be isolated from excessive noise.
1.2 V
Analog Supply Voltage for D-PHY. Should be isolated and from excessive noise.
1
1.2 V
PLL Supply voltage for D-PHY. Should be isolated and “clean” from excessive noise.
1
1.2 V
VCC_DPHY1, VCCA_DPHY1 and VCCPLL_DPHY1 ganged together in the WLCSP36 package. Should be
isolated from excessive noise.
VCCMU_DPHYx
Notes:
1. X denotes bank number.
2. Refer to DS1055, CrossLink Family Data Sheet for recommended minimum and maximum values.
Table 4.2 lists the I/O Standards that are available in each bank on the device.
Table 4.2. I/O Standards Supported by Various Banks
Description (Types of I/O Buffers)
Top Side D-PHY Banks
Bottom Side Bank 0
Bottom Side Bank 1 and Bank 2
—
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS12
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS12
Differential Output Standards
MIPI D-PHY
SLVS
—
LVDS
LVTTL33D
LVCMOS33D
LVCMOS25D
Single-ended Input Standards
—
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS12
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS12
MIPI D-PHY
SLVS
—
LVDS
SUBLVDS
SLVS
LVCMOS25D
Yes
No
Yes (only for LVDS)
Single-ended Output Standards
Differential Input Standards
On Die Termination
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TN1305-1.0
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CrossLink sysI/O Usage Guide
Preliminary Technical Note
5. sysI/O Buffer Configurations
This section describes the various sysI/O features available on the CrossLink device.
5.1. Programmable PULLMODE Settings
The CrossLink sysI/O buffer supports programmable pull up resistors on banks. Each of the LVCMOS and LVTTL inputs
has a programmable weak pull-up capability that can be enabled if required on Bank 0, Bank 1 and Bank 2. In addition,
2
on Bank 0, the shared sysCONFIG bank, there is a programmable I C resistor. The available options for Bank 0 are:
 3P3K (3.3 kΩ)
 6P8K (6.8 kΩ)
 10K (10 kΩ)
 UP (100 kΩ), and
 NONE
2
These are mostly used to support I C interface, but can be used for other purposes also.
5.2. Output Drive Strength
The CrossLink outputs have preset drive strengths and cannot be programmed by the user. Table 5.1 lists the available
drive settings for each of the output standards.
Table 5.1. LVCMOS Drive Values
VCCIO
3.3
Dependent IO Type
Drive Strength (mA)
LVCMOS33
8
2.5
LVCMOS25
6
1.8
LVCMOS18
4
1.2
LVCMOS12
2
5.3. Open-Drain Control
All LVCMOS and LVTTL output buffers can be configured to function as open drain outputs. The user can implement an
open drain output by turning on the OPENDRAIN attribute in the software.
5.4. Differential I/O Support
CrossLink devices support true differential input buffers on each pair of IOs in the LVDS Bank 1 and Bank 2 with a
DIFFDRIVE of 3.5 mA. The performance of the LVDS input buffer is 1.2 Gb/s* for flip chip packages and 1.0 Gb/s* for
WLCSP.
*Note: The values are subject to change according to the final characterization.
5.5. Complementary Outputs
The single-ended driver associated with the complementary pad can optionally be driven by the complement of the
data that drives the single-ended driver associated with the true pad. CrossLink uses pads A and C as true pads and
pads B and D as complement pads. This allows a pair of single-ended drivers to be used to drive complementary
outputs with the lowest possible skew between the signals. Pads A and B form a Programmable Input/Output (PIO) pair
and pads C and D form another PIO pair.
It can be used in conjunction with off-chip resistors to emulate LVDS output drivers. When this option is selected, the
tri-state control for the driver associated with the complement pad is driven by the same signal as the tri-state control
for the driver associated with the true pad. In CrossLink, this option is available for LVCMOS33 and LVCMOS25 outputs.
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CrossLink sysI/O Usage Guide
Preliminary Technical Note
5.6. On-Chip Termination
Bank 0 in the CrossLink device is also called config/shared I/O bank. This I/O Bank only supports single-ended input and
output. There is a programmable I2C resistor on this bank that can be configured to use one of the internal integrated
pull-ups, the weak pull-up shall be off, and the following integrated pull-up values (or equivalent current source
through the transition region) are available.
 3.3 kΩ ±20%
 6.8 kΩ ±20%
 10 kΩ ±20%
Bank 1 and Bank 2 support differential and MIPI D-PHY inputs. These banks support the on-chip 100 Ω input differential
termination between all pairs of LVDS, SLVS, SUBLVDS and MIPI D-PHY inputs. It is statically configured as ON and OFF
for all differential input types except MIPI D-PHY.
When the IO type is MIPI, the on-chip termination is enabled dynamically based on the HSSEL signal (see Table 5.2 on
the next page for details). The tolerance of this input termination is ±20% over the operating range of the device.
5.7. Programmable Input Delay
Each input can optionally be delayed before it is passed to the core logic or input registers. The primary use for the
input delay is to achieve zero hold time for the input registers when using a direct drive primary clock. To arrive at zero
hold time, the input delay stalls the data by at least as much as the primary clock injection delay.
5.8. Standby
The Standby mode is a way to dynamically power down the bank. It disables the differential receiver and True
differential driver. The Standby modes are enabled on a bank by bank basis, with bit settings and each Bank has user
routed fabric input signals to enable the Standby (Dynamic power down) modes.
Refer to the TN1307, Power Management and Calculation for CrossLink Devices for more information about the
Standby settings for the I/O banks.
5.9. MIPI D-PHY Support
The following primitive should be used when implementing MIPI D-PHY I/O CrossLink supports High Speed (HS) Rx, Low
Power (LP) Rx and Low Power Tx mode. MIPI primitive is supported in Bank 1 and Bank 2.
PAP
MIP
AN
BP
BN
OLSN
TP
TN
HSSEL
OLSP
OHS
MIPI
Figure 5.1. MIPI Primitive Symbol
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TN1305-1.0
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CrossLink sysI/O Usage Guide
Preliminary Technical Note
Table 5.2. MIPI Port List
Port
I/O
Description
BP
IO
Bidirectional PAD A, C used for DPHY Clock / Data HS and LP mode
BN
IO
Bidirectional PAD B, D used for DPHY Clock / Data HS and LP mode
AP
I
Input from fabric to PAD A, C – used for LP Tx function only
AN
I
Input from fabric to PAD B, D – used for LP Tx function only
HSSEL
I
High Speed Select Signal.
HSSEL=1: High Speed mode, 100 Ω differential termination is on.
HSSEL=0: Low Speed mode, 100 Ω termination is turned off.
TP
I
Tristate for PAD A,C
TN
I
Tristate for PAD B,D
OLSP
O
LP Rx signal from BP
OLSN
O
LP Rx signal from BN
OHS
O
HS Rx signal from BP/BN differential
When IO_TYPE is MIPI, the MIPI primitive above should be instantiated in the design, otherwise the software Design
Rule Check (DRC) will error out. The output from the MIPI D-PHY buffer can only be used with the Double Data Rate
(DDR) registers. Refer to TN1301, CrossLink High-Speed I/O Interface for details on building MIPI D-PHY interfaces.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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CrossLink sysI/O Usage Guide
Preliminary Technical Note
6. Software sysI/O Attributes
The sysI/O attributes can be specified in the Hardware Description Language (HDL), using the Spreadsheet View or in
the logical preference file (.lpf) file directly. Appendix A and Appendix B list examples of how these can be assigned
using each of these methods mentioned above. This section describes in detail each of these attributes.
6.1. IO_TYPE
This is used to set the sysI/O standard for an I/O. The VCCIO required to set these I/O standards are embedded in the
attribute names itself. There is no separate attribute to set the VCCIO requirements. Table 6.1 lists the available I/O
types.
Table 6.1. IO_TYPE Attribute Values
sysI/O Signaling Standard
IO_TYPE
DEFAULT
LVCMOS25
LVTTL
LVTTL33
LVTTL Differential
LVTTL33D
3.3 V LVCMOS
LVCMOS33
3.3 V LVCMOS Differential
LVCMOS33D
2.5 V LVCMOS
LVCMOS25
2.5 V LVCMOS Differential
LVCMOS25D
1.8 V LVCMOS
LVCMOS18
1.2 V LVCMOS
LVCMOS12
LVDS 2.5 V
LVDS
Sub-LVDS
SUBLVDS
SLVS
SLVS
MIPI D-PHY
MIPI
6.2. PULLMODE
The PULLMODE attribute is available for all the LVTLL and LVCMOS inputs and bidirectional I/Os. This attribute can be
enabled for each I/O independently.
Table 6.2. PULLMODE Settings
Pull Options
PULLMODE VALUE
Weak Pull-up (Default)
2
I C Pull-up Resistors
UP
3P3K (3.3K), 6P8K (6.8K), 10K
Pull Off
NONE
Table 6.3. PULLMODE Settings
Buffer
Values
Input
UP, NONE, 3P3K, 6P8K, 10K
Output
NONE
Default
UP
NONE
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
TN1305-1.0
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CrossLink sysI/O Usage Guide
Preliminary Technical Note
6.3. OPENDRAIN
LVCMOS and LVTTL I/O standards can be set to Open Drain configuration by using the OPENDRAIN attribute.
Table 6.4. Open Drain Attribute Values
Attribute
Values
OPENDRAIN
ON, OFF
Default
OFF
6.4. DIFFRESISTOR
This attribute is used to set the on-chip differential termination on MIPI D-PHY HS, LVDS, SLVS and Sub-LVDS inputs.
Table 6.5. DIFFRESISTOR Values
Attribute
Values
DIFFRESISTOR
OFF, 100
Default
100
6.5. HYSTERESIS
Hysteresis can be enabled for LVCMOS and LVTTL inputs.
Table 6.6. Hysteresis Attribute Values
Attribute
Values
Default
HYSTERESIS
ON, NA
ON
6.6. DIN/DOUT
This attribute can be used when an I/O register need to be assigned. Using DIN will assert an input register and using
DOUT attribute will assert an output register in the design. By default the software will try to assign the I/O registers if
applicable. User can turn this OFF by using synthesis attribute or using the preference editor of the software. These
attributes can only be applied on registers.
6.7. LOC
This attribute can be used to make pin assignments to the I/O ports in the design. This attribute is only used when the
pin assignments are made in HDL source. You can also assign pins directly using the Graphical User Interface (GUI) in
the Spreadsheet View of the software.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Preliminary Technical Note
7. Design Recommendations
This section discusses some of design rules and considerations that need to be taken into account when designing with
the CrossLink sysI/O buffer.
7.1. Banking Rules








If VCCIO for any bank is set to 2.5 V, it is recommended to connect it to the same power supply as VCCAUX25VPP, thus
minimizing leakage.
If VCCIO for any bank is set to 1.2 V, it is recommended to connect it to the same power supply as VCC, thus
minimizing leakage.
On the top of the device, the two banks have hard DPHY blocks. These are not available for any other functions.
On the bottom side Bank 0 is General Purpose Input/Output (GPIO) and sysConfig bank. Only single-ended I/O
standards can be built into this bank.
Bank 1 and Bank 2 at the bottom support differential Inputs and Outputs as well as singled-ended I/Os.
DIFFRESISTOR can be turned on for each PIO. Only Bank 1 and Bank 2 have this feature.
I2C pull-up resistors are only available on Bank 0.
Only one VCCIO level is allowed in a given bank so all IO_TYPES of that bank should be compatible with that VCCIO
level.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
TN1305-1.0
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CrossLink sysI/O Usage Guide
Preliminary Technical Note
Appendix A. HDL Attributes
Using these HDL attributes, you can assign the sysI/O attributes directly in your source. Use the attribute definition
and syntax for your synthesis vendor. The sysI/O attributes syntax and examples for Synplify Pro® synthesis tool and
Lattice Synthesis Engine (LSE) are listed here. This appendix only lists the sysI/O buffer attributes for these devices.
Refer to the Synplify Pro user manual to see a complete list of synthesis attributes. These manuals are available
through the Diamond Software Help.
VHDL Synplify Pro and LSE
This section lists syntax and examples for all the sysI/O attributes in VHSIC Hardware Description Language (VHDL)
when using Synplify Pro synthesis tool and LSE.
Syntax
Table A.1. VHDL Attribute Syntax for Synplify
Attribute
Syntax
IO_TYPE
attribute IO_TYPE: string;
attribute IO_TYPE of Pinname: signal is “IO_TYPE Value”;
attribute PULLMODE: string;
attribute PULLMODE of Pinname: signal is “Pullmode Value”;
attribute OPENDRAIN: string;
attribute OPENDRAIN of Pinname: signal is “OpenDrain Value”;
attribute DIFFRESISTOR: string;
attribute DIFFRESISTOR of Pinname: signal is “DIFFRESISTOR Value”;
attribute HYSTERESIS: string;
attribute HYSTERESIS of Pinname: signal is “HYSTERESIS Value”;
attribute DIN: string;
attribute DIN of Pinname: signal is “ ”;
attribute DOUT: string;
attribute DOUT of Pinname: signal is “ ”;
attribute LOC: string;
attribute LOC of Pinname: signal is “pin_locations”;
PULLMODE
OPENDRAIN
DIFFRESISTOR
HYSTERESIS
DIN
DOUT
LOC
Examples
IO_TYPE
--***Attribute Declaration***
ATTRIBUTE IO_TYPE: string;
--***IO_TYPE assignment for I/O Pin***
ATTRIBUTE IO_TYPE OF portA: SIGNAL IS "LVCMOS25";
ATTRIBUTE IO_TYPE OF portB: SIGNAL IS "LVCMOS33";
ATTRIBUTE IO_TYPE OF portC: SIGNAL IS "LVDS25";
PULLMODE
--***Attribute Declaration***
ATTRIBUTE PULLMODE: string;
--***PULLMODE assignment for I/O Pin***
ATTRIBUTE PULLMODE OF portB: SIGNAL IS "UP";
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
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OPENDRAIN
--***Attribute Declaration***
ATTRIBUTE OPENDRAIN: string;
--***Open Drain assignment for I/O Pin***
ATTRIBUTE OPENDRAIN OF portB: SIGNAL IS "ON";
DIFFERESISTOR
--***Attribute Declaration***
ATTRIBUTE DIFFRESISTOR: string;
--*** DIFFRESISTOR assignment for I/O Pin***
ATTRIBUTE DIFFRESISTOR OF portB: SIGNAL IS "100";
HYSTERESIS
--***Attribute Declaration***
ATTRIBUTE HYSTERESIS: string;
--*** DIFFRESISTOR assignment for I/O Pin***
ATTRIBUTE HYSTERESIS OF portB: SIGNAL IS "ON";
DIN/DOUT
--***Attribute Declaration***
ATTRIBUTE din: string;
ATTRIBUTE dout: string;
--*** din/dout assignment for I/O Pin***
ATTRIBUTE din OF input_vector: SIGNAL IS " ";
ATTRIBUTE dout OF output_vector: SIGNAL IS " ";
LOC
--***Attribute Declaration***
ATTRIBUTE LOC: string;
--*** LOC assignment for I/O Pin***
ATTRIBUTE LOC OF input_vector: SIGNAL IS "E3,B3,C3 ";
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Verilog Synplify Pro and LSE
This section lists syntax and examples for all the sysI/O attributes in Verilog using Synplify Pro synthesis tool.
Syntax
Table A.2. Verilog Synplify Attribute Syntax
Attribute
Syntax
IO_TYPE
PinType PinName /* synthesis IO_TYPE=“IO_Type Value”*/;
PULLMODE
PinType PinName /* synthesis PULLMODE=“Pullmode Value”*/;
OPENDRAIN
PinType PinName /* synthesis OPENDRAIN =“OpenDrain Value”*/;
DIFFRESISTOR
PinType PinName /* synthesis DIFFRESISTOR =“ DIFFRESISTOR Value”*/;
HYSTERESIS
PinType PinName /* synthesis HYSTERESIS =“Hysteresis Value”*/;
DIN
PinType PinName /* synthesis DIN=“ ”*/;
DOUT
PinType PinName /* synthesis DOUT=“ ”*/;
LOC
PinType PinName /* synthesis LOC=“pin_locations”*/;
Examples
//IO_TYPE and PULLMODE assignment
output portB /*synthesis IO_TYPE="LVCMOS33" PULLMODE =”UP”*/;
output portC /*synthesis IO_TYPE="LVDS" */;
//PULLMODE
output [4:0] portA /* synthesis IO_TYPE="LVCMOS33" PULLMODE = “NONE” */;
//OPENDRAIN
output portA /*synthesis OPENDRAIN =”ON”*/;
//DIFFRESISTOR
input portB /*synthesis IO_TYPE="LVDS" DIFFRESITOR=”100” */;
//HYSTERESIS
input portB /*synthesis HYSTERESIS=”ON” */;
//DIN (Place the flip-flops near the load input)
input load /* synthesis din="" */;
//DOUT (Place the flip-flops near the load output)
output load /* synthesis dout="" */;
//LOC (I/O pin location)/input [3:0] DATA0 /* synthesis loc="E3,B1,F3"*/;
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Appendix B. sysI/O Attributes Using Spreadsheet View User
Interface
The sysI/O buffer attributes can be assigned using the Spreadsheet View in Lattice Diamond design software. The Port
Assignments sheet lists all the ports in a design and all the available sysI/O attributes in multiple columns. Click on each
of these cells for a list of all valid I/O preferences for that port.
Each column takes precedence over the next. Therefore, when you choose a particular IO_TYPE, the columns for the
PULLMODE, DRIVE, SLEWRATE and other attributes will only list the valid entries for that IO_TYPE.
Pin locations can be locked using the Pin column of the Port Assignments sheet or using the Pin Assignments sheet.
You can right-click on a cell in the Pin column and click Assign Pins to see the list of available pins. In Spreadsheet View,
go to Design, then Preference PIO DRC to look for incorrect pin assignments.
You can enter the DIN/DOUT preferences using the Cell Mapping tab. All the preferences assigned using the
Spreadsheet View are written into the logical preference file (.lpf).
Figure B.1 shows the Port Assignments sheet of the Spreadsheet View. For further information on how to use the
Spreadsheet View, refer to the Diamond Help documentation, available in the Help menu option of the software.
Figure B.1. Port Attributes Tab of Spreadsheet View
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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References
For more information, refer to the following documents:
 DS1055, CrossLink Family Data Sheet
 TN1301, CrossLink High-Speed I/O Interface
 TN1302, CrossLink Hardware Checklist
 TN1303, CrossLink Programming and Configuration Usage Guide
 TN1304, CrossLink sysCLOCK PLL/DLL Design and Usage Guide
 TN1306, CrossLink Memory Usage Guide
 TN1307, Power Management and Calculation for CrossLink Devices
 TN1308, CrossLink I2C Hardened IP Usage Guide
 TN1309, Advanced CrossLink I2C Hardened IP Reference Guide
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.
Revision History
Date
Version
May 2016
1.0
Change Summary
First preliminary release.
© 2015-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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