Advanced Silicon Devices –
Applications and Technology Trends
Gerald Deboy
Winfried Kaindl, Uwe Kirchner, Matteo Kutschak,
Eric Persson, Michael Treu
APEC 2015
Content
Silicon devices versus GaN devices: An unbiased view on key
performance indicators
Applications: Comparison of devices in hard-switching and
resonant circuits
Summary
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 2
Content
Silicon devices versus GaN devices: An unbiased view on key
performance indicators
Applications: Comparison of devices in hard-switching and
resonant circuits
Summary
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 3
Comparing competing device concepts
Si
SiC
Superjunction
vertical drift zone
G
S
GaN
S
G
S
n+ p+
lateral HEMT
G
D
2DEG
D
p
n
D
D
RON×A scales with cell pitch
Inherently fast switching
dv/dt scales inversely with
cell pitch
Reverse recovery charge and
snappyness of body diode as
major drawbacks
March 2015
Pitch influences RON×A by
improved utillization of the
semiconductor volume
Normally-on; turns into
normally-off by Cascode or
direct-driven concept
Good body diode; Qrr close
to SiC Schottky diodes
Good starting point for low
RON×A and QOSS due to high
electron mobility
Device capacitances are
strongly influenced by the
metal re-routing
Excellent reverse behavior
n-Epitaxy
p-Implantation
Metal/Poly-Si
p+-Implantation
AlN/AlGaN Barrier
n+-Implantation
Si Substrate
Oxide
Buffer layer
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 4
How far can the Superjunction concept be
exploited in terms of RDSon*A?
G
S
RDSON, max × A [Ωmm2]
n
p+
Other 1
CoolMOSTM C3
CoolMOSTM CP
1,00
Si Superjunction MOSFET
pp
Other 2
Other 3
1.55 Ωmm2
CoolMOSTM C7
1.0 Ωmm2
nepi
n+s
ub
D
SiC FET
GaN HEMT
Si Superjunction limit
D. Disney, G. Dolny
0,10
ISPSD 2008
SiC and GaN devices
0,01
2000
2002
2004
2006
2008
2010
2012
2014
2016
2018
2020
Still a long way until the limit is reached with Si Superjunction.
Si limit potentially lower than 0.5 Ωmm2
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 5
The output capacitance of SJ devices gets more nonlinear with every generation! 190 mOhm, 600V / 650V devices
longer delay times
lower switching losses
Stronger non-linearity
lower Eoss
higher dv/dt
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 6
The Qoss characteristic will become more and
more flat! 190 mOhm, 600V / 650V devices
longer delay times
in resonant applications
trend reversed for
next gen CoolMOS™
more rectangular voltage waveforms
GaN significantly better in
absolute FoM and linearity
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 7
Eoss scales with cell pitch and can be brought below
the level of 1st gen GaN devices 190 mOhm, 600V / 650V devices
FoM Ron*Eoss scales
with pitch of SJ device
next gen CoolMOS™
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 8
40% Eoss reduction versus earlier SJ generation fully
translates into lower turn-off losses! 190 mOhm / 600V
BoxPlot Eoff2 [mJ] (Subset:Iset2 [A] ('5,3')) grouped by GRP
lo -- hi -- qty 36/36 mean 0.008648 sigma 0.002466 cp -- cpk -0,013
Turn-off losses
@ 5.3A [mJ]
Eoff2 [mJ]
0,012
0,011
CoolMOS™ CP 600V
0,01
0,009
next gen CoolMOS™
0,008
0,007
LEGEND
GRP
G1
G2
G3
0,006
0,005
40% reduction of switching losses
0,004
(CoolMOS™ CP vs next gen CoolMOS™)
0,003
Fully relieved switching up to around
10 Ohm gate resistor
0,002
0,001
0
4
March 2015
6
8
10
12
14
16
18
20
Rg [Ohm]
22
24
26
Copyright © Infineon Technologies AG 2015. All rights reserved.
28
30
32
Page 9
Turn-on losses are mainly determined by package and
no longer benefit from silicon improvements! 190 mOhm / 600V
BoxPlot Eon [mJ] (Subset:Iset2 [A] ('5,3')) grouped by GRP
lo -- hi -- qty 36/36 mean 0.0172 sigma 0.007441 cp -- cpk --
Turn-on losses
Eon [mJ]@ 5.3A [mJ]
0,035
0,03
0,025
CoolMOS™ CP
0,02
next gen CoolMOS™
0,015
Turn-on losses mainly limited by
parasitic package inductances
Significant improvement potential
for 4pin & SMD packages
0,01
0,005
LEGEND
GRP
G1
G2
G3
0
4
March 2015
6
8
10
12
14
16
18
20
Rg [Ohm]
22
24
26
Copyright © Infineon Technologies AG 2015. All rights reserved.
28
30
32
Page 10
Package and switching cell optimization are mandatory
to fully benefit from fast switching devices!
TO-247 4pin
Package level
Kelvin contact to source,
decoupling of gate drive,
Eon improvement
- Source inductance
most critical
- Solved by Kelvin contact
- however inductance still
in the commutation loop
ThinPAK, TOLL,
DSO-20
Switching cell level
- True SMD solution allows
compact, low-inductive
switching cell
- Symmetric coupling
capacitances to heatsink
are important from EMI
point of view
- Top side cooling
optional in DSO-20
March 2015
Heatsink
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 11
SMD packages will be important for SJ
devices and mandatory for GaN!
T_LS
PCB top view:
Losses
d1
T_HS
s1
85-265VAC
s2
d2
Cheatsink TO = ~20 pF
E400V
= 1.6 µJ
Cpar
Edev
= 3 µJ
Voltage overshoot
Power loop caps
d1
Current flow:
C
T_HS
T_LS
Top Layer
s1
85-265VAC
d2
s2
Lpar TO
Elpar_10A
Vovershoot
400V
= ~20 nH
= 1 µJ
= 100V
@ 5kA/µs
Mid Layer
Lpar = 3- 6 nH
heatsink
Commutation loop 3.2 nH
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 12
In case of layout constraints…
Possible Ringing Circuit
dV/ dt
Cparasitic
Layout
Turn Off dV/dt
[V/ns]
Lparasitic
Layout
Example 190 mΩ
250
200
150
100
50
0
C7
CP
P6
E6
C6
0
Package
Damping Element
dI/ dt
Oscillation circuit triggered by dV/ dt
5
0
C7
CM1
nG
P6
E6 CFD II CFD I
Best performance
March 2015
20
C3
C3
C6
Avoid
30 a coupling capacitance between G,D
C7
η
20 the gate resistor close to the gate
Place
CP
10 Stray inductance in the Power Loop
Avoid
P6
Use 0the mutual inductance effect (opposite
E6
20 forced
40
60
80 in the
100 power
-10 0 flow,
current
current)
loop
C6
-20
current
Vgs [V]
+
Cparasitic = 5pF
Rg int
Layout sensitiviity
high efficiency
CP
10
15
Current ID [A]
Low switching losses are inevitably coupled to high
dv/dt and di/dt values both at turn-on and turn-off.
Example 190mΩ
With C6 a integrated Gate Resistor was
introduced to damp Oscillations
Optimization tradeoff efficiency and
Layout with each new technology
-
5
How
to use
fast switching
SJ devices
Damping
behavior
of Rg Internal
Layout Sensitivity
10
η
-30
Ids [A]
C3
Less
layout
dependencies
can be achieved by
Add
ferrite
beads if necessary
choosing a technology with higher values of the
damping resistor.
Cost/performance segment
Ease of Use optimized
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 13
Content
Silicon devices versus GaN devices: An unbiased view on key
performance indicators
Applications: Comparison of devices in hard-switching and
resonant circuits
Summary
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 14
SJ devices will prevail in classic and dual boost
GaN offers significant value in Totem Pole PFC
Classic PFC
Dual Boost PFC
Less System Cost
Less Efficiency
High Power Density
High System Cost
High Efficiency
Less Power Density
Totem Pole PFC
Less System Cost
High Efficiency
High Power Density
GaN enables hard
commutation on
internal “diode”
Superjunction
SiC
March 2015
(S1)
(D1)
Superjunction
SiC
(S1, S2)
(D1, D2)
Copyright © Infineon Technologies AG 2015. All rights reserved.
Superjunction
GaN, SJ, IGBT
(S1, S2)
(S3, S4)
Page 15
Best competing silicon alternative in terms of power
density and efficiency: TCM PFC 3 kW, 4.5 kW/l (74W/in³)
Source: U. Badstübner, J. Miniböck, J. Kolar, „ Experimental Verification of the Efficiency/Power-Density (n-p) Pareto Front
of Single-Phase Double-Boost and TCM PFC Rectifier Systems”, Proc. APEC 2013.
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 16
Advantage of GaN: very high frequency operation
with Ron*Qoss and Qg as key parameters
Input Caps
Output
Caps
RF Inductor
GaN Switches
Gate
Driver
High efficiency possible by frequency control
99%
Efficiency
97%
95%
2.5 MHz
93%
91%
89%
87%
85%
0
March 2015
100
200
300
Po [W]
Copyright © Infineon Technologies AG 2015. All rights reserved.
400
500
Page 17
Comparison of hard-switching PFC stages:
Reference: CoolMOS™ C7 / SiC G5
Reference: CCM PFC 100 kHz;
CoolMOS™ C7 65 mOhm, 4pin;
SiC G5 SBD 16A
diode rectification bridge
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 18
Advantage of GaN: CCM modulation in Totem Pole PFC,
close to 99% efficiency with simple half bridge solution
0.5% better efficiency
half bridge Totem Pole, 65 kHz;
GaN 70 mOhm
return path: bridge rectifier (one diode only)
Reference: CCM PFC 100 kHz;
CoolMOS C7 65 mOhm, 4 pin;
SiC G5 SBD 16A
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 19
Advantage of GaN: > 99% efficiency with
combination of SJ and GaN in Totem Pole full bridge
0.2% better than half bridge
0.4% better than IGBT solution
full bridge Totem Pole, 65 kHz;
Reference: CCM PFC 100 kHz;
GaN 70 mOhm / IGBT F5 40A + 16A SiC SBD
CoolMOS C7 65 mOhm, 4 pin;
return path: CoolMOS™ C7 35 mOhm
SiC G5 SBD 16A
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 20
Advantage of GaN: > 99% efficiency across wide
low range with low frequency Totem Pole PFC
>99% efficiency from 20..70% load
0.1% better than 65 kHz solution
full bridge Totem Pole, 45 kHz;
Reference: CCM PFC 100 kHz;
GaN 70 mOhm
CoolMOS C7 65 mOhm, 4 pin;
return path: CoolMOS™ C7 35 mOhm
SiC G5 SBD 16A
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 21
Expected performance of GaN versus
latest SJ devices
Resonant LLC DC/DC Converter (750 W, 400 kHz)
D1
Q1
VIN
Cr
Lr
n:1:1
S1
A
D2
Q2
VO
Lm
RL
0
S2
GaN expected to be 0.7% better
in partial load range
GaN, 70 mOhm
GaN, 190 mOhm
P6, 190 mOhm
350V…410 V to 12 V
Power density > 200W/in³
Pure convection cooled
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 22
Latest SJ devices will benefit from parallel
cap to counterbalance non-linearity
Same dv/dt at 1/5th of magnetizing current
Potential path to further efficiency increase
for narrow range Vin applications
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 23
Last but not least! Recent improvements in key
Figure-of-Merits for low voltage MOSFETs …
S
G
n
p
nn+sub
sub
D
n
5
4,5
4
3,5
3
2,5
2
1,5
1
0,5
0
Gen 3
Gen 4
RDSon / SSO8
[mOhm]
RDSon*Qoss
[mOhm*nC *100]
100 V MOSFET: smaller area-specific on-resistance and charges
through further optimization of trench structure
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 24
… Allow new solutions by using cascaded
multi-cell architectures!
3 kW AC/DC converter, 48V out
Cascaded converter topology, Totem Pole + phase shift ZVS
Efficiency target > 98%
100 V OptiMOS™ BSC034N10NS5
FinSix 65 W Adapter, 19V out
Switching frequency > 10 MHz
200 V OptiMOS™ BSZ22DN20NS3
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 25
Content
Silicon devices versus GaN devices: An unbiased view on key
performance indicators
Applications: Comparison of devices in hard-switching and
resonant circuits
Summary
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 26
Summary
Superjunction devices will continue to deliver better Best-inClass RDSon devices with further improved FoM Ron*Eoss
Recent improvements in low voltage devices FoMs allow to
rethink classic architectures and consider the use of LV devices
in HV applications
The use of good layout practice, transition to 4pin packages and
finally to SMD packages will become more and more important
and is mandatory for GaN
GaN offers specifically advantages both in terms of power
density and efficiency at hard switching topologies with
continuous use of the reverse characteristic and at very high
switching frequencies in resonant converters
March 2015
Copyright © Infineon Technologies AG 2015. All rights reserved.
Page 27