(Application Note)

SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1926 Application Note
This document contains information on a product under development. Solomon Systech reserves the right to change
or discontinue this product without notice.
http://www.solomon-systech.com
SSD1926
Rev 1.0
P 1/1
Application Note
Jul 2009
Copyright  2009 Solomon Systech Limited
CONTENTS
1
DISPLAY DATA FORMATS ..................................................................................................... 5
2
REGISTERS TABLE .................................................................................................................. 6
2.1
2.2
2.3
2.4
REGISTER MAPPING ...................................................................................................................................................6
READ-ONLY CONFIGURATION REGISTERS .................................................................................................................6
CLOCK CONFIGURATION REGISTERS .........................................................................................................................8
LOOK-UP TABLE REGISTERS ...................................................................................................................................10
2.4.1
Monochrome Modes....................................................................................................................................10
2.4.2
Color Modes ...............................................................................................................................................12
2.5
PANEL CONFIGURATION REGISTERS ........................................................................................................................17
2.5.1
Monochrome 8-Bit Panel Timing................................................................................................................19
2.5.2
Color 8-Bit Panel Timing (Format stripe) ..................................................................................................20
2.5.3
Color 16-Bit Panel Timing..........................................................................................................................21
2.5.4
Generic TFT Panel Timing .........................................................................................................................23
2.5.5
Serial TFT Panel Timing ............................................................................................................................24
2.6
SMART PANEL CONFIGURATION REGISTERS ............................................................................................................40
2.6.1
Write Through Mode...................................................................................................................................40
2.7
INTERRUPT REGISTERS ............................................................................................................................................52
2.8
POWER UP REGISTERS .............................................................................................................................................53
2.9
DISPLAY MODE REGISTERS .....................................................................................................................................55
2.10 MAIN WINDOW REGISTERS .....................................................................................................................................57
2.11 SCRATCH BIT REGISTERS .........................................................................................................................................59
2.12 GENERAL IO PINS REGISTERS .................................................................................................................................59
2.13 2D ENGINE REGISTERS ............................................................................................................................................83
2.14 DISPLAY ROTATE MODE..........................................................................................................................................84
2.14.1 90° Display Rotate Mode ............................................................................................................................84
2.14.2 180° Display Rotate Mode ..........................................................................................................................85
2.14.3 270° Display Rotate Mode ..........................................................................................................................86
2.15 FLOATING WINDOW MODE......................................................................................................................................87
2.15.1 Floating window under 90°Display Rotate Mode.......................................................................................87
2.15.2 Floating window under 180°Display Rotate Mode.....................................................................................88
2.15.3 Floating window under 270°Display Rotate Mode.....................................................................................88
2.16 CURSOR MODE ........................................................................................................................................................95
2.16.2 Cursor with 270° Display Rotate Mode ...................................................................................................101
2.17 DRAW2D MODE ....................................................................................................................................................118
2.18 JPEG DECODE REGISTERS ....................................................................................................................................130
2.18.1 Decode Procedure ....................................................................................................................................130
2.19 MMC/SD/SDIO REGISTERS .................................................................................................................................145
Solomon Systech
Jul 2009
P 2/3
Rev 1.0
SSD1926
Application Note
TABLES
TABLE 2-1: SUGGESTED M & N VALUE ................................................................................................................................9
TABLE 2-2: PANEL TIMING PARAMETER DEFINITION AND REGISTER SUMMARY ................................................................18
TABLE 2-3: PANEL DATA WIDTH SELECTION ......................................................................................................................27
TABLE 2-4: LCD PANEL TYPE SELECTION ..........................................................................................................................27
TABLE 2-5: THE SETTING FOR DISPLAY POST-PROCESSING SATURATION .............................................................................34
TABLE 2-6: THE SETTING FOR DISPLAY POST-PROCESSING BRIGHTNESS .............................................................................35
TABLE 2-7: THE SETTING FOR DISPLAY POST-PROCESSING CONTRAST................................................................................35
TABLE 2-8: THE RGB SEQUENCE FOR SERIAL-TFT INTERFACE ..........................................................................................37
TABLE 2-9: DATA TYPE FOR PARALLEL INTERFACE OF ALL PANEL TYPES............................................................................40
TABLE 2-10: INPUT DATA FORMAT FOR WRITE THROUGH MODE ........................................................................................40
TABLE 2-11: DATA OUTPUT FORMAT FOR DISPLAY PIXEL IN PARALLEL INTERFACE ............................................................41
TABLE 2-12: DATA OUTPUT FORMAT FOR 4-WIRE SERIAL INTERFACE (REG[260H] BIT 6= 1) ............................................41
TABLE 2-13: DATA OUTPUT FORMAT FOR 3-WIRE SERIAL INTERFACE (REG[260H] BIT 6= 0) ............................................42
TABLE 2-14: DATA INPUT FORMAT FOR AUTO REFRESH MODE ..........................................................................................42
TABLE 2-15: OUTPUT TIMING FOR 6800 PARALLEL INTERFACE ..........................................................................................42
TABLE 2-16: OUTPUT TIMING FOR 8080 PARALLEL INTERFACE ..........................................................................................43
TABLE 2-17: OUTPUT TIMING FOR SERIAL INTERFACE ........................................................................................................44
TABLE 2-18: REGISTER FOR SMART PANEL INTERFACE........................................................................................................46
TABLE 2-19: LCD BIT-PER-PIXEL SELECTION .....................................................................................................................56
TABLE 2-20: DISPLAY ROTATE MODE SELECT OPTIONS .....................................................................................................84
TABLE 2-21: 32-BIT ADDRESS X INCREMENTS FOR VARIOUS COLOR DEPTHS ....................................................................91
TABLE 2-22: 32-BIT ADDRESS Y INCREMENTS FOR VARIOUS COLOR DEPTHS ....................................................................92
TABLE 2-23: 32-BIT ADDRESS X INCREMENTS FOR VARIOUS COLOR DEPTHS ....................................................................93
TABLE 2-24: 32-BIT ADDRESS Y INCREMENTS FOR VARIOUS COLOR DEPTHS ....................................................................94
TABLE 2-25: INDEXING SCHEME FOR HARDWARE CURSOR .................................................................................................95
TABLE 2-26: X INCREMENT MODE FOR VARIOUS COLOR DEPTHS ....................................................................................106
TABLE 2-27: Y INCREMENT MODE FOR VARIOUS COLOR DEPTHS ....................................................................................107
TABLE 2-28: YUV OUTPUT RANGE SELECTION ................................................................................................................131
TABLE 2-29: JPEG FIFO THRESHOLD STATUS .................................................................................................................131
TABLE 2-30: JPEG FIFO THRESHOLD STATUS .................................................................................................................133
TABLE 2-31: JPEG FIFO TRIGGER THRESHOLD SELECTION .............................................................................................137
TABLE 2-32: JPEG FIFO THRESHOLD STATUS .................................................................................................................137
TABLE 2-33: YUV FORMAT SELECTION ...........................................................................................................................140
TABLE 2-34: RST MARKER SELECTION ............................................................................................................................144
TABLE 2-35: JPEG ERROR STATUS ...................................................................................................................................145
TABLE 2-36: DETERMINATION OF TRANSFER TYPE ...........................................................................................................150
TABLE 2-37: COMMAND REGISTER ...................................................................................................................................152
TABLE 2-38: RELATION BETWEEN PARAMETERS AND THE NAME OF RESPONSE TYPE .....................................................152
TABLE 2-39: RESPONSE BIT DEFINITION FOR EACH RESPONSE TYPE ................................................................................153
TABLE 2-40: THE RELATION BETWEEN COMMAND CRC ERROR AND COMMAND TIMEOUT ERROR..................................168
TABLE 2-41: THE RELATION BETWEEN COMMAND CRC ERROR AND COMMAND TIMEOUT ERROR FOR AUTO CMDI2 ...173
SSD1926
Application Note
Rev 1.0
P 3/4
Jul 2009
Solomon Systech
FIGURES
FIGURE 1-1: DISPLAY DATA MEMORY ORGANIZATION ........................................................................................................5
FIGURE 2-1: CLOCK CONFIGURATION ....................................................................................................................................8
FIGURE 2-2: 1 BIT-PER-PIXEL MONOCHROME MODE DATA OUTPUT PATH .........................................................................10
FIGURE 2-3: 2 BIT-PER-PIXEL MONOCHROME MODE DATA OUTPUT PATH .........................................................................11
FIGURE 2-4: 4 BIT-PER-PIXEL MONOCHROME MODE DATA OUTPUT PATH .........................................................................11
FIGURE 2-5: 8 BIT-PER-PIXEL MONOCHROME MODE DATA OUTPUT PATH .........................................................................11
FIGURE 2-6: 1 BIT-PER-PIXEL COLOR MODE DATA OUTPUT PATH.....................................................................................12
FIGURE 2-7: 2 BIT-PER-PIXEL COLOR MODE DATA OUTPUT PATH.....................................................................................12
FIGURE 2-8: 4 BIT-PER-PIXEL COLOR MODE DATA OUTPUT PATH.....................................................................................13
FIGURE 2-9: 8 BIT-PER-PIXEL COLOR MODE DATA OUTPUT PATH .....................................................................................14
FIGURE 2-10: PANEL TIMING PARAMETERS ........................................................................................................................18
FIGURE 2-11: MONOCHROME 8-BIT PANEL TIMING ............................................................................................................19
FIGURE 2-12: COLOR 8-BIT PANEL TIMING (FORMAT STRIPE) ............................................................................................20
FIGURE 2-13: COLOR 16-BIT PANEL TIMING .......................................................................................................................21
FIGURE 2-14: GENERIC TFT PANEL TIMING .......................................................................................................................23
FIGURE 2-15: SERIAL TFT PANEL TIMING ..........................................................................................................................25
FIGURE 2-16: 6800 TIMING DIAGRAM.................................................................................................................................43
FIGURE 2-17: 8080 TIMING DIAGRAM.................................................................................................................................44
FIGURE 2-18: 4 WIRES TIMING DIAGRAM ...........................................................................................................................45
FIGURE 2-19: 3 WIRES TIMING DIAGRAM ...........................................................................................................................45
FIGURE 2-20: GPIO[4:0] OUTPUT SETUP .............................................................................................................................61
FIGURE 2-21: EXAMPLES FOR LCD SIGNALX BY NDPOFF AND ODD / EVEN BITS ............................................................79
FIGURE 2-22: DISPLAY DATA BYTE/WORD SWAP ...............................................................................................................83
FIGURE 2-23: RELATIONSHIP BETWEEN SCREEN IMAGE AND IMAGE REFRESHED IN 90° DISPLAY ROTATE MODE.............84
FIGURE 2-24: RELATIONSHIP BETWEEN SCREEN IMAGE AND IMAGE REFRESHED IN 180° DISPLAY ROTATE MODE...........85
FIGURE 2-25: RELATIONSHIP BETWEEN SCREEN IMAGE AND IMAGE REFRESHED IN 270° DISPLAY ROTATE MODE...........86
FIGURE 2-26: FLOATING WINDOW WITH DISPLAY ROTATE MODE DISABLED .....................................................................87
FIGURE 2-27: FLOATING WINDOW WITH DISPLAY ROTATE MODE 90° ENABLED................................................................87
FIGURE 2-28: FLOATING WINDOW WITH DISPLAY ROTATE MODE 180° ENABLED..............................................................88
FIGURE 2-29: FLOATING WINDOW WITH DISPLAY ROTATE MODE 270° ENABLED..............................................................88
FIGURE 2-30: DISPLAY PRECEDENCE IN HARDWARE CURSOR ............................................................................................96
FIGURE 2-31: CURSORS ON THE MAIN WINDOW ...................................................................................................................96
FIGURE 2-32: CURSORS WITH DISPLAY ROTATE MODE 90° ENABLED.................................................................................97
FIGURE 2-33: CURSORS WITH DISPLAY ROTATE MODE 180° ENABLED...............................................................................99
FIGURE 2-34: CURSORS WITH DISPLAY ROTATE MODE 270° ENABLED.............................................................................101
FIGURE 2-35: TIMING OF COMMAND INHIBIT (DAT) AND COMMAND INHIBIT (CMD) WITH DATA TRANSFER .................158
FIGURE 2-36: TIMING OF COMMAND INHIBIT (DAT) FOR THE CASE OF RESPONSE WITH BUSY..........................................159
FIGURE 2-37: TIMING OF COMMAND INHIBIT (CMD) FOR THE CASE OF NO RESPONSE COMMAND ....................................159
Solomon Systech
Jul 2009
P 4/5
Rev 1.0
SSD1926
Application Note
1
Display Data Formats
The following diagrams show the display mode data formats.
1 bpp:
bit 7
bit 0
Byte 0
A0
A1
A2
Byte 1
A8
A9
A10 A11
A12 A13 A14 A15
Byte 2
A16 A17 A18 A19
A20 A21 A22 A23
A3
A4
A5
A6
P0 P1 P2 P3 P4 P5 P6 P7
A7
LUT
Pn = RGB value from LUT
Index (An)
Host Address
Display Buffer
2 bpp:
Panel Display
bit 7
bit 0
Byte 0
A0
B0
A1
B1
A2
B2
A3
B3
Byte 1
A4
B4
A5
B5
A6
B6
A7
B7
Byte 2
A8
B8
A9
B9
A10 B10 A11 B11
P0 P1 P2 P3 P4 P5 P6 P7
LUT
Host Address
Pn = RGB value from LUT
Index (An, Bn)
A is MSB, B is LSB
Display Buffer
4 bpp:
Panel Display
bit 7
Byte 0
A0
Byte 1
Byte 2
bit 0
B0
C0
D0
A1
B1
C1
D1
A2
B2
C2
D2
A3
B3
C3
D3
A4
B4
C4
D4
A5
B5
C5
D5
P0 P1 P2 P3 P4 P5 P6 P7
LUT
Pn = RGB value from LUT
Index (An, Bn, Cn, Dn)
A is MSB, D is LSB
Host Address
Display Buffer
8 bpp:
Panel Display
bit 7
bit 0
Byte 0
A0
B0
C0
D0
E0
F0
G0
H0
Byte 1
A1
B1
C1
D1
E1
F1
G1
H1
Byte 2
A2
B2
C2
D2
E2
F2
G2
H2
P0 P1 P2 P3 P4 P5 P6 P7
LUT
Pn = RGB value from LUT Index
(An, Bn, Cn, Dn, En, Fn, Gn, Hn)
A is MSB, H is LSB
Host Address
Display Buffer
16 bpp:
Byte 0
bit 7
2
G0 G01 G00 B04
4
3
2
2
B0
5
3
B0
0
B0
1
Panel Display
1
4
bit 0
0
B0
3
Byte 1
R0
R0
R0
R0
R0
G0
G0
G0
Byte 2
2
G1
1
G1
0
G1
4
B1
3
B1
2
B1
1
B1
0
B1
Byte 3
R1
4
3
R1
Host Address
32 bpp:
2
R1
1
R1
0
R1
5
G1
4
G1
P0 P1 P2 P3 P4 P5 P6 P7
Bypasses LUT
4-0
5-0
4-0
Pn = (Rn , Gn , Bn )
3
G1
Panel Display
Display Buffer
Byte 0
bit 7
bit 0
7
R0 R06 R05 R04 R03 R02 R01 R00
Byte 1
G07 G06 G05 G04 G03 G02 G01 G00
Byte 2
7
B0
7
Byte 3
Byte 4
A0
7
R1
Host Address
6
B0
6
A0
6
R1
5
B0
5
A0
5
R1
4
B0
4
A0
4
R1
3
B0
3
A0
3
R1
2
B0
2
A0
2
R1
1
B0
1
A0
1
R1
0
B0
P0 P1 P2 P3 P4 P5 P6 P7
Bypasses LUT
7-0
7-0
7-0
7-0
Pn = (Rn , Gn , Bn , An )
3
A0
0
R1
Panel Display
Display Buffer
Figure 1-1: Display Data Memory Organization
Note
1.
2.
For 16 bpp format, Rn, Gn, Bn represent the red, green, and blue color components.
For 32 bpp format, Rn, Gn, Bn, An represent the red, green, blue color and alpha blending components.
SSD1926
Application Note
Rev 1.0
P 5/6
Jul 2009
Solomon Systech
2
REGISTERS TABLE
This document discusses how and where to access the SSD1926 registers. It also provides detailed
information about the layout and usage of each register.
2.1
Register Mapping
The SSD1926 registers are memory-mapped. When the system decodes the input pins as CS# = 0 and
M/R# = 0, the registers may be accessed. The register space is decoded by A[18:0].
Unless specified otherwise, all register bits are set to 0 during power-on or software reset (REG[A2h]
bit 0 = 1). All bits marked “0” should be programmed as zero. All bits marked “1” should be
programmed as one.
Key :
RO : Read Only. Writes to these bits are ignored.
ROC : Read Only and initialized to zero at reset. Writes to these bits are ignored.
WO : Write Only
RW : Read / Write
RW1C : Read Only. Write 1 to clear status. Writing a 0 to these bits has no effect.
RWAC : Read-Write, automatic clear. Writing a 0 to these bits has no effect.
NA : Not Applicable
X : Don’t care
2.2
Read-Only Configuration Registers
Debug Code Register
Bit
Type
Reset
state
7
Debug
Code
Bit 7
RO
0
Bits 7-0
6
Debug
Code
Bit 6
RO
0
REG[00h]
5
Debug
Code
Bit 5
RO
1
4
Debug
Code
Bit 4
RO
0
3
Debug
Code
Bit 3
RO
1
2
Debug
Code
Bit 2
RO
0
Type
Reset
state
0
Debug
Code
Bit 0
RO
0
Debug Code
These bits show the dummy value for debug purpose. The readback code is 00101000.
Read Dummy Register
Bit
1
Debug
Code
Bit 1
RO
0
7
Debug
Code
Bit 7
RO
1
Bits 7-0
Solomon Systech
6
Debug
Code
Bit 6
RO
0
REG[01h]
5
Debug
Code
Bit 5
RO
0
4
Debug
Code
Bit 4
RO
0
3
Debug
Code
Bit 3
RO
0
2
Debug
Code
Bit 2
RO
0
1
Debug
Code
Bit 1
RO
0
0
Debug
Code
Bit 0
RO
0
Debug Code
These bits show the dummy value for debug purpose. The readback code is 10000000.
Jul 2009
P 6/7
Rev 1.0
SSD1926
Application Note
Configuration Readback Register
Bit
7
Reserved
Type
Reset
state
RO
X
6
CNF6
Status
RO
X
Bits 7-0
5
Reserved
RO
X
REG[02h]
4
CNF4
Status
RO
X
3
CNF3
Status
RO
X
2
CNF2
Status
RO
X
1
CNF1
Status
RO
X
0
CNF0
Status
RO
X
CNF[6:0] Status
These status bits return the status of the configuration pins CNF[6:0]. CNF[4:0] are latched at
the rising edge of RESET# or software reset (REG[A2h] bit 0 = 1).
Bit 7 = Bit 6
Bit 5 = Bit 4
REG[03h]
Product Code Register
Bit
7
Product
Code
Bit 5
RO
1
Type
Reset
state
6
Product
Code
Bit 4
RO
0
Bits 7-2
5
Product
Code
Bit 3
RO
0
4
Product
Code
Bit 2
RO
0
3
Product
Code
Bit 1
RO
0
2
Product
Code
Bit 0
RO
0
1
Revision
Code Bit 1
0
Revision
Code Bit 0
RO
0
RO
0
Product Code Bits [5:0]
These are read-only bits that indicate the product code.
The product code of SSD1926 is 100000.
Revision Code Bits [1:0]
These are read-only bits that indicate the revision code which readback value is 00.
Bits 1-0
REG[05h]
Memory status Register
Bit
7
Reserved
6
Reserved
Type
Reset
state
RO
1
RO
X
5
AD_MODE
Status
RO
X
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
RO
0
RO
0
RO
0
RO
0
RO
0
Bits 7, 4-0
Reserved bits
Bits 6-5
AD_MODE Status
These status bits return the status of the configuration pin AD_MODE which is latched at the
rising edge of RESET# or software reset (REG[A2h] bit 0 = 1).
Bit 6 = Bit 5
SSD1926
Application Note
Rev 1.0
P 7/8
Jul 2009
Solomon Systech
2.3
Clock Configuration Registers
MCLK Divider
REG[04h] or
CNF7:6
PLL_CLK
REG[126-127h]
MCLK
SDHC Divider
REG[1001h]
and
REG[112Dh]
SD_CLK
PCLK Divider
REG
[15A-158h]
PCLK
Figure 2-1: Clock configuration
PLL Clock Setting Register 0
Bit
7
PLL enable
bit
RW
0
Type
Reset
state
Bit 7
REG[126h]
6
Reserved
5
Reserved
RW
0
RW
0
4
N value bit
4
RW
1
3
N value bit
3
RW
0
2
N value bit
2
RW
0
1
N value bit
1
RW
0
0
N value bit
0
RW
0
PLL enable bit
1
Enable PLL. PLL_DIS should tie to IOVSS and clock source should be provided
through CLKI and CLKO(optional).
0
Disable PLL. PLL_DIS should tie to IOVDD and clock source should be provided
through CLKI2.
Reserved bits
N value bits [4:0]
This register is used to program the N value for clock frequency
Bits 6-5
Bits 4-0
Note : The value of N should be greater than 1.
PLL Clock Setting Register 1
Bit
Type
Reset
state
7
M value bit
7
RW
1
Bits 7-0
6
M value bit
6
RW
0
5
M value bit
5
RW
0
REG[127h]
4
M value bit
4
RW
0
3
M value bit
3
RW
0
2
M value bit
2
RW
0
1
M value bit
1
RW
0
0
M value bit
0
RW
0
M value bits [7:0]
This register is used to program the M value for clock frequency
Note : The value of M should be greater than 1.
Solomon Systech
Jul 2009
P 8/9
Rev 1.0
SSD1926
Application Note
PLL Clock Setting Register 2
Bit
7
PLL config
value bit 7
RW
1
Type
Reset
state
6
PLL config
bit 6
RW
0
Bits 7-0
REG[12Bh]
5
PLL config
bit 5
RW
0
4
PLL config
bit 4
RW
0
3
PLL config
bit 3
RW
1
2
PLL config
bit 2
RW
1
1
PLL config
bit 1
RW
1
0
PLL config
bit 0
RW
0
PLL configuration value bits [7:0]
This register is used to config the PLL setting. This register should be programmed to 0xAE.
Bits 7:5 : control the internal reference clock value when PLL is not locked
Bits 4:0 : control the bias current of PLL (b’0x00000 is not allowed)
Program sequence (example input clock frequency = 2MHz) :
1. Write the N value (REG[126h] = 0x05)
2. Write the M value (REG[127h] = 0xC8)
3. Write the PLL Conf value (REG[12Bh] = 0xAE)
4. Enable the PLL (REG[126h] = 0x85)
Then, the PLL output clock frequency = Input clock frequency * (M / N) = 80MHz
Maximum output clock frequency = 85MHz
Table 2-1: Suggested M & N value
Input clock frequency
2MHz
2.5MHz
3MHz
3.5MHz
4Mz
N value
0x05
0x06
0x08
0x09
0x0A
M value
0xC8
0xC0
0xD5
0xCE
0xC8
3
MCLK
Divide
Select Bit 3
RW
0
2
MCLK
Divide
Select Bit 2
RW
0
Memory Clock Configuration Register
Bit
7
0
6
0
5
0
Type
Reset
state
RO
0
RW
0
RW
0
4
MCLK
Divide
Select Bit 4
RW
0
REG[04h]
1
MCLK
Divide
Select Bit 1
RW
0
0
MCLK
Divide
Select Bit 0
RW
0
Bits 7-5
Reserved bits
Bits 4-0
MCLK Divide Select Bits [4:0]
These bits determine the divide used to generate the Memory Clock (MCLK) from the PLL
output frequency. Refer to REG[126h], REG[127h] for the PLL output frequency.
MCLK Frequency = PLL output frequency / (MCLK divide value + 1)
SSD1926
Application Note
Rev 1.0
P 9/10
Jul 2009
Solomon Systech
PCLK Frequency Ratio Register 0
Bit
Type
Reset
state
7
PCLK
Ratio bit 7
RW
0
6
PCLK
Ratio bit 6
RW
0
5
PCLK
Ratio bit 5
RW
0
REG[158h]
4
PCLK
Ratio bit 4
RW
0
3
PCLK
Ratio bit 3
RW
0
2
PCLK
Ratio bit 2
RW
0
4
PCLK
Ratio bit 12
RW
0
3
PCLK
Ratio bit 11
RW
0
2
PCLK
Ratio bit 10
RW
0
3
PCLK
Ratio bit 19
RW
0
2
PCLK
Ratio bit 18
RW
0
1
PCLK
Ratio bit 1
RW
0
PCLK Frequency Ratio Register 1
Bit
Type
Reset
state
7
PCLK
Ratio bit 15
RW
0
6
PCLK
Ratio bit 14
RW
0
5
PCLK
Ratio bit 13
RW
0
REG[159h]
1
PCLK
Ratio bit 9
RW
0
PCLK Frequency Ratio Register 2
0
PCLK
Ratio bit 8
RW
0
REG[15Ah]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
REG[15Ah] Bits 3-0,
REG[159h] Bits 7-0,
REG[158h] Bits 7-0
0
PCLK
Ratio bit 0
RW
0
1
PCLK
Ratio bit 17
RW
0
0
PCLK
Ratio bit 16
RW
0
PCLK Frequency Ratio [19:0]
These bits determine the Frequency for PCLK.
PCLK frequency = MCLK frequency * (PCLK Frequency Ratio + 1) / (220)
Note
(1)
Bit[19:0] are used for non Serial-TFT panel type (REG[10h] bit 2:0 not equal to 010)
(2)
Bit[17:0] are used for Serial-TFT panel type (REG[10h] bit 2:0 equal to 010)
(3)
PCLK = MCLK (Bit[19:0] = 0xFFFFF) for smart panel interface.
2.4
Look-Up Table Registers
The following sections are the Look-up Table architecture which shows the display data output path only.
2.4.1 Monochrome Modes
The green Look-Up Table (LUT) is used for all monochrome modes.
Green Look-Up Table 256x6
1 bit-per-pixel data
from Display Buffer
6-bit Gray Data
00
01
Figure 2-2: 1 Bit-per-pixel Monochrome Mode Data Output Path
Solomon Systech
Jul 2009
P 10/11
Rev 1.0
SSD1926
Application Note
Green Look-Up Table 256x6
00
01
02
03
2 bit-per-pixel data
from Display Buffer
6-bit Gray Data
Figure 2-3: 2 Bit-per-pixel Monochrome Mode Data Output Path
Green Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
4 bit-per-pixel data
from Display Buffer
6-bit Gray Data
Figure 2-4: 4 Bit-per-pixel Monochrome Mode Data Output Path
Green Look-Up Table 256x6
00
01
02
03
04
05
06
07
6-bit Gray Data
8 bit-per-pixel data
from Display Buffer
F8
F9
FA
FB
FC
FD
FE
FF
Figure 2-5: 8 Bit-per-pixel Monochrome Mode Data Output Path
For 16/32 bit-per-pixel monochrome Mode, the LUT is bypassed and the green data is directly mapped for this color
depth – See Figure 1-1.
SSD1926
Application Note
Rev 1.0
P 11/12
Jul 2009
Solomon Systech
2.4.2 Color Modes
Red Look-Up Table 256x6
00
01
6-bit Red Data
Green Look-Up Table 256x6
1 bit-per-pixel data
from Display Buffer
6-bit Green Data
00
01
Blue Look-Up Table 256x6
6-bit Blue Data
00
01
Figure 2-6: 1 Bit-Per-Pixel Color Mode Data Output Path
Red Look-Up Table 256x6
00
01
02
03
6-bit Red Data
Green Look-Up Table 256x6
2 bit-per-pixel data
from Display Buffer
00
01
02
03
6-bit Green Data
Blue Look-Up Table 256x6
6-bit Blue Data
00
01
02
03
Figure 2-7: 2 Bit-Per-Pixel Color Mode Data Output Path
Solomon Systech
Jul 2009
P 12/13
Rev 1.0
SSD1926
Application Note
Red Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
6-bit Red Data
Green Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
4 bit-per-pixel data
from Display Buffer
6-bit Green Data
Blue Look-Up Table 256x6
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
6-bit Blue Data
Figure 2-8: 4 Bit-Per-Pixel Color Mode Data Output Path
SSD1926
Application Note
Rev 1.0
P 13/14
Jul 2009
Solomon Systech
Red Look-Up Table 256x6
00
01
02
03
04
05
06
07
6-bit Red Data
F8
F9
FA
FB
FC
FD
FE
FF
Green Look-Up Table 256x6
00
01
02
03
04
05
06
07
6-bit Green Data
8 bit-per-pixel data
from Display Buffer
F8
F9
FA
FB
FC
FD
FE
FF
Blue Look-Up Table 256x6
00
01
02
03
04
05
06
07
6-bit Blue Data
F8
F9
FA
FB
FC
FD
FE
FF
Figure 2-9: 8 Bit-per-pixel Color Mode Data Output Path
For 16/32 bit-per-pixel color mode, the LUT is bypassed and the color data is directly mapped for this color depth – See
Figure 1-1.
Solomon Systech
Jul 2009
P 14/15
Rev 1.0
SSD1926
Application Note
Look-Up Table Blue Write Data Register
Bit
Type
Reset
state
7
LUT Blue
Write Data
Bit 7
WO
0
6
LUT Blue
Write Data
Bit 6
WO
0
Bits 7-0
5
LUT Blue
Write Data
Bit 5
WO
0
4
LUT Blue
Write Data
Bit 4
WO
0
REG[08h]
3
LUT Blue
Write Data
Bit 3
WO
0
2
LUT Blue
Write Data
Bit 2
WO
0
1
LUT Blue
Write Data
Bit 1
WO
0
0
LUT Blue
Write Data
Bit 0
WO
0
LUT Blue Write Data Bits [7:0]
This register contains the data to be written to the blue component of the Look-Up Table.
The data is stored in this register until a write to the LUT Write Address register (REG[0Bh])
moves the data into the Look-Up Table.
Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is written.
Look-Up Table Green Write Data Register
Bit
Type
Reset
state
7
LUT Green
Write Data
Bit 7
WO
0
6
LUT Green
Write Data
Bit 6
WO
0
Bits 7-0
5
LUT Green
Write Data
Bit 5
WO
0
4
LUT Green
Write Data
Bit 4
WO
0
REG[09h]
3
LUT Green
Write Data
Bit 3
WO
0
2
LUT Green
Write Data
Bit 2
WO
0
1
LUT Green
Write Data
Bit 1
WO
0
0
LUT Green
Write Data
Bit 0
WO
0
LUT Green Write Data Bits [7:0]
This register contains the data to be written to the green component of the Look-Up Table.
The data is stored in this register until a write to the LUT Write Address register (REG[0Bh])
moves the data into the Look-Up Table.
Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is written.
Look-Up Table Red Write Data Register
Bit
Type
Reset
state
7
LUT Red
Write Data
Bit 7
WO
0
6
LUT Red
Write Data
Bit 6
WO
0
Bits 7-0
5
LUT Red
Write Data
Bit 5
WO
0
4
LUT Red
Write Data
Bit 4
WO
0
REG[0Ah]
3
LUT Red
Write Data
Bit 3
WO
0
2
LUT Red
Write Data
Bit 3
WO
0
1
LUT Red
Write Data
Bit 1
WO
0
0
LUT Red
Write Data
Bit 0
WO
0
LUT Red Write Data Bits [7:0]
This register contains the data to be written to the red component of the Look-Up Table.
The data is stored in this register until a write to the LUT Write Address register (REG[0Bh])
moves the data into the Look-Up Table.
Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is written.
SSD1926
Application Note
Rev 1.0
P 15/16
Jul 2009
Solomon Systech
Look-Up Table Write Address Register
Bit
Type
Reset
state
7
LUT Write
Address Bit
7
WO
0
Bits 7-0
6
LUT Write
Address Bit
6
WO
0
5
LUT Write
Address Bit
5
WO
0
4
LUT Write
Address Bit
4
WO
0
REG[0Bh]
3
LUT Write
Address Bit
3
WO
0
2
LUT Write
Address Bit
2
WO
0
1
LUT Write
Address Bit
1
WO
0
0
LUT Write
Address Bit
0
WO
0
LUT Write Address Bits [7:0]
This register is a pointer to the Look-Up Table (LUT) which is used to write LUT data stored in
REG[08h], REG[09h], and REG[0Ah]. The data is updated to the LUT only with the
completion of a write to this register. This is a write-only register and returns 00h if read.
Note
The SSD1926 has three 256-entry, 8-bit-wide LUTs, one for each of red, green and blue (see
Section “Look-Up Table Architecture” in datasheet).
Look-Up Table Blue Read Data Register
Bit
Type
Reset
state
7
LUT Blue
Read Data
Bit 7
RO
0
Bits 7-0
6
LUT Blue
Read Data
Bit 6
RO
0
5
LUT Blue
Read Data
Bit 5
RO
0
4
LUT Blue
Read Data
Bit 4
RO
0
REG[0Ch]
3
LUT Blue
Read Data
Bit 3
RO
0
2
LUT Blue
Read Data
Bit 2
RO
0
1
LUT Blue
Read Data
Bit 1
RO
0
0
LUT Blue
Read Data
Bit 0
RO
0
LUT Blue Read Data Bits [7:0]
This register contains the data from the blue component of the Look-Up Table. The LUT entry
read is controlled by the LUT Read Address Register (REG[0Fh]).
Note
This register is updated only when the LUT Read Address Register (REG[0Fh]) is written.
Look-Up Table Green Read Data Register
Bit
Type
Reset
state
7
LUT Green
Read Data
Bit 7
RO
0
Bits 7-0
6
LUT Green
Read Data
Bit 6
RO
0
5
LUT Green
Read Data
Bit 5
RO
0
4
LUT Green
Read Data
Bit 4
RO
0
REG[0Dh]
3
LUT Green
Read Data
Bit 3
RO
0
2
LUT Green
Read Data
Bit 2
RO
0
1
LUT Green
Read Data
Bit 1
RO
0
0
LUT Green
Read Data
Bit 0
RO
0
LUT Green Read Data Bits [7:0]
This register contains the data from the green component of the Look-Up Table. The LUT entry
read is controlled by the LUT Read Address Register (REG[0Fh]).
Note
This register is updated only when the LUT Read Address Register (REG[0Fh]) is written.
Solomon Systech
Jul 2009
P 16/17
Rev 1.0
SSD1926
Application Note
Look-Up Table Red Read Data Register
Bit
7
LUT Red
Read Data
Bit 7
RO
0
Type
Reset
state
6
LUT Red
Read Data
Bit 6
RO
0
Bits 7-0
5
LUT Red
Read Data
Bit 5
RO
0
4
LUT Red
Read Data
Bit 4
RO
0
REG[0Eh]
3
LUT Red
Read Data
Bit 3
RO
0
2
LUT Red
Read Data
Bit 2
RO
0
1
LUT Red
Read Data
Bit 1
RO
0
0
LUT Red
Read Data
Bit 0
RO
0
LUT Red Read Data Bits [7:0]
This register contains the data from the red component of the Look-Up Table. The LUT entry
read is controlled by the LUT Read Address Register (REG[0Fh]).
Note
This register is updated only when the LUT Read Address Register (REG[0Fh]) is written.
Look-Up Table Read Address Register
Bit
7
LUT Read
Address Bit
7
WO
0
Type
Reset
state
6
LUT Read
Address Bit
6
WO
0
Bits 7-0
5
LUT Read
Address Bit
5
WO
0
4
LUT Read
Address Bit
4
WO
0
REG[0Fh]
3
LUT Read
Address Bit
3
WO
0
2
LUT Read
Address Bit
2
WO
0
1
LUT Read
Address Bit
1
WO
0
0
LUT Read
Address Bit
0
WO
0
LUT Read Address Bits [7:0]
This register is a pointer to the Look-Up Table (LUT) which is used to read LUT data and store
it in REG[0Ch], REG[0Dh], REG[0Eh]. The data is read from the LUT only when a write to
this register is completed. This is a write-only register and returns 00h if read.
Note
The SSD1926 has three 256-entry, 8-bit-wide LUTs, one for each of red, green and blue (see
Section “Look-Up Table Architecture” in datasheet).
2.5
Panel Configuration Registers
Figure 2-10 shows the timing parameters required to drive a flat panel display. Timing details for each
supported panel types are provided in the remainder of this section.
SSD1926
Application Note
Rev 1.0
P 17/18
Jul 2009
Solomon Systech
HT
HDPS
HPS
HPW
VDPS
HDP
VT
VPS
VDP
VPW
Figure 2-10: Panel Timing Parameters
Table 2-2: Panel Timing Parameter Definition and Register Summary
Symbol
HT
Description
Horizontal Total
HDP 2
HDPS
HPS
HPW
VT
Horizontal Display Period 2
Horizontal Display Period Start Position
LLINE Pulse Start Position
LLINE Pulse Width
Vertical Total
VDP 3
Vertical Display Period 3
VDPS
VPS
Vertical Display Period Start Position
LFRAME Pulse Start Position
VPW
LFRAME Pulse Width
Derived From
((REG[12h] bits 7-0) + 1) x 8 + (REG[13h] bits 20)
((REG[14h] bits 6-0) + 1) x 8
((REG[17h]bits 2-0,REG[16h]bits7-0))
(REG[23h] bits 2-0, REG[22h] bits 7-0) + 1
(REG[20h] bits 6-0) + 1
((REG[19h] bits 2-0, REG[18h] bits 7-0) + 1) x
HT
((REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1) x
HT
(REG[1Fh] bits 2-0, REG[1Eh] bits 7-0) x HT
(REG[27h] bits 2-0, REG[26h] bits 7-0) x HT +
(REG[31h] bits 2-0, REG[30h] bits 7-0)
((REG[24h] bits 2-0) + 1) x HT + (REG[35h] bits
2-0, REG[34h] bits 7-0) – (REG[31h] bits 2-0,
REG[30h] bits 7-0)
Units
Ts 1
Ts 1
The following conditions must be fulfilled for all panel timings:
HDPS + HDP < HT
VDPS + VDP < VT
1
Ts = pixel clock period
2
The HDP must be a minimum of 32 pixels and can be increased by multiples of 8.
3
The VDP must be a minimum of 2 lines.
Solomon Systech
Jul 2009
P 18/19
Rev 1.0
SSD1926
Application Note
2.5.1
Monochrome 8-Bit Panel Timing
VDP
VNDP
LFRAME
LLINE
LDEN (MOD)
LDATA[7:0]
LINE1
LINE2
LINE3
LINE479
LINE480
LINE1
LINE2
LLINE
LDEN (MOD)
HDP
HNDP
LSHIFT
LDATA7
1-1
1-9
1-633
LDATA6
1-2
1-10
1-634
LDATA5
1-3
1-11
1-635
LDATA4
1-4
1-12
1-636
LDATA3
1-5
1-13
1-637
LDATA2
1-6
1-14
1-638
LDATA1
1-7
1-15
1-639
LDATA0
1-8
1-16
1-640
*Diagram drawn with 2 LLINE vertical blank period
Example timing for a 640x480 panel
Figure 2-11: Monochrome 8-Bit Panel Timing
VDP
= Vertical Display Period
= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 Lines
VNDP = Vertical Non-Display Period
= VT-VDP
= (REG[19h] bits 2:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines
HDP = Horizontal Display Period
= ((REG[14h] bits 6:0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 7:0) + 1) x 8Ts + (REG[13h] bits 2-0)) - (((REG[14h] bits 6:0) + 1) x 8Ts)
SSD1926
Application Note
Rev 1.0
P 19/20
Jul 2009
Solomon Systech
2.5.2 Color 8-Bit Panel Timing (Format stripe)
VDP
VNDP
LFRAME
LLINE
LDEN (MOD)
LDATA[7:0]
LINE1
LINE2
LINE3
LINE479
LINE480
LINE1
LINE2
LLINE
LDEN (MOD)
HDP
HNDP
LSHIFT
LDATA7
1-R1
LDATA6
1-G1
1-R4
1-B6
1-B638
LDATA5
1-B1
1-G4
1-R7
1-R639
LDATA4
1-R2
1-B4
1-G7
1-G639
LDATA3
1-G2
1-R5 1-B7
1-B639
LDATA2
1-B2
1-G5
1-R8
1-R640
LDATA1
1-R3
1-B5
1-G8
1-G640
LDATA0
1-G3
1-R6
1-B8
1-B640
1-B3
1-G6
1-G638
*Diagram drawn with 2 LLINE vertical blank period
Example timing for a 640X480 panel
Figure 2-12: Color 8-Bit Panel Timing (Format stripe)
VDP
= Vertical Display Period
= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 Lines
VNDP = Vertical Non-Display Period
= VT-VDP
= (REG[19h] bits 2:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines
HDP = Horizontal Display Period
= ((REG[14h] bits 6:0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 7:0) + 1) x 8Ts + (REG[13h] bits 2-0) ) - (((REG[14h] bits 6:0) + 1) x 8Ts)
Solomon Systech
Jul 2009
P 20/21
Rev 1.0
SSD1926
Application Note
2.5.3
Color 16-Bit Panel Timing
VDP
VNDP
LFRAME
LLINE
LDEN (MOD)
LDATA[7:0]
LINE1
LINE2
LINE3
LINE479
LINE480
LINE1
LINE2
LLINE
LDEN (MOD)
HDP
HNDP
LSHIFT
LDATA15
1-R1
LDATA14
1-B1
1-R7
1-G12
1-G636
LDATA13
1-G2
1-B7
1-R13
1-R637
LDATA12
1-R3
1-G8
1-B13
1-B637
LDATA7
1-B3
1-R9 1-G14
1-G638
LDATA6
1-G4
1-B9
1-R15
1-R639
LDATA5
1-R5
1-G10 1-B15
1-B639
LDATA4
1-B5
1-R11 1-G16
1-G640
LDATA11
1-G1
1-B6 1-R12
LDATA10
1-R2
1-G7
1-B12
1-B636
LDATA9
1-B2
1-R8
1-G13
1-G637
LDATA8
1-G3
1-B8
1-R14
1-R638
LDATA3
1-R4
1-G9 1-B14
1-B638
LDATA2
1-B4
1-R10 1-G15
1-G639
LDATA1
1-G5
1-B10 1-R16
1-R640
LDATA0
1-R6
1-G11 1-B16
1-B640
1-G6 1-B11
1-G635
1-R636
*Diagram drawn with 2 LLINE vertical blank period
Example timing for a 640X480 panel
Figure 2-13: Color 16-Bit Panel Timing
SSD1926
Application Note
Rev 1.0
P 21/22
Jul 2009
Solomon Systech
VDP
= Vertical Display Period
= (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) + 1 Lines
VNDP = Vertical Non-Display Period
= VT-VDP
= (REG[19h] bits 2:0, REG[18h] bits 7:0) - (REG[1Dh] bits 1:0, REG[1Ch] bits 7:0) Lines
HDP = Horizontal Display Period
= ((REG[14h] bits 6:0) + 1) x 8Ts
HNDP = Horizontal Non-Display Period
= HT - HDP
= (((REG[12h] bits 7:0) + 1) x 8Ts + (REG[13h] bits 2-0) ) - (((REG[14h] bits 6:0) + 1) x 8Ts)
Solomon Systech
Jul 2009
P 22/23
Rev 1.0
SSD1926
Application Note
2.5.4
Generic TFT Panel Timing
VT (= 1 Frame)
VPS
VPW
LFRAME
VDPS
VDP
LLINE
LDEN
LDATA[17:0]
HT (= 1 Line)
HPW
HPS
LLINE
LSHIFT
LDEN
HDP
HDPS
LDATA[17:0]
Figure 2-14: Generic TFT Panel Timing
VT
= Vertical Total
= [(REG[19h] bits 2-0, REG[18h] bits 7-0) + 1] lines
VPS = LFRAME Pulse Start Position
= [(REG[27h] bits 2-0, REG[26h] bits 7-0)] x HT + (REG[31h] bits 2-0, REG[30h] bits 7-0) pixels
VPW = LFRAME Pulse Width
= [(REG[24h]bits2-0)+ 1] x HT + (REG[35h] bits 2-0, REG[34h] bits 7-0) – (REG[31h] bits 2-0,
REG[30h] bits 7-0) pixels
VDPS = Vertical Display Period Start Position
= [(REG[1Fh]bits2-0,REG[1Eh]bits7-0)] lines
VDP = Vertical Display Period
SSD1926
Application Note
Rev 1.0
P 23/24
Jul 2009
Solomon Systech
= [(REG[1Dh]bits1-0,REG[1Ch]bits7-0) + 1] lines
* The VDP must be a minimum of 2 lines
HT
= Horizontal Total
= [((REG[12h] bits 7-0) + 1) x 8 + (REG[13h] bits 2-0)] pixels
HPS = LLINE Pulse Start Position
= [(REG[23h] bits 2-0, REG[22h] bits 7-0) + 1] pixels
HPW = LLINE Pulse Width
= [(REG[20h] bits 6-0)+ 1] pixels
HDPS = Horizontal Display Period Start Position
= [(REG[17h] bits 2-0, REG[16h] bits 7-0) + 5] pixels
HDP = Horizontal Display Period
= [((REG[14h] bits 6-0) + 1) x 8] pixels
The HDP must be a minimum of 32 pixels and can be increased by multiples of 8.
*Panel Type Bits (REG[10h] bits 2-0) = 001 (TFT)
*LLINE Pulse Polarity Bit (REG[24h] bit 7) = 0 (active low)
*LFRAME Polarity Bit (REG[20h] bit 7) = 0 (active low)
2.5.5
Serial TFT Panel Timing
Solomon Systech
Jul 2009
P 24/25
Rev 1.0
SSD1926
Application Note
VT (= 1 Frame)
VPS
VPW
LFRAME
VDPS
VDP
LLINE
LDEN
LDATA[7:0]
HT (= 1 Line)
HPW
HPS
LLINE
LSHIFT
LDEN
HDP
HDPS
LDATA[7:0]
Figure 2-15: Serial TFT Panel Timing
VT
= Vertical Total
= [(REG[19h] bits 2-0, REG[18h] bits 7-0) + 1] lines
VPS = LFRAME Pulse Start Position
= [(REG[27h] bits 2-0, REG[26h] bits 7-0)] x HT + (REG[31h] bits 2-0, REG[30h] bits 7-0) pixels
VPW = LFRAME Pulse Width
= [(REG[24h]bits2-0)+ 1] x HT + (REG[35h] bits 2-0, REG[34h] bits 7-0) – (REG[31h] bits 2-0,
REG[30h] bits 7-0) pixels
VDPS = Vertical Display Period Start Position
= [(REG[1Fh]bits2-0,REG[1Eh]bits7-0)] lines
VDP = Vertical Display Period
= [(REG[1Dh]bits1-0,REG[1Ch]bits7-0)+ 1] lines
*
The VDP must be a minimum of 2 lines
SSD1926
Application Note
Rev 1.0
P 25/26
Jul 2009
Solomon Systech
HT
= Horizontal Total
= [(REG[12h] bits 7-0) x 8 + (REG[13h] bits 2-0) + 1] pixels
HPS = LLINE Pulse Start Position
= [(REG[23h] bits 2-0, REG[22h] bits 7-0) + 1] pixels
HPW = LLINE Pulse Width
= [(REG[20h] bits 6-0)+ 1] pixels
HDPS = Horizontal Display Period Start Position
= [(REG[17h] bits 2-0, REG[16h] bits 7-0) ] pixels
HDP = Horizontal Display Period
= [((REG[14h] bits 6-0) + 1) x 8] pixels
The HDP must be a minimum of 32 pixels and can be increased by multiples of 8.
*Panel Type Bits (REG[10h] bits 2-0) = 010 (Serial 8-bit TFT)
*LLINE Pulse Polarity Bit (REG[24h] bit 7) = 0 (active low)
*LFRAME Polarity Bit (REG[20h] bit 7) = 0 (active low)
In horizontal display period, one cycle out of every four LSHIFT clock is off. In horizontal non-display
period, all LSHIFT clock cycles are on.
So, Horizontal Total (REG[13h] bits 2-0, REG[12h] bits 7-0) = [(no of subpixel clock of horizontal total – no
of subpixel clock of horizontal display period)/4 + (no of subpixel clock of horizontal display period)/3] - 1
LLINE Pulse Start Position (REG[23h] bits 2-0, REG[22h] bits 7-0) = (no of subpixel clock of LLINE Pulse
Start Position)/4 - 1
LLINE Pulse Width (REG[20h] bits 6-0) = (no of subpixel clock of LLINE Pulse Width)/4 – 1
Horizontal Display Period Start Position (REG[17h] bits 2-0, REG[16h] bits 7-0) = (no of subpixel clock of
Horizontal Display Period Start Position)/4 - 1
Horizontal Display Period (REG[14h] bits 6-0) = [(no of subpixel clock of horizontal display period)/3]/8 – 1
The frequency of LSHIFT was different during display and non-display period.
During horizontal display period:
LSHIFT frequency = (¾) * MCLK frequency * (PCLK Frequency Ratio + 1) / (218)
During horizontal non-display period:
LSHIFT frequency = MCLK frequency * (PCLK Frequency Ratio + 1) / (218)
Solomon Systech
Jul 2009
P 26/27
Rev 1.0
SSD1926
Application Note
Panel Type Register
Bit
7
Color STN
Panel
Select
Type
Reset
state
RW
0
REG[10h]
6
Color/Mon
o
Panel
Select
RW
0
Bit 7
5
Panel Data
Width Bit 1
4
Panel Data
Width Bit 0
3
Reserved
2
Panel Type
Bit 2
1
Panel Type
Bit 1
0
Panel Type
Bit 0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Color STN Panel Select
When this bit = 0, non CSTN LCD panel is selected.
When this bit = 1, CSTN LCD panel is selected.
Color/Mono Panel Select
When this bit = 0, monochrome LCD panel is selected.
When this bit = 1, color LCD panel is selected.
Panel Data Width Bits [1:0]
These bits are determined by the data width of the LCD panel. Refer to Table 2-3: Panel Data
Width Selection for the selection.
Bit 6
Bits 5-4
Note : These 2 bits are not effective for Serial TFT panel.
Table 2-3: Panel Data Width Selection
Panel Data Width Bits [1:0]
Passive Panel Data Width
00
01
10
11
4-bit
8-bit
Reserved
Reserved
Bit 3
Active Panel Data Width
(for TFT only)
9-bit
12-bit
18-bit
24-bit
Reserved bit
This bit should be programmed by 0.
Panel Type Bit [2:0]
This bit selects the panel type.
Bits 2-0
Table 2-4: LCD Panel Type Selection
Panel Type Bit[2:0]
000
001
010
011
100
101
110
111
SSD1926
Application Note
Rev 1.0
P 27/28
Jul 2009
Panel Type
STN
TFT
Serial-TFT
Reserved
Smart TFT
Smart CSTN
Smart OLED
Reserved
Solomon Systech
MOD Rate Register
Bit
7
0
6
0
Type
Reset
state
RO
0
RO
0
Bits 5-0
REG[11h]
5
MOD Rate
Bit 5
RW
0
4
MOD Rate
Bit 4
RW
0
3
MOD Rate
Bit 3
RW
0
2
MOD Rate
Bit 2
RW
0
1
MOD Rate
Bit 1
RW
0
0
MOD Rate
Bit 0
RW
0
MOD Rate Bits [5:0]
When these bits are all 0, the MOD output signal (LDEN) toggles every LFRAME.
For any non-zero value n, the MOD output signal (LDEN) toggles every n LLINE.
Note: These bits are for passive LCD panels and REG[340h] = 0 only.
Horizontal Total Register 1
Bit
Type
Reset
state
7
Horizontal
Total Bit 10
RW
0
6
Horizontal
Total Bit 9
RW
0
REG[12h]
5
Horizontal
Total Bit 8
RW
0
4
Horizontal
Total Bit 7
RW
0
3
Horizontal
Total Bit 6
RW
0
2
Horizontal
Total Bit 5
RW
0
2
Horizontal
Total Bit 2
RW
1
Horizontal Total Register 0
0
Horizontal
Total Bit 3
RW
0
REG[13h]
Bit
7
0
6
0
5
0
4
0
3
0
Type
Reset
state
RO
0
RW
0
RW
0
RW
0
RW
0
REG[12h], Bits 6-0
REG[13h], Bits 2-0
1
Horizontal
Total Bit 4
RW
0
1
Horizontal
Total Bit 1
RW
1
0
Horizontal
Total Bit 0
RW
1
Horizontal Total Bits [10:0]
This register is used for both dumb and smart panel interface.
For dumb panel interface, these bits specify the LCD panel Horizontal Total period. The
Horizontal Total is the sum of the Horizontal Display period and the Horizontal Non-Display
period.
The maximum Horizontal Total is 2048 pixels.
Horizontal Total in number of pixels = REG[12h] Bits [7:0] x 8 + REG[13h] Bits [2:0] + 1
Note
(1)
This register must be programmed such that the following condition is fulfilled.
HDPS + HDP < HT
(2)
For panel AC timing and timing parameter definitions, see Section “Display Interface” in
datasheet.
(3)
For smart panel interface (i.e. REG[10h] bit 2 = 1 and REG[250h] bit 5 = 1), REG[12h] will
be used as horizontal number of pixels and REG[13h] = 0x07.
Horizontal width of smart panel = REG[12h] Bits[7:0] x 8 + 8
Solomon Systech
Jul 2009
P 28/29
Rev 1.0
SSD1926
Application Note
Horizontal Display Period Register
Bit
7
0
Type
Reset
state
RO
0
6
Horizontal
Display
Period Bit 6
RW
0
Bit 7
Bits 6-0
5
Horizontal
Display
Period Bit 5
RW
0
REG[14h]
4
Horizontal
Display
Period Bit 4
RW
0
3
Horizontal
Display
Period Bit 3
RW
0
2
Horizontal
Display
Period Bit 2
RW
0
1
Horizontal
Display
Period Bit 1
RW
0
0
Horizontal
Display
Period Bit 0
RW
0
Reserved bit
Horizontal Display Period Bits [6:0]
This register is used for both dumb and smart panel interface.
For dumb panel interface, these bits specify the LCD panel Horizontal Display period, in 8
pixel resolution. The Horizontal Display period should be less than the Horizontal Total to
allow for a sufficient Horizontal Non-Display period.
Horizontal Display Period in number of pixels = (Bits [6:0] + 1) x 8
Note
(1)
Maximum value of REG[14h] ≤ 0x3F when Display Rotate Mode (90° or 270°) is selected.
(2)
For panel AC timing and timing parameter definitions, see Section “Display Interface” in
datasheet.
(3)
For smart panel interface (i.e. REG[10h] bit 2 = 1 and REG[250h] bit 5 = 1), these bits
should be set as same as REG[12h].
Horizontal Display Period Start Position Register 0
Bit
Type
Reset
state
7
Horizontal
Display
Period Start
Position Bit
7
RW
0
6
Horizontal
Display
Period Start
Position Bit
6
RW
0
5
Horizontal
Display
Period Start
Position Bit
5
RW
0
4
Horizontal
Display
Period Start
Position Bit
4
RW
0
REG[16h]
3
Horizontal
Display
Period Start
Position Bit
3
RW
0
2
Horizontal
Display
Period Start
Position Bit
2
RW
0
Horizontal Display Period Start Position Register 1
7
0
6
0
5
0
4
0
3
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
SSD1926
Application Note
0
Horizontal
Display
Period Start
Position Bit
0
RW
0
REG[17h]
Bit
REG[17h] bits1-0,
REG[16h] bits 7-0
1
Horizontal
Display
Period Start
Position Bit
1
RW
0
2
Horizontal
Display
Period Start
Position Bit
10
RO
0
1
Horizontal
Display
Period Start
Position Bit
9
RW
0
0
Horizontal
Display
Period Start
Position Bit
8
RW
0
Horizontal Display Period Start Position Bits [10:0]
These bits specify the Horizontal Display Period Start Position in 1 pixel resolution.
Note
(1)
For panel AC timing and timing parameter definitions, see Section “Display Interface” in
datasheet.
(2)
These bit can not be updated for smart panel interface (REG[250h] bit 5 = 1)
Rev 1.0
P 29/30
Jul 2009
Solomon Systech
Vertical Total Register 0
Bit
Type
Reset
state
7
Vertical
Total Bit 7
RW
0
6
Vertical
Total Bit 6
RW
0
REG[18h]
5
Vertical
Total Bit 5
RW
0
4
Vertical
Total Bit 4
RW
0
3
Vertical
Total Bit 3
RW
0
2
Vertical
Total Bit 2
RW
0
2
Vertical
Total Bit 10
RW
0
Vertical Total Register 1
0
Vertical
Total Bit 0
RW
0
REG[19h]
Bit
7
0
6
0
5
0
4
0
3
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[19h] bits 1-0,
REG[18h] bits 7-0
1
Vertical
Total Bit 1
RW
0
1
Vertical
Total Bit 9
RW
0
0
Vertical
Total Bit 8
RW
0
Vertical Total Bits [10:0]
This register is used for both dumb and smart panel interface.
For dumb panel interface, these bits specify the LCD panel Vertical Total period, in 1 line
resolution. The Vertical Total is the sum of the Vertical Display Period and the Vertical NonDisplay Period.
The maximum Vertical Total is 2048 lines. See “Display Interface” in datasheet.
Vertical Total in number of lines = Bits [10:0]+ 1
Note
(1)
This register must be programmed such that the following condition is fulfilled.
VDPS + VDP < VT
(2)
For panel AC timing and timing parameter definitions, see Section “Display Interface”.
(3)
For smart panel interface (i.e. REG[10h] bit 2 = 1 and REG[250h] bit 5 = 1), these bits will
be used as vertical number of lines in smart panel.
Vertical height of smart panel = REG[19h] 2:0, REG[18h] 7:0 + 1
Vertical Display Period Register 0
Bit
Type
Reset
state
7
Vertical
Display
Period Bit 7
RW
0
Solomon Systech
6
Vertical
Display
Period Bit 6
RW
0
5
Vertical
Display
Period Bit 5
RW
0
REG[1Ch]
4
Vertical
Display
Period Bit 4
RW
0
3
Vertical
Display
Period Bit 3
RW
0
Jul 2009
2
Vertical
Display
Period Bit 2
RW
0
P 30/31
1
Vertical
Display
Period Bit 1
RW
0
Rev 1.0
0
Vertical
Display
Period Bit 0
RW
0
SSD1926
Application Note
Vertical Display Period Register 1
REG[1Dh]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
Ro
0
RO
0
RO
0
RO
0
RO
0
REG[1Dh] bits 1-0,
REG[1Ch] bits 7-0
1
Vertical
Display
Period Bit 9
RW
0
0
Vertical
Display
Period Bit 8
RW
0
Vertical Display Period Bits [9:0]
This register is used for both main and smart panel interface.
For dumb panel interface, these bits specify the LCD panel Vertical Display period, in 1 line
resolution. The Vertical Display period should be less than the Vertical Total to allow for a
sufficient Vertical Non-Display period.
Vertical Display Period in number of lines = Bits [9:0] + 1
Note
(1)
For panel AC timing and timing parameter definitions, see Section “Display Interface” in
datasheet.
(2)
For smart panel interface (i.e. REG[10h] bit 2 = 1 and REG[250h] bit 5 = 1), these bits
should be set as same as REG[19h-18h].
Vertical Display Period Start Position Register 0
Bit
Type
Reset
state
7
Vertical
Display
Period Start
Position Bit
7
RW
0
6
Vertical
Display
Period Start
Position Bit
6
RW
0
5
Vertical
Display
Period Start
Position Bit
5
RW
0
4
Vertical
Display
Period Start
Position Bit
4
RW
0
REG[1Eh]
3
Vertical
Display
Period Start
Position Bit
3
RW
0
2
Vertical
Display
Period Start
Position Bit
2
RW
0
2
Vertical
Display
Start
Position
Period Bit
10
NA
0
Vertical Display Period Start Position Register 1
0
Vertical
Display
Period Start
Position Bit
0
RW
0
REG[1Fh]
Bit
7
0
6
0
5
0
4
0
3
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
REG[1Fh] bits 1-0,
REG[1Eh] bits 7-0
1
Vertical
Display
Period Start
Position Bit
1
RW
0
1
Vertical
Display
Start
Position
Period Bit 9
0
Vertical
Display
Start
Position
Period Bit 8
RW
0
RW
0
Vertical Display Period Start Position Bits [10:0]
These bits specify the Vertical Display Period Start Position in 1 line resolution.
Note
For panel AC timing and timing parameter definitions, see Section “Display Interface” in
datasheet.
SSD1926
Application Note
Rev 1.0
P 31/32
Jul 2009
Solomon Systech
LLINE Pulse Width Register
Bit
Type
Reset
state
7
LLINE
Pulse
Polarity
RW
0
Bit 7
6
LLINE
Pulse
Width Bit 6
RW
0
REG[20h]
5
LLINE
Pulse
Width Bit 5
RW
0
4
LLINE
Pulse
Width Bit 4
RW
0
3
LLINE
Pulse
Width Bit 3
RW
0
2
LLINE
Pulse
Width Bit 2
RW
0
1
LLINE
Pulse
Width Bit 1
RW
0
0
LLINE
Pulse
Width Bit 0
RW
0
LLINE Pulse Polarity
This bit determines the polarity of the horizontal sync signal. The horizontal sync signal is
typically named as LLINE or LP, depending on the panel type.
When this bit = 0, the horizontal sync signal is active low.
When this bit = 1, the horizontal sync signal is active high.
Note
(1)
These bit can not be updated for smart panel interface (REG[250h] bit 5 = 1)
LLINE Pulse Width Bits [6:0]
These bits specify the width of the panel horizontal sync signal, in number of PCLK. The
horizontal sync signal is typically named as LLINE or LP, depending on the panel type.
Bits 6-0
LLINE Pulse Width in PCLK = Bits [6:0] + 1
Note
(1)
These bit can not be updated for smart panel interface (REG[250h] bit 5 = 1)
Note
(1)
For panel AC timing and timing parameter definitions, see Section “Display Interface” in datasheet.
LLINE Pulse Start Sub-pixel Position Register
REG[21h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 7-2
Reserved bits
Bits 1-0
Sub-pixel Position Bits [1:0]
00 :
No sub-pixel delay
01 :
1 sub-pixel clock delay
10 :
2 sub-pixel clock delay
11 :
3 sub-pixel clock delay
1
Sub-pixel
Position Bit
1
RW
0
0
Sub-pixel
Position Bit
0
RW
0
Note
(1)
This register is effective for Serial-TFT panel only.
Solomon Systech
Jul 2009
P 32/33
Rev 1.0
SSD1926
Application Note
LLINE Pulse Start Position Register 0
Bit
Type
Reset
state
7
LLINE
Pulse Start
Position Bit
7
RW
0
6
LLINE
Pulse Start
Position Bit
6
RW
0
5
LLINE
Pulse Start
Position Bit
5
RW
0
REG[22h]
4
LLINE
Pulse Start
Position Bit
4
RW
0
3
LLINE
Pulse Start
Position Bit
3
RW
0
2
LLINE
Pulse Start
Position Bit
2
RW
0
2
LLINE
Pulse Start
Position Bit
10
NA
0
1
LLINE
Pulse Start
Position Bit
1
RW
0
LLINE Pulse Start Position Register 1
REG[23h]
Bit
7
0
6
0
5
0
4
0
3
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
REG[23h] bits 1-0,
REG[22h] bits 7-0
0
LLINE
Pulse Start
Position Bit
0
RW
0
1
LLINE
Pulse Start
Position Bit
9
RW
0
0
LLINE
Pulse Start
Position Bit
8
RW
0
LLINE Pulse Start Position Bits [10:0]
These bits specify the start position of the horizontal sync signal, in number of PCLK.
LLINE Pulses Start Position in PCLK = Bits [10:0] + 1
Note
(1)
These bit can not be updated for smart panel interface (REG[250h] bit 5 = 1)
Note
(1)
For panel AC timing and timing parameter definitions, see Section “Display Interface” in datasheet”.
LFRAME Pulse Width Register
Bit
Type
Reset
state
7
LFRAME
Pulse
Polarity
RW
0
Bit 7
REG[24h]
6
0
5
0
4
0
3
0
NA
0
NA
0
NA
0
NA
0
2
LFRAME
Pulse
Width Bit 2
RW
0
1
LFRAME
Pulse
Width Bit 1
RW
0
0
LFRAME
Pulse
Width Bit 0
RW
0
LFRAME Pulse Polarity
This bit selects the polarity of the vertical sync signal. The vertical sync signal is typically
named as LFRAME or SPS, depending on the panel type.
When this bit = 0, the vertical sync signal is active low.
When this bit = 1, the vertical sync signal is active high.
Note
(1)
These bit can not be updated for smart panel interface (REG[250h] bit 5 = 1)
LFRAME Pulse Width Bits [2:0]
These bits specify the width of the panel vertical sync signal, in 1 line resolution. The vertical
sync signal is typically named as LFRAME or SPS, depending on the panel type.
Bits 2-0
LFRAME Pulse Width in number of pixels = (Bits [2:0] + 1) x Horizontal Total + offset
Note
(1)
These bit can not be updated for smart panel interface (REG[250h] bit 5 = 1)
Note
(1)
For panel AC timing and timing parameter definitions, see Section “Display Interface” in datasheet.
SSD1926
Application Note
Rev 1.0
P 33/34
Jul 2009
Solomon Systech
LFRAME Pulse Start Position Register 0
Bit
Type
Reset
state
7
LFRAME
Pulse Start
Position Bit
7
RW
0
6
LFRAME
Pulse Start
Position Bit
6
RW
0
5
LFRAME
Pulse Start
Position Bit
5
RW
0
REG[26h]
4
LFRAME
Pulse Start
Position Bit
4
RW
0
3
LFRAME
Pulse Start
Position Bit
3
RW
0
2
LFRAME
Pulse Start
Position Bit
2
RW
0
2
LFRAME
Pulse Start
Position Bit
10
NA
0
1
LFRAME
Pulse Start
Position Bit
1
RW
0
LFRAME Pulse Start Position register 1
REG[27h]
Bit
7
0
6
0
5
0
4
0
3
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
REG[27h] bits 1-0
REG[26h] bits 7-0
0
LFRAME
Pulse Start
Position Bit
0
RW
0
1
LFRAME
Pulse Start
Position Bit
9
RW
0
0
LFRAME
Pulse Start
Position Bit
8
RW
0
LFRAME Pulse Start Position Bits [10:0]
These bits specify the start position of the vertical sync signal, in 1 line resolution.
LFRAME Pulse Start Position in number of pixels = (Bits [10:0]) x Horizontal Total + offset
Note
(1)
These bit can not be updated for smart panel interface (REG[250h] bit 5 = 1)
Note
(1)
For panel AC timing and timing parameter definitions, see Section “Display Interface” in datasheet.
Display Post-processing Saturation Control Register
Bit
Type
Reset
state
7
Display
Post-proc
Saturation
Bit 7
NA
0
Bits 7-0
6
Display
Post-proc
Saturation
Bit 6
NA
1
5
Display
Post-proc
Saturation
Bit 5
NA
0
4
Display
Post-proc
Saturation
Bit 4
NA
0
REG[2Ch]
3
Display
Post-proc
Saturation
Bit 3
NA
0
2
Display
Post-proc
Saturation
Bit 2
NA
0
1
Display
Post-proc
Saturation
Bit 1
RW
0
0
Display
Post-proc
Saturation
Bit 0
RW
0
Display Post-processing Saturation Control [7:0]
These bits control the saturation of the display.
Table 2-5: The setting for display post-processing saturation
Control Bits [7:0]
0x00
0x01
…
0x40
…
0x7F
Solomon Systech
Saturation Control
Gain = 0
Gain = 1/64
(Default) Gain = 1
Gain = 127/64
Jul 2009
P 34/35
Rev 1.0
SSD1926
Application Note
Display Post-processing Brightness Control Register
Bit
Type
Reset
state
7
Display
Post-proc
Brightness
Bit 7
NA
1
6
Display
Post-proc
Brightness
Bit 6
NA
0
Bits 7-0
5
Display
Post-proc
Brightness
Bit 5
NA
0
4
Display
Post-proc
Brightness
Bit 4
NA
0
REG[2Dh]
3
Display
Post-proc
Brightness
Bit 3
NA
0
2
Display
Post-proc
Brightness
Bit 2
NA
0
1
Display
Post-proc
Brightness
Bit 1
RW
0
0
Display
Post-proc
Brightness
Bit 0
RW
0
Display Post-processing Brightness Control [7:0]
These bits control the brightness of the display.
Table 2-6: The setting for Display Post-processing brightness
Control Bits [7:0]
0x00
…
0x80
…
0xFF
Brightness Control
Value = 0
(Default) Value = 128
Value = 255
Display Post-processing Contrast Control Register
Bit
Type
Reset
state
7
Display
Post-proc
Contrast Bit
7
NA
0
6
Display
Post-proc
Contrast Bit
6
NA
1
Bits 7-0
5
Display
Post-proc
Contrast Bit
5
NA
0
4
Display
Post-proc
Contrast Bit
4
NA
0
REG[2Eh]
3
Display
Post-proc
Contrast Bit
3
NA
0
2
Display
Post-proc
Contrast Bit
2
NA
0
1
Display
Post-proc
Contrast Bit
1
RW
0
0
Display
Post-proc
Contrast Bit
0
RW
0
Display Post-processing Contrast Control [7:0]
These bits control the contrast of the display.
Table 2-7: The setting for Display Post-processing contrast
Control Bits [7:0]
0x00
0x01
…
0x40
…
0x7F
SSD1926
Application Note
Rev 1.0
P 35/36
Jul 2009
Contrast Control
Gain = 0
Gain = 1/64
(Default) Gain = 1
Gain = 127/64
Solomon Systech
Display Post-processing Control Register
REG[2Fh]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Type
Reset
state
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 7-1
Reserved bits
These bits should be programmed by 0.
Display Post-processing Enable
When this bit = 1, display post-processing is enabled.
When this bit = 0, display post-processing is disabled.
Bit 0
LFRAME Pulse Start Offset Register 0
Bit
Type
Reset
state
0
Display
Post-proc
Enable
RW
0
7
LFRAME
Start Offset
Bit 7
RW
0
6
LFRAME
Start Offset
Bit 6
RW
0
5
LFRAME
Start Offset
Bit 5
RW
0
REG[30h]
4
LFRAME
Start Offset
Bit 4
RW
0
3
LFRAME
Start Offset
Bit 3
RW
0
2
LFRAME
Start Offset
Bit 2
RW
0
2
LFRAME
Start Offset
Bit 10
NA
0
1
LFRAME
Start Offset
Bit 1
RW
0
LFRAME Pulse Start Offset Register 1
REG[31h]
Bit
7
0
6
0
5
0
4
0
3
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
REG[31h] bits 2-0
REG[30h] bits 7-0
0
LFRAME
Start Offset
Bit 0
RW
0
1
LFRAME
Start Offset
Bit 9
RW
0
0
LFRAME
Start Offset
Bit 8
RW
0
LFRAME Pulse Start Offset [10:0]
These bits specify the start offset of the vertical sync signal within a line, in 1 pixel resolution.
Note
For panel AC timing and timing parameter definitions, see Section “Display Interface” in datasheet.
(1)
LFRAME Pulse Stop Offset Register 0
Bit
Type
Reset
state
7
LFRAME
Stop Offset
Bit 7
RW
0
Solomon Systech
6
LFRAME
Stop Offset
Bit 6
RW
0
5
LFRAME
Stop Offset
Bit 5
RW
0
4
LFRAME
Stop Offset
Bit 4
RW
0
REG[34h]
3
LFRAME
Stop Offset
Bit 3
RW
0
Jul 2009
2
LFRAME
Stop Offset
Bit 2
RW
0
P 36/37
1
LFRAME
Stop Offset
Bit 1
RW
0
Rev 1.0
0
LFRAME
Stop Offset
Bit 0
RW
0
SSD1926
Application Note
LFRAME Pulse Stop Offset Register 1
REG[35h]
Bit
7
0
6
0
5
0
4
0
3
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
REG[35h] bits 2-0
REG[34h] bits 7-0
2
LFRAME
Stop Offset
Bit 10
NA
0
1
LFRAME
Stop Offset
Bit 9
RW
0
0
LFRAME
Stop Offset
Bit 8
RW
0
LFRAME Pulse Stop Offset [10:0]
These bits specify the stop offset of the vertical sync signal within a line, in 1 pixel resolution.
Note
For panel AC timing and timing parameter definitions, see Section “Display Interface” in datasheet.
(1)
LSHIFT Polarity Register
REG[38h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Type
Reset
state
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 7-1
0
LSHIFT
Polarity
swap
RW
0
Reserved bits
These bits should be programmed by 0.
LSHIFT Polarity Swap
When this bit = 1, LSHIFT signal is falling trigger.
When this bit = 0, LSHIFT signal is rising trigger.
Bit 0
Note
(1)
Bit 0 is effective for TFT panels only (REG[10h] bit 0 = 1).
RGB sequence Register
Bit
7
0
6
0
Type
Reset
state
RW
0
RW
0
Bits 7-6
Bits 5-3
Bits 2-0
REG[42h]
5
Even line
RGB
sequence Bit
2
RW
0
4
Even line
RGB
sequence Bit
1
RW
0
3
Even line
RGB
sequence Bit
0
RW
0
2
Odd line
RGB
sequence Bit
2
RW
0
1
Odd line
RGB
sequence Bit
1
RW
0
0
Odd line
RGB
sequence Bit
0
RW
0
Reserved bits
Even line RGB sequence Bits [2:0]
Odd line RGB sequence Bits [2:0]
The first display line is the odd line.
Note
This register is effective for Serial-TFT panel only. The first line is the even line.
Table 2-8: The RGB sequence for Serial-TFT interface
RGB sequence bits [2:0]
000
001
010
011
100
101
11x
SSD1926
Application Note
Rev 1.0
P 37/38
Jul 2009
RGB output sequence
RGB
RBG
GRB
GBR
BRG
BGR
Reserved
Solomon Systech
MOD Time Period Register 0
Bit
Type
Reset
state
REG[340h]
7
6
5
4
3
2
1
0
0
0
0
0
RO
0
RO
0
RO
0
RO
0
MOD Time
Period
Bit 3
RW
0
MOD Time
Period
Bit 2
RW
0
MOD Time
Period
Bit 1
RW
0
MOD Time
Period
Bit 0
RW
0
REG[340h] bits 3-0
MOD Period position Register [3:0]
This register define the period of MOD output signal, in terms of display line.
0 : Disable and MOD output will follow the setting of REG[11h]
n : MOD polarity will repeat every n frames with the patterns defined in REG[342-343h]. The
setting of REG[11h] will be ignored.
Note: These bits are for passive LCD panels only.
MOD Time Pattern Register 0
Bit
Type
Reset
state
7
MOD Time
Pattern
Bit 7
RW
0
6
MOD Time
Pattern
Bit 6
RW
0
5
MOD Time
Pattern
Bit 5
RW
0
REG[342h]
4
MOD Time
Pattern
Bit 4
RW
0
3
MOD Time
Pattern
Bit 3
RW
0
2
MOD Time
Pattern
Bit 2
RW
0
4
MOD Time
Pattern
Bit 12
RW
0
3
MOD Time
Pattern
Bit 11
RW
0
2
MOD Time
Pattern
Bit 10
RW
0
MOD Time Pattern Register 1
Bit
Type
Reset
state
7
MOD Time
Pattern
Bit 15
RW
0
REG[343h] bits 7-0,
REG[342h] bits 7-0
6
MOD Time
Pattern
Bit 14
RW
0
5
MOD Time
Pattern
Bit 13
RW
0
1
MOD Time
Pattern
Bit 1
RW
0
0
MOD Time
Pattern
Bit 0
RW
0
REG[343h]
1
MOD Time
Pattern
Bit 9
RW
0
0
MOD Time
Pattern
Bit 8
RW
0
MOD Time pattern register [15:0]
This register defines MOD pattern.
1 : Positive polarity
0 : Negative polarity
For example,
REG[340h] = 0x4
REG[343-342h] = 0x0001 (i.e. b0001)
Then the frame #1 is positive polarity, frame #2-4 are negative polarity. And such pattern will
be repeated for every 4 frames.
Note
(1)
These bits are for passive LCD panels only.
Solomon Systech
Jul 2009
P 38/39
Rev 1.0
SSD1926
Application Note
LSHIFT signal start position Register 0
Bit
Type
Reset
state
7
LSHIFT
start
Bit 7
RW
0
6
LSHIFT
start
Bit 6
RW
0
5
LSHIFT
start
Bit 5
RW
0
REG[350h]
4
LSHIFT
start
Bit 4
RW
0
3
LSHIFT
start
Bit 3
RW
0
2
LSHIFT
start
Bit 2
RW
0
LSHIFT signal start position Register1
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
2
LSHIFT
start
Bit 10
RO
0
4
LCD shift
end
Bit 4
RW
0
3
LCD shift
end
Bit 3
RW
0
2
LCD shift
end
Bit 2
RW
0
2
LCD shift
end
Bit 10
RO
0
LSHIFT signal end position Register 0
Type
Reset
state
7
LCD shift
end
Bit 7
RW
0
6
LCD shift
end
Bit 6
RW
0
5
LCD shift
end
Bit 5
RW
0
1
LSHIFT
start
Bit 9
RW
0
0
LSHIFT
start
Bit 8
RW
0
REG[354h]
LSHIFT signal end position Register1
1
LCD shift
end
Bit 1
RW
0
0
LCD shift
end
Bit 0
RW
0
REG[355h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[351h] bits 1-0,
REG[350h] bits 7-0
REG[355h] bits 1-0,
REG[354h] bits 7-0
0
LSHIFT
start
Bit 0
RW
0
REG[351h]
Bit
Bit
1
LSHIFT
start
Bit 1
RW
0
1
LCD shift
end
Bit 9
RW
0
0
LCD shift
end
Bit 8
RW
0
LSHIFT signal start position Register [10:0]
These bits define the start position of LSHIFT within a line for active lcd signal.
LSHIFT signal end position Register [10:0]
These bit defines the end position of LSHIFT within a line for active lcd signal.
If REG[351-350h] and REG[355-354h] are 0, LSHIFT will be enabled on the time (i.e. both
display and non-display period).
If REG[351-350h] and REG[355-354h] are not equal to 0, LSHIFT will be enabled within the
range defined by start and end position within each line.
The end position > The start position
For example,
Horizontal display period = 16
Horizontal total = 24
Horizontal period start = 4
LSHIFT start = 3 and LSHIFT end = 20
Then the LSHIFT will enabled between horizontal position pixel 3 and 20 within a line.
SSD1926
Application Note
Rev 1.0
P 39/40
Jul 2009
Solomon Systech
2.6
Smart Panel Configuration Registers
To operate with smart panel module, first is to enable the smart display (REG[250h] bit 5 = 1), then select the
operation mode (Write Through or Auto Reflesh Mode), panel type and panel interface (REG[260h] &
REG[10h]). The maximum resolution for main smart panel is 2048 x 2048.
Then next step is to configure the type of data to be transferred for Write Through Mode. Detail will be
covered in section 2.6.1.
Data transfer is initiated by writing data to REG[26Ch] and REG[26Dh] for Write Through Mode while by
setting REG[A0h] to enable the Auto Reflesh Mode of smart panel interface.
2.6.1 Write Through Mode
There are three types of data for Write Through Mode:
- Display pixel data
- Command
- Command argument
Write Through Mode will send either pixel display data or command or command argument to the panel
driver at each time by issuing an enable pulse together with the 16-bit data or command.
Table 2-9: Data type for parallel interface of all panel types
Data Type
Data / Command Selection
REG[26Eh] Bit 0
Command
Command Argument
Pixel Data
Data / Argument
Selection
REG[26Eh] Bit 7
x
0
1
0
1
1
2.6.1.1 Input Format
MCU data for Write Through mode are stored in REG[26Ch-26Dh]. Input data format from MCU in Write
Through Mode as Table 2-10: Input data format for Write Through Mode.
Table 2-10: Input data format for Write Through Mode
Input Data Type
Command/Argument (8 bit)
Pixel Data (16bpp)
Smart Display Input Data [15:0]
(REG[26Dh-26Ch])
XXXXXXXXDDDDDDDD
RRRRRGGGGGGBBBBB
2.6.1.2 Output Format
Considering parallel output interface, only TFT will support 8-bit and 9-bit interface while CSTN and OLED
will only have 8-bit interface (LCD_DATA8 will be 0). Refer to Table 2-11 for output data format of different
panel interface.
Solomon Systech
Jul 2009
P 40/41
Rev 1.0
SSD1926
Application Note
Table 2-11: Data output format for display pixel in Parallel interface
Panel Type
TFT
Parallel Interface
Width
REG[260h] Bit 5
0
CSTN
OLED
Byte per pixel
REG[261h] Bits 1-0
Pixel Data
Description
xx
2 transfers
per pixel
(18bpp)
2 transfers
per
pixel(16bpp)
3 transfers
per pixel
(18bpp)
1 transfer per
pixel (8bpp)
3 transfers
per 2 pixels
(12bpp)
2 transfers
per pixel
(16bpp)
3 transfers
per pixel
(18bpp)
1 transfer per
pixel (8bpp)
3 transfers
per 2 pixels
(12bpp)
2 transfers
per pixel
(16bpp)
3 transfers
per pixel
(18bpp)
1
10
1
11
x
00
x
01
x
10
x
11
x
00
x
01
x
10
x
11
Parallel Pixel Data
Format
(LCD_DATA[8:0])
RRRRRRGGG
GGGBBBBBB
RRRRRGGG0
GGGBBBBB0
RRRRRR000
GGGGGG000
BBBBBB000
0RRRGGGBB
0RRRRGGGG
0BBBBRRRR
0GGGGBBBB
0RRRRRGGG
0GGGBBBBB
0RRRRRR00
0GGGGGG00
0BBBBBB00
0RRRGGGBB
0RRRRGGGG
0BBBBRRRR
0GGGGBBBB
0RRRRRGGG
0GGGBBBBB
000RRRRRR
000GGGGGG
000BBBBBB
Table 2-12: Data output format for 4-wire serial interface (REG[260h] Bit 6= 1)
Panel
Type
TFT/CSTN
OLED
Output Data Type
Command/Argument
Pixel (8bpp)
Pixel (12bpp)
Pixel (16bpp)
Pixel (18bpp)
Command/Argument
Pixel (8bpp)
Pixel (12bpp)
Pixel (16bpp)
Pixel (18bpp)
SSD1926
Application Note
Rev 1.0
Byte per pixel
REG[261h] Bits 1-0
xx
00
01
10
11
xx
00
01
10
11
P 41/42
Jul 2009
Data Length
per burst
8 bit
8 bit
8 bit, 16 bit
16 bit
24 bit
8 bit
8 bit
8 bit, 16 bit
16 bit
24 bit
Serial Output Format (SDA)
DDDDDDDD
RRRGGGBB
RRRRGGGG, BBBBRRRRGGGGBBBB
RRRRRGGGGGGBBBBB
RRRRRR00GGGGGG00BBBBBB00
DDDDDDDD
RRRGGGBB
RRRRGGGG BBBBRRRRGGGGBBBB
RRRRRGGGGGGBBBBB
00RRRRRR00GGGGGG00BBBBBB
Solomon Systech
Table 2-13: Data output format for 3-wire serial interface (REG[260h] Bit 6= 0)
Panel Type
TFT/CSTN
OLED
Output Data
Type
Command
Argument
Pixel (8bpp)
Pixel (12bpp)
Pixel (16bpp)
Pixel (18bpp)
Command
Argument
Pixel (8bpp)
Pixel (12bpp)
Pixel (16bpp)
Pixel (18bpp)
Byte per pixel
REG[261h] Bits 1-0
xx
xx
00
01
10
11
xx
xx
00
01
10
11
Data Length
per burst
9 bit
9 bit
9 bit
9 bit, 18 bit
18 bit
27 bit
9 bit
9 bit
9 bit
9 bit, 18 bit
18 bit
27 bit
Serial Output Format (SDA)
0DDDDDDDD
1DDDDDDDD
1RRRGGGBB
1RRRRGGGG, 1BBBBRRRR1GGGGBBBB
1RRRRRGGG1GGGBBBBB
1RRRRRR001GGGGGG001BBBBBB00
0DDDDDDDD
1DDDDDDDD
1RRRGGGBB
1RRRRGGGG 1BBBBRRRR1GGGGBBBB
1RRRRRGGG1GGGBBBBB
100RRRRRR100GGGGGG100BBBBBB
2.6.1.3 Auto Refresh Mode
Auto Refresh Mode will accept 32-bit (32 bits per pixel or 16 bits per pixel) display data from display
memory and transfer them to panel driver continuously.
There is only display pixel data transfer (no command or argument transfer) for Auto Refresh Mode. So there
is no need to configure the data type.
Before transfer the pixel data to smart panel, it should configure the panel parameter with REG[12h] REG[13h], REG[18h]- REG[19h], REG[74h]- REG[76h], REG[78h]- REG[79h].
The data input is set according to the format below in memory:
Table 2-14: Data input format for Auto Refresh Mode
Bit per pixel
REG[70h] Bits 2:0
100 (16 bit per pixel)
101 (32 bit per pixel)
Data [31:0]
RRRRRGGGGGGBBBBBRRRRRGGGGGGBBBBB (2 pixels)
RRRRRRRRGGGGGGGGBBBBBBBBXXXXXXXX (1 pixel)
The output data format is as same as the output pixel data format in Write Through Mode.
2.6.1.4 Output Interface Timing
Table 2-15: Output Timing for 6800 Parallel interface
Symbol
tcycle
tCSL
tCSH
tAS
tAH
tDS
tDH
Solomon Systech
Parameter
Clock Cycle Time (write cycle) (note2)
Chip Select Low Width (note3)
Chip Select High Width (note4)
Address Setup Time
Address Hold Time
Data Setup Time (note5)
Data Hold Time (note6)
Min
2
1
3
1
3
Typ
1
1
-
Jul 2009
Max
36
16
20
16
20
P 42/43
Unit
Ts (note1)
Ts
Ts
Ts
Ts
Ts
Ts
Rev 1.0
SSD1926
Application Note
D/C
tAS
tAH
R/W
CS
tcycle
tCSL
tCSH
E
tDHW
tDSW
D0~D8
Valid Data
Figure 2-16: 6800 Timing Diagram
Note
(1)
Ts = 1/(MCLK frequency / 2(REG[252h] bit 2-0))
(2)
tcycle = tCSL + tCSH
(3)
tCSL = REG [270h] bit 3-0 + 1
(4)
tCSH = REG [271h] bit 3-0 + 1 + t during a burst or
tCSH = REG [271h] bit 3-0 + 1 + t*2 at the end of the burst, t = 2
(5)
tDSW = tCSL
(6)
tDHW = tCSH
Table 2-16: Output Timing for 8080 Parallel interface
Symbol
tcycle
tCSL
tCSH
tAS
tAH
tDSW
tDHW
SSD1926
Application Note
Parameter
Clock Cycle Time (write cycle) (note2)
Control Pulse Low Width (note3)
Control Pulse High Width (note4)
Address Setup Time
Address Hold Time
Data Setup Time (note5)
Data Hold Time (note6)
Rev 1.0
P 43/44
Jul 2009
Min
2
1
3
1
3
Typ
1
1
-
Max
36
16
20
16
20
Unit
Ts (note1)
Ts
Ts
Ts
Ts
Ts
Ts
Solomon Systech
D/C
tAH
tAS
CS
tcycl
tCSH
tCSL
WR
RD
tDSW
D0~D8
tDHW
Valid Data
Figure 2-17: 8080 Timing Diagram
Note
Ts = 1/(MCLK frequency / 2(REG[252h] bit 2-0))
(2)
tcycle = tCSL + tCSH
(3)
tCSL = REG [270h] bit 3-0 + 1
(4)
tCSH = REG [271h] bit 3-0 + 1 + t during a burst or
tCSH = REG [271h] bit 3-0 + 1 + t*2 at the end of the burst, t = 2
(5)
tDSW = tCSL
(6)
tDHW = tCSH
(1)
Table 2-17: Output Timing for Serial interface
Symbol
tcycle
tCLKL
tCLKH
tCSS
tCSH
tDSW
tDHW
Solomon Systech
Parameter
Clock Cycle Time (write cycle) (note2)
SCK Low Width (note3)
SCK High Width (note4)
Chip Select Setup Time (note5)
Chip Select Hold Time (note6)
Data Setup Time (note7)
Data Hold Time (note8)
Min
2
1
1
2
2
1
1
Typ
-
Jul 2009
Max
32
16
16
17
17
16
16
P 44/45
Unit
Ts (note1)
Ts
Ts
Ts
Ts
Ts
Ts
Rev 1.0
SSD1926
Application Note
D/C
CS
tCSH
tCSS
tcycle
tCLKL
SCK (D6)
tCLKH
tDHW
tDSW Valid Data
SDA(D7)
Figure 2-18: 4 Wires Timing Diagram
CS
tCSS
tcycle
tCLKL
SCK (D6)
tCLKH
tDHW
tDSW D/C
SDA(D7)
Valid Data
Figure 2-19: 3 Wires Timing Diagram
Note
(1)
Ts = 1/(MCLK frequency / 2(REG[252h] bit 2-0))
(2)
tcycle = tCLKL + tCLKH
(3)
tCLKL = REG [263h] bit 3-0 + 1
(4)
tCLKH = REG [263h] bit 3-0 + 1
(5)
tCSS = REG [270h] bit 3-0 + 2
(6)
tCSH = REG [271h] bit 3-0 + 2
(7)
tDSW = tCLKL
(8)
tDHW = tCLKH
SSD1926
Application Note
Rev 1.0
P 45/46
Jul 2009
Solomon Systech
Table 2-18: Register for smart panel interface
Register Description
Display reset
Display Enable
Smart Select Enable
Display mode [1] (YUV/RGB)
Display mode [0] (32/16 bpp)
Divide input clock source Ration [2:0]
Display horizontal panel size [7:0]
Display vertical panel size [7:0]
Display Operation Mode Selection
Serial Input Interface Width
Parallel Input Interface Width
Parallel/Serial Output Interface Selection [1:0]
Panel Type Selection [1:0]
Byte per pixel Bit [1:0]
Serial Clock divide ratio [3:0]
Hold count1 Bit [3:0]
Hold count2 Bit [3:0]
Display CSC Mode
Display Y Offset Registers [7:0]
Display CB Offset Registers [7:0]
Display CR Offset Registers [7:0]
Display Write Through Mode input data bit [15:8]
Display Write Through Mode input data bit [7:0]
Pixel data/Argument Selection
Data/Command Selection
Window Display Start Address Bit [7:0]
Window Display Start Address Bit [15:8]
Window Display Start Address Bit [16]
Window Line Address Offset Bit [7:0]
Window Line Address Offset Bit [9:8]
Display ready
Smart Display
250h[7]
A0h[0]
250h[5]
1A4h[7:6]
70h[2:0](1)
252h[2:0]
13h[2:0] -12h[7:0]
19h[2:0] -18h[7:0]
260h[7]
260h[6]
260h[5]
260h[3:2]
10h[2:0](2)
261h[1:0]
263h[3:0]
270h[3:0]
271h[3:0]
1A8h[7]
1A9h[7:0]
1AAh[7:0]
1ABh[7:0]
26Ch[7:0]
26Dh[7:0]
26Eh[7]
26Eh[0]
74h[7:0]
75h[7:0]
76h[0]
78h[7:0]
79h[1:0]
27Dh[0]
Note
(1)
For Smart panel interface, 1/2/4/8/16/32 bit per pixel will be supported, 1/2/4/8 bpp will use lookup table.
(2)
REG[10h] bit 2 should be set to 1 to enable Smart panel interface.
Smart Display Mode Register
Bit
Type
Reset
state
7
Smart
Display
reset
RW
0
REG [250h] Bit 7
6
Reserved
RW
0
5
Smart
Select
Enable
RW
0
REG[250h]
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
RO
0
RO
0
RO
0
RW
0
RW
0
Smart Display Reset
1 : Reset
0 : Normal
0 -> 1 : transmission stop immediately
1 -> 0 : start transmission from beginning of display frame
This bit should be set to 0 before smart panel command send.
Solomon Systech
Jul 2009
P 46/47
Rev 1.0
SSD1926
Application Note
REG [250h] Bit 6
Reserved bits
These bits should be programmed by 0.
REG [250h] Bit 5
Smart Enable
1: Enable
0 : Disable
Reserved bits
These bits should be programmed by 0.
REG [250h] Bits 4-0
Clock Divide Register
REG[252h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG [252h] Bits 7-3
2
Divide
input clock
source
Ratio Bit 2
RW
0
1
Divide
input clock
source
Ratio Bit 1
RW
0
0
Divide
input clock
source
Ratio Bit 0
RW
0
Reserved bits
These bits should be programmed by 0.
Divide input clock source ratio register [2:0]
This register is used for both main and smart panel interface.
REG [252h] Bits 2-0
Sub_CLK frequency = MCLK frequency / 2REG[252h] bit 2:0
000 : MCLK divide by 1
001 : MCLK divide by 2
010 : MCLK divide by 4
011 : MCLK divide by 8
100 : MCLK divide by 16
101 : MCLK divide by 32
11x : reserved
Smart Display Control Register
Bit
Type
Reset
state
7
Smart panel
Operation
Mode
Selection
RW
0
REG[260h]
6
Serial
interface
Width
5
Parallel
Interface
Width
4
Reserved
RW
0
RW
0
RO
0
3
Output
Interface
Selection
Bit 1
RW
0
2
Output
Interface
Selection
Bit 0
RW
0
1
Reserved
0
Reserved
RW
0
RW
0
This register is used for both main and smart panel interface.
REG [260h] Bit 7
Smart panel Operation Mode Selection register
1 : Write-Through Mode
0 : Auto-Refresh Mode
0 -> 1 : Stop immediately
1 -> 0 : continue
Serial interface Width
Define the width of serial interface mode
1 : 4 wire serial interface
0 : 3 wire serial interface
REG [260h] Bit 6
SSD1926
Application Note
Rev 1.0
P 47/48
Jul 2009
Solomon Systech
REG [260h] Bit 5
REG [260h] Bit 4
REG [260h] Bits 3-2
REG [260h] Bits 1-0
Parallel Interface width
Define the width of parallel interface for TFT
1 : 8-bit parallel interface
0 : 9-bit parallel interface
Note
(1)
This bit is effective for 6800/8080 parallel TFT interface only
Reserved bit
This bit should be programmed by 0
Output Interface Selection bits [1:0]
00 : 6800 parallel interface
01 : 8080 parallel interface
10 : serial interface
11 : reserved
Reserved bit
This bit should be programmed by 0
Display Byte Per Pixel Register
REG[261h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
3
Serial
Clock
divide ratio
Bit 3
RW
0
2
Serial
Clock
divide ratio
Bit 2
RW
0
Bit 4
1
Byte per
pixel Bit 1
RW
0
0
Byte per
pixel Bit 0
RW
0
Byte Per Pixel register [1:0]
00 : 8 bits per pixel output color resolution
01 : 12 bits per pixel output color resolution
10 :16 bits per pixel output color resolution
11 : 18 bits per pixel output color resolution
Serial Clock divide Register
REG[263h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
Bits 7-4
Bits 3-0
1
Serial
Clock
divide ratio
Bit 1
RW
0
0
Serial
Clock
divide ratio
Bit 0
RW
0
Reserved bits
These bits should be programmed by 0.
Serial Clock divide register [3:0]
This register is used for both main and smart panel interface.
SCK frequency = Sub_CLK frequency / (REG[263h] * 2 +2)
0000 : Sub_CLK divide by 2
0001 : Sub_CLK divide by 4
0010 : Sub_CLK divide by 6
0011 : Sub_CLK divide by 8
…
1101 : Sub_CLK divide by 28
1110 : Sub_CLK divide by 30
1111 : Sub_CLK divide by 32
Solomon Systech
Jul 2009
P 48/49
Rev 1.0
SSD1926
Application Note
SCK
(s+1) Sub_CLK (s+1) Sub_CLK
Note
(1)
(2)
Sub_CLK refer to REG[252h] bits 2-0
s : Serial clock divide value, REG[263h] bits 3-0
Hold count for Count 1 Register
REG[270h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
Bits 7-4
Reserved bits
Bits 3-0
Hold count register [3:0]
3
Hold count
2 Bit 3
RW
0
2
Hold count
2 Bit 2
RW
0
1
Hold count
2 Bit 1
RW
0
0
Hold count
2 Bit 0
RW
0
If 6800 interface, Hold count for E high register [3:0]
E will hold high for 1-16 extra clock cycles
If 8080 interface, Hold count for WR low register [3:0]
WR will hold low for 1-16 extra clock cycles
If SPI interface, CS to SCK cycle count register [3:0]
2-17 extra clock cycles for CS hold low before SCK start
Smart Display Hold Count 2 Register
REG[271h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
Bits 7-4
Reserved bits
Bits 3-0
Hold count register [3:0]
3
Hold count
1 Bit 3
RW
0
2
Hold count
1 Bit 2
RW
0
1
Hold 1 Bit
1
RW
0
0
Hold 1Bit 0
RW
0
If 6800 interface, Hold count for E low register [3:0]
E will hold low for 3-20 extra clock cycles
If 8080 interface, Hold count for WR high register [3:0]
WR will hold high for 3-20 extra clock cycles
If SPI interface, SCK to CS cycle count register [3:0]
2-17 extra clock cycles for SCK hold high before CS return
SSD1926
Application Note
Rev 1.0
P 49/50
Jul 2009
Solomon Systech
For 6800 interface
E
During retrieval of
internal buffer
CS
(t + h2 + 1) Sub_CLK
(h1 + 1) Sub_CLK (t*2 + h2 + 1) Sub_CLK
Note :
t=2
Sub_CLK refer to REG[252] bits 2-0
h1 : Hold count for Count 1, REG[270h] bits 3:0
h2 : Hold count for Count 2, REG[271h] bits 3:0
For 8080 interface
WR
CS
During retrieval of
internal buffer
(t + h2 + 1) Sub_CLK (h1 + 1) Sub_CLK (t*2 + h2 + 1) Sub_CLK
Note :
t=2
Sub_CLK refer to REG[252] bits 2-0
h1 : Hold count for Count 1, REG[270h] bits 3:0
h2 : Hold count for Count 2, REG[271h] bits 3:0
For SPI interface
CS
SCK
End of each
serial burst
Start of each
serial burst
(h2 + 2) Sub_CLK
(h1 + 2) Sub_CLK
Note :
Sub_CLK refer to REG[252] bits 2-0
h1 : Hold count for Count 1, REG[270h] bits 3:0
h2 : Hold count for Count 2, REG[271h] bits 3:0
Solomon Systech
Jul 2009
P 50/51
Rev 1.0
SSD1926
Application Note
Smart Display Write Through Mode input data Register 0
Bit
7
Smart
Display
Write
Through
Mode input
data Bit 7
6
Smart
Display
Write
Through
Mode input
data Bit 6
Type
Reset
state
RW
0
RW
0
5
Smart
Display
Write
Through
Mode input
data
Bit 5
RW
0
REG[26Ch]
4
Smart
Display
Write
Through
Mode input
data Bit 4
3
Smart
Display
Write
Through
Mode input
data Bit 3
2
Smart
Display
Write
Through
Mode input
data Bit 2
1
Smart
Display
Write
Through
Mode input
data Bit 1
0
Smart
Display
Write
Through
Mode input
data Bit 0
RW
0
RW
0
RW
0
RW
0
RW
0
Smart Display Write Through Mode input data Register 1
Bit
7
Smart
Display
Write
Through
Mode input
data Bit 15
6
Smart
Display
Write
Through
Mode input
data Bit 14
Type
Reset
state
RW
0
RW
0
REG[26Dh] Bits 7-0
REG[26Ch] Bits 7-0
5
Smart
Display
Write
Through
Mode input
data
Bit 13
RW
0
REG[26Dh]
4
Smart
Display
Write
Through
Mode input
data Bit 12
3
Smart
Display
Write
Through
Mode input
data Bit 11
2
Smart
Display
Write
Through
Mode input
data Bit 10
1
Smart
Display
Write
Through
Mode input
data Bit 9
0
Smart
Display
Write
Through
Mode input
data Bit 8
RW
0
RW
0
RW
0
RW
0
RW
0
Write Through Mode input data register [15:0]
NB : for byte access,
Please update REG[26Ch], then REG[26Dh]
Smart Display Output Data Format Register
Bit
Type
Reset
state
7
Pixel
data/Argum
ent
Selection
RW
0
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Data/Comm
and
Selection
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
REG[26Eh] Bit 7
REG[26Eh] Bits 6-1
REG[26Eh] Bit 0
SSD1926
Application Note
REG[26Eh]
6
Reserved
Rev 1.0
Pixel data/Argument Selection
1 : Pixel Data
0 : Argument
Note :
This bit is effective for Write Through mode only.
Reserved bits
These bits should be programmed by 0.
Data/Command Selection
1 : Data
0 : Command
Note :
This bit is effective for Write Through mode only.
P 51/52
Jul 2009
Solomon Systech
Smart Display Ready Register
REG[27Dh]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
4
0
3
0
2
JPEG
Interrupt
Status Flag
1
DRAW2D
Interrupt
Status Flag
0
Reserved
RO
0
RO
0
RW
0
RW
0
R
0
REG[27Dh] Bit 0
2.7
Smart Display ready register
0 : idle
1 : busy
Interrupt Registers
Interrupt Status Flag Register
Bit
Type
Reset
state
0
Smart
Display
ready
RO
0
7
SDHC
Interrupt
Status Flag
0
RW
0
6
0
RW
0
5
I2C
Interrupt
Status Flag
0
RW
0
REG[48h]
Bit 7
SDHC Interrupt Status Flag
When this bit = 1, SDHC Interrupt Status detected. Write 1 to clear the status flag. Write 0 has
no hardware effect.
When this bit = 0, SDHC Interrupt Status is not detected.
Bits 6, 4, 3, 0
Reserved bits
Bit 5
I2C Interrupt Status Flag
When this bit = 1, I2C Interrupt Status detected. Write 1 to clear the status flag. Write 0 has no
hardware effect.
When this bit = 0, I2C Interrupt Status is not detected.
Bit 2
JPEG Interrupt Status Flag
When this bit = 1, JPEG Interrupt Status detected. Write 1 to clear the status flag. Write 0 has
no hardware effect.
When this bit = 0, JPEG Interrupt Status is not detected.
Bit 1
DRAW2D Interrupt Status Flag
When this bit = 1, DRAW2D Interrupt Status detected. Write 1 to clear the status flag. Write 0
has no hardware effect.
When this bit = 0, DRAW2D Interrupt Status is not detected.
Solomon Systech
Jul 2009
P 52/53
Rev 1.0
SSD1926
Application Note
Interrupt Enable Register
Bit
7
SDHC
Interrupt
Enable
RW
0
Type
Reset
state
6
0
RW
0
Bit 7
4
0
3
0
RO
0
RO
0
2
JPEG
Interrupt
Enable
RW
0
1
DRAW2D
Interrupt
Enable
RW
0
0
Reserved
RO
0
SDHC Interrupt Enable
When this bit = 1, SDHC Interrupt Enable.
When this bit = 0, SDHC Interrupt Disable.
Reserved bits
These bits should be programmed as 0
I2C Interrupt Enable
When this bit = 1, I2C Interrupt Enable.
When this bit = 0, I2C Interrupt Disable.
JPEG Interrupt Enable
When this bit = 1, JPEG Interrupt Enable.
When this bit = 0, JPEG Interrupt Disable.
DRAW2D Interrupt Enable
When this bit = 1, DRAW2D Interrupt Enable.
When this bit = 0, DRAW2D Interrupt Disable.
Bits 6, 4, 3, 0
Bit 5
Bit 2
Bit 1
2.8
REG[4Ah]
5
I2C
Interrupt
Enable
RW
0
Power Up Registers
Power Saving Configuration Register
Bit
Type
Reset
state
7
Vertical
NonDisplay
Period
Status
RO
1
Bit 7
5
0
NA
0
RO
0
REG[A0h]
4
Memory
Controller
Power
Saving
Status Bit
RO
0
3
Display
Power
Saving
Status Bit
RO
0
2
Power
Saving
Mode
Enable Bit
2
RW
0
1
Power
Saving
Mode
Enable Bit
1
RW
0
0
Power
Saving
Mode
Enable Bit
0
RW
1
Vertical Non-Display Period Status
When this bit = 0, the LCD panel is in Vertical Display Period.
When this bit = 1, the LCD panel is in Vertical Non-Display Period.
Reserved bits
Bits 6-5
Bit 4
Memory Controller Power Saving Status Bit
This bit indicates the Power Saving status of the Main Memory
When this bit = 0, the Main memory is on
When this bit = 1, the Main memory is off
Display Power Saving Status Bit
This bit indicates the Power Saving status of the Main display
When this bit = 0, the Main display is on
When this bit = 1, the Main display is off
Power Saving Mode Enable Bit 2
This bit control MCLK generation
When this bit = 1, all MCLK will be off.
When this bit = 0, all MCLK will be on.
Power Saving Mode Enable Bit 1
This bit control Display Memory Clock
When this bit = 1, MCLK for display SRAM will be off.
When this bit = 0, MCLK for display SRAM will be on.
Bit 3
Bit 2
Bit 1
SSD1926
Application Note
6
0
Rev 1.0
P 53/54
Jul 2009
Solomon Systech
Bit 0
Power Saving Mode Enable Bit 0
This bit control Main display power save mode.
When this bit = 1, Power Saving mode is enabled.
When this bit = 0, Power Saving mode is disabled.
Note :
Power saving mode sequence :
Set power saving mode bit 0 = 1 -> check the display power saving status bit until = 1 -> Set
power saving mode bits 2:1 = 11
Memory can not be access if bits 2:1 = 11
Power save frame count Register
Bit
Type
Reset
state
7
Power save
frame count
Bit 7
RW
0
Bits 7-0
6
Power save
frame count
Bit 6
RW
0
5
Power save
frame count
Bit 5
RW
0
REG[A1h]
4
Power save
frame count
Bit 4
RW
0
3
Power save
frame count
Bit 3
RW
0
2
Power save
frame count
Bit 2
RW
0
1
Power save
frame count
Bit 1
RW
0
0
Power save
frame count
Bit 0
RW
0
Power save frame count Bits [7:0]
These bit control main panel switch count once power save is enabled (REG[A0h] bit 0 = 1).
0 : Switch off immediately
n : Switch off at the end of n – 1 frames
Software Reset Register
REG[A2h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Type
Reset
state
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit 0
Solomon Systech
0
Software
Reset
WO
0
Software Reset
When a one is written to this bit, the SSD1926 registers are reset. This bit has no effect on the
contents of the display buffer.
Jul 2009
P 54/55
Rev 1.0
SSD1926
Application Note
2.9
Display Mode Registers
STN Color Depth Control Register
REG[45h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
STN Color
Depth
Control /
FRC Bit
Select
Bit 0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
RW
0
RW
0
RW
0
RW
0
Bit 0
STN Color Depth control
This bit controls the maximum number of color available for STN panels.
When this bit = 0, it allows maximum 32k color depth.
When this bit = 1, it allows maximum 256k color depth.
Refer Table 2-19: LCD Bit-per-pixel Selection for the color depth relationship.
Note
This register is effective for STN panel only (REG[10h] bits 2:0 = 000).
This register can be reset by the RESET signal pin only.
Dithering / FRC Control Register
Bit
Type
Reset
state
7
Dynamic
Dithering
Enable
RW
0
Bit 7
6
0
5
0
NA
0
NA
0
REG[50h]
4
FRC Seed
Rotate
Enable
RW
0
3
Reserved
2
Reserved
1
FRC Period
Select Bit 1
0
FRC Period
Select Bit 0
RW
0
RW
0
RW
1
RW
0
Dynamic Dithering Enable
This bit will enable the dynamic dithering, the dithering mask will change after each 16 frames.
When this bit = 0, dynamic dithering is disabled.
When this bit = 1, dynamic dithering is enabled.
Note
This register is effective for both STN panel and dithering enabled (REG[10h] bits 2:0 = 000
and REG[70h] bit 6 = 0).
FRC Seed Rotate Enable
1 – Enable
0 – Disable
Reserved bits
These bits should be programmed by 0.
FRC Period Select
00 – 14 frames
01 – 15 frames
10 – 16 frames
11 – 17 frames
Bit 4
Bits 3, 2
Bits 1:0
SSD1926
Application Note
Rev 1.0
P 55/56
Jul 2009
Solomon Systech
Display Mode Register
REG[70h]
Bit
7
Display
Blank
6
Dithering
Disable
5
0
Type
Reset
state
RW
0
RW
0
RW
0
Bit 7
Bit 6
4
Software
Color
Invert
RW
0
3
0
RO
0
2
Bit-perpixel Select
Bit 2
RW
0
1
Bit-perpixel Select
Bit 1
RW
0
0
Bit-perpixel Select
Bit 0
RW
0
Display Blank
When this bit = 0, the LCD display output is enabled.
When this bit = 1, the LCD display output is blank and all LCD data outputs are forced to zero
(i.e., the screen is blanked).
Dithering Disable
SSD1926 use a combination of FRC and 4 pixel square formation dithering to achieve more
colors per pixel.
In 256K mode (REG[45h] bit 0 = 1), the 4-bit MSB will be considered as FRC and the 2-bit
LSB will be dithering. In the 32K mode (REG[45h] bit 0 = 0), the 3-bit MSB will be considered
as FRC, the next 2-bit MSB will be dithering and the last LSB will be neglected.
When this bit = 0, dithering is enabled on the passive LCD panel. It allows maximum 64
intensity levels for each color component (RGB).
When this bit = 1, dithering is disabled on the passive LCD panel. It allows maximum 16
intensity levels for each color component (RGB).
Bits 5, 3
Bit 4
Bits 2-0
Note
This bit does not refer to the number of simultaneously displayed colors but rather the
maximum available colors (refer Table 2-19: LCD Bit-per-pixel Selection for the maximum
number of displayed colors).
Reserved bits
Software Color Invert
When this bit = 0, display color is normal.
When this bit = 1, display color is inverted.
This bit has no effect if REG[70h] bit 7 = 1.
Note
Display color is inverted after the Look-Up Table.
Bit-per-pixel Select Bits [2:0]
These bits select the color depth (bit-per-pixel) for the displayed data for both the main window
and the floating window (if active).
Note
1, 2, 4 and 8 bpp modes use three 8-bit LUTs, allowing maximum 256 colors. 16 and 32 bpp
mode bypasses the LUT, allowing 64K and 16M colors respectively.
Table 2-19: LCD Bit-per-pixel Selection
Bit-per-pixel
Select Bits [2:0]
Color Depth
(bpp)
000
001
010
011
100
101
110, 111
1 bpp
2 bpp
4 bpp
8 bpp
16 bpp
32 bpp
Reserved
Solomon Systech
Maximum Number of Colors/Shades
Passive Panel
(Dithering On)
TFT Panel
REG[45h] REG[45h]
bit 0 = 0
bit 0 = 1
32K/32
256K/64
256K/64
32K/32
256K/64
256K/64
32K/32
256K/64
256K/64
32K/32
256K/64
256K/64
32K/32
64K/64
64K/64
32K/32
256K/64
16M/256
n/a
n/a
n/a
Jul 2009
P 56/57
Max. No. Of
Simultaneously
Displayed
Colors/Shades
2/2
4/4
16/16
256/64
64K/64
16M/256
n/a
Rev 1.0
SSD1926
Application Note
TFT FRC Enable Bit Register
REG[346h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[346h] bits 7-1
0
TFT FRC
Enable
Bit
RW
0
Reserved bits
These bits should be programmed by 0.
TFT FRC Enable Bit Register
SSD1926 use 2-bits Frame Rate Control (FRC) to achieve more colors for TFT. So 2 LSB are
used for each RGB color component.
REG[346h] bit 0
TFT FRC will be enabled if this bit is set to 1.
Note : This register is effective for 9/12/18 bit TFT only.
2.10 Main Window Registers
Main Window Display Start Address Register 0
Bit
Type
Reset
state
7
Main
window
Display
Start
Address
Bit 7
RW
0
6
Main
window
Display
Start
Address
Bit 6
RW
0
5
Main
window
Display
Start
Address
Bit 5
RW
0
4
Main
window
Display
Start
Address
Bit 4
RW
0
REG[74h]
3
Main
window
Display
Start
Address
Bit 3
RW
0
2
Main
window
Display
Start
Address
Bit 2
RW
0
3
Main
window
Display
Start
Address
Bit 11
RW
0
2
Main
window
Display
Start
Address
Bit 10
RW
0
Main Window Display Start Address Register 1
Bit
Type
Reset
state
7
Main
window
Display
Start
Address
Bit 15
RW
0
6
Main
window
Display
Start
Address
Bit 14
RW
0
5
Main
window
Display
Start
Address
Bit 13
RW
0
4
Main
window
Display
Start
Address
Bit 12
RW
0
1
Main
window
Display
Start
Address
Bit 1
RW
0
REG[75h]
Main Window Display Start Address Register 2
1
Main
window
Display
Start
Address
Bit 9
RW
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
Rev 1.0
P 57/58
Jul 2009
0
Main
window
Display
Start
Address
Bit 8
RW
0
REG[76h]
Bit
SSD1926
Application Note
0
Main
window
Display
Start
Address
Bit 0
RW
0
0
Main
window
Display
Start
Address
Bit 16
RW
0
Solomon Systech
REG[76h] bit 0,
REG[75h] bits 7-0,
REG[74h] bits 7-0
Main Window Display Start Address Bits [16:0]
These bits form the 17-bit address for the starting double-word of the LCD image in the display
buffer for the main window.
Note that this is a double-word (32-bit) address. An entry of 00000h into these registers
represents the first double-word of display memory, an entry of 00001h represents the second
double-word of the display memory, and so on.
Calculate the Display Start Address as follows :
Main Window Display Start Address Bits 16:0
= Image address ÷ 4 (valid only for Display Rotate Mode 0°)
Note
For information on setting this register for other Display Rotate Mode, see Section “Display Rotate Mode” in
datasheet.
(1)
Main Window Line Address Offset Register 0
Bit
Type
Reset
state
7
Main
window
Line
Address
Offset Bit 7
RW
0
6
Main
window
Line
Address
Offset Bit 6
RW
0
5
Main
window
Line
Address
Offset Bit 5
RW
0
4
Main
window
Line
Address
Offset Bit 4
RW
0
REG[78h]
3
Main
window
Line
Address
Offset Bit 3
RW
0
2
Main
window
Line
Address
Offset Bit 2
RW
0
Main Window Line Address Offset Register 1
0
Main
window
Line
Address
Offset Bit 0
RW
0
REG[79h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[79h] bits 1-0,
REG[78h] bits 7-0
1
Main
window
Line
Address
Offset Bit 1
RW
0
1
Main
window
Line
Address
Offset Bit 9
RW
0
0
Main
window
Line
Address
Offset Bit 8
RW
0
Main Window Line Address Offset Bits [9:0]
This register specifies the offset, in double words, from the beginning of one display line to the
beginning of the next display line in the main window. Note that this is a 32-bit address
increment.
Calculate the Line Address Offset as follows :
Main Window Line Address Offset bits 9-0
= Display Width in pixels ÷ (32 ÷ bpp)
Note
(1)
A virtual display can be created by programming this register with a value greater than the
formula requires. When a virtual display is created the image width is larger than the display
width and the displayed image becomes a window into the larger virtual image.
Solomon Systech
Jul 2009
P 58/59
Rev 1.0
SSD1926
Application Note
RGB Setting Register
Bit
Type
Reset
state
7
Floating
Window
RGB
RW
0
REG[1A4h]
6
Main
Window
RGB
RW
0
Bit 7
5
0
4
0
3
0
2
0
1
0
0
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Floating Window RGB
1 : RGB
0 : YUV
Main Window RGB
1 : RGB
0 : YUV
Reserved bits
These bits should be programmed by 0.
Bit 6
Bits 5-0
2.11 Scratch bit Registers
Scratch bit Register 0
Bit
Type
Reset
state
7
Scratch Pad
Bit 7
RW
0
6
Scratch Pad
Bit 6
RW
0
REG[A4h]
5
Scratch Pad
Bit 5
RW
0
4
Scratch Pad
Bit 4
RW
0
3
Scratch Pad
Bit 3
RW
0
2
Scratch Pad
Bit 2
RW
0
5
Scratch Pad
Bit 13
RW
0
4
Scratch Pad
Bit 12
RW
0
3
Scratch Pad
Bit 11
RW
0
2
Scratch Pad
Bit 10
RW
0
Scratch bit Register 1
Bit
Type
Reset
state
7
Scratch Pad
Bit 15
RW
0
6
Scratch Pad
Bit 14
RW
0
REG[A5h] bits 7-0,
REG[A4h] bits 7-0
1
Scratch Pad
Bit 1
RW
0
0
Scratch Pad
Bit 0
RW
0
REG[A5h]
1
Scratch Pad
Bit 9
RW
0
0
Scratch Pad
Bit 8
RW
0
Scratch Pad Bits [15:0]
This register contains general purpose read/write bits. These bits have no effect on hardware
configuration.
2.12 General IO Pins Registers
General Purpose I/O Pins Configuration Register 0
Bit
7
Reserved
6
Reserved
5
Reserved
Type
Reset
state
RW
0
RW
0
RW
0
Bits 7-5
Reserved bits
Bit 4
GPIO4 I/O Configuration
When this bit = 0, GPIO4 is configured as an input pin.
When this bit = 1, GPIO4 is configured as an output pin.
SSD1926
Application Note
Rev 1.0
P 59/60
Jul 2009
REG[A8h]
4
3
2
1
0
GPIO4 I/O
GPIO3 I/O
GPIO2 I/O
GPIO1 I/O
GPIO0 I/O
Configuration Configuration Configuration Configuration Configuration
RW
RW
RW
RW
RW
0
0
0
0
0
Solomon Systech
Bit 3
GPIO3 I/O Configuration
When this bit = 0, GPIO3 is configured as an input pin.
When this bit = 1, GPIO3 is configured as an output pin.
GPIO2 I/O Configuration
When this bit = 0, GPIO2 is configured as an input pin.
When this bit = 1, GPIO2 is configured as an output pin.
GPIO1 I/O Configuration
When this bit = 0, GPIO1 is configured as an input pin.
When this bit = 1, GPIO1 is configured as an output pin.
GPIO0 I/O Configuration
When this bit = 0, GPIO0 is configured as an input pin.
When this bit = 1, GPIO0 is configured as an output pin.
Bit 2
Bit 1
Bit 0
Note
(1)
The input functions of the GPIO pins are not enabled until REG[A9h] bit 7 is set to 1.
General Purpose IO Pins Configuration Register 1
Bit
Type
Reset
state
7
GPIO Pin
Input
Enable
RW
0
Bit 7
REG[A9h]
6
0
5
0
4
0
3
0
2
0
1
0
0
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
GPIO Pin Input Enable
This bit is used to enable the input function of the GPIO[4:0] pins. It must be changed to a 1
after power-on reset to enable the input function of the GPIO[4:0] pins.
General Purpose IO Pins Status/Control Register
Bit
7
Reserved
6
Reserved
5
Reserved
Type
Reset
state
RW
0
RW
0
RW
0
4
GPIO4 Pin
IO Status
RW
0
REG[ACh]
3
GPIO3 Pin
IO Status
RW
0
2
GPIO2 Pin
IO Status
RW
0
1
GPIO1 Pin
IO Status
RW
0
0
GPIO0 Pin
IO Status
RW
0
Bits 7-5
Reserved bits
Bit 4
GPIO4 Pin IO Status
When GPIO4 is configured as an output, writing a 1 to this bit drives GPIO4 high and writing a
0 to this bit drives GPIO4 low or controlled by LCD Gen4 (REG[334h]).
Bit 3
When GPIO4 is configured as an input, a read from this bit returns the status of GPIO4.
GPIO3 Pin IO Status
When GPIO3 is configured as an output, writing a 1 to this bit drives GPIO3 high and writing a
0 to this bit drives GPIO3 low or controlled by LCD Gen3 (REG[333h]).
When GPIO3 is configured as an input, a read from this bit returns the status of GPIO3.
Bit 2
GPIO2 Pin IO Status
When GPIO2 is configured as an output, writing a 1 to this bit drives GPIO2 high and writing a
0 to this bit drives GPIO2 low or controlled by LCD Gen2 (REG[332h]).
When GPIO2 is configured as an input, a read from this bit returns the status of GPIO2.
Bit 1
GPIO1 Pin IO Status
When GPIO1 is configured as an output, writing a 1 to this bit drives GPIO1 high and writing a
0 to this bit drives GPIO1 low or controlled by LCD Gen1 (REG[331h]).
When GPIO1 is configured as an input, a read from this bit returns the status of GPIO1.
Solomon Systech
Jul 2009
P 60/61
Rev 1.0
SSD1926
Application Note
Bit 0
GPIO0 Pin IO Status
When GPIO0 is configured as an output, writing a 1 to this bit drives GPIO0 high and writing a
0 to this bit drives GPIO0 low or controlled by LCD Gen0 (REG[330h]).
When GPIO0 is configured as an input, a read from this bit returns the status of GPIO0.
Signal source
1 for Gen x
REG[330334h]
Signal 0-7
REG[2B0-32Ch]
Signal source
2 for Gen x
REG[330334h]
Signal source
3 for Gen x
REG[330334h]
LCD Gen x
Config,
REG[338h33Ch]
GPIO[4:0]
Output
GPIO[4:0]
Output
setting,
REG[ACh]
Figure 2-20: GPIO[4:0] output setup
General Purpose I/O (LDATA) Pins Configuration Register 0
REG[AAh]
Bit
7
6
5
4
3
2
1
0
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
(LDATA17) (LDATA16) (LDATA15) (LDATA14) (LDATA13 (LDATA12 (LDATA11 (LDATA10
I/O
I/O
I/O
I/O
) I/O
) I/O
) I/O
) I/O
Configuration Configuration Configuration Configuration Configuration Configuration Configuration Configuration
Type
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
state
Bit 7
GPIO12 (LDATA17) I/O Configuration
When this bit = 0, GPIO12 (LDATA17) is configured as an input pin.
When this bit = 1, GPIO12 (LDATA17) is configured as an output pin.
GPIO11 (LDATA16) I/O Configuration
When this bit = 0, GPIO11 (LDATA16) is configured as an input pin.
When this bit = 1, GPIO11 (LDATA16) is configured as an output pin.
GPIO10 (LDATA15) I/O Configuration
When this bit = 0, GPIO10 (LDATA15) is configured as an input pin.
When this bit = 1, GPIO10 (LDATA15) is configured as an output pin.
GPIO9 (LDATA14) I/O Configuration
When this bit = 0, GPIO9 (LDATA14) is configured as an input pin.
When this bit = 1, GPIO9 (LDATA14) is configured as an output pin.
GPIO8 (LDATA13) I/O Configuration
When this bit = 0, GPIO8 (LDATA13) is configured as an input pin.
When this bit = 1, GPIO8 (LDATA13) is configured as an output pin.
GPIO7 (LDATA12) I/O Configuration
When this bit = 0, GPIO7 (LDATA12) is configured as an input pin.
When this bit = 1, GPIO7 (LDATA12) is configured as an output pin.
GPIO6 (LDATA11) I/O Configuration
When this bit = 0, GPIO6 (LDATA11) is configured as an input pin.
When this bit = 1, GPIO6 (LDATA11) is configured as an output pin.
GPIO5 (LDATA10) I/O Configuration
When this bit = 0, GPIO5 (LDATA10) is configured as an input pin.
When this bit = 1, GPIO5 (LDATA10) is configured as an output pin.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note
(1) The input functions of the GPIO pins are not enabled until REG[ABh] bit 7 is set to 1.
(2) This register is effective when the specified LDATA is not used for LCD interface.
SSD1926
Application Note
Rev 1.0
P 61/62
Jul 2009
Solomon Systech
General Purpose IO (LDATA) Pins Configuration Register 1
Bit
Type
Reset
state
7
LDATA
Pin
Input
Enable
RW
0
Bit 7
REG[ABh]
6
0
5
0
4
0
3
0
2
0
1
0
0
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
LDATA Pin Input Enable
This bit is used to enable the input function of the LDATA17:10 pins. It must be changed to a 1
after power-on reset to enable the input function of the LDATA17:10 pins.
Note
(1) This register is effective when the specified LDATA is not used for LCD interface.
General Purpose IO (LDATA) Pins Status/Control Register
Bit
Type
Reset
state
7
GPIO12
(LDATA17
) Pin IO
Status
RW
0
Bit 7
6
GPIO11
(LDATA16
) Pin IO
Status
RW
0
5
GPIO10
(LDATA15
) Pin IO
Status
RW
0
4
GPIO9
(LDATA14
) Pin IO
Status
RW
0
3
GPIO8
(LDATA13
) Pin IO
Status
RW
0
REG[AEh]
2
GPIO7
(LDATA12
) Pin IO
Status
RW
0
1
GPIO6
(LDATA11
) Pin IO
Status
RW
0
0
GPIO5
(LDATA10
) Pin IO
Status
RW
0
GPIO12 (LDATA17) Pin IO Status
When GPIO12 (LDATA17) is configured as an output, writing a 1 to this bit drives GPIO12
(LDATA17) high and writing a 0 to this bit drives GPIO11 (LDATA17) low.
Bit 6
When GPIO12 (LDATA17) is configured as an input, a read from this bit returns the status of
GPIO12 (LDATA17).
GPIO11 (LDATA16) Pin IO Status
When GPIO11 (LDATA16) is configured as an output, writing a 1 to this bit drives GPIO11
(LDATA16) high and writing a 0 to this bit drives GPIO11 (LDATA16) low.
Bit 5
When GPIO11 (LDATA16) is configured as an input, a read from this bit returns the status of
GPIO11 (LDATA16).
GPIO10 (LDATA15) Pin IO Status
When GPIO10 (LDATA15) is configured as an output, writing a 1 to this bit drives GPIO10
(LDATA15) high and writing a 0 to this bit drives LDATA15 low.
Bit 4
When GPIO10 (LDATA15) is configured as an input, a read from this bit returns the status of
GPIO10 (LDATA15).
GPIO9 (LDATA14) Pin IO Status
When GPIO9 (LDATA14) is configured as an output, writing a 1 to this bit drives GPIO9
(LDATA14) high and writing a 0 to this bit drives GPIO9 (LDATA14) low.
Bit 3
When GPIO9 (LDATA14) is configured as an input, a read from this bit returns the status of
GPIO9 (LDATA14).
GPIO8 (LDATA13) Pin IO Status
When GPIO8 (LDATA13) is configured as an output, writing a 1 to this bit drives GPIO8
(LDATA13) high and writing a 0 to this bit drives LDATA13 low.
When GPIO8 (LDATA13) is configured as an input, a read from this bit returns the status of
GPIO8 (LDATA13).
Bit 2
Solomon Systech
GPIO7 (LDATA12) Pin IO Status
When GPIO7 (LDATA12) is configured as an output, writing a 1 to this bit drives GPIO7
(LDATA12) high and writing a 0 to this bit drives LDATA12 low.
When GPIO7 (LDATA12) is configured as an input, a read from this bit returns the status of
GPIO7 (LDATA12).
Jul 2009
P 62/63
Rev 1.0
SSD1926
Application Note
Bit 1
GPIO6 (LDATA11) Pin IO Status
When GPIO6 (LDATA11) is configured as an output, writing a 1 to this bit drives GPIO6
(LDATA11) high and writing a 0 to this bit drives LDATA11 low.
When GPIO6 (LDATA11) is configured as an input, a read from this bit returns the status of
GPIO6 (LDATA11).
Bit 0
GPIO5 (LDATA10) Pin IO Status
When GPIO5 (LDATA10) is configured as an output, writing a 1 to this bit drives GPIO5
(LDATA10) high and writing a 0 to this bit drives LDATA10 low.
When GPIO5 (LDATA10) is configured as an input, a read from this bit returns the status of
GPIO5 (LDATA10).
Note
(1) This register is effective when the specified LDATA is not used for LCD interface.
LCD Power Control Register
Bit
Type
Reset
state
7
LPOWER
Control
RW
0
Bit 7
REG[ADh]
6
0
5
0
4
0
3
0
2
0
1
0
0
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
LPOWER Control
This bit controls the General Purpose Output pin.
Writing a 0 to this bit drives LPOWER to low.
Writing a 1 to this bit drives LPOWER to high.
Note
(1)
Many implementations use the LPOWER pin to control the LCD bias power (see Section
“LCD Power Sequencing” in datasheet).
LCD Signal0 Rise Location Register 0
Bit
Type
Reset
state
7
LCD
Signal0
Rise
Location
Bit 7
RW
0
6
LCD
Signal0
Rise
Location
Bit 6
RW
0
5
LCD
Signal0
Rise
Location
Bit 5
RW
0
REG[2B0h]
4
LCD
Signal0
Rise
Location
Bit 4
RW
0
3
LCD
Signal0
Rise
Location
Bit 3
RW
0
2
LCD
Signal0
Rise
Location
Bit 2
RW
0
2
LCD
Signal0
Rise
Location
Bit 10
RW
0
LCD Signal0 0 Rise Location Register 1
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
SSD1926
Application Note
Rev 1.0
0
LCD
Signal0
Rise
Location
Bit 0
RW
0
REG[2B1h]
Bit
REG[2B1h] bits 2-0,
REG[2B0h] bits 7-0
1
LCD
Signal0
Rise
Location
Bit 1
RW
0
1
LCD
Signal0
Rise
Location
Bit 9
RW
0
0
LCD
Signal0
Rise
Location
Bit 8
RW
0
LCD Signal0 Rise position Register [10:0]
This register define the lcd Signal0 rise position.
P 63/64
Jul 2009
Solomon Systech
LCD Signal0 Fall Location Register 0
Bit
Type
Reset
state
7
LCD
Signal0
Fall
Location
Bit 7
RW
0
6
LCD
Signal0
Fall
Location
Bit 6
RW
0
5
LCD
Signal0
Fall
Location
Bit 5
RW
0
REG[2B4h]
4
LCD
Signal0
Fall
Location
Bit 4
RW
0
3
LCD
Signal0
Fall
Location
Bit 3
RW
0
2
LCD
Signal0
Fall
Location
Bit 2
RW
0
2
LCD
Signal0
Fall
Location
Bit 10
RW
0
1
LCD
Signal0
Fall
Location
Bit 1
RW
0
LCD Signal0 Fall Location Register 1
REG[2B5h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[2B5h] bits 2-0,
REG[2B4h] bits 7-0
1
LCD
Signal0
Fall
Location
Bit 9
RW
0
Type
Reset
state
7
LCD
Signal0
Period
Location
Bit 7
RW
0
6
LCD
Signal0
Period
Location
Bit 6
RW
0
5
LCD
Signal0
Period
Location
Bit 5
RW
0
REG[2B8h]
4
LCD
Signal0
Period
Location
Bit 4
RW
0
3
LCD
Signal0
Period
Location
Bit 3
RW
0
2
LCD
Signal0
Period
Location
Bit 2
RW
0
2
LCD
Signal0
Period
Location
Bit 10
RW
0
1
LCD
Signal0
Period
Location
Bit 1
RW
0
LCD Signal0 Period Location Register 1
0
LCD
Signal0
Period
Location
Bit 0
RW
0
REG[2B9h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[2B9h] bits 2-0,
REG[2B8h] bits 7-0
0
LCD
Signal0
Fall
Location
Bit 8
RW
0
LCD Signal0 Fall position Register [10:0]
This register define the lcd Signal0 Fall position.
LCD Signal0 Period Location Register 0
Bit
0
LCD
Signal0
Fall
Location
Bit 0
RW
0
1
LCD
Signal0
Period
Location
Bit 9
RW
0
0
LCD
Signal0
Period
Location
Bit 8
RW
0
LCD Signal0 Period position Register [10:0]
This register define the lcd Signal0 Period position.
Note
(1)
This register is ignored if toggle by frame (REG[2BCh] bit 1:0 = 11).
Solomon Systech
Jul 2009
P 64/65
Rev 1.0
SSD1926
Application Note
LCD Signal0 Control Register
Bit
Type
Reset
state
7
LCD
Signal0
Reset
Bit
RW
0
6
LCD
Signal0
NDPOFF
RW
0
Bit 7
5
LCD
Signal0
Odd / Even
Bit 1
RW
0
REG[2BCh]
4
LCD
Signal0
Odd / Even
Bit 0
RW
0
3
Reserved
2
Reserved
RO
0
RO
0
Note
(1)
This bit effective only when LCD signal toggle by PCLK.
LCD Singal0 Odd / Even [1:0]
These bits enable signal output in odd or even lines
00/11 : enable signal in all lines
01 : enable signal in even lines
10 : enable signal in odd lines
Bits 5-4
Note
(1)
These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.
Reserved bits
These bits should be programmed by 0.
LCD Signal0 Toggle Register [1:0]
00 : Disable
01 : toggle by PCLK
10 : toggle by Line
11 : toggle by Frame
Bits 3-2
Bits 1-0
LCD Signal1 Rise Location Register 0
Type
Reset
state
0
LCD
Signal0
Toggle
Bit 0
RW
0
LCD Signal0 Reset Register
This LCD Signal0 will be under frame reset state when this reset bit is set to 1.
LCD Signal0 NDPOFF
This bit enables signal output in non-display period.
0 : enable signal in non-display period
1 : disable signal in non-display period
Bit 6
Bit
1
LCD
Signal0
Toggle
Bit 1
RW
0
7
LCD
Signal1
Rise
Location
Bit 7
RW
0
6
LCD
Signal1
Rise
Location
Bit 6
RW
0
5
LCD
Signal1
Rise
Location
Bit 5
RW
0
REG[2C0h]
4
LCD
Signal1
Rise
Location
Bit 4
RW
0
3
LCD
Signal1
Rise
Location
Bit 3
RW
0
2
LCD
Signal1
Rise
Location
Bit 2
RW
0
2
LCD
Signal1
Rise
Location
Bit 10
RW
0
LCD Signal1 Rise Location Register 1
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
SSD1926
Application Note
Rev 1.0
0
LCD
Signal1
Rise
Location
Bit 0
RW
0
REG[2C1h]
Bit
REG[2C1h] bits 2-0,
REG[2C0h] bits 7-0
1
LCD
Signal1
Rise
Location
Bit 1
RW
0
1
LCD
Signal1
Rise
Location
Bit 9
RW
0
0
LCD
Signal1
Rise
Location
Bit 8
RW
0
LCD Signal1 Rise position Register [10:0]
This register define the lcd Signal1 rise position.
P 65/66
Jul 2009
Solomon Systech
LCD Signal1 Fall Location Register 0
Bit
7
LCD
Signal1 Fall
Location
Bit 7
Type
Reset
state
RW
0
6
LCD
Signal1
Fall
Location
Bit 6
RW
0
5
LCD
Signal1
Fall
Location
Bit 5
RW
0
REG[2C4h]
4
LCD
Signal1
Fall
Location
Bit 4
RW
0
3
LCD
Signal1
Fall
Location
Bit 3
RW
0
2
LCD
Signal1
Fall
Location
Bit 2
RW
0
2
LCD
Signal1
Fall
Location
Bit 10
RW
0
1
LCD
Signal1
Fall
Location
Bit 1
RW
0
LCD Signal1 Fall Location Register 1
REG[2C5h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[2C5h] bits 2-0,
REG[2C4h] bits 7-0
1
LCD
Signal1
Fall
Location
Bit 9
RW
0
Type
Reset
state
7
LCD
Signal1
Period
Location
Bit 7
RW
0
6
LCD
Signal1
Period
Location
Bit 6
RW
0
5
LCD
Signal1
Period
Location
Bit 5
RW
0
REG[2C8h]
4
LCD
Signal1
Period
Location
Bit 4
RW
0
3
LCD
Signal1
Period
Location
Bit 3
RW
0
2
LCD
Signal1
Period
Location
Bit 2
RW
0
2
LCD
Signal1
Period
Location
Bit 10
RW
0
1
LCD
Signal1
Period
Location
Bit 1
RW
0
LCD Signal1 Period Location Register 1
0
LCD
Signal1
Period
Location
Bit 0
RW
0
REG[2C9h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[2C9h] bits 2-0,
REG[2C8h] bits 7-0
0
LCD
Signal1
Fall
Location
Bit 8
RW
0
LCD Signal1 Fall position Register [10:0]
This register define the lcd Signal1 Fall position.
LCD Signal1 Period Location Register 0
Bit
0
LCD
Signal1
Fall
Location
Bit 0
RW
0
1
LCD
Signal1
Period
Location
Bit 9
RW
0
0
LCD
Signal1
Period
Location
Bit 8
RW
0
LCD Signal1 Period position Register [10:0]
This register define the lcd Signal1Period position.
Note
(1)
This register is ignored if toggle by frame (REG[2CCh] bit 1:0 = 11).
Solomon Systech
Jul 2009
P 66/67
Rev 1.0
SSD1926
Application Note
LCD Signal1 Control Register
Bit
Type
Reset
state
7
LCD
Signal1
Reset
Bit
RW
0
6
LCD
Signal1
NDPOFF
RW
0
Bit 7
5
LCD
Signal1
Odd / Even
Bit 1
RW
0
REG[2CCh]
4
LCD
Signal1
Odd / Even
Bit 0
RW
0
3
Reserved
2
Reserved
RO
0
RO
0
Note
(1)
This bit effective only when LCD signal toggle by PCLK.
LCD Singal1 Odd / Even [1:0]
These bits enable signal output in odd or even lines
00/11 : enable signal in all lines
01 : enable signal in even lines
10 : enable signal in odd lines
Bits 5-4
Note
(1)
These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.
Reserved bits
These bits should be programmed by 0.
LCD Signal1 Toggle Register [1:0]
00 : Disable
01 : toggle by PCLK
10 : toggle by Line
11 : toggle by Frame
Bits 3-2
Bits 1-0
LCD Signal2 Rise Location Register 0
Type
Reset
state
0
LCD
Signal1
Toggle
Bit 0
RW
0
LCD Signal1 Reset Register
This LCD Signal1 will be under reset state when this reset bit is set to 1.
LCD Signal1 NDPOFF
This bit enables signal output in non-display period.
0 : enable signal in non-display period
1 : disable signal in non-display period
Bit 6
Bit
1
LCD
Signal1
Toggle
Bit 1
RW
0
7
LCD
Signal2
Rise
Location
Bit 7
RW
0
6
LCD
Signal2
Rise
Location
Bit 6
RW
0
5
LCD
Signal2
Rise
Location
Bit 5
RW
0
REG[2D0h]
4
LCD
Signal2
Rise
Location
Bit 4
RW
0
3
LCD
Signal2
Rise
Location
Bit 3
RW
0
2
LCD
Signal2
Rise
Location
Bit 2
RW
0
2
LCD
Signal2
Rise
Location
Bit 10
RW
0
LCD Signal2 0 Rise Location Register 1
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
SSD1926
Application Note
Rev 1.0
0
LCD
Signal2
Rise
Location
Bit 0
RW
0
REG[2D1h]
Bit
REG[2D1h] bits 2-0,
REG[2D0h] bits 7-0
1
LCD
Signal2
Rise
Location
Bit 1
RW
0
1
LCD
Signal2
Rise
Location
Bit 9
RW
0
0
LCD
Signal2
Rise
Location
Bit 8
RW
0
LCD Signal2 Rise position Register [10:0]
This register define the lcd Signal2 rise position.
P 67/68
Jul 2009
Solomon Systech
LCD Signal2 Fall Location Register 0
Bit
Type
Reset
state
7
LCD
Signal2
Fall
Location
Bit 7
RW
0
6
LCD
Signal2
Fall
Location
Bit 6
RW
0
5
LCD
Signal2
Fall
Location
Bit 5
RW
0
REG[2D4h]
4
LCD
Signal2
Fall
Location
Bit 4
RW
0
3
LCD
Signal2
Fall
Location
Bit 3
RW
0
2
LCD
Signal2
Fall
Location
Bit 2
RW
0
1
LCD
Signal2
Fall
Location
Bit 1
RW
0
2
LCD
Signal2
Fall
Location
Bit 10
RW
0
1
LCD
Signal2
Fall
Location
Bit 9
RW
0
3
LCD
Signal2
Period
Location
Bit 3
RW
0
2
LCD
Signal2
Period
Location
Bit 2
RW
0
1
LCD
Signal2
Period
Location
Bit 1
RW
0
2
LCD
Signal2
Period
Location
Bit 10
RW
0
1
LCD
Signal2
Period
Location
Bit 9
RW
0
LCD Signal2 Fall Location Register 1
REG[2D5h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[2D5h] bits 2-0,
REG[2D4h] bits 7-0
Type
Reset
state
7
LCD
Signal2
Period
Location
Bit 7
RW
0
6
LCD
Signal2
Period
Location
Bit 6
RW
0
5
LCD
Signal2
Period
Location
Bit 5
RW
0
REG[2D8h]
4
LCD
Signal2
Period
Location
Bit 4
RW
0
LCD Signal2 Period Location Register 1
0
LCD
Signal2
Period
Location
Bit 0
RW
0
REG[2D9h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[2D9h] bits 2-0,
REG[2D8h] bits 7-0
0
LCD
Signal2
Fall
Location
Bit 8
RW
0
LCD Signal2 Fall position Register [10:0]
This register define the lcd Signal2 Fall position.
LCD Signal2 Period Location Register 0
Bit
0
LCD
Signal2
Fall
Location
Bit 0
RW
0
0
LCD
Signal2
Period
Location
Bit 8
RW
0
LCD Signal2 Period position Register [10:0]
This register define the lcd Signal2 Period position.
Note
(1)
This register is ignored if toggle by frame (REG[2DCh] bit 1:0 = 11).
Solomon Systech
Jul 2009
P 68/69
Rev 1.0
SSD1926
Application Note
LCD Signal2 Control Register
Bit
Type
Reset
state
7
LCD
Signal2
Reset
Bit
RW
0
6
LCD
Signal2
NDPOFF
RW
0
Bit 7
5
LCD
Signal2
Odd / Even
Bit 1
RW
0
REG[2DCh]
4
LCD
Signal2
Odd / Even
Bit 0
RW
0
3
Reserved
2
Reserved
RO
0
RO
0
Bits 5-4
Bits 3-2
Bits 1-0
LCD Signal3 Rise Location Register 0
Type
Reset
state
0
LCD
Signal2
Toggle
Bit 0
RW
0
LCD Signal2 Reset Register
This LCD Signal2 will be under reset state when this reset bit is set to 1.
LCD Signal2 NDPOFF
This bit enables signal output in non-display period.
0 : enable signal in non-display period
1 : disable signal in non-display period
Note
(1)
This bit effective only when LCD signal toggle by PCLK.
LCD Singal2 Odd / Even [1:0]
These bits enable signal output in odd or even lines
00/11 : enable signal in all lines
01 : enable signal in even lines
10 : enable signal in odd lines
Note
(1)
These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.
Reserved bits
These bits should be programmed by 0.
LCD Signal2 Toggle Register [1:0]
00 : Disable
01 : toggle by PCLK
10 : toggle by Line
11 : toggle by Frame
Bit 6
Bit
1
LCD
Signal2
Toggle
Bit 1
RW
0
7
LCD
Signal3
Rise
Location
Bit 7
RW
0
6
LCD
Signal3
Rise
Location
Bit 6
RW
0
5
LCD
Signal3
Rise
Location
Bit 5
RW
0
REG[2E0h]
4
LCD
Signal3
Rise
Location
Bit 4
RW
0
3
LCD
Signal3
Rise
Location
Bit 3
RW
0
2
LCD
Signal3
Rise
Location
Bit 2
RW
0
2
LCD
Signal3
Rise
Location
Bit 10
RW
0
LCD Signal3 0 Rise Location Register 1
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
SSD1926
Application Note
Rev 1.0
0
LCD
Signal3
Rise
Location
Bit 0
RW
0
REG[2E1h]
Bit
REG[2E1h] bits 2-0,
REG[2E0h] bits 7-0
1
LCD
Signal3
Rise
Location
Bit 1
RW
0
1
LCD
Signal3
Rise
Location
Bit 9
RW
0
0
LCD
Signal3
Rise
Location
Bit 8
RW
0
LCD Signal3 Rise position Register [10:0]
This register define the lcd Signal3 rise position.
P 69/70
Jul 2009
Solomon Systech
LCD Signal3 Fall Location Register 0
Bit
Type
Reset
state
7
LCD
Signal3
Fall
Location
Bit 7
RW
0
6
LCD
Signal3
Fall
Location
Bit 6
RW
0
5
LCD
Signal3
Fall
Location
Bit 5
RW
0
REG[2E4h]
4
LCD
Signal3
Fall
Location
Bit 4
RW
0
3
LCD
Signal3
Fall
Location
Bit 3
RW
0
2
LCD
Signal3
Fall
Location
Bit 2
RW
0
2
LCD
Signal3
Fall
Location
Bit 10
RW
0
1
LCD
Signal3
Fall
Location
Bit 1
RW
0
LCD Signal3 Fall Location Register 1
REG[2E5h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[2E5h] bits 2-0,
REG[2E4h] bits 7-0
1
LCD
Signal3
Fall
Location
Bit 9
RW
0
Type
Reset
state
7
LCD
Signal3
Period
Location
Bit 7
RW
0
6
LCD
Signal3
Period
Location
Bit 6
RW
0
5
LCD
Signal3
Period
Location
Bit 5
RW
0
REG[2E8h]
4
LCD
Signal3
Period
Location
Bit 4
RW
0
3
LCD
Signal3
Period
Location
Bit 3
RW
0
2
LCD
Signal3
Period
Location
Bit 2
RW
0
2
LCD
Signal3
Period
Location
Bit 10
RW
0
1
LCD
Signal3
Period
Location
Bit 1
RW
0
LCD Signal3 Period Location Register 1
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
Solomon Systech
0
LCD
Signal3
Period
Location
Bit 0
RW
0
REG[2E9h]
Bit
REG[2E9h] bits 2-0,
REG[2E8h] bits 7-0
0
LCD
Signal3
Fall
Location
Bit 8
RW
0
LCD Signal3 Fall position Register [10:0]
This register define the lcd Signal3 fall location.
LCD Signal3 Period Location Register 0
Bit
0
LCD
Signal3
Fall
Location
Bit 0
RW
0
1
LCD
Signal3
Period
Location
Bit 9
RW
0
0
LCD
Signal3
Period
Location
Bit 8
RW
0
LCD Signal3 Period position Register [10:0]
This register define the lcd Signal3 Period position.
Note
(1)
This register is ignored if toggle by frame (REG[2ECh] bit 1:0 = 11).
Jul 2009
P 70/71
Rev 1.0
SSD1926
Application Note
LCD Signal3 Control Register
Bit
Type
Reset
state
7
LCD
Signal3
Reset
Bit
RW
0
6
LCD
Signal3
NDPOFF
RW
0
Bit 7
5
LCD
Signal3
Odd / Even
Bit 1
RW
0
REG[2ECh]
4
LCD
Signal3
Odd / Even
Bit 0
RW
0
3
Reserved
2
Reserved
RO
0
RO
0
Bits 5-4
Bits 3-2
Bits 1-0
LCD Signal4 Rise Location Register 0
Type
Reset
state
0
LCD
Signal3
Toggle
Bit 0
RW
0
LCD Signal3 Reset Register
This LCD Signal3 will be under reset state when this reset bit is set to 1.
LCD Signal3 NDPOFF
This bit enables signal output in non-display period.
0 : enable signal in non-display period
1 : disable signal in non-display period
Note
(1)
This bit effective only when LCD signal toggle by PCLK.
LCD Singal3 Odd / Even [1:0]
These bits enable signal output in odd or even lines
00/11 : enable signal in all lines
01 : enable signal in even lines
10 : enable signal in odd lines
Note
(1)
These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.
Reserved bits
These bits should be programmed by 0.
LCD Signal3 Toggle Register [1:0]
00 : Disable
01 : toggle by PCLK
10 : toggle by Line
11 : toggle by Frame
Bit 6
Bit
1
LCD
Signal3
Toggle
Bit 1
RW
0
7
LCD
Signal4
Rise
Location
Bit 7
RW
0
6
LCD
Signal4
Rise
Location
Bit 6
RW
0
5
LCD
Signal4
Rise
Location
Bit 5
RW
0
REG[2F0h]
4
LCD
Signal4
Rise
Location
Bit 4
RW
0
3
LCD
Signal4
Rise
Location
Bit 3
RW
0
2
LCD
Signal4
Rise
Location
Bit 2
RW
0
2
LCD
Signal4
Rise
Location
Bit 10
RW
0
LCD Signal4 Rise Location Register 1
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
SSD1926
Application Note
Rev 1.0
0
LCD
Signal4
Rise
Location
Bit 0
RW
0
REG[2F1h]
Bit
REG[2F1h] bits 2-0,
REG[2F0h] bits 7-0
1
LCD
Signal4
Rise
Location
Bit 1
RW
0
1
LCD
Signal4
Rise
Location
Bit 9
RW
0
0
LCD
Signal4
Rise
Location
Bit 8
RW
0
LCD Signal4 Rise position Register [10:0]
This register define the lcd Signal4 rise position.
P 71/72
Jul 2009
Solomon Systech
LCD Signal4 Fall Location Register 0
Bit
Type
Reset
state
7
LCD
Signal4
Fall
Location
Bit 7
RW
0
6
LCD
Signal4
Fall
Location
Bit 6
RW
0
5
LCD
Signal4
Fall
Location
Bit 5
RW
0
REG[2F4h]
4
LCD
Signal4
Fall
Location
Bit 4
RW
0
3
LCD
Signal4
Fall
Location
Bit 3
RW
0
2
LCD
Signal4
Fall
Location
Bit 2
RW
0
2
LCD
Signal4
Fall
Location
Bit 10
RW
0
1
LCD
Signal4
Fall
Location
Bit 1
RW
0
LCD Signal4 Fall Location Register 1
REG[2F5h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[2F5h] bits 2-0,
REG[2F4h] bits 7-0
1
LCD
Signal4
Fall
Location
Bit 9
RW
0
Type
Reset
state
7
LCD
Signal4
Period
Location
Bit 7
RW
0
6
LCD
Signal4
Period
Location
Bit 6
RW
0
5
LCD
Signal4
Period
Location
Bit 5
RW
0
REG[2F8h]
4
LCD
Signal4
Period
Location
Bit 4
RW
0
3
LCD
Signal4
Period
Location
Bit 3
RW
0
2
LCD
Signal4
Period
Location
Bit 2
RW
0
2
LCD
Signal4
Period
Location
Bit 10
RW
0
1
LCD
Signal4
Period
Location
Bit 1
RW
0
LCD Signal4 Period Location Register 1
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
Solomon Systech
0
LCD
Signal4
Period
Location
Bit 0
RW
0
REG[2F9h]
Bit
REG[2F9h] bits 2-0,
REG[2F8h] bits 7-0
0
LCD
Signal4
Fall
Location
Bit 8
RW
0
LCD Signal4 Fall position Register [10:0]
This register define the lcd Signal4 Fall position.
LCD Signal4 Period Location Register 0
Bit
0
LCD
Signal4
Fall
Location
Bit 0
RW
0
1
LCD
Signal4
Period
Location
Bit 9
RW
0
0
LCD
Signal4
Period
Location
Bit 8
RW
0
LCD Signal4 Period position Register [10:0]
This register define the lcd Signal4 Period position.
Note
(1)
This register is ignored if toggle by frame (REG[2FCh] bit 1:0 = 11).
Jul 2009
P 72/73
Rev 1.0
SSD1926
Application Note
LCD Signal4 Control Register
Bit
Type
Reset
state
7
LCD
Signal4
Reset
Bit
RW
0
6
LCD
Signal4
NDPOFF
RW
0
Bit 7
5
LCD
Signal4
Odd / Even
Bit 1
RW
0
REG[2FCh]
4
LCD
Signal4
Odd / Even
Bit 0
RW
0
3
Reserved
2
Reserved
RO
0
RO
0
Bits 5-4
Bits 3-2
Bits 1-0
LCD Signal5 Rise Location Register 0
Type
Reset
state
0
LCD
Signal4
Toggle
Bit 0
RW
0
LCD Signal4 Reset Register
This LCD Signal4will be under reset state when this reset bit is set to 1.
LCD Signal4 NDPOFF
This bit enables signal output in non-display period.
0 : enable signal in non-display period
1 : disable signal in non-display period
Note
(1)
This bit effective only when LCD signal toggle by PCLK.
LCD Singal4 Odd / Even [1:0]
These bits enable signal output in odd or even lines
00/11 : enable signal in all lines
01 : enable signal in even lines
10 : enable signal in odd lines
Note
(1)
These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.
Reserved bits
These bits should be programmed by 0.
LCD Signal4 Toggle Register [1:0]
00 : Disable
01 : toggle by PCLK
10 : toggle by Line
11 : toggle by Frame
Bit 6
Bit
1
LCD
Signal4
Toggle
Bit 1
RW
0
7
LCD
Signal5
Rise
Location
Bit 7
RW
0
6
LCD
Signal5
Rise
Location
Bit 6
RW
0
5
LCD
Signal5
Rise
Location
Bit 5
RW
0
REG[300h]
4
LCD
Signal5
Rise
Location
Bit 4
RW
0
3
LCD
Signal5
Rise
Location
Bit 3
RW
0
2
LCD
Signal5
Rise
Location
Bit 2
RW
0
2
LCD
Signal5
Rise
Location
Bit 10
RW
0
LCD Signal5 Rise Location Register 1
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
SSD1926
Application Note
Rev 1.0
0
LCD
Signal5
Rise
Location
Bit 0
RW
0
REG[301h]
Bit
REG[301h] bits 2-0,
REG[300h] bits 7-0
1
LCD
Signal5
Rise
Location
Bit 1
RW
0
1
LCD
Signal5
Rise
Location
Bit 9
RW
0
0
LCD
Signal5
Rise
Location
Bit 8
RW
0
LCD Signal5 Rise position Register [10:0]
This register define the lcd Signal5 rise position.
P 73/74
Jul 2009
Solomon Systech
LCD Signal5 Fall Location Register 0
Bit
Type
Reset
state
7
LCD
Signal5
Fall
Location
Bit 7
RW
0
6
LCD
Signal5
Fall
Location
Bit 6
RW
0
5
LCD
Signal5
Fall
Location
Bit 5
RW
0
REG[304h]
4
LCD
Signal5
Fall
Location
Bit 4
RW
0
3
LCD
Signal5
Fall
Location
Bit 3
RW
0
2
LCD
Signal5
Fall
Location
Bit 2
RW
0
2
LCD
Signal5
Fall
Location
Bit 10
RW
0
1
LCD
Signal5
Fall
Location
Bit 1
RW
0
LCD Signal5 Fall Location Register 1
REG[305h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[305h] bits 2-0,
REG[304h] bits 7-0
1
LCD
Signal5
Fall
Location
Bit 9
RW
0
Type
Reset
state
7
LCD
Signal5
Period
Location
Bit 7
RW
0
6
LCD
Signal5
Period
Location
Bit 6
RW
0
5
LCD
Signal5
Period
Location
Bit 5
RW
0
REG[308h]
4
LCD
Signal5
Period
Location
Bit 4
RW
0
3
LCD
Signal5
Period
Location
Bit 3
RW
0
2
LCD
Signal5
Period
Location
Bit 2
RW
0
2
LCD
Signal5
Period
Location
Bit 10
RW
0
1
LCD
Signal5
Period
Location
Bit 1
RW
0
LCD Signal5 Period Location Register 1
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
Solomon Systech
0
LCD
Signal5
Period
Location
Bit 0
RW
0
REG[309h]
Bit
REG[309h] bits 2-0,
REG[308h] bits 7-0
0
LCD
Signal5
Fall
Location
Bit 8
RW
0
LCD Signal5 Fall position Register [10:0]
This register define the lcd Signal5 Fall position.
LCD Signal5 Period Location Register 0
Bit
0
LCD
Signal5
Fall
Location
Bit 0
RW
0
1
LCD
Signal5
Period
Location
Bit 9
RW
0
0
LCD
Signal5
Period
Location
Bit 8
RW
0
LCD Signal5 Period position Register [10:0]
This register define the lcd Signal5 Period position.
Note
(1)
This register is ignored if toggle by frame (REG[30Ch] bit 1:0 = 11).
Jul 2009
P 74/75
Rev 1.0
SSD1926
Application Note
LCD Signal5 Control Register
Bit
Type
Reset
state
7
LCD
Signal5
Reset
Bit
RW
0
6
LCD
Signal5
NDPOFF
RW
0
Bit 7
5
LCD
Signal5
Odd / Even
Bit 1
RW
0
REG[30Ch]
4
LCD
Signal5
Odd / Even
Bit 0
RW
0
3
Reserved
2
Reserved
RO
0
RO
0
Bits 5-4
Bits 3-2
Bits 1-0
LCD Signal6 Rise Location Register 0
Type
Reset
state
0
LCD
Signal5
Toggle
Bit 0
RW
0
LCD Signal5 Reset Register
This LCD Signal5 will be under reset state when this reset bit is set to 1.
LCD Signal5 NDPOFF
This bit enables signal output in non-display period.
0 : enable signal in non-display period
1 : disable signal in non-display period
Note
(1)
This bit effective only when LCD signal toggle by PCLK.
LCD Singal5 Odd / Even [1:0]
These bits enable signal output in odd or even lines
00/11 : enable signal in all lines
01 : enable signal in even lines
10 : enable signal in odd lines
Note
(1)
These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.
Reserved bits
These bits should be programmed by 0.
LCD Signal5 Toggle Register [1:0]
00 : Disable
01 : toggle by PCLK
10 : toggle by Line
11 : toggle by Frame
Bit 6
Bit
1
LCD
Signal5
Toggle
Bit 1
RW
0
7
LCD
Signal6
Rise
Location
Bit 7
RW
0
6
LCD
Signal6
Rise
Location
Bit 6
RW
0
5
LCD
Signal6
Rise
Location
Bit 5
RW
0
REG[310h]
4
LCD
Signal6
Rise
Location
Bit 4
RW
0
3
LCD
Signal6
Rise
Location
Bit 3
RW
0
2
LCD
Signal6
Rise
Location
Bit 2
RW
0
2
LCD
Signal6
Rise
Location
Bit 10
RW
0
LCD Signal6 0 Rise Location Register 1
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
SSD1926
Application Note
Rev 1.0
0
LCD
Signal6
Rise
Location
Bit 0
RW
0
REG[311h]
Bit
REG[311h] bits 2-0,
REG[310h] bits 7-0
1
LCD
Signal6
Rise
Location
Bit 1
RW
0
1
LCD
Signal6
Rise
Location
Bit 9
RW
0
0
LCD
Signal6
Rise
Location
Bit 8
RW
0
LCD Signal6 Rise position Register [10:0]
This register define the lcd Signal6 rise position.
P 75/76
Jul 2009
Solomon Systech
LCD Signal6 Fall Location Register 0
Bit
Type
Reset
state
7
LCD
Signal6
Fall
Location
Bit 7
RW
0
6
LCD
Signal6
Fall
Location
Bit 6
RW
0
5
LCD
Signal6
Fall
Location
Bit 5
RW
0
REG[314h]
4
LCD
Signal6
Fall
Location
Bit 4
RW
0
3
LCD
Signal6
Fall
Location
Bit 3
RW
0
2
LCD
Signal6
Fall
Location
Bit 2
RW
0
2
LCD
Signal6
Fall
Location
Bit 10
RW
0
1
LCD
Signal6
Fall
Location
Bit 1
RW
0
LCD Signal6 Fall Location Register 1
REG[315h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[315h] bits 2-0,
REG[314h] bits 7-0
1
LCD
Signal6
Fall
Location
Bit 9
RW
0
Type
Reset
state
7
LCD
Signal6
Period
Location
Bit 7
RW
0
6
LCD
Signal6
Period
Location
Bit 6
RW
0
5
LCD
Signal6
Period
Location
Bit 5
RW
0
REG[318h]
4
LCD
Signal6
Period
Location
Bit 4
RW
0
3
LCD
Signal6
Period
Location
Bit 3
RW
0
2
LCD
Signal6
Period
Location
Bit 2
RW
0
2
LCD
Signal6
Period
Location
Bit 10
RW
0
1
LCD
Signal6
Period
Location
Bit 1
RW
0
LCD Signal6 Period Location Register 1
0
LCD
Signal6
Period
Location
Bit 0
RW
0
REG[319h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[319h] bits 2-0,
REG[318h] bits 7-0
0
LCD
Signal6
Fall
Location
Bit 8
RW
0
LCD Signal6 Fall position Register [10:0]
This register define the lcd Signal6 Fall position.
LCD Signal6 Period Location Register 0
Bit
0
LCD
Signal6
Fall
Location
Bit 0
RW
0
1
LCD
Signal6
Period
Location
Bit 9
RW
0
0
LCD
Signal6
Period
Location
Bit 8
RW
0
LCD Signal6 Period position Register [10:0]
This register define the lcd Signal6 Period position.
Note
(1)
This register is ignored if toggle by frame (REG[31Ch] bit 1:0 = 11).
Solomon Systech
Jul 2009
P 76/77
Rev 1.0
SSD1926
Application Note
LCD Signal6 Control Register
Bit
Type
Reset
state
7
LCD
Signal6
Reset
Bit
RW
0
6
LCD
Signal6
NDPOFF
RW
0
Bit 7
5
LCD
Signal6
Odd / Even
Bit 1
RW
0
REG[31Ch]
4
LCD
Signal6
Odd / Even
Bit 0
RW
0
3
Reserved
2
Reserved
RO
0
RO
0
Bits 5-4
Bits 3-2
Bits 1-0
LCD Signal7 Rise Location Register 0
Type
Reset
state
0
LCD
Signal6
Toggle
Bit 0
RW
0
LCD Signal6 Reset Register
This LCD Signal6 will be under reset state when this reset bit is set to 1.
LCD Signal6 NDPOFF
This bit enables signal output in non-display period.
0 : enable signal in non-display period
1 : disable signal in non-display period
Note
(1)
This bit effective only when LCD signal toggle by PCLK.
LCD Singal6 Odd / Even [1:0]
These bits enable signal output in odd or even lines
00/11 : enable signal in all lines
01 : enable signal in even lines
10 : enable signal in odd lines
Note
(1)
These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.
Reserved bits
These bits should be programmed by 0.
LCD Signal6 Toggle Register [1:0]
00 : Disable
01 : toggle by PCLK
10 : toggle by Line
11 : toggle by Frame
Bit 6
Bit
1
LCD
Signal6
Toggle
Bit 1
RW
0
7
LCD
Signal7
Rise
Location
Bit 7
RW
0
6
LCD
Signal7
Rise
Location
Bit 6
RW
0
5
LCD
Signal7
Rise
Location
Bit 5
RW
0
REG[320h]
4
LCD
Signal7
Rise
Location
Bit 4
RW
0
3
LCD
Signal7
Rise
Location
Bit 3
RW
0
2
LCD
Signal7
Rise
Location
Bit 2
RW
0
2
LCD
Signal7
Rise
Location
Bit 10
RW
0
LCD Signal7 0 Rise Location Register 1
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
SSD1926
Application Note
Rev 1.0
0
LCD
Signal7
Rise
Location
Bit 0
RW
0
REG[321h]
Bit
REG[321h] bits 2-0,
REG[320h] bits 7-0
1
LCD
Signal7
Rise
Location
Bit 1
RW
0
1
LCD
Signal7
Rise
Location
Bit 9
RW
0
0
LCD
Signal7
Rise
Location
Bit 8
RW
0
LCD Signal7 Rise position Register [10:0]
This register define the lcd Signal7 rise position.
P 77/78
Jul 2009
Solomon Systech
LCD Signal7 Fall Location Register 0
Bit
Type
Reset
state
7
LCD
Signal7
Fall
Location
Bit 7
RW
0
6
LCD
Signal7
Fall
Location
Bit 6
RW
0
5
LCD
Signal7
Fall
Location
Bit 5
RW
0
REG[324h]
4
LCD
Signal7
Fall
Location
Bit 4
RW
0
3
LCD
Signal7
Fall
Location
Bit 3
RW
0
2
LCD
Signal7
Fall
Location
Bit 2
RW
0
2
LCD
Signal7
Fall
Location
Bit 10
RW
0
1
LCD
Signal7
Fall
Location
Bit 1
RW
0
LCD Signal7 Fall Location Register 1
REG[325h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[325h] bits 2-0,
REG[324h] bits 7-0
1
LCD
Signal7
Fall
Location
Bit 9
RW
0
Type
Reset
state
7
LCD
Signal7
Period
Location
Bit 7
RW
0
6
LCD
Signal7
Period
Location
Bit 6
RW
0
5
LCD
Signal7
Period
Location
Bit 5
RW
0
REG[328h]
4
LCD
Signal7
Period
Location
Bit 4
RW
0
3
LCD
Signal7
Period
Location
Bit 3
RW
0
2
LCD
Signal7
Period
Location
Bit 2
RW
0
2
LCD
Signal7
Period
Location
Bit 10
RW
0
1
LCD
Signal7
Period
Location
Bit 1
RW
0
LCD Signal7 Period Location Register 1
0
LCD
Signal7
Period
Location
Bit 0
RW
0
REG[329h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[329h] bits 2-0,
REG[328h] bits 7-0
0
LCD
Signal7
Fall
Location
Bit 8
RW
0
LCD Signal7 Fall position Register [10:0]
This register define the lcd Signal7 Fall position.
LCD Signal7 Period Location Register 0
Bit
0
LCD
Signal7
Fall
Location
Bit 0
RW
0
1
LCD
Signal7
Period
Location
Bit 9
RW
0
0
LCD
Signal7
Period
Location
Bit 8
RW
0
LCD Signal7 Period position Register [10:0]
This register define the lcd Signal7 Period position.
Note
(1)
This register is ignored if toggle by frame (REG[32Ch] bit 1:0 = 11).
Solomon Systech
Jul 2009
P 78/79
Rev 1.0
SSD1926
Application Note
LCD Signal7 Control Register
Bit
7
LCD
Signal7
Reset
Bit
RW
0
Type
Reset
state
6
LCD
Signal7
NDPOFF
RW
0
Bit 7
5
LCD
Signal7
Odd / Even
Bit 1
RW
0
REG[32Ch]
4
LCD
Signal7
Odd / Even
Bit 0
RW
0
3
Reserved
2
Reserved
RO
0
RO
0
1
LCD
Signal7
Toggle
Bit 1
RW
0
0
LCD
Signal7
Toggle
Bit 0
RW
0
LCD Signal7 Reset Register
This LCD Signal7 will be under reset state when this reset bit is set to 1.
LCD Signal7 NDPOFF
This bit enables signal output in non-display period.
0 : enable signal in non-display period
1 : disable signal in non-display period
Note
(1)
This bit effective only when LCD signal toggle by PCLK.
LCD Singal7 Odd / Even [1:0]
These bits enable signal output in odd or even lines
00/11 : enable signal in all lines
01 : enable signal in even lines
10 : enable signal in odd lines
Note
(1)
These bits effective only when NDPOFF = 1 and LCD signal toggle by PCLK.
Reserved bits
These bits should be programmed by 0.
LCD Signal7 Toggle Register [1:0]
00 : Disable
01 : toggle by PCLK
10 : toggle by Line
11 : toggle by Frame
Bit 6
Bits 5-4
Bits 3-2
Bits 1-0
VDP
Line 0
Line 1
Line 2
Line 3
LFRAME
LLINE
Signalx
NDPOFF=0
ODD/EVEN = 00
NDPOFF=1
ODD/EVEN = 00/11
NDPOFF=1
ODD/EVEN = 01
NDPOFF=1
ODD/EVEN = 10
Assume VDP = 4
Figure 2-21: Examples for LCD signalx by NDPOFF and ODD / Even bits
SSD1926
Application Note
Rev 1.0
P 79/80
Jul 2009
Solomon Systech
LCD Gen0 Configure Register
Bit
Type
Reset
state
7
LCD Signal
Select for
source 1
Bit 2
RW
0
Bits 7-5
6
LCD Signal
Select for
source 1
Bit 1
RW
0
5
LCD Signal
Select for
source 1
Bit 0
RW
0
REG[330h]
4
LCD Signal
Select for
source 2
Bit 2
RW
0
3
LCD Signal
Select for
source 2
Bit 1
RW
0
2
LCD Signal
Select for
source 2
Bit 0
RW
0
1
LCD Signal
Select for
source 3
Bit 1
RW
0
2
LCD Signal
Select for
source 2
Bit 0
RW
0
1
LCD Signal
Select for
source 3
Bit 1
RW
0
LCD Signal Select for source 1 Register [2:0]
This register select signal generator for source 1.
LCD Signal Select for source 2 Register [2:0]
This register select signal generator for source 2.
LCD Signal Select for source 3 Register [1:0]
This register select signal generator for source 3.
Bits 4-2
Bits 1-0
LCD Gen1 Configure Register
Bit
Type
Reset
state
7
LCD Signal
Select for
source 1
Bit 2
RW
0
Bits 7-5
6
LCD Signal
Select for
source 1
Bit 1
RW
0
5
LCD Signal
Select for
source 1
Bit 0
RW
0
REG[331h]
4
LCD Signal
Select for
source 2
Bit 2
RW
0
3
LCD Signal
Select for
source 2
Bit 1
RW
0
Bits 1-0
LCD Gen2 Configure Register
Type
Reset
state
0
LCD Signal
Select for
source 3
Bit 0
RW
0
LCD Signal Select for source 1 Register [2:0]
This register select signal generator for source 1.
LCD Signal Select for source 2 Register [2:0]
This register select signal generator for source 2.
LCD Signal Select for source 3 Register [1:0]
This register select signal generator for source 3.
Bits 4-2
Bit
0
LCD Signal
Select for
source 3
Bit 0
RW
0
7
LCD Signal
Select for
source 1
Bit 2
RW
0
Bits 7-5
Bits 4-2
Bits 1-0
Solomon Systech
6
LCD Signal
Select for
source 1
Bit 1
RW
0
5
LCD Signal
Select for
source 1
Bit 0
RW
0
REG[332h]
4
LCD Signal
Select for
source 2
Bit 2
RW
0
3
LCD Signal
Select for
source 2
Bit 1
RW
0
2
LCD Signal
Select for
source 2
Bit 0
RW
0
1
LCD Signal
Select for
source 3
Bit 1
RW
0
0
LCD Signal
Select for
source 3
Bit 0
RW
0
LCD Signal Select for source 1 Register [2:0]
This register select signal generator for source 1.
LCD Signal Select for source 2 Register [2:0]
This register select signal generator for source 2.
LCD Signal Select for source 3 Register [1:0]
This register select signal generator for source 3.
Jul 2009
P 80/81
Rev 1.0
SSD1926
Application Note
LCD Gen3 Configure Register
Bit
Type
Reset
state
7
LCD Signal
Select for
source 1
Bit 2
RW
0
6
LCD Signal
Select for
source 1
Bit 1
RW
0
Bits 7-5
5
LCD Signal
Select for
source 1
Bit 0
RW
0
REG[333h]
4
LCD Signal
Select for
source 2
Bit 2
RW
0
3
LCD Signal
Select for
source 2
Bit 1
RW
0
2
LCD Signal
Select for
source 2
Bit 0
RW
0
Bits 1-0
LCD Gen4 Configure Register
Type
Reset
state
7
LCD Signal
Select for
source 1
Bit 2
RW
0
6
LCD Signal
Select for
source 1
Bit 1
RW
0
Bits 7-5
5
LCD Signal
Select for
source 1
Bit 0
RW
0
REG[334h]
4
LCD Signal
Select for
source 2
Bit 2
RW
0
3
LCD Signal
Select for
source 2
Bit 1
RW
0
2
LCD Signal
Select for
source 2
Bit 0
RW
0
Bits 1-0
LCD Gen0 ROP Configure Register
Type
Reset
state
7
LCD Gen0
Configure
Bit 7
RW
0
6
LCD Gen0
Configure
Bit 6
RW
0
Bits 7-0
5
LCD Gen0
Configure
Bit 5
RW
0
Type
Reset
state
0
LCD Signal
Select for
source 3
Bit 0
RW
0
REG[338h]
4
LCD Gen0
Configure
Bit 4
RW
0
3
LCD Gen0
Configure
Bit 3
RW
0
2
LCD Gen0
Configure
Bit 2
RW
0
1
LCD Gen0
Configure
Bit 1
RW
0
0
LCD Gen0
Configure
Bit 0
RW
0
LCD Gen0 ROP Configure Register [1:0]
This register configures signal generator operation for source 1, 2 and 3
LCD Gen1 ROP Configure Register
Bit
1
LCD Signal
Select for
source 3
Bit 1
RW
0
LCD Signal Select for source 1 Register [2:0]
This register select signal generator for source 1.
LCD Signal Select for source 2 Register [2:0]
This register select signal generator for source 2.
LCD Signal Select for source 3 Register [1:0]
This register select signal generator for source 3.
Bits 4-2
Bit
0
LCD Signal
Select for
source 3
Bit 0
RW
0
LCD Signal Select for source 1 Register [2:0]
This register select signal generator for source 1.
LCD Signal Select for source 2 Register [2:0]
This register select signal generator for source 2.
LCD Signal Select for source 3 Register [1:0]
This register select signal generator for source 3.
Bits 4-2
Bit
1
LCD Signal
Select for
source 3
Bit 1
RW
0
7
LCD Gen1
Configure
Bit 7
RW
0
6
LCD Gen1
Configure
Bit 6
RW
0
Bits 7-0
SSD1926
Application Note
5
LCD Gen1
Configure
Bit 5
RW
0
REG[339h]
4
LCD Gen1
Configure
Bit 4
RW
0
3
LCD Gen1
Configure
Bit 3
RW
0
2
LCD Gen1
Configure
Bit 2
RW
0
1
LCD Gen1
Configure
Bit 1
RW
0
0
LCD Gen1
Configure
Bit 0
RW
0
LCD Gen1 ROP Configure Register [1:0]
This register configures signal generator operation for source 1, 2 and 3
Rev 1.0
P 81/82
Jul 2009
Solomon Systech
LCD Gen2 ROP Configure Register
Bit
Type
Reset
state
7
LCD Gen2
Configure
Bit 7
RW
0
Bits 7-0
6
LCD Gen2
Configure
Bit 6
RW
0
5
LCD Gen2
Configure
Bit 5
RW
0
REG[33Ah]
4
LCD Gen2
Configure
Bit 4
RW
0
3
LCD Gen2
Configure
Bit 3
RW
0
2
LCD Gen2
Configure
Bit 2
RW
0
1
LCD Gen2
Configure
Bit 1
RW
0
LCD Gen2 ROP Configure Register [1:0]
This register configures signal generator operation for source 1, 2 and 3
LCD Gen3 ROP Configure Register
Bit
Type
Reset
state
7
LCD Gen3
Configure
Bit 7
RW
0
Bits 7-0
6
LCD Gen3
Configure
Bit 6
RW
0
5
LCD Gen3
Configure
Bit 5
RW
0
REG[33Bh]
4
LCD Gen3
Configure
Bit 4
RW
0
3
LCD Gen3
Configure
Bit 3
RW
0
2
LCD Gen3
Configure
Bit 2
RW
0
1
LCD Gen3
Configure
Bit 1
RW
0
Type
Reset
state
0
LCD Gen3
Configure
Bit 0
RW
0
LCD Gen3 ROP Configure Register [1:0]
This register configures signal generator operation for source 1, 2 and 3
LCD Gen4 ROP Configure Register
Bit
0
LCD Gen2
Configure
Bit 0
RW
0
7
LCD Gen4
Configure
Bit 7
RW
0
Bits 7-0
6
LCD Gen4
Configure
Bit 6
RW
0
5
LCD Gen4
Configure
Bit 5
RW
0
REG[33Ch]
4
LCD Gen4
Configure
Bit 4
RW
0
3
LCD Gen4
Configure
Bit 3
RW
0
2
LCD Gen4
Configure
Bit 2
RW
0
1
LCD Gen4
Configure
Bit 1
RW
0
0
LCD Gen4
Configure
Bit 0
RW
0
LCD Gen4 ROP Configure Register [1:0]
This register configures signal generator operation for source 1, 2 and 3
Note
(1)
Refer to WindowCE for the detailed Raster Operation (ROP).
Solomon Systech
Jul 2009
P 82/83
Rev 1.0
SSD1926
Application Note
2.13 2D Engine Registers
Special Effects Register
REG[71h]
Bit
7
Display
Data
Word Swap
6
Display
Data
Byte Swap
5
0
4
Floating
Window
Enable
3
0
2
Display
Mirror
Mode
Type
Reset
state
RW
0
RW
0
RO
0
RW
0
RO
0
RO
0
Bit 7
1
Display
Rotate
Mode
Select
Bit 1
RW
0
0
Display
Rotate
Mode
Select
Bit 0
RW
0
Display Data Word Swap
The display pipe fetches 32-bit of data from the display buffer. This bit enables the lower 16-bit
word and the upper 16-bit word to be swapped before sending them to the LCD display. If the
Display Data Byte Swap bit is also enabled, then the byte order of the fetched 32-bit data is
reversed.
Display Data Byte Swap
The display pipe fetches 32-bit of data from the display buffer. This bit enables swapping of
byte 0 and byte 1, byte 2 and byte 3, before sending them to the LCD. If the Display Data Word
Swap bit is also set, then the byte order of the fetched 32-bit data is reversed.
Bit 6
byte 0
32-bit display data
from display buffer
byte 1
Data
Serialization
byte 2
To LUT
byte 3
Byte Swap
Word Swap
Figure 2-22: Display Data Byte/Word Swap
Bit 4
Floating Window Enable
This bit enables the floating window within the main window used for the Floating
Window feature. The location of the floating window within the main window is determined
by the Floating Window Position X registers (REG[84h], REG[85h], REG[8Ch], REG[8Dh])
and Floating Window Position Y registers (REG[88h], REG[89h], REG[90h], REG[91h]). The
floating window has its own Display Start Address register (REG[7Ch, REG[7Dh], REG[7Eh])
and Memory Address Offset register (REG[80h], REG[81h]). The floating window shares the
same color depth and display orientation as the main window.
When this bit = 1, Floating Window is enabled.
When this bit = 0, Floating Window is disabled.
Display Mirror Mode
When this bit = 1,
When this bit = 1, Mirror Mode is enabled.
When this bit = 0, Mirror Mode is disable.
Bit 2
Bits 1-0
SSD1926
Application Note
Display Rotate Mode Select Bits [1:0]
These bits select different display orientations:
Rev 1.0
P 83/84
Jul 2009
Solomon Systech
Table 2-20: Display Rotate Mode Select Options
Display Rotate Mode
Select Bits [1:0]
00
01
10
11
Display Orientation
0° (Normal)
90°
180°
270°
2.14 Display Rotate Mode
The image is not actually rotated in the display buffer since there is no address translation during CPU
read/write. The image is rotated during display refresh.
2.14.1 90° Display Rotate Mode
The following figure shows how the programmer sees a 320x480 rotated image and how the image is being
displayed. The application image is written to the SSD1926 in the following sense: A–B–C–D. The display is
refreshed by the SSD1926 in the following sense: B-D-A-C.
physical memory
start address
B
C
D
320
C
display start address
(panel origin)
A
480
Display
Rotate
Window
D
B
Display
Rotate
Window
A
480
320
image seen by programmer
image refreshed by SSD1926
= image in display buffer
Figure 2-23: Relationship Between Screen Image and Image Refreshed in 90°° Display Rotate Mode.
Enable 90°° Display Rotate Mode
Set Display Rotate Mode Select bits to 01 (REG[71h] bits 1:0 = 01).
Display Start Address
The display refresh circuitry starts at pixel “B”, therefore the Main Window Display Start Address registers (REG[74h],
REG[75h], REG[76h]) must be programmed with the address of pixel “B”.
To calculate the value of the address of pixel “B” use the following formula (assumes 8bpp color depth).
Main Window Display Start Address bits 16-0
= ((Image address + (panel height x bpp ÷ 8)) ÷ 4) –1
= ((0 + (320 pixels x 8 bpp ÷ 8)) ÷ 4) – 1
= 79 (4Fh)
Line Address Offset
The Main Window Line Address Offset register (REG[78h], REG[79h]) is based on the display width and programmed
using the following formula.
Main Window Line Address Offset bits 9-0
= Display width in pixels ÷ (32 ÷ bpp)
= 320 pixels ÷ (32 ÷ 8 bpp)
= 80 (50h)
Solomon Systech
Jul 2009
P 84/85
Rev 1.0
SSD1926
Application Note
2.14.2 180° Display Rotate Mode
The following figure shows how the programmer sees a 480x320 landscape image and how the image is
being displayed. The application image is written to the SSD1926 in the following sense: A–B–C–D. The
display is refreshed by the SSD1926 in the following sense: D-C-B-A.
physical memory
start address
display start address
(panel origin)
D
320
Display
Rotate
Window
B
D
A
C
320
B
Display
Rotate
Window
C
A
480
480
image seen by programmer
image refreshed by SSD1926
= image in display buffer
Figure 2-24: Relationship Between Screen Image and Image Refreshed in 180°° Display Rotate Mode.
Enable 180°° Display Rotate Mode
Set Display Rotate Mode Select bits to 10 (REG[71h] bits 1:0 = 10).
Display Start Address
The display refresh circuitry starts at pixel “D”, therefore the Main Window Display Start Address registers
(REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel “D”.
To calculate the value of the address of pixel “D” use the following formula (assumes 8bpp color depth).
Main Window Display Start Address bits 16-0
= ((Image address + (image width x (panel height – 1) + panel width) x bpp ÷ 8) ÷ 4) –1
= ((0 + (480 pixels x 319 pixels + 480 pixels) x 8 bpp ÷ 8) ÷ 4) – 1
= 38399 (95FFh)
Line Address Offset
The Main Window Line Address Offset register (REG[78h], REG[79h]) is based on the display width and
programmed using the following formula.
Main Window Line Address Offset bits 9-0
= Display width in pixels ÷ (32 ÷ bpp)
= 480 pixels ÷ (32 ÷ 8 bpp)
= 120 (78h)
SSD1926
Application Note
Rev 1.0
P 85/86
Jul 2009
Solomon Systech
2.14.3 270° Display Rotate Mode
The following figure shows how the programmer sees a 320x480 rotated image and how the image is being
displayed. The application image is written to the SSD1926 in the following sense: A–B–C–D. The display is
refreshed by the SSD1926 in the following sense: C-A-D-B.
physical memory
start address
B
Display
Rotate
Window
480
A
C
Display
Rotate
Window
display start address
(panel origin)
D
B
D
C
320
A
480
320
image seen by programmer
image refreshed by SSD1926
= image in display buffer
Figure 2-25: Relationship Between Screen Image and Image Refreshed in 270°° Display Rotate Mode.
Enable 270°° Display Rotate Mode
Set Display Rotate Mode Select bits to 11 (REG[71h] bits 1:0 = 11).
Display Start Address
The display refresh circuitry starts at pixel “C”, therefore the Main Window Display Start Address registers
(REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel “C”.
To calculate the value of the address of pixel “C” use the following formula (assumes 8bpp color depth).
Main Window Display Start Address bits 16-0
= (Image address + ((panel width – 1) x image width x bpp ÷ 8) ÷ 4)
= (0 + ((480 pixels – 1) x 320 pixels x 8 bpp ÷ 8) ÷ 4)
= 38320 (95B0h)
Line Address Offset
The Main Window Line Address Offset register (REG[78h], REG[79h]) is based on the display width and
programmed using the following formula.
Main Window Line Address Offset bits 9-0
= Display width in pixels ÷ (32 ÷ bpp)
= 320 pixels ÷ (32 ÷ 8 bpp)
= 80 (50h)
Solomon Systech
Jul 2009
P 86/87
Rev 1.0
SSD1926
Application Note
2.15 Floating Window Mode
This mode enables a floating window within the main display window. The floating window can be
positioned anywhere within the virtual display and is controlled through the Floating Window control
registers (REG[7Ch] through REG[91h]). The floating window retains the same color depth and display
orientation as the main window.
The following diagram shows an example of a floating window within a main window and the registers used
to position it.
Normal Orientation Mode
Floating Window Start Y Position
(REG[89h],REG[88h])
panel’s origin
Floating Window End Y Position
(REG[91h],REG[90h])
Main Window
Floating Window
Floating Window Start X Position
(REG[85h],REG[84h])
Floating Window End X Position
(REG[8Dh],REG[8Ch])
Figure 2-26: Floating Window with Display Rotate Mode disabled
2.15.1 Floating window under 90°Display Rotate Mode
panel’s origin
90°° Display Rotate Mode
Floating Window End X Position
(REG[8Dh],REG[8Ch])
Floating Window Start X Position
(REG[85h],REG[84h])
Floating window
Floating Window Start Y Position
(REG[89h],REG[88h])
Main Window
Floating Window End Y Position
(REG[91h],REG[90h])
Figure 2-27: Floating Window with Display Rotate Mode 90° enabled
SSD1926
Application Note
Rev 1.0
P 87/88
Jul 2009
Solomon Systech
2.15.2 Floating window under 180°Display Rotate Mode
180°° Display Rotate Mode
Floating Window Start X Position
(REG[85h],REG[84h])
Floating Window End X Position
(REG[8Dh],REG[8Ch])
Floating Window
Main Window
Floating Window End Y Position
(REG[91h],REG[90h]) Floating Window Start Y Position
(REG[89h],REG[88h])
panel’s origin
Figure 2-28: Floating Window with Display Rotate Mode 180° enabled
2.15.3 Floating window under 270°Display Rotate Mode
270°° Display Rotate Mode
Floating Window End Y Position
(REG[91h],REG[90h])
Main Window
Floating Window Start Y Position
(REG[89h],REG[88h])
Floating Window
Floating Window Start X Position
(REG[85h],REG[84h])
panel’s origin
Floating Window End X Position
(REG[8Dh],REG[8Ch])
Figure 2-29: Floating Window with Display Rotate Mode 270° enabled
Solomon Systech
Jul 2009
P 88/89
Rev 1.0
SSD1926
Application Note
Floating Window Display Start Address Register 0
Bit
Type
Reset
state
7
Floating
Window
Display
Start
Address
Bit 7
RW
0
6
Floating
Window
Display
Start
Address
Bit 6
RW
0
5
Floating
Window
Display
Start
Address
Bit 5
RW
0
4
Floating
Window
Display
Start
Address
Bit 4
RW
0
REG[7Ch]
3
Floating
Window
Display
Start
Address
Bit 3
RW
0
2
Floating
Window
Display
Start
Address
Bit 2
RW
0
1
Floating
Window
Display
Start
Address
Bit 1
RW
0
Floating Window Display Start Address Register 1
Bit
7
Floating
Window
Display
Start
Address
Bit 15
RW
0
Type
Reset
state
6
Floating
Window
Display
Start
Address
Bit 14
RW
0
5
Floating
Window
Display
Start
Address
Bit 13
RW
0
4
Floating
Window
Display
Start
Address
Bit 12
RW
0
REG[7Dh]
3
Floating
Window
Display
Start
Address
Bit 11
RW
0
2
Floating
Window
Display
Start
Address
Bit 10
RW
0
1
Floating
Window
Display
Start
Address
Bit 9
RW
0
Floating Window Display Start Address Register 2
0
Floating
Window
Display
Start
Address
Bit 8
RW
0
REG[7Eh]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[7Eh] bit 0,
REG[7Dh] bits 7-0,
REG[7Ch] bits 7-0
0
Floating
Window
Display
Start
Address
Bit 0
RW
0
0
Floating
Window
Display
Start
Address
Bit 16
RW
0
Floating Window Display Start Address Bits [16:0]
These bits form the 17-bit address for the starting double-word of the floating window.
Note that this is a double-word (32-bit) address. An entry of 00000h into these registers
represents the first double-word of display memory, an entry of 00001h represents the second
double-word of the display memory, and so on.
Note
These bits will not effective until the Floating Window Enable bit is set to 1 (REG[71h] bit
4=1).
SSD1926
Application Note
Rev 1.0
P 89/90
Jul 2009
Solomon Systech
Floating Window Line Address Offset Register 0
Bit
Type
Reset
state
7
Floating
Window
Line
Address
Offset Bit 7
RW
0
6
Floating
Window
Line
Address
Offset Bit 6
RW
0
5
Floating
Window
Line
Address
Offset Bit 5
RW
0
4
Floating
Window
Line
Address
Offset Bit 4
RW
0
REG[80h]
3
Floating
Window
Line
Address
Offset Bit 3
RW
0
2
Floating
Window
Line
Address
Offset Bit 2
RW
0
1
Floating
Window
Line
Address
Offset Bit 1
RW
0
Floating Window Line Address Offset Register 1
REG[81h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[81h] bits 1-0,
REG[80h] bits 7-0
0
Floating
Window
Line
Address
Offset Bit 0
RW
0
1
Floating
Window
Line
Address
Offset Bit 9
RW
0
0
Floating
Window
Line
Address
Offset Bit 8
RW
0
Floating Window Line Address Offset Bits [9:0]
These bits are the LCD display’s 10-bit address offset from the starting double-word of line “n”
to the starting double-word of line “n + 1” for the floating window.
Note
(1)
This is a 32-bit address increment.
Note
(1)
These bits will not effective until the Floating Window Enable bit is set to 1 (REG[71h] bit
4=1).
Solomon Systech
Jul 2009
P 90/91
Rev 1.0
SSD1926
Application Note
Floating Window Start Position X Register 0
Bit
Type
Reset
state
7
Floating
Window
Start X
Position Bit
7
RW
0
6
Floating
Window
Start X
Position Bit
6
RW
0
5
Floating
Window
Start X
Position Bit
5
RW
0
REG[84h]
4
Floating
Window
Start X
Position Bit
4
RW
0
3
Floating
Window
Start X
Position Bit
3
RW
0
2
Floating
Window
Start X
Position Bit
2
RW
0
1
Floating
Window
Start X
Position Bit
1
RW
0
1
Floating
Window
Start X
Position Bit
9
RW
0
Floating Window Start Position X Register 1
REG[85h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[85h] bits 1-0,
REG[84h] bits 7-0
0
Floating
Window
Start X
Position Bit
0
RW
0
0
Floating
Window
Start X
Position Bit
8
RW
0
Floating Window Start Position X Bits [9:0]
These bits determine the start position X of the floating window in relation to the origin of the
panel. Due to the SSD1926 Display Rotate feature, the start position X may not be a horizontal
position value (only true in 0° and 180° rotation). For further information on defining the value
of the Start Position X register, see Section “Floating Window Mode” in datasheet.
The value of register is also increased differently based on the display orientation. For 0° and
180° Display Rotate Mode, the start position X is incremented by x pixels where x is relative to
the current color depth. Refer to Table 2-21. For 90° and 270° Display Rotate Mode, the start
position X is incremented by 1 line.
Depending on the color depth, some of the higher bits in this register are unused because the
maximum horizontal display width is 1024 pixels.
Note
(1)
These bits will not effective until the Floating Window Enable bit is set to 1 (REG[71h] bit
4=1).
Table 2-21: 32-bit Address X Increments for Various Color Depths
Color Depth (bpp)
1
2
4
8
16
32
SSD1926
Application Note
Rev 1.0
P 91/92
Jul 2009
Pixel Increment (x)
32
16
8
4
2
1
Solomon Systech
Floating Window Start Position Y Register 0
Bit
Type
Reset
state
7
Floating
Window
Start Y
Position Bit
7
RW
0
6
Floating
Window
Start Y
Position Bit
6
RW
0
5
Floating
Window
Start Y
Position Bit
5
RW
0
REG[88h]
4
Floating
Window
Start Y
Position Bit
4
RW
0
3
Floating
Window
Start Y
Position Bit
3
RW
0
2
Floating
Window
Start Y
Position Bit
2
RW
0
1
Floating
Window
Start Y
Position Bit
1
RW
0
1
Floating
Window
Start Y
Position Bit
9
RW
0
Floating Window Start Position Y Register 1
REG[89h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[89h] bits 1-0,
REG[88h] bits 7-0
0
Floating
Window
Start Y
Position Bit
0
RW
0
0
Floating
Window
Start Y
Position Bit
8
RW
0
Floating Window Start Position Y Bits [9:0]
These bits determine the start position Y of the floating window in relation to the origin of the
panel. Due to the SSD1926 Display Rotate feature, the start position Y may not be a vertical
position value (only true in 0° and 180° Floating Window). For further information on defining
the value of the Start Position Y register, see Section “Floating Window Mode” in datasheet.
The register is also incremented according to the display orientation. For 0° and 180° Display
Rotate Mode, the start position Y is incremented by 1 line. For 90° and 270° Display Rotate
Mode, the start position Y is incremented by y pixels where y is relative to the current color
depth. Refer to Table 2-22: 32-bit Address Y Increments for Various Color Depths.
Depending on the color depth, some of the higher bits in this register are unused because the
maximum vertical display height is 1024 pixels.
Note
(1)
These bits will not effective until the Floating Window Enable bit is set to 1 (REG[71h] bit
4=1).
Table 2-22: 32-bit Address Y Increments for Various Color Depths
Color Depth (bpp)
1
2
4
8
16
32
Solomon Systech
Pixel Increment (y)
32
16
8
4
2
1
Jul 2009
P 92/93
Rev 1.0
SSD1926
Application Note
Floating Window End Position X Register 0
Bit
Type
Reset
state
7
Floating
Window
End X
Position Bit
7
RW
0
6
Floating
Window
End X
Position Bit
6
RW
0
5
Floating
Window
End X
Position Bit
5
RW
0
REG[8Ch]
4
Floating
Window
End X
Position Bit
4
RW
0
3
Floating
Window
End X
Position Bit
3
RW
0
2
Floating
Window
End X
Position Bit
2
RW
0
1
Floating
Window
End X
Position Bit
1
RW
0
1
Floating
Window
End X
Position Bit
9
RW
0
Floating Window End Position X Register 1
REG[8Dh]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[8Dh] bits 1-0,
REG[8Ch] bits 7-0
0
Floating
Window
End X
Position Bit
0
RW
0
0
Floating
Window
End X
Position Bit
8
RW
0
Floating Window End Position X Bits [9:0]
These bits determine the end position X of the floating window in relation to the origin of the
panel. Due to the SSD1926 Display Rotate feature, the end position X may not be a horizontal
position value (only true in 0° and 180° rotation). For further information on defining the value
of the End Position X register, see “Floating Window Mode” in datasheet.
The value of register is also increased according to the display orientation. For 0° and 180°
Display Rotate Mode, the end position X is incremented by x pixels where x is relative to the
current color depth. Refer to Table 2-23: 32-bit Address X Increments for Various Color
Depths. For 90° and 270° Display Rotate Mode, the end position X is incremented by 1 line.
Depending on the color depth, some of the higher bits in this register are unused because the
maximum horizontal display width is 1024 pixels.
Note
(1)
These bits will not effective until the Floating Window Enable bit is set to 1 (REG[71h] bit
4=1).
Table 2-23: 32-bit Address X Increments for Various Color Depths
Color Depth (bpp)
1
2
4
8
16
32
SSD1926
Application Note
Rev 1.0
P 93/94
Jul 2009
Pixel Increment (x)
32
16
8
4
2
1
Solomon Systech
Floating Window End Position Y Register 0
Bit
Type
Reset
state
7
Floating
Window
End Y
Position Bit
7
RW
0
6
Floating
Window
End Y
Position Bit
6
RW
0
5
Floating
Window
End Y
Position Bit
5
RW
0
REG[90h]
4
Floating
Window
End Y
Position Bit
4
RW
0
3
Floating
Window
End Y
Position Bit
3
RW
0
2
Floating
Window
End Y
Position Bit
2
RW
0
1
Floating
Window
End Y
Position Bit
1
RW
0
1
Floating
Window
End Y
Position Bit
9
RW
0
Floating Window End Position Y Register 1
REG[91h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
NA
0
NA
0
NA
0
NA
0
NA
0
NA
0
REG[91h] bits 1-0,
REG[90h] bits 7-0
0
Floating
Window
End Y
Position Bit
0
RW
0
0
Floating
Window
End Y
Position Bit
8
RW
0
Floating Window End Position Y Bits [9:0]
These bits determine the end position Y of the floating window in relation to the origin of the
panel. Due to the SSD1926 Display Rotate feature, the end position Y may not be a vertical
position value (only true in 0° and 180° Display Rotate Mode). For further information on
defining the value of the End Position Y register, see Section “Floating Window Mode” in
datasheet.
The value of register is also increased according to the display orientation. For 0° and 180°
Display Rotate Mode, the end position Y is incremented by 1 line. For 90° and 270° Display
Rotate Mode, the end position Y is incremented by y pixels where y is relative to the current
color depth. Refer to Table 2-24: 32-bit Address Y Increments for Various Color Depths.
Depending on the color depth, some of the higher bits in this register are unused because the
maximum vertical display height is 1024 pixels.
Note
(1)
These bits will not effective until the Floating Window Enable bit is set to 1 (REG[71h] bit
4=1).
Table 2-24: 32-bit Address Y Increments for Various Color Depths
Color Depth (bpp)
1
2
4
8
16
32
Solomon Systech
Pixel Increment (y)
32
16
8
4
2
1
Jul 2009
P 94/95
Rev 1.0
SSD1926
Application Note
2.16 Cursor Mode
This mode enables two cursors on the main display window. The cursors can be positioned anywhere within
the display and are controlled through Cursor Mode registers (REG[C0h] through REG[111h]). Cursor
support is available only at 4/8/16/32-bpp display modes.
Each cursor pixel is 2-bit and the indexing scheme is as follows:
Table 2-25: Indexing scheme for Hardware Cursor
Value
00
01
10
11
Color of Cursor 1 / Cursor 2
Transparent
(REG[E31h-E0h] / REG[10Bh-108h])
(REG[E7h-E4h] / REG[10Fh-10Ch])
(REG[EBh-E8h] / REG[1131h-110h])
Content of color index 1 register
Content of color index 2 register
Content of color index 3 register
Three 16-bit color index registers (REG[E0h] through REG[E9h] and REG[108h] through REG[111h]) have
been implemented for each cursor. Only the lower portion of the color index register is used in 4/8-bpp
display modes. The LUT is bypassed and the color data is directly mapped for 16/32-bpp display mode.
4 Bit-per-pixel
15
12
11
8
7
4
3
Don’t Care
0
4-bit Color Index
8 Bit-per-pixel
15
12
11
8
7
Don’t Care
4
3
0
8-bit Color Index
16 Bit-per-pixel (the index registers represents the 16-bit color component)
15
13
Green Component
Bits 2-0
12
8
7
Blue Component
Bits 4-0
3
Red Component
Bits 4-0
2
0
Green Component
Bits 5-3
32 Bit-per-pixel (the index registers represents the 32-bit color component)
31
24
23
Alpha Component
Bits 7-0
16
Blue Component
Bits 5-3
15
8
Green Component
Bits 7-0
7
0
Red Component
Bits 5-3
The display precedence is Cursor1 > Cursor2 > Floating window > Main Window.
SSD1926
Application Note
Rev 1.0
P 95/96
Jul 2009
Solomon Systech
Cursor 1
Cursor 2
Floating Window
Main Window
Figure 2-30: Display Precedence in Hardware Cursor
Note
(1)
The minimum size varies for different color depths and display orientations.
The cursors retains the same color depth and display orientation as the main window. The following diagram
shows an example of two cursors within a main window and the registers used to position it.
Cursor1 Position Y
(REG[D5h],REG[D4h])
Cursor2 Position Y
(REG[FDh],REG[FCh])
panel’s origin
Main-Window
Cursor1 Position X
(REG[D1h],REG[D0h])
Cursor1
Cursor2
Cursor2 Position X
(REG[F9h],REG[F8h])
Figure 2-31: Cursors on the main window
Assume the pixel data stores start at address n, which n must be divisible by 4 (i.e. aligned to 32-bit
boundary). In this example, a 16x16 cursor is displayed which each cursor index is defined by x and y
coordinate, C(y,x). Following are the pixel format.
Solomon Systech
Jul 2009
P 96/97
Rev 1.0
SSD1926
Application Note
For 4/8/16 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
n+4
6
5
C(0,0)
C(0,4)
C(0,8)
C(0,12)
C(1,0)
4
C(0,1)
C(0,5)
C(0,9)
C(0,13)
C(1,1)
3
2
1
0
C(0,2)
C(0,6)
C(0,10)
C(0,14)
C(1,2)
C(0,3)
C(0,7)
C(0,11)
C(0,15)
C(1,3)
C(15,2)
C(15,6)
C(15,10)
C(15,14)
C(15,3)
C(15,7)
C(15,11)
C(15,15)
.
.
.
Addr.
Addr.
Addr.
Addr.
n + 60
n + 61
n + 62
n + 63
C(15,0)
C(15,4)
C(15,8)
C(15,12)
C(15,1)
C(15,5)
C(15,9)
C(15,13)
2.16.1.1 Cursor with 90°° Display Rotate Mode
Cursor1 Position X
(REG[D1h],REG[D0h])
Cursor2 Position X
(REG[F9h],REG[F8h])
panel’s origin
Cursor1
Cursor1 Position Y
(REG[D5h],REG[D4h])
Cursor2
Main-Window
Cursor2 Position Y
(REG[FDh],REG[FCh])
Figure 2-32: Cursors with Display Rotate Mode 90°° enabled
Assume the pixel data stores start at address n, which n must be divisible by 4 (i.e. aligned to 32-bit
boundary). In this example, a 16x16 cursor is displayed which each cursor index is defined x and y
coordinate, C(y,x). Following are the pixel format.
SSD1926
Application Note
Rev 1.0
P 97/98
Jul 2009
Solomon Systech
For 4 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
6
5
C(0,8)
C(0,12)
C(1,8)
C(1,12)
4
3
C(0,9)
C(0,13)
C(1,9)
C(1,13)
2
1
0
C(0,10)
C(0,14)
C(1,10)
C(1,14)
C(0,11)
C(0,15)
C(1,11)
C(1,15)
C(14,10)
C(14,14)
C(15,10)
C(15,14)
C(0,2)
C(0,6)
C(1,2)
C(1,6)
C(14,11)
C(14,15)
C(15,11)
C(15,15)
C(0,3)
C(0,7)
C(1,3)
C(1,7)
C(14,2)
C(14,6)
C(15,2)
C(15,6)
C(14,3)
C(14,7)
C(15,3)
C(15,7)
.
.
.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
n + 28
n + 29
n + 30
n + 31
n + 32
n + 33
n + 34
n + 35
C(14,8)
C(14,12)
C(15,8)
C(15,12)
C(0,0)
C(0,4)
C(1,0)
C(1,4)
C(14,9)
C(14,13)
C(15,9)
C(15,13)
C(0,1)
C(0,5)
C(1,1)
C(1,5)
.
.
.
Addr.
Addr.
Addr.
Addr.
n + 60
n + 61
n + 62
n + 63
C(14,0)
C(14,4)
C(15,0)
C(15,4)
C(14,1)
C(14,5)
C(15,1)
C(15,5)
For 8 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
6
C(0,12)
C(1,12)
C(2,12)
C(3,12)
5
4
C(0,13)
C(1,13)
C(2,13)
C(3,13)
3
2
1
0
C(0,14)
C(1,14)
C(2,14)
C(3,14)
C(0,15)
C(1,15)
C(2,15)
C(3,15)
C(12,14)
C(13,14)
C(14,14)
C(15,14)
C(0,10)
C(1,10)
C(2,10)
C(3,10)
C(12,15)
C(13,15)
C(14,15)
C(15,15)
C(0,11)
C(1,11)
C(2,11)
C(3,11)
C(12,2)
C(13,2)
C(14,2)
C(15,2)
C(12,3)
C(13,3)
C(14,3)
C(15,3)
.
.
.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
n + 12
n + 13
n + 14
n + 15
n + 16
n + 17
n + 18
n + 19
C(12,12)
C(13,12)
C(14,12)
C(15,12)
C(0,8)
C(1,8)
C(2,8)
C(3,8)
C(12,13)
C(13,13)
C(14,13)
C(15,13)
C(0,9)
C(1,9)
C(2,9)
C(3,9)
.
.
.
Addr.
Addr.
Addr.
Addr.
n + 60
n + 61
n + 62
n + 63
Solomon Systech
C(12,0)
C(13,0)
C(14,0)
C(15,0)
C(12,1)
C(13,1)
C(14,1)
C(15,1)
Jul 2009
P 98/99
Rev 1.0
SSD1926
Application Note
For 16 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n + 10
n + 11
6
5
C(0,14)
C(2,14)
C(4,14)
C(6,14)
C(8,14)
C(10,14)
C(12,14)
C(14,14)
C(0,12)
C(2,12)
C(4,12)
C(6,12)
4
C(0,15)
C(2,15)
C(4,15)
C(6,15)
C(8,15)
C(10,15)
C(12,15)
C(14,15)
C(0,13)
C(2,13)
C(4,13)
C(6,13)
3
2
1
0
C(1,14)
C(3,14)
C(5,14)
C(7,14)
C(9,14)
C(11,14)
C(12,14)
C(15,14)
C(1,12)
C(3,12)
C(5,12)
C(7,12)
C(1,15)
C(3,15)
C(5,15)
C(7,15)
C(9,15)
C(11,15)
C(12,15)
C(15,15)
C(1,13)
C(3,13)
C(5,13)
C(7,13)
C(9,0)
C(11,0)
C(12,0)
C(15,0)
C(9,1)
C(11,1)
C(12,1)
C(15,1)
.
.
.
Addr.
Addr.
Addr.
Addr.
n + 60
n + 61
n + 62
n + 63
C(8,0)
C(10,0)
C(12,0)
C(14,0)
C(8,1)
C(10,1)
C(12,1)
C(14,1)
2.16.1.2 Cursor with 180°° Display Rotate Mode
Cursor2 Position X
(REG[F9h],REG[F8h])
Cursor1 Position X
(REG[D1h],REG[D0h])
Main-Window
Cursor1
Cursor2
Cursor2 Position Y
(REG[FDh],REG[FCh])
Cursor1 Position Y
(REG[D5h],REG[D4h])
panel’s origin
Figure 2-33: Cursors with Display Rotate Mode 180°° enabled
Assume the pixel data stores start at address n, which n must be divisible by 4 (i.e. aligned to 32-bit
boundary). In this example, a 16x16 cursor is displayed which each cursor index is defined by x and y
coordinate, C(y,x). Following are the pixel format.
SSD1926
Application Note
Rev 1.0
P 99/100
Jul 2009
Solomon Systech
For 4 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
n+4
6
5
C(15,8)
C(15,12)
C(15,0)
C(15,4)
C(14,8)
4
3
C(15,9)
C(15,13)
C(15,1)
C(15,5)
C(14,9)
2
1
0
C(15,10)
C(15,14)
C(15,2)
C(15,6)
C(14,10)
C(15,11)
C(15,15)
C(15,3)
C(15,7)
C(14,11)
C(0,10)
C(0,14)
C(0,2)
C(0,6)
C(0,11)
C(0,15)
C(0,3)
C(0,7)
.
.
.
Addr.
Addr.
Addr.
Addr.
n + 60
n + 61
n + 62
n + 63
C(0,8)
C(0,12)
C(0,0)
C(0,4)
C(0,9)
C(0,13)
C(0,1)
C(0,5)
For 8 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
n+4
6
5
C(15,12)
C(15,8)
C(15,4)
C(15,0)
C(14,12)
4
3
C(15,13)
C(15,9)
C(15,5)
C(15,1)
C(14,13)
2
1
0
C(15,14)
C(15,10)
C(15,6)
C(15,2)
C(14,14)
C(15,15)
C(15,11)
C(15,7)
C(15,3)
C(14,15)
C(0,14)
C(0,10)
C(0,6)
C(0,2)
C(0,15)
C(0,11)
C(0,7)
C(0,3)
.
.
.
Addr.
Addr.
Addr.
Addr.
n + 60
n + 61
n + 62
n + 63
C(0,12)
C(0,8)
C(0,4)
C(0,0)
C(0,13)
C(0,9)
C(0,5)
C(0,1)
For 16 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
n+4
6
C(15,14)
C(15,10)
C(15,6)
C(15,2)
C(14,14)
5
4
C(15,15)
C(15,11)
C(15,7)
C(15,3)
C(14,15)
3
2
1
0
C(15,12)
C(15,8)
C(15,4)
C(15,0)
C(14,12)
C(15,13)
C(15,9)
C(15,5)
C(15,1)
C(14,13)
C(0,12)
C(0,8)
C(0,4)
C(0,0)
C(0,13)
C(0,9)
C(0,5)
C(0,1)
.
.
.
Addr.
Addr.
Addr.
Addr.
n + 60
n + 61
n + 62
n + 63
Solomon Systech
C(0,14)
C(0,10)
C(0,6)
C(0,2)
C(0,15)
C(0,11)
C(0,7)
C(0,3)
Jul 2009
P 100/101
Rev 1.0
SSD1926
Application Note
2.16.2 Cursor with 270°° Display Rotate Mode
Cursor1 Position Y
(REG[D5h],REG[D4h])
Main-Window
Cursor2 Position Y
(REG[FDh],REG[FCh])
Cursor1
Cursor2
Cursor1 Position X
(REG[D1h],REG[D0h])
Cursor2 Position X
(REG[F9h],REG[F8h])
panel’s origin
Figure 2-34: Cursors with Display Rotate Mode 270°° enabled
Assume the pixel data stores start at address n, which n must be divisible by 4 (i.e. aligned to 32-bit
boundary). In this example, a 16x16 cursor is displayed which each cursor index is defined by x and y
coordinate, C(y,x). Following are the pixel format.
Fro 4 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
6
5
C(15,0)
C(15,4)
C(14,0)
C(14,4)
4
C(15,1)
C(15,5)
C(14,1)
C(14,5)
3
2
1
0
C(15,2)
C(15,6)
C(14,2)
C(14,6)
C(15,3)
C(15,7)
C(14,3)
C(14,7)
C(1,2)
C(1,6)
C(0,2)
C(0,6)
C(15,10)
C(15,14)
C(14,10)
C(14,14)
C(1,3)
C(1,7)
C(0,3)
C(0,7)
C(15,11)
C(15,15)
C(14,11)
C(14,15)
C(1,10)
C(1,14)
C(0,10)
C(0,14)
C(1,11)
C(1,15)
C(0,11)
C(0,15)
.
.
.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
n + 28
n + 29
n + 30
n + 31
n + 32
n + 33
n + 34
n + 35
C(1,0)
C(1,4)
C(0,0)
C(0,4)
C(15,8)
C(15,12)
C(14,8)
C(14,12)
C(1,1)
C(1,5)
C(0,1)
C(0,5)
C(15,9)
C(15,13)
C(14,9)
C(14,13)
.
.
.
Addr.
Addr.
Addr.
Addr.
SSD1926
Application Note
n + 60
n + 61
n + 62
n + 63
Rev 1.0
C(1,8)
C(1,12)
C(0,8)
C(0,12)
P 101/102
C(1,9)
C(1,13)
C(0,9)
C(0,13)
Jul 2009
Solomon Systech
For 8 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
6
5
C(15,0)
C(14,0)
C(13,0)
C(12,0)
4
3
C(15,1)
C(14,1)
C(13,1)
C(12,1)
2
1
0
C(15,2)
C(14,2)
C(13,2)
C(12,2)
C(15,3)
C(14,3)
C(13,3)
C(12,3)
C(3,2)
C(2,2)
C(1,2)
C(0,2)
C(15,6)
C(14,6)
C(13,6)
C(12,6)
C(3,3)
C(2,3)
C(1,3)
C(0,3)
C(15,7)
C(14,7)
C(13,7)
C(12,7)
C(3,14)
C(2,14)
C(1,14)
C(0,14)
C(3,15)
C(2,15)
C(1,15)
C(0,15)
.
.
.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
n + 12
n + 13
n + 14
n + 15
n + 16
n + 17
n + 18
n + 19
C(3,0)
C(2,0)
C(1,0)
C(0,0)
C(15,4)
C(14,4)
C(13,4)
C(12,4)
C(3,1)
C(2,1)
C(1,1)
C(0,1)
C(15,5)
C(14,5)
C(13,5)
C(12,5)
.
.
.
Addr.
Addr.
Addr.
Addr.
n + 60
n + 61
n + 62
n + 63
C(3,12)
C(2,12)
C(1,12)
C(0,12)
C(3,13)
C(2,13)
C(1,13)
C(0,13)
For 16 Bit-per-pixel
7
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
Addr.
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n + 10
n + 11
6
C(15,0)
C(13,0)
C(11,0)
C(9,0)
C(7,0)
C(5,0)
C(3,0)
C(1,0)
C(15,2)
C(13,2)
C(11,2)
C(9,2)
5
4
C(15,1)
C(13,1)
C(11,1)
C(9,1)
C(7,1)
C(5,1)
C(3,1)
C(1,1)
C(15,3)
C(13,3)
C(11,3)
C(9,3)
3
2
1
0
C(14,0)
C(12,0)
C(10,0)
C(8,0)
C(6,0)
C(4,0)
C(2,0)
C(0,0)
C(14,2)
C(12,2)
C(10,2)
C(8,2)
C(14,1)
C(12,1)
C(10,1)
C(8,1)
C(6,1)
C(4,1)
C(2,1)
C(0,1)
C(14,3)
C(12,3)
C(10,3)
C(8,3)
C(6,14)
C(4,14)
C(2,14)
C(0,14)
C(6,15)
C(4,15)
C(2,15)
C(0,15)
.
.
.
Addr.
Addr.
Addr.
Addr.
n + 60
n + 61
n + 62
n + 63
Solomon Systech
C(7,14)
C(5,14)
C(3,14)
C(1,14)
C(7,15)
C(5,15)
C(3,15)
C(1,15)
Jul 2009
P 102/103
Rev 1.0
SSD1926
Application Note
Cursor Feature Register
Bit
Type
Reset
state
7
Cursor1
Enable
RW
0
6
Cursor2
Enable
RW
0
Bit 7
REG[C0h]
5
0
4
0
3
0
2
0
1
0
0
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Cursor1 Enable
When this bit = 0 Cursor1 is disabled.
When this bit = 1 Cursor1 is enabled.
Cursor2 Enable
When this bit = 0, Cursor2 is disabled.
When this bit = 1, Cursor2 is enabled.
Bit 6
Note
(1)
This register is effective for 4/8/16/32 bpp (REG[70h] Bits 2:0 = 010/011/100/101)
Cursor1 Blink Total Register 0
Bit
Type
Reset
state
7
Cursor1
Blink Total
Bit 7
RW
0
6
Cursor1
Blink Total
Bit 6
RW
0
5
Cursor1
Blink Total
Bit 5
RW
0
REG[C4h]
4
Cursor1
Blink Total
Bit 4
RW
0
3
Cursor1
Blink Total
Bit 3
RW
0
2
Cursor1
Blink Total
Bit 2
RW
0
1
Cursor1
Blink Total
Bit 1
RW
0
1
Cursor1
Blink Total
Bit 9
RW
0
Cursor1 Blink Total Register 1
REG[C5h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[C5h] bits 1-0,
REG[C4h] bits 7-0
0
Cursor1
Blink Total
Bit 0
RW
0
0
Cursor1
Blink Total
Bit 8
RW
0
Cursor1 Blink Total Bits [9:0]
This is the total blinking period per frame for cursor1. This register must be set to a non-zero
value in order to make the cursor visible.
Note
(1)
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
SSD1926
Application Note
Rev 1.0
P 103/104
Jul 2009
Solomon Systech
Cursor1 Blink On Register 0
Bit
Type
Reset
state
7
Cursor1
Blink On
Bit 7
RW
0
6
Cursor1
Blink On
Bit 6
RW
0
REG[C8h]
5
Cursor1
Blink On
Bit 5
RW
0
4
Cursor1
Blink On
Bit 4
RW
0
3
Cursor1
Blink On
Bit 3
RW
0
2
Cursor1
Blink On
Bit 2
RW
0
1
Cursor1
Blink On
Bit 1
RW
0
Cursor1 Blink On Register 1
REG[C9h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[C9h] bits 1-0,
REG[C8h] bits 7-0
0
Cursor1
Blink On
Bit 0
RW
0
1
Cursor1
Blink On
Bit 9
RW
0
0
Cursor1
Blink On
Bit 8
RW
0
Cursor1 Blink On Bits [9:0]
This is the blink on frame period for Cursor1.
This register must be set to a non-zero value in order to make the cursor1 visible. Also, cursor1
will start to blink if the following conditions are fulfilled :
Cursor1 Blink Total Bits [9:0] > Cursor1 Blink On Bits [9:0] > 0
To enable cursor1 without blinking, user must program cursor1 blink on register with a nonzero value, and this value must be greater than or equal to Cursor1 Blink Total Register.
Cursor1 Blink On Bits [9:0] > Cursor1 Blink Total Bits [9:0] > 0
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
Cursor1 Memory Start Register 0
Bit
Type
Reset
state
7
Cursor1
Memory
Start Bit 7
RW
0
6
Cursor1
Memory
Start Bit 6
RW
0
5
Cursor1
Memory
Start Bit 5
RW
0
REG[CCh]
4
Cursor1
Memory
Start Bit 4
RW
0
3
Cursor1
Memory
Start Bit 3
RW
0
2
Cursor1
Memory
Start Bit 2
RW
0
4
Cursor1
Memory
Start Bit 12
RW
0
3
Cursor1
Memory
Start Bit 11
RW
0
2
Cursor1
Memory
Start Bit 10
RW
0
Cursor1 Memory Start Register 1
Bit
Type
Reset
state
7
Cursor1
Memory
Start Bit 15
RW
0
6
Cursor1
Memory
Start Bit 14
RW
0
5
Cursor1
Memory
Start Bit 13
RW
0
1
Cursor1
Memory
Start Bit 1
RW
0
REG[CDh]
Cursor1 Memory Start Register 2
1
Cursor1
Memory
Start Bit 9
RW
0
0
Cursor1
Memory
Start Bit 8
RW
0
REG[CEh]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Solomon Systech
0
Cursor1
Memory
Start Bit 0
RW
0
Jul 2009
P 104/105
Rev 1.0
0
Cursor1
Memory
Start Bit 16
RW
0
SSD1926
Application Note
REG[CEh] bit 0,
REG[CDh] bits 7-0,
REG[CCh] bits 7-0
Cursor1 Memory Start Bits [16:0]
These bits form the 17-bit address for the starting double-word of the LCD image in the display
buffer for the Cursor1 image.
Note
(1)
That this is a double-word (32-bit) address.
An entry of 00000h into these registers represents the first double-word of display memory, an
entry of 00001h represents the second double-word of the display memory, and so on.
Calculate the Cursor1 Start Address as follows :
Cursor1 Memory Start Bits 16:0
= Cursor Image address ÷ 4 (valid only for Display Rotate Mode 0°)
Note
(1)
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
Cursor1 Position X Register 0
Bit
Type
Reset
state
7
Cursor1
Position X
Bit 7
RW
0
6
Cursor1
Position X
Bit 6
RW
0
REG[D0h]
5
Cursor1
Position X
Bit 5
RW
0
4
Cursor1
Position X
Bit 4
RW
0
3
Cursor1
Position X
Bit 3
RW
0
2
Cursor1
Position X
Bit 2
RW
0
Cursor1 Position X Register 1
0
Cursor1
Position X
Bit 0
RW
0
REG[D1h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[D1h] bits 1-0,
REG[D0h] bits 7-0
1
Cursor1
Position X
Bit 1
RW
0
1
Cursor1
Position X
Bit 9
RW
0
0
Cursor1
Position X
Bit 8
RW
0
Cursor1 Position X Bits [9:0]
This is starting position X of Cursor1 image. The definition of this register is same as Floating
Window Start Position X Register.
Note
(1)
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
Cursor1 Position Y Register 0
Bit
Type
Reset
state
7
Cursor1
Position Y
Bit 7
RW
0
6
Cursor1
Position Y
Bit 6
RW
0
REG[D4h]
5
Cursor1
Position Y
Bit 5
RW
0
4
Cursor1
Position Y
Bit 4
RW
0
3
Cursor1
Position Y
Bit 3
RW
0
2
Cursor1
Position Y
Bit 2
RW
0
Cursor1 Position Y Register 1
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Rev 1.0
P 105/106
0
Cursor1
Position Y
Bit 0
RW
0
REG[D5h]
Bit
SSD1926
Application Note
1
Cursor1
Position Y
Bit 1
RW
0
Jul 2009
1
Cursor1
Position Y
Bit 9
RW
0
0
Cursor1
Position Y
Bit 8
RW
0
Solomon Systech
REG[D5h] bits 1-0,
REG[D4h] bits 7-0
Cursor1 Position Y Bits [9:0]
This is starting position Y of Cursor1 image. The definition of this register is same as Floating
Window Y Start Position Register.
Note
(1)
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
Cursor1 Horizontal Size Register 0
Bit
Type
Reset
state
7
Cursor1
Horizontal
Size Bit 7
RW
0
6
Cursor1
Horizontal
Size Bit 6
RW
0
5
Cursor1
Horizontal
Size Bit 5
RW
0
REG[D8h]
4
Cursor1
Horizontal
Size Bit 4
RW
0
3
Cursor1
Horizontal
Size Bit 3
RW
0
2
Cursor1
Horizontal
Size Bit 2
RW
0
1
Cursor1
Horizontal
Size Bit 1
RW
0
Cursor1 Horizontal Size Register 1
REG[D9h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[D9h] bits 1-0,
REG[D8h] bits 7-0
0
Cursor1
Horizontal
Size Bit 0
RW
0
1
Cursor1
Horizontal
Size Bit 9
RW
0
0
Cursor1
Horizontal
Size Bit 8
RW
0
Cursor1 Horizontal Size Bits [9:0]
These bits specify the horizontal size of Cursor1.
Note
The definition of this register various under different panel orientation and color depth settings.
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
Table 2-26: X Increment Mode for Various Color Depths
Orientation
0˚
0˚
90˚
90˚
180˚
90˚
270˚
90˚
Solomon Systech
Main window Color
Depth (bpp)
4
8
16
32
4
8
16
32
4
8
16
32
4
8
16
32
Increment (x)
16 pixels increment
e.g. 0000h = 16 pixels; 0001h = 32 pixels
16 pixels increment
e.g. 0000h = 16 pixels; 0001h = 32 pixels
2 lines increment
4 lines increment
8 lines increment
16 lines increment
16 pixels increment
2 lines increment
2 lines increment
4 lines increment
8 lines increment
16 lines increment
Jul 2009
P 106/107
Rev 1.0
SSD1926
Application Note
Cursor1 Vertical Size Register 0
Bit
Type
Reset
state
7
Cursor1
Vertical
Size Bit 7
RW
0
6
Cursor1
Vertical
Size Bit 6
RW
0
5
Cursor1
Vertical
Size Bit 5
RW
0
REG[DCh]
4
Cursor1
Vertical
Size Bit 4
RW
0
3
Cursor1
Vertical
Size Bit 3
RW
0
2
Cursor1
Vertical
Size Bit 2
RW
0
Cursor1 Vertical Size Register 1
0
Cursor1
Vertical
Size Bit 0
RW
0
REG[DDh]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[DDh] bits 1-0,
REG[DCh] bits 7-0
1
Cursor1
Vertical
Size Bit 1
RW
0
1
Cursor1
Vertical
Size Bit 9
RW
0
0
Cursor1
Vertical
Size Bit 8
RW
0
Cursor1 Vertical Size Bits [9:0]
These bits specify the vertical size of Cursor1.
Note
(1)
The definition of this register various under different panel orientation and color depth
settings.
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
Table 2-27: Y Increment Mode for Various Color Depths
Orientation
0˚
90˚
180˚
270˚
SSD1926
Application Note
Rev 1.0
Main window Color
Depth (bpp)
4
8
16
32
4
8
16
32
4
8
16
32
4
8
16
32
P 107/108
Jul 2009
Increment (y)
1 line increment
e.g. 0000h = 1 line; 0001h = 2 lines
8 pixels increment
4 pixels increment
2 pixels increment
1 pixel increment
1 line increment
8 pixels increment
4 pixels increment
2 pixels increment
1 pixel increment
Solomon Systech
Cursor1 Color Index1 Register 0
Bit
Type
Reset
state
7
Cursor1
Color
Index1 Bit
7
RW
0
6
Cursor1
Color
Index1 Bit
6
RW
0
5
Cursor1
Color
Index1 Bit
5
RW
0
REG[E0h]
4
Cursor1
Color
Index1 Bit
4
RW
0
3
Cursor1
Color
Index1 Bit
3
RW
0
2
Cursor1
Color
Index1 Bit
2
RW
0
4
Cursor1
Color
Index1 Bit
12
RW
0
3
Cursor1
Color
Index1 Bit
11
RW
0
2
Cursor1
Color
Index1 Bit
10
RW
0
4
Cursor1
Color
Index1 Bit
20
RW
0
3
Cursor1
Color
Index1 Bit
19
RW
0
2
Cursor1
Color
Index1 Bit
18
RW
0
4
Cursor1
Color
Index1 Bit
28
RW
0
3
Cursor1
Color
Index1 Bit
27
RW
0
2
Cursor1
Color
Index1 Bit
26
RW
0
Cursor1 Color Index1 Register 1
Bit
Type
Reset
state
7
Cursor1
Color
Index1 Bit
15
RW
0
6
Cursor1
Color
Index1 Bit
14
RW
0
5
Cursor1
Color
Index1 Bit
13
RW
0
Type
Reset
state
7
Cursor1
Color
Index1 Bit
23
RW
0
6
Cursor1
Color
Index1 Bit
22
RW
0
5
Cursor1
Color
Index1 Bit
21
RW
0
Type
Reset
state
7
Cursor1
Color
Index1 Bit
31
RW
0
REG[E3h] bits 7-0,
REG[E2h] bits 7-0,
REG[E1h] bits 7-0,
REG[E0h] bits 7-0
6
Cursor1
Color
Index1 Bit
30
RW
0
5
Cursor1
Color
Index1 Bit
29
RW
0
1
Cursor1
Color
Index1 Bit
9
RW
0
0
Cursor1
Color
Index1 Bit
8
RW
0
REG[E2h]
Cursor1 Color Index1 Register 3
Bit
0
Cursor1
Color
Index1 Bit
0
RW
0
REG[E1h]
Cursor1 Color Index1 Register 2
Bit
1
Cursor1
Color
Index1 Bit
1
RW
0
1
Cursor1
Color
Index1 Bit
17
RW
0
0
Cursor1
Color
Index1 Bit
16
RW
0
REG[E3h]
1
Cursor1
Color
Index1 Bit
25
RW
0
0
Cursor1
Color
Index1 Bit
24
RW
0
Cursor1 Color Index1 Bits [31:0]
Each cursor pixel is represented by 2 bits. This register stores the color index for pixel value 01
of Cursor1.
Note
(1)
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
For Hardware Cursors operation, see Section “Hardware Cursor Mode” in datasheet.
Solomon Systech
Jul 2009
P 108/109
Rev 1.0
SSD1926
Application Note
Cursor1 Color Index2 Register 0
Bit
Type
Reset
state
7
Cursor1
Color
Index2 Bit
7
RW
0
6
Cursor1
Color
Index2 Bit
6
RW
0
5
Cursor1
Color
Index2 Bit
5
RW
0
REG[E4h]
4
Cursor1
Color
Index2 Bit
4
RW
0
3
Cursor1
Color
Index2 Bit
3
RW
0
2
Cursor1
Color
Index2 Bit
2
RW
0
4
Cursor1
Color
Index2 Bit
12
RW
0
3
Cursor1
Color
Index2 Bit
11
RW
0
2
Cursor1
Color
Index2 Bit
10
RW
0
4
Cursor1
Color
Index2 Bit
20
RW
0
3
Cursor1
Color
Index2 Bit
19
RW
0
2
Cursor1
Color
Index2 Bit
18
RW
0
4
Cursor1
Color
Index2 Bit
28
RW
0
3
Cursor1
Color
Index2 Bit
27
RW
0
2
Cursor1
Color
Index2 Bit
26
RW
0
Cursor1 Color Index2 Register 1
Bit
Type
Reset
state
7
Cursor1
Color
Index2 Bit
15
RW
0
6
Cursor1
Color
Index2 Bit
14
RW
0
5
Cursor1
Color
Index2 Bit
13
RW
0
Type
Reset
state
7
Cursor1
Color
Index2 Bit
23
RW
0
6
Cursor1
Color
Index2 Bit
22
RW
0
5
Cursor1
Color
Index2 Bit
21
RW
0
Type
Reset
state
7
Cursor1
Color
Index2 Bit
31
RW
0
6
Cursor1
Color
Index2 Bit
30
RW
0
REG[E7h] bits 7-0,
REG[E6h] bits 7-0,
REG[E5h] bits 7-0,
REG[E4h] bits 7-0
5
Cursor1
Color
Index2 Bit
29
RW
0
1
Cursor1
Color
Index2 Bit
9
RW
0
0
Cursor1
Color
Index2 Bit
8
RW
0
REG[E6h]
Cursor1 Color Index2 Register 3
Bit
0
Cursor1
Color
Index2 Bit
0
RW
0
REG[E5h]
Cursor1 Color Index2 Register 2
Bit
1
Cursor1
Color
Index2 Bit
1
RW
0
1
Cursor1
Color
Index2 Bit
17
RW
0
0
Cursor1
Color
Index2 Bit
16
RW
0
REG[E7h]
1
Cursor1
Color
Index2 Bit
25
RW
0
0
Cursor1
Color
Index2 Bit
24
RW
0
Cursor1 Color Index2 Bits [31:0]
Each cursor pixel is represented by 2 bits. This register stores the color index for pixel value 10
of Cursor1.
Note
(1)
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
For Hardware Cursors operation, see Section “Hardware Cursor Mode” in datasheet.
SSD1926
Application Note
Rev 1.0
P 109/110
Jul 2009
Solomon Systech
Cursor1 Color Index3 Register 0
Bit
Type
Reset
state
7
Cursor1
Color
Index3 Bit
7
RW
0
6
Cursor1
Color
Index3 Bit
6
RW
0
5
Cursor1
Color
Index3 Bit
5
RW
0
REG[E8h]
4
Cursor1
Color
Index3 Bit
4
RW
0
3
Cursor1
Color
Index3 Bit
3
RW
0
2
Cursor1
Color
Index3 Bit
2
RW
0
4
Cursor1
Color
Index3 Bit
12
RW
0
3
Cursor1
Color
Index3 Bit
11
RW
0
2
Cursor1
Color
Index3 Bit
10
RW
0
4
Cursor1
Color
Index3 Bit
20
RW
0
3
Cursor1
Color
Index3 Bit
19
RW
0
2
Cursor1
Color
Index3 Bit
18
RW
0
4
Cursor1
Color
Index3 Bit
28
RW
0
3
Cursor1
Color
Index3 Bit
27
RW
0
2
Cursor1
Color
Index3 Bit
26
RW
0
Cursor1 Color Index3 Register 1
Bit
Type
Reset
state
7
Cursor1
Color
Index3 Bit
15
RW
0
6
Cursor1
Color
Index3 Bit
14
RW
0
5
Cursor1
Color
Index3 Bit
13
RW
0
Type
Reset
state
7
Cursor1
Color
Index3 Bit
23
RW
0
6
Cursor1
Color
Index3 Bit
22
RW
0
5
Cursor1
Color
Index3 Bit
21
RW
0
Type
Reset
state
7
Cursor1
Color
Index3 Bit
31
RW
0
REG[EBh] bits 7-0,
REG[EAh] bits 7-0,
REG[E9h] bits 7-0,
REG[E8h] bits 7-0
6
Cursor1
Color
Index3 Bit
30
RW
0
5
Cursor1
Color
Index3 Bit
29
RW
0
1
Cursor1
Color
Index3 Bit
9
RW
0
0
Cursor1
Color
Index3 Bit
8
RW
0
REG[EAh]
Cursor1 Color Index3 Register 3
Bit
0
Cursor1
Color
Index3 Bit
0
RW
0
REG[E9h]
Cursor1 Color Index3 Register 2
Bit
1
Cursor1
Color
Index3 Bit
1
RW
0
1
Cursor1
Color
Index3 Bit
17
RW
0
0
Cursor1
Color
Index3 Bit
16
RW
0
REG[EBh]
1
Cursor1
Color
Index3 Bit
25
RW
0
0
Cursor1
Color
Index3 Bit
24
RW
0
Cursor1 Color Index3 Bits [31:0]
Each cursor pixel is represented by 2 bits. This register stores the color index for pixel value 11
of Cursor1.
Note
(1)
These bits will not effective until the Cursor1 Enable bit is set to 1 (REG[C0h] bit 7=1).
For Hardware Cursors operation, see Section “Hardware Cursor Mode” in datasheet.
Solomon Systech
Jul 2009
P 110/111
Rev 1.0
SSD1926
Application Note
Cursor2 Blink Total Register 0
Bit
Type
Reset
state
7
Cursor2
Blink Total
Bit 7
RW
0
6
Cursor2
Blink Total
Bit 6
RW
0
REG[ECh]
5
Cursor2
Blink Total
Bit 5
RW
0
4
Cursor2
Blink Total
Bit 4
RW
0
3
Cursor2
Blink Total
Bit 3
RW
0
2
Cursor2
Blink Total
Bit 2
RW
0
1
Cursor2
Blink Total
Bit 1
RW
0
Cursor2 Blink Total Register 1
REG[EDh]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[EDh] bits 1-0,
REG[ECh] bits 7-0
0
Cursor2
Blink Total
Bit 0
RW
0
1
Cursor2
Blink Total
Bit 9
RW
0
0
Cursor2
Blink Total
Bit 8
RW
0
Cursor2 Blink Total Bits [9:0]
This is the total blinking period per frame for Cursor2. This register must be set to a non-zero
value in order to make the cursor visible.
Note
(1)
These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).
Cursor2 Blink On Register 0
Bit
Type
Reset
state
7
Cursor2
Blink On
Bit 7
RW
0
6
Cursor2
Blink On
Bit 6
RW
0
REG[F0h]
5
Cursor2
Blink On
Bit 5
RW
0
4
Cursor2
Blink On
Bit 4
RW
0
3
Cursor2
Blink On
Bit 3
RW
0
2
Cursor2
Blink On
Bit 2
RW
0
1
Cursor2
Blink On
Bit 1
RW
0
Cursor2 Blink On Register 1
REG[F1h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[F1h] bits 1-0,
REG[F0h] bits 7-0
0
Cursor2
Blink On
Bit 0
RW
0
1
Cursor2
Blink On
Bit 9
RW
0
0
Cursor2
Blink On
Bit 8
RW
0
Cursor2 Blink On Bits [9:0]
This is the blink on frame period for Cursor2. This register must be set to a non-zero value in
order to make the Cursor2 visible. Also, Cursor2 will start to blink if the following conditions
are fulfilled:
Cursor2 Blink Total Bits [9:0] > Cursor2 Blink On Bits [9:0] > 0
To enable Cursor2 without blinking, user must program Cursor2 Blink On Register with a nonzero value, and this value must be greater than or equal to Cursor2 Blink Total Register.
Cursor2 Blink On Bits [9:0] > Cursor2 Blink Total Bits [9:0] > 0
These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).
SSD1926
Application Note
Rev 1.0
P 111/112
Jul 2009
Solomon Systech
Cursor2 Memory Start Register 0
Bit
Type
Reset
state
7
Cursor2
Memory
Start Bit 7
RW
0
6
Cursor2
Memory
Start Bit 6
RW
0
5
Cursor2
Memory
Start Bit 5
RW
0
REG[F4h]
4
Cursor2
Memory
Start Bit 4
RW
0
3
Cursor2
Memory
Start Bit 3
RW
0
2
Cursor2
Memory
Start Bit 2
RW
0
4
Cursor2
Memory
Start Bit 12
RW
0
3
Cursor2
Memory
Start Bit 11
RW
0
2
Cursor2
Memory
Start Bit 10
RW
0
1
Cursor2
Memory
Start Bit 1
RW
0
Cursor2 Memory Start Register 1
Bit
Type
Reset
state
7
Cursor2
Memory
Start Bit 15
RW
0
6
Cursor2
Memory
Start Bit 14
RW
0
5
Cursor2
Memory
Start Bit 13
RW
0
REG[F5h]
1
Cursor2
Memory
Start Bit 9
RW
0
Cursor2 Memory Start Register 2
0
Cursor2
Memory
Start Bit 8
RW
0
REG[F6h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[F6h] bit 0,
REG[F5h] bits 7-0,
REG[F4h] bits 7-0
0
Cursor2
Memory
Start Bit 0
RW
0
0
Cursor2
Memory
Start Bit 16
RW
0
Cursor2 Memory Start Bits [16:0]
These bits form the 17-bit address for the starting double-word of the LCD image in the display
buffer for the Cursor2 image.
Note that this is a double-word (32-bit) address. An entry of 00000h into these registers
represents the first double-word of display memory, an entry of 00001h represents the second
double-word of the display memory, and so on.
Calculate the Cursor2 Start Address as follows :
Cursor2 Memory Start Bits 16:0
= Cursor Image address ÷ 4 (valid only for Display Rotate Mode 0°)
Note
(1)
These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).
Solomon Systech
Jul 2009
P 112/113
Rev 1.0
SSD1926
Application Note
Cursor2 Position X Register 0
Bit
Type
Reset
state
7
Cursor2
Position X
Bit 7
RW
0
6
Cursor2
Position X
Bit 6
RW
0
REG[F8h]
5
Cursor2
Position X
Bit 5
RW
0
4
Cursor2
Position X
Bit 4
RW
0
3
Cursor2
Position X
Bit 3
RW
0
2
Cursor2
Position X
Bit 2
RW
0
Cursor2 Position X Register 1
0
Cursor2
Position X
Bit 0
RW
0
REG[F9h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[F9h] bits 1-0,
REG[F8h] bits 7-0
1
Cursor2
Position X
Bit 1
RW
0
1
Cursor2
Position X
Bit 9
RW
0
0
Cursor2
Position X
Bit 8
RW
0
Cursor2 Position X Bits [9:0]
This is starting position X of Cursor2 image. The definition of this register is same as Floating
Window Start Position X Register.
Note
(1)
These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).
Cursor2 Position Y Register 0
Bit
Type
Reset
state
7
Cursor2
Position Y
Bit 7
RW
0
6
Cursor2
Position Y
Bit 6
RW
0
REG[FCh]
5
Cursor2
Position Y
Bit 5
RW
0
4
Cursor2
Position Y
Bit 4
RW
0
3
Cursor2
Position Y
Bit 3
RW
0
2
Cursor2
Position Y
Bit 2
RW
0
Cursor2 Position Y Register 1
0
Cursor2
Position Y
Bit 0
RW
0
REG[FDh]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[FDh] bits 1-0,
REG[FCh] bits 7-0
1
Cursor2
Position Y
Bit 1
RW
0
1
Cursor2
Position Y
Bit 9
RW
0
0
Cursor2
Position Y
Bit 8
RW
0
Cursor2 Position Y Bits [9:0]
This is starting position Y of Cursor2 image. The definition of this register is same as Floating
Window Y Start Position Register.
Note
(1)
These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).
SSD1926
Application Note
Rev 1.0
P 113/114
Jul 2009
Solomon Systech
Cursor2 Horizontal Size Register 0
Bit
Type
Reset
state
7
Cursor2
Horizontal
Size Bit 7
RW
0
6
Cursor2
Horizontal
Size Bit 6
RW
0
5
Cursor2
Horizontal
Size Bit 5
RW
0
REG[100h]
4
Cursor2
Horizontal
Size Bit 4
RW
0
3
Cursor2
Horizontal
Size Bit 3
RW
0
2
Cursor2
Horizontal
Size Bit 2
RW
0
Cursor2 Horizontal Size Register 1
0
Cursor2
Horizontal
Size Bit 0
RW
0
REG[101h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[101h] bits 1-0,
REG[100h] bits 7-0
1
Cursor2
Horizontal
Size Bit 1
RW
0
1
Cursor2
Horizontal
Size Bit 9
RW
0
0
Cursor2
Horizontal
Size Bit 8
RW
0
Cursor2 Horizontal Size Bits [9:0]
These bits specify the horizontal size of Cursor2.
Note
(1)
The definition of this register various under different panel orientation and color depth
settings. Refer to Table 2-26.
These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).
Cursor2 Vertical Size Register 0
Bit
Type
Reset
state
7
Cursor2
Vertical
Size Bit 7
RW
0
6
Cursor2
Vertical
Size Bit 6
RW
0
5
Cursor2
Vertical
Size Bit 5
RW
0
REG[104h]
4
Cursor2
Vertical
Size Bit 4
RW
0
3
Cursor2
Vertical
Size Bit 3
RW
0
2
Cursor2
Vertical
Size Bit 2
RW
0
1
Cursor2
Vertical
Size Bit 1
RW
0
Cursor2 Vertical Size Register 1
REG[105h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[105h] bits 1-0,
REG[104h] bits 7-0
0
Cursor2
Vertical
Size Bit 0
RW
0
1
Cursor2
Vertical
Size Bit 9
RW
0
0
Cursor2
Vertical
Size Bit 8
RW
0
Cursor2 Vertical Size Bits [9:0]
These bits specify the vertical size of Cursor2.
Note
(1)
The definition of this register various under different panel orientation and color depth
settings. Refer to Table 2-27.
These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).
Solomon Systech
Jul 2009
P 114/115
Rev 1.0
SSD1926
Application Note
Cursor2 Color Index1 Register 0
Bit
Type
Reset
state
7
Cursor2
Color
Index1 Bit
7
RW
0
6
Cursor2
Color
Index1 Bit
6
RW
0
5
Cursor2
Color
Index1 Bit
5
RW
0
REG[108h]
4
Cursor2
Color
Index1 Bit
4
RW
0
3
Cursor2
Color
Index1 Bit
3
RW
0
2
Cursor2
Color
Index1 Bit
2
RW
0
4
Cursor2
Color
Index1 Bit
12
RW
0
3
Cursor2
Color
Index1 Bit
11
RW
0
2
Cursor2
Color
Index1 Bit
10
RW
0
4
Cursor2
Color
Index1 Bit
20
RW
0
3
Cursor2
Color
Index1 Bit
19
RW
0
2
Cursor2
Color
Index1 Bit
18
RW
0
4
Cursor2
Color
Index1 Bit
28
RW
0
3
Cursor2
Color
Index1 Bit
27
RW
0
2
Cursor2
Color
Index1 Bit
26
RW
0
Cursor2 Color Index1 Register 1
Bit
Type
Reset
state
7
Cursor2
Color
Index1 Bit
15
RW
0
6
Cursor2
Color
Index1 Bit
14
RW
0
5
Cursor2
Color
Index1 Bit
13
RW
0
Type
Reset
state
7
Cursor2
Color
Index1 Bit
23
RW
0
6
Cursor2
Color
Index1 Bit
22
RW
0
5
Cursor2
Color
Index1 Bit
21
RW
0
Type
Reset
state
7
Cursor2
Color
Index1 Bit
31
RW
0
6
Cursor2
Color
Index1 Bit
30
RW
0
REG[10Bh] bits 7-0
REG[10Ah] bits 7-0
REG[109h] bits 7-0
REG[108h] bits 7-0
5
Cursor2
Color
Index1 Bit
29
RW
0
1
Cursor2
Color
Index1 Bit
9
RW
0
0
Cursor2
Color
Index1 Bit
8
RW
0
REG[10Ah]
Cursor2 Color Index1 Register 3
Bit
0
Cursor2
Color
Index1 Bit
0
RW
0
REG[109h]
Cursor2 Color Index1 Register 2
Bit
1
Cursor2
Color
Index1 Bit
1
RW
0
1
Cursor2
Color
Index1 Bit
17
RW
0
0
Cursor2
Color
Index1 Bit
16
RW
0
REG[10Bh]
1
Cursor2
Color
Index1 Bit
25
RW
0
0
Cursor2
Color
Index1 Bit
24
RW
0
Cursor2 Color Index1 Bits [31:0]
Each cursor pixel is represented by 2 bits. This register stores the color index for pixel value 01
of Cursor2.
Note
(1)
These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).
For Hardware Cursors operation, see Section “Hardware Cursor Mode” in datasheet.
SSD1926
Application Note
Rev 1.0
P 115/116
Jul 2009
Solomon Systech
Cursor2 Color Index2 Register 0
Bit
Type
Reset
state
7
Cursor2
Color
Index2 Bit
7
RW
0
6
Cursor2
Color
Index2 Bit
6
RW
0
5
Cursor2
Color
Index2 Bit
5
RW
0
REG[10Ch]
4
Cursor2
Color
Index2 Bit
4
RW
0
3
Cursor2
Color
Index2 Bit
3
RW
0
2
Cursor2
Color
Index2 Bit
2
RW
0
4
Cursor2
Color
Index2 Bit
12
RW
0
3
Cursor2
Color
Index2 Bit
11
RW
0
2
Cursor2
Color
Index2 Bit
10
RW
0
4
Cursor2
Color
Index2 Bit
20
RW
0
3
Cursor2
Color
Index2 Bit
19
RW
0
2
Cursor2
Color
Index2 Bit
18
RW
0
4
Cursor2
Color
Index2 Bit
28
RW
0
3
Cursor2
Color
Index2 Bit
27
RW
0
2
Cursor2
Color
Index2 Bit
26
RW
0
Cursor2 Color Index2 Register 1
Bit
Type
Reset
state
7
Cursor2
Color
Index2 Bit
15
RW
0
6
Cursor2
Color
Index2 Bit
14
RW
0
5
Cursor2
Color
Index2 Bit
13
RW
0
Type
Reset
state
7
Cursor2
Color
Index2 Bit
23
RW
0
6
Cursor2
Color
Index2 Bit
22
RW
0
5
Cursor2
Color
Index2 Bit
21
RW
0
Type
Reset
state
7
Cursor2
Color
Index2 Bit
31
RW
0
REG[10Fh] bits 7-0
REG[10Eh] bits 7-0
REG[10Dh] bits 7-0
REG[10Ch] bits 7-0
6
Cursor2
Color
Index2 Bit
30
RW
0
5
Cursor2
Color
Index2 Bit
29
RW
0
1
Cursor2
Color
Index2 Bit
9
RW
0
0
Cursor2
Color
Index2 Bit
8
RW
0
REG[10Eh]
Cursor2 Color Index2 Register 1
Bit
0
Cursor2
Color
Index2 Bit
0
RW
0
REG[10Dh]
Cursor2 Color Index2 Register 0
Bit
1
Cursor2
Color
Index2 Bit
1
RW
0
1
Cursor2
Color
Index2 Bit
17
RW
0
0
Cursor2
Color
Index2 Bit
16
RW
0
REG[10Fh]
1
Cursor2
Color
Index2 Bit
25
RW
0
0
Cursor2
Color
Index2 Bit
24
RW
0
Cursor2 Color Index2 Bits [31:0]
Each cursor pixel is represented by 2 bits. This register stores the color index for pixel value 10
of Cursor2.
Note
(1)
These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).
For Hardware Cursors operation, see Section “Hardware Cursor Mode” in datasheet.
Solomon Systech
Jul 2009
P 116/117
Rev 1.0
SSD1926
Application Note
Cursor2 Color Index3 Register 0
Bit
Type
Reset
state
7
Cursor2
Color
Index3 Bit
7
RW
0
6
Cursor2
Color
Index3 Bit
6
RW
0
5
Cursor2
Color
Index3 Bit
5
RW
0
REG[110h]
4
Cursor2
Color
Index3 Bit
4
RW
0
3
Cursor2
Color
Index3 Bit
3
RW
0
2
Cursor2
Color
Index3 Bit
2
RW
0
4
Cursor2
Color
Index3 Bit
12
RW
0
3
Cursor2
Color
Index3 Bit
11
RW
0
2
Cursor2
Color
Index3 Bit
10
RW
0
4
Cursor2
Color
Index3 Bit
20
RW
0
3
Cursor2
Color
Index3 Bit
19
RW
0
2
Cursor2
Color
Index3 Bit
18
RW
0
Cursor2 Color Index3 Register 1
Bit
Type
Reset
state
7
Cursor2
Color
Index3 Bit
15
RW
0
6
Cursor2
Color
Index3 Bit
14
RW
0
5
Cursor2
Color
Index3 Bit
13
RW
0
Type
Reset
state
7
Cursor2
Color
Index3 Bit
23
RW
0
6
Cursor2
Color
Index3 Bit
22
RW
0
5
Cursor2
Color
Index3 Bit
21
RW
0
Type
Reset
state
1
Cursor2
Color
Index3 Bit
9
RW
0
0
Cursor2
Color
Index3 Bit
8
RW
0
REG[112h]
Cursor2 Color Index3 Register 3
Bit
0
Cursor2
Color
Index3 Bit
0
RW
0
REG[111h]
Cursor2 Color Index3 Register 2
Bit
1
Cursor2
Color
Index3 Bit
1
RW
0
1
Cursor2
Color
Index3 Bit
17
RW
0
0
Cursor2
Color
Index3 Bit
16
RW
0
REG[113h]
7
Cursor2
Color
Index3 Bit
31
RW
6
Cursor2
Color
Index3 Bit
30
RW
5
Cursor2
Color
Index3 Bit
29
RW
4
Cursor2
Color
Index3 Bit
28
RW
3
Cursor2
Color
Index3 Bit
27
RW
2
Cursor2
Color
Index3 Bit
26
RW
1
Cursor2
Color
Index3 Bit
25
RW
0
Cursor2
Color
Index3 Bit
24
RW
0
0
0
0
0
0
0
0
REG[113h] bits 7-0
REG[112h] bits 7-0
REG[111h] bits 7-0
REG[110h] bits 7-0
Cursor2 Color Index3 Bits [31:0]
Each cursor pixel is represented by 2 bits. This register stores the color index for pixel value 11
of Cursor2.
Note
(1)
These bits will not effective until the Cursor2 Enable bit is set to 1 (REG[C0h] bit 6=1).
For Hardware Cursors operation, see Section “Hardware Cursor Mode” in datasheet.
SSD1926
Application Note
Rev 1.0
P 117/118
Jul 2009
Solomon Systech
2.17 Draw2D Mode
Draw 2D Command Register 1
Bit
Type
Reset
state
7
Draw 2D
Command
Bit 7
RW
0
6
Draw 2D
Command
Bit 6
RW
0
5
Draw 2D
Command
Bit 5
RW
0
REG[1D0h]
4
Draw 2D
Command
Bit 4
RW
0
3
Draw 2D
Command
Bit 3
RW
0
2
Draw 2D
Command
Bit 2
RW
0
4
Draw 2D
Command
Bit 12
RW
0
3
Draw 2D
Command
Bit 11
RW
0
2
Draw 2D
Command
Bit 10
RW
0
1
Draw 2D
Command
Bit 1
RW
0
Draw 2D Command Register 2
Bit
Type
Reset
state
7
Draw 2D
Command
Bit 15
RW
0
REG[1D1h] Bits 7-4
6
Draw 2D
Command
Bit 14
RW
0
5
Draw 2D
Command
Bit 13
RW
0
0
Draw 2D
Command
Bit 0
RW
0
REG[1D1h]
1
Draw 2D
Command
Bit 9
RW
0
0
Draw 2D
Command
Bit 8
RW
0
Draw 2D Command Registers [15:0]
These bits are rotation extension decoded as below:
Rotation extension is used for bitblt, alpha blending, rop and stretch blt operations.
Bits 7:6 is the x orientation
Bits 5:4 is y orientation
2’b00: original orientation
2’b01: mirror in own axis
2’b10: mirror in opposite axis
2’b11: original orientation using opposite axis
Note
(1)
Restriction: when x axis orientation setting is opposite axis, y axis orientation cannot be own
axis. Same restriction applies when x axis orientation setting is own axis (mirror or not mirror),
y axis orientation cannot be opposite axis.
REG[1D1h] Bits 3-0
REG[1D0h] Bits 7:0
Solomon Systech
Some example settings:
0 degree: 4’b0000
horizontal mirror: 4’b0100
vertical mirror: 4’b0001
rotate CW 90: 4’b1110
rotate CCW 90: 4’b1011
These bits are the command decode:
0x00: nop
0x01: line draw
0x02: rect draw
0x03: ellipse draw
0x04: transparent blt
0x05: bitblt
0x06: clut setup
0x07: alpha blending
0x08: stretchblt
0x09: rop
In the color expansion mode, these 8 bits specifies the default alpha value.
In the CLUT operation, these 8 bits specifies the color index to be set.
In the alpha blending operation, these 8 bits is the default alpha in 16bpp modes.
Jul 2009
P 118/119
Rev 1.0
SSD1926
Application Note
Draw 2D Command FIFO Status
REG[1D2h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit 1
0
Draw 2D
Command
start
RW
0
Draw2D AutoMode in
After setting up the appropriate parameters, set this bit to 1 and then set the draw2d command
start bit (REG[1D2h] Bit 0) to 1. The draw2d operation’s start timing will switch to automode.
In automode, the 2D engine will start only once after DV stream in non display period.
There are some limitations in automode, 1) only a single command is possible, 2)
draw2d_brush_win_start will be behave as designed. This is because DV window is double
buffered, and we will have to find some way to specify a secondary destination address to 2D
engine. We’ve chosen draw2d_brush_win_start as the secondary destination address pointer.
Note : ROP256 operations are not allowed in automode.
Draw 2D Command start Bit
Write this bit = 1, draw2d operation will be started.
Bit 0
SSD1926
Application Note
1
Draw2D
AutoMode
In
RW
0
Rev 1.0
P 119/120
Jul 2009
Solomon Systech
Draw 2D Source Window Start Address Register 0
REG[1D4h]
Bit
7
Draw 2D
Window
Src Start
Address
Bit 7
6
Draw 2D
Window
Src Start
Address
Bit 6
5
Draw 2D
Window
Src Start
Address
Bit 5
4
Draw 2D
Window
Src Start
Address
Bit 4
3
Draw 2D
Window
Src Start
Address
Bit 3
2
Draw 2D
Window
Src Start
Address
Bit 2
1
Draw 2D
Window
Src Start
Address
Bit 1
0
Draw 2D
Window
Src Start
Address
Bit 0
Type
Reset
state
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Draw 2D Source Window Start Address Register 1
Bit
Type
Reset
state
7
Draw 2D
Window
Src Start
Address
Bit 15
RW
0
6
Draw 2D
Window
Src Start
Address
Bit 14
RW
0
5
Draw 2D
Window
Src Start
Address
Bit 13
RW
0
4
Draw 2D
Window
Src Start
Address
Bit 12
RW
0
REG[1D5h]
3
Draw 2D
Window
Src Start
Address
Bit 11
RW
0
2
Draw 2D
Window
Src Start
Address
Bit 10
RW
0
3
Draw 2D
Window
Src Start
Address
Bit 19
RW
0
2
Draw 2D
Window
Src Start
Address
Bit 18
RW
0
Draw 2D Source Window Start Address Register 2
Bit
7
x
Type
Reset
state
RO
0
REG[1D6h] bits6-0,
REG[1D5h] bits 7-0,
REG[1D4h] bits 7-0
6
Draw 2D
Window
Src Start
Address
Bit 22
RW
0
5
Draw 2D
Window
Src Start
Address
Bit 21
RW
0
4
Draw 2D
Window
Src Start
Address
Bit 20
RW
0
1
Draw 2D 1
Window
Src Start
Address
Bit 9
RW
0
0
Draw 2D
Window
Src Start
Address
Bit 8
RW
0
REG[1D6h]
1
Draw 2D
Window
Src Start
Address
Bit 17
RW
0
0
Draw 2D
Window
Src Start
Address
Bit 16
RW
0
Draw 2D Source Window Start Address Bits [22:0]
These bits form the 16bit internal start address of draw2d source window in SSD1926 memory
with 64bit width (in term of bit per pixel).
E.g. to specify a 1bpp source buffer located physically at ram address 0x0001, the value of this
register should be 0x0040.
This is a multi-usage register
In bitBlt, alpha-blend, stretchblt, transparent blt operations, this register is the source window
start address. When operations do not require a source window, it will not be interpreted as an
address.
In CLUT setup command, bits 15:0 is the {red, green} color of the table being set.
In ellipse draw operation, bits 8:0 is ellipse’s center x coordinate and bits 17:9 is ellipse’s y
clipping boundary.
Solomon Systech
Jul 2009
P 120/121
Rev 1.0
SSD1926
Application Note
Bit
Type
Reset
state
Draw 2D Source Window Line Address Offset Register 0
7
6
5
4
3
Draw 2D
Draw 2D
Draw 2D
Draw 2D
Draw 2D
Src
Src
Src
Src
Src
Window
Window
Window
Window
Window
Line
Line
Line
Line
Line
Address
Address
Address
Address
Address
Offset Bit 7 Offset Bit 6 Offset Bit 5 Offset Bit 4 Offset Bit 3
RW
RW
RW
RW
RW
0
0
0
0
0
2
Draw 2D
Src
Window
Line
Address
Offset Bit 2
RW
0
Draw 2D Source Window Line Address Offset Register 1
REG[1D9h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[1D9h] bits 1-0,
REG[1D8h] bits 7-0
1
Draw 2D
Src
Window
Line
Address
Offset Bit 9
RW
0
0
Draw 2D
Src
Window
Line
Address
Offset Bit 8
RW
0
Draw 2D Source Window Line Address Offset Bits [9:0]
This register is the screen pixel width, (not necessarily same as draw2d window width)
Draw 2D Source Window Color Mode
REG[1DCh
Bit
7
0
6
0
5
0
4
0
3
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
REG[1DCh] Bits 2-0
2
SRC Color
Bit 2
RW
0
1
SRC Color
Bit 1
RW
0
1
Draw 2D
Dest
Window
Color Mode
Bit 1
RW
0
0
SRC Color
Bit 0
RW
0
Source Window Color Bits [2:0]
000 : 16 bpp
001 : 32 bpp
010 : YUV
100 : 1 bpp
101 : 8 bpp
Draw 2D Destination Window Color Mode Register
REG[1DDh]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[1DDh] Bits 1-0
SSD1926
Application Note
REG[1D8h]
0
1
Draw 2D
Draw 2D
Src
Src
Window
Window
Line
Line
Address
Address
Offset Bit 1 Offset Bit 0
RW
RW
0
0
Rev 1.0
0
Draw 2D
Dest
Window
Color Mode
Bit 0
RW
0
Destination Window Color Bits [1:0]
00 : 16 bpp
01 : 32 bpp
10 : YUV
P 121/122
Jul 2009
Solomon Systech
Draw 2D Source Window Width Register 0
Bit
Type
Reset
state
7
Draw 2D
Src
Window
Width
Bit 7
RW
0
6
Draw 2D
Src
Window
Width
Bit 6
RW
0
5
Draw 2D
Src
Window
Width
Bit 5
RW
0
4
Draw 2D
Src
Window
Width
Bit 4
RW
0
REG[1E4h]
3
Draw 2D
Src
Window
Width
Bit 3
RW
0
2
Draw 2D
Src
Window
Width
Bit 2
RW
0
1
Draw 2D
Src
Window
Width
Bit 1
RW
0
1
Draw 2D
Src
Window
Width
Bit 9
RW
0
Draw 2D Source Window Width Register 1
REG[1E5h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[1E5h] bits 1-0,
REG[1E4h] bits 7-0
0
Draw 2D
Src
Window
Width
Bit 0
RW
0
0
Draw 2D
Src
Window
Width
Bit 8
RW
0
Draw 2D Source Window Width Register [9:0]
This is a multi purpose register
In line draw mode, this register is the starting x coordinate of the line drawn
For “blting” operations (alpha blend, stretchblt, bitblt etc), this register is the width of the
source window (in pixel). Alpha blend is for RGB mode only. In YUV mode, this value should
be a multiple of 2 (This limitation is not applicable in RGB mode).
In ellipse draw mode, this register is the y coordinate of the ellipse’s center.
Draw 2D Source Window Height Register 0
Bit
Type
Reset
state
7
Draw 2D
Src
Window
Height
Bit 7
RW
0
6
Draw 2D
Src
Window
Height
Bit 6
RW
0
5
Draw 2D
Src
Window
Height
Bit 5
RW
0
4
Draw 2D
Src
Window
Height
Bit 4
RW
0
REG[1E8h]
3
Draw 2D
Src
Window
Height
Bit 3
RW
0
2
Draw 2D
Src
Window
Height
Bit 2
RW
0
Draw 2D Source Window Height Register 1
0
Draw 2D
Src
Window
Height
Bit 0
RW
0
REG[1E9h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Solomon Systech
1
Draw 2D
Src
Window
Height
Bit 1
RW
0
Jul 2009
P 122/123
1
Draw 2D
Src
Window
Height
Bit 9
RW
0
Rev 1.0
0
Draw 2D
Src
Window
Height
Bit 8
RW
0
SSD1926
Application Note
REG[1E9h] bits 1-0,
REG[1E8h] bits 7-0
Draw 2D Source Window Height Register [9:0]
This is a multi purpose register
For “blting” operations (alpha blend, stretchblt, bitblt etc), this register is the height of the
source window (in pixel).
In line draw mode, this register is the starting y coordinate
In ellipse draw mode, this register is the “radius” of the ellipse in x axis.
Draw 2D Destination Window Width Register 0
Bit
Type
Reset
state
7
Draw 2D
Dest
Window
Width
Bit 7
RW
0
6
Draw 2D
Dest
Window
Width
Bit 6
RW
0
5
Draw 2D
Dest
Window
Width
Bit 5
RW
0
4
Draw 2D
Dest
Window
Width
Bit 4
RW
0
REG[1ECh]
3
Draw 2D
Dest
Window
Width
Bit 3
RW
0
2
Draw 2D
Dest
Window
Width
Bit 2
RW
0
Draw 2D Destination Window Width Register 1
Bit
Type
Reset
state
1
Draw 2D
Dest
Window
Width
Bit 1
RW
0
0
Draw 2D
Dest
Window
Width
Bit 0
RW
0
REG[1EDh]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Draw 2D
Dest
Window
Width
Bit 9
RW
0
Draw 2D
Dest
Window
Width
Bit 8
RW
0
REG[1EDh] bits 1-0,
REG[1ECh] bits 7-0
Draw 2D Destination Window Width Register [9:0]
This is a multi purpose register
For stretchblt operation, this is the width of destination window in pixel. In YUV mode, this
value should be a multiple of 2 (This limitation is not applicable in RGB mode).
In line draw mode, this register is the ending x coordinate
In ellipse draw mode, this register is the starting angle of the ellipse (360 < register value < 0 )
SSD1926
Application Note
Rev 1.0
P 123/124
Jul 2009
Solomon Systech
Draw 2D Destination Window Height Register 0
Bit
Type
Reset
state
7
Draw 2D
Dest
Window
Height
Bit 7
RW
0
6
Draw 2D
Dest
Window
Height
Bit 6
RW
0
5
Draw 2D
Dest
Window
Height
Bit 5
RW
0
4
Draw 2D
Dest
Window
Height
Bit 4
RW
0
REG[1F0h]
3
Draw 2D
Dest
Window
Height
Bit 3
RW
0
2
Draw 2D
Dest
Window
Height
Bit 2
RW
0
Draw 2D Destination Window Y Height Register 1
Bit
Type
Reset
state
1
Draw 2D
Dest
Window
Height
Bit 1
RW
0
0
Draw 2D
Dest
Window
Height
Bit 0
RW
0
REG[1F1h]
7
6
5
4
3
2
1
0
0
0
0
0
0
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Draw 2D
Dest
Window
Height
Bit 9
RW
0
Draw 2D
Dest
Window
Height
Bit 8
RW
0
REG[1F1h] bits 1-0,
REG[1F0h] bits 7-0
Draw 2D Destination Window Height Register [9:0]
This is a multi-purpose register
In stretch blit operation, this register is the height of destination window in pixel.
In line draw operation, this register is the ending y coordinate.
In ellipse draw operation, this register is the “radius” of the ellipse in y axis.
Draw 2D Destination Window Start Address Register 0
Bit
Type
Reset
state
7
Draw 2D
Dest
Window
Start
Address
Bit 7
RW
0
6
Draw 2D
Dest
Window
Start
Address
Bit 6
RW
0
5
Draw 2D
Dest
Window
Start
Address
Bit 5
RW
0
4
Draw 2D
Dest
Window
Start
Address
Bit 4
RW
0
3
Draw 2D
Dest
Window
Start
Address
Bit 3
RW
0
REG[1F4h]
2
Draw 2D
Dest
Window
Start
Address
Bit 2
RW
0
Draw 2D Destination Window Start Address Register 1
Bit
Type
Reset
state
7
Draw 2D
Dest
Window
Start
Address
Bit 15
RW
0
Solomon Systech
6
Draw 2D
Dest
Window
Start
Address
Bit 14
RW
0
5
Draw 2D
Dest
Window
Start
Address
Bit 13
RW
0
4
Draw 2D
Dest
Window
Start
Address
Bit 12
RW
0
3
Draw 2D
Dest
Window
Start
Address
Bit 11
RW
0
Jul 2009
1
Draw 2D
Dest
Window
Start
Address
Bit 1
RW
0
0
Draw 2D
Dest
Window
Start
Address
Bit 0
RW
0
REG[1F5h]
2
Draw 2D
Dest
Window
Start
Address
Bit 10
RW
0
P 124/125
1
Draw 2D
Dest
Window
Start
Address
Bit 9
RW
0
Rev 1.0
0
Draw 2D
Dest
Window
Start
Address
Bit 8
RW
0
SSD1926
Application Note
Draw 2D Destination Window Start Address Register 2
Bit
7
0
Type
Reset
state
RO
0
6
Draw 2D
Dest
Window
Start
Address
Bit 22
RW
0
REG[1F6h] bits 6-0,
REG[1F5h] bits 7-0,
REG[1F4h] bits 7-0
5
Draw 2D
Dest
Window
Start
Address
Bit 21
RW
0
4
Draw 2D
Dest
Window
Start
Address
Bit 20
RW
0
REG[1F6h]
3
Draw 2D
Dest
Window
Start
Address
Bit 19
RW
0
2
Draw 2D
Dest
Window
Start
Address
Bit 18
RW
0
1
Draw 2D
Dest
Window
Start
Address
Bit 17
RW
0
0
Draw 2D
Dest
Window
Start
Address
Bit 16
RW
0
Draw 2D Destination Window Start Address Bits [22:0]
These bits form the 16bit internal start address of draw2d destination window in SSD1926
memory with 64bit width (in term of bit per pixel).
E.g. to specify a 1bpp destination buffer located at physically ram address 0x0001, the value of
this register should be 0x0040.
This is a multi-usage register
This register is the destination window start address of all draw2d operations, expect CLUT
setup.
In the CLUT setup command, bits 15:0 is the {blue, alpha} color of the table being set.
Draw 2D Destination Window Line Address Offset Register 0
Bit
Type
Reset
state
7
Draw 2D
Line
Address
Offset Bit 7
RW
0
6
Draw 2D
Line
Address
Offset Bit 6
RW
0
5
Draw 2D
Line
Address
Offset Bit 5
RW
0
4
Draw 2D
Line
Address
Offset Bit 4
RW
0
3
Draw 2D
Line
Address
Offset Bit 3
RW
0
REG[1f8h]
2
Draw 2D
Line
Address
Offset Bit 2
RW
0
Draw 2D Destination Window Line Address Offset Register 1
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
SSD1926
Application Note
Rev 1.0
0
Draw 2D
Line
Address
Offset Bit 0
RW
0
REG[1f9h]
Bit
REG[1D9h] bits 1-0,
REG[1D8h] bits 7-0
1
Draw 2D
Line
Address
Offset Bit 1
RW
0
1
Draw 2D
Line
Address
Offset Bit 9
RW
0
0
Draw 2D
Line
Address
Offset Bit 8
RW
0
Draw Destination Window Line Address Offset Bits [9:0]
This register is the number of pixels between lines inside the display screen size.
P 125/126
Jul 2009
Solomon Systech
Draw 2D Write Value Pattern (Command Parameter) Register 0
Bit
Type
Reset
state
7
Draw 2D
Window
Write
Pattern
Bit 7
RW
0
6
Draw 2D
Window
Write
Pattern
Bit 6
RW
0
5
Draw 2D
Window
Write
Pattern
Bit 5
RW
0
4
Draw 2D
Window
Write
Pattern
Bit 4
RW
0
3
Draw 2D
Window
Write
Pattern
Bit 3
RW
0
2
Draw 2D
Window
Write
Pattern
Bit 2
RW
0
Draw 2D Window Write Pattern (Command Parameter) Register 1
Bit
Type
Reset
state
7
Draw 2D
Window
Write
Pattern
Bit 15
RW
0
6
Draw 2D
Window
Write
Pattern Bit
14
RW
0
5
Draw 2D
Window
Write
Pattern
Bit 13
RW
0
4
Draw 2D
Window
Write
Pattern
Bit 12
RW
0
3
Draw 2D
Window
Write
Pattern
Bit 11
RW
0
2
Draw 2D
Window
Write
Pattern
Bit 10
RW
0
Draw 2D Window Write Pattern (Command Parameter) Register 2
Bit
Type
Reset
state
7
Draw 2D
Window
Write
Pattern Bit
23
RW
0
REG[1FEh] bits 7-0,
REG[1FDh] bits 7-0,
REG[1FCh] bits 7-0
6
Draw 2D
Window
Write
Pattern Bit
22
RW
0
5
Draw 2D
Window
Write
Pattern
Bit 21
RW
0
4
Draw 2D
Window
Write
Pattern
Bit 20
RW
0
3
Draw 2D
Window
Write
Pattern
Bit 19
RW
0
2
Draw 2D
Window
Write
Pattern
Bit 18
RW
0
REG[1FCh]
1
Draw 2D
Window
Write
Pattern
Bit 1
RW
0
0
Draw 2D
Window
Write
Pattern
Bit 0
RW
0
REG[1FDh]
1
Draw 2D
Window
Write
Pattern
Bit 9
RW
0
0
Draw 2D
Window
Write
Pattern
Bit 8
RW
0
REG[1FEh]
1
Draw 2D
Window
Write
Pattern
Bit 17
RW
0
0
Draw 2D
Window
Write
Pattern
Bit 16
RW
0
Draw 2D Window Write Pattern Bits [23:0]
Multi-purpose register
In ROP mode, [7:0] marks the ROP code specified by Microsoft’s ROP3 operation.
In transparent blt mode, this register represents the transparent color’s BGR value. However,
since this register is 24bit in width, when a 16bit color is compared to, the 16bit red color will
be shifted left by 3, Green is shifted left by 2, and blue shifted left by 2.
In alpha blending mode, [1:0] is 2 different modes:
2’b00 => Microsoft pre-blend:
dst = (src * const_alpha + dst * (255-const_alpha)) / 255
2’b01 => Microsoft pre-blend2:
if (draw2d_cmd[7:0] == 7’hff)
dst = src + (1 – src.alpha/255) * dst
else // 2 cycle blending
dst = (src + (1 – src.alpha) * dst) * const_alpha
2’b10, 2’b11 => reserved mode
In drawing lines, ellipse, this register is the {R,G,B} color
Solomon Systech
Jul 2009
P 126/127
Rev 1.0
SSD1926
Application Note
Draw 2D Brush Window Start Address Register 0
Bit
Type
Reset
state
7
Draw 2D
Brush
Window
Start
Address
Bit 7
RW
0
6
Draw 2D
Brush
Window
Start
Address
Bit 6
RW
0
5
Draw 2D
Brush
Window
Start
Address
Bit 5
RW
0
4
Draw 2D
Brush
Window
Start
Address
Bit 4
RW
0
REG[204h]
3
Draw 2D
Brush
Window
Start
Address
Bit 3
RW
0
2
Draw 2D
Brush
Window
Start
Address
Bit 2
RW
0
3
Draw 2D
Brush
Window
Start
Address
Bit 11
RW
0
2
Draw 2D
Brush
Window
Start
Address
Bit 10
RW
0
3
Draw 2D
Brush
Window
Start
Address
Bit 19
RW
0
2
Draw 2D
Brush
Window
Start
Address
Bit 18
RW
0
Draw 2D Brush Window Start Address Register 1
Bit
Type
Reset
state
7
Draw 2D
Brush
Window
Start
Address
Bit 15
RW
0
6
Draw 2D
Brush
Window
Start
Address
Bit 14
RW
0
5
Draw 2D
Brush
Window
Start
Address
Bit 13
RW
0
4
Draw 2D
Brush
Window
Start
Address
Bit 12
RW
0
7
0
Type
Reset
state
RO
0
6
Draw 2D
Brush
Window
Start
Address
Bit 22
RW
0
6REG[206h] bits 6-0,
REG[205h] bits 7-0,
REG[204h] bits 7-0
5
Draw 2D
Brush
Window
Start
Address
Bit 21
RW
0
4
Draw 2D
Brush
Window
Start
Address
Bit 20
RW
0
Type
Reset
state
7
Draw 2D
Brush Line
Address
Offset Bit 7
RW
0
SSD1926
Application Note
1
Draw 2D
Brush
Window
Start
Address
Bit 9
RW
0
0
Draw 2D
Brush
Window
Start
Address
Bit 8
RW
0
REG[206h]
1
Draw 2D
Brush
Window
Start
Address
Bit 17
RW
0
0
Draw 2D
Brush
Window
Start
Address
Bit 16
RW
0
Draw 2D Brush Window Start Address Bits [22:0]
These bits form the 16bit internal start address of draw2d brush window in SSD1926 memory
for ROP operation (in term of bit per pixel).
E.g. to specify a 1bpp destination buffer located at physically ram address 0x0001, the value of
this register should be 0x0040.
Draw 2D Brush Window Line Address Offset Register 0
Bit
0
Draw 2D
Brush
Window
Start
Address
Bit 0
RW
0
REG[205h]
Draw 2D Brush Window Start Address Register 2
Bit
1
Draw 2D
Brush
Window
Start
Address
Bit 1
RW
0
6
Draw 2D
Brush Line
Address
Offset Bit 6
RW
0
Rev 1.0
5
Draw 2D
Brush Line
Address
Offset Bit 5
RW
0
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Jul 2009
4
Draw 2D
Brush Line
Address
Offset Bit 4
RW
0
3
Draw 2D
Brush Line
Address
Offset Bit 3
RW
0
REG[208h]
2
Draw 2D
Brush Line
Address
Offset Bit 2
RW
0
1
Draw 2D
Brush Line
Address
Offset Bit 1
RW
0
0
Draw 2D
Brush Line
Address
Offset Bit 0
RW
0
Solomon Systech
Draw 2D brush Window Line Address Offset Register 1
REG[209h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[209h] bits 1-0,
REG[208h] bits 7-0
Type
Reset
state
7
Draw 2D
Brush
Window
Width
Bit 7
RW
0
6
Draw 2D
Brush
Window
Width
Bit 6
RW
0
5
Draw 2D
Brush
Window
Width
Bit 5
RW
0
REG[214h]
4
Draw 2D
Brush
Window
Width
Bit 4
RW
0
3
Draw 2D
Brush
Window
Width
Bit 3
RW
0
2
Draw 2D
Brush
Window
Width
Bit 2
RW
0
Draw 2D Brush Window Width Register 1
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Type
Reset
state
7
Draw 2D
Brush
Window
Height
Bit 7
RW
0
Solomon Systech
0
Draw 2D
Brush
Window
Width
Bit 0
RW
0
1
Draw 2D
Brush
Window
Width
Bit 9
RW
0
0
Draw 2D
Brush
Window
Width
Bit 8
RW
0
Draw 2D Brush Window Width[9:0]
This register is the operation region width. Note that “operation width” is not necessarily equal
to Brush Window line offset (i.e. line offset is related to the brush’s layout in memory, while
one might choose a smaller part of the brush to operate on)
Draw 2D Brush Window Height Register 0
Bit
1
Draw 2D
Brush
Window
Width
Bit 1
RW
0
REG[215h]
Bit
REG[215h] bits 1-0,
REG[214h] bits 7-0
0
Draw 2D
Brush Line
Address
Offset Bit 8
RW
0
Draw Brush Window Line Address Offset Bits [9:0]
This register is the width of the pattern in memory in terms of number of pixels
Draw 2D Brush Window width Register 0
Bit
1
Draw 2D
Brush Line
Address
Offset Bit 9
RW
0
6
Draw 2D
Brush
Window
Height
Bit 6
RW
0
5
Draw 2D
Brush
Window
Height
Bit 5
RW
0
4
Draw 2D
Brush
Window
Height
Bit 4
RW
0
REG[[218h]
3
Draw 2D
Brush
Window
Height
Bit 3
RW
0
Jul 2009
2
Draw 2D
Brush
Window
Height
Bit 2
RW
0
P 128/129
1
Draw 2D
Brush
Window
Height
Bit 1
RW
0
Rev 1.0
0
Draw 2D
Brush
Window
Height
Bit 0
RW
0
SSD1926
Application Note
Draw 2D brush Window Y Height Register 1
REG[219h]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG[219h] bits 1-0,
REG[218h] bits 7-0
1
Draw 2D
Brush
Window
Height
Bit 9
RW
0
Draw 2D Brush Window Height Register [9:0]
This register is Draw2D Brush Window height.
Draw 2D Command FIFO Interrupt enable
REG[21Ch]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
Bit 1
Draw 2D Command FIFO Interrupt Status
REG[21Eh]
Bit
7
0
6
0
5
0
4
0
3
0
2
0
1
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit 1
Bit 0
0
Draw 2D
cmd fifo
status flag
RO
0
Reserved bit
Draw 2D Cmd FIFO Status Flag
When this bit = 1: Cmd FIFO ready. Write 1 to clear the flag .Write 0 has not hardware effect
When this bit = 0 : Busy
Raw Draw 2D Command FIFO FLAG
7
6
Reserved
Type
Reset
state
0
Draw 2D
Command
FIFO
Interrupt
Enable
RW
0
Reserved bit
This bit should be programmed as 0.
Draw 2D Command FIFI Interrupt Enable
When this bit = 1 : Enable Command FIFO Ready.
When this bit = 0 : Enable Command FIFO Busy.
Bit 0
Bit
0
Draw 2D
Brush
Window
Height
Bit 8
RW
0
RO
0
5
Reserved
RO
0
Bit 1
Bit 0
SSD1926
Application Note
REG[220h]
4
Reserved
RO
0
3
Reserved
RO
0
2
Reserved
RO
0
1
Reserved
RO
0
Reserved
RO
0
0
Raw
Draw2D
Command
Status flag
RO
1
Reserved bit
RAW Draw 2D CMD status flag
When this bit = 1 : Ready
When this bit = 0 : Busy
Rev 1.0
P 129/130
Jul 2009
Solomon Systech
2.18 JPEG Decode Registers
2.18.1 Decode Procedure
1) Enable the JPEG Codec (REG[380h] bit 0 = 1).
2) Initialize the JPEG Codec registers.
a) Software reset the JPEG Codec (REG[402h] bit 7 = 1).
b) Set operation mode to decode (REG[400h] bit 2).
c) Set JPEG MJPEG Mode (REG[400h] bit 5).
d) Set the RST Marker Operation Setting (REG[41Ch] bit 1-0).
3) Initialize the JPEG module registers (i.e. JPEG Line Buffer and FIFO).
a) Set the JPEG Source Start Address (REG[410h] – REG[412h]).
b) Set the JPEG Destination Address (REG[414h] – REG[416h]).
c) Set the JPEG FIFO Size (REG[3A4h]).
d) Set the JPEG File Size (REG[3B8h] – REG[3BAh]).
e) Set JPEG YUV Output Data Range Select (REG[380h] bit 4).
4) Start the decode process:
a) Clear all status of JPEG Line Buffer and FIFO (REG[382h] – REG[383h] = 0000h).
b) Enable required interrupts (REG[386h] – REG[387h]).
c) Start JPEG operation (REG[402h] bit 0 = 1).
d) Start decoding (REG[38Ah] bit 0 = 1).
5) Write data to JPEG FIFO (REG[414h – REG[416h]]
6) Wait for FIFO condition is met (i.e Empty/Half-Full/Quad-Full) by interrupt or polling. If Decode Marker
Read Interrupt is detected, read the Vertical Pixel Size (REG[3DCh] – REG[3DDh]) and Horizontal Pixel
Size (REG[3D8h] – REG[3D9h]) and set the registers for display.
7) Repeat steps 5 and 6 until the end of file.
8) Wait for JPEG Decode Complete Flag (REG[383h] bit 5) .
9) Verify the decode process is complete with the JPEG Operation Status (REG[404h] bit 0 = 0).
Note: 64-bit unit data is required to write to the JPEG FIFO. Pad the end of the JPEG data stream with 8’h00s
to complete the last 64-bit data for the last FIFO entry is necessary.
Followings description for Error Handling:
If JPEG Codec Interrupt Flag is high and both the Decode Marker Read Interrupt and JPEG Decode Complete
Interrupt are low, the JPEG codec encountered error in the JPEG data stream and cannot finish decoding.
Check the JPEG Operation Status and JPEG Error Status for debug.
If RST Marker Operation is set to enable the data revise function, JPEG codec may finish decoding even if
the JPEG data stream is corrupted. In this case, the decode process is complete according to steps 1 and 9 but
a corrupted JPEG image will be displayed. Check the RST Revise Code to confirm if a revise operation is
done and the type of error is indicated by the JPEG Error Status.
Solomon Systech
Jul 2009
P 130/131
Rev 1.0
SSD1926
Application Note
JPEG Control Register
REG[380h]
Bit
7
Reserved
6
Reserved
5
Reserved
Type
Reset
state
RW
0
RW
0
RW
0
Bits 7-5
4
YUV
Output
Data Range
Select
RW
0
3
Reserved
2
Reserved
1
Reserved
0
JPEG
Module
Enable
RW
0
RW
0
RW
0
RW
0
Reserved bits
These bits should be programmed by 0.
YUV Output Data Range Select
The YUV output range depends on the display data range.
Bit 4
Table 2-28: YUV Output Range Selection
REG[0380h] bit 4
0
1
Bits 3-1
YUV Output Data Range
0 =< Y =< 255
-128 =< U =< 127
-128 =< V =< 127
0 =< Y =< 255
0 =< U =< 255
0 =< V =< 255
Reserved bits
These bits should be programmed by 0.
JPEG Module Enable
This bit enables/disables the JPEG module and its associated registers.
When this bit = 1, the JPEG module is enabled and a clock source is supplied.
When this bit = 0, the JPEG module is disabled and the clock source is disabled.
Bit 0
JPEG Status Flag Register 0
REG[382h]
Bit
7
Reserved
6
Reserved
5
JPEG FIFO
Threshold
Status Bit 1
4
JPEG FIFO
Threshold
Status Bit 0
3
Reserved
Type
Reset
state
RW
0
RO
0
RO
0
RO
0
RW
0
Bit 7
2
JPEG FIFO
Threshold
Trigger
Flag
RW
0
1
JPEG FIFO
Full Flag
0
JPEG FIFO
Empty Flag
RW
0
RW
0
Reserved bit
This bit should be programmed as 0.
Reserved bit
Bit 6
Bit 5-4
JPEG FIFO Threshold Status bits [1:0]
These bits indicate how much data is currently in the JPEG FIFO. See the JPEG FIFO Size
register (REG[03A4h]) for information on setting the JPEG FIFO size.
Table 2-29: JPEG FIFO Threshold Status
REG[0382h] bits 5-4
00
01
10
11
SSD1926
Application Note
Rev 1.0
P 131/132
JPEG FIFO Threshold Status
no data (same as empty)
more than 4 bytes of data exist
more than 1/4 of specified FIFO size data exists
more than 1/2 of specified FIFO size data exists
Jul 2009
Solomon Systech
Bit 3
Reserved bit
This bit should be programmed as 0.
JPEG FIFO Threshold Trigger Flag
This flag is asserted when the amount of data in the JPEG FIFO meets the condition specified
by the JPEG FIFO Trigger Threshold bits (REG[03A0h] bits 5-4). This flag is masked by the
JPEG FIFO Threshold Trigger Interrupt Enable bit and is only available when REG[0386h] bit
2 = 1.
For Reads:
When this bit = 1, the amount of data in the JPEG FIFO has reached the JPEG FIFO Trigger
Threshold.
When this bit = 0, the amount of data in the JPEG FIFO is less than the JPEG FIFO Trigger
Threshold.
For Writes:
When a 1 is written to this bit, the FIFO Threshold Trigger Flag is cleared.
When a 0 is written to this bit, there is no hardware effect.
JPEG FIFO Full Flag
This flag is asserted when the JPEG FIFO is full. This flag is masked by the JPEG FIFO Full
Interrupt Enable bit and is only available when REG[0386h] bit 1 = 1.
For Reads:
When this bit = 1, the JPEG FIFO is full.
When this bit = 0, the JPEG FIFO is not full.
For Writes:
When a 1 is written to this bit, the JPEG FIFO Full Flag is cleared.
When a 0 is written to this bit, there is no hardware effect.
JPEG FIFO Empty Flag
This flag is asserted when the JPEG FIFO is empty. This flag is masked by the JPEG FIFO
Empty Interrupt Enable bit and is only available when REG[0386h] bit 0 = 1.
For Reads:
When this bit = 1, the JPEG FIFO is empty.
When this bit = 0, the JPEG FIFO is not empty.
For Writes:
When a 1 is written to this bit, the JPEG FIFO Empty Flag is cleared.
When a 0 is written to this bit, there is no hardware effect.
Bit 2
Bit 1
Bit 0
Bit
Type
Reset
state
JPEG Status Flag Register 1
7
6
5
4
3
2
1
REG[383h]
0
Reserved
Reserved
JPEG
Decode
Complete
Flag
JPEG
Decode
Marker
Read
Flag
Reserved
JPEG
Line
Buffer
Overflow
Flag
JPEG
Codec
Interrupt
Flag
Reserved
RW
0
RW
0
RW
0
RW
0
RW
0
RO
0
RO
0
RW
0
Bits 7-6
Bit 5
Solomon Systech
Reserved bits
These bits should be programmed by 0.
JPEG Decode Complete Flag
This flag is asserted when the JPEG decode operation is finished. This flag is masked by the
JPEG Decode Complete Interrupt Enable bit and is only available when REG[0387h] bit 5 = 1.
For Reads:
When this bit = 1, the JPEG decode operation is finished.
When this bit = 0, the JPEG decode operation is not finished yet.
For Writes:
When a 1 is written to this bit after disabling the interrupt, this bit is cleared.
When a 0 is written to this bit, there is no hardware effect.
Jul 2009
P 132/133
Rev 1.0
SSD1926
Application Note
Bit 4
JPEG Decode Marker Read Flag
This flag is asserted during the JPEG decoding process when decoded marker information is
read from the JPEG file. This flag is masked by the JPEG Decode Marker Read Interrupt
Enable bit and is only available when REG[0387h] bit 4 = 1.
For Reads:
When this bit = 1, a JPEG decode marker has been read.
When this bit = 0, a JPEG decode marker has not been read.
For Writes:
When a 1 is written to this bit after disabling the interrupt, this bit is cleared.
When a 0 is written to this bit, there is no hardware effect.
Reserved bit
This bit should be programmed by 0.
JPEG Line Buffer Overflow Flag
This flag is asserted when a JPEG Line Buffer overflow occurs. This flag is masked by the
JPEG Line Buffer Overflow Interrupt Enable bit and is only available when REG[387h] bit 2 =
1.
When this bit = 1, a JPEG Line Buffer overflow has occurred.
When this bit = 0, a JPEG Line Buffer overflow has not occurred.
To clear this flag, perform a JPEG Codec Software Reset (REG[402h] bit 7 = 1).
JPEG Codec Interrupt Flag
This flag is asserted when the JPEG codec generates an interrupt. This flag is masked by the
JPEG Codec Interrupt Enable bit and is only available when REG[0387h] bit 1 = 1).
When this bit = 1, the JPEG codec has generated an interrupt.
When this bit = 0, the JPEG codec has not generated an interrupt.
To clear this flag, perform a JPEG Codec Software Reset (REG[402h] bit 7 = 1).
Reserved bit
This bit should be programmed by 0.
Bit 3
Bit 2
Bit 1
Bit 0
JPEG RAW Status Flag Register 0
REG[384h]
Bit
7
Reserved
6
Reserved
5
JPEG FIFO
Threshold
Status Bit 1
4
JPEG FIFO
Threshold
Status Bit 0
3
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
2
Raw JPEG
FIFO
Threshold
Trigger
Flag
RO
0
1
Raw JPEG
FIFO Full
Flag
0
Raw JPEG
FIFO
Empty Flag
RO
0
RO
0
Bits 7-6
Reserved bit
Bits 5-4
JPEG FIFO Threshold Status bits [1:0]
These bits indicate how much data is currently in the JPEG FIFO. See the JPEG FIFO Size
Register (REG[3A4h] for information on setting the JPEG FIFO Size.
Table 2-30: JPEG FIFO Threshold Status
REG[0384h] bits 5-4
00
01
10
11
SSD1926
Application Note
Rev 1.0
P 133/134
JPEG FIFO Threshold Status
no data (same as empty)
more than 4 bytes of data exist
more than 1/4 of specified FIFO size data exists
more than 1/2 of specified FIFO size data exists
Jul 2009
Solomon Systech
Bit 3
Reserved bit
Bit 2
Raw JPEG FIFO Threshold Trigger Flag
This flag is asserted when the amount of data in the JPEG FIFO meets the condition specified
by the JPEG FIFO Trigger Threshold bits (REG[3A0] bits 5-4). This flag is not affected by the
JPEG FIFO Threshold Trigger Interrupt Enable bit (REG[386h] bit 2).
When this bit = 1, the amount of data in the JPEG FIFO has reached the JPEG FIFO Trigger
Threshold.
When this bit = 0, the amount of data in the JPEG FIFO is less than the JPEG FIFO Trigger
Threshold.
To clear this flag, write a 1 to the JPEG FIFO Threshold Trigger Flag (REG[382h] bit 2 = 1).
Raw JPEG FIFO Full Flag
This flag is asserted when the JPEG FIFO is full. This flag is not affected by the JPEG
FIFO Full Interrupt Enable bit (REG[386h] bit 1).
When this bit = 1, the JPEG FIFO is full.
When this bit = 0, the JPEG FIFO is not full.
To clear this flag, write a 1 to the JPEG FIFO Full Flag (REG[382h] bit 1 = 1).
Raw JPEG FIFO Empty Flag
This flag is asserted when the JPEG FIFO is empty. This flag is not affected by the JPEG FIFO
Empty Interrupt Enable bit (REG[386h] bit 0).
When this bit = 1, the JPEG FIFO is empty.
When this bit = 0, the JPEG FIFO is not empty.
To clear this flag, write a 1 to the JPEG FIFO Empty Flag (REG[382h] bit 0 = 1).
Bit 1
Bit 0
JPEG RAW Status Flag Register 1
Bit
7
Reserved
6
Reserved
Type
Reset
state
RW
0
RW
0
Bits 7-6
Bit 5
Bit 4
Bit 3
Bit 2
Solomon Systech
5
Raw JPEG
Decode
Complete
Flag
RO
0
REG[385h]
4
Raw JPEG
Decode
Marker
Read Flag
RO
0
3
Reserved
RW
0
2
Raw JPEG
Line Buffer
Overflow
Flag
RO
0
1
Raw JPEG
Codec
Interrupt
Flag
RO
0
0
Reserved
RW
0
Reserved bits
These bits should be programmed by 0.
Raw JPEG Decode Complete Flag
This flag is asserted when the JPEG decode operation is finished and ready to display.
This flag is not affected by the JPEG Decode Complete Interrupt Enable bit (REG[387h] bit 5).
When this bit = 1, the JPEG decode operation is finished.
When this bit = 0, the JPEG decode operation is not finished yet.
To clear this flag, write a 1 to the JPEG Decode Complete Flag (REG[383h] bit 5 = 1).
Raw JPEG Decode Marker Read Flag
This flag is asserted during the JPEG decoding process when decoded marker information is
read from the JPEG file.
When this bit = 1, a JPEG decode marker has been read.
When this bit = 0, a JPEG decode marker has not been read.
To clear this flag, write a 1 to the JPEG Decode Marker Read Flag (REG[383h] bit 4 = 1).
Reserved bit
This bit should be programmed by 0.
Raw JPEG Line Buffer Overflow Flag
This flag is asserted when a JPEG Line Buffer overflow occurs. This flag is not affected by the
JPEG Line Buffer Overflow Interrupt Enable (REG[387h] bit 2).
When this bit = 1, a JPEG Line Buffer overflow has occurred.
When this bit = 0, a JPEG Line Buffer overflow has not occurred.
To clear this flag, perform a JPEG Codec Software Reset (REG[402h] bit 7 = 1).
Jul 2009
P 134/135
Rev 1.0
SSD1926
Application Note
Bit 1
Raw JPEG Codec Interrupt Flag
This flag is asserted when an interrupt is generated by the JPEG codec. This flag is not affected
by the JPEG Codec Interrupt Enable bit (REG[387h] bit 1).
When this bit = 1, the JPEG codec has generated an interrupt.
When this bit = 0, no interrupt has been generated.
To clear this flag, perform a JPEG Codec Software Reset (REG[402h] bit 7 = 1).
Reserved bit
This bit should be programmed by 0.
Bit 0
JPEG Interrupt Control Register 0
REG[386h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 7-3
2
JPEG FIFO
Threshold
Trigger
Interrupt
Enable
RW
0
1
JPEG FIFO
Full
Interrupt
Enable
0
JPEG FIFO
Empty
Interrupt
Enable
RW
0
RW
0
Reserved bits
This bit should be programmed as 0.
JPEG FIFO Threshold Trigger Interrupt Enable
This bit controls the JPEG FIFO threshold trigger interrupt. The status of this interrupt can be
determined using the JPEG FIFO Threshold Trigger Flag bit (REG[382h] bit 2).
When this bit = 1, the interrupt is enabled.
When this bit = 0, the interrupt is disabled.
JPEG FIFO Full Interrupt Enable
This bit controls the JPEG FIFO full interrupt. The status of this interrupt can be determined
using the JPEG FIFO Full Flag bit (REG[382h] bit 1).
When this bit = 1, the interrupt is enabled.
When this bit = 0, the interrupt is disabled.
JPEG FIFO Empty Interrupt Enable
This bit controls the JPEG FIFO empty interrupt. The status of this interrupt can be determined
using the JPEG FIFO Empty Flag bit (REG[382h] bit 0).
When this bit = 1, the interrupt is enabled.
When this bit = 0, the interrupt is disabled.
Bit 2
Bit 1
Bit 0
JPEG Interrupt Control Register 1
Bit
7
Reserved
6
Reserved
5
JPEG
Decode
Complete
Interrupt
Enable
Type
Reset
state
RW
0
RW
0
RW
0
Bits 7-6
3
Reserved
2
JPEG Line
Buffer
Overflow
Interrupt
Enable
1
JPEG
Codec
Interrupt
Enable
0
Reserved
RW
0
RW
0
RW
0
RW
0
Reserved bits
These bits should be programmed by 0.
JPEG Decode Complete Interrupt Enable
This bit controls the JPEG decode complete interrupt. The status of this interrupt can be
determined using the JPEG Decode Complete Flag bit (REG[383h] bit 5).
When this bit = 1, the interrupt is enabled.
When this bit = 0, the interrupt is disabled.
Bit 5
SSD1926
Application Note
REG[387h]
4
JPEG
Decode
Marker
Read
Interrupt
Enable
RW
0
Rev 1.0
P 135/136
Jul 2009
Solomon Systech
Bit 4
JPEG Decode Marker Read Interrupt Enable
This bit controls the JPEG decode marker read interrupt. The status of this interrupt can be
determined using the JPEG Decode Marker Read Flag (REG[383h] bit 4).
When this bit = 1, the interrupt is enabled.
When this bit = 0, the interrupt is disabled.
Reserved bit
This bit should be programmed by 0.
JPEG Line Buffer Overflow Interrupt Enable
This bit controls the JPEG Line Buffer overflow interrupt. The status of this interrupt can be
determined using the JPEG Line Buffer Overflow Flag (REG[383h] bit 2).
When this bit = 1, the interrupt is enabled.
When this bit = 0, the interrupt is disabled.
JPEG Codec Interrupt Enable
This bit controls the JPEG codec interrupt. The status of this interrupt can be determined using
the JPEG Codec Interrupt Flag (REG[383h] bit 1).
When this bit = 1, the interrupt is enabled.
When this bit = 0, the interrupt is disabled.
Reserved bit
This bit should be programmed by 0.
Bit 3
Bit 2
Bit 1
Bit 0
JPEG Code Start / Stop Control Register)
REG[38Ah]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
Type
Reset
state
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 7-1
0
JPEG
Start/Stop
Control
WO
0
Reserved bits
These bits should be programmed by 0.
JPEG Start/Stop Control
This bit controls the JPEG decode mode.
When this bit is set to 1, the JPEG codec starts to decode the image.
When this bit is set to 0, the JPEG codec will be ready to read the JPEG markers.
Bit 0
JPEG FIFO Control Register
Bit
7
Reserved
6
Reserved
Type
Reset
state
RW
0
RW
0
Bits 7-6
Bit 5-4
Solomon Systech
5
JPEG FIFO
Trigger
Threshold
Bit 1
RW
0
REG[3A0h]
4
JPEG FIFO
Trigger
Threshold
Bit 0
RW
0
3
Reserved
2
Reserved
1
Reserved
0
Reserved
RW
0
RW
0
RO
0
RW
0
Reserved bits
These bits should be programmed by 0.
JPEG FIFO Trigger Threshold bits [1:0]
These bits set the JPEG FIFO Threshold Trigger Flag (REG[382h] bit 2) when the specified
conditions are met.
Jul 2009
P 136/137
Rev 1.0
SSD1926
Application Note
Table 2-31: JPEG FIFO Trigger Threshold Selection
REG[03A0h] bits 5-4
00
01
10
11
Bits 3-2
JPEG FIFO Trigger Threshold
Never trigger
Trigger when the JPEG FIFO contains 4 bytes of data or
more
Trigger when the JPEG FIFO contains more than 1/4 of
the specified JPEG FIFO size (REG[3A4h] bits 6-0)
Trigger when the JPEG FIFO contains more than 1/2 of
the specified JPEG FIFO size (REG[3A4h] bits 6-0)
Reserved bits
This bit should be programmed by 0.
Reserved bit
Bit 1
Bit 0
Reserved bit
This bit should be programmed by 0.
JPEG FIFO Status Register
REG[3A2h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
Type
Reset
state
RW
0
RW
0
RW
0
RW
0
Bits 7-4
3
JPEG FIFO
Threshold
Status Bit 1
RO
0
2
JPEG FIFO
Threshold
Status Bit 0
RO
0
1
JPEG FIFO
Full Status
RO
0
0
JPEG FIFO
Empty
Status
RO
0
Reserved bits
These bits should be programmed by 0.
JPEG FIFO Threshold Status bits [1:0]
These bits indicate the amount of data in the JPEG FIFO.
Bit 3-2
Table 2-32: JPEG FIFO Threshold Status
REG[03A2h] bits 3-2
00
01
10
JPEG FIFO Threshold Status
No data (Same as Empty)
4 bytes of data or more exists
More than 1/4 of the specified JPEG FIFO size data exists
(see REG[03A4h] bits 6-0)
More than 1/2 of the specified JPEG FIFO size data exists
(see REG[03A4h] bits 6-0)
11
Bit 1
JPEG FIFO Full Status
This bit indicates whether the JPEG FIFO is full.
When this bit = 1, the JPEG FIFO is full.
When this bit = 0, the JPEG FIFO is not full.
JPEG FIFO Empty Status
This bit indicates that the JPEG FIFO is empty.
When this bit = 1, the JPEG FIFO is empty.
When this bit = 0, the JPEG FIFO is not empty.
Bit 0
SSD1926
Application Note
Rev 1.0
P 137/138
Jul 2009
Solomon Systech
JPEG FIFO Size Register
Bit
7
Reserved
Type
Reset
state
RW
0
Bit 7
6
JPEG FIFO
Size Bit 6
RW
0
REG[3A4h]
5
JPEG FIFO
Size Bit 5
RW
0
4
JPEG FIFO
Size Bit 4
RW
0
3
JPEG FIFO
Size Bit 3
RO
0
2
JPEG FIFO
Size Bit2
RO
0
JPEG File Size Register 0
Type
Reset
state
7
JPEG File
Size Bit 7
RW
0
6
JPEG File
Size Bit 6
RW
0
REG[3B8h]
5
JPEG File
Size Bit 5
RW
0
4
JPEG File
Size Bit 4
RW
0
3
JPEG File
Size Bit 3
RW
0
2
JPEG File
Size Bit 2
RW
0
5
JPEG File
Size Bit 13
RW
0
4
JPEG File
Size Bit 12
RW
0
3
JPEG File
Size Bit 11
RW
0
2
JPEG File
Size Bit 10
RW
0
1
JPEG File
Size Bit 9
RW
0
5
JPEG File
Size Bit 21
RW
0
4
JPEG File
Size Bit 20
RW
0
3
JPEG File
Size Bit 19
RW
0
2
JPEG File
Size Bit 18
RW
0
1
JPEG File
Size Bit 17
RW
0
JPEG File Size Register 1
Bit
Type
Reset
state
7
JPEG File
Size Bit 15
RW
0
6
JPEG File
Size Bit 14
RW
0
Type
Reset
state
7
JPEG File
Size Bit 23
RW
0
REG[3BAh] Bits 7-0,
REG[3B9h] Bits 7-0,
REG[3B8h] Bits 7-0
Solomon Systech
6
JPEG File
Size Bit 22
RW
0
1
JPEG File
Size Bit 1
RW
0
0
JPEG File
Size Bit 0
RW
0
REG[3B9h]
JPEG File Size Register 2
Bit
0
JPEG FIFO
Size Bit 0
RO
0
Reserved bit
This bit should be programmed by 0.
JPEG FIFO Size bits [6:0]
These bits determine the JPEG FIFO size in 4K byte units. The maximum size of the
JPEG FIFO is 512K bytes. These bits also specify the amount of memory reserved for the JPEG
FIFO.
JPEG FIFO size = (REG[3A4h] bits 6-0 + 1) x 4K bytes
Bits 6-0
Bit
1
JPEG FIFO
Size Bit 1
RO
0
0
JPEG File
Size Bit 8
RW
0
REG[3BAh]
0
JPEG File
Size Bit 16
RW
0
JPEG File Size bits [23:0]
These bits specify the JPEG file size in bytes and must be set before the Host begins writing
decoded data to the JPEG FIFO.
Jul 2009
P 138/139
Rev 1.0
SSD1926
Application Note
JPEG Decode Horizontal Pixel Size Register 0
Bit
Type
Reset
state
7
JPEG
Decode
Horizontal
Pixel Size
Bit 7
RO
0
6
JPEG
Decode
Horizontal
Pixel Size
Bit 6
RO
0
5
JPEG
Decode
Horizontal
Pixel Size
Bit 5
RO
0
4
JPEG
Decode
Horizontal
Pixel Size
Bit 4
RO
0
REG[3D8h]
3
JPEG
Decode
Horizontal
Pixel Size
Bit 3
RO
0
2
JPEG
Decode
Horizontal
Pixel Size
Bit 2
RO
0
3
JPEG
Decode
Horizontal
Pixel Size
Bit 11
RO
0
2
JPEG
Decode
Horizontal
Pixel Size
Bit 10
RO
0
JPEG Decode Horizontal Pixel Size Register 1
Bit
Type
Reset
state
7
JPEG
Decode
Horizontal
Pixel Size
Bit 15
RO
0
6
JPEG
Decode
Horizontal
Pixel Size
Bit 14
RO
0
REG[3D9h] Bits 7-0,
REG[3D8h] Bits 7-0
5
JPEG
Decode
Horizontal
Pixel Size
Bit 13
RO
0
4
JPEG
Decode
Horizontal
Pixel Size
Bit 12
RO
0
Type
Reset
state
7
JPEG
Decode
Vertical
Pixel Size
Bit 7
RO
0
Type
Reset
state
7
JPEG
Decode
Vertical
Pixel Size
Bit 15
RO
0
6
JPEG
Decode
Vertical
Pixel Size
Bit 6
RO
0
6
JPEG
Decode
Vertical
Pixel Size
Bit 14
RO
0
REG[3DDh] Bits 7-0,
REG[3DCh] Bits 7-0
SSD1926
Application Note
1
JPEG
Decode
Horizontal
Pixel Size
Bit 9
RO
0
0
JPEG
Decode
Horizontal
Pixel Size
Bit 8
RO
0
JPEG Decode Horizontal Pixel Size bits [15:0]
These bits specify the horizontal image size during JPEG decode process.
5
JPEG
Decode
Vertical
Pixel Size
Bit 5
RO
0
4
JPEG
Decode
Vertical
Pixel Size
Bit 4
RO
0
REG[3DCh]
3
JPEG
Decode
Vertical
Pixel Size
Bit 3
RO
0
2
JPEG
Decode
Vertical
Pixel Size
Bit 2
RO
0
3
JPEG
Decode
Vertical
Pixel Size
Bit 11
RO
0
2
JPEG
Decode
Vertical
Pixel Size
Bit 10
RO
0
JPEG Decode Vertical Pixel Size Register 1
Bit
0
JPEG
Decode
Horizontal
Pixel Size
Bit 0
RO
0
REG[3D9h]
JPEG Decode Vertical Pixel Size Register 0
Bit
1
JPEG
Decode
Horizontal
Pixel Size
Bit 1
RO
0
Rev 1.0
5
JPEG
Decode
Vertical
Pixel Size
Bit 13
RO
0
4
JPEG
Decode
Vertical
Pixel Size
Bit 12
RO
0
1
JPEG
Decode
Vertical
Pixel Size
Bit 1
RO
0
0
JPEG
Decode
Vertical
Pixel Size
Bit 0
RO
0
REG[3DDh]
1
JPEG
Decode
Vertical
Pixel Size
Bit 9
RO
0
0
JPEG
Decode
Vertical
Pixel Size
Bit 8
RO
0
JPEG Decode Vertical Pixel Size bits [15:0]
These bits specify the vertical image size during JPEG decode process.
P 139/140
Jul 2009
Solomon Systech
JPEG Operation Mode Setting Register
Bit
7
Reserved
6
Reserved
Type
Reset
state
RW
0
RW
0
Bits 7-6
Bit 5
Bits 4, 3, 1, 0
Bit 2
5
MJPEG
Mode
RW
0
REG[400h]
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
RW
0
RW
0
RW
0
RW
0
RW
0
Reserved bits
These bits should be programmed by 0.
MJPEG mode
This bit determines if Motion JPEG mode is used for decode process.
When this bit = 1, Motion JPEG mode is used.
When this bit = 0, Still JPEG mode is used.
Reserved bits
This bit should be programmed by 0.
Reserved bit
This bit should be programmed by 1.
JPEG Operation Mode Setting Register
REG[401h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
Type
Reset
state
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 7-2
1
YUV
Decode
Format
Bit 1
RO
0
0
YUV
Decode
Format
Bit 0
RO
0
Reserved bits
These bits should be programmed by 0.
YUV Decode Format bits [1:0]
These bits indicate the YUV format of the data being decoded.
Bits 1-0
Table 2-33: YUV Format Selection
REG[401h] bits 1-0
00
01
10
11
YUV Format
4:4:4
4:2:2
4:2:0
4:1:1
JPEG Command Setting Register
Bit
Type
Reset
state
7
JPEG
Codec
SW
Reset
WO
0
Bit 7
Solomon Systech
REG[402h]
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
JPEG
Operation
Start
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
WO
0
JPEG Codec Software Reset
This bit initiates a software reset of the JPEG Codec. The JPEG Codec registers
(REG[400h]-[9A2h]) are not affected.
When a 1 is written to this bit, the JPEG Codec is reset.
When a 0 is written to this bit, there is no hardware effect.
Jul 2009
P 140/141
Rev 1.0
SSD1926
Application Note
Bits 6-1
Reserved bits
These bits should be programmed by 0.
JPEG Operation Start
This bit is used to begin a JPEG operation.
When a 1 is written to this bit, the JPEG operation is started.
When a 0 is written to this bit, there is no hardware effect.
Bit 0
JPEG Operation Status Register
REG[404h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bits 7-1
Bit 0
0
JPEG
Operation
Status
RO
0
Reserved bit
JPEG Operation Status
This bit indicates the state of the JPEG codec.
When this bit = 1, the JPEG codec is busy (decode operation is in progress).
When this bit = 0, the JPEG codec is idle.
JPEG Decode Quantization Table Number Register
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
Type
Reset
state
RW
0
RW
0
RW
0
RW
0
RW
0
Bit 7-3
REG[407h]
2
Color 3
QTable
Select
RO
0
1
Color 2
QTable
Select
RO
0
0
Color 1
QTable
Select
RO
0
Reserved bits
These bits should be programmed by 0.
Color 3 QTable Select
This bit indicates the Quantization Table used by Color 3.
Color 2 QTable Select
This bit indicates the Quantization Table used by Color 2.
Color 1 QTable Select
This bit indicates the Quantization Table used by Color 1.
Bit 2
Bit 1
Bit 0
JPEG Decode Huffman Table Register
REG[408h]
Bit
7
Reserved
6
Reserved
5
Color 3 AC
HTable
Select
4
Color 3 DC
HTable
Select
3
Color 2 AC
HTable
Select
2
Color 2 DC
HTable
Select
1
Color 1 AC
HTable
Select
0
Color 1 DC
HTable
Select
Type
Reset
state
RW
0
RW
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Bit 7-6
Reserved bits
These bits should be programmed by 0.
Color 3 AC HTable Select
This bit indicated the AC Huffman Table used by Color 3.
Color 3 DC HTable Select
This bit indicated the DC Huffman Table used by Color 3.
Bit 5
Bit 4
SSD1926
Application Note
Rev 1.0
P 141/142
Jul 2009
Solomon Systech
Bit 3
Color 2 AC HTable Select
This bit indicated the AC Huffman Table used by Color 2.
Color 2 DC HTable Select
This bit indicated the DC Huffman Table used by Color 2.
Color 1 AC HTable Select
This bit indicated the AC Huffman Table used by Color 1.
Color 1 DC HTable Select
This bit indicated the DC Huffman Table used by Color 1.
Bit 2
Bit 1
Bit 0
JPEG Decode DRI Setting Register 0
REG[40Ah]
Bit
7
JPEG
Decode
DRI Setting
bit 7
6
JPEG
Decode
DRI Setting
bit 6
5
JPEG
Decode
DRI Setting
bit 5
4
JPEG
Decode
DRI Setting
bit 4
3
JPEG
Decode
DRI Setting
bit 3
2
JPEG
Decode
DRI Setting
bit 2
1
JPEG
Decode
DRI Setting
bit 1
0
JPEG
Decode
DRI Setting
bit 0
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
JPEG Decode DRI Setting Register 1
REG[40Bh]
Bit
7
JPEG
Decode
DRI Setting
bit 15
6
JPEG
Decode
DRI Setting
bit 14
5
JPEG
Decode
DRI Setting
bit 13
4
JPEG
Decode
DRI Setting
bit 12
3
JPEG
Decode
DRI Setting
bit 11
2
JPEG
Decode
DRI Setting
bit 10
1
JPEG
Decode
DRI Setting
bit 9
0
JPEG
Decode
DRI Setting
bit 8
Type
Reset
state
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
REG [40Bh] bits 7-0,
REG [40Ah] bits 7-0
JPEG Decode DRI Setting bits [15:0]
These bits indicate DRI Setting used for the JPEG decode process.
JPEG Line Buffer Start Address Register 0
Bit
Type
Reset
state
7
JPEG Line
Buffer Start
Address Bit
7
RW
0
6
JPEG Line
Buffer Start
Address Bit
6
RW
0
5
JPEG Line
Buffer Start
Address Bit
5
RW
0
4
JPEG Line
Buffer Start
Address Bit
4
RW
0
REG[410h]
3
JPEG Line
Buffer Start
Address Bit
3
RW
0
2
JPEG Line
Buffer Start
Address Bit
2
RW
0
3
JPEG Line
Buffer Start
Address Bit
11
RW
0
2
JPEG Line
Buffer Start
Address Bit
10
RW
0
JPEG Line Buffer Start Address Register 1
Bit
Type
Reset
state
7
JPEG Line
Buffer Start
Address Bit
15
RW
0
Solomon Systech
6
JPEG Line
Buffer Start
Address Bit
14
RW
0
5
JPEG Line
Buffer Start
Address Bit
13
RW
0
4
JPEG Line
Buffer Start
Address Bit
12
RW
0
1
JPEG Line
Buffer Start
Address Bit
1
RW
0
0
0
RW
0
REG[411h]
Jul 2009
P 142/143
1
JPEG Line
Buffer Start
Address Bit
9
RW
0
Rev 1.0
0
JPEG Line
Buffer Start
Address Bit
8
RW
0
SSD1926
Application Note
JPEG Line Buffer Start Address Register 2
REG[412h]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
Type
Reset
state
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
REG[412h] Bits 1-0,
REG[411h] Bits 7-0,
REG[410h] Bits 7-0
REG[412h] Bits 7-2
Type
Reset
state
7
JPEG FIFO
Start
Address Bit
7
RW
0
6
JPEG FIFO
Start
Address Bit
6
RW
0
5
JPEG FIFO
Start
Address Bit
5
RW
0
REG[414h]
4
JPEG FIFO
Start
Address Bit
4
RW
0
3
JPEG FIFO
Start
Address Bit
3
RW
0
2
JPEG FIFO
Start
Address Bit
2
RW
0
4
JPEG FIFO
Start
Address Bit
12
RW
0
3
JPEG FIFO
Start
Address Bit
11
RW
0
2
JPEG FIFO
Start
Address Bit
10
RW
0
JPEG FIFO Start Address Register 1
Bit
Type
Reset
state
7
JPEG FIFO
Start
Address Bit
15
RW
0
6
JPEG FIFO
Start
Address Bit
14
RW
0
5
JPEG FIFO
Start
Address Bit
13
RW
0
JPEG FIFO Start Address Register 2
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
Type
Reset
state
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Rev 1.0
0
0
RW
0
1
JPEG FIFO
Start
Address Bit
9
RW
0
0
JPEG FIFO
Start
Address Bit
8
RW
0
REG[416h]
7
Reserved
REG[416h] Bits 1-0,
REG[415h] Bits 7-0,
REG[414h] Bits 7-0
REG[416h] Bits 7-2
1
JPEG FIFO
Start
Address Bit
1
RW
0
REG[415h]
Bit
SSD1926
Application Note
0
JPEG Line
Buffer Start
Address Bit
16
RW
0
JPEG Line Buffer Start Address bits [17:0]
Bit 0 must be program as 0.
These bits define the start address for the JPEG Line Buffer.
Reserved bits
These bits should be programmed by 0.
JPEG FIFO Start Address Register 0
Bit
1
JPEG Line
Buffer Start
Address Bit
17
RW
0
1
JPEG FIFO
Start
Address Bit
17
RW
0
0
JPEG FIFO
Start
Address Bit
16
RW
0
JPEG FIFO Start Address bits [17:0]
Bit 0 must be program as 0
These bits define the start address for the JPEG FIFO.
Reserved bits
These bits should be programmed by 0.
P 143/144
Jul 2009
Solomon Systech
JPEG DNL Value Setting Register 0
Bit
Type
Reset
state
7
DNL Value
Bit 7
RO
0
6
DNL Value
Bit 6
RO
0
5
DNL Value
Bit 5
RO
0
REG[418h]
4
DNL Value
Bit 4
RO
0
3
DNL Value
Bit 3
RO
0
2
DNL Value
Bit 2
RO
0
1
DNL Value
Bit 1
RO
0
4
DNL Value
Bit 12
RO
0
3
DNL Value
Bit 11
RO
0
2
DNL Value
Bit 10
RO
0
1
DNL Value
Bit 9
RO
0
JPEG DNL Value Setting Register 1
Bit
Type
Reset
state
7
DNL Value
Bit 15
RO
0
6
DNL Value
Bit 14
RO
0
REG[419h] Bits 7-0,
REG[418h] Bits 7-0
5
DNL Value
Bit 13
RO
0
0
DNL Value
Bit 0
RO
0
REG[419h]
0
DNL Value
Bit 8
RO
0
DNL Value bits [15:0]
These bits are read-only and indicate the DNL value.
JPEG RST Marker Operation Setting Register
REG[41Ch]
Bit
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
Type
Reset
state
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bits 7-2
1
RST
Marker
Operation
Select Bit 1
RW
0
0
RST
Marker
Operation
Select Bit 0
RW
0
Reserved bits
These bits should be programmed by 0.
RST Marker Operation Select bits [1:0]
These bits select the RST Marker Operation.
Bit 1-0
Table 2-34: RST Marker Selection
REG[41Ch] bits 1-0
00
01
10
11
Solomon Systech
RST Marker Operation
Error detection and data revise function is turned off
This option should only be used when it is certain that the JPEG file to
be decoded is correct and has no errors. If there is an error in the file,
no error detection will take place and the decode process will not finish
correctly.
Error detection on
When an error is detected during the decode process, the decode
process finishes and the JPEG interrupt is asserted (REG[48h] bit 2 =
1, to determine the exact nature of the error see REG[382h]). Because
the decode process finished before normal completion, all data can not
be displayed. If the JPEG file is to be decoded again with the Data
Revise function on, a software reset is required (see REG[402h] bit 7).
Data revise function on
When an error is detected during the decode process, data is
skipped/added automatically and the decode process continues
normally to the end of file. After the decode process finishes, a data
revise interrupt is asserted. Because the decode process is finished
completely, the next JPEG file can be decoded immediately.
Reserved
Jul 2009
P 144/145
Rev 1.0
SSD1926
Application Note
JPEG RST Marker Operation Status Register
Bit
Type
Reset
state
7
Revise
Code
RO
0
6
JPEG Error
Status Bit 3
RO
0
Bit 7
5
JPEG Error
Status Bit 2
RO
0
4
JPEG Error
Status Bit 1
RO
0
REG[41Eh]
3
JPEG Error
Status Bit 0
RO
0
2
Reserved
1
Reserved
0
Reserved
RW
0
RW
0
RW
0
Revise Code
This bit indicates whether a revise operation has been done.
When this bit = 1, a revise operation was done.
When this bit = 0, a revise operation was not done.
JPEG Error Status [3:0]
For the JPEG decode process, these bits indicate the type of JPEG error. If these bits return
0000, no error has occurred.
Bits 6-3
Table 2-35: JPEG Error Status
REG[41Eh] bits 6-3
0000
0001 – 1010
1011
1100
1101 - 1111
Bits 2-0
JPEG Error Status
No error
Reserved
Restart interval error
Image size error
Reserved
Reserved bits
These bits should be programmed by 0.
2.19 MMC/SD/SDIO Registers
The detailed description for registers of SDHC module (REG[1001h-11FFh]) were referred to Part A2, SD
Host Controller Standard Specification i.
The detailed description for the SDHC was referred to Part 1, Physical Layer Specificationii.
Note
i
ii
Part A2, SD Host Controller Standard Specification, Version 1.0, February 2004
Part 1, Physical Layer Specification, Version 1.01
SD_CLK Divider Register
Bit
Type
Reset
state
REG[1001h]
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
RW
0
SD_CLK
Divisor
RW
1
REG[1001h] Bits 7-1
Reserved bits
REG[1001h] Bit 0
SD_CLK Divisor bit
This bit divides the MCLK by 2 for SD_CLK. It is enabled by default.
Bit 0 = 1 : SD_CLK = MCLK / 2
Bit 0 = 0 : SD_CLK = MCLK.
The SD_CLK output will be further divides by REG[112Dh].
SSD1926
Application Note
Rev 1.0
P 145/146
Jul 2009
Solomon Systech
DMA System Address Register 0
Bit
Type
Reset
state
7
DMA
Address Bit
7
RW
0
6
DMA
Address Bit
6
RW
0
5
DMA
Address Bit
5
RW
0
REG[1100h]
4
DMA
Address Bit
4
RW
0
3
DMA
Address Bit
3
RW
0
2
DMA
Address Bit
2
RW
0
4
DMA
Address Bit
12
RW
0
3
DMA
Address Bit
11
RW
0
2
DMA
Address Bit
10
RW
0
4
DMA
Address Bit
20
RW
0
3
DMA
Address Bit
19
RW
0
2
DMA
Address Bit
18
RW
0
4
DMA
Address Bit
28
RW
0
3
DMA
Address Bit
27
RW
0
2
DMA
Address Bit
26
RW
0
DMA System Address Register 1
Bit
Type
Reset
state
7
DMA
Address Bit
15
RW
0
6
DMA
Address Bit
14
RW
0
5
DMA
Address Bit
13
RW
0
Type
Reset
state
7
DMA
Address Bit
23
RW
0
6
DMA
Address Bit
22
RW
0
5
DMA
Address Bit
21
RW
0
Type
Reset
state
7
DMA
Address Bit
31
RW
0
REG[1100h] Bits 7-0,
REG[1101h] Bits 7-0,
REG[1102h] Bits 7-0,
REG[1103h] Bits 7-0
Solomon Systech
6
DMA
Address Bit
30
RW
0
5
DMA
Address Bit
29
RW
0
1
DMA
Address Bit
9
RW
0
0
DMA
Address Bit
8
RW
0
REG[1102h]
DMA System Address Register 3
Bit
0
DMA
Address Bit
0
RW
0
REG[1101h]
DMA System Address Register 2
Bit
1
DMA
Address Bit
1
RW
0
1
DMA
Address Bit
17
RW
0
0
DMA
Address Bit
16
RW
0
REG[1103h]
1
DMA
Address Bit
25
RW
0
0
DMA
Address Bit
24
RW
0
DMA System Address bits [31:0]
This register contains the system memory address for a DMA transfer. Bits [31:16] are reserved
and should programmed as ‘0’.
When the Host Controller stops a DMA transfer, this register shall point to the system address
of the next contiguous data position. It can be accessed only if no transaction is executing (i.e.,
after a transaction has stopped). Read operations during transfers may return an invalid value.
The Host Driver shall initialize this register before starting a DMA transaction.
After DMA has stopped, the next system address of the next contiguous data position can be
read from this register.
The DMA transfer waits at the every boundary specified by the Host DMA Buffer
Boundary in the Block Size register. The Host Controller generates DMA Interrupt to request
the Host Driver to update this register. The Host Driver set the next system address of the next
data position to this register. When the most upper byte of this register (REG[1103h]) is
written, the Host Controller restart the DMA transfer.
When restarting DMA by the Resume command or by setting Continue Request in the Block
Gap Control register, the Host Controller shall start at the next contiguous address stored here
in the System Address register.
Jul 2009
P 146/147
Rev 1.0
SSD1926
Application Note
Block size Register 0
Bit
Type
Reset
state
REG[1104h]
7
6
5
4
3
2
1
0
Transfer
Block Size
Bit 7
RW
0
Transfer
Block Size
Bit 6
RW
0
Transfer
Block Size
Bit 5
RW
0
Transfer
Block Size
Bit 4
RW
0
Transfer
Block Size
Bit 3
RW
0
Transfer
Block Size
Bit 2
RW
0
Transfer
Block Size
Bit 1
RW
0
Transfer
Block Size
Bit 0
RW
0
Block size Register1
Bit
Type
Reset
state
REG[1105h]
7
6
5
4
3
2
1
0
Reserved
DMA
Buffer
Boundary
Bit 2
RW
0
DMA
Buffer
Boundary
Bit 1
RW
0
DMA
Buffer
Boundary
Bit 0
RW
0
Transfer
Block Size
Bit 11
Transfer
Block Size
Bit 10
Transfer
Block Size
Bit 9
Transfer
Block Size
Bit 8
RW
0
RW
0
RW
0
RW
0
RO
0
REG[1105h] Bit 7
Reserved bit
REG[1105h] Bits 6-4
Host DMA Buffer Boundary bits [2:0]
The large contiguous memory space may not be available in the virtual memory system. To
perform long DMA transfer, System Address register shall be updated at every system memory
boundary during DMA transfer.
These bits specify the size of contiguous buffer in the system memory in terms of byte
granularity. This requires the Host Controller to break the last access according to the left over
count of bytes.
The DMA transfer shall wait at the every boundary specified by these fields and the Host
Controller generates the DMA Interrupt to request the Host Driver to update the System
Address register.
In case of this register is set to 0 (buffer size = 4K bytes), lower 12-bit of byte address points
data in the contiguous buffer and the upper 20-bit points the location of the buffer in the system
memory. The DMA transfer stops when the Host Controller detects carry out of the address
from bit 11 to 12.
These bits shall be supported when the DMA Support in the Capabilities register is set to 1
and this function is active when the DMA Enable in the Transfer Mode register is set to 1.
000b
001b
010b
011b
100b
101b
110b
111b
SSD1926
Application Note
Rev 1.0
4K bytes (Detects A11 carry out)
8K bytes (Detects A12 carry out)
16K Bytes (Detects A13 carry out)
32K Bytes (Detects A14 carry out)
64K bytes (Detects A15 carry out)
128K Bytes (Detects A16 carry out)
256K Bytes (Detects A17 carry out)
512K Bytes (Detects A18 carry out)
P 147/148
Jul 2009
Solomon Systech
REG[1104h] Bits 7-0,
REG[1105h] Bits 3-0
Transfer Block Size bits [11:0]
This register specifies the block size for block data transfers for CMD17, CMD18, CMD24,
CMD25, and CMD53 in terms of byte granularity. This requires the Host Controller to break
the last access according to the left over count of bytes. Values ranging from 1 up to the
maximum buffer size can be set (Refer to SD Specification [i] ‘Determining Buffer block
length’). It can be accessed only if no transaction is executing (i.e., after a transaction has
stopped). Read operations during transfers may return an invalid value, and write operations
shall be ignored.
0800h
…
0200h
01FFh
…
0004h
0003h
0002h
0001h
0000h
2048 Bytes
512 Bytes
511 Bytes
4 Bytes
3 Bytes
2 Bytes
1 Byte
No data transfer
Block Count Register 0
Bit
Type
Reset
state
REG[1106h]
7
6
5
4
3
2
1
0
Block
Count Bit 7
RW
0
Block
Count Bit 6
RW
0
Block
Count Bit 5
RW
0
Block
Count Bit 4
RW
0
Block
Count Bit 3
RW
0
Block
Count Bit 2
RW
0
Block
Count Bit 1
RW
0
Block
Count Bit 0
RW
0
Block Count Register 1
Bit
Type
Reset
state
REG[1107h]
7
6
5
4
3
2
1
0
Block
Count Bit
15
RW
0
Block
Count Bit
14
RW
0
Block
Count Bit
13
RW
0
Block
Count Bit
12
RW
0
Block
Count Bit
11
RW
0
Block
Count Bit
10
RW
0
Block
Count Bit 9
Block
Count Bit 8
RW
0
RW
0
REG[1106h] Bits 7-0,
REG[1107h] Bits 7-0
Block Count bits [15:0]
This register is enabled when Block Count Enable in the Transfer Mode register is set to 1 and
is valid only for multiple block transfers. The Host Driver shall set this register to a value
between 1 and the maximum block count. The Host Controller decrements the block count after
each block transfer and stops when the count reaches zero. Setting the block count to 0 results
in no data blocks being transferred.
This register should be accessed only when no transaction is executing (i.e., after transactions
are stopped). During data transfer, read operations on this register may return an invalid value
and write operations are ignored.
When saving transfer context as a result of a Suspend command, the number of blocks yet to be
transferred can be determined by reading this register. When restoring transfer context prior to
issuing a Resume command, the Host Driver shall restore the previously saved block count.
FFFFh
……
0002h
0001h
0000h
Solomon Systech
65535 blocks
2 blocks
1 block
Stop Count
Jul 2009
P 148/149
Rev 1.0
SSD1926
Application Note
Argument Register 0
Bit
Type
Reset
state
REG[1108h]
7
6
5
4
3
2
1
0
Argument
Bit 7
RW
0
Argument
Bit 6
RW
0
Argument
Bit 5
RW
0
Argument
Bit 4
RW
0
Argument
Bit 3
RW
0
Argument
Bit 2
RW
0
Argument
Bit 1
RW
0
Argument
Bit 0
RW
0
Argument Register 1
Bit
Type
Reset
state
REG[1109h]
7
6
5
4
3
2
1
0
Argument
Bit 15
RW
0
Argument
Bit 14
RW
0
Argument
Bit 13
RW
0
Argument
Bit 12
RW
0
Argument
Bit 11
RW
0
Argument
Bit 10
RW
0
Argument
Bit 9
RW
0
Argument
Bit 8
RW
0
Argument Register 2
Bit
Type
Reset
state
REG[110Ah]
7
6
5
4
3
2
1
0
Argument
Bit 23
RW
0
Argument
Bit 22
RW
0
Argument
Bit 21
RW
0
Argument
Bit 20
RW
0
Argument
Bit 19
RW
0
Argument
Bit 18
RW
0
Argument
Bit 17
RW
0
Argument
Bit16
RW
0
Argument Register 3
Bit
Type
Reset
state
REG[110Bh]
7
6
5
4
3
2
1
0
Argument
Bit 31
RW
0
Argument
Bit 30
RW
0
Argument
Bit 29
RW
0
Argument
Bit 28
RW
0
Argument
Bit 27
RW
0
Argument
Bit 26
RW
0
Argument
Bit 25
RW
0
Argument
Bit 24
RW
0
REG[1108h] Bits 7-0,
REG[1109h] Bits 7-0,
REG[110Ah] Bits 7-0,
REG[110Bh] Bits 7-0
Argument bits [31:0]
This register contains the SD Command Argument.
The SD Command Argument is specified as bit39-8 of Command-Format in the SD Memory
Physical Layer Specification.
Transfer Mode Register 0
Bit
Type
Reset
state
REG[110Ch]
7
6
5
4
3
2
1
0
Reserved
Reserved
Auto
CMD12
Enable
Block
Count
Enable
DMA
Enable
RO
0
Data
Transfer
Direction
Select
RW
0
Reserved
RO
0
Multi /
Single
Block
Select
RW
0
RO
0
RW
0
RW
0
RW
0
Transfer Mode Register 1
Bit
Type
Reset
state
REG[110Dh]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
SSD1926
Application Note
Rev 1.0
P 149/150
Jul 2009
Solomon Systech
REG[110Ch] Bits 7,6,3
REG[110Dh] Bits 7:0
REG[110Ch] Bit 5
REG[110Ch] Bit 4
REG[110Ch] Bit 2
REG[110Ch] Bit 1
REG[110Ch] Bit 0
Transfer Mode bits [15:0]
This register is used to control the operation of data transfers. The Host Driver shall set this
register before issuing a command which transfers data (see Data Present Select in the
Command register), or before issuing a Resume command. The Host Driver shall save the value
of this register when the data transfer is suspended (as a result of a Suspend command) and
restore it before issuing a Resume command. To prevent data loss, the Host Controller shall
implement write protection for this register during data transactions. Writes to this register shall
be ignored when the Command Inhibit (DAT) in the Present State register is 1.
Reserved bits
Multi / Single Block Select
This bit enables multiple block DATA line data transfers. For any other commands, this bit
shall be set to 0. If this bit is 0, it is not necessary to set the Block Count register. (Refer to
Table 1-45)
1
Multiple Block
0
Single Block
Data Transfer Direction Select
This bit defines the direction of DAT line data transfers. The bit is set to 1 by the Host Driver to
transfer data from the SD card to the SD Host Controller and it is set to 0 for all other
commands.
1
Read (Card to Host)
0
Write (Host to Card)
Auto CMD12 Enable
Multiple block transfers for memory require CMD12 to stop the transaction. When this bit is set
to 1, the Host Controller shall issue CMD12 automatically when last block transfer is
completed. The Host Driver shall not set this bit to issue commands that do not require CMD12
to stop data transfer. In particular, secure commands defined in the SD Specification [File
Security] do not require CMD12.
1
Enable
0
Disable
Block Count Enable
This bit is used to enable the Block Count register, which is only relevant for multiple block
transfers. When this bit is 0, the Block Count register is disabled, which is useful in executing
an infinite transfer. (Refer to Table 1-45)
1
Enable
0
Disable
DMA Enable
This bit enables DMA functionality as described in SD Specification [i] ‘Supporting DMA’.
DMA can be enabled only if it is supported as indicated in the DMA Support in the
Capabilities register. If DMA is not supported, this bit is meaningless and shall always read 0.
If this bit is set to 1, a DMA operation shall begin when the Host Driver writes to the upper byte
of Command register REG[110Fh].
1
Enable
0
Disable
Table 2-36 shows the summary of how register settings determine types of data transfer.
Table 2-36: Determination of Transfer Type
Multi/Single Block Select
0
1
1
1
Solomon Systech
Block Count Enable
Don’t care
0
1
1
Block Count
Don’t care
Don’t care
Not Zero
Zero
Jul 2009
Function
Single Transfer
Infinite Transfer
Multiple Transfer
Stop Multiple Transfer
P 150/151
Rev 1.0
SSD1926
Application Note
Command Register 0
Bit
Type
Reset
state
REG[110Eh]
7
6
5
4
3
2
1
0
Command
Type Bit 1
Command
Type Bit 0
Data
Present
Select
Command
CRC Check
Enable
Reserved
Response
Type Select
Bit 1
Response
Type Select
Bit 0
RW
0
RW
0
RW
0
Command
Index
Check
Enable
RW
0
RW
0
RO
0
RW
0
RW
0
Command Register 1
Bit
Type
Reset
state
REG[110Fh]
7
6
5
4
3
2
1
0
Reserved
Reserved
RO
0
RO
0
Command
Index Bit 5
RW
0
Command
Index Bit 4
RW
0
Command
Index Bit 3
RW
0
Command
Index Bit 2
RW
0
Command
Index Bit 1
RW
0
Command
Index Bit 0
RW
0
REG[110Eh] Bit 2,
REG[110Fh] Bits 7-6
REG[110Fh] Bits 5-0
REG[110Eh] Bits 7-6
SSD1926
Application Note
Rev 1.0
Command bits [15:0]
The Host Driver shall check the Command Inhibit (DAT) bit and Command Inhibit (CMD)
bit in the Present State register before writing to this register. Writing to the upper byte of this
register triggers SD command generation. The Host Driver has the responsibility to write this
register because the Host Controller does not protect for writing when Command Inhibit
(CMD) is set.
Reserved bits
Command Index bits [5:0]
These bits shall be set to the command number (CMD0-63, ACMD0-63) that is specified in bits
45-40 of the Command-Format in the SD Memory Card Physical Layer Specification and SDIO
Card Specification.
Command Type bits [1:0]
There are three types of special commands: Suspend, Resume and Abort. These bits shall be set
to 00b for all other commands.
(1) Suspend Command
If the Suspend command succeeds, the Host Controller shall assume the SD Bus has been
released and that it is possible to issue the next command which uses the DAT line. The Host
Controller shall de-assert Read Wait for read transactions and stop checking busy for write
transactions. The interrupt cycle shall start, in 4-bit mode. If the Suspend command fails, the
Host Controller shall maintain its current state, and the Host Driver shall restart the transfer by
setting Continue Request in the Block Gap Control register. (Refer to SD Specification [i]
‘Suspend Sequence’)
(2) Resume Command
The Host Driver re-starts starts the data transfer by restoring the registers in the range of 00000Dh. (Refer to SD Specification [i] ‘Suspend and Resume mechanism’ for the register map.)
The Host Controller shall check for busy before starting write transfers.
(3) Abort Command
If this command is set when executing a read transfer, the Host Controller shall stop reads to the
buffer. If this command is set when executing a write transfer, the Host Controller shall stop
driving the DATA line. After issuing the Abort command, the Host Driver should issue a
software reset. (Refer to SD Specification [i] ‘Abort Transaction’)
11b
Abort
10b
01b
00b
Resume
Suspend
Normal
P 151/152
Jul 2009
CMD12, CMD52 for writing “I/O Abort” in
CCCR
CMD52 for writing “Function Select” in CCCR
CMD52 for writing “Bus Suspend” in CCCR
Other commands
Solomon Systech
REG[110Eh] Bit 5
Data Present Select
This bit is set to 1 to indicate that data is present and shall be transferred using the DATA line.
It is set to 0 for the following:
(1) Commands using only CMD line (ex. CMD52).
(2) Commands with no data transfer but using busy signal on SD_DATA[0] line (R1b or R5b
ex. CMD38)
(3) Resume command
1
Data Present
0
No Data Present
Command Index Check Enable
If this bit is set to 1, the Host Controller shall check the Index field in the response to see if it
has the same value as the command index. If it is not, it is reported as a Command Index Error.
If this bit is set to 0, the Index field is not checked.
1
Enable
0
Disable
Command CRC Check Enable
If this bit is set to 1, the Host Controller shall check the CRC field in the response. If an error is
detected, it is reported as a Command CRC Error. If this bit is set to 0, the CRC field is not
checked. The number of bits checked by the CRC field value changes according to the length of
the response. (Refer to D01-00 and Table 2-38 below.)
1
Enable
0
Disable
REG[110Eh] Bit 4
REG[110Eh] Bit 3
REG[110Eh] Bits 1-0
Response Type Select bits [1:0]
Table 2-37: Command Register
00
01
10
11
No Response
Response Length 136
Response Length 48
Response Length 48 check Busy after response
These bits determine Response types.
Note
(1)
In the SDIO specification, response type notation of R5b is not defined. R5 includes R5b in
the SDIO specification. But R5b is defined in this specification to specify the Host Controller
shall check busy after receiving response. For example, usually CMD52 is used as R5 but I/O
abort command shall be used as R5b.
Implementation Note
(1)
The CRC field for R3 and R4 is expected to be all “1” bits. The CRC check should be
disabled for these response types.
Table 2-38: Relation Between Parameters and the Name of Response Type
Response Type
00
01
10
10
Index Check Enable
0
0
0
1
CRC Check Enable
0
1
0
1
11
1
1
Solomon Systech
Name of Response Type
No Response
R2
R3, R4
R1, R6, R5
R1b, R5b
Jul 2009
P 152/153
Rev 1.0
SSD1926
Application Note
Response Register 15-0
Bit
Type
Reset
state
REG[1110h]-[111Fh]
7
6
5
4
3
2
1
0
Response
Bit
RO
0
Response
Bit
RO
0
Response
Bit
RO
0
Response
Bit
RO
0
Response
Bit
RO
0
Response
Bit
RO
0
Response
Bit
RO
0
Response
Bit
RO
0
REG[1110h] Bits 7-0 to
REG[111Fh] Bits 7-0
Response bits [127:0]
This register is used to store responses from SD cards.
The Table 2-39 describes the mapping of command responses from the SD Bus to this register
for each response type. In the table, R[] refers to a bit range within the response data as
transmitted on the SD Bus, REP[] refers to a bit range within the Response register.
The Response Field indicates bit positions of “Responses” defined in the SD Specification [ii].
The Table 2-39 shows that most responses with a length of 48 (R[47:0]) have 32 bits of the
response data (R[39:8]) stored in the Response register at REP[31:0]. Responses of type R1b
(Auto CMD12 responses) have response data bits R[39:8] stored in the Response register at
REP[127:96]. Responses with length 136 (R[135:0]) have 120 bits of the response data
(R[127:8]) stored in the Response register at REP[119:0].
To be able to read the response status efficiently, the Host Controller only stores part of the
response data in the Response register. This enables the Host Driver to efficiently read 32 bits
of response data in one read cycle on a 32-bit bus system. Parts of the response, the Index field
and the CRC, are checked by the Host Controller (as specified by the Command Index Check
Enable and the Command CRC Check Enable bits in the Command
Register REG[110Eh-110Fh]) and generate an error interrupt if an error is detected. The bit
range for the CRC check depends on the response length. If the response length is 48, the Host
Controller shall check R[47:1], and if the response length is 136 the Host Controller shall check
R[119:1].
Since the Host Controller may have a multiple block data DAT line transfer executing
concurrently with a CMD_wo_DAT command, the Host Controller stores the Auto CMD12
response in the upper bits (REP[127:96]) of the Response register. The CMD_wo_DAT
response is stored in REP[31:0]. This allows the Host Controller to avoid overwriting the Auto
CMD12 response with the CMD_wo_DAT and vice versa.
When the Host Controller modifies part of the Response register, as shown in the Table 2-39, it
shall preserve the unmodified bits.
Table 2-39: Response Bit Definition for Each Response Type
Kind of Response
R1, R1b (normal response)
R1b (Auto CMD12
response)
R2 (CID, CSD register)
R3 (OCR register)
R4 (OCR register)
R5,R5b
R6 (Published RCA
response)
Meaning of Response
Card Status
Card Status for Auto
CMD12
CID or CSD reg. incl.
OCR register for memory
OCR register for I/O etc
SDIO response
New published RCA[31:16]
etc
SSD1926
Application Note
P 153/154
Rev 1.0
Jul 2009
Response Field
R [39:8]
R [39:8]
Response Register
REP [31:0]
REP [127:96]
R [127:8]
R [39:8]
R [39:8]
R [39:8]
R [39:8]
REP [119:0]
REP [31:0]
REP [31:0]
REP [31:0]
REP [31:0]
Solomon Systech
Data Port Register 0
Bit
Type
Reset
state
REG[1120h]
7
6
5
4
3
2
1
0
Data Port
Bit 7
RO
0
Data Port
Bit 6
RO
0
Data Port
Bit 5
RO
0
Data Port
Bit 4
RO
0
Data Port
Bit 3
RO
0
Data Port
Bit 2
RO
0
Data Port
Bit 1
RO
0
Data Port
Bit 0
RO
0
Data Port Register 1
Bit
Type
Rese
t
state
REG[1121h]
7
6
5
4
3
2
1
0
Data Port
Bit 15
RO
0
Data Port
Bit 14
RO
0
Data Port
Bit 13
RO
0
Data Port
Bit 12
RO
0
Data Port
Bit 11
RO
0
Data Port
Bit 10
RO
0
Data Port
Bit 9
RO
0
Data Port
Bit 8
RO
0
Data Port Register 2
Bit
Type
Reset
state
REG[1122h]
7
6
5
4
3
2
1
0
Data Port
Bit 23
RO
0
Data Port
Bit 22
RO
0
Data Port
Bit 21
RO
0
Data Port
Bit 20
RO
0
Data Port
Bit 19
RO
0
Data Port
Bit 18
RO
0
Data Port
Bit 17
RO
0
Data Port
Bit 16
RO
0
Data Port Register 3
Bit
Type
Reset
state
REG[1123h]
7
6
5
4
3
2
1
0
Data Port
Bit 31
RW
0
Data Port
Bit 30
RW
0
Data Port
Bit 29
RW
0
Data Port
Bit 28
RW
0
Data Port
Bit 27
RW
0
Data Port
Bit 26
RW
0
Data Port
Bit 25
RW
0
Data Port
Bit 24
RW
0
REG[1120h] Bits 7-0,
REG[1121h] Bits 7-0,
REG[1122h] Bits 7-0,
REG[1123h] Bits 7-0
Data Port bits [31:0]
The Data Port Register shall be accessible via the MCU interface in 8-bit read and write modes
only.
Present State Register 0
Bit
Type
Reset
state
REG[1124h]
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
DATA Line
Active
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Command
Inhibit
(DAT)
RO
0
Command
Inhibit
(CMD)
RO
0
Present State Register 1
Bit
Type
Reset
state
REG[1125h]
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
RO
0
RO
0
RO
0
RO
0
Buffer
Read
Enable
RO
0
Buffer
Write
Enable
RO
0
Read
Transfer
Active
RO
0
Write
Transfer
Active
RO
0
Solomon Systech
Jul 2009
P 154/155
Rev 1.0
SSD1926
Application Note
Present State Register 2
Bit
Type
Reset
state
REG[1126h]
7
6
5
4
3
2
1
0
DATA[3:0]
Line Signal
Level Bit 3
DATA[3:0]
Line Signal
Level Bit 2
DATA[3:0]
Line Signal
Level Bit 1
DATA[3:0]
Line Signal
Level Bit 0
Card Detect
Pin Level
Card State
Stable
Card
Inserted
RO
0
RO
0
RO
0
RO
0
Write
Protect
Switch Pin
Level
RO
0
RO
0
RO
0
RO
0
Present State Register 3
Bit
Type
Reset
state
REG[1127h]
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
CMD Line
Single
Level
RO
0
Present State bits [31:0]
The Host Driver can get status of the Host Controller from this 32-bit read only register.
REG[1124h] Bits 7-3,
REG[1125h] Bits 7-4,
REG[1127h] Bits 7-1
REG[1127h] Bit 0
Reserved bits
REG[1126h] Bits 7-4
DATA[3:0] Line Signal Level
This status is used to check the DATA line level to recover from errors, and for debugging.
This is especially useful in detecting the busy signal level from SD_DATA[0]
Bit 7
SD_DATA[3]
Bit 6
SD_DATA[2]
Bit 5
SD_DATA[1]
Bit 4
SD_DATA[0]
Write Protect Switch Pin Level
The Write Protect Switch is supported for memory and combo cards.
This bit reflects the SD_WP pin
1
Write Enabled (SD_WP = 1)
0
Write Disabled (SD_WP = 0)
Card Detect Pin Level
This bit reflects the inverse value of the SD_CD pin. Debouncing is not performed on this bit.
This bit may be valid when Card State Stable is set to 1, but it is not guaranteed because of
propagation delay. Use of this bit is limited to testing since it must be debounced by software
REG[1126h] Bit 3
REG[1126h] Bit 2
1
Card present (SD_CD = 0)
0
No card present (SD_CD = 1)
Card State Stable
This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit is set to
1, it means the Card Detect Pin Level is stable. No Card state can be detected by this bit is set
to 1 and Card Inserted is set to 0. The Software Reset For All in the Software Reset register
shall not affect this bit.
1
No Card or Inserted
0
Reset or Debouncing
REG[1126h] Bit 1
SSD1926
Application Note
CMD Line Signal Level
This status is used to check the SD_CMD line level to recover from errors, and for debugging.
Rev 1.0
P 155/156
Jul 2009
Solomon Systech
REG[1126h] Bit 0
REG[1125h] Bit 3
REG[1125h] Bit 2
REG[1125h] Bit 1
Solomon Systech
Card Inserted
This bit indicates whether a card has been inserted. The Host Controller shall debounce this
signal so that the Host Driver will not need to wait for it to stabilize. Changing from 0 to 1
generates a Card Insertion interrupt in the Normal Interrupt Status register and changing from
1 to 0 generates a Card Removal interrupt in the Normal Interrupt Status register. The
Software Reset For All in the Software Reset register shall not affect this bit.
If a card is removed while its power is on and its clock is oscillating, the Host Controller shall
clear SD Bus Power in the Power Control register (REG[1129h]) and SD Clock Enable in the
Clock Control register (REG[112Ch]). In addition, the Host Driver should clear the Host
Controller by the Software Reset For All in Software Reset register. The card detect is active
regardless of the SD Bus Power.
1
Card Inserted
0
Reset or Debouncing or No Card
Implementation Note: The Host Controller starts in “Reset” state at power on and changes to
the “Debouncing” state once the debouncing clock is valid. In the “Debouncing” state, if the
Host Controller detects that the signal (SD_CD) is stable during the debounce period, the state
shall change to “Card Inserted” or “No Card”. If the card is removed while in the “Card
Inserted” state, it will immediately change to the “Debouncing” state. Since the card detect
signal is then not stable, the Host Controller will change to the “Debouncing” state.
Buffer Read Enable
This status is used for non-DMA read transfers.
The Host Controller may implement multiple buffers to transfer data efficiently. This read only
flag indicates that valid data exists in the host side buffer status. If this bit is 1, readable data
exists in the buffer. A change of this bit from 1 to 0 occurs when all the block data is read from
the buffer. A change of this bit from 0 to 1 occurs when block data is ready in the buffer and
generates the Buffer Read Ready interrupt.
1
Read enable
0
Read disable
Buffer Write Enable
This status is used for non-DMA write transfers.
The Host Controller can implement multiple buffers to transfer data efficiently. This read only
flag indicates if space is available for write data. If this bit is 1, data can be written to the buffer.
A change of this bit from 1 to 0 occurs when all the block data is written to the buffer. A change
of this bit from 0 to 1 occurs when top of block data can be written to the buffer and generates
the Buffer Write Ready interrupt.
1
Write enable
0
Write disable
Read Transfer Active
This status is used for detecting completion of a read transfer. Refer to SD specification [i]
‘Read transaction wait / continue timing’ for sequence details.
This bit is set to 1 for either of the following conditions:
(1) After the end bit of the read command.
(2) When writing a 1 to Continue Request in the Block Gap Control register to restart a read
transfer.
This bit is cleared to 0 for either of the following conditions::
(1) When the last data block as specified by block length is transferred to the System.
(2) When all valid data blocks have been transferred to the System and no current
block transfers are being sent as a result of the Stop At Block Gap Request being set to 1.
A Transfer Complete interrupt is generated when this bit changes to 0.
1
Transferring data
0
No valid data
Jul 2009
P 156/157
Rev 1.0
SSD1926
Application Note
REG[1125h] Bit 0
Write Transfer Active
This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists
in the Host Controller. Refer to SD Specification [i] ‘Write transaction wait / continue timing’
for more details on the sequence of events.
This bit is set in either of the following cases:
(1) After the end bit of the write command.
(2) When writing a 1 to Continue Request in the Block Gap Control register to restart a write
transfer.
This bit is cleared in either of the following cases:
(1) After getting the CRC status of the last data block as specified by the transfer count
(Single and Multiple)
(2) After getting the CRC status of any block where data transmission is about to be stopped by
a Stop At Block Gap Request.
During a write transaction, a Block Gap Event interrupt is generated when this bit is changed
to 0, as result of the Stop At Block Gap Request being set. This status is useful for the Host
Driver in determining when to issue commands during write busy.
1
Transferring data
0
No valid data
DATA Line Active
This bit indicates whether one of the DATA line on SD Bus is in use.
(a) In the case of read transactions
This status indicates if a read transfer is executing on the SD Bus. Changes in this value from 1
to 0 between data blocks generates a Block Gap Event interrupt in the Normal Interrupt Status
register. Refer to SD Specification [i] ‘Read transaction wait/continue timing’ for details on
timing.
This bit shall be set in either of the following cases:
(1) After the end bit of the read command.
(2) When writing a 1 to Continue Request in the Block Gap Control register to
restart a read transfer.
This bit shall be cleared in either of the following cases:
(1) When the end bit of the last data block is sent from the SD Bus to the Host
Controller.
(2) When beginning a wait read transfer at a stop at the block gap initiated by a Stop At Block
Gap Request.
The Host Controller shall wait at the next block gap by driving Read Wait at the start of the
interrupt cycle. If the Read Wait signal is already driven (data buffer cannot receive data), the
Host Controller can wait for current block gap by continuing to drive the Read Wait signal. It is
necessary to support Read Wait in order to use the suspend / resume function.
(b) In the case of write transactions
This status indicates that a write transfer is executing on the SD Bus. Changes in this
value from 1 to 0 generate a Transfer Complete interrupt in the Normal Interrupt Status
register. Refer to SD Specification [i] ‘Write transaction wait/continue timing’ for sequence
details.
This bit shall be set in either of the following cases:
(1) After the end bit of the write command.
(2) When writing to 1 to Continue Request in the Block Gap Control register to continue a
write transfer.
This bit shall be cleared in either of the following cases:
(1) When the SD card releases write busy of the last data block the Host Controller shall also
detect if output is not busy. If SD card does not drive busy signal for 8
SD Clocks, the Host Controller shall consider the card drive “Not Busy”.
(2) When the SD card releases write busy prior to waiting for write transfer as a result of a Stop
At Block Gap Request.
1
DATA Line Active
0
DATA Line Inactive
REG[1124h] Bit 2
SSD1926
Application Note
Rev 1.0
P 157/158
Jul 2009
Solomon Systech
REG[1124h] Bit 1
Command Inhibit (DAT)
This status bit is generated if either the DATA Line Active or the Read Transfer Active is set
to 1. If this bit is 0, it indicates the Host Controller can issue the next SD Command.
Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type).
Changing from 1 to 0 generates a Transfer Complete interrupt in the Normal Interrupt Status
register.
Note
(1)
The SD Host Driver can save registers in the range of 000-00Dh for a suspend transaction
after this bit has changed from 1 to 0.
1
Cannot issue command which uses the DATA line
0
Can issue command which uses the DATA line
REG[1124h] Bit 0
Command Inhibit (CMD)
If this bit is 0, it indicates the CMD line is not in use and the Host Controller can issue a SD
Command using the CMD line.
This bit is set immediately after the Command register (00Fh) is written. This bit is cleared
when the command response is received. Even if the Command Inhibit (DAT) is set to 1,
Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
generates a Command Complete interrupt in the Normal Interrupt Status register. If the Host
Controller cannot issue the command because of a command conflict error (Refer to Command
CRC Error (REG[1132h]) or because of Command Not Issued By Auto CMD12 Error
(REG[113Ch]), this bit shall remain 1 and the Command Complete is not set.
Status issuing Auto CMD12 is not read from this bit.
1
Cannot issue command
0
Can issue command using only CMD line
Implementation Note
(1)
The Host Driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for SDIO) when the DATA lines are
busy during data transfer. These commands can be issued when Command Inhibit (CMD) is set to zero.
Other commands shall be issued when Command Inhibit (DAT) is set to zero. Possible changes to the SD
Physical Specification may add other commands to this list in the future.
Implementation Note
(1)
Some fields defined in the Present State Register change values asynchronous to the system clock. The
System reads these statuses through the System Bus Interface and it may require data stable period during bus cycle. The
Host Controller should sample and hold values during reads from this register according to the timing required by the
System Bus Interface specification.
Figure 2-35 to Figure 2-37 show the timing of setting and clearing the Command Inhibit (DAT) and the
Command Inhibit (CMD).
Figure 2-35: Timing of Command Inhibit (DAT) and Command Inhibit (CMD) with data transfer
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Jul 2009
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Rev 1.0
SSD1926
Application Note
Figure 2-36: Timing of Command Inhibit (DAT) for the case of response with busy
Figure 2-37: Timing of Command Inhibit (CMD) for the case of no response command
Host Control Register
Bit
Type
Reset
state
REG[1128h]
7
6
5
4
3
2
1
0
Reserved
Bit
Reserved
Bit
Reserved
Bit
Reserved
Bit
Reserved
Bit
Reserved
Bit
LED
Control
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
Data
Transfer
Width
RW
0
RW
0
REG[1128h] Bits 7-2
Reserved bits
REG[1128h] Bit 1
Data Transfer Width bit
This bit selects the data width of the Host Controller. The Host Driver shall set it to match the
data width of the SD card.
1
4 bit mode
0
1 bit mode
LED Control bit
This bit is used to caution the user not to remove the card while the SD card is being accessed.
If the software is going to issue multiple SD commands, this bit can be set during all these
transactions. It is not necessary to change for each transaction.
If this bit = 1, LED on
If this bit = 0, LED off
REG[1128h] Bit 0
SSD1926
Application Note
Rev 1.0
P 159/160
Jul 2009
Solomon Systech
Power Control Register
Bit
Type
Reset
state
REG[1129h]
7
6
5
4
3
2
1
0
Reserved
Bit
Reserved
Bit
Reserved
Bit
Reserved
Bit
RO
0
RO
0
RO
0
SD Bus
Voltage
Select Bit 1
RW
0
SD Bus
Voltage
Select Bit 0
RW
0
SD Bus
Power Bit
RO
0
SD Bus
Voltage
Select Bit 2
RW
0
RW
0
REG[1129h] Bits 7-4
Reserved bits
REG[1129h] Bits 3-1
SD Bus Voltage bits [2:0]
By setting these bits, the Host Driver selects the voltage level for the SD card. Before setting
this register, the Host Driver shall check the Voltage Support bits in the Capabilities register.
If an unsupported voltage is selected, the Host System shall not supply SD Bus voltage.
SD Bus Voltage bits [2:0]
SD Bus Voltage
111
3.3V
110-000
Reserved
SD Bus Power bit
Before setting this bit, the SD Host Driver shall set SD Bus Voltage Select. If the Host
Controller detects the No Card state, this bit shall be cleared.
If this bit = 1, Power on
If this bit = 0, Power off
REG[1129h] Bit 0
Implementation Note
(1)
Basically, the Host Driver has responsibility to supply SD Bus voltage by SD Bus Power, according to SD card OCR
and supply voltage capabilities depend on the Host System.
If the Host Driver selects an unsupported voltage in the SD Bus Voltage Select field, the Host Controller may ignore
writes to SD Bus Power and keep its value at zero.
Implementation Note
(1)
The Host System shall not supply SD Bus power when SD Bus Power is set to 0 and can supply SD Bus power when
SD Bus Power is set to 1 depending on the system conditions (ex. Left of the battery).
Bit
Type
Reset
state
Reserved Register
7
6
Reserved
Bit
RO
0
REG[112Ah] Bits 7-0
Reserved
Bit
RO
0
5
4
3
2
Reserved
Bit
RO
0
Reserved
Bit
RO
0
Reserved
Bit
RW
0
Reserved
Bit
RW
0
Type
Reset
state
Reserved
Bit
RW
0
0
Reserved
Bit
RW
0
Reserved bits
Wake Up Control Register
Bit
REG[112Ah]
1
REG[112Bh]
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
RO
0
RO
0
RO
0
RO
0
RO
0
Wake
Event
Enable on
SD Card
Removal
RW
0
Wake
Event
Enable on
SD Card
Insertion
RW
0
Wake
Event
Enable on
SD Card
Interrupt
RW
0
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Jul 2009
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Rev 1.0
SSD1926
Application Note
REG[112Bh] Bits 7-3
Reserved bit
REG[112Bh] Bit 2
Wake Event Enable on SD Card Removal bit
This bit enables wakeup event via Card Removal assertion in the Normal Interrupt Status
register.
1
Enable
0
Disable
Wake Event Enable on SD Card Insertion bit
This bit enables wakeup event via Card Insertion assertion in the Normal Interrupt Status
register.
1
Enable
0
Disable
Wake Event Enable on SD Card interrupt bit
This bit enables wakeup event via Card Interrupt assertion in the Normal Interrupt Status
register.
1
Enable
0
Disable
REG[112Bh] Bit 1
REG[112Bh] Bit 0
Clock Control Register 0
Bit
Type
Reset
state
REG[112Ch]
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
SD Clock
Enable
RO
0
RO
0
RO
0
RO
0
RO
0
RW
0
Internal
Clock
Stable
RO
0
Internal
Clock
enable
RW
0
Clock Control Register 1
Bit
Type
Reset
state
REG[112Dh]
7
6
5
4
3
2
1
0
SDCLK
Frequency
Select bit 7
RW
0
SDCLK
Frequency
Select bit 6
RW
0
SDCLK
Frequency
Select bit 5
RW
0
SDCLK
Frequency
Select bit 4
RW
0
SDCLK
Frequency
Select bit 3
RW
0
SDCLK
Frequency
Select bit 2
RW
0
SDCLK
Frequency
Select bit 1
RW
0
SDCLK
Frequency
Select bit 0
RW
0
REG[112Dh] Bits 7-0
SSD1926
Application Note
Rev 1.0
SDCLK Frequency Select bits [7:0]
At the initialization of the Host Controller, the Host Driver shall set the SDCLK Frequency
Select.
This register is used to select the frequency of SD_CLK pin. The frequency is not
programmed directly; rather this register holds the divisor of the MCLK Frequency. Only the
following settings are allowed.
80h
MCLK divided by 256
40h
MCLK divided by 128
20h
MCLK divided by 64
10h
MCLK divided by 32
08h
MCLK divided by 16
04h
MCLK divided by 8
02h
MCLK divided by 4
01h
MCLK divided by 2
00h
MCLK (10MHz-63MHz)
Setting 00h specifies the highest frequency of the SD Clock. When setting multiple bits, the
most significant bit is used as the divisor.
According to the SD Physical Specification Version 1.01 and the SDIO Card Specification
Version 1.0, maximum SD Clock frequency is 25MHz, and shall never exceed this limit.
P 161/162
Jul 2009
Solomon Systech
Note : The SD_CLK will default divided by 2 with REG[1001h] bit 0 = 1.
The frequency of SDCLK is set by the following formula:
SDCLK Frequency = MCLK / divisor
REG[112Ch] Bits 7-3
REG[112Ch] Bit 2
REG[112Ch] Bit 1
REG[112Ch] Bit 0
Thus, choose the smallest possible divisor which results in a clock frequency that is less than or
equal to the target frequency.
For example, if the MCLK has the value 33MHz, and the target frequency is 25MHz, then
choosing the divisor value of 01h will yield 16.5MHz (if REG[1001h] bit 0 = 0), which is the
nearest frequency less than or equal to the target.
Reserved bits
SD Clock Enable
The Host Controller shall stop SD_CLK when writing this bit to 0. SDCLK Frequency Select
can be changed when this bit is 0. Then, the Host Controller shall maintain the same clock
frequency until SDCLK is stopped (Stop at SD_CLK=0). If the Host Controller detects the No
Card state, this bit shall be cleared.
1
Enable
0
Disable
Internal Clock Stable
This bit is set to 1 when SD Clock is stable after writing to Internal Clock Enable in this
register to 1. The SD Host Driver shall wait to set SD Clock Enable until this bit is set to 1.
Note: This is useful when using PLL for a clock oscillator that requires setup time.
1
Ready
0
Not Ready
Internal Clock Enable
This bit is set to 0 when the Host Driver is not using the Host Controller or the Host
Controller awaits a wakeup interrupt. The Host Controller should stop its internal clock to go
very low power state. Still, registers shall be able to be read and written. Clock starts to oscillate
when this bit is set to 1. When clock oscillation is stable, the Host Controller shall set Internal
Clock Stable in this register to 1. This bit shall not affect card detection.
1
Oscillate
0
Stop
Timeout Control Register
Bit
Type
Reset
state
REG[112Eh]
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
RO
0
RO
0
RO
0
RO
0
Timeout
Control Bit
3
RW
0
Timeout
Control Bit
2
RW
0
Timeout
Control Bit
1
RW
0
Timeout
Control Bit
0
RW
0
REG[112Eh] Bits 7-4
REG[112Eh] Bits 3-0
Solomon Systech
Reserved bits
These bits should be programmed by 0.
Timeout Control bits [3:0]
At the initialization of the Host Controller, the Host Driver shall set the Data Timeout Counter
Value according to the Capabilities register.
This value determines the interval by which DATA line timeouts are detected. Refer to the
Data Timeout Error in the Error Interrupt Status register for information on factors that
dictate timeout generation. Timeout clock frequency will be generated by dividing the base
clock MCLK value by this value. When setting this register, prevent inadvertent timeout events
by clearing the Data Timeout Error Status Enable (in the Error Interrupt Status Enable
register)
1111
Reserved
1110
MCLK x 227
…..
0001
MCLK x 214
0000
MCLK x 213
Jul 2009
P 162/162
Rev 1.0
SSD1926
Application Note
Software Reset Register
Bit
Type
Reset
state
REG[112Fh]
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
RO
0
RO
0
RO
0
RO
0
Software
Reset for
CMD Line
RWAC
0
Software
Reset for all
RO
0
Software
Reset for
DATA Line
RWAC
0
RWAC
0
REG[112Fh] Bits 7-3
Reserved bits
REG[112Fh] Bit 2
Software reset bits
A reset pulse is generated when writing 1 to each bit of this register. After completing the reset,
the Host Controller shall clear each bit. Because it takes some time to complete software reset,
the SD Host Driver shall confirm that these bits are 0.
Software Reset for DATA Line
Only part of data circuit is reset. DMA circuit is also reset.
The following registers and bits are cleared by this bit:
Buffer Data Port register
Buffer is cleared and initialized.
Present State register
Buffer Read Enable
Buffer Write Enable
Read Transfer Active
Write Transfer Active
DATA Line Active
Command Inhibit (DAT)
Block Gap Control register
Continue Request
Stop At Block Gap Request
Normal Interrupt Status register
Buffer Read Ready
Buffer Write Ready
DMA Interrupt
Block Gap Event
Transfer Complete
1
Reset
0
Work
Software Reset For CMD Line
Only part of command circuit is reset.
The following registers and bits are cleared by this bit:
Present State register
Command Inhibit (CMD)
Normal Interrupt Status register
Command Complete
1
Reset
0
Work
Software Reset For All
This reset affects the entire Host Controller except for the card detection circuit. Register bits of
type ROC, RW, RW1C, RWAC are cleared to 0. During its initialization, the Host Driver shall
set this bit to 1 to reset the Host Controller. The Host Controller shall reset this bit to 0 when
capabilities registers are valid and the Host Driver can read them.
Additional use of Software Reset For All may not affect the value of the Capabilities
registers. If this bit is set to 1, the SD card shall reset itself and must be reinitialized by the Host
Driver.
1
Reset
0
Work
REG[112Fh] Bit 1
REG[112Fh] Bit 0
SSD1926
Application Note
Rev 1.0
P 163/164
Jul 2009
Solomon Systech
Normal Interrupt Status Register 0
Bit
Type
Reset
state
REG[1130h]
7
6
5
4
3
2
1
0
Card
Removal
Card
Insertion
Buffer
Read Ready
DMA
Interrupt
Block Gap
Event
Transfer
Complete
Command
Complete
RW1C
0
RW1C
0
RW1C
0
Buffer
Write
Ready
RW1C
0
RW1C
0
RW1C
0
RW1C
0
RW1C
0
Normal Interrupt Status Register 1
Bit
Type
Reset
state
REG[1131h]
7
6
5
4
3
2
1
0
Error
Interrupt
RO
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Card
Interrupt
RO
0
REG[1131h] Bit 7
REG[1131h] Bits 6-1
REG[1131h] Bit 0
REG[1130h] Bit 7
Solomon Systech
Normal Interrupt Status bits [15:0]
The Normal Interrupt Status Enable affects reads of this register, but Normal Interrupt Signal
Enable does not affect these reads. An interrupt is generated when the Normal Interrupt Signal
Enable is enabled and at least one of the status bits is set to 1. For all bits except Card
Interrupt and Error Interrupt, writing 1 to a bit clears it; writing to 0 keeps the bit
unchanged. More than one status can be cleared with a single register write. The Card
Interrupt is cleared when the card stops asserting the interrupt; that is, when the Card Driver
services the interrupt condition.
Error Interrupt
If any of the bits in the Error Interrupt Status register are set, then this bit is set. Therefore the
Host Driver can efficiently test for an error by checking this bit first. This bit is read only.
1
Error
0
No Error
Reserved bits
Card Interrupt
Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor.
In 1-bit mode, the Host Controller shall detect the Card Interrupt without SD Clock to support
wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there
are some sample delays between the interrupt signal from the SD card and the interrupt to the
Host System. It is necessary to define how to handle this delay.
When this status has been set and the Host Driver needs to start this interrupt service, Card
Interrupt Status Enable in the Normal Interrupt Status Enable register shall be set to 0 in
order to clear the card interrupt statuses latched in the Host Controller and to stop driving the
interrupt signal to the Host System. After completion of the card interrupt service (It should
reset interrupt factors in the SD card and the interrupt signal may not be asserted), set Card
Interrupt Status Enable to 1 and start sampling the interrupt signal again.
1
Generate Card Interrupt
0
No Card Interrupt
Card Removal
This status is set if the Card Inserted in the Present State register changes from 1 to 0.
When the Host Driver writes this bit to 1 to clear this status, the status of the Card Inserted in
the Present State register should be confirmed. Because the card detect state may possibly be
changed when the Host Driver clear this bit and interrupt event may not be generated
1
Card removed
0
Card state stable or Debouncing
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P 164/165
Rev 1.0
SSD1926
Application Note
REG[1130h] Bit 6
Card Insertion
This status is set if the Card Inserted in the Present State register changes from 0 to 1.
When the Host Driver writes this bit to 1 to clear this status, the status of the Card Inserted in
the Present State register should be confirmed. Because the card detect state may possibly be
changed when the Host Driver clear this bit and interrupt event may not be generated.
1
Card inserted
0
Card state stable or Debouncing
REG[1130h] Bit 5
Buffer Read Ready
This status is set if the Buffer Read Enable changes from 0 to 1. Refer to the Buffer Read
Enable in the Present State register.
1
Ready to read buffer
0
Not ready to read buffer
REG[1130h] Bit 4
Buffer Write Ready
This status is set if the Buffer Write Enable changes from 0 to 1. Refer to the Buffer Write
Enable in the Present State register.
1
Ready to write buffer
0
Not ready to write buffer
REG[1130h] Bit 3
DMA Interrupt
This status is set if the Host Controller detects the Host DMA Buffer boundary during transfer.
Refer to the Host DMA Buffer Boundary in the Block Size register.
Other DMA interrupt factors may be added in the future. This interrupt shall not be generated
after the Transfer Complete.
1
DMA Interrupt is generated
0
No DMA Interrupt
REG[1130h] Bit 2
Block Gap Event
If the Stop At Block Gap Request in the Block Gap Control register is set, this bit is set when
both a read / write transaction is stopped at a block gap. If Stop At Block Gap Request is not
set to 1, this bit is not set to 1.
(1) In the case of a Read Transaction
This bit is set at the falling edge of the DATA Line Active Status (When the transaction is
stopped at SD Bus timing. The Read Wait must be supported in order to use this function. Refer
to SD Specification [i] ‘Read transaction wait / continue timing’ about the detail timing.
(2) Case of Write Transaction
This bit is set at the falling edge of Write Transfer Active Status (After getting CRC status at
SD Bus timing). Refer to SD Specification [i] ‘Write transaction wait / continue timing’ for
more details on the sequence of events.
1
Transaction stopped at block gap
0
No Block Gap Event
REG[1130h] Bit 1
Transfer Complete
This bit is set when a read / write transfer is completed.
(1) In the case of a Read Transaction
This bit is set at the falling edge of Read Transfer Active Status. There are two cases in which
this interrupt is generated. The first is when a data transfer is
completed as specified by data length (After the last data has been read to the
Host System). The second is when data has stopped at the block gap and
completed the data transfer by setting the Stop At Block Gap Request in the
Block Gap Control register (After valid data has been read to the Host System).
Refer to Section 3.10.3 of [i] for more details on the sequence of events.
(2) In the case of a Write Transaction
This bit is set at the falling edge of the DATA Line Active Status. There are two cases in which
this interrupt is generated. The first is when the last data is written to the SD card as specified
by data length and the busy signal released. The second is when data transfers are stopped at the
block gap by setting Stop At Block Gap Request in the Block Gap Control register and data
transfers completed. (After valid data is written to the SD card and the busy signal released).
SSD1926
Application Note
Rev 1.0
P 165/166
Jul 2009
Solomon Systech
Refer to SD Specification [i] ‘Write transaction wait / continue timing’ for more details on the
sequence of events.
The table below shows that Transfer Complete has higher priority than Data Timeout Error.
If both bits are set to 1, the data transfer can be considered complete.
Relation between Transfer Complete and Data Timeout Error
Meaning of the status
Transfer Complete
Data Timeout Error
0
0
Interrupted by another factor
0
1
Timeout occur during
transfer
1
Don’t Care
Data transfer complete
1
Data transfer complete
0
No transfer complete
REG[1130h] Bit 0
Command Complete
This bit is set when get the end bit of the command response. (Except Auto CMD12)
Refer to Command Inhibit (CMD) in the Present State register.
The table below shows that Command Timeout Error has higher priority than Command
Complete. If both bits are set to 1, it can be considered that the response was not received
correctly.
Command Complete
0
Don’t Care
Command Timeout Error
0
1
1
0
1
0
Meanin of the status
Interrupted by another factor
Response not received
within 64 SDCLK cycles.
Response received
Command complete
No command complete
Error Interrupt Status Register 0
Bit
Type
Reset
state
REG[1132h]
7
6
5
4
3
2
1
0
Current
limit Error
Data End
Bit Error
Data CRC
Error
Command
Index Error
RW1C
0
RW1C
0
RW1C
0
Command
End bit
Error
RW1C
0
Command
CRC Error
RW1C
0
Data
Timeout
Error
RW1C
0
Command
Timeout
Error
RW1C
0
Error Interrupt Status Register 1
Bit
Type
Reset
state
RW1C
0
REG[1133h]
7
6
5
4
3
2
1
0
Reserved
Block Size
Bit
Data Line
Conflict Bit
Reserved
Reserved
Reserved
RO
0
RW1C
0
RW1C
0
Response
Direction
Bit Error
RW1C
0
RO
0
RO
0
RO
0
Auto
CMD12
Error
RW1C
0
Signals defined in this register can be enabled by the Error Interrupt Status Enable register, but
not by the Error Interrupt Signal Enable register. The interrupt is generated when the Error
Interrupt Signal Enable is enabled and at least one of the statuses is set to 1. Writing to 1 clears
the bit and writing to 0 keeps the bit unchanged. More than one status can be cleared at the one
register write.
Solomon Systech
Jul 2009
P 166/166
Rev 1.0
SSD1926
Application Note
REG[1133h] Bits 7, 3-1
Reserved bit
REG[1133h] Bit 6
Block Size Error Bit
This bit indicates that a Block Size limit error was detected. A Block Size limit error is detected
when the programmed Block Size for a read or write transaction is set to 0 or greater than 2048.
This bit is not set when the corresponding status enable bit is not enabled.
Data Line Conflict
This bit indicates that a DATA Line Conflict was detected on SD_DATA0 or additionally on
SD_DATA1-3 when the 4-bit Transfer Mode is selected. This bit is not set when the
corresponding status enable bit is not enabled.
Response Direction Bit Error
This bit indicates that the Card-to-Host Transmitter bit was not set to ‘0’. This bit is not set
when the corresponding status enable bit is not enabled.
Auto CMD12 Error
Occurs when detecting that one of the bits in Auto CMD12 Error Status register has changed
from 0 to 1. This bit is set to 1,not only when the errors in Auto CMD12 occur but also when
Auto CMD12 is not executed due to the previous command error.
1
Error
0
No Error
Current Limit Error
By setting the SD Bus Power bit in the Power Control register, the Host Controller is requested
to supply power for the SD Bus. If the Host Controller supports the Current Limit function, it
can be protected from an illegal card by stopping power supply to the card in which case this bit
indicates a failure status. Reading 1 means the Host Controller is not supplying power to SD
card due to some failure. Reading 0 means that the Host Controller is supplying power and no
error has occurred. The Host Controller may require some sampling time to detect the current
limit. If the Host Controller does not support this function, this bit shall always be set to 0.
1
Power failed
0
No Error
Data End Bit Error
Occurs either when detecting 0 at the end bit position of read data which uses the DATA line or
at the end bit position of the CRC Status.
1
Error
0
No Error
Data CRC Error
Occurs when detecting CRC error when transferring read data which uses the DATA line or
when detecting the Write CRC status having a value of other than "010".
1
Error
0
No Error
Data Timeout Error
Occurs when detecting one of following timeout conditions.
(1) Busy timeout for R1b,R5b type
(2) Busy timeout after Write CRC status
(3) Write CRC Status timeout
(4) Read Data timeout.
1
Time out
0
No Error
Command Index Error
Occurs if a Command Index error occurs in the command response.
1
Error
0
No Error
Command End Bit Error
Occurs when detecting that the end bit of a command response is 0.
1
End Bit Error Generated
0
No Error
REG[1133h] Bit 5
REG[1133h] Bit 4
REG[1133h] Bit 0
REG[1132h] Bit 7
REG[1132h] Bit 6
REG[1132h] Bit 5
REG[1132h] Bit 4
REG[1132h] Bit 3
REG[1132h] Bit 2
SSD1926
Application Note
Rev 1.0
P 167/168
Jul 2009
Solomon Systech
REG[1132h] Bit 1
Command CRC Error
Command CRC Error is generated in two cases.
(1) If a response is returned and the Command Timeout Error is set to 0 (indicating no
timeout), this bit is set to 1 when detecting a CRC error in the command response.
(2) The Host Controller detects a CMD line conflict by monitoring the CMD line when a
command is issued. If the Host Controller drives the CMD line to 1 level, but detects 0 level on
the CMD line at the next SDCLK edge, then the Host Controller shall abort the command (Stop
driving CMD line) and set this bit to 1. The Command Timeout Error shall also be set to 1 to
distinguish CMD line conflict (Refer to Table 1-50).
1
CRC Error Generated
0
No Error
Command Timeout Error
Occurs only if no response is returned within 64 SDCLK cycles from the end bit of the
command. If the Host Controller detects a CMD line conflict, in which case Command CRC
Error shall also be set as shown in Table 2-40, this bit shall be set without waiting for 64
SDCLK cycles because the command will be aborted by the Host Controller.
1
Time out
0
No Error
REG[1132h] Bit 0
The relation between Command CRC Error and Command Timeout Error is shown in Table 2-40.
Table 2-40: The relation between Command CRC Error and Command Timeout Error
Command CRC Error
0
0
1
1
Command Timeout Error
0
1
0
1
Kinds of error
No Error
Response Timeout Error
Response CRC Error
CMD line conflict
Normal Interrupt Status Enable Register 0
Bit
Type
Reset
state
REG[1134h]
7
6
5
4
3
2
1
0
Card
Removal
Status
Enable
Card
Insertion
Status
Enable
Buffer
Read Ready
Status
Enable
DMA
Interrupt
Status
Enable
Block Gap
Event
Status
Enable
Transfer
Complete
Status
Enable
Command
Complete
Status
Enable
RW
0
RW
0
RW
0
Buffer
Write
Ready
Status
Enable
RW
0
RW
0
RW
0
RW
0
RW
0
3
2
Normal Interrupt Status Enable Register 1
Bit
7
0
Type
Reset
state
RO
0
6
Reserved
5
Reserved
RO
0
RO
0
4
Reserved
RO
0
REG[1135h] Bits 7-1
This bit should be readback as 0.
REG[1135h] Bits 6-1
Reserved bit
Solomon Systech
REG[1135h]
Reserved
RO
0
Jul 2009
Reserved
RO
0
P 168/169
1
0
Reserved
RO
0
Rev 1.0
Card
Interrupt
Status
Enable
RW
0
SSD1926
Application Note
REG[1135h] Bit 0
Card Interrupt Status Enable
If this bit is set to 0, the Host Controller shall clear interrupt request to the System. The Card
Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1.
The Host Driver should clear the Card Interrupt Status Enable before servicing the Card
Interrupt and should set this bit again after all interrupt requests from the card are cleared to
prevent inadvertent interrupts.
1
Enabled
0
Masked
Card Removal Status Enable
1
Enabled
0
Masked
Card Insertion Status Enable
1
Enabled
0
Masked
Buffer Read Ready Status Enable
1
Enabled
0
Masked
Buffer Write Ready Status Enable
1
Enabled
0
Masked
DMA Interrupt Status Enable
1
Enabled
0
Masked
Block Gap Event Status Enable
1
Enabled
0
Masked
Transfer Complete Status Enable
1
Enabled
0
Masked
Command Complete Status Enable
1
Enabled
0
Masked
REG[1134h] Bit 7
REG[1134h] Bit 6
REG[1134h] Bit 5
REG[1134h] Bit 4
REG[1134h] Bit 3
REG[1134h] Bit 2
REG[1134h] Bit 1
REG[1134h] Bit 0
Implementation Note
The Host Controller may sample the card interrupt signal during interrupt period and may hold its value in the flipflop. If the Card Interrupt Status Enable is set to 0, the Host Controller shall clear all internal signals regarding Card
Interrupt.
(1)
Error Interrupt Status Enable Register 0
Bit
Type
Reset
state
Bit
Type
Reset
state
REG[1136h]
7
6
5
4
3
2
1
0
Current
Limit Error
Status
Enable
RW
0
Data End
Bit Error
Status
Enable
RW
0
Data CRC
Error Status
Enable
Data
Timeout
Error Status
Enable
RW
0
Command
Index Error
Status
Enable
RW
0
Command
End Bit
Error Status
Enable
RW
0
Command
CRC Error
Status
Enable
RW
0
Command
Timeout
Error Status
Enable
RW
0
4
3
2
RW
0
Error Interrupt Status Enable Register 1
7
6
5
REG[1137h]
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
SSD1926
Application Note
Rev 1.0
P 169/170
Jul 2009
0
Auto
CMD12
Error Status
Enable
RW
0
Solomon Systech
REG[1137h] Bits 7-1
Reserved bits
REG[1137h] Bit 0
Auto CMDI2 Error Status Enable
1
Enabled
0
Masked
Current Limit Error Status Enable
1
Enabled
0
Masked
Data End Bit Error Status Enable
1
Enabled
0
Masked
Data CRC Error Status Enable
1
Enabled
o
Masked
Data Timeout Error Status Enable
1
Enabled
0
Masked
Command Index Error Status Enable
1
Enabled
0
Masked
Command End Bit Error Status Enable
1
Enabled
0
Masked
Command CRC Error Status Enable
1
Enabled
0
Masked
Command Timeout Error Status Enable
1
Enabled
0
Masked
REG[1136h] Bit 7
REG[1136h] Bit 6
REG[1136h] Bit 5
REG[1136h] Bit 4
REG[1136h] Bit 3
REG[1136h] Bit 2
REG[1136h] Bit 1
REG[1136h] Bit 0
Implementation Note
To detect SD_CMD line conflict, the Host Driver must set Status Enable and Command CRC Error Status Enable to
1.
(1)
Bit
Type
Reset
state
Normal Interrupt Signal Enable Register 0
7
6
5
Card
Removal
Signal
Enable
Card
Insertion
Signal
Enable
Buffer
Read Ready
Signal
Enable
RW
0
RW
0
RW
0
3
2
Buffer
Write
Ready
Signal
Enable
RW
0
DMA
Interrupt
Signal
Enable
Block Gap
Event
Signal
Enable
Transfer
Complete
Signal
Enable
Command
Complete
Signal
Enable
RW
0
RW
0
RW
0
RW
0
Normal Interrupt Signal Enable Register 1
Bit
Type
Reset
state
REG[1138h]
1
4
0
REG[1139h]
7
6
5
4
3
2
1
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Card
Interrupt
Signal
Enable
RW
0
This register is used to select which interrupt status is indicated to the Host System as the
interrupt. These status bits all share the same bit interrupt line. Setting any of these bits to 1
enables interrupt generation.
Solomon Systech
Jul 2009
P 170/171
Rev 1.0
SSD1926
Application Note
REG[1139h] Bit 7
This bit should be readback as 0.
REG[1139h] Bit 6-1
Reserved bits
REG[1139h] Bit 0
Card Interrupt Signal Enable
1
Enabled
0
Masked
Card Removal Signal Enable
1
Enabled
0
Masked
Card Insertion Signal Enable
1
Enabled
0
Masked
Buffer Read Ready Signal Enable
1
Enabled
0
Masked
Buffer Write Ready Signal Enable
1
Enabled
0
Masked
DMA Interrupt Signal Enable
1
Enabled
0
Masked
Block Gap Event Signal Enable
1
Enabled
0
Masked
Transfer Complete Signal Enable
1
Enabled
0
Masked
Command Complete Signal Enable
1
Enabled
0
Masked
REG[1138h] Bit 7
REG[1138h] Bit 6
REG[1138h] Bit 5
REG[1138h] Bit 4
REG[1138h] Bit 3
REG[1138h] Bit 2
REG[1138h] Bit 1
REG[1138h] Bit 0
Bit
Type
Reset
state
Bit
Type
Reset
state
Error Interrupt Signal Enable Register 0
7
6
5
Current
Limit Error
Signal
Enable
Data End
Bit Error
Signal
Enable
Data CRC
Error
Signal
Enable
RW
0
RW
0
RW
0
Error Interrupt Signal Enable Register 1
7
6
5
4
3
2
Data
Timeout
Error
Signal
Enable
RW
0
Command
Index Error
Signal
Enable
RW
0
Command
End Bit
Error
Signal
Enable
RW
0
4
3
2
REG[113Ah]
1
Command
CRC Error
Signal
Enable
RW
0
REG[113Bh]
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
0
Command
Timeout
Error
Signal
Enable
RW
0
0
Auto
CMD12
Error
Signal
Enable
RW
0
This register is used to select which interrupt status is notified to the Host System as the
interrupt. These status bits all share the same 1 bit interrupt line. Setting any of these bits to 1
enables interrupt generation.
SSD1926
Application Note
Rev 1.0
P 171/172
Jul 2009
Solomon Systech
REG[113Bh] Bits 7-1
Reserved bits
REG[113Bh] Bit 0
Auto CMDI2 Error Signal Enable
1
Enabled
0
Masked
Current Limit Error Signal Enable
1
Enabled
0
Masked
Data End Bit Error Signal Enable
1
Enabled
0
Masked
Data CRC Error Signal Enable
1
Enabled
0
Masked
Data Timeout Error Signal Enable
1
Enabled
0
Masked
Command Index Error Signal Enable
1
Enabled
0
Masked
Command End Bit Error Signal Enable
1
Enabled
0
Masked
Command CRC Error Signal Enable
1
Enabled
0
Masked
Command Timeout Error Signal Enable
1
Enabled
0
Masked
REG[113Ah] Bit 7
REG[113Ah] Bit 6
REG[113Ah] Bit 5
REG[113Ah] Bit 4
REG[113Ah] Bit 3
REG[113Ah] Bit 2
REG[113Ah] Bit 1
REG[113Ah] Bit 0
Auto CMD12 Error Status Register 0
Bit
Type
Reset
state
REG[113Ch]
7
6
5
4
3
2
1
0
Command
Not Issued
by Auto
CMD12
Error
RO
0
Reserved
Reserved
Auto
CMD12
Index Error
Auto
CMD12
End Bit
Error
Auto
CMD12
CRC Error
Auto
CMD12
Timeout
Error
Auto
CMD12 not
executed
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Auto CMD12 Error Status Register 1
Bit
Type
Reset
state
REG[113Dh]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
REG[113Dh] Bits 7-0
REG[113Ch] Bit 7
Solomon Systech
When Auto CMDI2 Error Status is set, the Host Driver shall check this register to identify what
kind of errorAuto CMD12 indicated. This register is valid only when the Auto CMDI2 Error is
set.
Reserved bits
Command Not Issued By Auto CMDI2 Error
Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 Error
(D04-D01) in this register.
1 Not Issued
0 No error
Jul 2009
P 172/173
Rev 1.0
SSD1926
Application Note
REG[113Ch] Bits 6-5
Reserved bits
REG[113Ch] Bit 4
Auto CMDI2 Index Error
Occurs if the Command Index error occurs in response to a command.
1 Error
0 No error
Auto CMDI2 End Bit Error
Occurs when detecting that the end bit of command response is 0.
1 End Bit Error Generated
0 No error
Auto CMDI2 CRC Error
Occurs when detecting a CRC error in the command response.
1 CRC Error Generated
0 No error
Auto CMDI2 Timeout Error
Occurs if no response is returned within 64 SDCLK cycles from the end bit of command.
If this bit is set to 1, the other error status bits (D04-D02) are meaningless.
1 Time out
0 No error
Auto CMDI2 Not Executed
If memory multiple block data transfer is not started due to command error, this bit is not set
because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the Host Controller
cannot issue Auto CMD12 to stop memory multiple block data transfer due to some error. If
this bit is set to 1, other error status bits (D04-D01) are meaningless.
1 Not executed
0 Executed
REG[113Ch] Bit 3
REG[113Ch] Bit 2
REG[113Ch] Bit 1
REG[113Ch] Bit 0
The relation between Auto CMDI2 CRC Error and Auto CMDI2 Timeout Error is shown in Table 2-41.
Table 2-41: The relation between Command CRC Error and Command Timeout Error for Auto CMDI2
Auto CMDI2 CRC Error
0
0
1
1
Auto CMDI2 Timeout Error
0
1
0
1
Kinds of error
No Error
Response Timeout Error
Response CRC Error
CMD line conflict
The timing of changing Auto CMDI2 Error Status can be classified in three scenarios:
(1) When the Host Controller is going to issue Auto CMD12
Set D00 to 1 if Auto CMD12 cannot be issued due to an error in the previous command.
Set D00 to 0 if Auto CMD12 is issued.
(2) At the end bit of an Auto CMD12 response
Check received responses by checking the error bits D0l, D02, D03 and D04.
Set to 1 if error is detected.
Set to 0 if error is not detected.
(3) Before reading the Auto CMD12 Error Status bit D07
Set D07 to 1 if there is a command cannot be issued
Set D07 to 0 if there is no command to issue
Timing of generating the Auto CMDI2 Error and writing to the Command register are asynchronous. Then
D07 shall be sampled when driver never writing to the Command register. So just before reading the Auto
CMDI2 Error Status register is good timing to set the D07 status bit.
An Auto CMD12 Error Interrupt is generated when one of the error bits D00 to D04 is set to 1. The Command Not
Issued By Auto CMDI2 Error does not generate an interrupt.
SSD1926
Application Note
Rev 1.0
P 173/174
Jul 2009
Solomon Systech
Reserved Register
Bit
Type
Reset
state
REG[113Eh]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved Register
Bit
Type
Reset
state
REG[113Fh]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
REG[113Eh] Bits 7-0,
REG[113Fh] Bits 7-0
Reserved bits
Capabilities Register 0
Bit
Type
Reset
state
REG[1140h]
7
6
5
4
3
2
1
0
Timeout
clock unit
Reserved
Timeout
clock
frequency 5
Timeout
clock
frequency 4
Timeout
clock
frequency 3
Timeout
clock
frequency 2
Timeout
clock
frequency 1
Timeout
clock
frequency 0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Capabilities Register 1
Bit
Type
Reset
state
REG[1141h]
7
6
5
4
3
2
1
0
Reserved
Reserved
Base clock
Freq for SD
Clock 5
Base clock
Freq for SD
Clock 4
Base clock
Freq for SD
Clock 3
Base clock
Freq for SD
Clock 2
Base clock
Freq for SD
Clock 1
Base clock
Freq for SD
Clock 0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Capabilities Register 2
Bit
Type
Reset
state
REG[1142h]
7
6
5
4
3
2
1
0
Suspend /
Resume
support
DMA
support
High speed
support
Reserved
Reserved
Reserved
Max block
length 1
Max block
length 0
RO
0
RO
1
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
Capabilities Register 3
Bit
Type
Reset
state
REG[1143h]
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3.3V Voltage
support
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
1
Solomon Systech
Jul 2009
P 174/175
Rev 1.0
SSD1926
Application Note
Capabilities Register 4
Bit
Type
Reset
state
REG[1144h]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Capabilities Register 5
Bit
Type
Reset
state
REG[1145h]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Capabilities Register 6
Bit
Type
Reset
state
REG[1146h]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Capabilities Register 7
Bit
Type
Reset
state
REG[1147h]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
REG[1143h] Bits 7-1
REG[1143h] Bit 0
REG[1142h] Bit 7
REG[1142h] Bit 6
REG[1142h] Bit 5
REG[1142h] Bits 4-2
SSD1926
Application Note
Rev 1.0
This register provides the Host Driver with information specific to the Host Controller
implementation. The Host Controller may implement these values as fixed or loaded from flash
memory during power on initialization. Refer to Software Reset For All in the Software Reset
register for loading from flash memory and completion timing control.
Reserved bits
Voltage Support 3.3V
1
3.3V Supported
0
3.3V Not Supported
Suspend/Resume Support
This bit indicates whether the Host Controller supports Suspend / Resume functionality. If this
bit is 0, the Suspend and Resume mechanism (Refer to SD Specification [i] ‘Suspend and
Resume mechanism’) are not supported and the Host Driver shall not issue either Suspend or
Resume commands.
1
Supported
0
Not supported
DMA Support
This bit indicates whether the Host Controller is capable of using DMA to transfer data between
system memory and the Host Controller directly.
1
DMA Supported
0
DMA not supported
High Speed Support
This bit indicates whether the Host Controller and the Host System support High Speed mode
and they can supply SD Clock frequency from 25MHz to 50MHz.
1
High Speed Supported
0
High Speed not supported
Reserved bits
P 175/176
Jul 2009
Solomon Systech
REG[1142h] Bits 1-0
Max Block Length bits [1:0]
This value indicates the maximum block size that the Host Driver can read and write to the
buffer in the Host Controller. The buffer shall transfer this block size without wait cycles.
Block sizes can be defined as indicated below.
00/10/11
01
Reserved
1024
REG[1141h] Bits 7-6
Reserved bits
REG[1141h] Bits 5-0
Base Clock Frequency for SD Clock bits [5:0]
This value indicates the base (maximum) clock frequency for the SD Clock. Unit values are
1MHz. If the real frequency is 16.5MHz, the lager value shall be set 01 0001b (17MHz)
because the Host Driver use this value to calculate the clock divider value (Refer to the
SDCLK Frequency Select in the Clock Control register.) and it shall not exceed upper limit of
the SD Clock frequency. The supported clock range is 10MHz to 63MHz. If these bits are all 0,
the Host System has to get information via another method.
REG[1140h] Bit 7
REG[1140h] Bit 6
REG[1140h] Bits 5-0
REG[1144h] Bits 7-0
REG[1145h] Bits 7-0
REG[1146h] Bits 7-0
REG[1147h] Bits 7-0
Not 0 Reserved
0
Get information via another method
Timeout Clock unit
This bit shows the unit of base clock frequency used to detect Data Timeout Error.
0
kHz
1
MHz
Reserved bit
Timeout clock Frequency bits [5:0]
This bit shows the base clock frequency used to detect Data Timeout Error.
The Timeout Clock Unit defines the unit of this fields value.
Timeout Clock Unit =0 [KHz] unit: 1KHz to 63KHz
Timeout Clock Unit =1 [MHz] unit: 1MHz to 63MHz
Not 0 1KHz to 63KHz or 1MHz to 63MHz
0
Get information via another method
Reserved bits
Maximum Current Capabilities Register 0
Bit
Type
Reset
state
REG[1148h]
7
6
5
4
3
2
1
0
Maximum
current for
3.3V bit 7
RO
0
Maximum
current for
3.3V bit 6
RO
0
Maximum
current for
3.3V bit 5
RO
0
Maximum
current for
3.3V bit 4
RO
0
Maximum
current for
3.3V bit 3
RO
0
Maximum
current for
3.3V bit 2
RO
0
Maximum
current for
3.3V bit 1
RO
0
Maximum
current for
3.3V bit 0
RO
0
Maximum Current Capabilities Register 1
Bit
Type
Reset
state
REG[1149h]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Solomon Systech
Jul 2009
P 176/177
Rev 1.0
SSD1926
Application Note
Maximum Current Capabilities Register 2
Bit
Type
Reset
state
REG[114Ah]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Maximum Current Capabilities Register 3
Bit
Type
Reset
state
REG[114Bh]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Maximum Current Capabilities Register 4
Bit
Type
Reset
state
REG[114Ch]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Maximum Current Capabilities Register 5
Bit
Type
Reset
state
REG[114Dh]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Maximum Current Capabilities Register 6
Bit
Type
Reset
state
REG[114Eh]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Maximum Current Capabilities Register 7
Bit
Type
Reset
state
REG[114Fh]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
REG[1149h-114Fh]
Bits 7-0
Reserved bits
REG[1148H] BITS 7-0
Maximum Current for 3.3V bits [7:0]
SSD1926
Application Note
Rev 1.0
P 177/178
Jul 2009
Solomon Systech
Slot Interrupt Register 0
Bit
Type
Reset
state
REG[11FCh]
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0
Slot 0
Interrupt
status
RO
0
Slot Interrupt Register 1
Bit
Type
Reset
state
REG[11FDh]
7
6
5
4
3
2
1
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
Reserved
RO
0
REG[11FDh] Bits 7-0
REG[11FCh] Bits 7-6
Reserved bits
REG[11FCh] Bit 0
Slot Interrupt bit
The Host Controller supports only 1 slot.
This status bits indicate the logical OR of Interrupt Signal and Wakeup Signal for each slot. A
maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots, the
Host Driver can know which interrupt is generated by reading these status bits.
By a power on reset or by setting Software Reset For All, the interrupt signal shall be deasserted and this status shall read 00h.
Host Controller Version Register 0
Bit
Type
Reset
state
REG[11FEh]
7
6
5
4
3
2
1
0
Specificatio
n version
number bit
7
RO
0
Specificatio
n version
number bit
6
RO
0
Specificatio
n version
number bit
5
RO
0
Specificatio
n version
number bit
4
RO
0
Specificatio
n version
number bit
3
RO
0
Specificatio
n version
number bit
2
RO
0
Specificatio
n version
number bit
1
RO
0
Specificatio
n version
number bit
0
RO
0
Host Controller Version Register 1
Bit
Type
Reset
state
REG[11FFh]
7
6
5
4
3
2
1
0
Vendor
version
number bit
7
RO
0
Vendor
version
number bit
6
RO
0
Vendor
version
number bit
5
RO
0
Vendor
version
number bit
4
RO
1
Vendor
version
number bit
3
RO
0
Vendor
version
number bit
2
RO
0
Vendor
version
number bit
1
RO
0
Vendor
version
number bit
0
RO
0
REG[11FFh] Bits 7-0,
REG[11FEh] Bits 7-0,
Solomon Systech
Vendor version bits [7:0]
The Vendor Version Number field is implementation specific and shall be 2 BCD fields. The
value of the Vendor Version Number shall be set to 0x10 to indicate Version 1.0 of the Host
Controller design.
Specification version bits [7:0]
The Specification Version Number shall be set to 8’ b0 to indicate SD Host Specification, V1.0.
Jul 2009
P 178/179
Rev 1.0
SSD1926
Application Note
Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any, and all, liability, including without
limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters,
including “Typical” must be validated for each customer application by the customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the
part.
http://www.solomon-systech.com
SSD1926
Application Note
Rev 1.0
P 179/180
Jul 2009
Solomon Systech
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