prog16lx-cm44-00201-2e.pdf

FUJITSU MICROELECTRONICS
CONTROLLER MANUAL
CM44-00201-3E
2
F MC-16LX
16-BIT MICROCONTROLLER
PROGRAMMING MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
PROGRAMMING MANUAL
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Objectives and Intended Readership
The F2MC-16LX series products are original 16-bit one-chip microcontrollers that support application
specific ICs (ASICs). They are suitable for use in various types of industrial equipment, office-automation
equipment, on-vehicle equipment, and other equipment that is required to operate at high speed in real-time
mode.
Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■ Trademark
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
■ Configuration of this Manual
This manual contains the following 9 chapters and appendix.
CHAPTER 1 OVERVIEW OF THE F2MC-16LX CPU CORE AND SAMPLE CONFIGURATION
INCLUDING IT
This chapter briefly describes the configuration of the F2MC-16LX CPU core, and presents a sample
configuration of a device incorporating it.
CHAPTER 2 MEMORY SPACE
This chapter describes the memory spaces of the F2MC-16LX CPU.
CHAPTER 3 DEDICATED REGISTERS
This chapter describes the dedicated registers of the F2MC-16LX CPU.
CHAPTER 4 GENERAL-PURPOSE REGISTERS
This chapter describes the general-purpose registers of the F2MC-16LX CPU.
CHAPTER 5 PREFIX CODES
The operation of an instruction can be modified by prefixing it with prefix code. This chapter explains
the prefix codes.
CHAPTER 6 INTERRUPT HANDLING
This chapter describes the F2MC-16LX interrupt handling functions and their operations.
CHAPTER 7 ADDRESSING
This chapter explains the addressing mode for each instruction of the F2MC-16LX.
CHAPTER 8 INSTRUCTION OVERVIEW
This chapter explains the meanings of items and symbols used in explanations in "CHAPTER 9
DETAILED EXECUTION INSTRUCTIONS".
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
This chapter describes each execution instruction used in the assembler in a reference format.
APPENDIX
The appendix section includes lists of instructions used in the F2MC-16LX, as well as the related
instruction maps.
i
■ References
The following manuals should be referred along with this manual:
• F2MC-16LX/16L/16/16H/16F Assembler Manual
• F2MC-16LX Model-Specific Hardware Manual
•
•
•
•
•
•
•
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU
MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of
such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of
the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU
MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any thirdparty's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no
liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of
information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©1998-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
ii
READING THIS MANUAL
■ Page Layout
In this manual, an entire section is presented on a single page or spread whenever possible. You can thus
view a section without having to flip pages.
The content of each section is summarized immediately below the title. You can obtain a rough overview
of this product by reading through these summaries.
Also, higher level section headings are given in lower sections so that you can know to which section the
text your are currently reading belongs.
iii
iv
CONTENTS
CHAPTER 1
1.1
1.2
Overview of the F MC-16LX CPU Core ............................................................................................ 2
Sample Configuration of an F2MC-16LX Device ................................................................................ 3
Dedicated Register Types ............................................................................................
Accumulator (A) ................................................................................................................................
User Stack Pointer (USP) and System Stack Pointer (SSP) ............................................................
Processor Status (PS) ......................................................................................................................
Interrupt Level Mask Register (ILM) ............................................................................................
Register Bank Pointer (RP) .........................................................................................................
Condition Code Register (CCR) ..................................................................................................
Program Counter (PC) ......................................................................................................................
Direct Page Register (DPR) ..............................................................................................................
Bank Registers .................................................................................................................................
GENERAL-PURPOSE REGISTERS .......................................................... 29
PREFIX CODES ......................................................................................... 33
Bank Select Prefix ............................................................................................................................
Common Register Bank Prefix (CMR) ..............................................................................................
Flag Change Inhibit Prefix Code (NCC) ............................................................................................
Constraints Related to the Prefix Codes ...........................................................................................
CHAPTER 6
6.1
6.2
6.3
6.4
6.5
6.5.1
6.5.2
6.6
16
18
20
22
23
24
25
26
27
28
Register Banks in RAM ..................................................................................................................... 30
Calling General-purpose Registers in RAM ...................................................................................... 31
CHAPTER 5
5.1
5.2
5.3
5.4
DEDICATED REGISTERS ......................................................................... 15
F2MC-16LX
CHAPTER 4
4.1
4.2
MEMORY SPACE ........................................................................................ 5
CPU Memory Space ........................................................................................................................... 6
Linear Addressing Mode ..................................................................................................................... 7
Bank Addressing Mode ....................................................................................................................... 9
Memory Space Divided into Banks and Value in Each Bank Register ............................................. 11
Data Configuration of and Access to Multi-byte Data in Memory ..................................................... 12
CHAPTER 3
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.5
3.6
3.7
1
2
CHAPTER 2
2.1
2.2
2.3
2.4
2.5
OVERVIEW OF THE F2MC-16LX CPU CORE AND SAMPLE
CONFIGURATION INCLUDING IT
34
36
37
38
INTERRUPT HANDLING ........................................................................... 41
Interrupt Handling .............................................................................................................................
Hardware Interrupt Operation Flow ..................................................................................................
Interrupt Handling Flowchart and Saving the Contents of Registers ................................................
Interrupt Vectors ...............................................................................................................................
Extended Intelligent I/O Service .......................................................................................................
Flowchart of Extended Iintelligent I/O Service Operation ............................................................
Flowchart of Extended Intelligent I/O Service Application Procedure .........................................
Interrupt Control Register (ICR) ........................................................................................................
v
42
44
45
47
48
50
51
52
6.7
6.8
6.9
6.10
Meanings of the Bits of Interrupt Control Register (ICR) ..................................................................
Extended Intelligent I/O Service Descriptor (ISD) .............................................................................
Registers of Extended Intelligent I/O Service Descriptor ..................................................................
Exception Processing .......................................................................................................................
CHAPTER 7
7.1
7.2
7.3
ADDRESSING ............................................................................................ 59
Effective Address Field ..................................................................................................................... 60
Direct Addressing ............................................................................................................................. 61
Indirect Addressing ........................................................................................................................... 63
CHAPTER 8
8.1
8.2
8.3
8.4
53
55
56
58
INSTRUCTION OVERVIEW ....................................................................... 67
Instruction Overview .........................................................................................................................
Symbols (Abbreviations) Used in Detailed Execution Instructions ...................................................
Effective Address Field .....................................................................................................................
Execution Cycles ..............................................................................................................................
CHAPTER 9
DETAILED EXECUTION INSTRUCTIONS ................................................ 77
9.1
Detailed Execution Instructions ........................................................................................................
9.1.1
ADD (Add Byte Data of Destination and Source to Destination) .................................................
9.1.2
ADDC (Add Byte Data of AL and AH with Carry to AL) ...............................................................
9.1.3
ADDC (Add Byte Data of Accumulator and Effective Address with Carry to Accumulator) .........
9.1.4
ADDCW (Add Word Data of Accumulator and Effective Address with Carry to Accumulator)
9.1.5
9.1.6
9.1.7
9.1.8
9.1.9
9.1.10
9.1.11
9.1.12
9.1.13
9.1.14
9.1.15
9.1.16
9.1.17
9.1.18
9.1.19
9.1.20
9.1.21
9.1.22
9.1.23
9.1.24
9.1.25
9.1.26
9.1.27
9.1.28
68
70
72
73
78
79
81
82
84
ADDDC (Add Decimal Data of AL and AH with Carry to AL) ...................................................... 86
ADDL (Add Long Word Data of Destination and Source to Destination) ..................................... 87
ADDSP (Add Word Data of Stack Pointer and Immediate Data to Stack Pointer) ...................... 89
ADDW (Add Word Data of AL and AH to AL) .............................................................................. 90
ADDW (Add Word Data of Destination and Source to Destination) ............................................ 91
AND (And Byte Data of Destination and Source to Destination) ................................................. 93
AND (And Byte Data of Immediate Data and Condition Code Register) ..................................... 95
ANDL (And Long Word Data of Destination and Source to Destination) ..................................... 97
ANDW (And Word Data of AH and AL to AL) .............................................................................. 99
ANDW (And Word Data of Destination and Source to Destination) .......................................... 100
ASR (Arithmetic Shift Byte Data of Accumulator to Right) ........................................................ 102
ASRL (Arithmetic Shift Long Word Data of Accumulator to Right) ............................................ 104
ASRW (Arithmetic Shift Word Data of Accumulator to Right) .................................................... 106
ASRW (Arithmetic Shift Word Data of Accumulator to Right) .................................................... 108
BBcc (Branch if Bit Condition satisfied) ..................................................................................... 110
Bcc (Branch relative if Condition satisfied) ................................................................................ 112
CALL (Call Subroutine) .............................................................................................................. 114
CALLP (Call Physical Address) ................................................................................................. 116
CALLV (Call Vectored Subroutine) ............................................................................................ 118
CBNE (Compare Byte Data and Branch if not equal) ................................................................ 120
CLRB (Clear Bit) ........................................................................................................................ 122
CMP (Compare Byte Data of Destination and Source) ............................................................. 123
CMPL (Compare Long Word Data of Destination and Source) ................................................. 125
CMPW (Compare Word Data of Destination and Source) ........................................................ 127
vi
9.1.29
9.1.30
9.1.31
9.1.32
9.1.33
9.1.34
9.1.35
9.1.36
9.1.37
9.1.38
9.1.39
9.1.40
9.1.41
9.1.42
9.1.43
9.1.44
9.1.45
9.1.46
9.1.47
9.1.48
9.1.49
9.1.50
9.1.51
9.1.52
9.1.53
9.1.54
9.1.55
9.1.56
9.1.57
9.1.58
9.1.59
9.1.60
9.1.61
9.1.62
9.1.63
9.1.64
9.1.65
9.1.66
9.1.67
9.1.68
9.1.69
9.1.70
9.1.71
9.1.72
9.1.73
9.1.74
9.1.75
CWBNE (Compare Word Data and Branch if not Equal) ..........................................................
DBNZ (Decrement Byte Data and Branch if not "0") .................................................................
DEC (Decrement Byte Data) .....................................................................................................
DECL (Decrement Long Word Data) .........................................................................................
DECW (Decrement Word Data) ................................................................................................
DIV (Divide Word Data by Byte Data) .......................................................................................
DIVW (Divide Long Word Data by Word Data) ..........................................................................
DIVU (Divide unsigned Word Data by unsigned Byte Data) ......................................................
DIVUW (Divide unsigned Long Word Data by unsigned Word Data) ........................................
DWBNZ (Decrement Word Data and Branch if not Zero) ..........................................................
EXT (Sign Extend from Byte Data to Word Data) ......................................................................
EXTW (Sign Extend from Word Data to Long Word Data) ........................................................
FILS (Fill String Byte) ................................................................................................................
FILSW (Fill String Word) ............................................................................................................
INC (Increment Byte Data (Address Specification)) ..................................................................
INCL (Increment Long Word Data) ............................................................................................
INCW (Increment Word Data) ...................................................................................................
INT (Software Interrupt) .............................................................................................................
INT (Software Interrupt (Vector Specification)) ..........................................................................
INT9 (Software Interrupt) ...........................................................................................................
INTP (Software Interrupt) ..........................................................................................................
JCTX (Jump Context) ................................................................................................................
JMP (Jump Destination Address) ..............................................................................................
JMPP (Jump Destination Physical Address) .............................................................................
LINK (Link and create new stack frame) ...................................................................................
LSL (Logical Shift Byte Data of Accumulator to Left) ................................................................
LSLL (Logical Shift Long Word Data of Accumulator to Left) ....................................................
LSLW (Logical Shift Word Data of Accumulator to Left) ............................................................
LSLW (Logical Shift Word Data of Accumulator to Left) ............................................................
LSR (Logical Shift Byte Data of Accumulator to Right) .............................................................
LSRL (Logical Shift Long Word Data of Accumulator to Right) .................................................
LSRW (Logical Shift Word Data of Accumulator to Right) .........................................................
LSRW (Logical Shift Word Data of Accumulator to Right) .........................................................
MOV (Move Byte Data from Source to Accumulator) ................................................................
MOV (Move Byte Data from Accumulator to Destination) .........................................................
MOV (Move Byte Immediate Data to Destination) .....................................................................
MOV (Move Byte Data from Source to Destination) ..................................................................
MOV (Move Byte Data from AH to Memory) .............................................................................
MOVB (Move Bit Data from Bit Address to Accumulator) .........................................................
MOVB (Move Bit Data from Accumulator to Bit Address) .........................................................
MOVEA (Move Effective Address to Destination) .....................................................................
MOVL (Move Long Word Data from Source to Accumulator) ...................................................
MOVL (Move Long Word Data from Accumulator to Destination) .............................................
MOVN (Move Immediate Nibble Data to Accumulator) .............................................................
MOVS (Move String Byte) .........................................................................................................
MOVSW (Move String Word) ....................................................................................................
MOVW (Move Word Data from Source to Accumulator) ...........................................................
vii
129
131
133
134
135
137
139
141
143
145
147
148
149
151
153
154
155
157
159
161
163
165
167
168
169
170
171
172
173
174
176
178
179
181
183
184
186
188
189
191
193
194
195
196
197
199
201
9.1.76
9.1.77
9.1.78
9.1.79
9.1.80
9.1.81
9.1.82
9.1.83
9.1.84
9.1.85
9.1.86
9.1.87
9.1.88
9.1.89
9.1.90
9.1.91
9.1.92
9.1.93
9.1.94
9.1.95
9.1.96
9.1.97
9.1.98
9.1.99
9.1.100
9.1.101
9.1.102
9.1.103
9.1.104
9.1.105
9.1.106
9.1.107
9.1.108
9.1.109
9.1.110
9.1.111
9.1.112
9.1.113
9.1.114
9.1.115
9.1.116
9.1.117
9.1.118
9.1.119
9.1.120
MOVW (Move Word Data from Accumulator to Destination) ..................................................... 203
MOVW (Move Immediate Word Data to Destination) ................................................................ 205
MOVW (Move Word Data from Source to Destination) ............................................................. 207
MOVW (Move Immediate Word Data to io) ............................................................................... 209
MOVW (Move Word Data from AH to Memory) ........................................................................ 210
MOVX (Move Byte Data with Sign Extension from Source to Accumulator) ............................. 211
MUL (Multiply Byte Data of Accumulator) .................................................................................. 213
MUL (Multiply Byte Data of Accumulator and Effective Address) .............................................. 214
MULW (Multiply Word Data of Accumulator) ............................................................................. 215
MULW (Multiply Word Data of Accumulator and Effective Address) ......................................... 216
MULU (Multiply Unsigned Byte Data of Accumulator) ............................................................... 217
MULU (Multiply Unsigned Byte Data of Accumulator and Effective Address) ........................... 218
MULUW (Multiply Unsigned Word Data of Accumulator) .......................................................... 219
MULUW (Multiply Unsigned Word Data of Accumulator and Effective Address) ...................... 220
NEG (Negate Byte Data of Destination) .................................................................................... 221
NEGW (Negate Word Data of Destination) ............................................................................... 222
NOP (No Operation) .................................................................................................................. 223
NOT (Not Byte Data of Destination) .......................................................................................... 224
NOTW (Not Word Data of Destination) ..................................................................................... 226
NRML (NORMALIZE Long Word) ............................................................................................. 227
OR (Or Byte Data of Destination and Source to Destination) .................................................... 228
OR (Or Byte Data of Immediate Data and Condition Code Register to Condition Code Register)
230
ORL (Or Long Word Data of Destination and Source to Destination) ....................................... 232
ORW (Or Word Data of AH and AL to AL) ................................................................................ 234
ORW (Or Word Data of Destination and Source to Destination) ............................................... 235
POPW (Pop Word Data of Accumulator from Stack Memory) ................................................... 237
POPW (Pop Word Data of AH from Stack Memory) ................................................................. 239
POPW (Pop Word Data of Program Status from Stack Memory) .............................................. 240
POPW (Pop Registers from Stack Memory) ............................................................................. 242
PUSHW (Push Word Data of Inherent Register to Stack Memory) ........................................... 244
PUSHW (Push Registers to Stack Memory) ............................................................................. 246
RET (Return from Subroutine) ................................................................................................... 248
RETI (Return from Interrupt) ...................................................................................................... 249
RETP (Return from Physical Address) ...................................................................................... 251
ROLC (Rotate Byte Data of Accumulator with Carry to Left) ..................................................... 253
RORC (Rotate Byte Data of Accumulator with Carry to Right) .................................................. 255
SBBS (Set Bit and Branch if Bit Set) ......................................................................................... 257
SCEQ (Scan String Byte Until Equal) ........................................................................................ 259
SCWEQ (Scan String Word Until Equal) ................................................................................... 261
SETB (Set Bit) ........................................................................................................................... 263
SUB (Subtract Byte Data of Source from Destination to Destination) ....................................... 264
SUBC (Subtract Byte Data of AL from AH with Carry to AL) ..................................................... 266
SUBC (Subtract Byte Data of Effective Address from Accumulator with Carry to Accumulator)
267
SUBCW (Subtract Word Data of Effective Address from Accumulator with Carry to Accumulator)
269
SUBDC (Subtract Decimal Data of AL from AH with Carry to AL) ............................................. 271
viii
9.1.121
9.1.122
9.1.123
9.1.124
9.1.125
9.1.126
9.1.127
9.1.128
9.1.129
9.1.130
9.1.131
9.1.132
9.1.133
9.1.134
9.1.135
SUBL (Subtract Long Word Data of Source from Destination to Destination) ...........................
SUBW (Subtract Word Data of Source from Destination to Destination) ..................................
SUBW (Subtract Word Data of AL from AH to AL) ....................................................................
SWAP (Swap Byte Data of Accumulator) ..................................................................................
SWAPW (Swap Word Data of Accumulator) .............................................................................
UNLINK (Unlink and Create New Stack Frame) ........................................................................
WBTc (Wait until Bit Condition Satisfied) ..................................................................................
XCH (Exchange Byte Data of Source to Destination) ...............................................................
XCHW (Exchange Word Data of Source to Destination) ...........................................................
XOR (Exclusive Or Byte Data of Destination and Source to Destination) .................................
XORL (Exclusive Or Long Word Data of Destination and Source to Destination) .....................
XORW (Exclusive Or Word Data of AH and AL to AL) ..............................................................
XORW (Exclusive Or Word Data of Destination and Source to Destination) ............................
ZEXT (Zero Extend from Byte Data to Word Data) ...................................................................
ZEXTW (Zero Extend from Word Data to Long Word Data) .....................................................
272
274
276
277
278
279
280
282
284
286
288
290
291
293
294
APPENDIX ......................................................................................................................... 295
APPENDIX A Explanation of Instruction Lists ............................................................................................
A.1 Items Used in Instruction Lists .......................................................................................................
A.2 Symbols Used in Instruction Lists ..................................................................................................
A.3 Effective Address Field ..................................................................................................................
A.4 Calculating the Number of Execution Cycles .................................................................................
APPENDIX B F2MC-16LX Instruction Lists (351 Instructions) ...................................................................
B.1 Transfer Instructions ......................................................................................................................
B.2 Numeric Data Operation Instructions .............................................................................................
B.3 Logical Data Operation Instruction .................................................................................................
B.4 Shift Instruction ..............................................................................................................................
B.5 Branch Instructions ........................................................................................................................
B.6 Other Instructions ...........................................................................................................................
APPENDIX C F2MC-16LX Instruction Maps ...............................................................................................
C.1 Structure of the Instruction Map .....................................................................................................
C.2 Basic Page Map .............................................................................................................................
C.3 Bit Operation Instruction Map .........................................................................................................
C.4 Character String Operation Instruction Map ...................................................................................
C.5 2-byte Instruction Map ....................................................................................................................
C.6 ea-type Instruction Map ..................................................................................................................
C.7 MOVEA RWi, ea Instruction Map ...................................................................................................
C.8 MOV Ri, ea Instruction Map ...........................................................................................................
C.9 MOVW RWi, ea Instruction Map ....................................................................................................
C.10 MOV ea, Ri Instruction Map ...........................................................................................................
C.11 MOVW ea, RWi Instruction Map ....................................................................................................
C.12 XCH Ri, ea Instruction Map ............................................................................................................
C.13 XCHW RWi, ea Instruction Map .....................................................................................................
296
297
299
301
302
304
305
307
311
313
314
316
319
320
322
324
326
328
330
340
342
344
346
348
350
352
INDEX................................................................................................................................... 355
ix
x
Main changes in this edition
Page
Changes (For details, refer to main body.)
188
CHAPTER 9
DETAILED EXECUTION INSTRUCTIONS
9.1.66 MOV
(Move Byte Data from AH to Memory)
"● Assembler format:" is changed.
(MOV @AL,AH / MOV @A,T → MOV @AL,AH)
210
CHAPTER 9
DETAILED EXECUTION INSTRUCTIONS
9.1.80 MOVW
(Move Word Data from AH to Memory)
"● Assembler format:" is changed.
(MOVW @AL,AH / MOV @A,T → MOVW @AL,AH)
278
CHAPTER 9
DETAILED EXECUTION INSTRUCTIONS
9.1.125 SWAPW
(Swap Word Data of Accumulator)
"● Assembler format:" is changed.
(SWAPW /XCHW A,T → SWAPW)
305
B.1 Transfer Instructions
"Table B-1 Transfer Instruction (Byte): 41 Instructions" is
changed.
(MOV @AL,AH / MOV @A,T → MOV @AL,AH)
306
315
"Table B-2 Transfer Instruction (Word/Long-word):
38 Instructions" is changed.
(MOVW @AL,AH / MOVW @A,T → MOVW @AL,AH)
B.5 Branch Instructions
CBNE Instruction in "Table B-14 Branch 2: 19 Instructions" is
changed.
(CBNE
CBNE
→
CBNE
CBNE
ear,#imm8,rel
ear,#imm8,rel
byte(A) not equal to imm8
byte(A) not equal to imm8
ear,#imm8,rel
eam,#imm8,rel
byte(ear) not equal to imm8
byte(eam) not equal to imm8)
CWBNE Instruction in "Table B-14 Branch 2: 19 Instructions" is
changed.
(CWBNE ear,#imm16,rel
CWBNE ear,#imm16,rel
→
CWBNE ear,#imm16,rel
CWBNE eam,#imm16,rel)
xi
Page
316
Changes (For details, refer to main body.)
B.6 Other Instructions
"Table B-15 Other Control Systems (Byte/Word/Long-word):
28 Instructions" is changed.
(+&→ *5)
"Table B-15 Other Control Systems (Byte/Word/Long-word):
28 Instructions" is changed.
(*5: (number of POP operations), or (number of PUSH operations))
317
"Table B-17 Accumulator Operation Instruction (Byte/Word):
6 Instructions" is changed.
(SWAPW / XCHW A,T → SWAPW)
318
"Table B-18 String Instruction : 10 Instructions" is changed.
(+& → *5), ( +) → *8)
The vertical lines marked in the left side of the page show the changes.
xii
CHAPTER 1
OVERVIEW OF
THE
2
F MC-16LX
CPU CORE
AND SAMPLE
CONFIGURATION
INCLUDING IT
This chapter briefly describes the configuration of the
F2MC-16LX CPU core, and presents a sample
configuration of a device incorporating it.
1.1 Overview of the F2MC-16LX CPU Core
1.2 Sample Configuration of an F2MC-16LX Device
1
CHAPTER 1 OVERVIEW OF THE F2MC-16LX CPU CORE AND SAMPLE CONFIGURATION INCLUDING IT
1.1
Overview of the F2MC-16LX CPU Core
The F2MC-16LX CPU core is an advanced 16-bit CPU designed for use in various types
of industrial equipment, office automation equipment, on-vehicle equipment, and other
equipment required to operate at high speed in real-time mode.
■ Overview of the F2MC-16LX CPU Core
The F2MC-16LX CPU core is an advanced 16-bit CPU designed for use in various types of industrial
equipment, office automation equipment, on-vehicle equipment, and other equipment required to operate at
high speed in real-time mode. The design of the F2MC-16LX instruction set is optimized for use in
controllers. The instructions can perform various types of control at high speed and at high efficiency. The
F2MC-16LX is a suitable CPU for processing 16-bit data. Some of its instructions can be used also for 32bit data processing, because its CPU incorporates a 32-bit accumulator. The memory space of the F2MC16LX can be expanded up to 16 Mbytes. Each location in the memory space can be accessed using either a
linear pointer or a bank method. The instruction set is based on the F2MC-8 A-T architecture, but has been
enhanced by adding instructions that support high-level language, extending the addressing mode,
improving the multiplication and division instructions, and augmenting bit manipulation.
■ Features of the F2MC-16LX CPU Core
● Minimum instruction execution time: 62.5 ns (with internal clock at 16 MHz)
● Memory space: Up to 16 Mbytes, accessible using either a linear or bank mode
● Instruction set optimized for use in controllers
• Cornucopia of data types: Bit, byte, word, and long word
• Extended addressing mode: 23 types
• High code efficiency
• Reinforcement of high-precision calculation (32-bit length) by means of a 32-bit accumulator
● Powerful interrupt functions
Interrupt priority levels: 8 levels (programmable)
● CPU-independent automatic transfer function
● Extended intelligent I/O service: Up to 16 channels
● Instruction supporting high-level language (C language) and multitasking
• Use of a system stack pointer
• Various pointers
• High symmetry of the instruction set
• Barrel shift instruction
● Increased execution speed: Use of a 4-byte queue for waiting of instructions
2
CHAPTER 1 OVERVIEW OF THE F2MC-16LX CPU CORE AND SAMPLE CONFIGURATION INCLUDING IT
1.2
Sample Configuration of an F2MC-16LX Device
Figure 1.2-1 shows a sample configuration of an F2MC-16LX device.
■ Sample Configuration of an F2MC-16LX Device
Figure 1.2-1 F2MC-16LX Device Sample Configuration
User pin section
Pin section peripheral to the CPU
Direct page
register
Timer/counter
Stack pointer
Register bank
pointer
Serial port
Program
counter
Processor
status
register
Bank register
F²MC-16LX CPU
F²MC-16LX bus
Accumulator
A/D converter
RAM (data area)
ROM
(program area)
ALU
Interrupt
controller
Clock generator
3
CHAPTER 1 OVERVIEW OF THE F2MC-16LX CPU CORE AND SAMPLE CONFIGURATION INCLUDING IT
4
CHAPTER 2
MEMORY SPACE
This chapter describes memory spaces in the F2MC16LX CPU.
2.1 CPU Memory Space
2.2 Linear Addressing Mode
2.3 Bank Addressing Mode
2.4 Memory Space Divided into Banks and Value in Each Bank Register
2.5 Data Configuration of and Access to Multi-byte Data in Memory
5
CHAPTER 2 MEMORY SPACE
2.1
CPU Memory Space
All data, programs, and I/O areas managed in the F2MC-16LX CPU are allocated in its
16-Mbyte memory space. The CPU can access these resources using an address on
the 24-bit address bus (see Figure 2.1-1 ).
The F2MC-16LX addressing mode can be classified either as a linear or bank mode. The
linear mode specifies an entire 24-bit address using a instruction. The bank mode
specifies the upper 8 bits of each address using a bank register, and the remaining 16bit address using an instruction.
■ CPU Memory Space
Figure 2.1-1 Example of Relationship between the F2MC-16LX System and Memory Map
Program
⎧ FFFFFFH
⎨
⎩
Program area
⎧ 810000H
⎪
⎪
⎨
⎪
⎪
⎩ 800000
Data area
FF8000H
F2MC-16LX
CPU
Data
Interrupt
H
Peripheral
circuit
General-purpose
port
[Device]
6
⎧ 0000C0H
⎨
⎩
⎧ 0000B0H
⎨
⎩
000020H
⎧
⎨
⎩ 000000
H
Interrupt controller
Peripheral circuit
General-purpose port
CHAPTER 2 MEMORY SPACE
2.2
Linear Addressing Mode
The linear addressing mode of the F2MC-16LX specifies an entire 24-bit address using
an instruction.
The linear addressing mode can operate in two different ways. In the first way, an
operand of an instruction directly specifies an entire 24-bit address. In the second way,
the lower 24-bit of a 32-bit general-purpose register is referred as an address.
■ Linear Addressing Mode
The linear addressing mode of the F2MC-16LX specifies an entire 24-bit address using an instruction. The
address mode of the F2MC-16LX is determined according to the specification of the effective address or
instruction code (implied) of an instruction.
The linear addressing mode can operate in two different ways. In the first way, an operand of an
instruction directly specifies an entire 24-bit address. In the second way, the lower 24-bit of a 32-bit
general-purpose register is referred as an address (see Figure 2.2-1 ).
7
CHAPTER 2 MEMORY SPACE
Figure 2.2-1 Examples of Generating an Address in the Linear Addressing Mode
Example 1: 24-bit Operand Specification in the Linear Addressing Mode
JMPP 123456H
Previous content of
program counter plus
program bank
17452DH
17
Latest content of
program counter plus 12
program bank
JMPP 123456H
452D
123456H
Next instruction
3456
Example 2: Indirect Addressing Based on 32-bit Register in the Linear Addressing Mode
MOV A @RL1+7
Previous content
of the AL
XXXX
090700H
3A
+7
240906F9
RL1
(Upper 8 bits are ignored.)
Latest content
of the AL
8
003A
CHAPTER 2 MEMORY SPACE
2.3
Bank Addressing Mode
The bank addressing mode of the F2MC-16LX specifies the upper 8 bits of an address
using a bank register for use, and the remaining 16 bits using an instruction.
■ Bank Addressing Mode
In the bank addressing mode, the 16-Mbyte memory space is divided into 256 banks of 64-Kbyte, and the
corresponding bank to each space is specified by the following 4 bank registers.
● Program bank register (PCB)
A 64-Kbyte bank specified using the PCB register is called a program (PC) space. It is used to hold mainly
instruction codes, vector tables, and immediate data.
● Data bank register (DTB)
A 64-Kbyte bank specified using the DTB register is called a data (DT) space. It is used to hold mainly
readable/writable data and control/data registers for internal and external resources.
● User stack bank register (USB) and system stack bank register (SSB)
A 64-Kbyte bank specified using the USB or SSB register is called a stack (SP) space. It is accessed when
the execution of a push or pop instruction or interrupt handling is performed and which to be used, the USB
or SSB register, is determined according to the S flag in the condition code register to save register contents
and a stack access occurs.
● Additional data bank register (ADB)
A 64-Kbyte bank specified using the ADB register is called an additional (AD) space. It is used to hold
mainly data overflowing from the DT space.
Each instruction is assigned with one of the default spaces by each addressing listed in Table 2.3-1 to
improve instruction code efficiency.
Table 2.3-1 Default Spaces
Default space
Addressing
Program space
PC-indirect, program access, branch type
Data space
@A, addr16, dir, or addressing using @RW0, @RW1, @RW4, or @RW5
Stack space
Addressing using PUSHW, POPW, @RW3, @RW7, or @SP
Additional space
Addressing using @RW2 or @RW6
9
CHAPTER 2 MEMORY SPACE
If a space other than a default space is used, an arbitrary bank space corresponding to a prefix code can be
accessed by specifying the prefix code before the instruction.
Table 2.3-2 lists bank select prefixes and the memory space selected using each prefix.
Table 2.3-2 Bank Selection Prefix
Bank select prefix
Selected space
PCB
Program space
DTB
Data space
ADB
Additional space
SPB
System or user stack space depending on the contents of the selected
stack flag
The DTB, USB, SSB, and ADB registers are initialized to "00H" at a reset. The PCB register is initialized
to "FFH" at a reset. After a reset, the data, stack, and additional spaces are allocated in bank 00H (000000H
to 00FFFFH), and the program space is allocated in bank FFH (FF0000H to FFFFFFH).
10
CHAPTER 2 MEMORY SPACE
2.4
Memory Space Divided into Banks and Value in Each Bank
Register
Figure 2.4-1 shows an example of a memory space divided into banks and a value in
each register bank.
■ Memory Space Divided into Banks and Values in Each Register Bank
Figure 2.4-1 Example of the Physical Addresses of Each Space
FFFFFFH
Program space
FF0000H
FFH
: PCB (program bank register)
B3H
: ADB (additional data bank register)
B3FFFFH
Additional space
Physical Address
B30000H
92FFFFH
User stack space
920000H
92H
: USB (user stack bank register)
68H
: DTB (data bank register)
4BH
: SSB (system stack bank register)
68FFFFH
Data space
680000H
4BFFFFH
System stack space
4B0000H
000000H
11
CHAPTER 2 MEMORY SPACE
2.5
Data Configuration of and Access to Multi-byte Data in
Memory
Multi-byte data is written to memory starting at the lowest address. If the multi-byte
data is 32-bit long, the lower 16 bits are written to memory first and then upper 16 bits.
■ Multi-byte Data Layout in a Memory Space
Multi-byte data is written to memory starting at the lowest address. If the multi-byte data is 32-bit length,
the lower 16 bits are written to memory first and then upper 16 bits.
If a reset signal is input immediately after the low-order data is written to memory, the high-order data may
not be written. To keep the data in integrity, it is necessary to input a reset signal after the high-order data
is written.
Figure 2.5-1 shows the layout of multi-byte data in memory. The lower 8 bits are placed at address n, the
next lower 8 bits are placed at address n + 1, and the next lower 8 bits are placed at address n + 2, and so
on.
Figure 2.5-1 Multi-byte Data Layout in Memory
MSB
01010101
H
01010101
11001100
11111111
Address n
L
12
00010100
LSB
11001100
11111111
00010100
CHAPTER 2 MEMORY SPACE
■ Access to Multi-byte Data
When multi-byte data is accessed, it is assumed that all parts of the multi-byte data are within a single bank.
To put it another way, an instruction accessing multi-byte data assumes that an address that follows address
FFFFH is 0000H in the same bank as for FFFFH.
Figure 2.5-2 shows an execution example of an instruction accessing multi-byte data.
Figure 2.5-2 Execution Example of an Instruction (MOVPW A, 080FFFFH) Accessing Multi-byte Data
Higher address
80FFFFH
AL before execution
??
??
AL after execution
23H 01H
01H
·
·
·
800000H
23H
Lower address
13
CHAPTER 2 MEMORY SPACE
14
CHAPTER 3
DEDICATED REGISTERS
The registers of the F2MC-16LX can be grouped into two
major categories: dedicated registers in the CPU and
general-purpose registers allocated in memory.
This chapter describes the F2MC-16LX dedicated
registers. These registers are the dedicated hardware in
the CPU. Their use is limited due to the architecture of
the CPU.
3.1 F2MC-16LX Dedicated Register Types
3.2 Accumulator (A)
3.3 User Stack Pointer (USP) and System Stack Pointer (SSP)
3.4 Processor Status (PS)
3.5 Program Counter (PC)
3.6 Direct Page Register (DPR)
3.7 Bank Registers
15
CHAPTER 3 DEDICATED REGISTERS
3.1
F2MC-16LX Dedicated Register Types
There are 11 dedicated registers in the F2MC-16LX.
• Accumulator (A=AH:AL)
• User stack pointer (USP)
• System stack pointer (SSP)
• Processor status (PS)
• Program counter (PC)
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional data bank register (ADB)
• Direct page register (DPR)
■ F2MC-16LX Dedicated Register Types
● Accumulator (A=AH:AL)
This is a set of two 16-bit accumulators. It can be used as a single 32-bit accumulator.
● User stack pointer (USP)
This is a 16-bit pointer indicating a user stack area.
● System stack pointer (SSP)
This is a 16-bit pointer indicating a system stack area.
● Processor status (PS)
This is a 16-bit register indicating the status of the system.
● Program counter (PC)
This is a 16-bit register to hold an address where the next instruction to be executed is stored.
● Program bank register (PCB)
This is an 8-bit register indicating the program space.
● Data bank register (DTB)
This is an 8-bit register indicating the data space.
● User stack bank register (USB)
This is an 8-bit register indicating the user stack space.
● System stack bank register (SSB)
This is an 8-bit register indicating the system stack space.
16
CHAPTER 3 DEDICATED REGISTERS
● Additional data bank register (ADB)
This is an 8-bit register indicating the additional space.
● Direct page register (DPR)
This is an 8-bit register indicating the direct page.
Figure 3.1-1 shows an image of the dedicated registers.
Figure 3.1-1 Dedicated Registers
AL
AH
Accumulator
USP
SSP
PS
PC
DPR
PCB
DTB
USB
SSB
ADB
8 bits
16 bits
User stack pointer
System stack pointer
Processor status
Program counter
Direct page register
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
32 bits
17
CHAPTER 3 DEDICATED REGISTERS
3.2
Accumulator (A)
The accumulator (A) consists of two 16-bit length operation registers (AH and AL), is
used for temporary storage of the results for an operation or of data to be transferred.
■ Accumulator (A)
The accumulator (A) consists of two 16-bit length operation registers (AH and AL), used for temporary
storage of the results for an operation or of data to be transferred. To process 32-bit data, the AH and AL
registers are concatenated (see Figure 3.2-1 ). To process 16-bit data (used in word-unit processing) or 8bit data (used in byte-unit processing), only the AL register is used (see Figure 3.2-2 ). Various types of
arithmetic and logical operations can be performed between data in the accumulator (A) and data in
memory or a register (such as Ri, RWi, or RLi). Similarly to the F2MC-8, the F2MC-16LX automatically
transfers data from the AL register to the AH register, if it receives new data at the AL register and the new
data is not larger than a word (data preservation function). Use of this data preservation function and a
function to perform arithmetic and logical operations between the AL and AH registers makes various
types of processing more efficient (see Figure 3.2-2 ).
If data transferred to the AL register is not larger than a byte, the data is sign- or zero-extended to 16 bits
and it is stored in the AL register. The data in the AL register can be handled as either a word or a byte. If
a byte-unit arithmetic operation is performed on the AL register, the upper 8 bits of data that have been
previously set in the AL register are ignored and reset to all "0"s.
Figure 3.2-1 Example of Transferring 32-bit Data
MOVL A, @RW1+6
MSB
Previous content
of the A register
XXXXH
XXXXH
DTB
A6H
LSB
A61540H
8FH
74H
A6153EH
2BH
52H
RW1
15H
38H
+6
Latest content
of the A register
18
8F74H
2B52H
AH
AL
CHAPTER 3 DEDICATED REGISTERS
Figure 3.2-2 Example of Transferring Data between the AL and AH Registers by Means of the Data
Preservation Function
MOVW A, @RW1+6
MSB
Previous content
of the A register
XXXXH
1234H
DTB
LSB
A61540H
8FH
74H
A6153EH
2BH
52H
RW1
15H
38H
A6H
+6
Latest content
of the A register
1234H
2B52H
AH
AL
19
CHAPTER 3 DEDICATED REGISTERS
3.3
User Stack Pointer (USP) and System Stack Pointer (SSP)
Both the user stack pointer (USP) and system stack pointer (SSP) are 16-bit registers.
They are used to indicate a data save address or return address when a push, pop
instruction, or subroutine is executed.
Basically, a value to be set in a stack pointer must be an even address.
■ User Stack Pointer (USP) and System Stack Pointer (SSP)
Both the user stack pointer (USP) and system stack pointer (SSP) are a 16-bit register. They are used to
indicate a data save address or return address when a push, pop instruction, or subroutine is executed. The
USP and SSP registers are used by stack manipulation instructions in the same manner. If the S flag in the
condition code register (CCR) in the processor status (PS) register is "0", the USP register is active. If the
S flag is "1", the SSP register is active (see Figure 3.3-1 ). Because the S flag becomes "1" when an
interrupt is accepted, the SSP register is used to indicate a memory area to save register contents at an
interrupt. The SSP register is used by an interrupt routine for stack manipulation, while the USP register is
used by non-interrupt handling routines for stack manipulation. If it is unnecessary to divide the stack
space, only the SSP register should be used.
For the SSP register, the upper 8 bits of an address used for stack manipulation are indicated by the system
stack bank register (SSB). For the USP register, they are indicated by the user stack bank register (USB).
20
CHAPTER 3 DEDICATED REGISTERS
Figure 3.3-1 Relationships between Stack Manipulation Instruction and Stack Pointer
Example 1: PUSHW A executed when the S flag is "0"
MSB
AL A624H
S flag
After execution ➪
0
AL A624H
S flag
0
USB C6H
USP F328H
SSB 56H
SSP 1234H
USB C6H
USP F326H
SSB 56H
SSP 1234H
C6F326H
➪
Before execution ➪
LSB
XX
XX
The user stack is used
because the S flag is "0".
C6F326H A6H
24H
561232H
XX
XX
561232H
A6H
24H
Example 2: PUSHW A executed when the S flag is "1"
AL A624H
USB C6H
USP F328H
SSB 56H
SSP 1234H
AL A624H
USB C6H
USP F328H
S flag 1
SSB 56H
SSP 1232H
S flag
After execution ➪
1
➪
Before execution ➪
The system stack is used
because the S flag is "1".
21
CHAPTER 3 DEDICATED REGISTERS
3.4
Processor Status (PS)
The processor status (PS) register consists of bits for controlling the CPU and those for
indicating the status of the CPU. The PS register is divided into the following three
registers.
• Interrupt level mask register (ILM)
• Register bank pointer (RP)
• Condition code register (CCR)
■ Processor Status (PS)
The processor status (PS) register consists of bits for controlling the CPU and those for indicating the status
of the CPU.
• Interrupt level mask register (ILM): Indicates the level of an interrupt to be accepted.
• Register bank pointer (RP): Indicates the start address of a register bank.
• Condition code register (CCR): Consists of various flags that are set or reset during instruction
execution or at an interrupt occurrence.
Figure 3.4-1 shows the structure of the processor status (PS) register.
Figure 3.4-1 Processor Status (PS) Register Structure
bit
PS
22
13 12
15
ILM
87
RP
0
CCR
CHAPTER 3 DEDICATED REGISTERS
3.4.1
Interrupt Level Mask Register (ILM)
The following shows a configuration diagram of the interrupt level mask register (ILM).
ILM
ILM2
ILM1
ILM0
(Initial value)→
0
0
0
■ Interrupt Level Mask Register (ILM)
The interrupt level mask register (ILM) consists of 3 bits. It indicates the levels of interrupts acceptable to
the CPU. If an interrupt request whose level is higher than the level indicated using these 3 bits, the
interrupt is generated. Interrupt level 0 is the highest, and interrupt level 7 is the lowest (see Table 3.4-1 ).
In other words, for an interrupt to be accepted, its interrupt level value must be smaller than the value held
in the ILM register. When an interrupt is accepted, its interrupt level is set in the ILM register, thus
prohibiting interrupts on lower levels from being accepted. Because the ILM register is initialized to all
"0"s at a reset, the highest interrupt level is specified in the ILM register. It is possible to transfer 8-bit
immediate data to the ILM register, but only the lower 3 bits of the data can be used.
Table 3.4-1 Interrupt Levels Indicated in the Interrupt Level Mask Register (ILM)
ILM2
ILM1
ILM0
Level value
Levels of acceptable interrupts
0
0
0
0
Interrupt disabled
0
0
1
1
0
0
1
0
2
1 and below
0
1
1
3
2 and below
1
0
0
4
3 and below
1
0
1
5
4 and below
1
1
0
6
5 and below
1
1
1
7
6 and below
23
CHAPTER 3 DEDICATED REGISTERS
3.4.2
Register Bank Pointer (RP)
The following shows a configuration diagram of the register bank pointer (RP).
RP
B4
B3
B2
B1
B0
(Initial value)→
0
0
0
0
0
■ Register Bank Pointer (RP)
The register bank pointer (RP) indicates the address of an internal RAM area where the general-purpose
registers of the F2MC-16LX are. The start memory address of a register bank currently in use is
represented using the following conversion expression: [000180H + RP × 10H]. The RP register consists
of 5 bits. It can hold any value between "00H" and "1FH". So the start memory address of the register bank
can be set in the range between 000180H and 00037FH. Therefore, the register bank can be allocated at
memory locations in the range between 000180H and 00037FH. If the internal RAM area used as an
external area, however, it cannot be used as general-purpose registers even if the register bank is within that
range. It is possible to transfer 8-bit immediate data to the RP register, but only the lower 5 bits of the data
can be used.
24
CHAPTER 3 DEDICATED REGISTERS
3.4.3
Condition Code Register (CCR)
The following shows a configuration diagram of the condition code register (CCR).
bit
CCR
(Initial value)→
7
6
5
4
3
2
1
0
–
I
S
T
N
Z
V
C
0
1
–
–
–
–
–
-: Undefined
■ Condition Code Register (CCR)
• I (Interrupt enable flag): If the I flag is "1", all non-software interrupts are acceptable. If the flag is "0",
they are disabled. The flag is cleared by a reset.
• S (Stack flag): If the S flag is "0", the user stack pointer (USP) is active as a pointer for stack
manipulation. If the flag is "1", the system stack pointer (SSP) is active. The flag is set
at a reset and when an interrupt is accepted.
• T (Sticky bit flag): If at least one bit read from the C flag is "1" when a logical shift right instruction or
an arithmetic shift right instruction is executed, this flag becomes "1". Otherwise,
the flag becomes "0". The flag becomes "0" also if the amount of shifting is "0".
• N (Negative flag): If the most significant bit of an arithmetic or logical operation result is "1", this flag
is set. If it is "0", this flag is cleared.
• Z (Zero flag): If the result of an arithmetic or logical operation is all "0"s, this flag is set. Otherwise, it
is cleared.
• V (Overflow flag): This flag is set if a digit overflow occurs in a signed value generated as the result of
an arithmetic or logical operation. Otherwise, the flag is cleared.
• C (Carry flag): This flag is set if an arithmetic or logical operation causes a carry from or a borrow to
the most-significant bit. Otherwise, the flag is cleared.
25
CHAPTER 3 DEDICATED REGISTERS
3.5
Program Counter (PC)
The program counter (PC) consists of 16 bits. It indicates the upper 16 bits of a
memory address where the next instruction to be executed by the CPU.
■ Program Counter (PC)
The program counter (PC) consists of 16 bits. It indicates the lower 16 bits of a memory address where the
next instruction to be executed by the CPU is (see Figure 3.5-1 ). The upper 8 bits of the memory address
are indicated in the program bank register (PCB). The content of the PC register is updated, when a
conditional branch or subroutine call instruction is executed, upon an interrupt occurrence, or at a reset.
The PC register is used also as a base pointer for reading an operand.
Figure 3.5-1 Program Counter (PC)
PCB
FEH
PC
ABCDH
FEABCDH
26
Next instruction
to be executed
CHAPTER 3 DEDICATED REGISTERS
3.6
Direct Page Register (DPR)
The direct page register (DPR) specifies bits 8 to 15 (addr8 to addr15) of an operand
address for an instruction in direct addressing mode.
■ Direct Page Register (DPR)
The direct page register (DPR) specifies bits 8 to 15 (addr8 to addr15) of an operand address for an
instruction in direct addressing mode, as shown in Figure 3.6-1 . The DPR register is 8 bits long. It is
initialized to "01H" at a reset. It can be read- and write-accessed by an instruction.
Figure 3.6-1 Physical Address Specified in Direct Addressing Mode
DTB register
DPR register
Direct address in an instruction
ββββββββ
αααααααα
MSB
24-bit
physical address
γγγγγγγγ
LSB
ααααααααββββββββγγγγγγγγ
27
CHAPTER 3 DEDICATED REGISTERS
3.7
Bank Registers
The following 5 bank registers are available in the F2MC-16LX.
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional data bank register (ADB)
These registers indicate memory banks allocated for the program, data, user stack,
system stack, and additional spaces, respectively.
■ Bank Registers
All of these bank registers are 1 byte length. At a reset, the PCB register is initialized to "0FFH", and the
other registers, to "00H". The PCB register can be read-accessed, but not write-accessed. The other bank
registers can be both read- and write-accessed. The content of the PCB register is updated, when a JMPP,
CALLP, RETP, or RETI instruction for a branch anywhere in the 16-Mbyte space is executed or an
interrupt occurs. See "CHAPTER 2 MEMORY SPACE" for descriptions about the operation of each
register.
28
CHAPTER 4
GENERAL-PURPOSE
REGISTERS
The registers of the F2MC-16LX can be grouped into two
major categories: dedicated registers in the CPU and
general-purpose registers allocated in memory.
This chapter describes the F2MC-16LX general-purpose
registers. These registers are allocated in a RAM in
address space of the CPU. Similarly to the dedicated
registers, the general-purpose registers can be
accessed without specifying their address. However,
the user can specify the purpose for which they are used
in the same manner as for ordinary memory.
4.1 Register Banks in RAM
4.2 Calling General-purpose Registers in RAM
29
CHAPTER 4 GENERAL-PURPOSE REGISTERS
4.1
Register Banks in RAM
Each register bank consists of 8 words (16 bytes). They can be used as generalpurpose registers (byte registers R0 to R7, word registers RW0 to RW7, and long word
registers RL0 to RL3) for performing various types of operations and specifying
pointers. RL0 to RL3 can be used also as a linear pointer to gain direct access to all
spaces in memory.
■ Register Banks in RAM
Table 4.1-1 lists the function of each register, and Table 4.1-2 shows relationships between the registers.
Table 4.1-1 Functions of Each Register
Register name
Function
Used to hold an operand in various types of instructions.
Note: R0 is also used as a barrel shift counter and a counter of normarize
instruction.
R0 to R7
RW0 to RW7
Used to hold a pointer.
Used to hold an operand in various types of instructions.
Note: RW0 is used also as a string instruction counter.
RL0 to RL3
Used to hold a long pointer.
Used to hold an operand in various types of instructions.
Table 4.1-2 Relationship between Registers
RW0
RL0
RW1
RW2
RL1
RW3
R0
RW4
R1
RL2
R2
RW5
R3
R4
RW6
R5
RL3
R6
RW7
R7
30
4.2
Calling General-purpose Registers in RAM
For general-purpose registers of the F2MC-16LX, the register bank pointer (RP) is used
to specify where in internal RAM between 000180H and 00037FH the register bank
currently in use is allocated.
■ Calling General-purpose Registers in RAM
The general-purpose registers of the F2MC-16LX are allocated in internal RAM between 000180H and
00037FH (in maximum configuration). The register bank pointer (RP) is used to indicate where in internal
RAM between 000180H and 00037FH the register bank currently in use is allocated. Each bank contains
the following 3 different registers. These registers are not independent of one another. Instead, they have
the relationships shown in Figure 4.2-1 .
• R0 to R7:
8-bit general-purpose registers
• RW0 to RW7: 16-bit general-purpose registers
• RL0 to RL3: 32-bit general-purpose registers
Figure 4.2-1 General-purpose Registers
000180H + RP × 10H
Start address of a
general-purpose
register
16 bits
RW0
RW1
RW2
RW3
Lower order
Higher order
LSB
R1
R3
R5
R7
R0
R2
R4
R6
RW4
RW5
RW6
RW7
⎧
⎨
⎩
⎧
⎨
⎩
⎧
⎨
⎩
⎧
⎨
⎩
MSB
RL0
RL1
RL2
RL3
The relationships among the high- and low-order bytes in word registers (RW4 to RW7) and byte registers
(R0 to R7) are represented using the following expression:
RW (i + 4) = R (i × 2 + 1) × 256 + R (i × 2) [where i = 0 to 3]
The relationships among the high- and low-order bytes in long registers (RL0 to RL3) and word registers
(RW0 to RW7) are represented using the following expression:
RL (i) = RW (i × 2 + 1) × 65536 + RW (i × 2) [where i = 0 to 3]
For example, if the data in R1 and the data in R0 are arranged as high- and low-order bytes, respectively,
the resulting data equals the data (2 bytes) in RW4.
31
CHAPTER 4 GENERAL-PURPOSE REGISTERS
32
CHAPTER 5
PREFIX CODES
The operation of an instruction can be modified by
prefixing it with prefix code. The following 3 types of
prefix codes are available.
• Bank select prefix
• Common register bank prefix
• Flag change inhibit prefix code
This chapter describes these prefixes.
5.1 Bank Select Prefix
5.2 Common Register Bank Prefix (CMR)
5.3 Flag Change Inhibit Prefix Code (NCC)
5.4 Constraints Related to the Prefix Codes
33
CHAPTER 5 PREFIX CODES
5.1
Bank Select Prefix
Placing a bank select prefix before an instruction enables selecting the memory space
accessed by the instruction regardless of what the current addressing mode is.
■ Bank Select Prefix
The memory space of data to be accessed is determined according to the addressing mode. Placing a bank
select prefix before an instruction enables to select the memory space accessed by the instruction regardless
of what the current addressing mode is. Table 5.1-1 lists the bank select prefixes and the memory space
selected according to each bank select prefix.
Table 5.1-1 Bank Select Prefixes
Bank select prefix
Memory space to be selected
PCB
Program counter space
DTB
Data space
ADB
Additional space
SPB
System or user stack space depending on the state of the stack flag
Be careful when using the following instructions.
● Transfer instructions (I/O access)
MOV A,io
MOVW io,A
MOV io, A
MOV io,#imm8
MOVX A,io
MOVW A,io
MOVW io,#imm16
These instructions access the I/O space regardless of whether there is a prefix before them.
● Branch instruction
RETI
The system stack bank (SSB) is used regardless of whether there is a prefix before the branch instruction.
● Bit manipulation instructions (I/O access)
MOVB A,io:bp
MOVB io:bp,A
SETB io:bp
CLRB io:bp
BBC io:bp,rel
BBS io:bp,rel
WBTC
WBTS
The I/O space is accessed regardless of whether there is a prefix before those instructions.
34
CHAPTER 5 PREFIX CODES
● String manipulation instructions
MOVS
MOVSW
SCEQ
SCWEQ
FILS
FILSW
A bank register specified in the operand is used regardless of whether there is a prefix before these
instructions.
● Other types of control instructions (stack manipulation)
PUSHW
POPW
The system stack bank (SSB) or user stack bank (USB) is used depending on the state of the S flag,
regardless of whether there is a prefix before these instructions.
POPW
PS
In the following cases, the prefix of an instruction affects not only that instruction but also an instruction
that follows it.
● Other types of control instructions (flag change)
AND CCR,#imm8
OR CCR,#imm8
The operations of these instructions are performed normally. The prefix of each of these instructions
affects not only the instructions but also an instruction that follows them.
● Another type of control instruction (interrupt control)
MOV ILM,#imm8
The operation of the instruction is performed normally. The prefix of the instruction affects not only that
instruction but also an instruction that follows it.
35
CHAPTER 5 PREFIX CODES
5.2
Common Register Bank Prefix (CMR)
Placing a common register bank prefix (CMR) before an instruction accessing a register
bank enables to change that the instruction is to access only the registers in a common
bank (register bank selected when RP = 0) allocated between 000180H and 00018FH,
regardless of what the current value of the register bank pointer (RP) is.
■ Common Register Bank Prefix (CMR)
To make data exchange among tasks easier, it is necessary to use a method that can access a certain
specified register bank relatively easily no matter what value the RP register holds. To meet this
requirement, the F2MC-16LX has a register bank that can be used by all tasks in common. It is called a
common bank. The common bank is allocated in memory between address 000180H and 00018FH. It is
selected when the RP register contains a value of "0".
Placing the common register bank prefix (CMR) before an instruction accessing a register bank enables to
change that the instruction is to access only the registers in a common bank (register bank selected when
RP = 0) allocated between 000180H and 00018FH, regardless of what the current value of the register bank
pointer (RP) is.
Be careful when using the following instructions.
● String instructions
MOVS
NOVSW
SCEQ
FILS
FILSW
If an interrupt is requested during execution of a string manipulation instruction attached with a prefix
code, the prefix becomes ineffective for the string manipulation instruction after a return is made from the
interrupt handling routine, possibly resulting in a malfunction. Do not place the CMR prefix before these
string manipulation instructions.
● Other types of control instructions (flag change)
AND CCR,#imm8
OR CCR,#imm8
POPW PS
The operations of these instructions are performed normally. The prefix of each of these instructions
affects not only the instructions but also an instruction that follows them.
● MOV ILM,#imm8
The operation of the instruction is performed normally. The prefix of the instruction affects not only that
instruction but also an instruction that follows it.
36
CHAPTER 5 PREFIX CODES
5.3
Flag Change Inhibit Prefix Code (NCC)
Placing the flag change inhibit prefix code (NCC) before an instruction inhibits flags
from changing during execution of the instruction.
■ Flag Change Inhibit Prefix Code (NCC)
The flag change inhibit prefix code (NCC) is used to suppress undesired changes to flags. Placing the NCC
prefix before an instruction inhibits flags from changing during execution of the instruction.
Be careful when using the following instructions.
● Branch instructions
INT #vct8
INT9
INTP addr24
RETI
INT addr16
These instructions change the flags in the condition code register (CCR) regardless of whether there is a
prefix before them.
● String instructions
MOVE
MOVSW
SCEQ
SCWEQ
FILS
FISW
If an interrupt is requested during execution of a string manipulation instruction attached with a prefix
code, the prefix becomes ineffective for the string manipulation instruction after a return is made from the
interrupt handling routine, possibly resulting in a malfunction. Do not place the NCC prefix before these
string manipulation instructions.
● Another type of control instruction (task switching)
JCTX @A
This instruction changes the flags in the CCR register regardless of whether there is a prefix before it.
● Other types of control instructions (flag change)
AND CCR,#imm8
OR CCR,#imm8
POPW PS
These instructions change the flags in the CCR register regardless of whether there is a prefix before them.
The prefix of each of these instructions affects not only the instructions but also an instruction that follows
them.
● Another type of control instruction (interrupt control)
MOV ILM,#imm8
The operation of the instruction is performed normally. The prefix of the instruction affects not only that
instruction but also an instruction that follows it.
37
CHAPTER 5 PREFIX CODES
5.4
Constraints Related to the Prefix Codes
If a prefix code is placed before an instruction where interrupt and hold requests are
inhibited, the effect of the prefix code lasts until an instruction where neither an
interrupt nor hold request is inhibited appears for the first time, as shown in Figure 5.42.
If a prefix is followed by conflicting prefix codes, the last one is valid.
■ Relationships between Instructions Rejecting Interrupt Requests and Prefix Codes
The following 10 instructions/prefix codes reject interrupt and hold requests.
•
MOV ILM,#imm8
•
AND CCR,#imm8
•
OR CCR,#imm8
•
POPW PS
•
PCB
•
ADB
•
NCC
•
DTB
•
SPB
•
CMR
If an interrupt or hold request is issued during execution of any of the above instructions, the request is
accepted only after any instruction not listed above appears for the first time after that instruction and is
executed, as shown in Figure 5.4-1 .
Figure 5.4-1 Instructions Rejecting Interrupt and Hold Requests
Instructions rejecting interrupt and hold requests
••••••••
Interrupt request issued
(a)
•••
Interrupt accepted
(a):Ordinary instruction
If a prefix code is placed before an instruction rejecting interrupt and hold requests, its effect lasts until an
instruction other than instructions rejecting interrupt and hold requests appears for the first time after the
prefix code and is executed, as shown in Figure 5.4-2 .
Figure 5.4-2 Instructions Rejecting Interrupt and Hold Requests and Prefix Code
Instructions rejecting interrupt and hold requests
MOV A,FFH
NCC
CCR: XXX10XX
MOV ILM,#imm8
••••
ADD A,01H
CCR: XXX10XX
The NCC protects the
CCR from changing.
38
CHAPTER 5 PREFIX CODES
■ If Two or More Prefix Codes Appear in Succession
If a prefix is followed by conflicting prefix codes, the last one is valid (see Figure 5.4-3 ).
Figure 5.4-3 Consecutive Prefix Codes
Prefix codes
•••••
ADB
DTB
PCB
ADD A,01H
••••
The PCB prefix code is valid for this instruction.
The term "conflicting prefix codes" indicates PCB, ADB, DTB, and SPB in the above figure.
39
CHAPTER 5 PREFIX CODES
40
CHAPTER 6
INTERRUPT HANDLING
This chapter describes the interrupt function and
operation of F2MC-16LX.
6.1 Interrupt Handling
6.2 Hardware Interrupt Operation Flow
6.3 Interrupt Handling Flowchart and Saving the Contents of Registers
6.4 Interrupt Vectors
6.5 Extended Intelligent I/O Service
6.6 Interrupt Control Register (ICR)
6.7 Meanings of the Bits of Interrupt Control Register (ICR)
6.8 Extended Intelligent I/O Service Descriptor (ISD)
6.9 Registers of Extended Intelligent I/O Service Descriptor
6.10 Exception Processing
41
CHAPTER 6 INTERRUPT HANDLING
6.1
Interrupt Handling
In F2MC-16LX series, interrupt handling or extended intelligent I/O service is activated
by the interrupt request from an internal resource. For interrupt handling, the
processing appropriate to the interrupt request is performed by the interrupt handling
program. For extended intelligent I/O service, the data transfer between the requesting
internal resource and the memory is automatically performed. In addition, a function is
provided to stop the execution of the extended intelligent I/O service by the request
from the internal resource (such as built-in peripheral circuit).
■ Interrupt Handling
To permit an internal resource to make a hardware interrupt request to the F2MC-16LX CPU, an interrupt
request flag and an interrupt enable flag are required for that resource. The interrupt request flag is set by
the occurrence of an event specific to the internal resource. When the interrupt request flag indicates the
request being made and the interrupt enable flag is set to the enabled state, a hardware interrupt request is
issued from the internal resource.
In the case of the internal resource that requires the activation of the extended intelligent I/O service
accompanied by the occurrence of a hardware interrupt request, an extended intelligent I/O service enable
(ISE) flag is provided in the interrupt control register (ICR) in the interrupt controller associated with that
resource.
The occurrence of an interrupt request with the ISE flag set to "1" activates the extended intelligent I/O
service. If only normal hardware interrupt requests are intended, set the ISE flag to "0".
For interrupt requests by the execution of the INT instruction, which are software interrupts, no interrupt
request and enable flags are applied. Whenever the INT instruction is executed, an interrupt request occurs.
Any interrupt level of hardware interrupt request can be assigned to a given group regarding interrupt
request. Interrupt levels are specified by the interrupt level setting bits (IL0, IL1, and IL2) in the ICR
register in the interrupt controller. It is possible to specify eight interrupt level settings 0 to 7. Definition
of the interrupt levels is such that "0" is the highest and "6" is the lowest.
From a group set to interrupt level 7, no interrupt requests can be made. Hardware interrupt requests are
maskable (enabled/disabled) by the I flag in the condition code register (CCR) of the processor status (PS)
and the ILM register (ILM0, ILM1, and ILM2).
When an unmasked interrupt request occurs, the CPU takes the following actions:
42
CHAPTER 6 INTERRUPT HANDLING
(1) Saves the data (12 bytes) held by the following registers into the memory area indicated by the system
stack bank register (SSB) and the system stack pointer (SSP).
• Processor status (PS)
• Program counter (PC)
• Program bank register (PCB)
• Data bank register (DTB)
• Additional data bank register (ADB)
• Direct page register (DPR)
• Accumulator (A)
(2) Reads the interrupt vector in 3 bytes to PC and PCB.
(3) Updates the ILM register in the PS to the level setting value of the accepted interrupt request and sets
the S flag in the CCR register.
(4) Initiates the instruction execution, starting with the address indicated by the interrupt vector.
For the INT instruction, the ILM register is not updated and the I flag in the CCR register is cleared.
Subsequent interrupt requests are put to the pending state.
As a special case, hardware interrupt requests cannot be accepted during writing into an I/O area. This is
intended to avoid the CPU malfunction, which might otherwise be caused by the occurrence of an interrupt
request while the related data in the interrupt control registers for the resources are being rewritten.
43
CHAPTER 6 INTERRUPT HANDLING
6.2
Hardware Interrupt Operation Flow
Figure 6.2-1 shows the operation flow from the occurrence of a hardware interrupt
request until the interrupt request has been cleared and removed from within the
interrupt handling program.
■ Hardware Interrupt Operation Flow
Figure 6.2-1 From the Hardware Interrupt Occurrence to its Clearance
Register file
PS
Micro code
IR
F2MC-16 bus
ILM
I
Comparator
Check
(6)
(4)
(5)
F2MC-16LX CPU
PS : Processor status
I
: Interrupt enable flag
ILM : Interrupt level mask register
IR : Instruction register
(3)
AND
Source FF
(7)
(2)
(1)
Interrupt level IL
Enable FF
Level comparator
...
Peripheral
Interrupt
controller
Peripheral
(1) An interrupt source occurs within the peripheral.
(2) If the interrupt enable bit within the peripheral is referred and it indicates the interrupt enabled state, an
interrupt request is issued from the peripheral to the interrupt controller.
(3) The interrupt controller that has received that interrupt request determines the priority between the
requests made at the same time and transfers the interrupt level corresponding to the appropriate
interrupt to the CPU.
(4) The CPU compares the interrupt level requested by the interrupt controller with the IL bit held in the
processor status register.
(5) Only if the result of this comparison is that the interrupt level priority is higher than the current interrupt
handling level, the CPU checks the content of the I flag in the same processor status register.
(6) Only if the result of the check in (5) is that the I flag is set in the interrupt enabled state, the CPU sets
the content of the IL bit to the requested level. Upon the completion of the ongoing instruction
execution, the CPU passes the control to the interrupt handling routine to initiate the handling of that
interrupt.
(7) When the software within the user’s interrupt handling routine clears the occurred interrupt cause as
mentioned in (1), this interrupt request process is terminated.
44
CHAPTER 6 INTERRUPT HANDLING
6.3
Interrupt Handling Flowchart and Saving the Contents of
Registers
Figure 6.3-1 shows the interrupt handling flowchart and Figure 6.3-2 shows how the
contents of the registers are saved with interrupt handling.
■ Interrupt Handling Flowchart
Figure 6.3-1 Interrupt Handling Flowchart
I:
ILM:
I & IF & IE=1
AND
ILM > IL
YES
IF:
IE:
ISE:
IL:
S:
Flag in the CCR
Level register that holds a level value,
referenced by the CPU
Interrupt request by an internal resource
Interrupt enable flag for an internal resource
EI2OS enable flag
Interrupt request level of an internal resource
Flag in the CCR
NO
NO
YES
ISE=1
Fetch and decode next
instruction
Save the contents of PS, PC,
PCB, DTB, ADB, DPR, and A
into the SSP stack. Then, ILM=IL.
Perform extended intelligent
I/O service processing
YES
INT instruction
NO
Execute normal
instruction
NO
Stringprocessing
instruction repetition
completed
Save the contents of PS,
PC, PCB, DTB, ADB, DPR,
and A into the SSP stack.
Then, I = 0 and ILM = IL.
S←1
Fetch an interrupt vector
YES
Update PC
45
CHAPTER 6 INTERRUPT HANDLING
Figure 6.3-2 How the Contents of the Registers are Saved with Interrupt Handling
Word (16 bits)
MSB
LSB
H
← SSP (a value of SSP before the interrupt occurrence)
AH
AL
DPR
DTB
ADB
PCB
PC
PS
L
46
← SSP (a value of SSP after the interrupt occurrence)
CHAPTER 6 INTERRUPT HANDLING
6.4
Interrupt Vectors
Interrupt vectors are stored at addresses FFFC00H to FFFFFFH as shown in Table 6.4-1
Interrupt vectors share the same area for both hardware interrupt and software
interrupt.
■ Interrupt Vectors
Table 6.4-1 Interrupt Vectors
Interrupt
request
Vector address
L
Vector address
H
Vector address
bank
Mode register
INT0 *1
FFFFFCH
FFFFFDH
FFFFFEH
Not used
INT1 *1
FFFFF8H
FFFFF9H
FFFFFAH
Not used
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
INT7 *1
FFFFE0H
FFFFE1H
FFFFE2H
Not used
INT8 *2
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
INT9
FFFFD8H
FFFFD9H
FFFFDAH
Not used
INT10 *3
FFFFD4H
FFFFD5H
FFFFD6H
Not used
INT11
FFFFD0H
FFFFD1H
FFFFD2H
Not used
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
INT 254
FFFC04H
FFFC05H
FFFC06H
Not used
INT 254
FFFC00H
FFFC01H
FFFC02H
Not used
*1: Because the vector area for the CALLV instruction is also used as the vector area for INT #vct8 (#0 to #7) when the PCB is "FFH", care
should be taken in using a vector for the CALLV instruction.
*2: It becomes a reset vector.
*3: It becomes a vector for exception processing.
47
CHAPTER 6 INTERRUPT HANDLING
6.5
Extended Intelligent I/O Service
The extended intelligent I/O service (EI2OS) is a function for automatic data transfer
between I/O and the memory. It enables the data transfer from/to I/O on a direct memory
access (DMA) basis, though this was performed by the interrupt handling program
before.
■ Overview of Extended Intelligent I/O Service
The extended intelligent I/O service is one type of hardware interrupt. This service achieves automatic data
transfer between I/O and the memory, enabling the data transfer from/to I/O on a DMA basis, though this
was formerly performed by the interrupt handling program. As compared with the method applied before
as part of interrupt handling, the following advantages are added:
• Because the part of the program coded for data transfer is no longer needed, the program size is reduced.
•
It is unnecessary to save the contents of registers because the internal registers are not used for data
transfer, thus enhancing the transfer rate.
• Because the data transfer can be stopped according to the I/O status, unnecessary data transfer is
eliminated.
•
Buffer addresses can be selected without the need of increments and update.
•
I/O register addresses can be selected without the need of increments and update.
When the extended intelligent I/O service is terminated, it sets the end condition before the automatic
branch to the interrupt handling routine. This allows the user to know what the end condition was.
■ Structure of Extended Intelligent I/O Service
There are four functional entities below, which are related to the extended intelligent I/O service:
• Internal resource: Interrupt enable bit and interrupt request bit: Controls an interrupt request from a
resource.
• Interrupt controller: ICR: Assigns an interrupt level to each interrupt request, determines the priority
between the interrupts requested at the same time, and selects the operation
of EI2OS.
• CPU: I, ILM: Compares the requested interrupt level with the current level and verifies the interrupt
enabled state.
• RAM: Descriptor: Describes the transfer information of EI2OS.
Figure 6.5-1 shows the overview of extended intelligent I/O service.
48
CHAPTER 6 INTERRUPT HANDLING
Figure 6.5-1 Overview of Extended Intelligent I/O Service
Memory space
by IOA
Peripheral
I/O register
I/O register
CPU
Interrupt request
(3)
ISD
by ICS
(2)
(3)
(1)
Interrupt control
register
Interrupt controller
by BAP
(4)
Buffer
by DCT
(1) I/O requests data transfer.
(2) Interrupt controller selects the descriptor.
(3) Reads the transfer origin and destination from the descriptor.
(4) Data transfer between the I/O and the memory is performed.
Note:
Area that can be specified by the I/O address pointer (IOA) is 000000H to 00FFFFH.
Area that can be specified by the buffer address pointer (BAP) is 000000H to 00FFFFH.
The maximum transfer count that can be specified by the data counter (DCT) is 65536.
49
CHAPTER 6 INTERRUPT HANDLING
6.5.1
Flowchart of Extended Iintelligent I/O Service Operation
Figure 6.5-2 shows the flowchart of extended intelligent I/O service operation.
■ Flowchart of Extended Intelligent I/O Service Operation
Figure 6.5-2 Extended Intelligent I/O Service Operation Flowchart
Interrupt request issued
from an internal resource
NO
ISE = 1
YES
Interrupt sequence
Read ISD/ISCS
End request
from the
resource
BAP: Buffer address pointer
IOA:
IO address pointer
ISD:
EI2OS descriptor
ISCS: EI2OS status
DCT: Data counter
ISE:
EI2OS enable bit
S1, S0: EI2OS end status
YES
SE = 1
NO
YES
DIR = 1
NO
Data indicated by IOA
↓ (Data transfer)
Memory indicated by BAP
YES
IF = 0
NO
The updated value
depends on BW.
Update IOA
YES
BF = 0
NO
Data indicated by BAP
↓ (Data transfer)
Data indicated by IOA
The updated value
depends on BW.
(−1)
Decrement DCT
DCT = 00
Update BAP
YES
NO
Set S1 and S0 to "00"
50
Set S1 and S0 to "01"
Set S1 and S0 to "11"
Clear the interrupt
request from the
resource
Clearing ISE to "0"
CPU operation recovery
Interrupt sequence
CHAPTER 6 INTERRUPT HANDLING
6.5.2
Flowchart of Extended Intelligent I/O Service Application
Procedure
Figure 6.5-3 shows the flowchart of extended intelligent I/O service (EI2OS) application
procedure.
■ Flowchart of Extended Intelligent I/O Service Application Procedure
Figure 6.5-3 Flowchart of Extended Intelligent I/O Service Application Procedure
Processing by CPU
Processing by EI2OS
EI2OS initialization
(Interrupt request) AND (ISE = 1)
Job execution
Reinitializing EI2OS
(Channel switch)
Normal termination
state
Data transfer
Count-out OR
Interrupt occurs by the end
request from a resource.
Processing the data in
the buffer
51
CHAPTER 6 INTERRUPT HANDLING
6.6
Interrupt Control Register (ICR)
There are interrupt control registers (ICRs) in the interrupt controller. The number of
ICRs is equivalent to the number of all I/Os (internal resource I/Os) that have the
interrupt function.
■ Functions of Interrupt Control Registers (ICR0 to ICR15)
Each interrupt control register (ICR) has the following three functions:
• Sets the interrupt level of the associated internal resource.
• Selects either normal interrupt or extended intelligent I/O service to be executed for the interrupt request
from the associated internal resource.
• Selects the channel for extended intelligent I/O service.
Access to this register by read-modify-write instructions should not be performed, because it may cause
faulty operation.
■ Interrupt Control Register (ICR) Bit Configuration
Figure 6.6-1 shows the configuration of the bits of the interrupt control register (ICR).
Figure 6.6-1 Interrupt Control Register (ICR)
bit
15/7
14/6
ICS3
ICS2
W
W
13/5
12/4
ICS1/S1 ICS0/S0
*
*
11/3
10/2
9/1
8/0
ISE
IL2
IL1
IL0
R/W
R/W
R/W
R/W
00000111B when the
interrupt
control register (ICR) is reset.
* : "1" is read by read operation.
Notes:
• ICS3 to ICS0 are effective when the extended intelligent I/O service is activated. If the extended
intelligent I/O service is activated, set the ISE bit to "1". If not, set this bit to "0". Unless the
extended intelligent I/O service is activated, the settings of ICS3 to ICS0 may be omitted.
• Only write is enabled for ISC1 and ICS0. Only read is enabled for S1 and S0.
52
CHAPTER 6 INTERRUPT HANDLING
6.7
Meanings of the Bits of Interrupt Control Register (ICR)
The meanings of the bits of the interrupt control register (ICR) are as follows:
• Extended intelligent I/O service channel selection bits (ICS0 to ICS3):
Any combination of these bits specifies a channel for extended intelligent I/O
service.
• Extended intelligent I/O service end status (S0, S1):
The combinations of S0 and S1 bits indicate the end conditions of the
extended intelligent I/O service.
• Extended intelligent I/O service enable bit (ISE):
This bit activates the extended intelligent I/O service.
• Interrupt level setting bits (IL0 to IL2):
Any combination of these bits sets an interrupt level.
■ Extended Intelligent I/O Service Channel Selection Bits
(bit15 to bit12 or bit7 to bit4: ICS0 to ICS3)
These bits are used for write only and any combination of these bits specifies a channel for extended
intelligent I/O service. A value set by these bits determines the address in the memory of the extended
intelligent I/O service descriptor which is detailed later in this manual. All ICSs are initialized by reset.
Table 6.7-1 lists the correspondence between ICSs bits, the channel numbers, and descriptor addresses.
Table 6.7-1 Correspondence between ICS Bits, Channel Numbers, and Descriptor
Addresses
ICS3
ICS2
ICS1
ICS0
Selected channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
53
CHAPTER 6 INTERRUPT HANDLING
■ Extended Intelligent I/O Service End Status (bit13, bit 12 or bit5, bit4: S0, S1)
These bits are used for read only. By checking a value set by these bits at the end of the extended
intelligent I/O service, you can know what the end condition was. After reset, any value becomes "00".
Table 6.7-2 shows the relationship between the S0 and S1 bit settings and the end conditions.
Table 6.7-2 Extended Intelligent I/O Service End Status Bits (S0 and S1) and End
Conditions
S1
S0
End condition
0
0
Reserved
0
1
End by count out
1
0
Reserved
1
1
End by the request from an internal resource
■ Extended Intelligent I/O Service Enable Bit (bit11 or bit3: ISE)
This bit is read and write enabled. If an interrupt request occurs with this bit set to "1", the extended
intelligent I/O service is activated. If an interrupt request occurs with this bit set to "0", the interrupt
sequence is activated. Furthermore, when any end condition for the extended intelligent I/O service is met
(that is, S1 and S0 bits are other than "00"), the ISE bit is cleared. If the associated internal resource is not
provided with extended intelligent I/O service, the ISE bit must be set to "0" by software. The ISE bit is
initialized to "0" by reset.
■ Interrupt Level Setting Bits (bit10 to bit8 or bit2 to bit0: IL2 to IL0)
These bits are read and write enabled and any combination of these bits specifies an interrupt level of the
associated internal resource. The setting is initialized to level 7 (no interrupt) by reset. Table 6.7-3 shows
the relationship between the interrupt level setting bits and the interrupt levels.
Table 6.7-3 Interrupt Level Setting Bits and Associated Interrupt Levels
54
IL2
IL1
IL0
Level value
0
0
0
0 (Highest priority)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6 (Lowest priority)
1
1
1
7 (No interrupt)
CHAPTER 6 INTERRUPT HANDLING
6.8
Extended Intelligent I/O Service Descriptor (ISD)
The extended intelligent I/O service descriptor (ISD) is allocated to the area of 000100H
through 00017FH in the internal RAM. It consists of the followings:
• Various types of control data for data transfer
• Status data
• Buffer address pointer
■ Extended Intelligent I/O Service Descriptor (ISD)
Figure 6.8-1 shows the configuration of the extended intelligent I/O service descriptor (ISD).
Figure 6.8-1 Configuration of Extended Intelligent I/O Service Descriptor
MSB
000100H + 8 × ICS
ISD start address
Upper 8 bits of data counter (DCTH)
Lower 8 bits of data counter (DCTL)
Upper 8 bits of I/O address pointer (IOAH)
Lower 8 bits of I/O address pointer (IOAL)
EI2OS status (ISCS)
Upper 8 bits of buffer address pointer (BAPH)
Medium 8 bits of buffer address pointer (BAPM)
Lower 8 bits of buffer address pointer (BAPL)
LSB
H
L
55
CHAPTER 6 INTERRUPT HANDLING
6.9
Registers of Extended Intelligent I/O Service Descriptor
The extended intelligent I/O service descriptor (ISD) consists of the following registers:
• Buffer address pointer (BAP)
• Extended intelligent I/O service status register (ISCS)
• I/O register address pointer (IOA)
• Data counter (DCT)
Note that these registers are undefined when reset.
■ Buffer Address Pointer (BAP)
The buffer address pointer (BAP) is a 24-bit register that holds an address to be used in the next transfer by
extended intelligent I/O service. An independent buffer address pointer (BAP) exists for each extended
intelligent I/O service channel. Thus, data transfer on each extended intelligent I/O service channel is
possible between an arbitrary address among 16 Mbytes and I/O.
Note:
If the BF bit in the extended intelligent I/O service status register (ISCS) indicates "update enabled",
only the lower 16 bits of BAP (BAPL) will change, but the upper 8 bits (BAPH) will not change.
■ Extended Intelligent I/O Service Status Register (ISCS)
The extended intelligent I/O service status register (ISCS) is a register of 8-bit length. It indicates whether
the value is updated or fixed and incremental or decremental update is enabled regarding the buffer address
pointer and the I/O register address pointer. In addition, it indicates the data format (byte/word) for transfer
and the transfer direction. Figure 6.9-1 shows the configuration of the extended intelligent I/O service
status register (ISCS).
Figure 6.9-1 Configuration of Extended Intelligent I/O Service Status Register (ISCS)
bit
7
6
5
Reserved Reserved Reserved
4
3
2
1
0
IF
BW
BF
DIR
SE
: ISCS (undefined when reset)
Note: ISCS bit7 to bit5 must be coded with "0".
The contents of the bits of the ISCS register are as follows:
● bit4 (IF): Specifies whether the I/O register address pointer is updated or fixed.
• 0: The I/O register address pointer is updated after the data transfer.
• 1: The I/O register address pointer is not updated after the data transfer.
Note: Only increment is enabled.
56
CHAPTER 6 INTERRUPT HANDLING
● bit3 (BW): Specifies the data length for transfer.
• 0: Byte
• 1: Word
● bit2 (BF): Indicates whether the buffer address pointer is updated or fixed.
• 0: The buffer address pointer is updated after the data transfer.
• 1: The buffer address pointer is not updated after the data transfer.
Note: If updated, only the lower 16 bits of the buffer address pointer will change. Only increment is
enabled.
● bit1 (DIR): Specifies the data transfer direction.
• 0: I/O → Buffer
• 1: Buffer → I/O
● bit0 (SE): Controls the termination of the extended intelligent I/O service by the request from an
internal resource.
• 0: Does not terminate the extended intelligent I/O service by the request from an internal resource.
• 1: Terminates the extended intelligent I/O service by the request from an internal resource.
■ I/O Register Address Pointer (IOA)
The I/O register address pointer (IOA) is a register of 16-bit length. It indicates the lower digits of the
address (A15 to A0) of the I/O register that transfers data between itself and the buffer. All upper positions
of the address (A23 to A16) are coded with "0", and an arbitrary I/O address from 000000H to 00FFFFH
can be specified in the upper positions.
Figure 6.9-2 shows the configuration of the I/O register address pointer (IOA).
Figure 6.9-2 Configuration of I/O Register Address Pointer (IOA)
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 : IOA (undefined when reset)
■ Data Counter (DCT)
The data counter (DCT) is a register of 16-bit length and holds the data count for transfer. Before each data
is transferred, this counter is decremented by one. When this counter value becomes "0", the extended
intelligent I/O service is terminated.
Figure 6.9-3 shows the configuration of the data counter.
Figure 6.9-3 Configuration of Data Counter (DCT)
bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 : DCT (undefined when reset)
57
CHAPTER 6 INTERRUPT HANDLING
6.10
Exception Processing
Exception processing is basically the same as interrupts. Upon the detection of an
exceptional event on a boundary between instructions, exception processing is
performed apart from normal execution. Generally, exception processing occurs as a
result of an unexpected action. Thus, it is recommended to use the exception
processing feature only for debugging purposes or reactivating the software for
recovery in case of emergency.
■ Exception Occurrence because of the Execution of an Undefined Instruction
F2MC-16LX handles all codes that have not been defined in the instruction map as undefined instructions.
If an undefined instruction is executed, F2MC-16LX performs a processing similar to "INT10" which is a
software interrupt instruction. That is, the execution branches to a routine indicated by the interrupt
number 10 vector, after the contents of the following eight components are saved into the system stack:
• Lower bits of accumulator (AL)
• Lower bits of accumulator (AH)
• Direct page register (DPR)
• Data bank register (DTB)
• Additional data bank register (ADB)
• Program bank register (PCB)
• Program counter (PC)
• Processor status (PS)
Then, F2MC-16LX clears the interrupt enable flag (I flag) and sets the stack flag (S flag). The value of PC
saved into the stack is that address of the location where the undefined instruction is stored. For 2-byte or
longer instruction codes, it is that address of the location where the code identified as being undefined is
stored. It is possible to make recovery by the RETI instruction, but the same exception recurs, so there is
no point in making such recovery.
58
CHAPTER 7
ADDRESSING
This chapter describes addressing for the F2MC-16LX
instructions.
Addressing specifies the data to be used and an address.
In F2MC-16LX, effective addressing or an used instruction
code determines the address format (absolute address
or relative address). When the address format is determined
by the instruction code itself, an address must be specified
in compliance with the used instruction code.
Some instructions enable several types of addressing to
be specified.
7.1 Effective Address Field
7.2 Direct Addressing
7.3 Indirect Addressing
59
CHAPTER 7 ADDRESSING
7.1
Effective Address Field
Table 7.1-1 lists the address formats that may be specified in the effective address field.
■ Effective Address Field
Table 7.1-1 Effective Address Field
Code
00
01
02
03
04
05
06
07
60
Coding
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
10
11
12
13
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
14
15
16
17
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
18
19
1A
1B
1C
1D
1E
1F
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Address format
Default bank
Each column corresponds to the address coding
in the byte, word, and long word types in the
order left to right.
None
Register direct
Register indirect
DTB
DTB
ADB
SPB
Register indirect with post-increment
DTB
DTB
ADB
SPB
Register indirect with 8-bit displacement
DTB
DTB
ADB
SPB
Register indirect with 8-bit displacement
DTB
DTB
ADB
SPB
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit displacement
DTB
DTB
ADB
SPB
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
DTB
DTB
PCB
DTB
CHAPTER 7 ADDRESSING
7.2
Direct Addressing
In direct addressing, a value, register, and address must be directly specified for the
operands.
■ Direct Addressing
● Immediate data (#imm)
Directly specify an operand value. There are four types of immediate data according to data length as
below:
• #imm4
• #imm8
• #imm16
• #imm32
● Register direct
Directly specify a register for the operand. Registers that can be specified are as below:
• General-purpose registers
(Byte):
R0, R1, R2, R3, R4, R5, R6, R7
(Word):
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
(Long word): RL0, RL1, RL2, RL3
• Dedicated registers
(Accumulator): A, AL
(Pointer):
SP *
(Bank):
PCB, DTB, USB, SSB, ADB
(Page):
DPR
(Control):
PS, CCR, RP, ILM
*: For SP, either user stack pointer (USP) or system stack pointer (SSP) is selected for use, according to
the value of the S flag in the condition code register (CCR). For branch instructions, program
counter (PC) is not described in the operand of the instruction, but it is automatically specified.
● Direct branch address (addr16)
Directly specify an address to which the execution will branch by means of displacement. The address
length with displacement is 16 bits and the address indicates the destination of the branch in the logical
space. This addressing is applied to an unconditional branch instruction and a subroutine call instruction.
bits 16 to 23 of the address are given by the program bank register (PCB).
● Physical direct branch address (addr24)
Directly specify a physical address to which the execution will branch by means of displacement. The data
length with displacement is 24 bits. This addressing is applied to an unconditional branch instruction, a
subroutine call instruction, and a software interrupt instruction.
61
CHAPTER 7 ADDRESSING
● I/O direct (io)
Directly specify a memory address in the operand by means of 8-bit displacement. Independently of the
respective values for data bank register (DTB) and direct page register (DPR), the I/O space with physical
addresses 000000H to 0000FFH is accessible. It is invalid to describe the bank select prefix to specify a
bank before an instruction using this addressing.
● Abbreviated direct address (dir)
Specify lower eight bits of a memory address in the operand. Bits 8 to 15 of the address are given by the
direct page register (DPR). Bits 16 to 23 of the address are given by the data bank register (DTB).
● Direct address (addr16)
Specify lower 16 bits of a memory address in the operand. Bits 16 to 23 of the address are given by the
data bank register (DTB).
● I/O direct bit address (io:bp)
Directly specify a bit within the range of physical addresses 000000H to 0000FFH. Bit position is
represented by :bp. The higher number is the most significant bit and the lower number is the least
significant bit.
● Abbreviated direct bit address (dir:bp)
Directly specify lower eight bits of a memory address in the operand. Bits 8 to 15 of the address are given
by the direct page register (DPR). Bits 16 to 23 of the address are given by the data bank register (DTB).
Bit position is represented by :bp. The higher number is the most significant bit and the lower number is
the least significant bit.
● Direct bit address (addr16:bp)
Directly specify an arbitrary bit within 64 Kbytes. Bits 16 to 23 of the address are given by the data bank
register (DTB). Bit position is represented by :bp. The higher number is the most significant bit and the
lower number is the least significant bit.
● Vector address (#vct)
The address to which the execution will branch is determined by the content of the vector that is specified
herein. The vector number data length may be either four bits or eight bits. This addressing is applied to a
subroutine call instruction and a software interrupt instruction.
62
CHAPTER 7 ADDRESSING
7.3
Indirect Addressing
In indirect addressing, the data indicated by the operand you coded indirectly gives an
address.
■ Indirect Addressing
● Register indirect (@RWj j = 0 to 3)
The register indirect addressing is used to access a memory location whose address is specified by the
content of general-purpose register RWj. Bits 16 to 23 of the address are given by the data bank register
(DTB) if RW0 and RW1 are used, by the SPB if RW3 is used, and by the additional data bank register
(ADB) if RW2 is used.
● Register indirect with post-increment (@RWj+ j = 0 to 3)
This addressing is also used to access a memory location whose address is specified by the content of
general-purpose register RWj. After the execution of the operand operation, RWj is incremented by the
operand data length (1 for byte, 2 for word, and 4 for long word). Bits 16 to 23 of the address are given by
the data bank register (DTB) if RW0 and RW1 are used, by the SPB if RW3 is used, and by the additional
data bank register (ADB) if RW2 is used.
If the value resulting from post-increment indicates the address of the increment-specified register itself,
the value of this register is incremented when referred subsequently. Then, if a data write instruction is
issued to the register, the priority is given to the data write instruction, so that the register value, which
would otherwise be incremented, becomes the written data.
● Register indirect with displacement (@RWi+disp8 i = 0 to 7, @RWj+disp16 j = 0 to 3)
This addressing is used to access a memory location whose address is specified by the displacement added
to the content of general-purpose register RWj. Displacement may be either byte or word and is added as a
signed value. Bits 16 to 23 of the address are given by the data bank register (DTB) if RW0, RW1, RW4,
and RW5 are used. Bits 16 to 23 are given by the SPB if RW3 and RW7 and by the additional data bank
register (ADB) if RW2 and RW6 are used.
● Long register indirect with displacement (@RLi+disp8 i = 0 to 3)
This addressing is used to access a memory location whose address is specified by the lower 24 bits that
result from the displacement added to the content of general-purpose register RLi. Displacement is eight
bits and added as a signed value.
● Program counter indirect with displacement (@PC+disp16)
This addressing is used to access a memory location whose address is specified by (address of instruction +
4 + disp16). Displacement is a word length. Bits 16 to 23 of the address are given by the program bank
register (PCB).
Note that respective operand addresses of the instructions listed next are not regarded as being (next
instruction address + disp16):
63
CHAPTER 7 ADDRESSING
• DBNZ
eam, rel
• DWBNQ eam, rel
• CBNE
eam, #imm8, rel
• CWBNE eam, #imml16, rel
• MOV
eam, #imm8
• MOVM
eam, #imm16
● Register indirect with base index (@RW0+RW7, @RW1+RW7)
This addressing is used to access a memory location whose address is specified by a value obtained by
adding the content of RW0 or RW1 to the content of general-purpose register RW7. Bits 16 to 23 of the
address are given by the data bank register (DTB).
● Program counter relative branch address (rel)
The address to which the execution will branch is determined by a value obtained by adding the 8-bit
displacement to the value of the program counter (PC). If the result of the addition exceeds 16 bits, the
bank register is not incremented or decremented and the part of excess is ignored. Consequently, the
address falls within the closed bank of 64 Kbytes. This addressing is applied to an unconditional or
conditional branch instruction. Bits 16 to 23 of the address are given by the program bank register (PCB).
● Register List (rlst)
This addressing specifies a register subjected to push/pop for the stack (see Figure 7.3-1 ).
Figure 7.3-1 Configuration of Register List
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
When the bit is "1", the associated register is selected. When the bit is "0",
the associated register is not selected.
● Accumulator indirect (@A)
This addressing is used to access a memory location whose address is specified by the 16-bit content of the
lower bytes of the accumulator (AL). Bits 16 to 23 of the address are given by the data bank register
(DTB).
● Accumulator indirect branch address (@A)
The address to which the execution will branch is determined by the 16-bit content for the lower bytes of
the accumulator (AL). This address indicates the destination of the branch within the bank space. Bits 16
to 23 of the address are given by the program bank register (PCB). In the case of the jump context (JCTX)
instruction, however, bits 16 to 23 of the address are given by the data bank register (DTB). This
addressing is applied to an unconditional branch instruction.
64
CHAPTER 7 ADDRESSING
● Indirectly specified branch address (@ear)
The word data with the address specified by ear corresponds to the address to which the execution will
branch.
● Indirectly specified branch address (@eam)
The word data with the address specified by eam corresponds to the address to which the execution will
branch.
65
CHAPTER 7 ADDRESSING
66
CHAPTER 8
INSTRUCTION OVERVIEW
This chapter provides explanation for the items
described in "CHAPTER 9 DETAILED EXECUTION
INSTRUCTIONS" and what the symbols used therein
stand for.
8.1 Instruction Overview
8.2 Symbols (Abbreviations) Used in Detailed Execution Instructions
8.3 Effective Address Field
8.4 Execution Cycles
67
CHAPTER 8 INSTRUCTION OVERVIEW
8.1
Instruction Overview
In "CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS" the following items are
described for each instruction.
• Assembler format
• Execution cycles
• Operation
• Correction value
• CCR
• Example
• Byte count
■ Instruction Overview
In "CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS" the following items are described for each
instruction.
● Assembler format
The format for coding each instruction into an assembler source program is presented.
• Upper case letters and symbols: Write them as they are into a source program.
• Lower case letters:
Rewrite them into a source program.
• Number after a lower case letter: Indicates a bit width in the instruction.
● Operation
The operation for registers and data by instruction execution is presented.
● CCR
The status of each flag (I, S, T, N, Z, V and C) of the condition code register (CCR) is presented.
• *: Denotes that the flag changes with the instruction execution.
• –: Denotes that the flag does not change.
• S: Denotes that the flag is set with the instruction execution.
• R: Denotes that the flag is reset with the instruction execution.
● Byte count
The byte count of the instruction (machine language) after assembled is presented.
● Execution cycles
The number of instruction execution cycles is presented.
For the meaning of the letter symbol used in the table, which is presented for description of execution
cycles, see Table 8.4-1 .
68
CHAPTER 8 INSTRUCTION OVERVIEW
● Correction value
A correction value used for calculating the number of instruction execution cycles is presented. For the
meanings of the letter symbols ((b), (c), and (d)) used in the table, which is presented for description of
correction values, see Table 8.4-2 . The number of instruction execution cycles is determined by the sum of
a value given in the column of execution cycles and a value given in the column of correction value.
● Example
An example of each instruction is presented.
All numeric values of the data given in any example are hexadecimal numbers. Any numeric value of the
data given in the operand represents a hexadecimal number with suffix (H).
69
CHAPTER 8 INSTRUCTION OVERVIEW
8.2
Symbols (Abbreviations) Used in Detailed Execution
Instructions
Table 8.2-1 lists the symbols used in detailed execution instruction.
■ Symbols (abbreviations) Used in Detailed Execution Instructions
Table 8.2-1 Symbols (abbreviations) Used in Detailed Execution Instructions (1 / 2)
Coding
A
32-bit accumulator
The length of used bits varies depending on the instruction.
Byte:
Lower 8 bits of AL
Word:
16 bits of AL
Long word: 32 bits of AL and AH
AH
AL
Upper 16 bits of A
Lower 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB
brg2
DTB, ADB, SSB, USB, DPR
Ri
R0, R1, R2, R3, R4, R5, R6, R7
Rj
R0, R1, R2, R3
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
addr24
ad24 0-15
ad24 16-23
io
imm4
imm8
imm16
imm32
ext (imm8)
70
Meaning
Direct addressing
Physical direct addressing
Bits 0 to 15 of addr24
Bits 16 to 23 of addr24
I/O area (000000H to 0000FFH)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit data resulting from the signed extension of 8-bit immediate data
CHAPTER 8 INSTRUCTION OVERVIEW
Table 8.2-1 Symbols (abbreviations) Used in Detailed Execution Instructions (2 / 2)
Coding
disp8
disp16
bp
vct4
vct8
(
)b
Meaning
8-bit displacement
16-bit displacement
Bit offset value
Vector number (0 to 15)
Vector number (0 to 255)
Bit address
re1
Specifies a PC relative branch.
ear
eam
Effective addressing (codes 00 to 07)
Effective addressing (codes 08 to 1F)
r1st
Register list
71
CHAPTER 8 INSTRUCTION OVERVIEW
8.3
Effective Address Field
Table 8.3-1 lists the address formats that may be specified in the effective address field.
■ Effective Address Field
Table 8.3-1 Effective Address Field
Code
00
01
02
03
04
05
06
07
Coding
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Address format
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Byte count of address
extension *
Register direct
ea corresponds to the address coding in the
byte, word, and long word types in the
order left to right.
-
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
Register indirect
0
0C
0D
0E
0F
@RW0 +
@RW1 +
@RW2 +
@RW3 +
Register indirect with post-increment
0
10
11
12
13
14
15
16
17
@RW0 + disp8
@RW1 + disp8
@RW2 + disp8
@RW3 + disp8
@RW4 + disp8
@RW5 + disp8
@RW6 + disp8
@RW7 + disp8
Register indirect with 8-bit displacement
1
18
19
1A
1B
@RW0 + disp16
@RW1 + disp16
@RW2 + disp16
@RW3 + disp16
Register indirect with 16-bit displacement
2
1C
1D
1E
1F
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
*: The byte count of address extension corresponds to "#" (byte count) shown in the instruction list and "+" shown in the byte count field of
each detailed instruction.
72
CHAPTER 8 INSTRUCTION OVERVIEW
8.4
Execution Cycles
The number of cycles required for the execution of an instruction (execution cycles) is
obtained by adding a "correction value", which is determined according to the
condition, to the number of "cycles" specific to each instruction. However, actual
instruction execution cycles may include the cycles required for reading the program in
addition to the sum of "cycles" and a "correction value".
■ Execution Cycles
The number of cycles required for the execution of an instruction is obtained by adding up the number of
"cycles" specific to each instruction, a "correction value", which is determined according to the condition,
and "cycles" required for program fetch.
When fetching a program stored in a memory connected to a 16-bit bus, such as built-in ROM, program
fetch is performed each time the instruction under execution passes over a 2-byte (word) boundary. If data
access interference occurs, it results in an increasing number of execution cycles.
When fetching a program stored in a memory connected to an 8-bit bus, which is an external data bus,
program fetch is performed per byte in the instruction under execution. If data access interference occurs,
it results in an increasing number of execution cycles.
During CPU intermittent operation, the access to a general-purpose register, built-in ROM, built-in RAM,
built-in I/O or external bus causes the CPU clock to make a halt for a certain time. This CPU halt time is
equivalent to the number of cycles specified by the CG1/CG0 bit of the low power consumption mode
control register. Therefore, the number of cycles required for the execution of an instruction during the
CPU intermittent operation should be calculated differently. That is, add "a correction value" determined
by "the number of times for access" × "cycles" for the CPU halt time to normal execution cycles.
73
CHAPTER 8 INSTRUCTION OVERVIEW
■ Calculating Execution Cycles
Table 8.4-1 , Table 8.4-2 , and Table 8.4-3 provide the referenced information which may help you to
calculate instruction execution cycles.
Table 8.4-1 Execution Cycles Specific to Each Addressing Method of an Effective Address
(a) *
Number of times of register access
specific to each addressing method
Code
Operand
00
to
07
08
to
0B
0C
to
0F
10
to
17
18
to
1B
1C
1D
1E
1F
Ri
RWi
RLi
Presented in the instruction list.
@RWj
2
1
@RWj +
4
2
@RWi + disp8
2
1
@RWj +
disp16
2
1
@RW0 + RW7
@RW1 + RW7
@PC + disp16
addr16
4
4
2
1
2
2
0
0
Execution cycles specific to
each addressing method
Presented in the instruction list.
*: (a) is used in "~" (cycles) and "B" (correction value) in "APPENDIX B F2MC-16LX Instruction Lists (351
Instructions)" as well as "CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS".
Table 8.4-2 Correction Values for Cycles Used for Calculating Actual Execution Cycles
(b) * byte
Operand
Internal register
Internal memory even address
Internal memory odd address
External data bus 16-bit even
address
External data bus 16-bit odd
address
External data bus 8-bit
(c) * word
(d) * long
The
number of
cycles
The
number of
times of
access
The
number of
cycles
The
number of
times of
access
The
number of
cycles
The
number of
times of
access
+0
1
+0
1
+0
2
+0
+0
1
1
+0
+2
1
2
+0
+4
2
4
+1
1
+1
1
+2
2
+1
1
+4
2
+8
4
+1
1
+4
2
+8
4
*: (b), (c), and (d) are used in "~" (cycles) and "B" (correction value) in "APPENDIX B F2MC-16LX Instruction Lists (351 Instructions)"
as well as "CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS".
Note: For the application to external buses, the wait cycles for ready input and automatic ready must be added.
74
CHAPTER 8 INSTRUCTION OVERVIEW
Table 8.4-3 Correction Values for Cycles Used for Calculating Program Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
–
+2
External data bus 16-bit
–
+3
External data bus 8-bit
+3
–
Notes: • For the application to external buses, the wait cycles for ready input and automatic ready must
be added.
• Actually, all program fetches do not always cause the delay for the execution of an instruction.
Thus, these correction values should be used to calculate the required execution cycles in the
worst case.
75
CHAPTER 8 INSTRUCTION OVERVIEW
76
CHAPTER 9
DETAILED EXECUTION
INSTRUCTIONS
This chapter explains each of the execution instructions
used by the assembler, in reference format. The
execution instructions are presented in alphabetical
order.
9.1 Detailed Execution Instructions
77
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1
Detailed Execution Instructions
This section explains each of the execution instructions used by the assembler, in
reference format. The execution instructions are presented in alphabetical order.
■ Reading Detailed Execution Instructions
For an explanation of each of the items and symbols (abbreviations) used in the explanation of each
execution instruction, see "CHAPTER 8 INSTRUCTION OVERVIEW".
For an explanation of the alphabetical characters (a), (b), (c), and (d) used in an explanation (table) of
correction values and numbers of cycles, see Table 8.4-1 and Table 8.4-2 .
78
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.1
ADD (Add Byte Data of Destination and Source to
Destination)
Add the byte data specified by the second operand to the byte data specified by the first
operand and store the result in the first operand. If the first operand is the accumulator
(A), "0" are transferred to bits 8 to 15 of A.
■ ADD (Add Byte Data of Destination and Source to Destination)
● Assembler format:
ADD A,#imm8
ADD A,dir
ADD A,ear
ADD A,eam
ADD ear,A
ADD eam,A
● Operation:
(First operand) ← (First operand)+(Second operand)
(Byte addition)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
A
ear
eam
Second operand
#im8
dir
ear
eam
A
A
Number of bytes
2
2
2
2+
2
2+
Number of cycles
2
3
3
4+(a)
3
5+(a)
Correction value
0
(b)
0
(b)
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
79
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
ADD A,0E021H
In this example, the data (ABH) at address E021H is added to the least significant byte data (46H) of A.
A
×× ××
CCR
A0 46
×××××
A
×× ××
CCR
1 0 0 0
Memory
Memory
E021
Before execution
80
×
T N Z V C
T N Z V C
A B
00 F1
A B
E021
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.2
ADDC (Add Byte Data of AL and AH with Carry to AL)
Add the low-order byte data of AL, low-order byte data of AH, and carry bit (C) together
and restore the result in AL. "0" are transferred to the high-order byte of AL.
■ ADDC (Add Byte Data of AL and AH with Carry to AL)
● Assembler format:
ADDC A
● Operation:
(AL) ← (AH)+(AL)+(C)
(Byte addition with a carry)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
ADDC A
In this example, the low-order byte data (05H) of AH, low-order byte data (D4H) of AL, and carry bit (0)
are added together.
A
05 05
CCR
00 D4
××××
A
0
T N Z V C
Before execution
05 05
CCR
00 D9
×
1 0 0 0
T N Z V C
After execution
81
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.3
ADDC (Add Byte Data of Accumulator and Effective
Address with Carry to Accumulator)
Add the least significant byte data of the accumulator (A), byte data at the effective
address, and carry bit (C) together and restore the result in the least significant byte of
A. "0" are transferred to bits 8 to 15 of A.
■ ADDC (Add Byte Data of Accumulator and Effective Address with Carry to
Accumulator)
● Assembler format:
ADDC
A, ear
ADDC
A, eam
●Operation:
(A) ← (A)+(ea)+(C)
(Byte addition with a carry)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
4+(a)
Number of accesses
0
(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
82
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
ADDC
A, 0E035H
In this example, the least significant byte data (46H) of A, data (D5H) at address E035H, and carry bit (1)
are added together.
A
×× ××
CCR
A0 46
××××
A
1
×× ××
CCR
T N Z V C
×
0 0 0 1
T N Z V C
Memory
Memory
D 5
00 2C
E035
Before execution
D 5
E035
After execution
83
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.4
ADDCW (Add Word Data of Accumulator and Effective
Address with Carry to Accumulator)
Add the low-order word data (AL) of the accumulator (A), word data specified by the
second operand, and carry bit (C) together and restore the result in the low-order word
of A.
■ ADDCW (Add Word Data of Accumulator and Effective Address with Carry to
Accumulator)
● Assembler format:
ADDCW
A, ear
ADDCW
A, eam
● Operation:
(A) ← (A)+(ea)+(C)
(Word addition with a carry)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
4+(a)
Correction value
0
(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
84
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
ADDCW A,@RW0+
In this example, the low-order word data (2068H) of A, address data (8952H) specified by RW0, and carry
bit (1) are added together.
A
RW0
×× ××
20 68
CCR
E0 24
××××
A
1
RW0
×× ××
CCR
E0 26
T N Z V C
9
2
×
1 0 0 0
T N Z V C
Memory
Memory
8
5
A9 BB
E025
E024
Before execution
8
5
9
2
E025
E024
After execution
85
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.5
ADDDC (Add Decimal Data of AL and AH with Carry to
AL)
Add the low-order byte data of AL, low-order byte data of AH, and carry bit (C) together
in decimal and restore the result in the low-order byte of AL. "0" are transferred to the
high-order byte of AL.
■ ADDDC (Add Decimal Data of AL and AH with Carry to AL)
● Assembler format:
ADDDC A
● Operation:
(AL) ← (AH)+(AL)+(C)
(Decimal addition with a carry)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Undefined
C:
Set when a carry has occurred as a result of the decimal operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
3
Correction value:
0
● Example:
ADDDC A
In this example, the low-order byte data (62H) of AL, low-order byte data (58H) of AH, and carry bit (C)
are added together in decimal operation.
A
××
62
CCR
××
58
××××
A
0
T N Z V C
Before execution
86
××
62
CCR
00 20
×
0 0
×
1
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.6
ADDL (Add Long Word Data of Destination and Source to
Destination)
Add the long word data specified by the second operand to the long word data specified
by the first operand and restore the result in the first operand.
■ ADDL (Add Long Word Data of Destination and Source to Destination)
● Assembler format:
ADDL A,#imm32
ADDL A,ear
ADDL A,eam
● Operation:
(First operand) ← (First operand)+(Second operand)
(Long word addition)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
Second operand
#i32
ear
eam
Number of bytes
5
2
2+
Number of cycles
4
6
7+(a)
Correction value
0
0
(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
87
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
ADDL A,0E077H
In this example, the data (357F41ABH) at addresses E077H to E07AH is added to the data (85B7A073H) of
A.
A
85 B7
A0 73
CCR
A
BB 36
×××××
E2 1E
CCR
3
7
4
A
5
F
1
B
Memory
E07A
E079
E078
E077
Before execution
88
1 0 0 0
T N Z V C
T N Z V C
Memory
×
3
7
4
A
5
F
1
B
E07A
E079
E078
E077
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.7
ADDSP (Add Word Data of Stack Pointer and Immediate
Data to Stack Pointer)
Add 16-bit immediate data or the value resulting from sign-extending 8-bit immediate
data to the word data pointed to by SP (stack pointer) and restore the result in SP. If the
addition result exceeds 16 bits, an underflow occurs.
CCR does not indicate whether an underflow has occurred.
■ ADDSP (Add Word Data of Stack Pointer and Immediate Data to Stack Pointer)
● Assembler format:
(1) ADDSP #imm8
(2) ADDSP #imm16
● Operation:
(1) (SP) ← (SP)+Sign-extended #imm8
(Word addition)
(2) (SP) ← (SP)+#imm16
(Word addition)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
#im8
#i16
Number of bytes
2
3
Number of cycles
3
3
Correction value
0
0
● Example:
ADDSP #89BAH
In this example, 89BAH is added. The addition result exceeds 16 bits, causing an underflow.
E2 A4
SP
×0000
TNZVC
Before execution
CCR
6C 5E
SP
×0000
TNZVC
After execution
CCR
89
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.8
ADDW (Add Word Data of AL and AH to AL)
Add the word data of AH and that of AL together and restore the result to AL.
■ ADDW (Add Word Data of AL and AH to AL)
● Assembler format:
ADDW A
● Operation:
(AL) ← (AH)+(AL)
(Word addition)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
ADDW A
In this example, a carry occurs, causing the carry flag to be set.
A
83 A2
CCR
7F 23
×××××
T N Z V C
Before execution
90
A
83 A2
CCR
02 C5
×
0 0 0 1
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.9
ADDW (Add Word Data of Destination and Source to
Destination)
Add the word data specified by the second operand to the word data specified by the
first operand and restore the result in the first operand.
■ ADDW (Add Word Data of Destination and Source to Destination)
● Assembler format:
ADDW A,#imm16
ADDW A,ear
ADDW A,eam
ADDW ear,A
ADDW eam,A
● Operation:
(First operand) ← (First operand)+(Second operand)
(Word addition)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a carry has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#i16
ear
eam
A
A
Number of bytes
3
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(c)
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
91
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
ADDW @RW0+1,A
In this example, the low-order word data (CD04H) of the accumulator is added to the address value
(315DH) specified by @RW0+1.
A
RW0
×× ××
E2 A4
CD 04
CCR
×××××
A
RW0
×× ××
E2 A4
CD 04
CCR
Memory
3 1
5 D
X X
Memory
E2A6
E2A5
E2A4
Before execution
92
×
1 0 0 0
T N Z V C
T N Z V C
F E
6 1
× ×
E2A6
E2A5
E2A4
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.10
AND (And Byte Data of Destination and Source to
Destination)
Take the logical AND operation of the byte data specified by the first operand and the
byte data specified by the second operand and restore the result in the first operand.
■ AND (And Byte Data of Destination and Source to Destination)
● Assembler format:
AND A,#imm8
AND A,ear
AND A,eam
AND ear,A
AND eam,A
● Operation:
(First operand) ← (First operand) and (Second operand)
(Byte logical AND)
The logical AND operation of the byte data specified by the first operand and the byte data specified by the
second operand is taken on a bit-by-bit basis and the result is restored in the first operand.
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#im8
ear
eam
A
A
Number of bytes
2
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(b)
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
93
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
AND 0052H,A
In this example, the logical AND operation is taken of the address data (FAH) at 0052H and the least
significant byte data (55H) of the accumulator.
A
×× ××
CCR
00 55
×××××
A
×× ××
CCR
T N Z V C
0052
Before execution
94
×
0 0 0
×
T N Z V C
Memory
Memory
F A
00 55
5 0
0052
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.11
AND (And Byte Data of Immediate Data and Condition
Code Register)
Take the logical AND operation of the byte data of the condition code register (CCR) and
8-bit immediate data and restore the result in CCR.
In the logical AND operation, the most significant bit of the byte data is not taken into
consideration.
■ AND (And Byte Data of Immediate Data and Condition Code Register)
● Assembler format:
AND CCR,#imm8
● Operation:
(CCR) ← (CCR) and #imm8
(Byte logical AND)
● CCR:
I
S
T
N
Z
V
C
*
*
*
*
*
*
*
I
:
Stores bit 6 of the operation result.
S :
Stores bit 5 of the operation result.
T :
Stores bit 4 of the operation result.
N :
Stores bit 3 of the operation result.
Z :
Stores bit 2 of the operation result.
V :
Stores bit 1 of the operation result.
C :
Stores bit 0 of the operation result.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
3
Correction value:
0
95
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
AND CCR,#57H
In this example, the logical AND operation is taken of the value (0110101B) of the condition code register
(CCR) and 57H.
A
CCR
×× ××
I
0
S
1
T
1
×× ××
N
0
Z
1
V
0
C
1
A
CCR
×× ××
I
0
S
0
T
1
ILM2 ILM1 ILM0
× × ×
ILM
MSB
RP
Before execution
96
N
0
Z
1
V
0
C
1
ILM2 ILM1 ILM0
× × ×
ILM
LSB
× × × × ×
×× ××
MSB
RP
LSB
× × × × ×
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.12
ANDL (And Long Word Data of Destination and Source to
Destination)
Take the logical AND operation for the long word data of the accumulator (A) and that
specified by the second operand in a bit-by-bit basis and restore the result in A.
■ ANDL (And Long Word Data of Destination and Source to Destination)
● Assembler format:
ANDL A,ear
ANDL A,eam
● Operation:
(A) ← (A) and (Second operand)
(Long word logical AND)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
6
7+(a)
Correction value
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
97
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
ANDL A,0FFF0H
In this example, the logical AND operation is taken of the long word data (8252FEACH) of A and the data
(FF55AA00H) at 0FFF0H to 0FFF3H, in a bit-by-bit basis.
A
82 52
FE AC
CCR
A
82 50
×××××
AA 00
CCR
T N Z V C
Memory
F
5
A
0
F
5
A
0
1 0 0
FFF3
FFF2
FFF1
FFF0
×
T N Z V C
Memory
Before execution
98
×
F
5
A
0
F
5
A
0
FFF3
FFF2
FFF1
FFF0
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.13
ANDW (And Word Data of AH and AL to AL)
Take the logical AND operation of the word data of AH and that of AL and restore the
result in AL.
■ ANDW (And Word Data of AH and AL to AL)
● Assembler format:
ANDW A
● Operation:
(AL) ← (AH) and (AL)
(Word logical AND)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
ANDW A
In this example, the logical AND operation is taken of the word data (0426H) of AH and word data
(AB98H) of AL.
A
04 26
CCR
AB 98
×××××
T N Z V C
Before execution
A
04 26
CCR
00 00
×
0 1 0
×
T N Z V C
After execution
99
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.14
ANDW (And Word Data of Destination and Source to
Destination)
Take the logical AND operation of the word data specified by the first operand and the
word data specified by the second operand and restore the reresult in the first operand.
■ ANDW (And Word Data of Destination and Source to Destination)
● Assembler format:
ANDW A,#imm16
ANDW A,ear
ANDW A,eam
ANDW ear,A
ANDW eam,A
● Operation:
(First operand) ← (First operand) and (Second operand)
(Word logical AND)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#i16
ear
eam
A
A
Number of bytes
3
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(c)
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
100
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
ANDW 0E001H,A
In this example, the logical AND operation is taken of the word data (8342H) at addresses 0E001H and
0E002H and the low-order word data (5963H) of the accumulator.
A
×× ××
CCR
59 63
×××××
A
×× ××
CCR
T N Z V C
Memory
8 3
4 2
59 63
×
0 0 0
×
T N Z V C
Memory
E002
E001
Before execution
0 1
4 2
E002
E001
After execution
101
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.15
ASR (Arithmetic Shift Byte Data of Accumulator to Right)
Shift the least significant byte data of the accumulator (A) arithmetically to the right by
the number of bits specified by the second operand. The most significant bit of the
least significant byte data for A is not changed. The bit last shifted out from the least
significant bit is stored in the carry bit (C) of the condition code register (CCR).
■ ASR (Arithmetic Shift Byte Data of Accumulator to Right)
● Assembler format:
ASR A,R0
● Operation:
MSB
C
LSB
T
1
A
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S:
Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is "0".
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is "0", cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is "0".
● Number of bytes, Number of cycles, and Correction value:
102
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0; otherwise, 5 + (R0)
Correction value:
0
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
ASR A,R0
In this example, the least significant byte data (96H) of A is shifted arithmetically to the right by three bits.
A
×× ××
R0
××
03
CCR
96
×××××
T N Z V C
Before execution
A
×× ××
R0
××
03
F2
CCR 1 1 0
×
1
T N Z V C
After execution
103
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.16
ASRL (Arithmetic Shift Long Word Data of Accumulator
to Right)
Shift the long word data of the accumulator (A) arithmetically to the right by the number
of bits specified by the second operand. The most significant bit of A is not changed.
The bit last shifted out from the least significant bit is stored in the carry bit (C) of the
condition code register (CCR).
■ ASRL (Arithmetic Shift Long Word Data of Accumulator to Right)
● Assembler format:
ASRL A,R0
● Operation:
MSB
LSB
C
T
1
A
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S:
Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is "0".
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is "0", cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is "0".
● Number of bytes, Number of cycles, and Correction value:
104
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0; otherwise, 6 + (R0)
Correction value:
0
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
ASRL A,R0
In this example, the long word data (12345678H) of A is shifted arithmetically to the right by two bits.
A
12 34
56 78
R0
CCR
0
2
× ×××0
T N Z V C
Before execution
A
04 8D
15 9E
R0
0
2
CCR 1 0 0 × 0
T N Z V C
After execution
105
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.17
ASRW (Arithmetic Shift Word Data of Accumulator to
Right)
Shift the low-order word data of the accumulator (A) arithmetically to the right by one
bit. The most significant bit of the low-order word data for A is not changed. The bit
shifted out from the least significant bit is stored in the carry bit (C).
■ ASRW (Arithmetic Shift Word Data of Accumulator to Right)
● Assembler format:
ASRW A
● Operation:
MSB
LSB
C
T
1
A
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S:
Unchanged
T:
Set when the old carry value is equal to "1" or the old T value is equal to "1", cleared
otherwise.
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is "0", cleared otherwise.
V:
Unchanged
C:
Stores the bit shifted out from the LSB of A.
● Number of bytes, Number of cycles, and Correction value:
106
Number of bytes:
1
Number of cycles:
2
Correction value:
0
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
ASRW A
In this example, the low-order word data (A096H) of A is shifted arithmetically to the right by one bit.
A
×× ××
A0 96
CCR 0
×××
A
1
T N Z V C
Before execution
×× ××
D0 4B
CCR 1 1 0
×
0
T N Z V C
After execution
107
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.18
ASRW (Arithmetic Shift Word Data of Accumulator to
Right)
Shift the low-order word data of the accumulator (A) arithmetically to the right by the
number of bits specified by the second operand. The most significant bit of the loworder word data for A is not changed. The bit last shifted out from the least significant
bit is stored in the carry bit (C) of the condition code register (CCR).
■ ASRW (Arithmetic Shift Word Data of Accumulator to Right)
● Assembler format:
ASRW A,R0
● Operation:
MSB
LSB
C
T
1
A
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S:
Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is "0".
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is "0", cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is "0".
● Number of bytes, Number of cycles, and Correction value:
108
Number of bytes:
2
Number of states:
6 when (R0) is equal to 0; otherwise, 5 + (R0)
Correction value:
0
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
ASRW A,R0
In this example, the low-order word data (A096H) of A is shifted arithmetically to the right by two bits.
A
×× ××
R0 0 2
A0 96
CCR
××××
A
0
T N Z V C
Before execution
×× ××
R0 0 2
E8 25
CCR 0 1 0
×
1
T N Z V C
After execution
109
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.19
BBcc (Branch if Bit Condition satisfied)
Cause a branch if the bit data specified by the first operand satisfies the condition.
Control is transferred to the address resulting from word-adding the sign-extended
data, specified by the second operand, to the address of the instruction following the
BBcc instruction.
■ BBcc (Branch if Bit Condition satisfied)
● Assembler format:
BBC <First operand>,rel
BBS <First operand>,rel
● Operation:
If the condition is satisfied:
(PC) ← (PC) + <Number of bytes> + rel
(Word addition)
If the condition is not satisfied:
(PC) ← (PC)+<Number of bytes>
(Word addition)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
*
–
–
I, S, T, and N:Unchanged
Z:
Set when the bit data is "0"; cleared when "1".
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
BBcc
BBC
BBS
Condition
Bit data = 0
Bit data = 1
First
operand
addr16:bp
dir:bp
io:bp
addr16:bp
dir:bp
io:bp
Number of
bytes
5
4
4
5
4
4
Number of
cycles *1
If a branch is
taken: 8
If a branch is
not taken: 7
If a branch is
taken: 8
If a branch is
not taken: 7
If a branch is
taken: 7
If a branch is
not taken: 6
If a branch is
taken: 8
If a branch is
not taken: 7
If a branch is
taken: 8
If a branch is
not taken: 7
If a branch is
taken: 7
If a branch is
not taken: 6
Correction
value *2
(b)
(b)
(b)
(b)
(b)
(b)
*1: “If a branch is taken” indicates the number of cycles assumed if a branch is taken. “If a branch is not taken” indicates
the number of cycles assumed if a branch is not taken.
*2: For the explanation of (b) in the table, see Table 8.4-2 .
110
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
BBC 1234H:7,12H
In this example, a branch is taken if bit 7 of the data at memory address 1234H is equal to "0" (condition
satisfied).
PC
+ (12 + number of bytes 5)
E100
PC
E117
Memory
Memory
× ×
× ×
7 F
1234
: bit7 = 0
7 F
1234
× ×
× ×
Before execution
After execution
111
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.20
Bcc (Branch relative if Condition satisfied)
Each instruction causes a branch if the condition determined for that instruction is
satisfied. Control is transferred to the address resulting from word-adding the signextended data, specified by the operand, to the address of the instruction following the
BBcc instruction.
■ Bcc (Branch relative if Condition satisfied)
● Assembler format:
BZ/BEQ rel
BNZ/BNE
rel
BC/BLO rel
BNC/BHS
rel
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
● Operation:
If the condition is satisfied:
(PC) ← (PC)+2+rel
(Word addition)
If the condition is not satisfied:
(PC) ← (PC)+2
(Word addition)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
112
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
3 when branching is not performed, 4 otherwise.
Correction value:
0
Branch instruction and condition:
Bcc
BZ/
BEQ
BNZ/
BNE
BC/
BLO
BNC/
BHS
BN
BP
BV
BNV
BT
BNT
BRA
Condition
Z=1
Z=0
C=1
C=0
N=1
N=0
V=1
V=0
T=1
T=0
Always
satisfied
Bcc
BLT
BGE
BLE
BGT
BLS
BHI
Condition
V xor N = 1
V xor N = 0
(V xor N) or
Z=1
(V xor N) or
Z=0
C or Z = 1
C or Z = 0
● Example:
BHI 50H
In this example, a branch is taken if either C or Z or both of the condition code register (CCR) are equal to
"0" (condition satisfied).
PC
E 2
0 0
CCR 0 1 0 1 0
+(2+50)
C or Z = 0, then
PC
E 2
5 2
CCR 0 1 0 1 0
T N Z V C
T N Z V C
Before execution
After execution
113
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.21
CALL (Call Subroutine)
Cause a branch to the address specified by the operand. By executing the RET
instruction in the subroutine to which control has been transferred, control returns to
the instruction following the CALL instruction.
■ CALL (Call Subroutine)
● Assembler format:
CALL @ear
CALL @eam
CALL addr16
● Operation:
(SP) ← (SP)–2 (Word subtraction), ((SP)) ← (PC)+<Number of bytes>
(PC) ← <Operand>
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
@ear
@eam
ad16
Number of bytes
2
2+
3
Number of cycles
6
7+(a)
6
Correction value
(c)
2×(c)
(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
114
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
CALL @RW0
PC
E5 58
RW0
F3 40
SP
01 24
PC
DC 08
RW0
F3 40
Memory
SP
SP
01 22
Memory
D C
0 8
F341
F340
D C
0 8
F341
F340
× ×
× ×
× ×
0124
0123
0122
× ×
0124
0123
0122
Before execution
SP
E 5
5 A
After execution
115
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.22
CALLP (Call Physical Address)
Cause a branch to the physical address specified by the operand. The program bank
register (PCB) stores the most significant byte of the data specified by the operand. By
executing the RETP instruction in the subroutine to which control has been transferred,
control returns to the instruction following the CALLP instruction.
■ CALLP (Call physical Address)
● Assembler format:
CALLP @ear
CALLP @eam
CALLP addr24
● Operation:
(SP) ← (SP)–2 (Word subtraction), ((SP)) ← (PCB) (Zero extension)
(SP) ← (SP)–2 (Word subtraction), ((SP)) ← (PC)+<Number of bytes>
(PCB) ← Physical address to branch to (High-order byte)
(PC) ← Physical address to branch to (Low-order word)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
@ear
@eam
ad24
Number of bytes
2
2+
4
Number of cycles
10
11+(a)
10
Correction value
2×(c)
3×(c)+(b)
2×(c)
For the explanation of (a), (b), and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
116
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
CALLP 080711H
In this example, the most significant byte (08H) of the operand is set in the program bank register (PCB).
PC
43 45
PCB
SP
F9 00
AD
USB
CCR
×
0
15
PC
07 11
PCB
SP
08
×××××
CCR
×
×
×
×
×
×
×
×
×
×
USB
×
0
15
×××××
I S T N Z V C
I S T N Z V C
Memory
SP
F8 FC
Memory
15F900
15F8FF
15F8FE
15F8FD
15F8FC
Before execution
× ×
SP
0
A
4
4
0
D
3
9
15F900
15F8FF
15F8FE
15F8FD
15F8FC
After execution
117
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.23
CALLV (Call Vectored Subroutine)
Cause a branch to the address pointed to by the interrupt vector specified by the
operand. By executing the RET instruction in the subroutine to which control has been
transferred, control returns to the instruction following the CALLV instruction. The RET
instruction is the same as that used with the CALL instruction.
■ CALLV (Call Vectored Subroutine)
● Assembler format:
CALLV #vct4
● Operation:
(SP) ← (SP)–2 (Word subtraction)
((SP)) ← (PC) + 1
(PC) ← Vector address
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
7
Correction value:
2×(c)
Note: For the explanation of (c), see Table 8.4-2 .
Note:
When the value of the program bank register (PCB) is equal to "FFH", the vector area is also used as
the vector area for INT #vct8 (#0 to #7). Caution must, therefore, be exercised when the area is
used. (See Table 9.1-1 .)
118
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
CALLV #15
PC
F4 A7
SP
01 02
PC
E1 54
Memory
SP
SP
01 00
Memory
E 1
5 4
FFE1
FFE0
E 1
5 4
FFE1
FFE0
× ×
× ×
× ×
0102
0101
0100
× ×
0102
0101
0100
SP
Before execution
F 4
A 8
After execution
Table 9.1-1 CALLV Vector List
Note:
Instruction
Vector address L
Vector address H
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
XX is replaced by the value of the PCB register.
119
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.24
CBNE (Compare Byte Data and Branch if not equal)
Perform byte comparison on the first and second operands (8-bit immediate data) and
cause a branch if the first and second operands are not equal. Control is transferred to
the address equal to the address of the instruction following the CBNE instruction plus
the word value resulting from sign-extending the third operand. A branch is not taken if
the first and second operands are equal.
Note that, when the first operand is @PC + disp16, the operand address is equal to the
"address of the location containing the machine instruction for the CBNE instruction + 4
+ disp16", not the "address of the location containing the machine instruction for the
instruction following the CBNE instruction 4 + disp16".
■ CBNE (Compare Byte Data and Branch if not equal)
● Assembler format:
CBNE A,#imm8,rel
CBNE ear,#imm8,rel
CBNE eam,#imm8,rel
● Operation:
(First operand)≠imm8 (Byte comparison) :(PC) ← (PC)+<Number of bytes>+rel
(First operand)=imm8 (Byte comparison) :(PC) ← (PC)+<Number of bytes>
● CCR:
120
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the compare operation result is "1", cleared otherwise.
Z:
Set when (First operand) = imm8, cleared otherwise.
V:
Set when an overflow has occurred as a result of the compare operation, cleared
otherwise.
C:
Set when a borrow has occurred as a result of the compare operation, cleared otherwise.
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Number of bytes, Number of cycles, and Correction value:
First operand
A
ear
eam *
Number of bytes
3
4
4+
Number of cycles
If a branch is taken: 5
If a branch is not taken: 4
Correction value
If a branch is taken: 13
If a branch is not taken: 12
0
If a branch is taken: 7+(a)
If a branch is not taken: 6+(a)
0
(b)
* : @Rwj+ addressing cannot be used in eam. If such code is executed, +4 is added to the contents of Rwj.
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
●Example:
CBNE
A, #0F4H,55H
In this example, (First operand) ≠ Second operand (8-bit immediate data) is indicated.
A
×× ××
PC
CCR
00 F3
E3 10
×××××
T N Z V C
Before execution
F3H≠F4H
A
+(55H+Number of bytes: 3)
×× ××
PC
CCR
00 F3
E3 68
×
1 0 0 1
T N Z V C
After execution
121
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.25
CLRB (Clear Bit)
Clear the bit specified by bp to "0", in the memory location specified by the operand.
■ CLRB (Clear Bit)
● Assembler format:
CLRB dir:bp
CLRB io:bp
CLRB addr16:bp
● Operation:
(Operand) b ← 0
(Bit transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
dir:bp
io:bp
ad16:bp
Number of bytes
3
3
4
Number of cycles
7
7
7
Correction value
2×(b)
2×(b)
2×(b)
For the explanation of (b) in the table, see Table 8.4-2 .
● Example:
CLRB 0AA55H:3
In this example, bit 3 of the data (FFH) at address AA55H is cleared to "0".
Memory
Memory
× ×
× ×
F F
122
AA55
F 7
AA55
× ×
× ×
Before execution
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.26
CMP (Compare Byte Data of Destination and Source)
Compare the byte data specified by the first operand with that specified by the second
operand and set the flag changes in the condition code register (CCR). The data
specified by the first operand and that by the second operand are not changed.
If only the accumulator (A) is specified as an operand, AH and AL are compared.
■ CMP (Compare Byte Data of Destination and Source)
● Assembler format:
(1)
CMP A,#imm8
CMP A,ear
(2)
CMP A,eam
CMP A
● Operation:
(1)
(First operand)–(Second operand)
(Byte comparison)
(2)
(AH)–(AL)
(Byte comparison)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
AH
Second operand
#im8
ear
eam
AL
Number of bytes
2
2
2+
1
Number of cycles
2
2
3+(a)
1
Correction value
0
0
(b)
0
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
123
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
CMP A,#7FH
In this example, the least significant byte data (22H) of A is compared with 7FH.
A
×× ××
CCR
A0 22
×××××
T N Z V C
Before execution
124
A
×× ××
CCR
A0 22
×
1 0 0 1
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.27
CMPL (Compare Long Word Data of Destination and
Source)
Compare the long word data specified by the first operand with that specified by the
second operand and set the result in the condition code register (CCR). The data
specified by the first operand and that specified by the second are not changed.
■ CMPL (Compare Long Word Data of Destination and Source)
● Assembler format:
CMPL A,#imm32
CMPL A,ear
CMPL A,eam
● Operation:
(First operand)–(Second operand)
(Long word comparison)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
Second operand
#i32
ear
eam
Number of bytes
5
2
2+
Number of cycles
3
6
7+(a)
Correction value
0
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
125
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
CMPL A,#12345678H
A
12 34
CCR
56 78
×××××
T N Z V C
Before execution
126
A
12 34
CCR
56 78
×
0 1 0 0
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.28
CMPW (Compare Word Data of Destination and Source)
Compare the word data specified by the first operand with that specified by the second
operand and set the result in the condition code register (CCR). The data specified by
the first operand and that specified by the second operand are not changed.
If only A is specified as an operand, AH and AL are compared.
■ CMPW (Compare Word Data of Destination and Source)
● Assembler format:
(1)
CMPW A,#imm16
CMPW A,ear
(2)
CMPW A,eam
CMPW A
● Operation:
(1)
(First operand)–(Second operand)
(Word comparison)
(2)
(AH)–(AL)
(Word comparison)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
AH
Second operand
#i16
ear
eam
AL
Number of bytes
3
2
2+
1
Number of cycles
2
2
3+(a)
1
Correction value
0
0
(c)
0
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
127
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
CMPW A,RW0
In this example, the low-order word data (ABCDH) of A is compared with the data (ABCCH) specified by
RW0.
A
×× ××
RW0
CCR
AB CD
AB CC
×××××
T N Z V C
Before execution
128
A
×× ××
RW0
CCR
AB CD
AB CC
×
0 0 0 0
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.29
CWBNE (Compare Word Data and Branch if not Equal)
Perform word comparison on the first and second operands (16-bit immediate data) and
cause a branch if the first and second operands are not equal. Control is transferred to
the address equal to the address of the instruction following the CWBNE instruction
plus the word data resulting from sign-extending the third operand. A branch is not
taken if the first and second operands are equal.
Note that, when the first operand is @PC + disp16, the operand address is equal to the
"address of the location containing the machine instruction for the CWBNE instruction +
4 + disp16", not the "address of the location containing the machine instruction for the
instruction following the CWBNE instruction + disp16".
■ CWBNE (Compare Word Data and Branch if not Equal)
● Assembler format:
CWBNE A,#imm16,rel
CWBNE ear,#imm16,rel
CWBNE eam,#imm16,rel
● Operation:
(First operand)≠imm16 (Word comparison) : (PC) ← (PC)+<Number of bytes>+rel
(First operand)=imm16 (Word comparison) : (PC) ← (PC)+<Number of bytes>
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the comparison result is "1", cleared otherwise.
Z:
Set when (First operand) = #imm16, cleared otherwise.
V:
Set when an overflow has occurred as a result of the compare operation, cleared
otherwise.
C:
Set when a borrow has occurred as a result of the compare operation, cleared otherwise.
129
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Number of bytes, Number of cycles, and Correction value:
First operand
A
ear
eam *
Number of bytes
4
5
5+
Number of cycles
If a branch is taken: 5
If a branch is not taken: 4
If a branch is taken: 8
If a branch is not taken: 7
If a branch is taken: 7+(a)
If a branch is not taken:
6+(a)
Correction value
0
0
(c)
*: @Rwj+ addressing cannot be used in eam. If such code is executed, +4 is added to the contents of Rwj.
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
CWBNE A,#0E5E5H,30H
In this example, (First operand) ≠ imm16.
A
×× ××
PC
CCR
5E E5
D8 56
×××××
T N Z V C
Before execution
130
A
×× ××
PC
CCR
5E E5
D8 8A
×
0 0 0 0
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.30
DBNZ (Decrement Byte Data and Branch if not "0")
Decrement the data specified by the first operand by one byte, and if the result is not
equal to "0", a branch is generated. Control is transferred to the address equal to the
address of the instruction following the DBNZ instruction plus the word data resulting
from sign-extending the data specified by the second operand. If the decrement result
is equal to "0", control is transferred to the next instruction.
Note that, when the first operand is @PC + disp16, the operand address is equal to the
"address of the location containing the machine instruction for the DBNZ instruction + 4 +
disp16", not the "address of the location containing the machine instruction for the
instruction following the DBNZ instruction + disp16".
■ DBNZ (Decrement Byte Data and Branch if not "0")
● Assembler format:
DBNZ ear,rel
DBNZ eam,rel
● Operation:
(ea) ← (ea)–1 (Byte subtraction)
if (ea) ≠ 0 : (PC) ← (PC)+<Number of bytes>+rel
if (ea) = 0 : (PC) ← (PC)+<Number of bytes>
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
ear
eam
Number of bytes
3
3+
Number of cycles
If a branch is taken: 7
If a branch is not taken: 6
If a branch is taken: 8+(a)
If a branch is not taken: 7+(a)
Correction value
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
131
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
DBNZ @RW0+2,40H
In this example, (First operand) - 1 ≠ 0 is shown.
PC
E3 58
PC
E3 9C
RW0
01 20
RW0
01 20
CCR 0 0 0 0 1
T N Z V C
CCR 0 0 1 0 1
T N Z V C
Memory
RW0+2
0
3
× ×
× ×
Memory
0122
0121
0120
Before execution
132
RW0+2
0
2
× ×
× ×
After execution
0122
0121
0120
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.31
DEC (Decrement Byte Data)
Decrement the byte data specified by the operand by one and store the result in the
operand.
■ DEC (Decrement Byte Data)
● Assembler format:
DEC ear
DEC eam
● Operation:
(ea) ← (ea)–1
(Byte subtraction)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
5+(a)
Correction value
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
DEC R1
R1
CCR
80
×××××
T N Z V C
Before execution
R1
CCR
7F
×
0 0 1
×
T N Z V C
After execution
133
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.32
DECL (Decrement Long Word Data)
Decrement the long word data specified by the operand by one and restore the result in
the operand.
■ DECL (Decrement Long Word Data)
● Assembler format:
DECL ear
DECL eam
● Operation:
(ea) ← (ea)–1
(Long word subtraction)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
ear
eam
Number of bytes
2
2+
Number of cycles
7
9+(a)
Correction value
0
2×(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
DECL RL0
RL0
0 0 0 0
CCR
10 00
×××××
T N Z V C
Before execution
134
RL0
00 00
CCR
0F FF
×
0 0 0
×
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.33
DECW (Decrement Word Data)
Decrement the word data specified by the operand by one and restore the result in the
operand.
■ DECW (Decrement Word Data)
● Assembler format:
DECW ear
DECW eam
● Operation:
(ea) ← (ea)–1
(Word subtraction)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
5+(a)
Correction value
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
135
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
DECW @RW0+1000H
67 80
RW0
CCR
RW0+1000H
×××××
CCR
×
0 0 1
×
T N Z V C
T N Z V C
Memory
Memory
0
0
0
1
× ×
7781
7780
777F
Before execution
136
67 80
RW0
RW0+1000H
0
0
0
0
× ×
7781
7780
777F
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.34
DIV (Divide Word Data by Byte Data)
Divide the word data specified by the first operand by the byte data specified by the
second operand and store the quotient (byte data) in the first operand and the
remainder (byte data) in the second operand. The operation assumes that the values
are signed ones.
If only A is specified by an operand, the word data of AH is divided by the byte data of
AL and the quotient (byte data) is stored in AL and the remainder (byte data) in AH. The
operation assumes that the values are signed ones.
If division by "0" occurs, the second operand or AL retains the value it had immediately
before the instruction was executed. If an overflow occurs, the contents of AL are
destroyed.
■ DIV (Divide Word Data by Byte Data)
● Assembler format:
(1)
DIV A,ear
(2)
DIV A
DIV A,eam
● Operation:
(1)
Word (A)/Byte (ea), Quotient → Byte (A), Remainder → Byte (ea)
(2)
Word (AH)/Byte (AL), Quotient → Byte (AL), Remainder → Byte (AH)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
*
*
I, S, T, N, and Z: Unchanged
V:
Set when an overflow has occurred as a result of the operation or the divisor is "0",
cleared otherwise.
C:
Set when the divisor is "0", cleared otherwise.
137
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Number of bytes, Number of cycles, and Correction value:
Second operand
DIV A
DIV A, ear
DIV A, eam
Number of bytes
2
2
2+
Number of cycles
Division by zero: 3
Overflow: 8 or 18
Normal termination: 18
Division by zero: 4
Overflow: 11 or 22
Normal termination: 23
Division by zero: 5+(a)
Overflow: 12+(a) or 23+(a)
Normal termination: 24+(a)
Correction value
0
0
*
*: (b) when division by zero or an overflow occurs; 2 × (b) when the instruction terminated normally.
For the explanation of (a) in the table and (b) in "*", see Table 8.4-1 and Table 8.4-2 .
● Example:
DIVA
A
AH
13 57
CCR
AL
00 AA
×××××
T N Z V C
Before execution
138
A
AH
00 31
CCR
AL
EC D8
×××
0 0
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.35
DIVW (Divide Long Word Data by Word Data)
Divide the long word data specified by the first operand (A) by the word data specified
by the second operand and store the quotient (word data) in A and the remainder (word
data) in the second operand. The operation assumes that the values are signed ones.
If division by "0" occurs, the second operand or AL retains the value it had immediately
before the instruction was executed. If an overflow occurs, the contents of AL are
destroyed.
■ DIVW (Divide Long Word Data by Word Data)
● Assembler format:
DIVW A,ear
DIVW A,eam
● Operation:
Long word (A)/Word (ea), Quotient → Word (A), Remainder → Word (ea)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
*
*
I, S, T, N, and Z: Unchanged
V:
Set when an overflow has occurred as a result of the operation or the divisor is "0",
cleared otherwise.
C:
Set when the divisor is "0", cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Second operand
DIVW A, ear
DIVW A, eam
Sign of the dividend
Plus
Minus
Plus
Minus
Number of bytes
2
2
2+
2+
Number of cycles
Correction value
Division by zero: 5+(a) Division by zero: 5+(a)
Division by zero: 4 Division by zero: 4
Overflow: 12+(a) or
Overflow: 12+(a) or
Overflow: 11 or 30 Overflow: 12 or 31
31+(a)
32+(a)
Normal termination: Normal termination:
Normal termination:
Normal termination:
31
32
32+(a)
33+(a)
0
0
*
*
*: (c) when division by zero or an overflow occurs; 2 × (c) when the instruction terminated normally.
For the explanation of (a) in the table and (c) in "*", see Table 8.4-1 and Table 8.4-2 .
139
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
DIVW A,7254H
A
AH
AL
00 00
13 57
CCR
×××××
A
AL
00 1D
AH
00 00
CCR
×××
T N Z V C
T N Z V C
Memory
0 0
A A
Memory
7255
7254
Before execution
140
0 0
0 0
1 5
7255
7254
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.36
DIVU (Divide unsigned Word Data by unsigned Byte
Data)
Divide the word data specified by the first operand by the byte data specified by the
second operand and store the quotient (byte data) in the first operand and the
remainder (byte data) in the second operand. The operation assumes that the values
are unsigned ones.
If only A is specified by an operand, the word data of AH is divided by the byte data of
AL and the quotient (byte data) is stored in AL and the remainder (byte data) in AH. The
operation assumes that the values are unsigned ones.
If an overflow or division by "0" occurs, the second operand or AL retains the value it
had immediately before the instruction was executed.
■ DIVU (Divide unsigned Word Data by unsigned Byte Data)
● Assembler format:
(1)
DIVU A,ear
(2)
DIVU A
DIVU A,eam
● Operation:
(1)
Word (A)/Byte (ea), Quotient → Byte (A), Remainder → Byte (ea)
(2)
Word (AH)/Byte (AL), Quotient → Byte (AL), Remainder → Byte (AH)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
*
*
I, S, T, N, and Z: Unchanged
V:
Set when an overflow has occurred as a result of the operation or the divisor is "0",
cleared otherwise.
C:
Set when the divisor is "0", cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Assembler format
DIVU A
DIVU A, ear
DIVU A, eam
Number of bytes
1
2
2+
Number of cycles
Correction value
Division by zero: 3
Overflow: 7
Normal termination: 15
0
Division by zero: 4
Overflow: 8
Normal termination: 16
Division by zero: 6+(a)
Overflow: 9+(a)
Normal termination: 19+(a)
0
*
*: (b) when division by zero or an overflow occurs; 2 × (b) when the instruction terminated normally.
For the explanation of (a) in the table and (b) in "*", see Table 8.4-1 and Table 8.4-2 .
141
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
DIVU A
A
13 57
CCR
00 AA
×××××
T N Z V C
Before execution
142
A
00 15
CCR
00 1D
×××
0 0
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.37
DIVUW (Divide unsigned Long Word Data by unsigned
Word Data)
Divide the long word data specified by the first operand (A) by the word data specified
by the second operand and store the quotient (word data) in A and the remainder (word
data) in the second operand. The operation assumes that the values are unsigned
ones.
If an overflow or division by "0" occurs, the second operand or AL retains the value it
had immediately before the instruction was executed.
■ DIVUW (Divide unsigned Long Word Data by unsigned Word Data)
● Assembler format:
DIVUW A,ear
DIVUW A,eam
● Operation:
Long Word (A)/Word (ea), Quotient → Word (A), Remainder → Word (ea)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
*
*
I, S, T, N, and Z: Unchanged
V:
Set when an overflow has occurred as a result of the operation or the divisor is "0",
cleared otherwise.
C:
Set when the divisor is "0", cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Assembler format
DIVU A, ear
DIVU A, eam
Number of bytes
2
2+
Number of cycles
Correction value
Division by zero: 4
Overflow: 7
Normal termination: 22
0
Division by zero: 6+(a)
Overflow: 8+(a)
Normal termination: 26+(a)
*
*: (c) when division by zero or an overflow occurs; 2 × (c) when the instruction terminated normally.
For the explanation of (a) in the table and (c) in "*", see Table 8.4-1 and Table 8.4-2 .
143
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
DIVUW A,7254H
A
00 00
CCR
13 57
×××××
A
00 00
CCR
0 0
Memory
Memory
7255
7254
Before execution
144
×××
T N Z V C
T N Z V C
0 0
A A
00 1D
0 0
1 5
7255
7254
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.38
DWBNZ (Decrement Word Data and Branch if not Zero)
Decrement the data specified by the first operand by one word, and if the result is not
equal to "0", cause a branch. Control is transferred to the address equal to the address
of the instruction following the DWBNZ instruction plus the word data resulting from
sign-extending the data specified by the second operand. If the decrement result is
equal to "0", control is transferred to the instruction following the DWBNZ instruction.
When the first operand is @PC + disp16, the operand address is equal to the "address
of the location containing the machine instruction for the DWBNZ instruction + 4 +
disp16", not the "address of the location containing the machine instruction for the
instruction following the DWBNZ instruction + disp16".
■ DWBNZ (Decrement Word Data and Branch if not Zero)
● Assembler format:
DWBNZ ear,rel
DWBNZ eam,rel
● Operation:
(First operand) ← (First operand)–1 (Word subtraction)
When (First operand)≠0, (PC) ← (PC)+<Number of bytes>+second operand
(PC) ← (PC)+<Number of bytes>
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Second operand
ear
eam
Number of bytes
3
3+
Number of cycles
Correction value
If a branch is taken: 7
If a branch is not taken: 6
0
If a branch is taken: 8+(a)
If a branch is not taken: 7+(a)
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
145
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
DWBNZ RW0,30H
In this example, (First operand) – 1 = 0.
PC
F8 20
PC
F8 23
RW0
00 01
RW0
00 00
CCR
×××××
T N Z V C
Before execution
146
CCR
×
0 0 0
×
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.39
EXT (Sign Extend from Byte Data to Word Data)
Extend the least significant byte data of A to word data as a signed binary number.
■ EXT (Sign Extend from Byte Data to Word Data)
● Assembler format:
EXT
● Operation:
When bit 7 of A=0, bits 8 to 15 of A ← 00H
When bit 7 of A≠0, bits 8 to 15 of A ← FFH
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the sign-extended data is "1", cleared otherwise.
Z:
Set when the sign-extended data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
1
Correction value:
0
● Example:
EXT
In this example, the most significant bit of the least significant byte data ("80H") for A is equal to "1", and
"FFH" is set in bits 8 to 15 of A to extend the byte data.
A
×× ××
CCR
××
80
×××××
T N Z V C
Before execution
A
×× ××
CCR
FF 80
×
1 0
××
T N Z V C
After execution
147
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.40
EXTW (Sign Extend from Word Data to Long Word Data)
Extend the low-order word data of A to long word data as a signed binary number.
■ EXTW (Sign Extend from Word Data to Long Word Data)
● Assembler format:
EXTW
● Operation:
When bit15 of A=0, bits 16 to 31 of A ← 0000H
When bit15 of A≠0, bits 16 to 31 of A ← FFFFH
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the sign-extended data is "1", cleared otherwise.
Z:
Set when the sign-extended data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
EXTW
In this example, the most significant bit of the low-order word data ("FF80H") for A is equal to "1", and
"FFFFH" is set in bits 16 to 31 of A to extend the low-order word data.
A
×× ××
CCR
FF 80
×××××
T N Z V C
Before execution
148
A
FF FF
CCR
FF 80
×
1 0
××
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.41
FILS (Fill String Byte)
Transfer the contents of AL to the RW0-byte area that starts from the address whose
high-order eight bits are specified by the bank register specified by <bank> and whose
low-order 16 bits are specified by the contents of AH.
If RW0 is equal to "0", transfer is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended. After the
interrupt has been handled, the execution of the instruction is resumed.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. If <bank>
is omitted, DTB is assumed.
■ FILS (Fill String Byte)
● Assembler format:
FILS [I]
[<bank>]
● Operation:
While RW0 ≠ 0, the following operation is repeated:
((AH)) ← (AL) (Byte transfer), (AH) ← (AH)+1,
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
6×(RW0)+6
Correction value:
(b)×(RW0)
For the explanation of (b), see Table 8.4-2 .
149
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
FILS
AH
BC 00
RW0
01 00
CCR
AL
00 E5
DTB
94
AH
BD 00
RW0
00 00
×××××
CCR
T N Z V C
×
××
× ×
AH
1 0
94BC02
94BC01
94BC00
94BD00
94BCFF
94BCFE
E 5
E 5
...
...
...
...
94BD00
94BCFF
94BCFE
Before execution
150
94
Memory
× ×
× ×
× ×
AH
DTB
T N Z V C
Memory
× ×
× ×
× ×
AL
00 E5
E 5
E 5
E 5
94BC02
94BC01
94BC00
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.42
FILSW (Fill String Word)
Transfer the contents of AL to the RW0-word area that starts from the address whose
high-order eight bits are specified by the bank register specified by <bank> and whose
low-order 16 bits are specified by the contents of AH.
If RW0 is equal to "0", transfer is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended. After the
interrupt has been handled, the execution of the instruction is resumed.
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. If <bank>
is omitted, DTB is assumed.
■ FILSW (Fill String Word)
● Assembler format:
FILSW [I]
[<bank>]
● Operation:
While RW0 ≠ 0, the following operation is repeated:
((AH)) ← (AL) (Word transfer), (AH) ← (AH)+2,
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes: 2
Number of cycles: 6×(RW0)+6
Correction value: (c)×(RW0)
For the explanation of (c), see Table 8.4-2 .
151
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
FILSW ADB
AH
AB FE
RW0
00 80
CCR
AL
E5 5E
ADB
49
AH
AC FE
RW0
00 00
×××××
CCR
T N Z V C
×
××
× ×
× ×
AH
0 0
49AC00
49ABFF
49ABFE
49ACFF
49ACFE
49ACFD
E 5
...
...
...
...
49ACFF
49ACFE
49ACFD
Before execution
152
49
Memory
× ×
× ×
× ×
AH
ADB
T N Z V C
Memory
× ×
× ×
× ×
AL
E5 5E
5 E
E 5
5 E
49AC00
49ABFF
49ABFE
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.43
INC (Increment Byte Data (Address Specification))
Increment the byte data specified by the operand by one and restore the result in the
operand.
■ INC (Increment Byte Data (Address Specification))
● Assembler format:
INC ear
INC eam
● Operation:
(Operand) ← (Operand)+1
(Byte increment)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
5+(a)
Correction value
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
INC R0
R0
CCR
FF
×××××
T N Z V C
Before execution
00
R0
CCR
×
0 1 0
×
T N Z V C
After execution
153
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.44
INCL (Increment Long Word Data)
Increment the long word data specified by the operand by one and restore the result in
the operand.
■ INCL (Increment Long Word Data)
● Assembler format:
INCL ear
INCL eam
● Operation:
(Operand) ← (Operand)+1
(Long word increment)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
ear
eam
Number of bytes
2
2+
Number of cycles
7
9+(a)
Correction value
0
2×(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
INCL RL0
RL0
7F FF
CCR
FF FF
×××××
T N Z V C
Before execution
154
A
80 00
CCR
00 00
×
1 0 1
×
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.45
INCW (Increment Word Data)
Increment the word data specified by the operand by one and restore the result in the
operand.
■ INCW (Increment Word Data)
● Assembler format:
INCW ear
INCW eam
● Operation:
(Operand) ← (Operand)+1
(Word increment)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
5+(a)
Correction value
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
155
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
INCW @RW0+
03 54
RW0
CCR
×××××
CCR
0 0 0
×
T N Z V C
Memory
Memory
0
0
1
1
0357
0356
0355
0354
Before execution
156
×
T N Z V C
× ×
× ×
RW0
03 56
RW0
RW0
× ×
× ×
0
0
1
2
After execution
0357
0356
0355
0354
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.46
INT (Software Interrupt)
Cause a branch to the interrupt handling routine at the specified address in the bank
0FFH. By executing the RETI instruction in the interrupt handling routine to which
control has been transferred, control returns to the instruction following this
instruction.
■ INT (Software Interrupt)
● Assembler format:
INT addr16
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP)) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB)(DPR and ADB are saved as a set, DPR as the high-order
byte and ADB as the low-order byte.)
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB) (DTB and PCB are saved as a set, DTB as the high-order
byte and PCB as the low-order byte.)
(SSP) ← (SSP)–2, ((SSP)) ← (PC+3), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0, (PCB) ← 0FFH, (PC) ← addr16
● CCR:
I
S
T
N
Z
V
C
R
S
–
–
–
–
–
I
:
Cleared
S
:
Set
T, N, Z, V, and C :
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
3
Number of cycles:
16
Correction value:
6×(c)
For the explanation of (c), see Table 8.4-2 .
157
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
INT 020F2H
SA
FF EE
DD CC
DTB
PCB
PC
99
88
77 66
DPR ADB
CCR
BB
AA
ILM
RP
I S T N Z V C
03
10
0 0 0 0 1 0 1
SSB
SSP
03
80 00
SA
FF EE
DD CC
DTB
PCB
PC
99
FF
20 F2
DPR ADB
CCR
BB
AA
I S T N Z V C
ILM
RP
0 1 0 0 1 0 1
03
10
SSB
SSP
03
7F F4
Memory
Memory
SSP
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
Before execution
158
SSP
F
E
D
C
B
A
9
8
7
6
7
8
F
E
D
C
B
A
9
8
7
9
0
5
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.47
INT (Software Interrupt (Vector Specification))
Cause a branch to the interrupt handling routine pointed to by the interrupt vector
specified by the operand.
■ INT (Software Interrupt (Vector Specification))
● Assembler format:
INT #vct8
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB)(DPR and ADB are saved as a set, DPR as the high-order
byte and ADB as the low-order byte.)
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB) (DTB and PCB are saved as a set, DTB as the high-order
byte and PCB as the low-order byte.)
(SSP) ← (SSP)–2, ((SSP)) ← (PC+2), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0, (PCB) ← Vector address (High-order byte)
(PC) ← Vector address (Low-order word)
● CCR:
I
S
T
N
Z
V
C
R
S
–
–
–
–
–
I
:
Cleared
S
:
Set
T, N, Z, V, and C :
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
20
Correction value:
8×(c)
For the explanation of (c), see Table 8.4-2 .
159
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
INT #11
SA
SA
FF EE
DTB
99
DPR
BB
ILM
02
SSB
03
DD CC
PCB
PC
88
77 66
ADB
CCR
AA
RP
I S T N Z V C
15
0 0 0 0 1 0 1
SSP
80 00
FF EE
DTB
99
DPR
BB
ILM
02
SSB
03
Memory
PCB
PC
89
E7 95
ADB
CCR
AA
RP
I S T N Z V C
15
0 1 0 0 1 0 1
SSP
7F F4
Memory
8 9
E 7
9 5
FFFFD2
FFFFD1
FFFFD0
8 9
E 7
9 5
FFFFD2
FFFFD1
FFFFD0
×
×
×
×
×
×
×
×
×
×
×
×
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
F
E
D
C
B
A
9
8
7
6
5
8
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
SSP
×
×
×
×
×
×
×
×
×
×
×
×
Before execution
160
DD CC
SSP
F
E
D
C
B
A
9
8
7
8
5
5
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.48
INT9 (Software Interrupt)
Cause a branch to the interrupt handling routine pointed to by the vector.
By executing the RETI instruction in the interrupt handling routine to which control has
been transferred, control returns to the instruction following this instruction.
■ INT9 (Software Interrupt)
● Assembler format:
INT9
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP)) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB)(DPR and ADB are saved as a set, DPR as the high-order
byte and ADB as the low-order byte.)
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB) (DTB and PCB are saved as a set, DTB as the high-order
byte and PCB as the low-order byte.)
(SSP) ← (SSP)–2, ((SSP)) ← (PC+1), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0, (PCB) ← Vector address (High-order byte)
← Vector address (Low-order word)
(PC)
● CCR:
I
S
T
N
Z
V
C
R
S
–
–
–
–
–
I
:
Cleared
S
:
Set
T, N, Z, V, and C :
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
20
Correction value:
8×(c)
For the explanation of (c), see Table 8.4-2 .
161
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
INT9
SA
11 22
DTB
77
DPR
55
ILM
02
SSB
03
33 44
PCB
PC
88
99 AA
ADB
CCR
66
RP
I S T N Z V C
15
0 0 0 0 1 0 1
SSP
80 00
SA
11 22
33 44
DTB
PCB
PC
77
89
E7 95
DPR ADB
CCR
55
66
ILM
RP
I S T N Z V C
02
15
0 1 0 0 1 0 1
SSB
SSP
03
7F F4
Memory
Memory
8 9
E 7
9 5
FFFFDA
FFFFD9
FFFFD8
8 9
E 7
9 5
FFFFDA
FFFFD9
FFFFD8
×
×
×
×
×
×
×
×
×
×
×
×
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
1
2
3
4
5
6
7
8
9
A
5
8
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
SSP
×
×
×
×
×
×
×
×
×
×
×
×
Before execution
162
SSP
1
2
3
4
5
6
7
8
9
B
5
5
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.49
INTP (Software Interrupt)
Cause a branch to the interrupt handling routine at the 24-bit physical address specified
by the operand. Any address in the entire 16MB space can be specified.
By executing the RETI instruction in the interrupt handling routine to which control has
been transferred, control returns to the instruction following this instruction.
■ INTP (Software Interrupt)
● Assembler format:
INTP addr24
● Operation:
(SSP) ← (SSP)–2, ((SSP)) ← (AH), (SSP) ← (SSP)–2, ((SSP)) ← (AL)
(SSP) ← (SSP)–2, ((SSP)) ← (DPR) : (ADB)(DPR: High-order byte, ADB: Low-order byte)
(SSP) ← (SSP)–2, ((SSP)) ← (DTB) : (PCB) (DTB: High-order byte, PCB: Low-order byte)
(SSP) ← (SSP)–2, ((SSP)) ← (PC+4), (SSP) ← (SSP)–2, ((SSP)) ← (PS)
(S) ← 1, (I) ← 0, (PCB) ← Most significant byte of addr24,
(PC) ← Low-order word of addr24
● CCR:
I
S
T
N
Z
V
C
R
S
–
–
–
–
–
I:
Cleared
S:
Set
T, N, Z, V, and C: Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
4
Number of cycles:
17
Correction value:
6×(c)
For the explanation of (c), see Table 8.4-2 .
163
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
INTP 0C8F220H
A
A
11 22
DTB
77
DPR
55
ILM
03
SSB
03
33 44
PCB
PC
88
99 AA
ADB
CCR
66
RP
I S T N Z V C
10
0 0 0 0 1 0 1
SSP
80 00
11 22
DTB
77
DPR
55
ILM
03
SSB
03
Memory
Memory
SSP
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
Before execution
164
33 44
PCB
PC
C8
F2 20
ADB
CCR
66
I S T N Z V C
RP
0 1 0 0 1 0 1
10
SSP
7F F4
SSP
1
2
3
4
5
6
7
8
9
A
7
8
1
2
3
4
5
6
7
8
9
E
0
5
After execution
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.50
JCTX (Jump Context)
Restore register contents or an address saved in memory.
■ JCTX (Jump Context)
● Assembler format:
JCTX @A
● Operation:
(temp)
← (AL)
(PS)
← ((temp)) : (temp) ← (temp)+2
(PC)
← ((temp)) : (temp) ← (temp)+2
(DTB), (PCB)
← ((temp)) : (temp) ← (temp)+2
(DPR), (ADB)
← ((temp)) : (temp) ← (temp)+2
(AL)
← ((temp)) : (temp) ← (temp)+2
(AH)
← ((temp))
● CCR:
I
I
S
T
N
Z
V
C
*
*
*
*
*
*
*
:
Stores bit 6 of the address indicated by AL.
S :
Stores bit 5 of the address indicated by AL.
T :
Stores bit 4 of the address indicated by AL.
N :
Stores bit 3 of the address indicated by AL.
Z :
Stores bit 2 of the address indicated by AL.
V :
Stores bit 1 of the address indicated by AL.
C :
Stores bit 0 of the address indicated by AL.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
14
Correction value:
6×(c)
For the explanation of (c), see Table 8.4-2 .
165
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
JCTX @A
SA
SA
×× ××
CB 75
E0 20
DTB
09
DPR
PCB
PC
××
×× ××
××
××
ILM
RP
××
×× × × × × × × ×
ADB
CCR
I S T N Z V C
AL
B
5
2
0
8
E
0
0
8
1
6
A
09E02C
09E02B
09E02A
09E029
09E028
09E027
09E026
09E025
09E024
09E023
09E022
09E021
09E020
Before execution
166
PCB
50
ADB
CE
RP
16
PC
88 01
CCR
I S T N Z V C
0 0 0 1 0 1 0
Memory
Memory
C
7
0
5
0
C
8
5
8
0
F
8
DTB
80
DPR
08
ILM
07
02 50
C
7
0
5
0
C
8
5
8
0
F
8
B
5
2
0
8
E
0
0
8
1
6
A
After execution
09E02C
09E02B
09E02A
09E029
09E028
09E027
09E026
09E025
09E024
09E023
09E022
09E021
09E020
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.51
JMP (Jump Destination Address)
Read the word data from the address specified by the operand and cause a branch to
the address specified by the word data.
■ JMP (Jump Destination Address)
● Assembler format:
JMP @A
JMP addr16
JMP @ear
JMP @eam
● Operation:
(PC) ← (Operand)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
@A
@ear
@eam
ad16
Number of bytes
1
2
2+
3
Number of cycles
2
3
4+(a)
3
Correction value
0
0
(c)
0
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
JMP @@RW0+2
PC
E0 00
PC
DB 80
RW0
A0 A0
RW0
A0 A0
Memory
RW0+2
D
8
B
0
× ×
× ×
Memory
A0A3
A0A2
A0A1
A0A0
Before execution
RW0+2
D
8
B
0
× ×
× ×
A0A3
A0A2
A0A1
A0A0
After execution
167
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.52
JMPP (Jump Destination Physical Address)
If the operand is addr24, this instruction causes a branch to the physical address
specified by addr24.
If the operand is @ea, the instruction causes a branch to the physical address specified
by the contents of the operand.
■ JMPP (Jump Destination Physical Address)
● Assembler format:
(1)
JMPP addr24
(2)
JMPP @ear
JMPP @eam
● Operation:
(1):
(2):
(PC)
← Low-order word of addr24
(PCB)
← Most significant byte of addr24
(PC)
← (ea)
(Word transfer)
(PCB)
← (ea+2)
(Byte transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
ad24
@ear
@eam
Number of bytes
4
2
2+
Number of cycles
4
5
6+(a)
Correction value
0
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
JMPP 0FFC850H
PC
12 48
PCB 3 4
Before execution
168
PC
C8 50
PCB F F
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.53
LINK (Link and create new stack frame)
Store the current value of the frame pointer (RW3) in a stack and set a new frame
pointer. This allows an area for a new local variable to be reserved. This instruction is
used before a function is called.
■ LINK (Link and create new stack frame)
● Assembler format:
LINK #imm8
● Operation:
(sp) ← (sp)–2 ; ((sp)) ← (RW3) ; (RW3) ← (sp) ; (sp) ← (sp)–imm8
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
6
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
● Example:
LINK #20H
SP
RW3
E0 22
A0 46
SP
RW3
Memory
SP
× ×
E0 00
E0 20
Memory
A
4
E022
SP
Before execution
0
6
E020
× ×
E000
After execution
169
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.54
LSL (Logical Shift Byte Data of Accumulator to Left)
Shift the least significant byte data of the accumulator (A) to the left by the number of
bits specified by the second operand. The least significant bit of A is set to "0". The bit
last shifted out from the most significant bit of the least significant byte data for A is
stored in the carry bit (C).
■ LSL (Logical Shift Byte Data of Accumulator to Left)
● Assembler format:
LSL A,R0
● Operation:
C
A
MSB
LSB
0
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T:
Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is "0", cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the MSB of A. Cleared when the shift amount is "0".
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0 ; otherwise, 5 + (R0)
Correction value:
0
● Example:
LSL A,R0
A
×× ××
R0
CCR
××
FF
02
×××××
T N Z V C
Before execution
170
A
×× ××
R0
××
FC
02
1 0 ××
T N Z V C
After execution
CCR
×
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.55
LSLL (Logical Shift Long Word Data of Accumulator to
Left)
Shift the long word data of the accumulator (A) to the left by the number of bits
specified by the second operand. The least significant bit of A is set to "0". The bit last
shifted out from the most significant bit is stored in the carry bit (C).
■ LSLL (Logical Shift Long Word Data of Accumulator to Left)
● Assembler format:
LSLL A,R0
● Operation:
C
MSB
A
LSB
0
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T:
Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is "0", cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the MSB of A. Cleared when the shift amount is "0".
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0; otherwise, 6 + (R0)
Correction value:
0
● Example:
LSLL A,R0
A
33 33
33 33
R0
CCR
CC CC
CC CC
02
×××××
T N Z V C
Before execution
A
CCR
×
R0
02
1 0
×
0
T N Z V C
After execution
171
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.56
LSLW (Logical Shift Word Data of Accumulator to Left)
Shift the low-order word data of the accumulator (A) to the left by one bit. The least
significant bit of A is set to "0". The bit shifted out from the most significant bit of the
low-order word data for A is stored in the carry bit (C).
■ LSLW (Logical Shift Word Data of Accumulator to Left)
● Assembler format:
LSLW A/SHLW A
● Operation:
C
MSB
A
LSB
0
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T:
Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is "0", cleared otherwise.
V:
Unchanged
C:
Stores the bit shifted out from the MSB of A.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
LSLW A
A
×× ××
CCR
AA 55
×××××
T N Z V C
Before execution
172
A
×× ××
CCR
55 AA
×
0 0
×
1
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.57
LSLW (Logical Shift Word Data of Accumulator to Left)
Shift the low-order word data of the accumulator (A) to the left by the number of bits
specified by the second operand. The least significant bit of A is set to "0". The bit last
shifted out from the most significant bit of the low-order word data for A is stored in the
carry bit (C).
■ LSLW (Logical Shift Word Data of Accumulator to Left)
● Assembler format:
LSLW A,R0
● Operation:
C
MSB
A
LSB
0
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T:
Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is "0", cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the MSB of A. Cleared when the shift amount is "0".
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0; otherwise, 5 + (R0)
Correction value:
0
● Example:
LSLW A,R0
A
×× ××
AA 55
R0
CCR
×× ××
A5 50
04
×××××
T N Z V C
Before execution
A
R0
CCR
×
1 0
04
×
0
T N Z V C
After execution
173
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.58
LSR (Logical Shift Byte Data of Accumulator to Right)
Shift the least significant byte data of the accumulator (A) to the right by the number of
bits specified by the second operand. The most significant bit of the least significant
byte for A is set to "0". The bit last shifted out from the least significant bit is stored in
the carry bit (C).
■ LSR (Logical Shift Byte Data of Accumulator to Right)
● Assembler format:
LSR A,R0
● Operation:
A
MSB
LSB
C
T
1
0
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S:
Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is "0".
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is "0", cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is "0".
● Number of bytes, Number of cycles, and Correction value:
174
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0; otherwise, 5 + (R0)
Correction value:
0
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
LSR A,R0
A
×× ××
R0
CCR
××
FF
05
×××××
T N Z V C
Before execution
A
×× ××
R0
××
07
05
CCR 1 1 0
×
1
T N Z V C
After execution
175
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.59
LSRL (Logical Shift Long Word Data of Accumulator to
Right)
Shift the long word data of the accumulator (A) to the right by the number of bits
specified by the second operand. The most significant bit of A is set to "0". The bit last
shifted out from the least significant bit of A is stored in the carry bit (C).
■ LSRL (Logical Shift Long Word Data of Accumulator to Right)
● Assembler format:
LSRL A,R0
● Operation:
MSB
A
LSB
C
T
1
0
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S:
Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is "0".
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is "0", cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is "0".
● Number of bytes, Number of cycles, and Correction value:
176
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0; otherwise, 6 + (R0)
Correction value:
0
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
LSRL A,R0
A
33 33
33 33
R0
CCR
10
×××××
T N Z V C
Before execution
A
00 00
33 33
R0
CCR 1 0 0
10
×
0
T N Z V C
After execution
177
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.60
LSRW (Logical Shift Word Data of Accumulator to Right)
Shift the low-order word data of the accumulator (A) to the right by one bit. The most
significant bit of the low-order word data for A is set to "0". The least significant bit is
stored in the carry bit (C).
■ LSRW (Logical Shift Word Data of Accumulator to Right)
● Assembler format:
LSRW A/SHRW A
● Operation:
MSB
A
LSB
C
T
1
0
● CCR:
I
S
T
N
Z
V
C
–
–
*
R
*
–
*
I and S:
Unchanged
T:
Stores the OR of the shifted-out data from the carry and the old T flag value.
N:
Cleared
Z:
Set when the shifting result is "0", cleared otherwise.
V:
Unchanged
C:
Stores the bit shifted out from the LSB of A.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
LSRW A
A
×× ××
AA AA
CCR 1
×××
A
0
T N Z V C
Before execution
178
×× ××
55 55
CCR 1 0 0
×
0
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.61
LSRW (Logical Shift Word Data of Accumulator to Right)
Shift the low-order word data of the accumulator (A) to the right by the number of bits
specified by the second operand. The most significant bit of the low-order word data
for A is set to "0". The bit last shifted out from the least significant bit is stored in the
carry bit (C).
■ LSRW (Logical Shift Word Data of Accumulator to Right)
● Assembler format:
LSRW A,R0
● Operation:
MSB
A
LSB
C
T
1
0
● CCR:
I
S
T
N
Z
V
C
–
–
*
*
*
–
*
I and S:
Unchanged
T:
Set when the shifted-out data from the carry contains one or more "1" bits, cleared
otherwise. Also cleared when the shift amount is "0".
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is "0", cleared otherwise.
V:
Unchanged
C:
Stores the bit last shifted out from the LSB of A. Cleared when the shift amount is "0".
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
6 when (R0) is equal to 0; otherwise, 5 + (R0)
Correction value:
0
179
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
LSRW A,R0
A
×× ××
AA AA
R0
CCR
0C
×××××
T N Z V C
Before execution
180
A
×× ××
00 0A
R0
CCR 1 0 0
0C
×
1
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.62
MOV (Move Byte Data from Source to Accumulator)
Transfer the values of bits 0 to 15 for the accumulator (A) to bits 16 to 31, then transfer
"0" to bits 8 to 15. The byte data specified by the second operand is transferred to bits
0 to 7.
If the second operand is @A, transfer to bits 16 to 31 is not performed.
■ MOV (Move Byte Data from Source to Accumulator)
● Assembler format:
MOV A,#imm8
MOV A,Ri
MOV A,@A
MOV A,dir
MOV A,@RLi + disp8
MOV A,addr16
MOV A,io
MOV A,brg1
MOV A,eam
MOV A,ear
● Operation:
(A) ← (Second operand)
(Byte transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Second operand
#im8
@A
@RLi+8
io
ad16
Ri
dir
ear
eam
brg1
Number of bytes
2
2
3
2
3
1
2
2
2+
2
Number of cycles
2
3
10
3
4
2
3
2
3+(a)
*
Correction value
0
(b)
(b)
(b)
(b)
0
(b)
0
(b)
0
*: One cycle for the program bank register (PCB), additional data bank register (ADB), system stack bank register
(SSB), and user stack bank register (USB). Two cycles for the data bank register (DTB) and direct page register
(DPR).
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
181
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
MOV A,0092H
A
×× ××
CCR
A0 46
×××××
A
A0 46
00 71
×
CCR
Memory
Memory
0092
Before execution
182
××
T N Z V C
T N Z V C
7 1
0 0
7 1
0092
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.63
MOV (Move Byte Data from Accumulator to Destination)
Transfer the least significant byte data of the accumulator (A) to the address specified
by the first operand.
■ MOV (Move Byte Data from Accumulator to Destination)
● Assembler format:
MOV dir,A
MOV Ri,A
MOV @RLi+disp8,A
MOV io,A
MOV addr16,A
MOV brg2,A
MOV ear,A
MOV eam,A
● Operation:
(First operand) ← (A)
(Byte transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Second operand
dir
@RLi+8
ad16
io
Ri
ear
eam
brg2
Number of bytes
2
3
3
2
1
2
2+
2
Number of cycles
3
10
4
3
2
2
3+(a)
1
Correction value
(b)
(b)
(b)
(b)
0
0
(b)
0
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
MOV R1,A
A
×× ××
CCR
×××××
49 32
R1
××
T N Z V C
Before execution
A
CCR
×× ××
×
0 0
××
49 32
R1
32
T N Z V C
After execution
183
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.64
MOV (Move Byte Immediate Data to Destination)
Transfer the 8-bit immediate data specified by the second operand to the address
specified by the first operand.
When the first operand is @PC + disp16, the data is transferred to the "address of the
location containing the machine instruction for the MOV instruction + 4 + rel", not the
"address of the location containing the machine instruction for the instruction following
the MOV instruction + rel".
■ MOV (Move Byte Immediate Data to Destination)
● Assembler format:
MOV RP,#imm8
MOV ILM,#imm8
MOV io,#imm8
MOV dir,#imm8
MOV ear,#imm8
MOV eam,#imm8
● Operation:
(First operand) ← #imm8
● CCR:
If the data is transferred to a generalpurpose registers (R0 to R7) or bank
register
184
If the data is transferred to a register other
than the general-purpose registers (R0 to
R7) and the bank register
I
S
T
N
Z
V
C
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
–
–
–
–
–
–
–
I, S, and T:
Unchanged
N:
Unchanged if the data is transferred to a register other than the general-purpose registers.
If the data is transferred to the general-purpose register, N is set when the MSB of the
transferred data is "1", cleared otherwise.
Z:
Unchanged if the data is transferred to a register other than the general-purpose registers.
If the data is transferred to the general-purpose register, Z is set when the transferred data
is "0", cleared otherwise.
V and C:
Unchanged
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Number of bytes, Number of cycles, and Correction value:
First operand
RP
ILM
dir
io
ear
eam
Second operand
#im8
#im8
#im8
#im8
#im8
#im8
Number of bytes
2
2
3
3
3
3+
Number of cycles
2
2
5
5
2
4+(a)
Correction value
0
0
(b)
(b)
0
(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
MOV 009FH,#22H
A
×× ××
CCR
×× ××
×××××
A
×× ××
CCR
7 1
×××××
T N Z V C
T N Z V C
Memory
×× ××
Memory
009F
Before execution
2 2
009F
After execution
185
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.65
MOV (Move Byte Data from Source to Destination)
Transfer the byte data specified by the second operand to the first operand.
MOV Ri, #imm8, described below, is an instruction contained in the basic page map
(see C.1 Table C-1 ), with code different from that contained in MOV ear, #imm8.
■ MOV (Move Byte Data from Source to Destination)
● Assembler format:
MOV Ri,#imm8
MOV Ri,ear
MOV Ri,eam
MOV ear,Ri
MOV eam,Ri
● Operation:
(First operand) ← (Second operand)
(Byte transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
Ri
Ri
Ri
ear
eam
Second operand
#im8
ear
eam
Ri
Ri
Number of bytes
2
2
2+
2
2+
Number of cycles
2
3
4+(a)
4
5+(a)
Correction value
0
0
(b)
0
(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
186
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
MOV R3,@RW0
RW0
R3
××
E0 01
CCR
Memory
7 1
×××××
T N Z V C
E001
Before execution
RW0
R3
71
E0 01
CCR
Memory
7 1
××
0 0 ×
T N Z V C
E001
After execution
187
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.66
MOV (Move Byte Data from AH to Memory)
Transfer the low-order byte data of AH to the memory location specified by the contents
of AL.
■ MOV (Move Byte Data from AH to Memory)
● Assembler format:
MOV @AL,AH
● Operation:
((AL)) ← (AH)
(Byte transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
3
Correction value:
(b)
For the explanation of (b), see Table 8.4-2 .
● Example:
MOV @AL,AH
A
01 22
CCR
E0 84
×××××
A
01 22
CCR
7 1
0 0
××
Memory
E084
Before execution
188
×
T N Z V C
T N Z V C
Memory
E0 84
2 2
E084
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.67
MOVB (Move Bit Data from Bit Address to Accumulator)
Transfer zeros to bits 8 to 15 of the accumulator (A). "00H" is transferred to bits 0 to 7 of
A if the bit of the address specified by the second operand is equal to "0" and "FFH" is
transferred if the bit is equal to "1".
■ MOVB (Move Bit Data from Bit Address to Accumulator)
● Assembler format:
MOVB A,addr16:bp
MOVB A,dir:bp
MOVB A,io:bp
● Operation:
If (Second operand)=0 : (A) ← 00H
(Byte transfer)
If (Second operand)=1 : (A) ← FFH
(Byte transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the transferred bit is "1", cleared when "0".
Z:
Set when the transferred bit is "0", cleared when "1".
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Second operand
ad16:bp
dir:bp
io:bp
Number of bytes
4
3
3
Number of cycles
5
5
4
Correction value
(b)
(b)
(b)
For the explanation of (b) in the table, see Table 8.4-2 .
189
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
MOVB A,32H:3
A
×× ××
CCR
×× ××
×××××
A
×× ××
CCR
Memory
Memory
× ×
× ×
190
0032
×
1 0
××
T N Z V C
T N Z V C
7 F
00 FF
7 F
0032
× ×
× ×
Before execution
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.68
MOVB (Move Bit Data from Accumulator to Bit Address)
Transfer bit data 0 to the bit address specified by the first operand if the least significant
byte data of the accumulator (A) is 00H.
Bit data 1 is transferred to the bit address specified by the first operand if the least
significant byte data of A is not 00H.
■ MOVB (Move Bit Data from Accumulator to Bit Address)
● Assembler format:
MOVB addr16:bp,A
MOVB dir:bp,A
MOVB io:bp,A
● Operation:
If the byte data of (A) is 00H :
(First operand) b=0
(Bit transfer)
If the byte data of (A) is not 00H : (First operand) b=1
(Bit transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the byte data for A is "1", cleared otherwise.
Z:
Set when the byte data of A is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Second operand
ad16:bp
dir:bp
io:bp
Number of bytes
4
3
3
Number of cycles
7
7
6
Correction value
2×(b)
2×(b)
2×(b)
For the explanation of (b) in the table, see Table 8.4-2 .
191
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
MOVB 765FH: 7,A
A
×× ××
CCR
××
01
×××××
A
×× ××
CCR
Memory
Memory
× ×
× ×
192
765F
×
01
0 0
××
T N Z V C
T N Z V C
7 F
××
F F
× ×
× ×
Before execution
After execution
765F
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.69
MOVEA (Move Effective Address to Destination)
Transfer the value specified by the second operand (effective address) to the first
operand. If a general-purpose register is specified by the second operand, the address
of the general-purpose register is transferred.
If the destination (first operand) is the accumulator (A), the pre-transfer values of bits 0
to 15 are transferred to bits 16 to 31 of A.
■ MOVEA (Move Effective Address to Destination)
● Assembler format:
MOVEA <destination>,ear
MOVEA <destination>,eam
● Operation:
First operand ← ea
(Word transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
RWi
RWi
Second operand
ear
eam
ear
eam
Number of bytes
2
2+
2
2+
Number of cycles
1
1+(a)
3
2+(a)
Correction value
0
0
0
0
For the explanation of (a) in the table, see Table 8.4-1 .
● Example:
MOVEA RW2,@RW0+2
RW0
00 69
RW0
00 69
RW2
×× ××
RW2
00 6B
CCR
×××××
T N Z V C
Before execution
CCR
×××××
T N Z V C
After execution
193
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.70
MOVL (Move Long Word Data from Source to
Accumulator)
Transfer the long word data specified by the second operand to the accumulator (A).
■ MOVL (Move Long Word Data from Source to Accumulator)
● Assembler format:
MOVL A,#imm32
MOVL A,ear
MOVL A,eam
● Operation:
(A) ← (Second operand)
(Long word transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Second operand
#i32
ear
eam
Number of bytes
5
2
2+
Number of cycles
3
4
5+(a)
Correction value
0
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
MOVL A,#0053FF64H
A
×× ××
CCR
×× ××
×××××
T N Z V C
Before execution
194
A
00 53
CCR
FF 64
×
0 0
××
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.71
MOVL (Move Long Word Data from Accumulator to
Destination)
Transfer the long word data of the accumulator (A) to the first operand.
■ MOVL (Move Long Word Data from Accumulator to Destination)
● Assembler format:
MOVL ear,A
MOVL eam,A
● Operation:
(First operand) ← (A)
(Long word transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
ear
eam
Number of bytes
2
2+
Number of cycles
4
5+(a)
Correction value
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
MOVL RL1,A
A
01 97
A0 24
A
01 97
A0 24
RL1
×× ××
×× ××
RL1
01 97
A0 24
CCR
×××××
T N Z V C
Before execution
CCR
×
0 0
××
T N Z V C
After execution
195
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.72
MOVN (Move Immediate Nibble Data to Accumulator)
Transfer the values of bits 0 to 15 for the accumulator (A) to bits 16 to 31. "0" is
transferred to bits 4 to 15 and the nibble data specified by the second operand is
transferred to bits 0 to 3.
■ MOVN (Move Immediate Nibble Data to Accumulator)
● Assembler format:
MOVN A,#imm4
● Operation:
(A) ← imm4
(Byte transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
R
*
–
–
I, S, and T:
Unchanged
N:
Cleared
Z:
Set when the transferred data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
1
Correction value:
0
● Example:
MOVN A,#0FH
A
×× ××
CCR
62 07
×××××
T N Z V C
Before execution
196
A
62 07
00 0F
CCR
×
0 0
××
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.73
MOVS (Move String Byte)
Transfer byte data from the address specified by AL in the space specified by <source
bank> to the address specified by AH in the space specified by <destination bank>. The
transfer is repeated the number of times specified by RW0, with the addresses being
changed each time. The transfer is not performed if RW0 is equal to "0". Four types of
registers PCB, DTB, ADB, and SPB can be used as <destination bank> and <source
bank>. By default, DTB is assumed.
The addresses can be either incremented or decremented. By default, the addresses
are incremented.
If an interrupt occurs during the transfer, the transfer is suspended to handle the
interrupt. The transfer is resumed after the interrupt has been handled.
■ MOVS (Move String Byte)
● Assembler format:
MOVSI
[<destination bank>] [,<source bank>] (When the addresses are incremented)
MOVSD [<destination bank>] [,<source bank>] (When the addresses are decremented)
● Operation:
The following is repeated until RW0 becomes equal to "0":
((AH)) ← ((AL))
(Byte transfer)
(AH) ← (AH)±1, (AL) ← (AL)±1 (+ if MOVSWI, – if MOVSWD)
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
5 if (RW0) is equal to "0"; otherwise, 4+8×(RW0)
Correction value:
2×(b)×(RW0)
For the explanation of (b), see Table 8.4-2 .
197
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
MOVSI ADB,PCB
RW0
AH
80 00
AL
00 00
00 03
CCR
AH
80 03
×××××
RW0
00 00
AL
00 03
CCR
T N Z V C
PCB
FF
ADB
T N Z V C
PCB
01
FF
ADB
01
Memory
Memory
C
D
E
F
FF0003
FF0002
FF0001
FF0000
AL
AL
F
F
F
F
F
F
F
F
C
D
E
F
FF0003
FF0002
FF0001
FF0000
×
×
×
×
018003
018002
018001
018000
AH
× ×
AH
×
×
×
×
018003
018002
018001
018000
Before execution
198
×××××
F D
F E
F F
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.74
MOVSW (Move String Word)
Transfer word data from the address specified by AL in the space specified by <source
bank> to the address specified by AH in the space specified by <destination bank>. The
transfer is repeated the number of times specified by RW0, with the addresses being
changed each time. The transfer is not performed if RW0 is equal to "0". Four types of
registers PCB, DTB, ADB, and SPB can be used as <destination bank> and <source
bank>. By default, DTB is assumed.
The addresses can be either incremented or decremented. By default, the addresses
are incremented.
If an interrupt occurs during the transfer, the transfer is suspended to handle the
interrupt. The transfer is resumed after the interrupt has been handled.
■ MOVSW (Move String Word)
● Assembler format:
MOVSWI
[<destination bank>] [,<source bank>] (When the addresses are incremented)
MOVSWD
[<destination bank>] [,<source bank>] (When the addresses are decremented)
● Operation:
The following is repeated until RW0 becomes equal to "0":
((AH)) ← ((AL))
(Byte transfer)
(AH) ← (AH)±2, (AL) ← (AL)±2 (+ if MOVSWI, – for MOVSWD)
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
5 if (RW0) is equal to "0"; otherwise, 4 + 8×(RW0)
Correction value:
2×(c)×(RW0)
For the explanation of (c), see Table 8.4-2 .
199
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
MOVSW,ADB
AH
00 00
RW0
AH
00 06
AL
A0 00
CCR
00 03
×××××
RW0
AL
A0 06
CCR
00 00
T N Z V C
T N Z V C
DTB
CD
ADB
DTB
38
CD
ADB
AH
×
×
×
×
×
×
38
Memory
Memory
×
×
×
×
×
×
×××××
CD0005
CD0004
CD0003
CD0002
CD0001
CD0000
AH
2
4
3
3
4
4
6
2
6
1
D
6
CD0005
CD0004
CD0003
CD0002
CD0001
CD0000
2
4
3
3
4
4
6
2
6
1
D
6
38A005
38A004
38A003
38A002
38A001
38A000
AL
AL
2
4
3
3
4
4
6
2
6
1
D
6
38A005
38A004
38A003
38A002
38A001
38A000
Before execution
200
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.75
MOVW (Move Word Data from Source to Accumulator)
Transfer the values of bits 0 to 15 for the accumulator (A) to bits 16 to 31. Then, the
word data specified by the second operand is transferred to bit0 to bit15 of A. If the
second operand is @A, transfer the values of bits 0 to 15 of A to bits 16 to 31 is not
performed.
■ MOVW (Move Word Data from Source to Accumulator)
● Assembler format:
MOVW A,#imm16
MOVW A,@RWi+disp8
MOVW A,@A
MOVW A,addr16
MOVW A,@RLi+disp8
MOVW A,RWi
MOVW A,SP
MOVW A,dir
MOVW A,io
MOVW A,ear
MOVW A,eam
● Operation:
(A) ← (Second operand)
(Word transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Second operand
#i16
@A
@RLi+8
SP
io
@RWi+8
ad16
RWi
dir
ear
eam
Number of bytes
3
2
3
1
2
2
3
1
2
2
2+
Number of cycles
2
3
10
1
3
5
4
2
3
2
3+(a)
Correction value
0
(c)
(c)
0
(c)
(c)
(c)
0
(c)
0
(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
201
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
MOVW A,0F9A0H
A
×× ××
CCR
49 01
×××××
A
49 01
CCR
T N Z V C
Memory
A E
8 6
×
1 0
F9A1
F9A0
××
T N Z V C
Memory
Before execution
202
AE 86
A E
8 6
F9A1
F9A0
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.76
MOVW (Move Word Data from Accumulator to
Destination)
Transfer the low-order word data of the accumulator (A) to the first operand.
■ MOVW (Move Word Data from Accumulator to Destination)
● Assembler format:
MOVW @RLi+disp8,A
MOVW addr16,A
MOVW SP,A
MOVW RWi,A
MOVW io,A
MOVW dir,A
MOVW @RWi+disp8,A
MOVW ear,A
MOVW eam,A
● Operation:
(First operand) ← (A)
(Word transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
dir
@RLi+8
ad16
SP
io
@RWi+8
RWi
ear
eam
Number of bytes
2
3
3
1
2
2
1
2
2+
Number of cycles
3
10
4
1
3
5
2
2
3+(a)
Correction value
(c)
(c)
(c)
0
(c)
(c)
0
0
(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
203
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
MOVW RW0,A
A
×× ××
RW0
CCR
00 00
×× ××
×××××
T N Z V C
Before execution
204
A
×× ××
RW0
CCR
00 00
00 00
×
0 1
××
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.77
MOVW (Move Immediate Word Data to Destination)
This instruction transfers the 16-bit immediate data to the first operand.
When the first operand is @PC + disp16, the transfer destination address is the address
where the machine instruction of the MOVW instruction is stored + 4 + disp16. Note
that this is not the address where the machine instruction of the instruction subsequent
to the MOVW instruction is stored+disp16.
■ MOVW (Move Immediate Word Data to Destination)
● Assembler format:
MOVW ear,#imm16
MOVW eam,#imm16
● Operation:
(First operand) ← #imm16
● CCR:
If the data is transferred to a generalpurpose register (RW0 to RW7)
If the data is transferred to a register
other than the general-purpose registers
(RW0 to RW7)
I
S
T
N
Z
V
C
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
–
–
–
–
–
–
–
I, S, and T:
Unchanged
N:
Unchanged if the data is transferred to a register other than the general-purpose registers.
If the data is transferred to the general-purpose register, N is set when the MSB of the
transferred data is "1", cleared otherwise.
Z:
Unchanged if the data is transferred to a register other than the general-purpose registers.
If the data is transferred to the general-purpose register, Z is set when the transferred data
is "0", cleared otherwise.
V and C:
Unchanged and none of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
First operand
ear
eam
Number of bytes
4
4+
Number of cycles
2
4+(a)
Correction value
0
(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
205
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
MOVW RW0,#2343H
CCR
×××××
CCR
T N Z V C
RW0
×× ××
Before execution
206
RW0
×
0 0
××
T N Z V C
23 43
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.78
MOVW (Move Word Data from Source to Destination)
Transfer the word data specified by the second operand to the first operand.
■ MOVW (Move Word Data from Source to Destination)
● Assembler format:
MOVW RWi,#imm16
MOVW ear,RWi
MOVW eam,RWi
MOVW RWi,ear
MOVW RWi,eam
● Operation:
(First operand) ← (Second operand)
(Word transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
RWi
RWi
RWi
ear
eam
Second operand
#i16
ear
eam
RWi
RWi
Number of bytes
3
2
2+
2
2+
Number of cycles
2
4
5+(a)
3
4+(a)
Correction value
0
0
(c)
0
(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
207
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
MOVW RW1,RW0
A
×× ××
×× ××
×× ××
×× ××
RW0
00 4A
RW0
00 4A
RW1
×× ××
RW1
00 4A
CCR
×××××
T N Z V C
Before execution
208
A
CCR
×
0 0
××
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.79
MOVW (Move Immediate Word Data to io)
Transfer 16-bit immediate data to the I/O area specified by the first operand.
■ MOVW (Move Immediate Word Data to io)
● Assembler format:
MOVW io,#imm16
● Operation:
(First operand) ← imm16
(Word transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
4
Number of cycles:
5
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
● Example:
MOVW 24H,#2343H
CCR
×××××
CCR
T N Z V C
×
×
×
×
T N Z V C
Memory
Memory
×
×
×
×
×××××
× ×
000025
000024
Before execution
2 3
4 3
000025
000024
× ×
After execution
209
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.80
MOVW (Move Word Data from AH to Memory)
Transfer the word data of AH to the memory location specified by the contents of AL.
■ MOVW (Move Word Data from AH to Memory)
● Assembler format:
MOVW @AL,AH
● Operation:
((AL)) ← (AH)
(Word transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
3
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
● Example:
MOVW @AL,AH
A
00 CB
CCR
FE FF
×××××
A
00 CB
CCR
T N Z V C
Memory
7 1
×
1 0
FEFF
××
T N Z V C
Memory
Before execution
210
FE FF
C B
FEFF
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.81
MOVX (Move Byte Data with Sign Extension from Source
to Accumulator)
Transfer the values of bits 0 to 15 for the accumulator (A) to bits 16 to 31. Then, the
value resulting from sign-extending the second operand is transferred to bits 0 to 15 of
A. If the second operand is @A, transfer to bits 16 to 31 is not performed.
■ MOVX (Move Byte Data with Sign Extension from Source to Accumulator)
● Assembler format:
MOVX A,#imm8
MOVX A,@RWi+disp8
MOVX A,@A
MOVX A,addr16
MOVX A,@RLi+disp8
MOVX A,Ri
MOVX A,dir
MOVX A,io
MOVX A,ear
MOVX A,eam
● Operation:
(A) ← (Second operand)
(Byte transfer with sign extension)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
–
I, S, and T:
Unchanged
N:
Set when the MSB of the transferred data is "1", cleared otherwise.
Z:
Set when the transferred data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Second operand
#im8
@A
@RLi+8
dir
io
@RWi+8
ad16
Ri
ear
eam
Number of bytes
2
2
3
2
2
2
3
2
2
2+
Number of cycles
2
3
10
3
3
5
4
2
2
3+(a)
Correction value
0
(b)
(b)
(b)
(b)
(b)
(b)
0
0
(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
211
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
MOVX A,0E001H
A
×× ××
CCR
A0 46
×××××
A
A0 46
CCR
T N Z V C
Memory
8 6
×
1 0
E001
××
T N Z V C
Memory
Before execution
212
FF 86
8 6
E001
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.82
MUL (Multiply Byte Data of Accumulator)
This instruction multiplies the low-order byte data of AH by that of AL as signed binary
numbers, then returns the result to AL of the accumulator (A).
■ MUL (Multiply Byte Data of Accumulator)
● Assembler format:
MUL A
● Operation:
word (A) ← byte (AH)×byte (AL)
(Byte multiplication)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
3 if byte (AH) is equal to "0"; 12 if byte (AH) is not equal to "0" and the result is
positive; 13 if the result is negative.
Correction value:
0
● Example:
MUL A
A
AH
AL
00 FA
00 11
CCR
×××××
T N Z V C
Before execution
A
AH
AL
00 FA
FF 9A
CCR
×××××
T N Z V C
After execution
213
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.83
MUL (Multiply Byte Data of Accumulator and Effective
Address)
Multiply the byte data of the accumulator (A) by the byte data specified by the second
operand as signed binary numbers and restore the result in bits 0 to 15 of A.
■ MUL (Multiply Byte Data of Accumulator and Effective Address)
● Assembler format:
MUL A,ear
MUL A,eam
● Operation:
word (A) ← byte (A) × byte (ea)
(Byte multiplication)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
*1
*2
Correction value
0
(b)
*1: 4 if byte (ear) is equal to "0"; 13 if byte (ear) is not equal to"0" and the result is positive; 14 if the result is negative.
*2: 5 + (a) if byte (eam) is equal to "0"; 14 + (a) if byte (eam) is not equal to "0" and the result is positive; 15 + (a) if the
result is negative.
For the explanation of (b) in the table and (a) in *2, see Table 8.4-1 and Table 8.4-2 .
● Example:
MUL A,R7
A
AH
AL
×× ××
00 85
R7
CCR
T N Z V C
214
AL
×× ××
2B B9
A5
×××××
Before execution
A
AH
R7
CCR
A5
×××××
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.84
MULW (Multiply Word Data of Accumulator)
Multiply the word data of AH by the word data specified by AL as signed binary numbers
and restore the result in the accumulator as long word data.
■ MULW (Multiply Word Data of Accumulator)
● Assembler format:
MULW A
● Operation:
Long (A) ← word (AH)×word (AL)
(Word multiplication)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
3 if word (AH) is equal to "0"; 16 if word (AH) is not equal to "0" and the result is
positive; 19 if the result is negative.
Correction value:
0
● Example:
MULW A
A
AH
AL
AD 01
05 ED
CCR
×××××
T N Z V C
Before execution
A
AH
AL
FE 14
2E ED
CCR
×××××
T N Z V C
After execution
215
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.85
MULW (Multiply Word Data of Accumulator and Effective
Address)
Multiply the word data of the accumulator (A) by the word data specified by the second
operand as signed binary numbers and restore the result in A as long word data.
■ MULW (Multiply Word Data of Accumulator and Effective Address)
● Assembler format:
MULW A,ear
MULW A,eam
● Operation:
Long (A) ← word (A)×word (Second operand)
(Word multiplication)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
*1
*2
Correction value
0
(b)
*1: 4 if Word (ear) is equal to "0"; 17 if Word (ear) is not equal to "0" and the result is positive; 20 if the result is
negative.
*2: 5 + (a) if Word (eam) is equal to "0"; 18 + (a) if Word (eam) is not equal to "0" and the result is positive; 21 + (a) if
the result is negative.
For the explanation of (b) in the table and (a) in *2, see Table 8.4-1 and Table 8.4-2 .
● Example:
MULW A,RW5
A
AH
AL
×× ××
83 42
RW5
CCR
43 14
×××××
T N Z V C
Before execution
216
A
AH
AL
DF 50
87 28
RW5
CCR
43 14
×××××
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.86
MULU (Multiply Unsigned Byte Data of Accumulator)
Multiply the low-order byte data of AH by the low-order byte data of AL as unsigned
binary numbers and restore the result in the AL of the accumulator (A).
■ MULU (Multiply Unsigned Byte Data of Accumulator)
● Assembler format:
MULU A
● Operation:
word (A) ← byte (AH)×byte (AL)
(Byte multiplication)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
3 if byte (AH) is equal to "0"; 7 if byte (AH) is not equal to "0".
Correction value:
0
● Example:
MULU A
A
00 FA
CCR
00 11
×××××
T N Z V C
Before execution
A
00 FA
CCR
10 9A
×××××
T N Z V C
After execution
217
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.87
MULU (Multiply Unsigned Byte Data of Accumulator and
Effective Address)
Multiply the byte data of the accumulator (A) by the byte data specified by the second
operand as unsigned binary numbers and restore the result in bits 0 to 15 of A.
■ MULU (Multiply Unsigned Byte Data of Accumulator and Effective Address)
● Assembler format:
MULU A, ear
MULU A, eam
● Operation:
word (A) ← byte (A) × byte (Second operand)
(Byte multiplication)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
*1
*2
Correction value
0
(b)
*1: 4 if byte (ear) is equal to "0"; 8 if byte (ear) is not equal to "0".
*2: 5 + (a) if byte (eam) is equal to "0"; 9 + (a) if not equal to "0".
For the explanation of (b) in the table and (a) in *2, see Table 8.4-1 and Table 8.4-2 .
● Example:
MULU A, R7
A
×× ××
00 85
R7
CCR
T N Z V C
218
×× ××
A5
×××××
Before execution
A
55 B9
R7
CCR
A5
×××××
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.88
MULUW (Multiply Unsigned Word Data of Accumulator)
Multiply the word data of AH by the word data of AL as unsigned binary numbers and
restore the result in the accumulator (A) as long word data.
■ MULUW (Multiply Unsigned Word Data of Accumulator)
● Assembler format:
MULUW A
● Operation:
Long (A) ← word (AH)×word (AL)
(Word multiplication)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
3 if word (AH) is equal to "0"; 11 if word (AH) is not equal to "0".
Correction value:
0
● Example:
MULUW A
A
AD 01
CCR
05 ED
×××××
T N Z V C
Before execution
A
04 01
CCR
2E ED
×××××
T N Z V C
After execution
219
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.89
MULUW (Multiply Unsigned Word Data of Accumulator
and Effective Address)
Multiply the word data of the accumulator (A) by the word data specified by the second
operand as unsigned binary numbers and restore the result in A as long word data.
■ MULUW (Multiply Unsigned Word Data of Accumulator and Effective Address)
● Assembler format:
MULUW A, ear
MULUW A, eam
● Operation:
Long (A) ← word (A)×word (Second operand)
(Word multiplication)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
*1
*2
Correction value
0
(c)
*1: 4 if Word (ear) is equal to "0"; 12 if Word (ear) is not equal to "0".
*2: 5 + (a) if Word (eam) is "0"; 13 + (a) if Word (eam) is not equal to "0".
For the explanation of (c) in the table and (a) in *2, see Table 8.4-1 and Table 8.4-2 .
● Example:
MULUW A, RW5
A
RW5
×× ××
43 14
83 42
CCR
×××××
T N Z V C
Before execution
220
A
RW5
22 64
43 14
87 28
CCR
×××××
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.90
NEG (Negate Byte Data of Destination)
Take the 2's complement of the byte data specified by the operand and restore the
result in the operand. If the operand is the accumulator (A), the value resulting from
sign-extending the operation result is transferred to bits 8 to 15 of A.
■ NEG (Negate Byte Data of Destination)
● Assembler format:
NEG A
NEG ear
NEG eam
● Operation:
(Operand) ← 0–(Operand)
(Byte operation)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Operand
A
ear
eam
Number of bytes
1
2
2+
Number of cycles
2
3
5+(a)
Correction value
0
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
NEG R0
R0
CCR
59
×××××
T N Z V C
Before execution
R0
CCR
×
A7
1 0 0 1
T N Z V C
After execution
221
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.91
NEGW (Negate Word Data of Destination)
Take the 2's complement of the word data specified by the operand and restore the
result in the operand.
■ NEGW (Negate Word Data of Destination)
● Assembler format:
NEGW A
NEGW ear
NEGW eam
● Operation:
(Operand) ← 0–(Operand)
(Word operation)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Operand
A
ear
eam
Number of bytes
1
2
2+
Number of cycles
2
3
5+(a)
Correction value
0
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
NEGW A
A
×× ××
CCR
AB 98
×××××
T N Z V C
Before execution
222
A
×× ××
CCR
54 68
×
0 0 0 1
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.92
NOP (No Operation)
Perform no operation.
■ NOP (No Operation)
● Assembler format:
NOP
● Operation:
No operation is performed.
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
1
Correction value:
0
● Example:
NOP
A
×× ××
×× ××
PC
CCR
×× ××
A
F0 00
PC
×××××
CCR
T N Z V C
× ×
0 0
F0 01
×××××
T N Z V C
Memory
Memory
PC
×× ××
F001
F000
Before execution
PC
× ×
0 0
F001
F000
After execution
223
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.93
NOT (Not Byte Data of Destination)
Take the logical NOT of the byte data specified by the operand and restore the result in
the operand.
■ NOT (Not Byte Data of Destination)
● Assembler format:
NOT A
NOT ear
NOT eam
● Operation:
(Operand) ← not (Operand)
(Byte logical NOT)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
A
ear
eam
Number of bytes
1
2
2+
Number of cycles
2
3
5+(a)
Correction value
0
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
224
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
NOT 0071H
A
×× ××
CCR
×× ××
×××××
A
×× ××
CCR
T N Z V C
×
0 1 0
×
T N Z V C
Memory
Memory
F F
×× ××
0071
Before execution
0 0
0071
After execution
225
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.94
NOTW (Not Word Data of Destination)
Take the logical NOT of the word data specified by the operand and restore the result in
the operand.
■ NOTW (Not Word Data of Destination)
● Assembler format:
NOTW A
NOTW ear
NOTW eam
● Operation:
(Operand) ← not (Operand)
(Word logical NOT)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Operand
A
ear
eam
Number of bytes
1
2
2+
Number of cycles
2
3
5+(a)
Correction value
0
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
● Example:
NOTW RW3
RW3
CCR
25 8B
×××××
T N Z V C
Before execution
226
RW3
CCR
DA 74
×
1 0 0
×
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.95
NRML (NORMALIZE Long Word)
Shift the long word data of the accumulator (A) to the left until the most significant bit of
A becomes "1", if the long word data is not "0". R0 is set to the number of shifts
required and the zero flag (Z) is cleared.
If the long word data of the accumulator (A) is "0", R0 is set to "0" and the zero flag (Z)
is set.
■ NRML (NORMALIZE Long Word)
● Assembler format:
NRML A,R0
● Operation:
If A≠0:
The long word data is shifted to the left until the most significant bit of A becomes 1.
(R0) ← Number of shifts required, Z ← 0
If A=0:
(R0) ← 0, Z ← 1
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
*
–
–
I, S, T, and N:
Unchanged
Z:
Set when A is equal to "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
4 when the accumulator is equal to "0"; otherwise, 6 + (Number of shifts required)
Correction value:
0
● Example:
NRML A,R0
A
00 00
83 61
R0
CCR
83 61
34
×××××
T N Z V C
Before execution
A
00 00
R0
CCR
××
10
0
××
T N Z V C
After execution
227
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.96
OR (Or Byte Data of Destination and Source to
Destination)
Take the logical OR of the byte data specified by the first operand and the byte data
specified by the second operand and restore the result in the first operand.
■ OR (Or Byte Data of Destination and Source to Destination)
● Assembler format:
OR A,#imm8
OR A,ear
OR A,eam
OR ear,A
OR eam,A
● Operation:
(First operand) ← (First operand) or (Second operand)
(Byte logical OR)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#im8
ear
eam
A
A
Number of bytes
2
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(b)
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
228
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
OR 0052H,A
A
×× ××
CCR
00 37
×××××
A
×× ××
CCR
T N Z V C
Memory
F A
00 37
×
1 0 0
×
T N Z V C
Memory
0052
Before execution
F F
0052
After execution
229
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.97
OR (Or Byte Data of Immediate Data and Condition Code
Register to Condition Code Register)
Take the logical OR of the byte data in the condition code register (CCR) and specified
8-bit immediate data and restore the result in the condition code register (CCR).
Bit 7 of the immediate data is ignored because the condition code register (CCR) is 7
bits long.
■ OR (Or Byte Data of Immediate Data and Condition Code Register to Condition Code
Register)
● Assembler format:
OR CCR,#imm8
● Operation:
(CCR) ← (CCR) or #imm8
(Byte logical OR)
● CCR:
I
S
T
N
Z
V
C
*
*
*
*
*
*
*
I: Stores bit 6 of the operation result.
S: Stores bit 5 of the operation result.
T: Stores bit 4 of the operation result.
N: Stores bit 3 of the operation result.
Z: Stores bit 2 of the operation result.
V: Stores bit 1 of the operation result.
C: Stores bit 0 of the operation result.
● Number of bytes, Number of cycles, and Correction value:
230
Number of bytes:
2
Number of cycles:
3
Correction value:
0
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
OR CCR,#57H
A
CCR
×× ××
I
0
S
1
T
1
×× ××
N
0
Z
1
V
0
C
1
A
CCR
×× ××
I
1
S
1
T
1
ILM2 ILM1 ILM0
× × ×
ILM
MSB
RP
N
0
Z
1
V
1
C
1
ILM2 ILM1 ILM0
× × ×
ILM
LSB
× × × × ×
Before execution
×× ××
MSB
RP
LSB
× × × × ×
After execution
231
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.98
ORL (Or Long Word Data of Destination and Source to
Destination)
Take the logical OR of the long word data for the accumulator (A) and that specified by
the second operand and restore the result in A.
■ ORL (Or Long Word Data of Destination and Source to Destination)
● Assembler format:
ORL A,ear
ORL A,eam
● Operation:
(A) ← (A) or (Second operand)
(Long word logical OR)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
6
7+(a)
Correction value
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
232
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
ORL A,0FFF0H
A
72 5D
F0 5C
CCR
A
FF 5D
×××××
FA 5C
CCR
T N Z V C
Memory
F
5
A
0
F
5
A
0
×
1 0 0
×
T N Z V C
Memory
FFF3
FFF2
FFF1
FFF0
Before execution
F
5
A
0
F
5
A
0
FFF3
FFF2
FFF1
FFF0
After execution
233
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.99
ORW (Or Word Data of AH and AL to AL)
Take the logical OR of the word data for AH and that for AL and restore the result in AL.
■ ORW (Or Word Data of AH and AL to AL)
● Assembler format:
ORW A
● Operation:
(AL) ← (AH) or (AL)
(Word logical OR)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
ORW A
A
04 26
CCR
AB 98
×××××
T N Z V C
Before execution
234
A
04 26
CCR
AF BE
×
1 0 0
×
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.100
ORW (Or Word Data of Destination and Source to
Destination)
Take the logical OR of the word data specified by the first operand and the word data
specified by the second operand and restore the result in the first operand.
■ ORW (Or Word Data of Destination and Source to Destination)
● Assembler format:
ORW A,#imm16
ORW A,ear
ORW A,eam
ORW ear,A
ORW eam,A
● Operation:
(First operand) ← (First operand) or (Second operand)
(Word logical OR)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#i16
ear
eam
A
A
Number of bytes
3
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(c)
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
235
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
ORW 0E001H,A
A
×× ××
CCR
59 63
×××××
A
×× ××
CCR
T N Z V C
E002
E001
Before execution
236
×
1 0 0
×
T N Z V C
Memory
Memory
8 3
4 2
59 63
D B
6 3
E002
E001
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.101
POPW (Pop Word Data of Accumulator from Stack
Memory)
Transfer the values of bits 0 to 15 for the accumulator (A) to bits 16 to 31. Then, the
word data of the memory location pointed to by the stack pointer (SP) is transferred to
bits 0 to 15 of A. After the data is transferred, 0002H is word-added to the value of SP
(word data).
■ POPW (Pop Word Data of Accumulator from Stack Memory)
● Assembler format:
POPW A
● Operation:
(A) ← ((SP))
(Word transfer)
(SP) ← (SP)+2
(Word addition)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
3
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
237
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
POPW A
A
04 22
16 35
SP
01 20
CCR
A
×××××
16 35
10 AC
SP
01 22
CCR
T N Z V C
T N Z V C
Memory
SP
1 0
A C
Memory
0122
0121
0120
Before execution
238
×××××
SP
1 0
A C
0122
0121
0120
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.102
POPW (Pop Word Data of AH from Stack Memory)
Transfer word data from the memory location pointed to by the stack pointer (SP) to AH.
Then, 0002H is word-added to the value of SP (word data).
■ POPW (Pop Word Data of AH from Stack Memory)
● Assembler format:
POPW AH
● Operation:
(AH) ← ((SP))
(Word transfer)
(SP) ← (SP)+2
(Word addition)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
3
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
● Example:
POPW AH
A
04 22
SP
CCR
16 35
A
01 20
43 14
SP
×××××
CCR
T N Z V C
4 3
1 4
01 22
×××××
T N Z V C
Memory
SP
16 35
Memory
0122
0121
0120
Before execution
SP
4 3
1 4
0122
0121
0120
After execution
239
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.103
POPW (Pop Word Data of Program Status from Stack
Memory)
Transfer word data from the memory location pointed to by the stack pointer (SP) to the
processor status (PS). Bit 7 of the word data is ignored. Then, 0002H is word-added to
the value of SP (word data).
■ POPW (Pop Word Data of Program Status from Stack Memory)
● Assembler format:
POPW PS
● Operation:
(PS) ← ((SP))
(Word transfer)
(SP) ← (SP)+2
(Word addition)
● CCR:
I
S
T
N
Z
V
C
*
*
*
*
*
*
*
The values of the corresponding bits for the stack memory are transferred.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
4
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
240
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
POPW PS
SP
I
CCR
S
T
N
Z
V
SP
C
× × × × × × ×
MSB
ILM2 ILM1 ILM0
ILM
01 20
× × ×
RP
CCR
LSB
× × × × ×
SP
S
0
ILM2 ILM1 ILM0
ILM
0
Memory
4 3
1 4
I
0
1
0
01 22
T
1
N Z V C
0 1 0 0
MSB
LSB
RP 0 0 0 1 1
Memory
0122
0121
0120
Before execution
SP
4 3
1 4
0122
0121
0120
After execution
241
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.104
POPW (Pop Registers from Stack Memory)
Transfer the data pointed to by the stack pointer (SP) to the multiple general-purpose
word registers specified by the register list (rlst).
In assembler representation, register names are enumerated as a register list. After
assembly, the register list turns into byte data.
■ POPW (Pop Registers from Stack Memory)
● Assembler format:
POPW rlst
● Operation:
(RWx) ← ((SP))
(Word transfer)
(SP) ← (SP)+2
(Word addition)
The above operation is repeated for all the registers specified by rlst.
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
7 + 3 × (Number of transfers) + 2 × (Largest number in the transferred registers)
7 if rlst=0
Correction value:
(Number of transfers)×(c)
For the explanation of (c), see Table 8.4-2 .
242
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
POPW (RW0,RW4)
SP
34 FA
××
××
××
××
××
××
××
××
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Memory
SP
0
0
0
0
4
3
2
1
SP
××
××
××
××
××
××
××
××
34FE
34FD
34FC
34FB
34FA
Before execution
34 FE
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
SP
02
01
××
××
××
××
××
××
04
03
××
××
××
××
××
××
Memory
0
0
0
0
4
3
2
1
34FE
34FD
34FC
34FB
34FA
After execution
243
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.105
PUSHW (Push Word Data of Inherent Register to Stack
Memory)
Decrement the value of the stack pointer (SP) by two words and transfer the word data
of the register to the memory location pointed to by the resulting SP value.
■ PUSHW (Push Word Data of Inherent Register to Stack Memory)
● Assembler format:
PUSHW A
PUSHW AH
PUSHW PS
● Operation:
(SP) ← (SP)–2
(Word subtraction)
((SP)) ← (Operand)
(Word transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
A
AH
PS
Number of bytes
1
1
1
Number of cycles
4
4
4
Correction value
(c)
(c)
(c)
For the explanation of (c) in the table, see Table 8.4-2 .
244
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
PUSHW A
A
45 A4
A
45 A4
SP
01 22
SP
01 20
CCR
×××××
CCR
T N Z V C
T N Z V C
Memory
SP
× ×
× ×
×××××
Memory
0122
0121
0120
Before execution
SP
4 5
A 4
0122
0121
0120
After execution
245
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.106
PUSHW (Push Registers to Stack Memory)
Transfer the contents of the multiple general-purpose word registers specified by the
register list (rlst) to the memory location pointed to by the stack pointer (SP).
In assembler representation, register names are enumerated as a register list. After
assembly, the register list turns into byte data.
■ PUSHW (Push Registers to Stack Memory)
● Assembler format:
PUSHW rlst
● Operation:
(SP) ← (SP)–2
(Word subtraction)
((SP))← (RWx)
(Word transfer)
The above operation is repeated for all the registers specified by rlst.
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
29 + 3 × (Number of transfers) – 3 × (8 – Smallest number of the transferred registers)
8 if rlst = 0
Correction value:
(Number of transfers)×(c)
For the explanation of (c), see Table 8.4-2 .
246
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
PUSHW (RW1,RW3)
SP
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
SP
34 FE
×× ××
3 5
A 4
×× ××
6 D
F 0
×
×
×
×
×
×
×
×
×
×
×
×
Memory
×
×
×
×
×
×
×
×
×
×
×
×
34FE
34FD
34FC
34FB
34FA
Before execution
SP
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
34 FA
×× ××
3 5
×× ××
6 D
F 0
×
×
×
×
×
×
×
×
×
×
×
×
Memory
SP
A 4
6
F
3
A
D
0
5
4
×
×
×
×
34FE
34FD
34FC
34FB
34FA
After execution
247
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.107
RET (Return from Subroutine)
Cause a branch to the address pointed to by the stack pointer (SP). If this instruction is
used in combination with a subroutine call instruction (CALL, CALLV), control returns to
the instruction following the subroutine call instruction after the branch operation is
completed.
■ RET (Return from Subroutine)
● Assembler format:
RET
● Operation:
(PC) ← ((SP))
(Word transfer)
(SP) ← (SP)+2
(Word addition)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
4
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
● Example:
RET
SP
00 62
SP
00 64
PC
F0 02
PC
FC 22
Memory
SP
F C
2 2
Memory
0064
0063
0062
Before execution
248
SP
F C
2 2
After execution
0064
0063
0062
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.108
RETI (Return from Interrupt)
This instruction returns the data in the memory that is indicated by (SSP) to PS to
detect interrupt requests performed using IF or ILM.
When the next interrupt request is received, the procedure branches to the detected
interruption vector. If no next interrupt is received, the procedure will return from the
interruption process.
■ RETI (Return from Interrupt)
● Assembler format:
RETI
● Operation:
(1)
If the next interrupt is accepted
(PS)
←
((SSP))
(S)
←
1, (PCB), (PC) ← Interrupt vector address
(ILM)
←
Accepted interrupt level
DTB, PCB, DPR, ADB, AL, and AH are not restored.
(2)
If control is returned from the next interrupt
(PS)
←
((SSP)), (SSP)
←
(SSP)+2;
(PC)
←
((SSP)), (SSP)
←
(SSP)+2;
(DTB),(PCB)
←
((SSP)), (SSP)
←
(SSP)+2;
(DPR),(ADB)
←
((SSP)), (SSP)
←
(SSP)+2;
(AL)
←
((SSP)), (SSP)
←
(SSP)+2;
(AH)
←
((SSP)), (SSP)
←
(SSP)+2
● CCR
(1) If the next interrupt is accepted
(2) If control is returned from the next interrupt
I
S
T
N
Z
V
C
I
S
T
N
Z
V
C
*
S
*
*
*
*
*
*
*
*
*
*
*
*
I: Restored to the saved I value.
I:
Restored to the saved I value.
S: Set
S: Restored to the saved S value.
T: Restored to the saved T value.
T: Restored to the saved T value.
N: Restored to the saved N value.
N: Restored to the saved N value.
Z: Restored to the saved Z value.
Z: Restored to the saved Z value.
V: Restored to the saved V value.
V: Restored to the saved V value.
C: Restored to the saved C value.
C: Restored to the saved C value.
249
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
15 if the next interrupt is accepted; 17 if control is returned from the next interrupt
Correction value:
3 × (b) + 2 × (c) if the next interrupt is accepted; 6 × (c) if control is returned from the
next interrupt
For the explanation of (b) and (c), see Table 8.4-2 .
● Example:
RETI (if control is returned from the interrupt)
A
A
××××
DTB
××××
FFFE
PCB
PC
×× ××
××
××
DPR
ADB
××
××
CCR
ILM
RP
I S T N Z V C
××
××
× ×× × × × ×
SSB
03
DTB
99
DPR
BB
ILM
03
SSP
7F F4
SSP
F
E
D
C
B
A
9
8
7
6
1
0
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
Before execution
250
PCB
88
ADB
AA
RP
01
SSB
03
PC
77 66
CCR
I S T N Z V C
0 0 0 0 0 0 0
SSP
80 00
Memory
Memory
F
E
D
C
B
A
9
8
7
6
6
8
DDCC
SSP
F
E
D
C
B
A
9
8
7
6
6
8
F
E
D
C
B
A
9
8
7
6
1
0
After execution
038000
037FFF
037FFE
037FFD
037FFC
037FFB
037FFA
037FF9
037FF8
037FF7
037FF6
037FF5
037FF4
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.109
RETP (Return from Physical Address)
Cause a branch to the physical address pointed to by the stack pointer (SP). If this
instruction is used in combination with the CALLP instruction, control returns to the
instruction following the CALLP instruction after the branch operation is completed.
■ RETP (Return from Physical Address)
● Assembler format:
RETP
● Operation:
(PC) ← ((SP)), (SP) ← (SP)+2
(Word addition)
(PCB) ← ((SP)) (Byte transfer), (SP) ← (SP)+2
(Word addition)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
6
Correction value:
(d)
For the explanation of (d), see Table 8.4-2 .
251
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
RETP
PC
22 FC
PCB
CCR
SP
F8 FC
08
×
USB
0
PC
43 45
15
SP
PCB
×××××
AD
×
CCR
I S T N Z V C
SP
0
A
4
4
0
D
3
5
0
15F900
15F8FF
15F8FE
15F8FD
15F8FC
15
×××××
Memory
Before execution
252
USB
I S T N Z V C
Memory
× ×
F9 00
SP
× ×
0
A
4
4
0
D
3
5
15F900
15F8FF
15F8FE
15F8FD
15F8FC
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.110
ROLC (Rotate Byte Data of Accumulator with Carry to
Left)
Rotate or shift the byte data specified by the operand to the left by one bit, including the
carry bit (C). The most significant bit of the operand is placed in the carry bit (c).
■ ROLC (Rotate Byte Data of Accumulator with Carry to Left)
● Assembler format:
ROLC A
ROLC ear
ROLC eam
● Operation:
MSB
A or operand
LSB
C
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T:
Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is "0", cleared otherwise.
V:
Unchanged
C:
Stores the bit shifted out from the MSB of A.
● Number of bytes, Number of cycles, and Correction value:
Operand
A
ear
eam
Number of bytes
2
2
2+
Number of cycles
2
3
5+(a)
Correction value
0
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
253
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
ROLC A
A
×× ××
CCR
××
32
××××
A
0
T N Z V C
Before execution
254
×× ××
CCR
××
×
64
0 0
×
0
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.111
RORC (Rotate Byte Data of Accumulator with Carry to
Right)
Rotate or shift the byte data specified by the operand to the right by one bit, including
the carry bit (C). The least significant bit of the operand is placed in the carry bit (c).
■ RORC (Rotate Byte Data of Accumulator with Carry to Right)
● Assembler format:
RORC A
RORC ear
RORC eam
● Operation:
MSB
A or operand
LSB
C
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
–
*
I, S, and T:
Unchanged
N:
Set when the MSB of the shifting result is "1", cleared otherwise.
Z:
Set when the shifting result is "0", cleared otherwise.
V:
Unchanged
C:
Stores the bit shifted out from the LSB of A.
● Number of bytes, Number of cycles, and Correction value:
Operand
A
ear
eam
Number of bytes
2
2
2+
Number of cycles
2
3
5+(a)
Correction value
0
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
255
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
RORC A
A
×× ××
××
32
××××
0
T N Z V C
Before execution
CCR
256
A
×× ××
CCR
××
×
19
0 0 ×0
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.112
SBBS (Set Bit and Branch if Bit Set)
Cause a branch if the bit data specified by the first operand is "1". Control is
transferred to the address resulting from word-adding the value resulting from signextending the second operand to the address of the instruction following the SBBS
instruction.
After the instruction has been executed, the bit specified by the first operand is set to
"1".
■ SBBS (Set Bit and Branch if Bit Set)
● Assembler format:
SBBS addr16:bp,rel
● Operation:
If the condition is satisfied:
(PC) ← (PC)+<Number of bytes>+rel (Word addition), (addr16:bp) ← 1
If the condition is not satisfied:
(PC) ← (PC)+<Number of bytes> (Word addition), (addr16:bp) ← 1
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
*
–
–
I, S, T, and N:
Unchanged
Z:
Set when the bit data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
5
Number of cycles:
9 if the condition is not satisfied; 10 if the condition is satisfied
Correction value:
2×(b)
For the explanation of (b), see Table 8.4-2 .
257
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
SBBS 1234H:5,20H
PC
E1 00
E1 25
Memory
Memory
× ×
× ×
7 F
258
PC
1234
7 F
1234
× ×
× ×
Before execution
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.113
SCEQ (Scan String Byte Until Equal)
Compare the byte data specified by AH in the space specified by <bank> with the data
of AL. The address is incremented/decremented and RW0 is decremented until the byte
data matches the data or RW0 becomes equal to "0".
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. By
default, DTB is assumed. The address can be either incremented or decremented. By
default, the address is incremented.
If RW0 is equal to "0", comparison is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended to handle the
interrupt. After the interrupt has been handled, the execution of the instruction is
resumed.
■ SCEQ (Scan String Byte Until Equal)
● Assembler format:
SCEQ [<bank>] SCEQI [<bank>] (When the address is incremented)
SCEQD [<bank>] (When the address is decremented)
● Operation:
The following operation is repeated until RW0 = 0 or ((AH)) = (AL)
(Byte comparison):
(AH) ← (AH)±1
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Unchanged if the initial value of RW0 is "0". If the initial value of RW0 is not "0", N
is set when the MSB of the last compare operation result is "1", cleared otherwise.
Z:
Unchanged if the initial value of RW0 is "0". If the initial value of RW0 is not "0", Z
is set when a match with the contents of AL is found; cleared when the instruction
terminates with RW0 being set to "0".
V:
Unchanged if the initial value of RW0 is "0". If the initial value of RW0 is not "0", V
is set when an overflow has occurred as a result of the last compare operation; cleared
otherwise.
C:
Unchanged if the initial value of RW0 is "0". If the initial value of RW0 is not "0", V
is set when a borrow has occurred as a result of the last compare operation; cleared
otherwise.
259
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
5 when RW0 is "0", 4 + 7 × (RW0) when count-out is detected, and 7n + 5 when the
data in the AL register matches the byte data specified by the AH register in the space
that is specified by bank
Correction value:
(Number of times the operation was repeated)×(b)
For the explanation of (b), see Table 8.4-2 .
● Example:
SCEQ
AH
15 80
RW0
AH
15 86
AL
00 46
01 00
DTB
CCR
03
RW0
AL
00 46
00 FA
×××××
CCR
T N Z V C
Memory
AH
4
4
4
4
4
5
6
8
9
D
E
4
031586
031585
031584
031583
031582
031581
031580
Before execution
260
DTB
03
×××××
T N Z V C
AH
Memory
4
4
4
4
4
5
6
8
9
D
E
4
131586
031585
031584
031583
031582
031581
031580
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.114
SCWEQ (Scan String Word Until Equal)
Compare the word data specified by AH in the space specified by <bank> with the data
of AL. The address is incremented/decremented and RW0 is decremented until the
word data matches the data or RW0 becomes equal to "0".
Four types of registers PCB, DTB, ADB, and SPB can be specified by <bank>. By
default, DTB is assumed. The address can be either incremented or decremented. By
default, the address is incremented.
If RW0 is equal to "0", comparison is not performed. If an interrupt occurs during the
execution of the instruction, the execution of the instruction is suspended to handle the
interrupt. After the interrupt has been handled, the execution of the instruction is
resumed.
■ SCWEQ (Scan String Word until Equal)
● Assembler format:
SCWEQ [<bank>] SCWEQI [<bank>] (When the address is incremented)
SCWEQD [<bank>] (When the address is decremented)
● Operation:
The following operation is repeated until RW0 = 0 or ((AH)) = (AL)
(Word comparison):
(AH) ← (AH)±2
(RW0) ← (RW0)–1
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Unchanged if the initial value of RW0 is "0". If the initial value of RW0 is not "0", N
is set when the MSB of the last compare operation result is "1", cleared otherwise.
Z:
Unchanged if the initial value of RW0 is "0". If the initial value of RW0 is not "0", Z
is set when a match with the contents of AL is found; cleared when the instruction
terminates with RW0 being set to "0".
V:
Unchanged if the initial value of RW0 is "0". If the initial value of RW0 is not "0", V
is set when an overflow has occurred as a result of the last compare operation; cleared
otherwise.
C:
Unchanged if the initial value of RW0 is "0". If the initial value of RW0 is not "0", V
is set when a borrow has occurred as a result of the last compare operation; cleared
otherwise.
261
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
2
Number of cycles:
5 when RW0 is "0", 4 + 7 × (RW0) when count-out is detected, and 7n + 5 when the
data in the AL register matches the byte data specified by the AH register in the space
that is specified by bank
Correction value:
(Number of times the operation was repeated) × (c)
For the explanation of (c), see Table 8.4-2 .
● Example:
SCWEQ
AH
C0 00
RW0
AH
C0 06
AL
00 FF
00 03
DTB
CCR
DE
RW0
AL
00 FF
00 00
×××××
DTB
CCR
T N Z V C
AH
6
5
4
3
2
1
0
Memory
DEC006
DEC005
DEC004
DEC003
DEC002
DEC001
DEC000
Before execution
262
1 0 0 1
T N Z V C
Memory
E
E
E
E
E
E
E
×
DE
AH
E
E
E
E
E
E
E
6
5
4
3
2
1
0
After execution
DEC006
DEC005
DEC004
DEC003
DEC002
DEC001
DEC000
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.115
SETB (Set Bit)
Set the contents of the bit address specified by the operand to "1".
■ SETB (Set Bit)
● Assembler format:
SETB addr16:bp
SETB dir:bp
SETB io:bp
● Operation:
(Operand) b ← 1
(Bit transfer)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Operand
ad16:bp
dir:bp
io:bp
Number of bytes
4
3
3
Number of cycles
7
7
7
Correction value
2×(b)
2×(b)
2×(b)
For the explanation of (b) in the table, see Table 8.4-2 .
● Example:
SETB 0AA55H:4
CCR
00000
TNZVC
Memory
CCR
× ×
6 F
00000
TNZVC
Memory
× ×
AA55
7 F
AA55
× ×
× ×
Before execution
After execution
263
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.116
SUB (Subtract Byte Data of Source from Destination to
Destination)
Subtract the byte data specified by the second operand from the byte data specified by
the first operand and restore the result in the first operand. If the first operand is A, "0"
is transferred to bits 8 to 15 of A.
■ SUB (Subtract Byte Data of Source from Destination to Destination)
● Assembler format:
SUB A,#imm8
SUB A,dir
SUB A,ear
SUB A,eam
SUB ear,A
SUB eam,A
● Operation:
(First operand) ← (First operand)–(Second operand)
(Byte subtraction)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
A
ear
eam
Second operand
#im8
dir
ear
eam
A
A
Number of bytes
2
2
2
2+
2
2+
Number of cycles
2
5
3
4+(a)
3
5+(a)
Correction value
0
(b)
0
(b)
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
264
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
SUB A,#22H
A
×× ××
CCR
49 01
×××××
T N Z V C
Before execution
A
×× ××
CCR
00 DF
×
1 0 0 1
T N Z V C
After execution
265
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.117
SUBC (Subtract Byte Data of AL from AH with Carry to
AL)
Subtract the low-order byte data of AL and the carry bit (C) from the low-order byte data
of AH and restore the result in AL. "0" is transferred to bits 8 to 15 of the accumulator
(A).
■ SUBC (Subtract Byte Data of AL from AH with Carry to AL)
● Assembler format:
SUBC A
● Operation:
(AL) ← (AH)–(AL)–(C)
(Byte subtraction with a carry)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
SUBC A
A
05 05
CCR
00 D4
×××××
T N Z V C
Before execution
266
A
05 05
CCR
00 30
×
1 0 0 1
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.118
SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
Subtract the byte data specified by the second operand and the carry bit (C) from the
byte data of the accumulator (A) and restore the result in A. "0" is transferred to bits 8
to 15 of A.
■ SUBC (Subtract Byte Data of Effective Address from Accumulator with Carry to
Accumulator)
● Assembler format:
SUBC A,ear
SUBC A,eam
● Operation:
(A) ← (A)–(Second operand)–(C)
(Byte subtraction with a carry)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
4+(a)
Correction value
0
(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
267
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
SUBC A,R1
A
×× ××
00 35
R1
CCR
A
54
××××
0
T N Z V C
Before execution
268
×× ××
00 E1
R1
CCR
×
54
1 0 0 1
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.119
SUBCW (Subtract Word Data of Effective Address from
Accumulator with Carry to Accumulator)
Subtract the word data specified by the second operand and the carry bit (C) from the
low-order word data of the accumulator (A) and restore the result in A.
■ SUBCW (Subtract Word Data of Effective Address from Accumulator with Carry to
Accumulator)
● Assembler format:
SUBCW A,ear
SUBCW A,eam
● Operation:
(A) ← (A)–(Second operand)–(C)
(Word subtraction with a carry)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
3
4+(a)
Correction value
0
(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
269
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
SUBCW A,0E024H
A
×× ××
CCR
75 58
××××
A
1
×× ××
CCR
A 9
5 B
1 0 0 1
Memory
E025
E024
Before execution
270
×
T N Z V C
T N Z V C
Memory
CB FC
A 9
5 B
E025
E024
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.120
SUBDC (Subtract Decimal Data of AL from AH with Carry to
AL)
Subtract the low-order byte data of AL and the carry bit (C) from the low-order byte data
of AH and restore the result in AL. "0" is transferred to bits 8 to 15 of A.
■ SUBDC (Subtract Decimal Data of AL from AH with Carry to AL)
● Assembler format:
SUBDC A
● Operation:
(AL) ← (AH)–(AL)–(C)
(Decimal subtraction with a carry)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Undefined
C:
Set when a borrow has occurred as a result of the decimal operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
3
Correction value:
0
● Example:
SUBDC A
A
××
86
CCR
××
86
××××
A
0
T N Z V C
Before execution
××
86
CCR
00 00
×
0 1 0 0
T N Z V C
After execution
271
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.121
SUBL (Subtract Long Word Data of Source from
Destination to Destination)
Subtract the long word data specified by the second operand from the long word data of
the accumulator (A) and restore the result in A.
■ SUBL (Subtract Long Word Data of Source from Destination to Destination)
● Assembler format:
SUBL A,#imm32
SUBL A,ear
SUBL A,eam
● Operation:
(First operand) ← (First operand)–(Second operand)
(Long word subtraction)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
Second operand
#i32
ear
eam
Number of bytes
5
2
2+
Number of cycles
4
6
7+(a)
Correction value
0
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
272
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
SUBL A,0FD12H
A
34 B3
F2 01
CCR
A
E2 54
×××××
C0 44
CCR
5
5
3
B
2
F
1
D
1 0 0 1
T N Z V C
T N Z V C
Memory
×
Memory
FD16
FD15
FD14
FD13
FD12
Before execution
5
5
3
B
2
F
1
D
FD16
FD15
FD14
FD13
FD12
After execution
273
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.122
SUBW (Subtract Word Data of Source from Destination to
Destination)
Subtract the word data specified by the second operand from the word data specified by
the first operand and restore the result in the first operand.
■ SUBW (Subtract Word Data of Source from Destination to Destination)
● Assembler format:
SUBW A,#imm16
SUBW A,ear
SUBW A,eam
SUBW ear,A
SUBW eam,A
● Operation:
(First operand) ← (First operand)–(Second operand)
(Word subtraction)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#i16
ear
eam
A
A
Number of bytes
3
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(c)
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
274
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
SUBW @RW0+,A
A
×× ××
RW0
CCR
31 04
E2 A4
×××××
A
×× ××
RW0
CCR
T N Z V C
E2 A6
×
0 0 0 0
T N Z V C
Memory
Memory
5 D
A B
31 04
E2A5
E2A4
Before execution
2 C
A 7
E2A5
E2A4
After execution
275
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.123
SUBW (Subtract Word Data of AL from AH to AL)
Subtract the word data of AL from the word data of AH and restore the result to AL.
■ SUBW (Subtract Word Data of AL from AH to AL)
● Assembler format:
SUBW A
● Operation:
(AL) ← (AH)–(AL)
(Word subtraction)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
*
*
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Set when an overflow has occurred as a result of the operation, cleared otherwise.
C:
Set when a borrow has occurred as a result of the operation, cleared otherwise.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
SUBW A
A
83 A2
CCR
10 19
×××××
T N Z V C
Before execution
276
A
83 A2
CCR
73 89
×
0 0 1 0
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.124
SWAP (Swap Byte Data of Accumulator)
Swap the high- and low-order bytes of the word data for the accumulator (A) with each
other.
■ SWAP (Swap Byte Data of Accumulator)
● Assembler format:
SWAP
● Operation:
(A) 0 to 7 ↔ (A) 8 to 15
(Byte swapping)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
3
Correction value:
0
● Example:
SWAP
A
×× ××
CCR
06 90
×××××
T N Z V C
Before execution
A
×× ××
CCR
90 06
×××××
T N Z V C
After execution
277
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.125
SWAPW (Swap Word Data of Accumulator)
Swap the high- and low-order words of the long word data for the accumulator (A) with
each other.
■ SWAPW (Swap Word Data of Accumulator)
● Assembler format:
SWAPW
● Operation:
Bits 0 to 15 of A ↔ Bits 16 to 31 of A
(Word swapping)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
SWAPW
A
19 86
CCR
98 61
×××××
T N Z V C
Before execution
278
A
98 61
CCR
19 86
×××××
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.126
UNLINK (Unlink and Create New Stack Frame)
Restore an old frame pointer from a stack.
■ UNLINK (Unlink and Create New Stack Frame)
● Assembler format:
UNLINK
● Operation:
(sp) ← (RW3), (RW3) ← ((sp)), (sp) ← (sp)+2
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
5
Correction value:
(c)
For the explanation of (c), see Table 8.4-2 .
● Example:
UNLINK
SP
RW3
E0 00
SP
E0 20
A 0
4 6
A0 46
RW3
Memory
E0 22
Memory
E020
SP
× ×
A 0
4 6
SP
× ×
E022
E021
E020
E000
Before execution
After execution
279
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.127
WBTc (Wait until Bit Condition Satisfied)
This instruction keeps reading data from the bit address specified by the operand until
that data satisfies the conditions. Once the data at the specified bit address satisfies
the conditions, control is transferred to the instruction subsequent to the WBTc
instruction.
■ WBTc (Wait until Bit Condition Satisfied)
● Assembler format:
WBTC io:bp
WBTS io:bp
● Operation:
Data is read from the bit address specified by io:bp until the data satisfies the condition. If the data from
the bit address satisfies the condition, control is transferred to the next instruction.
Interrupts are acceptable while the read operation is repeated with the condition not satisfied. If an
interrupt is generated in this state, the RETI instruction causes control to return to the WBTc instruction,
not to the instruction following the WBTc instruction.
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
Instruction
WBTC
WBTS
Condition
Bit data=0
Bit data=1
Number of bytes
3
3
Number of cycles
Undefined
Undefined
Correction value
280
Until the condition is satisfied Until the condition is satisfied
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
WBTS 34H:7
PC
E1 00
Memory
Peripheral
register
× ×
7 F
× ×
0034H
Before execution
Data is read from address 34H until bit 7 is set to "1"
(because of resource operation, for example).
When bit 7 becomes "1", execute the next instruction.
After execution
281
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.128
XCH (Exchange Byte Data of Source to Destination)
Exchange the byte data specified by the first operand with that specified by the second
operand.
If the first operand is A, the high-order byte of AL is set to 00H.
■ XCH (Exchange Byte Data of Source to Destination)
● Assembler format:
XCH A,ear
XCH A,eam
XCH Ri,ear
XCH Ri,eam
● Operation:
(First operand) ↔ (Second operand)
(Byte exchange)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Ri
Ri
Second operand
ear
eam
ear
eam
Number of bytes
2
2+
2
2+
Number of cycles
4
5+(a)
7
9+(a)
Correction value
0
2×(b)
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
282
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
XCH R4,@RW0+
RW0
00 60
R4
CCR
RW0
F1
R4
×××××
CCR
T N Z V C
2 2
22
×××××
T N Z V C
Memory
Memory
RW0
00 61
0061
0060
Before execution
RW0
F 1
0061
0060
After execution
283
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.129
XCHW (Exchange Word Data of Source to Destination)
Exchange the word data specified by the first operand with that specified by the second
operand.
■ XCHW (Exchange Word Data of Source to Destination)
● Assembler format:
XCHW A,ear
XCHW A,eam
XCHW RWi,ear
XCHW RWi,eam
● Operation:
(First operand) ↔ (Second operand)
(Word exchange)
● CCR:
I
S
T
N
Z
V
C
–
–
–
–
–
–
–
None of the flags is changed.
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
RWi
RWi
Second operand
ear
eam
ear
eam
Number of bytes
2
2+
2
2+
Number of cycles
4
5+(a)
7
9+(a)
Correction value
0
2×(c)
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
284
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
XCHW A,@RW0
A
×× ××
34 B4
RW0
E0 01
CCR
A
×××××
×× ××
2D 58
RW0
E0 01
CCR
T N Z V C
T N Z V C
Memory
RW0
2 D
5 8
×××××
Memory
E002
E001
Before execution
RW0
3 4
B 4
E002
E001
After execution
285
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.130
XOR (Exclusive Or Byte Data of Destination and Source
to Destination)
Take the logical exclusive OR of the byte data specified by the first operand and the
byte data specified by the second operand and restore the result in the first operand.
■ XOR (Exclusive Or Byte Data of Destination and Source to Destination)
● Assembler format:
XOR A,#imm8
XOR A,ear
XOR A,eam
XOR ear,A
XOR eam,A
● Operation:
(First operand) ← (First operand) xor (Second operand)
(Byte logical exclusive OR)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#im8
ear
eam
A
A
Number of bytes
2
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(b)
0
2×(b)
For the explanation of (a) and (b) in the table, see Table 8.4-1 and Table 8.4-2 .
286
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
XOR 0052H,A
A
×× ××
CCR
00 55
×××××
A
×× ××
CCR
T N Z V C
Before execution
×
1 0 0
×
T N Z V C
Memory
Memory
F A
00 55
000052
A F
000052
After execution
287
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.131
XORL (Exclusive Or Long Word Data of Destination and
Source to Destination)
Take the logical exclusive OR of the long word data for the accumulator (A) and that
specified by the second operand and restore the result in A.
■ XORL (Exclusive Or Long Word Data of Destination and Source to Destination)
● Assembler format:
XORL A,ear
XORL A,eam
● Operation:
(A) ← (A) xor (Second operand)
(Long word logical exclusive OR)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
Second operand
ear
eam
Number of bytes
2
2+
Number of cycles
6
7+(a)
Correction value
0
(d)
For the explanation of (a) and (d) in the table, see Table 8.4-1 and Table 8.4-2 .
288
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
XORL A,0FFF0H
A
82 52
FE AC
CCR
A
7D 07
×××××
54 AC
CCR
T N Z V C
F
5
A
0
0 0 0
×
T N Z V C
Memory
Memory
F
5
A
0
×
FFF3
FFF2
FFF1
FFF0
Before execution
F
5
A
0
F
5
A
0
FFF3
FFF2
FFF1
FFF0
After execution
289
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.132
XORW (Exclusive Or Word Data of AH and AL to AL)
Take the logical exclusive OR for the word data of AH and that of AL and restore the
result in AL.
■ XORW (Exclusive Or Word Data of AH and AL to AL)
● Assembler format:
XORW A
● Operation:
(AL) ← (AH) xor (AL)
(Word logical exclusive OR)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
2
Correction value:
0
● Example:
XORW A
A
04 26
CCR
AB 98
×××××
T N Z V C
Before execution
290
A
04 26
CCR
AF BE
×
1 0 0
×
T N Z V C
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.133
XORW (Exclusive Or Word Data of Destination and
Source to Destination)
Take the logical exclusive OR of the word data specified by the first operand and the
word data specified by the second operand and restore the result in the first operand.
■ XORW (Exclusive Or Word Data of Destination and Source to Destination)
● Assembler format:
XORW A,#imm16
XORW A,ear
XORW A,eam
XORW ear,A
XORW eam,A
● Operation:
(First operand) ← (First operand) xor (Second operand)
(Word logical exclusive OR)
● CCR:
I
S
T
N
Z
V
C
–
–
–
*
*
R
–
I, S, and T:
Unchanged
N:
Set when the MSB of the operation result is "1", cleared otherwise.
Z:
Set when the operation result is "0", cleared otherwise.
V:
Cleared
C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
First operand
A
A
A
ear
eam
Second operand
#i16
ear
eam
A
A
Number of bytes
3
2
2+
2
2+
Number of cycles
2
3
4+(a)
3
5+(a)
Correction value
0
0
(c)
0
2×(c)
For the explanation of (a) and (c) in the table, see Table 8.4-1 and Table 8.4-2 .
291
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
● Example:
XORW 0E001H,A
A
×× ××
CCR
59 63
×××××
A
×× ××
CCR
T N Z V C
Memory
8 3
4 2
×
1 0 0
E002
E001
×
T N Z V C
Memory
Before execution
292
59 63
D A
2 1
E002
E001
After execution
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.134
ZEXT (Zero Extend from Byte Data to Word Data)
Transfer "0" to bits 8 to 15 of the accumulator (A).
■ ZEXT (Zero Extend from Byte Data to Word Data)
● Assembler format:
ZEXT
● Operation:
Bits 8 to 15 of A ← 00H
● CCR:
I
S
T
N
Z
V
C
–
–
–
R
*
–
–
I, S, and T:
Unchanged
N:
Cleared
Z:
Set when the zero-extended data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
1
Correction value:
0
● Example:
ZEXT
A
×× ××
CCR
××
80
×××××
T N Z V C
Before execution
A
×× ××
CCR
00 80
×
0 0
××
T N Z V C
After execution
293
CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS
9.1.135
ZEXTW (Zero Extend from Word Data to Long Word Data)
Transfer "0" to bits 16 to 31 of the accumulator (A).
■ ZEXTW (Zero Extend from Word Data to Long Word Data)
● Assembler format:
ZEXTW
● Operation:
Bits 16 to 31 of A ← 0000H
● CCR:
I
S
T
N
Z
V
C
–
–
–
R
*
–
–
I, S, andT:
Unchanged
N:
Cleared
Z:
Set when the zero-extended data is "0", cleared otherwise.
V and C:
Unchanged
● Number of bytes, Number of cycles, and Correction value:
Number of bytes:
1
Number of cycles:
1
Correction value:
0
● Example:
ZEXTW
A
×× ××
CCR
FF 80
×××××
T N Z V C
Before execution
294
A
00 00
CCR
FF 80
×
0 0
××
T N Z V C
After execution
APPENDIX
This appendix includes lists and maps of instructions
for the F2MC-16LX.
APPENDIX A Explanation of Instruction Lists
APPENDIX B F2MC-16LX Instruction Lists (351 Instructions)
APPENDIX C F2MC-16LX Instruction Maps
295
APPENDIX
APPENDIX A Explanation of Instruction Lists
This section explains items and symbols used in each instruction list included in
Appendix B.
A.1 Items Used in Instruction Lists
A.2 Symbols Used in Instruction Lists
A.3 Effective Address Field
A.4 Calculating the Number of Execution Cycles
296
APPENDIX A Explanation of Instruction Lists
A.1
Items Used in Instruction Lists
Table A-1 explains the items used in the instruction lists.
■ Explanation of the Items Used in the Instruction Lists
Table A-1 Explanation of the Items Used in the Instruction Lists (1 / 2)
Item
Mnemonic
Description
Upper-case letters and symbols: Described as they appear in assembler.
Lower-case letters:
Replaced when described in assembler.
Numbers after lower-case letters: Indicate the bit width within the instruction.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
See Table A-4 for details about meanings of letters in items.
RG
B
Operation
Indicates the register access count during execution of instruction.
Used to calculate compensation values for CPU intermittent operation.
Indicates the compensation value for calculating the number of actual cycles during
execution of instruction.
The number of actual cycles during execution of instruction is the compensation
value summed with the value in the "~" column.
Indicates operation of instruction.
LH
Indicates special operations involving bits 15 through 08 of the accumulator.
Z: Transfers "0".
X: Sign-extended transfer through sign extension.
- : Transfers nothing.
AH
Indicates special operations involving the high-order 16 bits in the accumulator.
*: Transfers from AL to AH.
- : No transfer
Z: Transfers 00H to AH.
X: Transfers 00H or FFH to AH using sign extension AL.
I
S
T
N
Indicates the status of each of the following flags: I (interrupt enable), S (stack),
T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry).
*: Changes due to execution of instruction.
- : No change
S: Set by execution of instruction.
R: Reset by execution of instruction.
Z
V
C
297
APPENDIX
Table A-1 Explanation of the Items Used in the Instruction Lists (2 / 2)
Item
Description
RMW
Indicates whether the instruction is a read-modify-write instruction (a single
instruction that reads data from memory, etc., processes the data, and then writes
the result to memory.).
*: Instruction is a read-modify-write instruction.
-: Instruction is not a read-modify-write instruction.
Note:
A read-modify-write instruction cannot be used on addresses that have different
meanings depending on whether they are read or written.
■ Number of Execution Cycles
The number of cycles required to execute instructions (number of execution cycles) is the summation of the
number of cycles of each instruction, the compensation value determined by conditions, and the number of
cycles required to fetch programs. If, however, a program stored in memory that is connected to a 16-bit
bus such as internal ROMs is to be fetched, program fetch is executed every time instructions being
executed exceed the two byte (one word) boundary. Therefore, interference with data access will increase
the number of execution cycles. Since program fetch is executed for each byte of instructions being
executed when a program stored on the memory connected to an external 8-bit bus is fetched, data access
interference will increase the number of execution cycles.
When access is made to general-purpose registers, built-in ROMs, built-in RAMs, built-in I/O units, or
external buses during CPU intermittent operation, the CPU clock suspends its operation for the number of
cycles that is specified by the CG0/CG1 bit of the low-power-consumption-mode control register. Therefore,
to obtain the number of cycles required to execute instructions during CPU intermittent operation, add
these compensation values (the number of accesses multiplied by the number of cycled suspended) to the
number of normal execution cycles.
298
APPENDIX A Explanation of Instruction Lists
A.2
Symbols Used in Instruction Lists
Table A-2 explains the symbols used in the instruction lists.
■ Explanation of the Symbols Used in the Instruction Lists
Table A-2 Explanation of the Symbols Used in the Instruction Lists (1 / 2)
Symbol
A
Explanation
32 bit accumulator
The bit length used is different for each instruction.
Byte: Lower 8 bits of AL
Word: 16 bits of AL
Long: 32 bits of AL and AH
AH
Upper 16 bits of A
AL
Lower 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB
brg2
DTB, ADB, SSB, USB, DPR
Ri
R0, R1, R2, R3, R4, R5, R6, R7
Rj
R0, R1, R2, R3
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bit0 to bit15 of address 24
ad24 16-23
Bit16 to bit23 of address 24
299
APPENDIX
Table A-2 Explanation of the Symbols Used in the Instruction Lists (2 / 2)
Symbol
io
I/O area (000000H to 0000FFH)
imm4
4-bit immediate data
imm8
8-bit immediate data
imm16
16-bit immediate data
imm32
32-bit immediate data
ext (imm8)
16-bit data signed and extended from 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
300
Explanation
Bit offset value
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
Branch specification relative to PC
ear
Effective addressing (codes 00 to 07)
eam
Effective addressing (codes 08 to 1F)
rlst
Register list
APPENDIX A Explanation of Instruction Lists
A.3
Effective Address Field
Table A-3 lists address formats used in the effective address field.
■ Effective Address Field
Table A-3 Effective Address Field
Code
00
01
02
03
04
05
06
07
08
09
0A
Notation
R0
R1
R2
R3
R4
R5
R6
R7
@RW0
@RW1
@RW2
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
RL0
(RL0)
RL1
(RL1)
RL2
(RL2)
RL3
(RL3)
Address format
Number of bytes
of address
expansion part*
Register direct
Starting from the left, "ea" corresponds to the
byte, word and long-word types.
-
Register indirect
0
0B
@RW3
0C
@RW0+
0D
@RW1+
Register indirect with post-incrementing
0
0E
@RW2+
0F
@RW3+
10
@RW0+disp8
11
@RW1+disp8
12
@RW2+disp8
13
@RW3+disp8
Register indirect with 8-bit displacement
1
14
@RW4+disp8
15
@RW5+disp8
16
@RW6+disp8
17
@RW7+disp8
18
@RW0+disp16
19
@RW1+disp16
Register indirect with 16-bit displacement
2
1A
@RW2+disp16
1B
@RW3+disp16
1C
@RW0+RW7
Register indirect with index
0
1D
@RW1+RW7
Register indirect with index
0
1E
@PC+disp16
PC indirect with 16-bit displacement
2
1F
addr16
Direct address
2
* : The number of bytes of the address expansion part is shown in the "#" (number of bytes) column or the figure
before "+" in the expression of bytes in the instruction details.
301
APPENDIX
A.4
Calculating the Number of Execution Cycles
Table A-4 , Table A-5 , and Table A-6 show the method of calculating the number of
execution cycles of instructions.
■ Calculating the Number of Execution Cycles
Table A-4 Number of Execution Cycles for Designating Each Effective Address
Code
Operand
(a)*
Number of execution cycles
for each form of addressing
Number of accesses for
each form of addressing
Listed in Table of Instructions
Listed in Table of Instructions
00
to
07
Ri
Rwi
RLi
08
to
0B
@RWj
2
1
0C
to
0F
@RWj+
4
2
10
to
17
@RWi+disp8
2
1
18
to
1B
@RWj+disp16
2
1
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
* : (a) is used in "~" (number of cycles), "B" (compensation value) (both in "APPENDIX B F2MC-16LX Instruction
Lists (351 Instructions)", and in "CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS".
302
APPENDIX A Explanation of Instruction Lists
Table A-5 Compensation Values for Calculating the Number of Execution Cycles
(b) byte *
Operand
(c) word *
(d) long *
Cycles
Access
count
Cycles
Access
count
Cycles
Access
count
Internal register
+0
1
+0
1
+0
2
Internal register even
address
+0
1
+0
1
+0
2
Internal register odd
address
+0
1
+2
2
+4
4
Even address on external
data bus (16-bits)
+1
1
+1
1
+2
2
Odd address on external
data bus (16-bits)
+1
1
+4
2
+8
4
External data bus
(8-bit)
+1
1
+4
2
+8
4
* : (b), (c), and (d) are used in "~" (number of cycles), "B" (compensation value) (both in "APPENDIX B F2MC16LX Instruction Lists (351 Instructions)", and in "CHAPTER 9 DETAILED EXECUTION INSTRUCTIONS".
Note:
If external data buses are used, add the number of cycles that are weighted with ready input and
automatic ready.
Table A-6 Compensation Values for Calculating The Number of Program Fetch Cycles
Instruction
Byte boundary
Word boundary
Internal memory
-
+2
External data bus (16-bit)
-
+3
External data bus (8-bit)
+3
-
Notes:
• If external data buses are used, add the number of cycles that are weighted with ready input and
automatic ready.
• Since all cases of program fetch do not delay the execution of instructions, use this compensation
value to calculate the worst case value.
303
APPENDIX
APPENDIX B F2MC-16LX Instruction Lists (351 Instructions)
This appendix lists the instructions used in assembler.
For items and symbols for each instruction list, see "APPENDIX A Explanation of
Instruction Lists".
B.1 Transfer Instructions
B.2 Numeric Data Operation Instructions
B.3 Logical Data Operation Instruction
B.4 Shift Instruction
B.5 Branch Instructions
B.6 Other Instructions
304
APPENDIX B F2MC-16LX Instruction Lists (351 Instructions)
B.1
Transfer Instructions
Table B-1 and Table B-2 lists the transfer instructions of the F2MC-16LX.
• Transfer instruction (Byte): 41 instructions in Table B-1
• Transfer instruction (Word/Long-word): 38 instructions in Table B-2
■ Transfer Instructions
Table B-1 Transfer Instruction (Byte): 41 Instructions
Mnemonic
#
~
RG
B
MOV
A,dir
2
3
0
(b)
MOV
A,addr16
3
4
0
(b)
MOV
A,Ri
1
2
1
0
MOV
A,ear
2
2
1
0
MOV
A,eam
2+
3 + (a)
0
(b)
MOV
A,io
2
3
0
(b)
MOV
A,#imm8
2
2
0
0
MOV
A,@A
2
3
0
(b)
MOV
A,@RLi+disp8
3
10
2
(b)
MOVN
A,#imm4
1
1
0
0
MOVX
A,dir
2
3
0
(b)
MOVX
A,addr16
3
4
0
(b)
MOVX
A,Ri
2
2
1
0
MOVX
A,ear
2
2
1
0
MOVX
A,eam
2+
3 + (a)
0
(b)
MOVX
A,io
2
3
0
(b)
MOVX
A,#imm8
2
2
0
0
MOVX
A,@A
2
3
0
(b)
MOVX
A,@RWi+disp8
2
5
1
(b)
MOVX
A,@RLi+disp8
3
10
2
(b)
MOV
dir,A
2
3
0
(b)
MOV
addr16,A
3
4
0
(b)
MOV
Ri,A
1
2
1
0
MOV
ear,A
2
2
1
0
MOV
eam,A
2+
3 + (a)
0
(b)
MOV
io,A
2
3
0
(b)
MOV
@RLi+disp8,A
3
10
2
(b)
MOV
Ri,ear
2
3
2
0
MOV
Ri,eam
2+
4 + (a)
1
(b)
MOV
ear,Ri
2
4
2
0
MOV
eam,Ri
2+
5 + (a)
1
(b)
MOV
Ri,#imm8
2
2
1
0
MOV
io,#imm8
3
5
0
(b)
MOV
dir,#imm8
3
5
0
(b)
MOV
ear,#imm8
3
2
1
0
MOV
eam,#imm8
3+
4 + (a)
0
(b)
MOV
@AL,AH
2
3
0
(b)
XCH
A,ear
2
4
2
0
XCH
A,eam
2+
5 + (a)
0
2 × (b)
XCH
Ri,ear
2
7
4
0
XCH
Ri,eam
2+
9 + (a)
2
2 × (b)
Note: See Table A-4 and Table A-5 for information on (a) and (b) in the table.
Operation
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← (imm8)
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi)+disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
byte (A) ↔ (ear)
byte (A) ↔ (eam)
byte (Ri) ↔ (ear)
byte (Ri) ↔ (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
R
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
305
APPENDIX
Table B-2 Transfer Instruction (Word/Long-word): 38 Instructions
Mnemonic
#
~
RG
B
Operation
MOVW
A,dir
2
3
0
(c)
word (A) ← (dir)
MOVW
A,addr16
3
4
0
(c)
word (A) ← (addr16)
MOVW
A,SP
1
1
0
0
word (A) ← (SP)
MOVW
A,RWi
1
2
1
0
word (A) ← (RWi)
MOVW
A,ear
2
2
1
0
word (A) ← (ear)
MOVW
A,eam
2+
3 + (a)
0
(c)
word (A) ← (eam)
MOVW
A,io
2
3
0
(c)
word (A) ← (io)
MOVW
A,@A
2
3
0
(c)
word (A) ← ((A))
MOVW
A,#imm16
3
2
2
0
word (A) ← imm16
MOVW
A,@RWi+disp8
2
5
1
(c)
word (A) ← ((RWi)+disp8)
MOVW
A,@RLi+disp8
3
10
2
(c)
word (A) ← ((RLi)+disp8)
MOVW
dir,A
2
3
0
(c)
word (dir) ← (A)
MOVW
addr16,A
3
4
0
(c)
word (addr16) ← (A)
MOVW
SP,A
1
1
0
0
word (SP) ← (A)
MOVW
RWi,A
1
2
1
0
word (RWi) ← (A)
MOVW
ear,A
2
2
1
0
word (ear) ← (A)
MOVW
eam,A
2+
3 + (a)
0
(c)
word (eam) ← (A)
MOVW
io,A
2
3
0
(c)
word (io) ← (A)
MOVW
@RWi+disp8,A
2
5
1
(c)
word ((RWi)+disp8) ← (A)
MOVW
@RLi+disp8,A
3
10
2
(c)
word ((RLi)+disp8) ← (A)
MOVW
RWi,ear
2
3
2
0
word (RWi) ← (ear)
MOVW
Rwi,eam
2+
4 + (a)
1
(c)
word (RWi) ← (eam)
MOVW
ear,Rwi
2
4
2
0
word (ear) ← (RWi)
MOVW
eam,Rwi
2+
5 + (a)
1
(c)
word (eam) ← (RWi)
MOVW
RWi,#imm16
3
2
1
0
word (RWi) ← imm16
MOVW
io,#imm16
4
5
0
(c)
word (io) ← imm16
MOVW
ear,#imm16
4
2
1
0
word (ear) ← imm16
MOVW
eam,#imm16
4+
4 + (a)
0
(c)
word (eam) ← imm16
MOVW
@AL,AH
2
3
0
(c)
word ((A)) ← (AH)
XCHW
A,ear
2
4
2
0
word (A) ↔ (ear)
XCHW
A,eam
2+
5 + (a)
0
2 × (c)
word (A) ↔ (eam)
XCHW
RWi, ear
2
7
4
0
word (RWi) ↔ (ear)
word (RWi) ↔ (eam)
XCHW
RWi, eam
2+
9 + (a)
2
2 × (c)
MOVL
A,ear
2
4
2
0
long (A) ← (ear)
MOVL
A,eam
2+
5 + (a)
0
(d)
long (A) ← (eam)
MOVL
A,#imm32
5
3
0
0
long (A) ← imm32
MOVL
ear,A
2
4
2
0
long (ear1) ← (A)
MOVL
eam,A
2+
5 + (a)
0
(d)
long(eam1) ← (A)
Note: See Table A-4 and Table A-5 for information on (a), (c) and (d) in the table.
306
LH
AH
I
S
T
N
Z
V
C
RMW
-
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
APPENDIX B F2MC-16LX Instruction Lists (351 Instructions)
B.2
Numeric Data Operation Instructions
The numeric data operation instructions of the F2MC-16L are listed in the following five
tables:
• Table B-3 for addition and subtraction (Byte/Word/Long-word) : 42 instructions
• Table B-4 for increment and decrement (Byte/Word/Long-word) : 12 instructions
• Table B-5 for compare (Byte/Word/Long-word) : 11 instructions
• Table B-6 for unsigned multiplication and division : 11 instructions (Word/Long-word)
• Table B-7 for signed multiplication and division : 11 instructions (Word/Long-word)
■ Numeric Data Operation Instructions
Table B-3 Addition and Subtraction (Byte/Word/Long-word): 42 Instructions
Mnemonic
#
~
RG
B
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 × (b)
0
0
(b)
0
ADDW
A
1
2
0
0
ADDW
A,ear
2
3
1
0
ADDW
A,eam
2+
4+(a)
0
(c)
ADDW
A,#imm16
3
2
0
0
ADDW
ear,A
2
3
2
0
ADDW
eam,A
2+
5+(a)
0
2 × (c)
ADDCW A,ear
2
3
1
0
ADDCW A,eam
2+
4+(a)
0
(c)
SUBW
A
1
2
0
0
SUBW
A,ear
2
3
1
0
SUBW
A,eam
2+
4+(a)
0
(c)
SUBW
A,#imm16
3
2
0
0
SUBW
ear,A
2
3
2
0
SUBW
eam,A
2+
5+(a)
0
2 × (c)
SUBCW A,ear
2
3
1
0
SUBCW A,eam
2+
4+(a)
0
(c)
ADDL
A,ear
2
6
2
0
ADDL
A,eam
2+
7+(a)
0
(d)
ADDL
A,#imm32
5
4
0
0
SUBL
A,ear
2
6
2
0
SUBL
A,eam
2+
7+(a)
0
(d)
SUBL
A,#imm32
5
4
0
0
Note: See Table A-4 and Table A-5 for information on (a) to (d) in the table.
Operation
byte (A) ← (A) + imm8
byte (A) ← (A) + (dir)
byte (A) ← (A) + (ear)
byte (A) ← (A) + (eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear)+ (C)
byte (A) ← (A) + (eam)+ (C)
byte (A) ← (AH) + (AL) + (C)
(decimal)
byte (A) ← (A) - imm8
byte (A) ← (A) - (dir)
byte (A) ← (A) - (ear)
byte (A) ← (A) - (eam)
byte (ear) ← (ear) - (A)
byte (eam) ← (eam) - (A)
byte (A) ← (AH) - (AL) - (C)
byte (A) ← (A) - (ear) - (C)
byte (A) ← (A) - (eam) - (C)
byte (A) ← (AH) - (AL) - (C)
(decimal)
word (A) ← (AH) + (AL)
word (A) ← (A) + (ear)
word (A) ← (A) + (eam)
word (A) ← (A) + imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) + (C)
word (A) ← (AH) - (AL)
word (A) ← (A) - (ear)
word (A) ← (A) - (eam)
word (A) ← (A) - imm16
word (ear) ← (ear) - (A)
word (eam) ← (eam) - (A)
word (A) ← (A) - (ear) - (C)
word (A) ← (A) - (eam) - (C)
long (A) ← (A) + (ear)
long (A) ← (A) + (eam)
long (A) ← (A) + imm32
long (A) ← (A) - (ear)
long (A) ← (A) - (eam)
long (A) ← (A) - imm32
LH
AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
307
APPENDIX
Table B-4 Increment and Decrement (Byte/Word/Long-word): 12 Instructions
Mnemonic
#
~
RG
B
INC
ear
2
3
2
0
INC
eam
2+
5+(a)
0
2 × (b)
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
byte (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
byte (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DEC
ear
2
3
2
0
byte (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
DEC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
INCW
ear
2
3
2
0
word (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
INCW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
DECW
ear
2
3
2
0
DECW
eam
2+
5+(a)
0
2 × (c)
INCL
ear
2
7
4
0
INCL
eam
2+
9+(a)
0
2 × (d)
DECL
ear
2
7
4
0
DECL
eam
2+
9+(a)
0
2 × (d)
word (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
word (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) + 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) + 1
-
-
-
-
-
*
*
*
-
*
long (ear) ← (ear) - 1
-
-
-
-
-
*
*
*
-
-
long (eam) ← (eam) - 1
-
-
-
-
-
*
*
*
-
*
Note: See Table A-4 and Table A-5 for information on (a) to (d) in the table.
Table B-5 Compare (Byte/Word/Long-word): 11 Instructions
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
Mnemonic
A
1
1
0
0
byte (AH) - (AL)
Operation
-
-
-
-
-
*
*
*
*
-
CMP
A,ear
2
2
1
0
byte (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMP
A,eam
2+
3+(a)
0
(b)
byte (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMP
A,#imm8
2
2
0
0
byte (A) - imm8
-
-
-
-
-
*
*
*
*
-
CMPW
A
1
1
0
0
word (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMPW
A,ear
2
2
1
0
word (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPW
A,eam
2+
3+(a)
0
(c)
word (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPW
A,#imm16
3
2
0
0
word (A) - imm16
-
-
-
-
-
*
*
*
*
-
CMPL
A,ear
2
6
2
0
long (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPL
A,eam
2+
7+(a)
0
(d)
long (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPL
A,#imm32
5
3
0
0
long (A) - imm32
-
-
-
-
-
*
*
*
*
-
Note: See Table A-4 and Table A-5 for information on (a) to (d) in the table.
308
APPENDIX B F2MC-16LX Instruction Lists (351 Instructions)
Table B-6 Unsigned Multiplication and Division: 11 Instructions (Word/Long-word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIVU
A
1
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL)
Remainder → byte (AH)
-
-
-
-
-
-
-
*
*
-
DIVU
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A)
Remainder → byte (ear)
-
-
-
-
-
-
-
*
*
-
DIVU
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A)
Remainder → byte (eam)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A)
Remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A)
Remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MULU
A
1
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A
1
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1: 3 for zero-divide, 7 for overflow, 15 for normal
*2: 4 for zero-divide, 8 for overflow, 16 for normal
*3: 6 + (a) for zero-divide, 9 + (a) for overflow, 19 + (a) for normal
*4: 4 for zero-divide, 7 for overflow, 22 for normal
*5: 6 + (a) for zero-divide, 8 + (a) for overflow, 26 + (a) for normal
*6: (b) for zero-divide or overflow, 2 × (b) for normal
*7: (c) for zero-divide or overflow, 2 × (c) for normal
*8: 3 when byte (AH) is 0, 7 when byte (AH) is not 0
*9: 4 when byte (ear) is 0, 8 when byte (ear) is not 0
*10: 5 + (a) when byte (eam) is 0, 9 + (a) when byte (eam) is not 0
*11: 3 when word (AH) is 0, 11 when word (AH) is not 0
*12: 4 when word (ear) is 0, 12 when word (ear) is not 0
*13: 5 + (a) when word (eam) is 0, 13 + (a) when word (eam) is not 0
Note: See Table A-4 and Table A-5 for information on (a), (b) and (c) in the table.
309
APPENDIX
Table B-7 Signed Multiplication and Division: 11 Instructions (Word/Long-word)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
DIV
A
2
*1
0
0
word (AH) / byte (AL)
quotient → byte (AL)
Remainder → byte (AH)
Z
-
-
-
-
-
-
*
*
-
DIV
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient → byte (A)
Remainder → byte (ear)
Z
-
-
-
-
-
-
*
*
-
DIV
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient → byte (A)
Remainder → byte (eam)
Z
-
-
-
-
-
-
*
*
-
DIVW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient → word (A)
Remainder → word (ear)
-
-
-
-
-
-
-
*
*
-
DIVW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient → word (A)
Remainder → word (eam)
-
-
-
-
-
-
-
*
*
-
MUL
A
2
*8
0
0
byte (AH) * byte (AL) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,ear
2
*9
1
0
byte (A) * byte (ear) → word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) → word (A)
-
-
-
-
-
-
-
-
-
-
MULW
A
2
*11
0
0
word (AH) * word (AL) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULW
A,ear
2
*12
1
0
word (A) * word (ear) → Long (A)
-
-
-
-
-
-
-
-
-
-
MULW
A,eam
2+
*13
0
(c)
word (A) * word (eam) → Long (A)
-
-
-
-
-
-
-
-
-
-
*1:
*2:
*3:
*4:
3 for zero-divide, 8 or 18 for overflow, 18 for normal
4 for zero-divide, 11 or 22 for overflow, 23 for normal
5 + (a) for zero-divide, 12 + (a) or 23 + (a) for overflow, 24 + (a) for normal
If the dividend is positive: 4 for zero-divide, 12 or 30 for overflow, 31 for normal
If the dividend is negative: 4 for zero-divide, 12 or 31 for overflow, 32 for normal
*5: If the dividend is positive: 5 + (a) for zero-divide, 12 + (a) or 31 + (a) for overflow, 32 + (a) for normal
If the dividend is negative: 5 + (a) for zero-divide, 12 + (a) or 32 + (a) for overflow, 33 + (a) for normal
*6: (b) for zero-divide or overflow, 2 x (b) for normal
*7: (c) for zero-divide or overflow, 2 x (c) for normal
*8: 3 when byte (AH) is 0, 12 when the result is positive, 13 when the result is negative
*9: 4 when byte (ear) is 0, 13 when the result is positive, 14 when the result is negative
*10: 5 + (a) when byte (eam) is 0, 14 + (a) when the result is positive, 15 + (a) when the result is negative
*11: 3 when word (AH) is 0, 16 when the result is positive, 19 when the result is negative
*12: 4 when word (ear) is 0, 17 when the result is positive, 20 when the result is negative
*13: 5 + (a) when word (eam) is 0, 18 + (a) when the result is positive, 21 + (a) when the result is negative
Notes:
• There are two numbers of execution cycles when overflow occurs during execution of the DIV and DIVW instructions, depending on the number of execution cycles is
detected before or after operation.
• The content of AL is corrupted when overflow occurs during execution of the DIV and DIVW instructions.
• See Table A-4 and Table A-5 for information on (a), (b) and (c) in the table.
310
APPENDIX B F2MC-16LX Instruction Lists (351 Instructions)
B.3
Logical Data Operation Instruction
The logical data operation instructions of the F2MC-16L are listed in the following four
tables:
• Table B-8 for logic 1 (Byte/Word): 39 instructions
• Table B-9 for logic 2 (Long): 6 instructions
• Table B-10 for sign inversion (Byte/Word): 6 instructions
• Table B-11 for normalize instructions (Long): 1 instruction
■ Logical Operation Instruction
Table B-8 Logic 1 (Byte/Word): 39 Instructions (1 / 2)
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
AND
A,#imm8
2
2
0
0
byte (A) ← (A) and imm8
-
-
-
-
-
*
*
R
-
-
AND
A,ear
2
3
1
0
byte (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
AND
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
byte (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
byte (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
AND
ear,A
2
3
2
0
AND
eam,A
2+
5+(a)
0
2 × (b)
OR
A,#imm8
2
2
0
0
byte (A) ← (A) or imm8
-
-
-
-
-
*
*
R
-
-
OR
A,ear
2
3
1
0
byte (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
OR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
OR
ear,A
2
3
2
0
byte (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
OR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XOR
A,#imm8
2
2
0
0
byte (A) ← (A) xor imm8
-
-
-
-
-
*
*
R
-
-
XOR
A,ear
2
3
1
0
byte (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XOR
A,eam
2+
4+(a)
0
(b)
byte (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XOR
ear,A
2
3
2
0
byte (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XOR
eam,A
2+
5+(a)
0
2 × (b)
byte (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOT
A
1
2
0
0
byte (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOT
ear
2
3
2
0
byte (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOT
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
ANDW
A
1
2
0
0
word (A) ← (AH) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
A,#imm16
3
2
0
0
word (A) ← (A) and imm16
-
-
-
-
-
*
*
R
-
-
ANDW
A,ear
2
3
1
0
word (A) ← (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
word (ear) ← (ear) and (A)
-
-
-
-
-
*
*
R
-
-
word (eam) ← (eam) and (A)
-
-
-
-
-
*
*
R
-
*
0
word (A) ← (AH) or (A)
-
-
-
-
-
*
*
R
-
-
0
word (A) ← (A) or imm16
-
-
-
-
-
*
*
R
-
-
1
0
word (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
0
(c)
word (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
word (ear) ← (ear) or (A)
-
-
-
-
-
*
*
R
-
-
word (eam) ← (eam) or (A)
-
-
-
-
-
*
*
R
-
*
ANDW
ear,A
2
3
2
0
ANDW
eam,A
2+
5+(a)
0
2 × (c)
ORW
A
1
2
0
ORW
A,#imm16
3
2
0
ORW
A,ear
2
3
ORW
A,eam
2+
4+(a)
ORW
ear,A
2
3
2
0
ORW
eam,A
2+
5+(a)
0
2 × (c)
311
APPENDIX
Table B-8 Logic 1 (Byte/Word): 39 Instructions (2 / 2)
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
XORW
Mnemonic
A
1
2
0
0
word (A) ← (AH) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
A,#imm16
3
2
0
0
word (A) ← (A) xor imm16
-
-
-
-
-
*
*
R
-
-
XORW
A,ear
2
3
1
0
word (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORW
A,eam
2+
4+(a)
0
(c)
word (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XORW
ear,A
2
3
2
0
word (ear) ← (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
eam,A
2+
5+(a)
0
2 × (c)
word (eam) ← (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOTW
A
1
2
0
0
word (A) ← not (A)
-
-
-
-
-
*
*
R
-
-
NOTW
ear
2
3
2
0
word (ear) ← not (ear)
-
-
-
-
-
*
*
R
-
-
NOTW
eam
2+
5+(a)
0
2 × (c)
word (eam) ← not (eam)
-
-
-
-
-
*
*
R
-
*
RMW
Note: See Table A-4 and Table A-5 for information on (a), (b) and (c) in the table.
Table B-9 Logic 2 (Long): 6 Instructions
Mnemonic
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
ANDL
A,ear
2
6
2
0
long (A) ← (A) and (ear)
Operation
-
-
-
-
-
*
*
R
-
-
ANDL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ORL
A,ear
2
6
2
0
long (A) ← (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) or (eam)
-
-
-
-
-
*
*
R
-
-
XORL
A,ear
2
6
2
0
long (A) ← (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORL
A,eam
2+
7+(a)
0
(d)
long (A) ← (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
Note: See Table A-4 and Table A-5 for information on (a) and (d) in the table.
Table B-10 Sign Inversion (Byte/Word): 6 Instructions
Mnemonic
NEG
A
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
1
2
0
0
byte (A) ← 0 - (A)
X
-
-
-
-
*
*
*
*
-
byte (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
byte (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
word (A) ← 0 - (A)
-
-
-
-
-
*
*
*
*
-
NEG
ear
2
3
2
0
NEG
eam
2+
5+(a)
0
2 × (b)
NEGW
A
1
2
0
0
NEGW
ear
2
3
2
0
NEGW
eam
2+
5+(a)
0
2 × (c)
Operation
word (ear) ← 0 - (ear)
-
-
-
-
-
*
*
*
*
-
word (eam) ← 0 - (eam)
-
-
-
-
-
*
*
*
*
*
LH
AH
I
S
T
N
Z
V
C
RMW
-
-
-
-
-
-
*
-
-
-
Note: See Table A-4 and Table A-5 for information on (a), ( b) and (c) in the table.
Table B-11 Normalize Instruction (Long): 1 Instruction
Mnemonic
NRML
A,R0
#
~
RG
B
2
*1
1
0
Operation
long (A) ← Shift to the first bit which is set to 1
formerly placed
byte (R0) ← Number of shifts at that time
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
Note: See Table A-3 and Table A-4 for information on (a), ( b) and (c) in the table.
312
APPENDIX B F2MC-16LX Instruction Lists (351 Instructions)
B.4
Shift Instruction
Table B-12 lists 18 shift instructions of F2MC-16L.
■ Shift Instruction
Table B-12 Shift Instructions (Byte/Word/Long-word): 18 Instructions
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
RMW
RORC
Mnemonic
A
2
2
0
0
byte (A) ← Right rotate with carry
Operation
-
-
-
-
-
*
*
-
*
-
ROLC
A
2
2
0
0
byte (A) ← Left rotate with carry
-
-
-
-
-
*
*
-
*
-
RORC
ear
2
3
2
0
byte (ear) ← Right rotate with carry
-
-
-
-
-
*
*
-
*
-
RORC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Right rotate with carry
-
-
-
-
-
*
*
-
*
*
ROLC
ear
2
3
2
0
byte (ear) ← Left rotate with carry
-
-
-
-
-
*
*
-
*
-
ROLC
eam
2+
5+(a)
0
2 × (b)
byte (eam) ← Left rotate with carry
-
-
-
-
-
*
*
-
*
*
ASR
A,R0
2
*1
1
0
byte (A) ← Arithmetic right shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSR
A,R0
2
*1
1
0
byte (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSL
A,R0
2
*1
1
0
byte (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRW
A
1
2
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSRW
A/SHRW A
1
2
0
0
word (A) ← Logical right shift (A, 1 bit)
-
-
-
-
*
R
*
-
*
-
LSLW
A/SHLW A
1
2
0
0
word (A) ← Logical left shift (A, 1 bit)
-
-
-
-
-
*
*
-
*
-
ASRW
A,R0
2
*1
1
0
word (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRW
A,R0
2
*1
1
0
word (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLW
A,R0
2
*1
1
0
word (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRL
A,R0
2
*2
1
0
long (A) ← Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRL
A,R0
2
*2
1
0
long (A) ← Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLL
A,R0
2
*2
1
0
long (A) ← Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
*1: 6 when R0 is 0; otherwise, 5 + (R0)
*2: 6 when R0 is 0; otherwise, 6 + (R0)
Note: See Table A-4 and Table A-5 for information on (a) and (b) in the table.
313
APPENDIX
B.5
Branch Instructions
The branch instructions of the F2MC-16L are listed in the following two tables:
• Table B-13 for branch 1: 31 instructions
• Table B-14 for branch 2: 19 instructions
■ Branch Instruction
Table B-13 Branch 1: 31 Instructions
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
BZ/BEQ
Mnemonic
rel
2
*1
0
0
Branch on (Z) = 1
Operation
-
-
-
-
-
-
-
-
-
RMW
-
BNZ/BNE
rel
2
*1
0
0
Branch on (Z) = 0
-
-
-
-
-
-
-
-
-
-
BC/BLO
rel
2
*1
0
0
Branch on (C) = 1
-
-
-
-
-
-
-
-
-
-
BNC/BHS
rel
2
*1
0
0
Branch on (C) = 0
-
-
-
-
-
-
-
-
-
-
BN
rel
2
*1
0
0
Branch on (N) = 1
-
-
-
-
-
-
-
-
-
-
BP
rel
2
*1
0
0
Branch on (N) = 0
-
-
-
-
-
-
-
-
-
-
BV
rel
2
*1
0
0
Branch on (V) = 1
-
-
-
-
-
-
-
-
-
-
BNV
rel
2
*1
0
0
Branch on (V) = 0
-
-
-
-
-
-
-
-
-
-
BT
rel
2
*1
0
0
Branch on (T) = 1
-
-
-
-
-
-
-
-
-
-
BNT
rel
2
*1
0
0
Branch on (T) = 0
-
-
-
-
-
-
-
-
-
-
BLT
rel
2
*1
0
0
Branch on (V) xor (N) = 1
-
-
-
-
-
-
-
-
-
-
BGE
rel
2
*1
0
0
Branch on (V) xor (N) = 0
-
-
-
-
-
-
-
-
-
-
BLE
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BGT
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BLS
rel
2
*1
0
0
Branch on (C) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BHI
rel
2
*1
0
0
Branch on (C) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BRA
rel
2
*1
0
0
Unconditional branch
-
-
-
-
-
-
-
-
-
-
JMP
@A
1
2
0
0
word (PC) ← (A)
-
-
-
-
-
-
-
-
-
JMP
addr16
3
3
0
0
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
JMP
@ear
2
3
1
0
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
word (PC) ← (ear), (PCB) ← (ear+2)
-
-
-
-
-
-
-
-
-
-
word (PC) ← (eam), (PCB) ← (eam+2)
-
-
-
-
-
-
-
-
-
-
JMP
@eam
2+
4+(a)
0
(c)
JMPP
@ear *3
2
5
2
0
JMPP
@eam *3
2+
6+(a)
0
(d)
JMPP
addr24
4
4
0
0
word (PC) ← ad24 0-15, (PCB) ← ad24 16-23
-
-
-
-
-
-
-
-
-
-
CALL
@ear *4
2
6
1
(c)
word (PC) ← (ear)
-
-
-
-
-
-
-
-
-
-
CALL
@eam *4
2+
7+(a)
0
2 × (c)
word (PC) ← (eam)
-
-
-
-
-
-
-
-
-
-
CALL
addr16 *5
3
6
0
(c)
word (PC) ← addr16
-
-
-
-
-
-
-
-
-
-
CALLV
#vct4 *5
1
7
0
2 × (c)
Vector call instruction
-
-
-
-
-
-
-
-
-
-
CALLP
@ear *6
2
10
2
2 × (c)
word (PC) ← (ear)0-15, (PCB) ← (ear)16-23
-
-
-
-
-
-
-
-
-
-
CALLP
@eam *6
2+
11+(a)
0
*2
word (PC) ← (eam)0-15, (PCB) ← (eam)16-23
-
-
-
-
-
-
-
-
-
-
CALLP
addr24 *7
4
10
0
2 × (c)
word (PC) ← addr0-15, (PCB) ← addr16-23
-
-
-
-
-
-
-
-
-
-
*1: 4 when branch is made, 6 when branch is not made
*2: 3 × (c) + (b)
*3: Read the branched address (word)
*4: W: Save to stack (word), R: Read the branched address (word)
*5: Save to stack (word)
*6: W: Save to stack (long), R: Read the branched address (long)
*7: Save to stack (long)
Note: See Table A-4 and for information on (a) to (d) in the table.
314
APPENDIX B F2MC-16LX Instruction Lists (351 Instructions)
Table B-14 Branch 2: 19 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S T N Z V C
RMW
CBNE
A,#imm8,rel
3
*1
0
0
Branch on byte (A) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
A,#imm16,rel
4
*1
0
0
Branch on word (A) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CBNE
ear,#imm8,rel
4
*2
1
0
Branch on byte (ear) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CBNE
eam,#imm8,rel *9
4+
*3
0
(b)
Branch on byte (eam) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
ear,#imm16,rel
5
*4
1
0
Branch on word (ear) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CWBNE
eam,#imm16,rel*9
5+
*3
0
(c)
Branch on word (eam) not equal to imm16
-
-
-
-
-
*
*
*
*
-
DBNZ
ear,rel
3
*5
2
0
Branch on byte (ear) = (ear) - 1, (ear) not equal to 0
-
-
-
-
-
*
*
*
-
-
DBNZ
eam,rel
3+
*6
2
*
DWBNZ
ear,rel
3
*5
2
DWBNZ
eam,rel
3+
*6
2
2 × (c) Branch on word (eam) = (eam) - 1, (eam) not equal to 0
2 × (b) Branch on byte (eam) = (eam) - 1, (eam) not equal to 0
0
Branch on word (ear) = (ear) - 1, (ear) not equal to 0
-
-
-
-
-
*
*
*
-
-
-
-
-
-
*
*
*
-
-
-
-
-
-
-
*
*
*
-
*
INT
#vct8
2
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT
addr16
3
16
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INTP
addr24
4
17
0
6 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
1
20
0
8 × (c) Software interrupt
-
-
R
S
-
-
-
-
-
-
INT9
RETI
LINK
#imm8
UNLINK
1
*8
0
*7
Return from interrupt
-
-
*
*
*
*
*
*
*
-
2
6
0
(c)
At the entrance of function, save old frame pointers im
stack, set up new frame pointers, reserve area for local
pointers.
-
-
-
-
-
-
-
-
-
-
1
5
0
(c)
At the exit of function, recover the old frame pointers from
the stack.
-
-
-
-
-
-
-
-
-
-
RET
*10
1
4
0
(c)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
RETP
*11
1
6
0
(d)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
*1: 5 when branch is made, 4 when branch is not made
*2: 13 when branch is made, 12 when branch is not made
*3: 7 + (a) when branch is made, 6 + (a) when branch is not made
*4: 8 when branch is made, 7 when branch is not made
*5: 7 when branch is made, 6 when branch is not made
*6: 8 + (a) when branch is made, 7 + (a) when branch is not made
*7: 3 × (b) + 2 × (c) when the sequence is branched to the next interrupt request, 6 × (c) when returned from the current interruption
*8: 15 when the sequence is branched to the next interrupt request, 17 when returned from the current interruption
*9: Do not use the RWj + addressing mode for the CBNE/CWBNE instruction.
*10: Return from stack (word)
*11: Return from stack (long)
Note: See Table A-5 and Table A-5 for information on (a) to (d) in the table.
315
APPENDIX
B.6
Other Instructions
Other instructions of the F2MC-16L are listed in the following four tables:
• Table B-15 for other control systems (Byte/Word/Long-word) : 28 instructions
• Table B-16 for bit operation instructions: 21 instructions
• Table B-17 for accumulator operation instructions (Byte/Word): 6 instructions
• Table B-18 for string instructions: 10 instructions
■ Other Instructions
Table B-15 Other Control Systems (Byte/Word/Long-word): 28 Instructions
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
PUSHW
Mnemonic
A
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (A)
Operation
-
-
-
-
-
-
-
-
-
RMW
-
PUSHW
AH
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (AH)
-
-
-
-
-
-
-
-
-
-
PUSHW
PS
1
4
0
(c)
word (SP) ← (SP) - 2, ((SP)) ← (PS)
-
-
-
-
-
-
-
-
-
PUSHW
rlst
2
*3
*5
*4
(SP) ← (SP) - 2n, ((SP)) ← (rlst)
-
-
-
-
-
-
-
-
-
-
POPW
A
1
3
0
(c)
word (A) ← ((SP)), (SP) ← (SP) + 2
-
*
-
-
-
-
-
-
-
-
POPW
AH
1
3
0
(c)
word (AH) ← ((SP)), (SP) ← (SP) + 2
-
-
-
-
-
-
-
-
-
-
POPW
PS
1
4
0
(c)
word (PS) ← ((SP)), (SP) ← (SP) + 2
-
-
*
*
*
*
*
*
*
-
POPW
rlst
2
*2
*5
*4
(rlst) ← ((SP)), (SP) ← (SP)
-
-
-
-
-
-
-
-
-
-
JCTX
@A
1
14
0
6 × (c)
Context switching instruction
-
-
*
*
*
*
*
*
*
-
AND
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) and imm8
-
-
*
*
*
*
*
*
*
-
OR
CCR,#imm8
2
3
0
0
byte (CCR) ← (CCR) or imm8
-
-
*
*
*
*
*
*
*
-
MOV
RP,#imm8
2
2
0
0
byte (RP) ← imm8
-
-
-
-
-
-
-
-
-
-
MOV
ILM,#imm8
2
2
0
0
byte (ILM) ← imm8
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,ear
2
3
1
0
word (RWi) ← ear
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,eam
2+
2+(a)
1
0
word (RWi) ← eam
-
-
-
-
-
-
-
-
-
-
MOVEA
A,ear
2
1
0
0
word (A) ← ear
-
*
-
-
-
-
-
-
-
-
MOVEA
A,eam
2+
1+(a)
0
0
word (A) ← eam
-
*
-
-
-
-
-
-
-
-
ADDSP
#imm8
2
3
0
0
word (SP) ← ext(imm8)
-
-
-
-
-
-
-
-
-
-
ADDSP
#imm16
3
3
0
0
word (SP) ← imm16
-
-
-
-
-
-
-
-
-
-
MOV
A,brg1
2
*1
0
0
byte (A) ← (brg1)
Z
*
-
-
-
*
*
-
-
-
MOV
brg2,A
-
2
1
0
0
byte (brg2) ← (A)
-
-
-
-
-
*
*
-
-
NOP
1
1
0
0
No operation
-
-
-
-
-
-
-
-
-
-
ADB
1
1
0
0
Prefix code for AD space access
-
-
-
-
-
-
-
-
-
-
DTB
1
1
0
0
Prefix code for DT space access
-
-
-
-
-
-
-
-
-
-
PCB
1
1
0
0
Prefix code for PC space access
-
-
-
-
-
-
-
-
-
-
SPB
1
1
0
0
Prefix code for SP space access
-
-
-
-
-
-
-
-
-
-
NCC
1
1
0
0
Prefix code for flag unchange setting
-
-
-
-
-
-
-
-
-
-
CMR
1
1
0
0
Prefix for common register banks
-
-
-
-
-
-
-
-
-
-
*1: 1 for PCB, ADB, SSB, USB, and SPB 2 for DTB and DPR
*2: 7 + 3 × (number of POP operations) + 2 × (number of the last register that operates POP), 7 when RLST = 0 (no transfer register)
*3: 29 + 3 × (number of PUSH operations) - 3 × (number of the last register that operates PUSH), 8 when RLST = 0 (no transfer register)
*4: (number of POP operations) × c, or (number of PUSH operations) × c
*5: (number of POP operations), or (number of PUSH operations)
Note: See Table A-4 and Table A-5 for information on (a) and (c) in the table.
316
APPENDIX B F2MC-16LX Instruction Lists (351 Instructions)
Table B-16 Bit Operation Instruction: 21 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
MOVB
A,dir:bp
3
5
0
(b)
byte (A) ← (dir:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,addr16:bp
4
5
0
(b)
byte (A) ← (addr16:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,io:bp
3
4
0
(b)
byte (A) ← (io:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
dir:bp,A
3
7
0
2 × (b)
bit (dir:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
addr16:bp,A
4
7
0
2 × (b)
bit (addr16:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
MOVB
io:bp,A
3
6
0
2 × (b)
bit (io:bp)b ← (A)
-
-
-
-
-
*
*
-
-
*
SETB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
SETB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 1
-
-
-
-
-
-
-
-
-
*
CLRB
dir:bp
3
7
0
2 × (b)
bit (dir:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
addr16:bp
4
7
0
2 × (b)
bit (addr16:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
CLRB
io:bp
3
7
0
2 × (b)
bit (io:bp)b ← 0
-
-
-
-
-
-
-
-
-
*
BBC
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBS
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
io:bp,rel
4
*2
0
(b)
SBBS
addr16:bp,rel
5
*3
0
2 × (b)
Branch on (io:bp) b = 1
-
-
-
-
-
-
*
-
-
-
Branch on (addr16:bp) b = 1, bit = 1
-
-
-
-
-
-
*
-
-
*
WBTS
io:bp
3
*4
0
WBTC
io:bp
3
*4
0
*5
Waits until (io:bp) b = 1
-
-
-
-
-
-
-
-
-
-
*5
Waits until (io:bp) b = 0
-
-
-
-
-
-
-
-
-
-
RMW
*1: 8 when branch is made, 7 when branch is not made
*2: 7 when branch is made, 6 when branch is not made
*3: 10 when the condition is met, 9 when the condition is not met
*4: Undefined count
*5: Until the condition is met
Note: See Table A-5 for information on (b) in the table.
Table B-17 Accumulator Operation Instruction (Byte/Word): 6 Instructions
#
~
RG
B
LH
AH
I
S
T
N
Z
V
C
SWAP
Mnemonic
1
3
0
0
byte (A)0-7 ↔ (A)8-15
Operation
-
-
-
-
-
-
-
-
-
-
SWAPW
1
2
0
0
word (AH) ↔ (AL)
-
*
-
-
-
-
-
-
-
-
EXT
1
1
0
0
Byte signed extension
X
-
-
-
-
*
*
-
-
-
EXTW
1
2
0
0
Word signed extension
-
X
-
-
-
*
*
-
-
-
ZEXT
1
1
0
0
Byte zero extension
Z
-
-
-
-
R
*
-
-
-
ZEXTW
1
1
0
0
Word zero extension
-
Z
-
-
-
R
*
-
-
-
317
APPENDIX
Table B-18 String Instruction : 10 Instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
-
MOVS / MOVSI
2
*2
*5
*3
byte transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
MOVSD
2
*2
*5
*3
byte transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCEQ / SCEQI
2
*1
*8
*4
byte search @AH+ ← AL, counter RW0
-
-
-
-
-
*
*
*
*
-
SCEQD
2
*1
*8
*4
byte search @AH- ← AL, counter RW0
-
-
-
-
-
*
*
*
*
FILS / FILSI
2
6m+6
*8
*3
byte fill @AH+ ← AL, counter RW0
-
-
-
-
-
*
*
-
-
-
MOVSW / MOVSWI
2
*2
*5
*6
word transfer @AH+ ← @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
-
MOVSWD
2
*2
*5
*6
word transfer @AH- ← @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCWEQ / SCWEQI
2
*1
*8
*7
word search @AH+ - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCWEQD
2
*1
*8
*7
word search @AH- - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILSW / FILSWI
2
6m+6
*8
*6
word fill @AH+ ← AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
*1: 5 when RW0 is 0, 4 + 7 × (RW0) when count-out is detected, and 7n + 5 when the data in the AL register matches the byte data specified by the AH register in the space that
is specified by bank
*2: 5 when RW0 is 0, 4 + 8 × (RW0) for otherwise
*3: (b) × (RW0) + (b) × (RW0):To access different areas for sources and destinations, calculate item (b) separately each other.
*4: (b) × n
*5: 2 × (b) × (RW0)
*6: (c) × (RW0) + (c) × (RW0):To access different areas for sources and destinations, calculate item (c) separately each other.
*7: (c) × n
*8: (b) × (RW0)
Notes: • m: RW0 value (counter value), n: Number of loops
•
318
See Table A-5 for information on (b) and (c) in the table.
APPENDIX C F2MC-16LX Instruction Maps
APPENDIX C F2MC-16LX Instruction Maps
This appendix describes F2MC-16LX instruction maps.
C.1 Structure of the Instruction Map
C.2 Basic Page Map
C.3 Bit Operation Instruction Map
C.4 Character String Operation Instruction Map
C.5 2-byte Instruction Map
C.6 ea-type Instruction Map
C.7 MOVEA RWi, ea Instruction Map
C.8 MOV Ri, ea Instruction Map
C.9 MOVW RWi, ea Instruction Map
C.10 MOV ea, Ri Instruction Map
C.11 MOVW ea, RWi Instruction Map
C.12 XCH Ri, ea Instruction Map
C.13 XCHW RWi, ea Instruction Map
319
APPENDIX
C.1
Structure of the Instruction Map
Since the instruction code of the F2MC-16LX consists of one- and two-byte instructions,
the instruction map consists of more than one page that can be used for one- and twobyte instructions.
■ Structure of the Instruction Map
Figure C-1 shows the structure of the instruction map.
Figure C-1 Structure of the Instruction Map
Basic page map
Bit operation
instruction
Character string
operation
instruction
2-byte
instructions
: First byte
ea-type
instruction × 9
: Second byte
The instruction code is described on the basic page map for one-byte instructions (such as the NOP
instruction). For two-byte instructions (such as the MOVS instruction), see the basic page map to find the
name of the map that describes the second byte of the instruction code to be referenced next.
Figure C-2 shows the relationship between actual instruction codes and instruction maps.
320
APPENDIX C F2MC-16LX Instruction Maps
Figure C-2 Relationship Between Actual Instruction Codes and Instruction Maps
May not exist for
some instruction.
Instruction
code
The length varies
depending on
instructions.
First byte
Second byte
Operand
Operand
...
[Basic page map]
XY
+Z
[Extended page map]*
UV
+W
*:
Extended page map is a generic name for bit operation instruction, character string
operation instruction, 2-byte instruction, and ea-type instruction. More than one extended
page map exists for each type of instruction.
321
APPENDIX
C.2
Basic Page Map
Table C-1 shows the basic page map.
■ Basic Page Map
322
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
SWAP
ADDSP
ADB
SPB
#8
@A
A
CMP
SUBC
SUB
ADD
A, #8
A
A, #8
A, #8
A, #8
dir, A
A, dir
io, A
A, io
JMP
BRA
60
MULU
DIVU
ea
@A instruction 2
A
A, #8
MOVW
MOVX
RET
SP, A A, addr16
MOVW
MOVW
RETP
A, SP
io, #16
A0
B0
C0
D0
E0
rel
rel
LSRW
ASRW
LSLW
A
A
A
ADDSP
#16
SWAPW
ZEXTW
EXTW
MULUW
XORW
ORW
ANDW
MOVW
ea, RWi
Bit operation MOV
A instruction
ea, Ri
ORW
PUSHW
POPW
A, #16
AH
AH
ANDW
PUSHW
POPW
A, #16
A
MOVW
RWi, ea
A
NOTW
A
PUSHW
rlst
POPW
2-byte
XCHW
rlst instruction
RWi, ea
Character string XCH
XORW
PUSHW
POPW
A
A, #16
PS
PS operation
Ri, ea
instruction
A
A
CMPW
MOVL
MOVW
RETI
A
A, #16
A, #32 addr16, A
BHI
BLS
BGT
BLE
rel
rel
rel
rel
rel
rel
CMPL
CMPW
A
A, #32
BGE
rel
rel
rel
rel
rel
NEGW
BNT
BT
BNV
BV
BP
BN
BNC/BHS
rel
BC/BL0
BNZ/BNE
rel
BZ/BEQ
BLT
ea
MOVW
MOVW
MOVW
MOV A,
MOVW @R
#vct8 instruction 9
A, RWi
RWi, A RWi, #16 @RWi+d8
Wi+d8, A
ea
instruction 8
ea
instruction 7
#4
F0
MOV
MOV
CBNE A, CWBNE A, MOVW
MOVW
INTP
MOV
RP, #8
ILM, #8
#8, rel
#16, rel
A, #16 A,addr16
addr24
Ri, ea
A
90
rel
SUBL
SUBW
A, #32
NOT
XOR
MOVX
MOVX
CALLP
ea
A, #8
A, dir
A, io
addr24 instruction 6
ADDW
MOVW
MOVW
INT
A
A, #16
A, dir
A, io
A
A
OR
OR
CCR, #8
80
ea
MOV
MOV
MOV
MOV
MOVX A, MOV
CALL
rel instruction 1
A, Ri
Ri, A
Ri, #8
A, Ri @RWi+d8
A, #4
70
MOV
JMP
ea
A, addr16
addr16 instruction 3
MOV
MOV
50
MOVX
MOV
JMPP
ea
A, #8 addr16, A
adde24 instruction 4
MOV
MOV
MOV
40
SUBW
MOVW
MOVW
INT
MOVEA
A, #16
dir, A
io, A
addr16
RWi, ea
UNLINK
A
A
A, dir
A, dir
30
AND
AND
MOV
MOV
CALL
ea
CCR, #8
A, #8
dir, #8
io, #8
addr16 instruction 5
CMP
ADDC
SUB
ADD
20
ADDL
ADDW
#imm8
A, #32
ZEXT
DTB
LINK
EXT
JCTX
PCB
A
SUBDC
ADDDC
NEG
NCC
INT9
A
CMR
10
NOP
00
APPENDIX C F2MC-16LX Instruction Maps
Table C-1 Basic Page Map
Note: For the information about ea-type instruction from (1) to (9), see Table C.6,"ea-type Instruction".
323
APPENDIX
C.3
Bit Operation Instruction Map
Table C-2 shows the bit operation instruction map.
324
+F
+E
+D
+C
+B
+A
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0
10
MOVB
io:bp, A
20
30
CLRB
io:bp
40
50
SETB
io:bp
60
70
BBC
io;bp, rel
80
90
BBS
io:bp, rel
A0
B0
MOVB
MOVB A, MOVB
MOVB
CLRB
CLRB
SETB
SETB
BBC
BBC
BBS
BBS
A, dir:bp addr16:bp
dir:bp, A addr16:bp,A
dir:bp addr16:bp
dir:bp addr16:bp dir:bp, rel addr16:bp,rel dir:bp, rel addr16:bp,rel
MOVB
A, io:bp
00
WBTS
io:bp
C0
D0
WBTC
io:bp
E0
SBBS
addr16:bp
F0
APPENDIX C F2MC-16LX Instruction Maps
■ Bit Operation Instruction Map
Table C-2 Bit Operation Instruction Map (First Byte = 6CH)
325
APPENDIX
C.4
Character String Operation Instruction Map
Table C-3 shows the character string operation instruction map.
326
MOVSI
MOVSD
PCB, PCB
PCB, DTB
PCB, ADB
PCB, SPB
DTB, PCB
DTB, DTB
DTB, ADB
DTB, SPB
ADB, PCB
ADB, DTB
ADB, ADB
ADB, SPB
SPB, PCB
SPB, DTB
SPB, ADB
SPB, SPB
+1
+2
+3
+4
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
10
+0
00
MOVSWI
20
MOVSWD
30
40
50
60
70
90
A0
B0
C0
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SPB
ADB
DTB
SCEQI
SCEQD
SCWEQI SCWEQD FILSI
PCB
PCB
PCB
PCB
PCB
80
D0
FILSI
SPB
ADB
DTB
PCB
E0
F0
APPENDIX C F2MC-16LX Instruction Maps
■ Character String Operation Instruction Map
Table C-3 Character String Operation Instruction Map (First Byte = 6EH)
327
APPENDIX
C.5
2-byte Instruction Map
Table C-4 shows the 2-byte instruction map.
328
LSLW
LSLL
LSL
MOVW
MOVW
A, R0
A, R0
A, R0 @RL2+d8, A A, @RL2+d8
MOVW
MOVW
NRML
A, @A @AL, AH
A, R0
ASRW
ASRL
ASR
MOVW
MOVW
A, R0
A, R0
A, R0 @RL3+d8, A A, @RL3+d8
LSRW
LSRL
LSR
A, R0
A, R0
A, R0
+D
+E
+F
MOVW
MOVW
@RL1+d8, A A, @RL1+d8
MOVW
MOVW
@RL0+d8, A A, @RL0+d8
+C
+B
+A
+9
+8
A
MOV
MOV
MOVX
MOV
MOV
A, PCB
A, @A A, @RL3+d8 @RL3+d8, A A, @RL3+d8
+6
ROLC
MOV
MOV
A, @A @AL, AH
+5
A
MOV
MOV
MOVX
MOV
MOV
A, DPR
DPR, A A, @RL2+d8 @RL2+d8, A A, @RL2+d8
+4
ROLC
MOV
MOV
A, USB
USB, A
+3
+7
MOV
MOV
MOVX
MOV
MOV
A, SSB
SSB, A A, @RL1+d8 @RL1+d8, A A, @RL1+d8
+2
40
MOV
MOV
A, ADB
ADB, A
30
+1
20
MOV
MOV
MOVX
MOV
MOV
A, DTB
DTB, A A, @RL0+d8 @RL0+d8, A A, @RL0+d8
10
+0
00
50
DIVU
MULW
MUL
60
A
A
A
70
80
90
A0
B0
C0
D0
E0
F0
APPENDIX C F2MC-16LX Instruction Maps
■ 2-byte Instruction Map
Table C-4 2-byte Instruction Map (First Byte = 6FH)
329
APPENDIX
C.6
ea-type Instruction Map
ea-type instruction maps (first byte = 70H to first byte = 78H) are shown in the following
nine tables:
• Table C-5 for ea-type instruction (1) (first byte = 70H)
• Table C-6 for ea-type instruction (2) (first byte = 71H)
• Table C-7 for ea-type instruction (3) (first byte = 72H)
• Table C-8 for ea-type instruction (4) (first byte = 73H)
• Table C-9 for ea-type instruction (5) (first byte = 74H)
• Table C-10 for ea-type instruction (6) (first byte = 75H)
• Table C-11 for ea-type instruction (7) (first byte = 76H)
• Table C-12 for ea-type instruction (8) (first byte = 77H)
• Table C-13 for ea-type instruction (9) (first byte = 78H)
330
50
90
B0
D0
@RW1, @RW1+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
@RW2, @RW2+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
@RW3, @RW3+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
SUBL
SUBL A,
A, RL2 @RW5+d8
SUBL
SUBL A,
A, RL3 @RW6+d8
SUBL
SUBL A,
A, RL3 @RW7+d8
ADDL
ADDL A,
A, RL2 @RW5+d8
ADDL
ADDL A,
A, RL3 @RW6+d8
ADDL
ADDL A,
A, RL3 @RW7+d8
ADDL
ADDL A, SUBL
SUBL A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ADDL
ADDL A, SUBL
SUBL A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ADDL
ADDL A, SUBL
SUBL A, Use
@RW0+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW0+RW7
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
#16, rel A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 prohibited
,#8, rel
ADDL
ADDL A, SUBL
SUBL A, Use
@RW1+RW7 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
@RW1+RW7
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
#16, rel A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 prohibited
,#8, rel
ADDL
ADDL A,
A,@RW2+ @PC+d16
ADDL
ADDL A, SUBL
SUBL A, Use
A,@RW3+
addr16 A,@RW3+
addr16 prohibited
+5
+6
+7
+8
+9
+A
+B
+C
+D
+E
+F
SUBL
SUBL A,
A,@RW2+ @PC+d16
@RW0, @RW0+d16 CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A,
#16, rel
#16, rel A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
SUBL
SUBL A,
A, RL2 @RW4+d8
Use
prohibited
ANDL
ANDL A,
A,@RW2+ @PC+d16
ANDL
ANDL A,
A, RL3 @RW7+d8
ANDL
ANDL A,
A, RL3 @RW6+d8
ANDL
ANDL A,
A, RL2 @RW5+d8
ANDL
ANDL A,
A, RL2 @RW4+d8
ORL
ORL A,
A,@RW2+ @PC+d16
ORL
ORL A,
A, RL3 @RW7+d8
ORL
ORL A,
A, RL3 @RW6+d8
ORL
ORL A,
A, RL2 @RW5+d8
ORL
ORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A,@RW2+ @PC+d16
XORL
XORL A,
A, RL3 @RW7+d8
XORL
XORL A,
A, RL3 @RW6+d8
XORL
XORL A,
A, RL2 @RW5+d8
XORL
XORL A,
A, RL2 @RW4+d8
XORL
XORL A,
A, RL1 @RW3+d8
addr16,
,#8, rel
Use
@PC+d16,
prohibited
,#8, rel
@RW3, @RW3+d16
#8, rel
,#8, rel
@RW2, @RW2+d16
#8, rel
,#8, rel
@RW1, @RW1+d16
#8, rel
,#8, rel
@RW0, @RW0+d16
#8, rel
,#8, rel
R7, @RW7+d8,
#8, rel
#8, rel
R6, @RW6+d8,
#8, rel
#8, rel
R5, @RW5+d8,
#8, rel
#8, rel
R4, @RW4+d8,
#8, rel
#8, rel
R3, @RW3+d8,
#8, rel
#8, rel
addr16, CMPL
CMPL A, ANDL
ANDL A, ORL
ORL A,
XORL
XORL A, Use
#16, rel A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 prohibited
@PC+d16, CMPL
CMPL A,
#16, rel A,@RW2+ @PC+d16
RW7, @RW7+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW7+d8
RW6, @RW6+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL3 @RW6+d8
RW5, @RW5+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW5+d8
RW4, @RW4+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL2 @RW4+d8
ORL
ORL A,
A, RL1 @RW3+d8
R2, @RW2+d8,
#8, rel
#8, rel
R1, @RW1+d8,
#8, rel
#8, rel
ADDL
ADDL A,
A, RL2 @RW4+d8
ANDL
ANDL A,
A, RL1 @RW3+d8
XORL
XORL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW1+d8
+4
RW3, @RW3+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW3+d8
ORL
ORL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW1+d8
SUBL
SUBL A,
A, RL1 @RW3+d8
ANDL
ANDL A,
A, RL1 @RW2+d8
ANDL
ANDL A,
A, RL0 @RW1+d8
ADDL
ADDL A,
A, RL1 @RW3+d8
RW2, @RW2+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL1 @RW2+d8
RW1, @RW1+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW1+d8
+3
CBNE ↓
F0
R0, @RW0+d8,
#8, rel
#8, rel
CBNE ↓
E0
SUBL
SUBL A,
A, RL1 @RW2+d8
XORL
XORL A,
A, RL0 @RW0+d8
C0
ADDL
ADDL A,
A, RL1 @RW2+d8
ORL
ORL A,
A, RL0 @RW0+d8
A0
+2
ANDL
ANDL A,
A, RL0 @RW0+d8
80
SUBL
SUBL A,
A, RL0 @RW1+d8
70
ADDL
ADDL A,
A, RL0 @RW1+d8
60
RW0, @RW0+d8 CMPL
CMPL A,
#16, rel
#16, rel
A, RL0 @RW0+d8
CWBNE ↓ CWBNE ↓
40
+1
30
+0
20
SUBL
SUBL A,
A, RL0 @RW0+d8
10
ADDL
ADDL A,
A, RL0 @RW0+d8
00
APPENDIX C F2MC-16LX Instruction Maps
■ ea-type Instruction Map
Table C-5 ea-byte Instruction (1) (First Byte = 70H)
331
332
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW7+d8
@RL3 @@RW7+d8
RL3 @RW7+d8
RL3 @RW7+d8
A, RL3 @RW7+d8
RL3, A @RW7+d8,A
R7, #8 @RW7+d8,#8
A, RW7 @RW7+d8
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #8 @RW0+d16,#8
A,@RW0 @RW0+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1,A @RW1+d16,A @RW1, #8 @RW1+d16,#8
A,@RW1 @RW1+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2,A @RW2+d16,A @RW2, #8 @RW2+d16,#8
A,@RW2 @RW2+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3,A @RW3+d16,A @RW3, #8 @RW3+d16,#8
A,@RW3 @RW3+d16
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+,A @RW0+RW7,A @RW0+, #8 @RW0+RW7,#8 A,@RW0+ @RW0+RW7
JMPP
JMPP @
CALLP
CALLP @
INCL
INCL
DECL
DECL
MOVL
MOVL A,
MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+,A @RW1+RW7,A @RW1+, #8 @RW1+RW7,#8 A,@RW1+ @RW1+RW7
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+,A @PC+d16, A @RW2+, #8 @PC+d16, #8 A,@RW2+ @PC+d16
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+,A
addr16, A @RW3+, #8
addr16, #8 A,@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL3 @@RW6+d8
@RL3 @@RW6+d8
RL3 @RW6+d8
RL3 @RW6+d8
A, RL3 @RW6+d8
RL3, A @RW6+d8,A
R6, #8 @RW6+d8,#8
A, RW6 @RW6+d8
D0
+6
C0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW5+d8
@RL2 @@RW5+d8
RL2 @RW5+d8
RL2 @RW5+d8
A, RL2 @RW5+d8
RL2, A @RW5+d8,A
R5, #8 @RW5+d8,#8
A, RW5 @RW5+d8
B0
+5
A0
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL2 @@RW4+d8
@RL2 @@RW4+d8
RL2 @RW4+d8
RL2 @RW4+d8
A, RL2 @RW4+d8
RL2, A @RW4+d8,A
R4, #8 @RW4+d8,#8
A, RW4 @RW4+d8
90
+4
80
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW3+d8
@RL1 @@RW3+d8
RL1 @RW3+d8
RL1 @RW3+d8
A, RL1 @RW3+d8
RL1, A @RW3+d8,A
R3, #8 @RW3+d8,#8
A, RW3 @RW3+d8
70
+3
60
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL1 @@RW2+d8
@RL1 @@RW2+d8
RL1 @RW2+d8
RL1 @RW2+d8
A, RL1 @RW2+d8
RL1, A @RW2+d8,A
R2, #8 @RW2+d8,#8
A, RW2 @RW2+d8
50
+2
40
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW1+d8
@RL0 @@RW1+d8
RL0 @RW1+d8
RL0 @RW1+d8
A, RL0 @RW1+d8
RL0, A @RW1+d8,A
R1, #8 @RW1+d8,#8
A, RW1 @RW1+d8
30
+1
20
JMPP
JMPP
CALLP
CALLP
INCL
INCL
DECL
DECL
MOVL
MOVL A, MOVL
MOVL
MOV
MOV
MOVEA
MOVEA A,
@RL0 @@RW0+d8
@RL0 @@RW0+d8
RL0 @RW0+d8
RL0 @RW0+d8
A, RL0 @RW0+d8
RL0, A @RW0+d8,A
R0, #8 @RW0+d8,#8
A, RW0 @RW0+d8
10
+0
00
APPENDIX
Table C-6 ea-type Instruction (2) (First Byte = 71H)
D0
E0
F0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV A,
MOV
MOV
MOVX
MOVX A,
XCH
XCH A,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A A,@RW3+
addr16 A,@RW3+
addr16
+D
+E
+F
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R7 @RW7+d8
A, R7 @RW7+d8
R7, A @RW7+d8,A
A, R7 @RW7+d8
A, R7 @RW7+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R6 @RW6+d8
A, R6 @RW6+d8
R6, A @RW6+d8,A
A, R6 @RW6+d8
A, R6 @RW6+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R5 @RW5+d8
A, R5 @RW5+d8
R5, A @RW5+d8,A
A, R5 @RW5+d8
A, R5 @RW5+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R4 @RW4+d8
A, R4 @RW4+d8
R4, A @RW4+d8,A
A, R4 @RW4+d8
A, R4 @RW4+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R3 @RW3+d8
A, R3 @RW3+d8
R3, A @RW3+d8,A
A, R3 @RW3+d8
A, R3 @RW3+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R2 @RW2+d8
A, R2 @RW2+d8
R2, A @RW2+d8,A
A, R2 @RW2+d8
A, R2 @RW2+d8
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R1 @RW1+d8
A, R1 @RW1+d8
R1, A @RW1+d8,A
A, R1 @RW1+d8
A, R1 @RW1+d8
+C
INC
DEC
R7 @RW7+d8
C0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
ROLC
RORC
RORC
INC
R7 @RW7+d8
R7 @RW7+d8
ROLC
INC
DEC
R6 @RW6+d8
B0
+B
ROLC
RORC
RORC
INC
R6 @RW6+d8
R6 @RW6+d8
ROLC
INC
DEC
R5 @RW5+d8
A0
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
ROLC
RORC
RORC
INC
R5 @RW5+d8
R5 @RW5+d8
ROLC
INC
DEC
R4 @RW4+d8
90
+A
ROLC
RORC
RORC
INC
R4 @RW4+d8
R4 @RW4+d8
ROLC
INC
DEC
R3 @RW3+d8
INC
DEC
R2 @RW2+d8
INC
DEC
R1 @RW1+d8
80
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
R0 @RW0+d8
A, R0 @RW0+d8
R0, A @RW0+d8,A
A, R0 @RW0+d8
A, R0 @RW0+d8
70
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
ROLC
RORC
RORC
INC
R3 @RW3+d8
R3 @RW3+d8
ROLC
60
INC
DEC
R0 @RW0+d8
50
+9
ROLC
RORC
RORC
INC
R2 @RW2+d8
R2 @RW2+d8
ROLC
40
ROLC
ROLC
RORC
RORC
INC
INC
DEC
DEC
MOV
MOV
A, MOV
MOV
MOVX
MOVX A, XCH
XCH
A,
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0, A @RW0+d16,A
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ROLC
RORC
RORC
INC
R1 @RW1+d8
R1 @RW1+d8
ROLC
30
ROLC
RORC
RORC
INC
R0 @RW0+d8
R0 @RW0+d8
20
ROLC
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX C F2MC-16LX Instruction Maps
Table C-7 ea-type Instruction (3) (First Byte = 72H)
333
334
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3 @RW3+d16 @@RW3 @RW3+d16 @RW3 @RW3+d16
@RW3 @RW3+d16 A,@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, #16 @RW3+d16,#16 A,@RW3 @RW3+d16
+B
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW3+ @addr16 @@RW3+ @addr16 @RW3+
addr16 @RW3+
addr16 A,@RW3+
addr16 @RW3+, A
addr16, A @RW3+, #16
addr16, #16 A,@RW3+
addr16
INCW @
+F
INCW
JMP
JMP
CALL
CALL
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2+ @@PC+d16 @@RW2+ @@PC+d16 @RW2+ @@PC+d16
@RW2+ @PC+d16 A,@RW2+ @PC+d16 @RW2+, A @PC+d16, A @RW2+, #16 @PC+d16, #16 A,@RW2+ @PC+d16
CALL @
+E
CALL
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, #16 @RW1+RW7,#16 A,@RW1+ @RW1+RW7
XCHW
XCHW A,
A, RW7 @RW7+d8
XCHW
XCHW A,
A, RW6 @RW6+d8
XCHW
XCHW A,
A, RW5 @RW5+d8
+D @@RW1+ @RW1+RW7 @@RW1+ @RW1+RW7 @RW1+ @RW1+RW7
INCW @
MOVW
MOVW
RW7, #16 @RW7+d8,#16
MOVW
MOVW
RW6, #16 @RW6+d8,#16
MOVW
MOVW
RW5, #16 @RW5+d8,#16
XCHW
XCHW A,
A, RW4 @RW4+d8
DECW
DECW
MOVW
MOVW A,
MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, #16 @RW0+RW7,#16 A,@RW0+ @RW0+RW7
INCW
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW7 @RW7+d8
RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, A @RW7+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW6 @RW6+d8
RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, A @RW6+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW5 @RW5+d8
RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, A @RW5+d8,A
MOVW
MOVW
RW4, #16 @RW4+d8,#16
+C @@RW0+ @RW0+RW7 @@RW0+ @RW0+RW7 @RW0+ @RW0+RW7
JMP @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW2 @RW2+d16 @@RW2 @RW2+d16 @RW2 @RW2+d16
@RW2 @RW2+d16 A,@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, #16 @RW2+d16,#16 A,@RW2 @RW2+d16
+A
JMP
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW1 @RW1+d16 @@RW1 @RW1+d16 @RW1 @RW1+d16
@RW1 @RW1+d16 A,@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, #16 @RW1+d16,#16 A,@RW1 @RW1+d16
+9
CALL @
JMP
JMP @
CALL
CALL @
INCW
INCW @ DECW
DECW
MOVW
MOVW A, MOVW
MOVW
MOVW
MOVW
XCHW
XCHW A,
@@RW0 @RW0+d16 @@RW0 @RW0+d16 @RW0 @RW0+d16
@RW0 @RW0+d16 A,@RW0 @RW0+d16 @RW0,A @RW0+d16,A @RW0, #16 @RW0+d16,#16 A,@RW0 @RW0+d16
+8
CALL
CALL
CALL
RW7 @@RW7+d8
JMP
JMP
@RW7 @@RW7+d8
+7
JMP @
CALL
CALL
RW6 @@RW6+d8
JMP
JMP
@RW6 @@RW6+d8
+6
JMP
CALL
CALL
RW5 @@RW5+d8
JMP
JMP
@RW5 @@RW5+d8
+5
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW4 @RW4+d8
RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, A @RW4+d8,A
XCHW
XCHW A,
A, RW3 @RW3+d8
XCHW
XCHW A,
A, RW2 @RW2+d8
XCHW
XCHW A,
A, RW1 @RW1+d8
CALL
CALL
RW4 @@RW4+d8
MOVW
MOVW
RW3, #16 @RW3+d8,#16
MOVW
MOVW
RW2, #16 @RW2+d8,#16
MOVW
MOVW
RW1, #16 @RW1+d8,#16
JMP
JMP
@RW4 @@RW4+d8
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW3 @RW3+d8
RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, A @RW3+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW2 @RW2+d8
RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, A @RW2+d8,A
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW1 @RW1+d8
RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, A @RW1+d8,A
+4
F0
XCHW
XCHW A,
A, RW0 @RW0+d8
E0
CALL
CALL
RW3 @@RW3+d8
D0
MOVW
MOVW
RW0, #16 @RW0+d8,#16
C0
JMP
JMP
@RW3 @@RW3+d8
B0
+3
A0
CALL
CALL
RW2 @@RW2+d8
90
JMP
JMP
@RW2 @@RW2+d8
80
+2
70
CALL
CALL
RW1 @@RW1+d8
60
JMP
JMP
@RW1 @@RW1+d8
50
INCW
INCW
DECW
DECW
MOVW
MOVW A, MOVW
MOVW
RW0 @RW0+d8
RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, A @RW0+d8,A
40
+1
30
CALL
CALL
RW0 @@RW0+d8
20
JMP
JMP
@RW0 @@RW0+d8
10
+0
00
APPENDIX
Table C-8 ea-type Instruction (4) (First Byte = 73H)
ADD
A, SUB
SUB
SUB
ADDC
A, ADDC
A,
ADDC
ADDC A,
A, CMP
CMP
CMP
CMP
A,
A,
A, AND
AND
AND
AND
AND
AND
A,
A,
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r PC+d16, r
+F A,@RW3+
ADD
ADD
SUB
SUB
ADDC
ADDC
CMP
CMP
AND
AND
OR
OR
XOR
XOR
DBNZ
DBNZ
A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+ A, addr16 A,@RW3+
A, addr16 A,@RW3+ A, addr16 @RW3+, r
addr16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
ADD
SUB
CMP
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW1+ @RW1+RW7 @RW1+, r W1+RW7, r
A,
CMP
OR
OR
A,
A,@RW1+ @RW1+RW7
ADD
ADD
ADDC A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
ADDC
XOR
XOR A,
DBNZ
DBNZ @R
A,@RW0+ @RW0+RW7 @RW0+, r W0+RW7, r
A,
OR
OR
A,
A,@RW0+ @RW0+RW7
SUB
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
SUB
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW3 @RW3+d16 @RW3, r W3+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
A,
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW2 @RW2+d16 @RW2, r W2+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW1 @RW1+d16 @RW1, r W1+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADD
XOR
XOR
A, DBNZ
DBNZ @R
A,@RW0 @RW0+d16 @RW0, r W0+d16, r
ADD
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
A, R7 @RW7+d8
R7, r RW7+d8, r
ADD
F0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
A, R6 @RW6+d8
R6, r RW6+d8, r
E0
ADD
D0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
A, R5 @RW5+d8
R5, r RW5+d8, r
C0
ADD
B0
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
A, R4 @RW4+d8
R4, r RW4+d8, r
A0
ADD
90
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
A, R3 @RW3+d8
R3, r RW3+d8, r
80
ADD
70
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
A, R2 @RW2+d8
R2, r RW2+d8, r
60
ADD
50
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
A, R1 @RW1+d8
R1, r RW1+d8, r
40
ADD
30
ADD
A, SUB
SUB
A, ADDC
ADDC A, CMP
CMP
A, AND
AND
A, OR
OR
A, XOR
XOR
A, DBNZ
DBNZ @
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
A, R0 @RW0+d8
R0, r RW0+d8, r
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX C F2MC-16LX Instruction Maps
Table C-9 ea-type Instruction (5) (First Byte = 74H)
335
336
NOT
NOT
R2 @RW2+d8
SUB
SUB
SUB
SUB
ADD
SUB
SUB
@RW1+RW7,A @RW1+, A @RW1+RW7,A
ADD @R
@RW0+RW7,A @RW0+, A @RW0+RW7,A
ADD @R
+F
ADD
ADD
@RW3+, A addr16, A
SUB
SUB
@RW3+, A addr16, A
+E @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
ADD
+D @RW1+, A
ADD
+C @RW0+, A
ADD
NOT
NOT
@RW1+ @RW1+RW7
NOT
NOT
@RW0+ @RW0+RW7
SUBC
SUBC A, NEG
NEG A,
AND
AND
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
OR
OR
@RW3+, A addr16, A
XOR
XOR
@RW3+, A addr16, A
NOT
NOT
@RW3+
addr16
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
NOT
NOT
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+ @PC+d16
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A
SUBC
SUBC A,
NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A
NOT
NOT
@RW3 @RW3+d16
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
+B
XOR
NOT
NOT
R7, A @RW7+d8, A
R7 @RW7+d8
XOR
NOT
NOT
R6, A @RW6+d8, A
R6 @RW6+d8
XOR
NOT
NOT
R5, A @RW5+d8, A
R5 @RW5+d8
XOR
NOT
NOT
R4, A @RW4+d8, A
R4 @RW4+d8
XOR
NOT
NOT
R3, A @RW3+d8, A
R3 @RW3+d8
XOR
R2, A @RW2+d8,A
XOR
NOT
NOT
R1, A @RW1+d8, A
R1 @RW1+d8
NOT
NOT
@RW2 @RW2+d16
XOR
F0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
NEG A,
AND
AND
OR
OR
R7 @RW7+d8
R7, A @RW7+d8, A
R7, A @RW7+d8, A
XOR
XOR
XOR
XOR
XOR
XOR
E0
XOR
NOT
NOT
R0, A @RW0+d8, A
R0 @RW0+d8
D0
+A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R7, A @RW7+d8, A
R7, A @RW7+d8, A
A, R7 @RW7+d8
ADD
NEG A,
AND
AND
OR
OR
R6 @RW6+d8
R6, A @RW6+d8, A
R6, A @RW6+d8, A
NEG A,
AND
AND
OR
OR
R5 @RW5+d8
R5, A @RW5+d8, A
R5, A @RW5+d8, A
NEG A,
AND
AND
OR
OR
R4 @RW4+d8
R4, A @RW4+d8, A
R4, A @RW4+d8, A
NEG A,
AND
AND
OR
OR
R3 @RW3+d8
R3, A @RW3+d8, A
R3, A @RW3+d8, A
NEG A,
AND
AND
OR
OR
R2 @RW2+d8
R2, A @RW2+d8,A
R2, A @RW2+d8,A
NEG A,
AND
AND
OR
OR
R1 @RW1+d8
R1, A @RW1+d8, A
R1, A @RW1+d8, A
XOR
C0
NOT
NOT
@RW1 @RW1+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R6, A @RW6+d8, A
R6, A @RW6+d8, A
A, R6 @RW6+d8
ADD
B0
ADD
ADD @R
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R5, A @RW5+d8, A
R5, A @RW5+d8, A
A, R5 @RW5+d8
ADD
A0
+9
ADD
SUB
SUB
SUBC
SUBC A, NEG
R4, A @RW4+d8, A
R4, A @RW4+d8, A
A, R4 @RW4+d8
ADD
90
NOT
NOT
@RW0 @RW0+d16
ADD
SUB
SUB
SUBC
SUBC A, NEG
R3, A @RW3+d8, A
R3, A @RW3+d8, A
A, R3 @RW3+d8
ADD
80
NEG A,
AND
AND
OR
OR
R0 @RW0+d8
R0, A @RW0+d8, A
R0, A @RW0+d8, A
70
ADD
ADD
SUB
SUB
SUBC
SUBC A, NEG
NEG A,
AND
AND
OR
OR
XOR
XOR
@RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
ADD
SUB
SUB
SUBC
SUBC A, NEG
R2, A @RW2+d8,A
R2, A @RW2+d8,A
A, R2 @RW2+d8
60
ADD
50
ADD
SUB
SUB
SUBC
SUBC A, NEG
R1, A @RW1+d8, A
R1, A @RW1+d8, A
A, R1 @RW1+d8
40
ADD
30
ADD
SUB
SUB
SUBC
SUBC A, NEG
R0, A @RW0+d8, A
R0, A @RW0+d8, A
A, R0 @RW0+d8
20
ADD
10
+8
+7
+6
+5
+4
+3
+2
+1
+0
00
APPENDIX
Table C-10 ea-type Instruction (6) (First Byte = 75H)
ADDW A, SUBW
ADDW
ADDCW
CMPW
ADDCW A, CMPW
ADDCW A,
ANDW
CMPW A, ANDW
CMPW A,
ORW
ORW
ANDW A, ORW
ANDW A,
ANDW A,
ORW
ORW
ORW
A,
A,
A, XORW
XORW A, DWBNZ
DWBNZ
+F A,@RW3+
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
addr 16 A,@RW3+ addr 16
A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr 16 A,@RW3+
addr r16 A,@RW3+
addr 16 @RW3+, r addr r16, r
+E A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16, A,@RW2+ @PC+d16 @RW2+, r @PC+d16,r
SUBW A, ADDCW
SUBW A,
ANDW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW1+ @RW1+RW7 @RW1+, r @RW1+RW7,r
SUBW
ADDW A,
ADDW
CMPW A,
+D A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
CMPW
XORW
XORW A,
DWBNZ
DWBNZ
A,@RW0+ @RW0+RW7 @RW0+, r @RW0+RW7,r
ADDCW A,
+C A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
ADDCW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW3 @RW3+d16 @RW3, r @RW3+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
+B
SUBW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW2 @RW2+d16 @RW2, r @RW2+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
+A
SUBW
XORW
XORW A, DWBNZ
DWBNZ
A,@RW1 @RW1+d16 @RW1, r @RW1+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
+9
ADDW A,
XORW
XORW A, DWBNZ
DWBNZ
A,@RW0 @RW0+d16 @RW0, r @RW0+d16,r
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
ADDW
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
A, RW7 @RW7+d8
RW7, r @RW7+d8,r
F0
+7
E0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
A, RW6 @RW6+d8
RW6, r @RW6+d8,r
D0
+6
C0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
A, RW5 @RW5+d8
RW5, r @RW5+d8,r
B0
+5
A0
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
A, RW4 @RW4+d8
RW4, r @RW4+d8,r
90
+4
80
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
A, RW3 @RW3+d8
RW3, r @RW3+d8,r
70
+3
60
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
A, RW2 @RW2+d8
RW2, r @RW2+d8,r
50
+2
40
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
A, RW1 @RW1+d8
RW1, r @RW1+d8,r
30
+1
20
ADDW
ADDW A, SUBW
SUBW A, ADDCW
ADDCW A, CMPW
CMPW A, ANDW
ANDW A, ORW
ORW
A, XORW
XORW A, DWBNZ
DWBNZ
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
A, RW0 @RW0+d8
RW0, r @RW0+d8,r
10
+0
00
APPENDIX C F2MC-16LX Instruction Maps
Table C-11 ea-type Instruction (7) (First Byte = 76H)
337
338
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW3 @RW3+d16 @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A
@RW3 @RW3+d16
SUBW
SUBW
@RW3+, A addr16, A
ADDW
ADDW
@RW3+, A addr16, A
+F
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
A,@RW3+
addr16 @RW3+
addr16 @RW3+, A addr16, A
ORW
ORW
@RW3+, A addr16, A
XORW
XORW
@RW3+, A addr16, A
NOTW
NOTW
@RW3+
addr16
SUBCW
SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
A,@RW2+ @PC+d16
@RW2+ @PC+d16 @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A @RW2+, A @PC+d16,A
@RW2+ @PC+d16
SUBW
SUBW
@RW2+, A @PC+d16,A
ADDW
ADDW
@RW2+, A @PC+d16,A
+E
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A A,@RW1+ @RW1+RW7 @RW1+ @RW1+RW7 @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+, A @RW1+RW7,A @RW1+ @RW1+RW7
SUBCW
+D
SUBW
SUBCW A,
ADDW
ADDW
SUBW
SUBW
SUBCW
SUBCW A,
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A A,@RW0+ @RW0+RW7 @RW0+ @RW0+RW7 @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+, A @RW0+RW7,A @RW0+ @RW0+RW7
SUBW
SUBCW
+C
ADDW
ADDW
SUBW
SUBCW A,
+B @RW3, A @RW3+d16,A @RW3, A @RW3+d16,A A, @RW3 @RW3+d16
SUBW
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW2 @RW2+d16 @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A
@RW2 @RW2+d16
ADDW
ADDW
SUBW
+A @RW2, A @RW2+d16,A @RW2, A @RW2+d16,A A, @RW2 @RW2+d16
SUBW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW1 @RW1+d16 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A
@RW1 @RW1+d16
ADDW
ADDW
SUBCW A,
+9 @RW1, A @RW1+d16,A @RW1, A @RW1+d16,A A, @RW1 @RW1+d16
SUBCW
NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
NOTW
NOTW
@RW0 @RW0+d16 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A
@RW0 @RW0+d16
SUBW
NOTW
NOTW
RW7 @RW7+d8
NOTW
NOTW
RW6 @RW6+d8
NOTW
NOTW
RW5 @RW5+d8
+8 @RW0, A @RW0+d16,A @RW0, A @RW0+d16,A A, @RW0 @RW0+d16
SUBW
XORW
XORW
RW7, A @RW7+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
A, RW7 @RW7+d8
RW7 @RW7+d8
RW7, A @RW7+d8, A
RW7, A @RW7+d8, A
+7
ADDW
XORW
XORW
RW6, A @RW6+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
A, RW6 @RW6+d8
RW6 @RW6+d8
RW6, A @RW6+d8, A
RW6, A @RW6+d8, A
+6
ADDW
XORW
XORW
RW5, A @RW5+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
A, RW5 @RW5+d8
RW5 @RW5+d8
RW5, A @RW5+d8, A
RW5, A @RW5+d8, A
+5
NOTW
NOTW
RW4 @RW4+d8
XORW
XORW
RW4, A @RW4+d8, A
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
A, RW4 @RW4+d8
RW4 @RW4+d8
RW4, A @RW4+d8, A
RW4, A @RW4+d8, A
+4
F0
NOTW
NOTW
RW0 @RW0+d8
E0
NOTW
NOTW
RW3 @RW3+d8
D0
XORW
XORW
RW3, A @RW3+d8, A
C0
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
A, RW3 @RW3+d8
RW3 @RW3+d8
RW3, A @RW3+d8, A
RW3, A @RW3+d8, A
B0
+3
A0
NOTW
NOTW
RW2 @RW2+d8
90
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
XORW
XORW
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
A, RW2 @RW2+d8
RW2 @RW2+d8
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
RW2, A @RW2+d8,A
80
+2
70
NOTW
NOTW
RW1 @RW1+d8
60
XORW
XORW
RW1, A @RW1+d8, A
50
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
A, RW1 @RW1+d8
RW1 @RW1+d8
RW1, A @RW1+d8, A
RW1, A @RW1+d8, A
40
+1
30
XORW
XORW
RW0, A @RW0+d8, A
20
ADDW
ADDW
SUBW
SUBW
SUBCW SUBCW A, NEGW
NEGW
ANDW
ANDW
ORW
ORW
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
A, RW0 @RW0+d8
RW0 @RW0+d8
RW0, A @RW0+d8, A
RW0, A @RW0+d8, A
10
+0
00
APPENDIX
Table C-12 ea-type Instruction (8) (First Byte = 77H)
DIV
DIV
A, DIVW
DIVW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
DIV
DIV
A, DIVW
DIVW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW MULUW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
MULU
MULU A, MULUW MULUW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
MULU
MULU A, MULUW MULUW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7 A,@RW0+ @RW0+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL A,
MULW
MULW A,
DIVU
DIVU A,
DIVUW
DIVUW A,
A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7 A,@RW1+ @RW1+RW7
MULU
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16 A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
A,@RW2+ @PC+d16
+9
+A
+B
+C
+D
+E
+F A, @RW3+
MULU
DIV
DIV
A, DIVW
DIVW A,
A,@RW3 @RW3+d16 A,@RW3 @RW3+d16
MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A,
A, @RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
+8
MULU A, MULUW
MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
addr16 A,@RW3+ addr16
A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
addr16 A,@RW3+
A, DIVW
DIVW A,
addr16 A,@RW3+
addr16
DIV
DIV
A, DIVW
DIVW A,
A,@RW2 @RW2+d16 A,@RW2 @RW2+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW1 @RW1+d16 A,@RW1 @RW1+d16
DIV
DIV
A, DIVW
DIVW A,
A,@RW0 @RW0+d16 A,@RW0 @RW0+d16
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
A, R7 @RW7+d8
A, RW7 @RW7+d8
F0
+7
E0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
A, R6 @RW6+d8
A, RW6 @RW6+d8
D0
+6
C0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
A, R5 @RW5+d8
A, RW5 @RW5+d8
B0
+5
A0
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
A, R4 @RW4+d8
A, RW4 @RW4+d8
90
+4
80
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
A, R3 @RW3+d8
A, RW3 @RW3+d8
70
+3
60
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
A, R2 @RW2+d8
A, RW2 @RW2+d8
50
+2
40
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
A, R1 @RW1+d8
A, RW1 @RW1+d8
30
+1
20
MULU
MULU A, MULUW MULUW A, MUL
MUL
A, MULW
MULW A, DIVU
DIVU
A, DIVUW
DIVUW A, DIV
DIV
A, DIVW
DIVW A,
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
A, R0 @RW0+d8
A, RW0 @RW0+d8
10
+0
00
APPENDIX C F2MC-16LX Instruction Maps
Table C-13 ea-type Instruction (9) (First Byte = 78H)
339
APPENDIX
C.7
MOVEA RWi, ea Instruction Map
Table C-14 lists MOVEA RWi, ea instruction map.
340
MOVEA
MOVEA RW1
RW1,RW4 ,@RW4+d8
MOVEA
MOVEA RW1
RW1,RW5 ,@RW5+d8
MOVEA
MOVEA RW1
RW1,RW6 ,@RW6+d8
MOVEA
MOVEA RW1
RW1,RW7 ,@RW7+d8
MOVEA
MOVEA RW1
RW1,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,@RW1 ,@RW1+d16
MOVEA
MOVEA RW1
RW1,@RW2 ,@RW2+d16
MOVEA
MOVEA RW1
RW1,@RW3 ,@RW3+d16
MOVEA
MOVEA RW0
RW0,RW4 ,@RW4+d8
MOVEA
MOVEA RW0
RW0,RW5 ,@RW5+d8
MOVEA
MOVEA RW0
RW0,RW6 ,@RW6+d8
MOVEA
MOVEA RW0
RW0,RW7 ,@RW7+d8
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA RW0
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
+4
+5
+6
+7
50
70
90
B0
C0
D0
F0
MOVEA
MOVEA RW3
RW3,@RW2+ ,@PC+d16
MOVEA
MOVEA RW4
RW4,@RW2+ ,@PC+d16
MOVEA
MOVEA RW7
RW7,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
RW6,@RW3+ RW6, addr16 RW7@RW3+ RW7, addr16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2+ ,@PC+d16
RW6,@RW2+ ,@PC+d16
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
MOVEA
RW0,@RW3+ RW0, addr16 RW1,@RW3+ RW1, addr16 RW2,@RW3+ RW2, addr16 RW3,@RW3+ RW3, addr16 RW4,@RW3+ RW4, addr16 RW5,@RW3+ RW5, addr16
MOVEA
MOVEA RW2
RW2,@RW2+ ,@PC+d16
+F
MOVEA
MOVEA RW1
RW1,@RW2+ ,@PC+d16
MOVEA
MOVEA RW0
RW0,@RW2+ ,@PC+d16
MOVEA RW1
+E
MOVEA
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW1+ ,@RW1+RW7 RW6,@RW1+ ,@RW1+RW7 RW7,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW7
RW7,@RW3 ,@RW3+d16
MOVEA
MOVEA RW7
RW7,@RW2 ,@RW2+d16
MOVEA
MOVEA RW7
RW7,@RW1 ,@RW1+d16
MOVEA
MOVEA RW7
RW7,@RW0 ,@RW0+d16
MOVEA
MOVEA RW7
RW7,RW7 ,@RW7+d8
MOVEA
MOVEA RW7
RW7,RW6 ,@RW6+d8
MOVEA
MOVEA RW7
RW7,RW5 ,@RW5+d8
MOVEA
MOVEA RW7
RW7,RW4 ,@RW4+d8
MOVEA
MOVEA RW7
RW7,RW3 ,@RW3+d8
MOVEA
MOVEA RW7
RW7,RW2 ,@RW2+d8
MOVEA
MOVEA RW7
RW7,RW1 ,@RW1+d8
MOVEA
MOVEA RW7
RW7,RW0 ,@RW0+d8
E0
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW1+ ,@RW1+RW7 RW3,@RW1+ ,@RW1+RW7 RW4,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW3 ,@RW3+d16 RW6,@RW3 ,@RW3+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW2 ,@RW2+d16 RW6,@RW2 ,@RW2+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW1 ,@RW1+d16 RW6,@RW1 ,@RW1+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,@RW0 ,@RW0+d16 RW6,@RW0 ,@RW0+d16
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW7 ,@RW7+d8
RW6,RW7 ,@RW7+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW6 ,@RW6+d8
RW6,RW6 ,@RW6+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW5 ,@RW5+d8
RW6,RW5 ,@RW5+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW4 ,@RW4+d8
RW6,RW4 ,@RW4+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW3 ,@RW3+d8
RW6,RW3 ,@RW3+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW2 ,@RW2+d8
RW6,RW2 ,@RW2+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW1 ,@RW1+d8
RW6,RW1 ,@RW1+d8
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6
RW5,RW0 ,@RW0+d8
RW6,RW0 ,@RW0+d8
A0
+D RW0,@RW1+ ,@RW1+RW7 RW1,@RW1+ ,@RW1+RW7
MOVEA
MOVEA RW4
RW4,@RW3 ,@RW3+d16
MOVEA
MOVEA RW4
RW4,@RW2 ,@RW2+d16
MOVEA
MOVEA RW4
RW4,@RW1 ,@RW1+d16
MOVEA
MOVEA RW4
RW4,@RW0 ,@RW0+d16
MOVEA
MOVEA RW4
RW4,RW7 ,@RW7+d8
MOVEA
MOVEA RW4
RW4,RW6 ,@RW6+d8
MOVEA
MOVEA RW4
RW4,RW5 ,@RW5+d8
MOVEA
MOVEA RW4
RW4,RW4 ,@RW4+d8
MOVEA
MOVEA RW4
RW4,RW3 ,@RW3+d8
MOVEA
MOVEA RW4
RW4,RW2 ,@RW2+d8
MOVEA
MOVEA RW4
RW4,RW1 ,@RW1+d8
MOVEA
MOVEA RW4
RW4,RW0 ,@RW0+d8
80
MOVEA
MOVEA RW5 MOVEA
MOVEA RW6 MOVEA
MOVEA RW7
RW5,@RW0+ ,@RW0+RW7 RW6,@RW0+ ,@RW0+RW7 RW7,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW3
RW3,@RW3 ,@RW3+d16
MOVEA
MOVEA RW3
RW3,@RW2 ,@RW2+d16
MOVEA
MOVEA RW3
RW3,@RW1 ,@RW1+d16
MOVEA
MOVEA RW3
RW3,@RW0 ,@RW0+d16
MOVEA
MOVEA RW3
RW3,RW7 ,@RW7+d8
MOVEA
MOVEA RW3
RW3,RW6 ,@RW6+d8
MOVEA
MOVEA RW3
RW3,RW5 ,@RW5+d8
MOVEA
MOVEA RW3
RW3,RW4 ,@RW4+d8
MOVEA
MOVEA RW3
RW3,RW3 ,@RW3+d8
MOVEA
MOVEA RW3
RW3,RW2 ,@RW2+d8
MOVEA
MOVEA RW3
RW3,RW1 ,@RW1+d8
MOVEA
MOVEA RW3
RW3,RW0 ,@RW0+d8
60
MOVEA
MOVEA RW2 MOVEA
MOVEA RW3 MOVEA
MOVEA RW4
RW2,@RW0+ ,@RW0+RW7 RW3,@RW0+ ,@RW0+RW7 RW4,@RW0+ ,@RW0+RW7
MOVEA
MOVEA RW2
RW2,@RW3 ,@RW3+d16
MOVEA
MOVEA RW2
RW2,@RW2 ,@RW2+d16
MOVEA
MOVEA RW2
RW2,@RW1 ,@RW1+d16
MOVEA
MOVEA RW2
RW2,@RW0 ,@RW0+d16
MOVEA
MOVEA RW2
RW2,RW7 ,@RW7+d8
MOVEA
MOVEA RW2
RW2,RW6 ,@RW6+d8
MOVEA
MOVEA RW2
RW2,RW5 ,@RW5+d8
MOVEA
MOVEA RW2
RW2,RW4 ,@RW4+d8
MOVEA
MOVEA RW2
RW2,RW3 ,@RW3+d8
MOVEA
MOVEA RW2
RW2,RW2 ,@RW2+d8
MOVEA
MOVEA RW2
RW2,RW1 ,@RW1+d8
MOVEA
MOVEA RW2
RW2,RW0 ,@RW0+d8
40
+C RW0,@RW0+ ,@RW0+RW7 RW1,@RW0+ ,@RW0+RW7
+B RW0,@RW3 ,@RW3+d16
+A RW0,@RW2 ,@RW2+d16
+9 RW0,@RW1 ,@RW1+d16
MOVEA RW1
MOVEA
MOVEA RW1
RW1,RW3 ,@RW3+d8
MOVEA
MOVEA RW0
RW0,RW3 ,@RW3+d8
+3
MOVEA
MOVEA
MOVEA RW1
RW1,RW2 ,@RW2+d8
MOVEA
MOVEA RW0
RW0,RW2 ,@RW2+d8
+2
+8 RW0,@RW0 ,@RW0+d16
MOVEA
MOVEA RW1
RW1,RW1 ,@RW1+d8
MOVEA
MOVEA RW0
RW0,RW1 ,@RW1+d8
+1
30
MOVEA
MOVEA RW1
RW1,RW0 ,@RW0+d8
20
MOVEA
MOVEA RW0
RW0,RW0 ,@RW0+d8
10
+0
00
APPENDIX C F2MC-16LX Instruction Maps
■ MOVEA RWi, ea Instruction Map
Table C-14 MOVEA RWi, ea Instruction (First Byte = 79H)
341
APPENDIX
C.8
MOV Ri, ea Instruction Map
Table C-15 lists MOV Ri, ea instruction map.
342
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW2 @RW2+d16 R1,@RW2 @RW2+d16 R2,@RW2 @RW2+d16 R3,@RW2 @RW2+d16 R4,@RW2 @RW2+d16 R5,@RW2 @RW2+d16 R6,@RW2 @RW2+d16 R7,@RW2 @RW2+d16
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
@RW0+ @RW0+RW7
MOV R0, MOV R0,
MOV R1, MOV R1,
MOV R2, MOV R2,
MOV R3, MOV R3,
MOV R4, MOV R4,
MOV R5, MOV R5,
MOV R6, MOV R6,
MOV R7, MOV R7,
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
@RW1+ @RW1+RW7
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
@RW2+ @PC+d16
MOV R0, MOV R0, MOV R1, MOV R1, MOV R2, MOV R2, MOV R3, MOV R3, MOV R4, MOV R4, MOV R5, MOV R5, MOV R6, MOV R6, MOV R7, MOV R7,
@RW3+
addr16 @RW3+
addr16
@RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16 @RW3+
addr16
@RW3+
addr16
+8
+9
+A
+B
+C
+D
+E
+F
F0
+7
E0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A0
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
MOV
MOV R0, MOV
MOV R1, MOV
MOV R2, MOV
MOV R3, MOV
MOV R4, MOV
MOV R5, MOV
MOV R6, MOV
MOV R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX C F2MC-16LX Instruction Maps
■ MOV Ri, ea Instruction Map
Table C-15 MOV Ri, ea Instruction (First Byte = 7AH)
343
APPENDIX
C.9
MOVW RWi, ea Instruction Map
Table C-16 lists MOVW RWi, ea instruction map.
344
MOVW
MOVW RW5,
RW5,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW1 @RW1+d16 RW1,@RW1 @RW1+d16 RW2,@RW1 @RW1+d16 RW3,@RW1 @RW1+d16 RW4,@RW1 @RW1+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW2 @RW2+d16 RW1,@RW2 @RW2+d16 RW2,@RW2 @RW2+d16 RW3,@RW2 @RW2+d16 RW4,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW3 @RW3+d16 RW1,@RW3 @RW3+d16 RW2,@RW3 @RW3+d16 RW3,@RW3 @RW3+d16 RW4,@RW3 @RW3+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4, MOVW
MOVW RW5, MOVW
MOVW RW6, MOVW
MOVW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, @RW2+ @PC+d16
RW2, @RW2+ @PC+d16
RW3, @RW2+ @PC+d16
RW4, @RW2+ @PC+d16
MOVW
MOVW
RW1, @RW3+ RW1, addr16
MOVW
RW0, @RW1+
MOVW
MOVW
RW0, @RW2+ @PC+d16
MOVW
MOVW
RW0, @RW3+ RW0, addr16
+9
+A
+B
+C
+D
+E
+F
MOVW
MOVW
RW2, @RW3+ RW2, addr16
MOVW
MOVW
RW3, @RW3+ RW3, addr16
MOVW
MOVW
RW5, @RW3+ RW5, addr16
MOVW
MOVW
RW5, @RW2+ @PC+d16
MOVW
MOVW
RW6, @RW3+ RW6, addr16
MOVW
MOVW RW6,
RW6, @RW2+ @PC+d16
MOVW
MOVW
RW7, @RW3+ RW7, addr16
MOVW
MOVW RW7,
RW7, @RW2+ @PC+d16
MOVW RW7,
@RW1+RW7
MOVW
MOVW RW7,
RW7,@RW3 @RW3+d16
MOVW
MOVW RW7,
RW7,@RW2 @RW2+d16
MOVW
MOVW RW7,
RW7,@RW1 @RW1+d16
MOVW
MOVW RW7,
RW7,@RW0 @RW0+d16
MOVW
MOVW RW7,
RW7, RW7 @RW7+d8
MOVW
MOVW RW7,
RW7, RW6 @RW6+d8
MOVW
MOVW RW7,
RW7, RW5 @RW5+d8
MOVW
MOVW RW7,
RW7, RW4 @RW4+d8
MOVW RW6, MOVW
@RW1+RW7 RW7, @RW1+
MOVW
MOVW RW6,
RW6,@RW3 @RW3+d16
MOVW
MOVW RW6,
RW6,@RW2 @RW2+d16
MOVW
MOVW RW6,
RW6,@RW1 @RW1+d16
MOVW
MOVW RW6,
RW6,@RW0 @RW0+d16
MOVW
MOVW RW6,
RW6, RW7 @RW7+d8
MOVW
MOVW RW6,
RW6, RW6 @RW6+d8
MOVW
MOVW RW6,
RW6, RW5 @RW5+d8
MOVW
MOVW RW6,
RW6, RW4 @RW4+d8
MOVW
MOVW
@RW1+RW7 RW6, @RW1+
MOVW
MOVW RW5,
RW5, RW6 @RW6+d8
MOVW
MOVW RW5,
RW5, RW5 @RW5+d8
MOVW RW4, MOVW
@RW1+RW7 RW5, @RW1+
MOVW
MOVW
RW4, @RW3+ RW4, addr16
MOVW RW3, MOVW
@RW1+RW7 RW4, @RW1+
MOVW
MOVW RW5,
RW5,@RW2 @RW2+d16
MOVW
MOVW
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW0,@RW0 @RW0+d16 RW1,@RW0 @RW0+d16 RW2,@RW0 @RW0+d16 RW3,@RW0 @RW0+d16 RW4,@RW0 @RW0+d16
+8
MOVW RW2, MOVW
@RW1+RW7 RW3, @RW1+
MOVW
MOVW RW5,
RW5,@RW1 @RW1+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
MOVW
MOVW
RW0, RW7 @RW7+d8
+7
MOVW RW1, MOVW
@RW1+RW7 RW2, @RW1+
MOVW
MOVW RW5,
RW5,@RW0 @RW0+d16
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
MOVW
MOVW
RW0, RW6 @RW6+d8
+6
MOVW
MOVW
@RW1+RW7 RW1, @RW1+
MOVW
MOVW RW5,
RW5, RW7 @RW7+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
MOVW
MOVW
RW0, RW5 @RW5+d8
+5
MOVW
MOVW RW5,
RW5, RW4 @RW4+d8
MOVW
MOVW RW7,
RW7, RW3 @RW3+d8
MOVW
MOVW RW7,
RW7, RW2 @RW2+d8
MOVW
MOVW RW7,
RW7, RW1 @RW1+d8
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
MOVW
MOVW RW6,
RW6, RW3 @RW3+d8
MOVW
MOVW RW6,
RW6, RW2 @RW2+d8
MOVW
MOVW RW6,
RW6, RW1 @RW1+d8
MOVW
MOVW
RW0, RW4 @RW4+d8
MOVW
MOVW RW5,
RW5, RW3 @RW3+d8
MOVW
MOVW RW5,
RW5, RW2 @RW2+d8
MOVW
MOVW RW5,
RW5, RW1 @RW1+d8
+4
F0
MOVW
MOVW RW7,
RW7, RW0 @RW0+d8
E0
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
D0
MOVW
MOVW RW6,
RW6, RW0 @RW0+d8
C0
MOVW
MOVW
RW0, RW3 @RW3+d8
B0
MOVW
MOVW RW5,
RW5, RW0 @RW0+d8
A0
+3
90
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
80
MOVW
MOVW
RW0, RW2 @RW2+d8
70
+2
60
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
50
MOVW
MOVW
RW0, RW1 @RW1+d8
40
+1
30
MOVW
MOVW RW1, MOVW
MOVW RW2, MOVW
MOVW RW3, MOVW
MOVW RW4,
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
20
MOVW
MOVW
RW0, RW0 @RW0+d8
10
+0
00
APPENDIX C F2MC-16LX Instruction Maps
■ MOVW RWi, ea Instruction Map
Table C-16 MOVW RWi, ea Instruction (First Byte = 7BH)
345
APPENDIX
C.10 MOV ea, Ri Instruction Map
Table C-17 lists MOV ea, Ri instruction map.
■ MOV ea, Ri Instruction Map
346
+F
+E
+D
+C
+B
+A
+9
+8
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R1 addr16, R1
MOV
MOV
@RW3+, R0 addr16, R0
MOV
MOV
MOV
@RW2+, R1 @PC+d16, R1
@RW2+, R0 @PC+d16, R0
MOV
MOV
MOV
MOV
MOV
@RW0+, R1 @RW0+RW7, R1
MOV
@RW3, R1 @RW3+d16, R1
MOV
@RW2, R1 @RW2+d16, R1
MOV
@RW1, R1 @RW1+d16, R1
MOV
@RW1+, R1 @RW1+RW7, R1
MOV
MOV
@RW0, R1 @RW0+d16, R1
MOV
@RW1+, R0 @RW1+RW7, R0
MOV
@RW0+, R0 @RW0+RW7, R0
MOV
@RW3, R0 @RW3+d16, R0
MOV
@RW2, R0 @RW2+d16, R0
MOV
@RW1, R0 @RW1+d16, R0
MOV
@RW0, R0 @RW0+d16, R0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R2 addr16, R2
MOV
@RW2+, R2 @PC+d16, R2
MOV
@RW1+, R2 @RW1+RW7, R2
MOV
@RW0+, R2 @RW0+RW7, R2
MOV
@RW3, R2 @RW3+d16, R2
MOV
@RW2, R2 @RW2+d16, R2
MOV
@RW1, R2 @RW1+d16, R2
MOV
@RW0, R2 @RW0+d16, R2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R3 addr16, R3
MOV
@RW2+, R3 @PC+d16, R3
MOV
@RW1+, R3 @RW1+RW7, R3
MOV
@RW0+, R3 @RW0+RW7, R3
MOV
@RW3, R3 @RW3+d16, R3
MOV
@RW2, R3 @RW2+d16, R3
MOV
@RW1, R3 @RW1+d16, R3
MOV
@RW0, R3 @RW0+d16, R3
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R4 addr16, R4
MOV
@RW2+, R4 @PC+d16, R4
MOV
@RW1+, R4 @RW1+RW7, R4
MOV
@RW0+, R4 @RW0+RW7, R4
MOV
@RW3, R4 @RW3+d16, R4
MOV
@RW2, R4 @RW2+d16, R4
MOV
@RW1, R4 @RW1+d16, R4
MOV
@RW0, R4 @RW0+d16, R4
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R5 addr16, R5
MOV
@RW2+, R5 @PC+d16, R5
MOV
@RW1+, R5 @RW1+RW7, R5
MOV
@RW0+, R5 @RW0+RW7, R5
MOV
@RW3, R5 @RW3+d16, R5
MOV
@RW2, R5 @RW2+d16, R5
MOV
@RW1, R5 @RW1+d16, R5
MOV
@RW0, R5 @RW0+d16, R5
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R6 addr16, R6
MOV
@RW2+, R6 @PC+d16, R6
MOV
@RW1+, R6 @RW1+RW7, R6
MOV
@RW0+, R6 @RW0+RW7, R6
MOV
@RW3, R6 @RW3+d16, R6
MOV
@RW2, R6 @RW2+d16, R6
MOV
@RW1, R6 @RW1+d16, R6
MOV
@RW0, R6 @RW0+d16,
R6
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
@RW3+, R7 addr16, R7
MOV
@RW2+, R7 @PC+d16, R7
MOV
@RW1+, R7 @RW1+RW7, R7
MOV
@RW0+, R7 @RW0+RW7, R7
MOV
@RW3, R7 @RW3+d16, R7
MOV
@RW2, R7 @RW2+d16, R7
MOV
@RW1, R7 @RW1+d16, R7
MOV
@RW0, R7 @RW0+d16, R7
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R7, R0 @RW7+d8, R0
R7, R1 @RW7+d8, R1
R7, R2 @RW7+d8, R2
R7, R3 @RW7+d8, R3
R7, R4 @RW7+d8, R4
R7, R5 @RW7+d8, R5
R7, R6 @RW7+d8, R6
R7, R7 @RW7+d8, R7
F0
+7
E0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R6, R0 @RW6+d8, R0
R6, R1 @RW6+d8, R1
R6, R2 @RW6+d8, R2
R6, R3 @RW6+d8, R3
R6, R4 @RW6+d8, R4
R6, R5 @RW6+d8, R5
R6, R6 @RW6+d8, R6
R6, R7 @RW6+d8, R7
D0
+6
C0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R5, R0 @RW5+d8, R0
R5, R1 @RW5+d8, R1
R5, R2 @RW5+d8, R2
R5, R3 @RW5+d8, R3
R5, R4 @RW5+d8, R4
R5, R5 @RW5+d8, R5
R5, R6 @RW5+d8, R6
R5, R7 @RW5+d8, R7
B0
+5
A0
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R4, R0 @RW4+d8, R0
R4, R1 @RW4+d8, R1
R4, R2 @RW4+d8, R2
R4, R3 @RW4+d8, R3
R4, R4 @RW4+d8, R4
R4, R5 @RW4+d8, R5
R4, R6 @RW4+d8, R6
R4, R7 @RW4+d8, R7
90
+4
80
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R3, R0 @RW3+d8, R0
R3, R1 @RW3+d8, R1
R3, R2 @RW3+d8, R2
R3, R3 @RW3+d8, R3
R3, R4 @RW3+d8, R4
R3, R5 @RW3+d8, R5
R3, R6 @RW3+d8, R6
R3, R7 @RW3+d8, R7
70
+3
60
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R2, R0 @RW2+d8, R0
R2, R1 @RW2+d8, R1
R2, R2 @RW2+d8, R2
R2, R3 @RW2+d8, R3
R2, R4 @RW2+d8, R4
R2, R5 @RW2+d8, R5
R2, R6 @RW2+d8, R6
R2, R7 @RW2+d8, R7
50
+2
40
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R1, R0 @RW1+d8, R0
R1, R1 @RW1+d8, R1
R1, R2 @RW1+d8, R2
R1, R3 @RW1+d8, R3
R1, R4 @RW1+d8, R4
R1, R5 @RW1+d8, R5
R1, R6 @RW1+d8, R6
R1, R7 @RW1+d8, R7
30
+1
20
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
R0, R0 @RW0+d8, R0
R0, R1 @RW0+d8, R1
R0, R2 @RW0+d8, R2
R0, R3 @RW0+d8, R3
R0, R4 @RW0+d8, R4
R0, R5 @RW0+d8, R5
R0, R6 @RW0+d8, R6
R0, R7 @RW0+d8, R7
10
+0
00
APPENDIX C F2MC-16LX Instruction Maps
Table C-17 MOV ea, Ri Instruction (First Byte = 7CH)
347
APPENDIX
C.11 MOVW ea, RWi Instruction Map
Table C-18 lists MOVW ea, RWi instruction map.
■ MOVW ea, RWi Instruction Map
348
MOVW
MOVW@RW2
@RW2, RW1 +d16, RW1
MOVW
MOVW@RW3
@RW3, RW1 +d16, RW1
MOVW
MOVW@RW0
@RW0+, RW1 +RW7,RW1
MOVW
MOVW@RW1
@RW1+,RW1 +RW7,RW1
MOVW
MOVW@PC
@RW2+,RW1 +d16, RW1
MOVW
MOVW
@RW3+,RW1 addr16, RW1
MOVW
MOVW@RW2
@RW2, RW0 +d16, RW0
MOVW
MOVW@RW3
@RW3, RW0 +d16, RW0
MOVW
MOVW@RW0
@RW0+,RW0 +RW7,RW0
MOVW
MOVW@RW1
@RW1+,RW0 +RW7,RW0
MOVW
MOVW@PC
@RW2+,RW0 +d16, RW0
MOVW
MOVW
@RW3+,RW0 addr16, RW0
+B
+C
+D
+E
+F
MOVW
MOVW
@RW3+,RW2 addr16, RW2
MOVW
MOVW@PC
@RW2+,RW2 +d16, RW2
MOVW
MOVW@RW1
@RW1+,RW2 +RW7,RW2
MOVW
MOVW@RW0
@RW0+,RW2 +RW7,RW2
MOVW
MOVW@RW3
@RW3, RW2 +d16, RW2
MOVW
MOVW@RW2
@RW2, RW2 +d16, RW2
MOVW
MOVW
@RW3+,RW3 addr16, RW3
MOVW
MOVW@PC
@RW2+,RW3 +d16, RW3
MOVW
MOVW@RW1
@RW1+,RW3 -+RW7,RW3
MOVW
MOVW@RW0
@RW0+,RW3 +RW7,RW3
MOVW
MOVW@RW3
@RW3, RW3 +d16, RW3
MOVW
MOVW@RW2
@RW2, RW3 +d16, RW3
MOVW
MOVW@RW1
@RW1, RW3 +d16, RW3
MOVW
MOVW
@RW3+,RW4 addr16, RW4
MOVW
MOVW@PC
@RW2+,RW4 +d16, RW4
MOVW
MOVW@RW1
@RW1+,RW4 +RW7,RW4
MOVW
MOVW@RW0
@RW0+,RW4 +RW7,RW4
MOVW
MOVW@RW3
@RW3, RW4 +d16, RW4
MOVW
MOVW@RW2
@RW2, RW4 +d16, RW4
MOVW
MOVW@RW1
@RW1, RW4 +d16, RW4
MOVW
MOVW
@RW3+,RW5 addr16, RW5
MOVW
MOVW@PC
@RW2+,RW5 +d16, RW5
MOVW
MOVW@RW1
@RW1+,RW5 +RW7,RW5
MOVW
MOVW@RW0
@RW0+,RW5 +RW7,RW5
MOVW
MOVW@RW3
@RW3, RW5 +d16, RW5
MOVW
MOVW@RW2
@RW2, RW5 +d16, RW5
MOVW
MOVW@RW1
@RW1, RW5 +d16, RW5
MOVW
MOVW
@RW3+,RW6 addr16, RW6
MOVW
MOVW @PC
@RW2+,RW6 +d16, RW6
MOVW
MOVW@RW1
@RW1+,RW6 +RW7,RW6
MOVW
MOVW@RW0
@RW0+,RW6 +RW7,RW6
MOVW
MOVW@RW3
@RW3, RW6 +d16, RW6
MOVW
MOVW@RW2
@RW2, RW6 +d16, RW6
MOVW
MOVW@RW1
@RW1, RW6 +d16, RW6
MOVW
MOVW
@RW3+,RW7 addr16, RW7
MOVW
MOVW@PC
@RW2+,RW7 +d16, RW7
MOVW
MOVW@RW1
@RW1+,RW7 +RW7,RW7
MOVW
MOVW@RW0
@RW0+,RW7 +RW7,RW7
MOVW
MOVW@RW3
@RW3, RW7 +d16, RW7
MOVW
MOVW@RW2
@RW2, RW7 +d16, RW7
MOVW
MOVW@RW1
@RW1, RW7 +d16, RW7
MOVW
MOVW@RW0
@RW0, RW7 +d16, RW7
+A
MOVW
MOVW@RW1
@RW1, RW2 +d16, RW2
MOVW
MOVW@RW0
@RW0, RW6 +d16, RW6
MOVW
MOVW@RW1
@RW1, RW1 +d16, RW1
MOVW
MOVW@RW0
@RW0, RW5 +d16, RW5
MOVW
MOVW@RW1
@RW1, RW0 +d16, RW0
MOVW
MOVW@RW0
@RW0, RW4 +d16, RW4
+9
MOVW
MOVW@RW0
@RW0, RW3 +d16, RW3
MOVW
MOVW@RW0
@RW0, RW1 +d16, RW1
MOVW
MOVW@RW0
@RW0, RW0 +d16, RW0
+8
MOVW
MOVW@RW0
@RW0, RW2 +d16, RW2
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW7, RW0 @RW7+d8, RW0
RW7, RW1 @RW7+d8, RW1 RW7, RW2 @RW7+d8, RW2 RW7, RW3 @RW7+d8, RW3 RW7, RW4 @RW7+d8, RW4 RW7, RW5 @RW7+d8, RW5 RW7, RW6 @RW7+d8, RW6 RW7, RW7 @RW7+d8, RW7
F0
+7
E0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW6, RW0 @RW6+d8, RW0
RW6, RW1 @RW6+d8, RW1 RW6, RW2 @RW6+d8, RW2 RW6, RW3 @RW6+d8, RW3 RW6, RW4 @RW6+d8, RW4 RW6, RW5 @RW6+d8, RW5 RW6, RW6 @RW6+d8, RW6 RW6, RW7 @RW6+d8, RW7
D0
+6
C0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW5, RW0 @RW5+d8, RW0
RW5, RW1 @RW5+d8, RW1 RW5, RW2 @RW5+d8, RW2 RW5, RW3 @RW5+d8, RW3 RW5, RW4 @RW5+d8, RW4 RW5, RW5 @RW5+d8, RW5 RW5, RW6 @RW5+d8, RW6 RW5, RW7 @RW5+d8, RW7
B0
+5
A0
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW4, RW0 @RW4+d8, RW0
RW4, RW1 @RW4+d8, RW1 RW4, RW2 @RW4+d8, RW2 RW4, RW3 @RW4+d8, RW3 RW4, RW4 @RW4+d8, RW4 RW4, RW5 @RW4+d8, RW5 RW4, RW6 @RW4+d8, RW6 RW4, RW7 @RW4+d8, RW7
90
+4
80
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW3, RW0 @RW3+d8, RW0
RW3, RW1 @RW3+d8, RW1 RW3, RW2 @RW3+d8, RW2 RW3, RW3 @RW3+d8, RW3 RW3, RW4 @RW3+d8, RW4 RW3, RW5 @RW3+d8, RW5 RW3, RW6 @RW3+d8, RW6 RW3, RW7 @RW3+d8, RW7
70
+3
60
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW2, RW0 @RW2+d8, RW0
RW2, RW1 @RW2+d8, RW1 RW2, RW2 @RW2+d8, RW2 RW2, RW3 @RW2+d8, RW3 RW2, RW4 @RW2+d8, RW4 RW2, RW5 @RW2+d8, RW5 RW2, RW6 @RW2+d8, RW6 RW2, RW7 @RW2+d8, RW7
50
+2
40
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW1, RW0 @RW1+d8, RW0
RW1, RW1 @RW1+d8, RW1 RW1, RW2 @RW1+d8, RW2 RW1, RW3 @RW1+d8, RW3 RW1, RW4 @RW1+d8, RW4 RW1, RW5 @RW1+d8, RW5 RW1, RW6 @RW1+d8, RW6 RW1, RW7 @RW1+d8, RW7
30
+1
20
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
RW0, RW0 @RW0+d8, RW0
RW0, RW1 @RW0+d8, RW1 RW0, RW2 @RW0+d8, RW2 RW0, RW3 @RW0+d8, RW3 RW0, RW4 @RW0+d8, RW4 RW0, RW5 @RW0+d8, RW5 RW0, RW6 @RW0+d8, RW6 RW0, RW7 @RW0+d8, RW7
10
+0
00
APPENDIX C F2MC-16LX Instruction Maps
Table C-18 MOVW ea, RWi Instruction (First Byte = 7DH)
349
APPENDIX C F2MC-16LX Instruction Maps
C.12 XCH Ri, ea Instruction Map
Table C-19 lists XCH Ri, ea instruction map.
350
XCH
XCH
XCH
XCH
R1,
XCH
XCH R1,
R1,@RW2 W2+d16, A
XCH
XCH
R2,
XCH
XCH R2,
R2,@RW2 W2+d16, A
XCH
XCH
R3,
XCH
XCH R3,
R3,@RW2 W2+d16, A
XCH
XCH
R4,
XCH
XCH R4,
R4,@RW2 W2+d16, A
XCH
XCH
R5,
XCH
XCH R5,
R5,@RW2 W2+d16, A
XCH
XCH
R6,
XCH
XCH R6,
R6,@RW2 W2+d16, A
XCH
XCH
R7,
XCH
XCH R7,
R7,@RW2 W2+d16, A
XCH
XCH
XCH
XCH
XCH
R1, XCH
XCH
R2, XCH
XCH
R3, XCH
XCH
R4, XCH
XCH
R5, XCH
XCH
R6, XCH
XCH
R7,
+F R0,@RW3+ R0, addr16
XCH
XCH
R1,@RW3+ R1, addr16
XCH
XCH
R2,@RW3+ R2, addr16
XCH
XCH
R3,@RW3+ R3, addr16
XCH
XCH
R4,@RW3+ R4, addr16
XCH
XCH
R5,@RW3+ R5, addr16
XCH
XCH
R6,@RW3+ R6, addr16
XCH
XCH
R7,@RW3+ R7, addr16
+E R0,@RW2+ @PC+d16 R1,@RW2+ @PC+d16 R2,@RW2+ @PC+d16 R3,@RW2+ @PC+d16 R4,@RW2+ @PC+d16 R5,@RW2+ @PC+d16 R6,@RW2+ @PC+d16 R7,@RW2+ @PC+d16
R0, XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW1+RW7 R1,@RW1+ @RW1+RW7 R2,@RW1+ @RW1+RW7 R3,@RW1+ @RW1+RW7 R4,@RW1+ @RW1+RW7 R5,@RW1+ @RW1+RW7 R6,@RW1+ @RW1+RW7 R7,@RW1+ @RW1+RW7
+D R0,@RW1+
XCH
XCH R0,
XCH
XCH R1,
XCH
XCH R2,
XCH
XCH R3,
XCH
XCH R4,
XCH
XCH R5,
XCH
XCH R6,
XCH
XCH R7,
@RW0+RW7 R1,@RW0+ @RW0+RW7 R2,@RW0+ @RW0+RW7 R3,@RW0+ @RW0+RW7 R4,@RW0+ @RW0+RW7 R5,@RW0+ @RW0+RW7 R6,@RW0+ @RW0+RW7 R7,@RW0+ @RW0+RW7
XCH
+C R0,@RW0+
+B R0,@RW3 @RW3+d16 R1,@RW3 @RW3+d16 R2,@RW3 @RW3+d16 R3,@RW3 @RW3+d16 R4,@RW3 @RW3+d16 R5,@RW3 @RW3+d16 R6,@RW3 @RW3+d16 R7,@RW3 @RW3+d16
R0,
+A R0,@RW2 W2+d16, A
R0,
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW1 @RW1+d16 R1,@RW1 @RW1+d16 R2,@RW1 @RW1+d16 R3,@RW1 @RW1+d16 R4,@RW1 @RW1+d16 R5,@RW1 @RW1+d16 R6,@RW1 @RW1+d16 R7,@RW1 @RW1+d16
+9
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0,@RW0 @RW0+d16 R1,@RW0 @RW0+d16 R2,@RW0 @RW0+d16 R3,@RW0 @RW0+d16 R4,@RW0 @RW0+d16 R5,@RW0 @RW0+d16 R6,@RW0 @RW0+d16 R7,@RW0 @RW0+d16
+8
XCH
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R7 @RW7+d8
R1, R7 @RW7+d8
R2, R7 @RW7+d8
R3, R7 @RW7+d8
R4, R7 @RW7+d8
R5, R7 @RW7+d8
R6, R7 @RW7+d8
R7, R7 @RW7+d8
F0
+7
E0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R6 @RW6+d8
R1, R6 @RW6+d8
R2, R6 @RW6+d8
R3, R6 @RW6+d8
R4, R6 @RW6+d8
R5, R6 @RW6+d8
R6, R6 @RW6+d8
R7, R6 @RW6+d8
D0
+6
C0
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R5 @RW5+d8
R1, R5 @RW5+d8
R2, R5 @RW5+d8
R3, R5 @RW5+d8
R4, R5 @RW5+d8
R5, R5 @RW5+d8
R6, R5 @RW5+d8
R7, R5 @RW5+d8
B0
+5
A
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R4 @RW4+d8
R1, R4 @RW4+d8
R2, R4 @RW4+d8
R3, R4 @RW4+d8
R4, R4 @RW4+d8
R5, R4 @RW4+d8
R6, R4 @RW4+d8
R7, R4 @RW4+d8
90
+4
80
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R3 @RW3+d8
R1, R3 @RW3+d8
R2, R3 @RW3+d8
R3, R3 @RW3+d8
R4, R3 @RW3+d8
R5, R3 @RW3+d8
R6, R3 @RW3+d8
R7, R3 @RW3+d8
70
+3
60
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R2 @RW2+d8
R1, R2 @RW2+d8
R2, R2 @RW2+d8
R3, R2 @RW2+d8
R4, R2 @RW2+d8
R5, R2 @RW2+d8
R6, R2 @RW2+d8
R7, R2 @RW2+d8
50
+2
40
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R1 @RW1+d8
R1, R1 @RW1+d8
R2, R1 @RW1+d8
R3, R1 @RW1+d8
R4, R1 @RW1+d8
R5, R1 @RW1+d8
R6, R1 @RW1+d8
R7, R1 @RW1+d8
30
+1
20
XCH
XCH R0, XCH
XCH R1, XCH
XCH R2, XCH
XCH R3, XCH
XCH R4, XCH
XCH R5, XCH
XCH R6, XCH
XCH R7,
R0, R0 @RW0+d8
R1, R0 @RW0+d8
R2, R0 @RW0+d8
R3, R0 @RW0+d8
R4, R0 @RW0+d8
R5, R0 @RW0+d8
R6, R0 @RW0+d8
R7, R0 @RW0+d8
10
+0
00
APPENDIX C F2MC-16LX Instruction Maps
■ XCH Ri, ea Instruction Map
Table C-19 XCH Ri, ea Instruction (First Byte = 7EH)
351
APPENDIX C F2MC-16LX Instruction Maps
C.13 XCHW RWi, ea Instruction Map
Table C-20 lists XCHW RWi, ea instruction map.
■ XCHW RWi, ea Instruction Map
352
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2+ @PC+d16
RW1,@RW2+ @PC+d16
RW2,@RW2+ @PC+d16
RW3,@RW2+ @PC+d16
RW4,@RW2+ @PC+d16
RW5,@RW2+ @PC+d16
RW6,@RW2+ @PC+d16
RW7,@RW2+ @PC+d16
XCHW
XCHW
RW0,@RW3+ RW0, addr16
+E
+F
XCHW
XCHW
RW7,@RW3+ RW7, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1+ @RW1+RW7 RW1,@RW1+ @RW1+RW7 RW2,@RW1+ @RW1+RW7 RW3,@RW1+ @RW1+RW7 RW4,@RW1+ @RW1+RW7 RW5,@RW1+ @RW1+RW7 RW6,@RW1+ @RW1+RW7 RW7,@RW1+ @RW1+RW7
+D
XCHW
XCHW
RW6,@RW3+ RW6, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0+ @RW0+RW7 RW1,@RW0+ @RW0+RW7 RW2,@RW0+ @RW0+RW7 RW3,@RW0+ @RW0+RW7 RW4,@RW0+ @RW0+RW7 RW5,@RW0+ @RW0+RW7 RW6,@RW0+ @RW0+RW7 RW7,@RW0+ @RW0+RW7
+C
XCHW
XCHW
RW5,@RW3+ RW5, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW3 @RW3+d16
RW1,@RW3 @RW3+d16
RW2,@RW3 @RW3+d16
RW3,@RW3 @RW3+d16
RW4,@RW3 @RW3+d16
RW5,@RW3 @RW3+d16
RW6,@RW3 @RW3+d16
RW7,@RW3 @RW3+d16
+B
XCHW
XCHW
RW4,@RW3+ RW4, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW2 @RW2+d16
RW1,@RW2 @RW2+d16
RW2,@RW2 @RW2+d16
RW3,@RW2 @RW2+d16
RW4,@RW2 @RW2+d16
RW5,@RW2 @RW2+d16
RW6,@RW2 @RW2+d16
RW7,@RW2 @RW2+d16
+A
XCHW
XCHW
RW3,@RW3+ RW3, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW1 @RW1+d16
RW1,@RW1 @RW1+d16
RW2,@RW1 @RW1+d16
RW3,@RW1 @RW1+d16
RW4,@RW1 @RW1+d16
RW5,@RW1 @RW1+d16
RW6,@RW1 @RW1+d16
RW7,@RW1 @RW1+d16
+9
XCHW
XCHW
RW2,@RW3+ RW2, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0,@RW0 @RW0+d16
RW1,@RW0 @RW0+d16
RW2,@RW0 @RW0+d16
RW3,@RW0 @RW0+d16
RW4,@RW0 @RW0+d16
RW5,@RW0 @RW0+d16
RW6,@RW0 @RW0+d16
RW7,@RW0 @RW0+d16
+8
XCHW
XCHW
RW1,@RW3+ RW1, addr16
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW7 @RW7+d8
RW1, RW7 @RW7+d8
RW2, RW7 @RW7+d8
RW3, RW7 @RW7+d8
RW4, RW7 @RW7+d8
RW5, RW7 @RW7+d8
RW6, RW7 @RW7+d8
RW7, RW7 @RW7+d8
F0
+7
E0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW6 @RW6+d8
RW1, RW6 @RW6+d8
RW2, RW6 @RW6+d8
RW3, RW6 @RW6+d8
RW4, RW6 @RW6+d8
RW5, RW6 @RW6+d8
RW6, RW6 @RW6+d8
RW7, RW6 @RW6+d8
D0
+6
C0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW5 @RW5+d8
RW1, RW5 @RW5+d8
RW2, RW5 @RW5+d8
RW3, RW5 @RW5+d8
RW4, RW5 @RW5+d8
RW5, RW5 @RW5+d8
RW6, RW5 @RW5+d8
RW7, RW5 @RW5+d8
B0
+5
A0
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW4 @RW4+d8
RW1, RW4 @RW4+d8
RW2, RW4 @RW4+d8
RW3, RW4 @RW4+d8
RW4, RW4 @RW4+d8
RW5, RW4 @RW4+d8
RW6, RW4 @RW4+d8
RW7, RW4 @RW4+d8
90
+4
80
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW3 @RW3+d8
RW1, RW3 @RW3+d8
RW2, RW3 @RW3+d8
RW3, RW3 @RW3+d8
RW4, RW3 @RW3+d8
RW5, RW3 @RW3+d8
RW6, RW3 @RW3+d8
RW7, RW3 @RW3+d8
70
+3
60
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW2 @RW2+d8
RW1, RW2 @RW2+d8
RW2, RW2 @RW2+d8
RW3, RW2 @RW2+d8
RW4, RW2 @RW2+d8
RW5, RW2 @RW2+d8
RW6, RW2 @RW2+d8
RW7, RW2 @RW2+d8
50
+2
40
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW1 @RW1+d8
RW1, RW1 @RW1+d8
RW2, RW1 @RW1+d8
RW3, RW1 @RW1+d8
RW4, RW1 @RW1+d8
RW5, RW1 @RW1+d8
RW6, RW1 @RW1+d8
RW7, RW1 @RW1+d8
30
+1
20
XCHW
XCHW RW0, XCHW
XCHW RW1, XCHW
XCHW RW2, XCHW
XCHW RW3, XCHW
XCHW RW4, XCHW
XCHW RW5, XCHW
XCHW RW6, XCHW
XCHW RW7,
RW0, RW0 @RW0+d8
RW1, RW0 @RW0+d8
RW2, RW0 @RW0+d8
RW3, RW0 @RW0+d8
RW4, RW0 @RW0+d8
RW5, RW0 @RW0+d8
RW6, RW0 @RW0+d8
RW7, RW0 @RW0+d8
10
+0
00
APPENDIX C F2MC-16LX Instruction Maps
Table C-20 XCHW RWi, ea Instruction (First Byte = 7FH)
Note:R0 is also used as a barrel shift counter or normalizing instruction counter.
353
APPENDIX C F2MC-16LX Instruction Maps
354
INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
355
INDEX
Index
Numerics
2-byte Instruction
2-byte Instruction Map...................................... 329
A
A
Accumulator (A) ................................................ 18
Accumulator
Accumulator (A) ................................................ 18
ADDC (Add Byte Data of Accumulator and Effective
Address with Carry to Accumulator) ....... 82
ADDCW (Add Word Data of Accumulator and
Effective
Address
with
Carry
to
Accumulator)........................................ 84
ASR (Arithmetic Shift Byte Data of Accumulator to
Right)................................................. 102
ASRL (Arithmetic Shift Long Word Data of
Accumulator to Right) ......................... 104
ASRW (Arithmetic Shift Word Data of Accumulator
to Right) ..................................... 106, 108
LSL (Logical Shift Byte Data of Accumulator to Left)
.......................................................... 170
LSLL (Logical Shift Long Word Data of Accumulator
to Left) ............................................... 171
LSLW (Logical Shift Word Data of Accumulator to
Left)........................................... 172, 173
LSR (Logical Shift Byte Data of Accumulator to
Right)................................................. 174
LSRL (Logical Shift Long Word Data of Accumulator
to Right) ............................................. 176
LSRW (Logical Shift Word Data of Accumulator to
Right)......................................... 178, 179
MOV (Move Byte Data from Accumulator to
Destination) ........................................ 183
MOV (Move Byte Data from Source to Accumulator)
.......................................................... 181
MOVB (Move Bit Data from Accumulator to Bit
Address)............................................. 191
MOVB (Move Bit Data from Bit Address to
Accumulator)...................................... 189
MOVL (Move Long Word Data from Accumulator to
Destination) ........................................ 195
MOVL (Move Long Word Data from Source to
Accumulator)...................................... 194
MOVN (Move Immediate Nibble Data to
Accumulator)...................................... 196
MOVW (Move Word Data from Accumulator to
Destination) ........................................ 203
MOVW (Move Word Data from Source to
Accumulator)...................................... 201
356
MOVX (Move Byte Data with Sign Extension from
Source to Accumulator) ....................... 211
MUL (Multiply Byte Data of Accumulator)........ 213
MUL (Multiply Byte Data of Accumulator and
Effective Address) .............................. 214
MULU (Multiply Unsigned Byte Data of
Accumulator) ..................................... 217
MULU (Multiply Unsigned Byte Data of Accumulator
and Effective Address) ........................ 218
MULUW (Multiply Unsigned Word Data of
Accumulator) ..................................... 219
MULUW (Multiply Unsigned Word Data of
Accumulator and Effective Address)
......................................................... 220
MULW (Multiply Word Data of Accumulator)
......................................................... 215
MULW (Multiply Word Data of Accumulator and
Effective Address) .............................. 216
POPW (Pop Word Data of Accumulator from Stack
Memory) ............................................ 237
ROLC (Rotate Byte Data of Accumulator with Carry
to Left)............................................... 253
RORC (Rotate Byte Data of Accumulator with Carry
to Right)............................................. 255
SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
......................................................... 267
SUBCW (Subtract Word Data of Effective Address
from
Accumulator
with
Carry
to
Accumulator) ..................................... 269
SWAP (Swap Byte Data of Accumulator) .......... 277
SWAPW (Swap Word Data of Accumulator) ..... 278
ADD
ADD (Add Byte Data of Destination and Source to
Destination).......................................... 79
ADDC
ADDC (Add Byte Data of Accumulator and Effective
Address with Carry to Accumulator)....... 82
ADDC (Add Byte Data of AL and AH with Carry to
AL) ..................................................... 81
ADDCW
ADDCW (Add Word Data of Accumulator and
Effective
Address
with
Carry
to
Accumulator) ....................................... 84
ADDDC
ADDDC (Add Decimal Data of AL and AH with
Carry to AL)......................................... 86
ADDL
ADDL (Add Long Word Data of Destination and
Source to Destination) ........................... 87
INDEX
Address Specification
INC (Increment Byte Data (Address Specification))
.......................................................... 153
Addressing
Bank Addressing Mode ........................................ 9
Direct Addressing .............................................. 61
Indirect Addressing ............................................ 63
Linear Addressing Mode....................................... 7
ADDSP
ADDSP (Add Word Data of Stack Pointer and
Immediate Data to Stack Pointer) ........... 89
ADDW
ADDW (Add Word Data of AL and AH to AL) .... 90
ADDW (Add Word Data of Destination and Source to
Destination).......................................... 91
AND
AND (And Byte Data of Destination and Source to
Destination).......................................... 93
AND (And Byte Data of Immediate Data and
Condition Code Register)....................... 95
AND (And Byte Data of Destination and Source to
Destination).......................................... 93
AND (And Byte Data of Immediate Data and
Condition Code Register)....................... 95
ANDL (And Long Word Data of Destination and
Source to Destination) ........................... 97
ANDL
ANDL (And Long Word Data of Destination and
Source to Destination) ........................... 97
ANDW
ANDW (And Word Data of AH and AL to AL) .... 99
ANDW (And Word Data of Destination and Source to
Destination)........................................ 100
Application Procedure
Flowchart of Extended Intelligent I/O Service
Application Procedure ........................... 51
Arithmetic Shift Byte Data
ASR (Arithmetic Shift Byte Data of Accumulator to
Right) ................................................ 102
Arithmetic Shift Long Word Data
ASRL (Arithmetic Shift Long Word Data of
Accumulator to Right) ......................... 104
Arithmetic Shift Word Data
ASRW (Arithmetic Shift Word Data of Accumulator
to Right)..................................... 106, 108
ASR
ASR (Arithmetic Shift Byte Data of Accumulator to
Right) ................................................ 102
ASRL
ASRL (Arithmetic Shift Long Word Data of
Accumulator to Right) ......................... 104
ASRW
ASRW (Arithmetic Shift Word Data of Accumulator
to Right)..................................... 106, 108
B
Bank Addressing
Bank Addressing Mode .........................................9
Bank Registers
Bank Registers ...................................................28
Bank Select Prefix
Bank Select Prefix ..............................................34
Banks
Memory Space Divided into Banks and Values in
Each Register Bank................................11
BAP
Buffer Address Pointer (BAP) .............................56
Basic Page Map
Basic Page Map................................................322
BBcc
BBcc (Branch if Bit Condition satisfied) .............110
Bcc
Bcc (Branch relative if Condition satisfied) .........112
Bit Address
MOVB (Move Bit Data from Accumulator to Bit
Address) .............................................191
MOVB (Move Bit Data from Bit Address to
Accumulator) ......................................189
Bit Configuration
Interrupt Control Register (ICR) Bit Configuration
............................................................52
Bit Data
MOVB (Move Bit Data from Accumulator to Bit
Address) .............................................191
MOVB (Move Bit Data from Bit Address to
Accumulator) ......................................189
Bit Operation Instruction
Bit Operation Instruction Map ...........................325
Branch
BBcc (Branch if Bit Condition satisfied) .............110
Bcc (Branch relative if Condition satisfied) .........112
CBNE (Compare Byte Data and Branch if not equal)
..........................................................120
CWBNE (Compare Word Data and Branch if not
Equal).................................................129
DBNZ (Decrement Byte Data and Branch if not Zero)
..........................................................131
DWBNZ (Decrement Word Data and Branch if not
Zero) ..................................................145
SBBS (Set Bit and Branch if Bit Set) ..................257
Branch Instruction
Branch Instruction ............................................314
Buffer Address Pointer
Buffer Address Pointer (BAP) .............................56
Byte
MUL (Multiply Byte Data of Accumulator) ........213
Byte Data
AND (And Byte Data of Destination and Source to
Destination) ..........................................93
357
INDEX
AND (And Byte Data of Immediate Data and
Condition Code Register) ....................... 95
CBNE (Compare Byte Data and Branch if not equal)
.......................................................... 120
CMP (Compare Byte Data of Destination and Source)
.......................................................... 123
DBNZ (Decrement Byte Data and Branch if not Zero)
.......................................................... 131
DEC (Decrement Byte Data) ............................. 133
DIV (Divide Word Data by Byte Data)............... 137
EXT (Sign Extend from Byte Data to Word Data)
.......................................................... 147
INC (Increment Byte Data (Address Specification))
.......................................................... 153
LSL (Logical Shift Byte Data of Accumulator to Left)
170
LSR (Logical Shift Byte Data of Accumulator to
Right)................................................. 174
MOV (Move Byte Data from Accumulator to
Destination) ........................................ 183
MOV (Move Byte Data from AH to Memory)
.......................................................... 188
MOV (Move Byte Data from Source to Accumulator)
.......................................................... 181
MOV (Move Byte Data from Source to Destination)
.......................................................... 186
MOVX (Move Byte Data with Sign Extension from
Source to Accumulator) ....................... 211
MUL (Multiply Byte Data of Accumulator and
Effective Address)............................... 214
MULU (Multiply Unsigned Byte Data of
Accumulator)...................................... 217
NEG (Negate Byte Data of Destination) ............. 221
NOT (Not Byte Data of Destination) .................. 224
OR (Or Byte Data of Destination and Source to
Destination) ........................................ 228
OR (Or Byte Data of Immediate Data and Condition
Code Register to Condition Code Register)
.......................................................... 230
ROLC (Rotate Byte Data of Accumulator with Carry
to Left) ............................................... 253
RORC (Rotate Byte Data of Accumulator with Carry
to Right) ............................................. 255
SUB (Subtract Byte Data of Source from Destination
to Destination) .................................... 264
SUBC (Subtract Byte Data of AL from AH with Carry
to AL) ................................................ 266
SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
.......................................................... 267
SWAP (Swap Byte Data of Accumulator)........... 277
XCH (Exchange Byte Data of Source to Destination)
.......................................................... 282
XOR (Exclusive Or Byte Data of Destination and
Source to Destination) ......................... 286
ZEXT (Zero Extend from Byte Data to Word Data)
.......................................................... 293
358
C
CALL
CALL (Call Subroutine) ................................... 114
CALLP
CALLP (Call physical Address) ........................ 116
CALLV
CALLV (Call Vectored Subroutine) .................. 118
Carry
ADDC (Add Byte Data of Accumulator and Effective
Address with Carry to Accumulator)....... 82
ADDC (Add Byte Data of AL and AH with Carry to
AL) ..................................................... 81
ADDCW (Add Word Data of Accumulator and
Effective
Address
with
Carry
to
Accumulator) ....................................... 84
ADDDC (Add Decimal Data of AL and AH with
Carry to AL)......................................... 86
ROLC (Rotate Byte Data of Accumulator with Carry
to Left)............................................... 253
RORC (Rotate Byte Data of Accumulator with Carry
to Right)............................................. 255
SUBC (Subtract Byte Data of AL from AH with Carry
to AL)................................................ 266
SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
......................................................... 267
SUBCW (Subtract Word Data of Effective Address
from
Accumulator
with
Carry
to
Accumulator) ..................................... 269
SUBDC (Subtract Decimal Data of AL from AH with
Carry to AL)....................................... 271
CBNE
CBNE (Compare Byte Data and Branch if not equal)
......................................................... 120
CCR
Condition Code Register (CCR) .......................... 25
Channel Selection Bits
Extended Intelligent I/O Service Channel Selection
Bits (bit15 to bit12 or bit7 to bit4: ICS0 to
ICS3) ................................................... 53
Character String Operation Instruction
Character String Operation Instruction Map ....... 327
Clear Bit
CLRB (Clear Bit)............................................. 122
CLRB
CLRB (Clear Bit)............................................. 122
CMP
CMP (Compare Byte Data of Destination and Source)
......................................................... 123
CMPL
CMPL (Compare Long Word Data of Destination and
Source) .............................................. 125
INDEX
CMPW
CMPW (Compare Word Data of Destination and
Source) .............................................. 127
CMR
Common Register Bank Prefix (CMR)................. 36
Common Register Bank Prefix
Common Register Bank Prefix (CMR)................. 36
Compare
CBNE (Compare Byte Data and Branch if not equal)
.......................................................... 120
CMP (Compare Byte Data of Destination and Source)
.......................................................... 123
CMPL (Compare Long Word Data of Destination and
Source) .............................................. 125
CMPW (Compare Word Data of Destination and
Source) .............................................. 127
CWBNE (Compare Word Data and Branch if not
Equal) ................................................ 129
Condition Code Register
AND (And Byte Data of Immediate Data and
Condition Code Register)....................... 95
Condition Code Register (CCR) .......................... 25
OR (Or Byte Data of Immediate Data and Condition
Code Register to Condition Code Register)
.......................................................... 230
Context
JCTX (Jump Context)....................................... 165
CPU
CPU Memory Space............................................. 6
Features of the F2MC-16LX CPU Core.................. 2
Overview of the F2MC-16LX CPU Core................ 2
Create
UNLINK (Unlink and Create New Stack Frame)
.......................................................... 279
LINK (Link and create new stack frame)............ 169
CWBNE
CWBNE (Compare Word Data and Branch if not
Equal) ................................................ 129
D
Data Counter
Data Counter (DCT)........................................... 57
Data Operation Instruction
Numeric Data Operation Instructions ................. 307
DBNZ
DBNZ (Decrement Byte Data and Branch if not Zero)
.......................................................... 131
DCT
Data Counter (DCT)........................................... 57
DEC
DEC (Decrement Byte Data) ............................. 133
Decimal Data
ADDDC (Add Decimal Data of AL and AH with
Carry to AL)......................................... 86
SUBDC (Subtract Decimal Data of AL from AH with
Carry to AL) .......................................271
DECL
DECL (Decrement Long Word Data) .................134
Decrement
DBNZ (Decrement Byte Data and Branch if not Zero)
..........................................................131
DEC (Decrement Byte Data) .............................133
DECL (Decrement Long Word Data) .................134
DECW (Decrement Word Data).........................135
DWBNZ (Decrement Word Data and Branch if not
Zero) ..................................................145
DECW
DECW (Decrement Word Data).........................135
Dedicated Register
F2MC-16LX Dedicated Register Types ................16
Descriptor
Extended Intelligent I/O Service Descriptor (ISD)
............................................................55
Destination
ADD (Add Byte Data of Destination and Source to
Destination) ..........................................79
ADDL (Add Long Word Data of Destination and
Source to Destination)............................87
ADDW (Add Word Data of Destination and Source to
Destination) ..........................................91
AND (And Byte Data of Destination and Source to
Destination) ..........................................93
ANDL (And Long Word Data of Destination and
Source to Destination)............................97
ANDW (And Word Data of Destination and Source to
Destination) ........................................100
CMP (Compare Byte Data of Destination and Source)
..........................................................123
CMPL (Compare Long Word Data of Destination and
Source) ...............................................125
CMPW (Compare Word Data of Destination and
Source) ...............................................127
JMP (Jump Destination Address) .......................167
JMPP (Jump Destination Physical Address) ........168
MOV (Move Byte Data from Accumulator to
Destination) ........................................183
MOV (Move Byte Data from Source to Destination)
..........................................................186
MOV (Move Byte Immediate Data to Destination)
..........................................................184
MOVEA (Move Effective Address to Destination)
..........................................................193
MOVL (Move Long Word Data from Accumulator to
Destination) ........................................195
MOVW (Move Immediate Word Data to Destination)
..........................................................205
MOVW (Move Word Data from Accumulator to
Destination) ........................................203
MOVW (Move Word Data from Source to
Destination) ........................................207
359
INDEX
NEG (Negate Byte Data of Destination) ............. 221
NEGW (Negate Word Data of Destination) ........ 222
NOT (Not Byte Data of Destination) .................. 224
NOTW (Not Word Data of Destination) ............. 226
OR (Or Byte Data of Destination and Source to
Destination) ........................................ 228
ORL (Or Long Word Data of Destination and Source
to Destination) .................................... 232
ORW (Or Word Data of Destination and Source to
Destination) ........................................ 235
SUB (Subtract Byte Data of Source from Destination
to Destination) .................................... 264
SUBL (Subtract Long Word Data of Source from
Destination to Destination) ................... 272
SUBW (Subtract Word Data of Source from
Destination to Destination) ................... 274
XCH (Exchange Byte Data of Source to Destination)
282
XCHW (Exchange Word Data of Source to
Destination) ........................................ 284
XOR (Exclusive Or Byte Data of Destination and
Source to Destination) ......................... 286
XORL (Exclusive Or Long Word Data of Destination
and Source to Destination) ................... 288
XORW (Exclusive Or Word Data of Destination and
Source to Destination) ......................... 291
Detailed Execution Instruction
Reading Detailed Execution Instructions .............. 78
Symbols (abbreviations) Used in Detailed Execution
Instructions ........................................... 70
Device
Sample Configuration of an F2MC-16LX Device
.............................................................. 3
Direct Addressing
Direct Addressing............................................... 61
Direct Page Register
Direct Page Register (DPR)................................. 27
DIV
DIV (Divide Word Data by Byte Data)............... 137
Divide
DIV (Divide Word Data by Byte Data)............... 137
DIVU (Divide unsigned Word Data by unsigned Byte
Data).................................................. 141
DIVUW (Divide unsigned Long Word Data by
unsigned Word Data) ........................... 143
DIVW (Divide Long Word Data by Word Data)
.......................................................... 139
DIVU
DIVU (Divide unsigned Word Data by unsigned Byte
Data).................................................. 141
DIVUW
DIVUW (Divide unsigned Long Word Data by
unsigned Word Data) ........................... 143
360
DIVW
DIVW (Divide Long Word Data by Word Data)
......................................................... 139
DPR
Direct Page Register (DPR) ................................ 27
DWBNZ
DWBNZ (Decrement Word Data and Branch if not
Zero) ................................................. 145
E
ea-type Instruction
ea-type Instruction Map .................................... 331
Effective Address
ADDC (Add Byte Data of Accumulator and Effective
Address with Carry to Accumulator)....... 82
ADDCW (Add Word Data of Accumulator and
Effective
Address
with
Carry
to
Accumulator) ....................................... 84
Effective Address Field ........................ 60, 72, 301
MOVEA (Move Effective Address to Destination)
......................................................... 193
MUL (Multiply Byte Data of Accumulator and
Effective Address) .............................. 214
MULU (Multiply Unsigned Byte Data of Accumulator
and Effective Address) ........................ 218
MULUW (Multiply Unsigned Word Data of
Accumulator and Effective Address)
......................................................... 220
MULW (Multiply Word Data of Accumulator and
Effective Address) .............................. 216
SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
......................................................... 267
SUBCW (Subtract Word Data of Effective Address
from
Accumulator
with
Carry
to
Accumulator) ..................................... 269
Exception
Exception Occurrence because of the Execution of an
Undefined Instruction............................ 58
Exchange
XCH (Exchange Byte Data of Source to Destination)
282
XCHW (Exchange Word Data of Source to
Destination)........................................ 284
Exclusive Or
XOR (Exclusive Or Byte Data of Destination and
Source to Destination) ......................... 286
XORL (Exclusive Or Long Word Data of Destination
and Source to Destination) ................... 288
XORW (Exclusive Or Word Data of AH and AL to
AL) ................................................... 290
XORW (Exclusive Or Word Data of Destination and
Source to Destination) ......................... 291
Execution Cycle
Calculating Execution Cycles.............................. 74
INDEX
Calculating the Number of Execution Cycles ...... 302
Execution Cycles ............................................... 73
Number of Execution Cycles............................. 298
EXT
EXT (Sign Extend from Byte Data to Word Data)
.......................................................... 147
Extended Intelligent I/O Service
Extended Intelligent I/O Service Channel Selection
Bits (bit15 to bit12 or bit7 to bit4: ICS0 to
ICS3) ................................................... 53
Extended Intelligent I/O Service Enable Bit (bit11 or
bit3: ISE) ............................................. 54
Extended Intelligent I/O Service End Status (bit13,bit
12 or bit5,bit4: S0,S1) ........................... 54
Flowchart of Extended Intelligent I/O Service
Application Procedure ........................... 51
Flowchart of Extended Intelligent I/O Service
Operation ............................................. 50
Overview of Extended Intelligent I/O Service ....... 48
Structure of Extended Intelligent I/O Service ........ 48
Extended Intelligent I/O Service Descriptor
Extended Intelligent I/O Service Descriptor (ISD)
............................................................ 55
Extended Intelligent I/O Service Status Register
Extended Intelligent I/O Service Status Register
(ISCS).................................................. 56
EXTW
EXTW (Sign Extend from Word Data to Long Word
Data).................................................. 148
F
F2MC-16LX
F2MC-16LX Dedicated Register Types................ 16
Features of the F2MC-16LX CPU Core.................. 2
Overview of the F2MC-16LX CPU Core................ 2
Sample Configuration of an F2MC-16LX Device.... 3
Fill
FILS (Fill String Byte) ..................................... 149
FILSW (Fill String Word)................................. 151
FILS
FILS (Fill String Byte) ..................................... 149
FILSW
FILSW (Fill String Word)................................. 151
Flag Change Inhibit Prefix Code
Flag Change Inhibit Prefix Code (NCC) ............... 37
G
General-purpose Registers
Calling General-purpose Registers in RAM .......... 31
H
Hardware Interrupt
Hardware Interrupt Operation Flow ..................... 44
I
I/O Register Address Pointer
I/O Register Address Pointer (IOA)......................57
ICR
Functions of Interrupt Control Registers (ICR0 to
ICR15) .................................................52
Interrupt Control Register (ICR) Bit Configuration 52
ILM
Interrupt Level Mask Register (ILM)....................23
Immediate Data
ADDSP (Add Word Data of Stack Pointer and
Immediate Data to Stack Pointer) ............89
AND (And Byte Data of Immediate Data and
Condition Code Register) .......................95
MOV (Move Byte Immediate Data to Destination)
..........................................................184
OR (Or Byte Data of Immediate Data and Condition
Code Register to Condition Code Register)
..........................................................230
Immediate Nibble Data
MOVN (Move Immediate Nibble Data to
Accumulator) ......................................196
Immediate Word Data
MOVW (Move Immediate Word Data to Destination)
205
MOVW (Move Immediate Word Data to io) .......209
INC
INC (Increment Byte Data (Address Specification))
..........................................................153
INCL
INCL (Increment Long Word Data)....................154
Increment
INC (Increment Byte Data (Address Specification))
..........................................................153
INCL (Increment Long Word Data)....................154
INCW (Increment Word Data) ...........................155
INCW
INCW (Increment Word Data) ...........................155
Indirect Addressing
Indirect Addressing.............................................63
Inherent Register
PUSHW (Push Word Data of Inherent Register to
Stack Memory)....................................244
Instruction
2-byte Instruction Map ......................................329
Bit Operation Instruction Map ...........................325
Branch Instruction ............................................314
Character String Operation Instruction Map ........327
ea-type Instruction Map.....................................331
Exception Occurrence because of the Execution of an
Undefined Instruction.............................58
Explanation of the Items Used in the Instruction Lists
..........................................................297
361
INDEX
Explanation of the Symbols Used in the Instruction
Lists................................................... 299
Instruction Overview .......................................... 68
Logical Operation Instruction ............................ 311
MOV ea, Ri Instruction Map ............................. 346
MOV Ri, ea Instruction Map ............................. 343
MOVEA RWi, ea Instruction Map ..................... 341
MOVW ea, RWi Instruction Map ...................... 348
MOVW RWi, ea Instruction Map ...................... 345
Numeric Data Operation Instructions ................. 307
Other Instructions............................................. 316
Reading Detailed Execution Instructions .............. 78
Relationships between Instructions Rejecting Interrupt
Requests and Prefix Codes ..................... 38
Shift Instruction ............................................... 313
Structure of the Instruction Map ........................ 320
Symbols (abbreviations) Used in Detailed Execution
Instructions ........................................... 70
Transfer Instruction .......................................... 305
XCH Ri, ea Instruction Map .............................. 351
XCHW RWi, ea Instruction Map ....................... 352
Instruction Map
Structure of the Instruction Map ........................ 320
INT
INT (Software Interrupt (Vector Specification))
.......................................................... 159
INT (Software Interrupt) ................................... 157
INT9
INT9 (Software Interrupt) ................................. 161
Interrupt
Hardware Interrupt Operation Flow...................... 44
INT (Software Interrupt (Vector Specification))
.......................................................... 159
INT (Software Interrupt) ................................... 157
INT9 (Software Interrupt) ................................. 161
Interrupt Handling .............................................. 42
Interrupt Handling Flowchart .............................. 45
Interrupt Vectors ................................................ 47
INTP (Software Interrupt) ................................. 163
Relationships between Instructions Rejecting Interrupt
Requests and Prefix Codes ..................... 38
RETI (Return from Interrupt) ............................ 249
Interrupt Control Register
Functions of Interrupt Control Registers (ICR0 to
ICR15) ................................................. 52
Interrupt Control Register (ICR) Bit Configuration
............................................................ 52
Interrupt Handling
Interrupt Handling .............................................. 42
Interrupt Handling Flowchart .............................. 45
Interrupt Level Mask Register
Interrupt Level Mask Register (ILM) ................... 23
Interrupt Level Setting Bits
Interrupt Level Setting Bits (bit10 to bit8 or bit2 to
bit0: IL2 to IL0) .................................... 54
362
Interrupt Vectors
Interrupt Vectors................................................ 47
INTP
INTP (Software Interrupt)................................. 163
IOA
I/O Register Address Pointer (IOA) ..................... 57
ISCS
Extended Intelligent I/O Service Status Register
(ISCS) ................................................. 56
ISD
Extended Intelligent I/O Service Descriptor (ISD)
........................................................... 55
J
JCTX
JCTX (Jump Context) ...................................... 165
JMP
JMP (Jump Destination Address)....................... 167
JMPP
JMPP (Jump Destination Physical Address) ....... 168
Jump
JCTX (Jump Context) ...................................... 165
JMP (Jump Destination Address)....................... 167
JMPP (Jump Destination Physical Address) ....... 168
L
Left
LSL (Logical Shift Byte Data of Accumulator to Left)
......................................................... 170
LSLL (Logical Shift Long Word Data of Accumulator
to Left)............................................... 171
LSLW (Logical Shift Word Data of Accumulator to
Left) .......................................... 172, 173
ROLC (Rotate Byte Data of Accumulator with Carry
to Left)............................................... 253
Linear Addressing
Linear Addressing Mode ...................................... 7
Linear Addressing Mode
Linear Addressing Mode ...................................... 7
LINK
LINK (Link and create new stack frame)............ 169
Logical Operation Instruction
Logical Operation Instruction............................ 311
Logical Shift
LSL (Logical Shift Byte Data of Accumulator to Left)
......................................................... 170
LSLL (Logical Shift Long Word Data of Accumulator
to Left)............................................... 171
LSLW (Logical Shift Word Data of Accumulator to
Left) .......................................... 172, 173
LSR (Logical Shift Byte Data of Accumulator to
Right) ................................................ 174
INDEX
LSRL (Logical Shift Long Word Data of Accumulator
to Right)............................................. 176
LSRW (Logical Shift Word Data of Accumulator to
Right) ........................................ 178, 179
Long Word
ANDL (And Long Word Data of Destination and
Source to Destination) ........................... 97
NRML (NORMALIZE Long Word) .................. 227
Long Word Data
ADDL (Add Long Word Data of Destination and
Source to Destination) ........................... 87
DECL (Decrement Long Word Data)................. 134
DIVW (Divide Long Word Data by Word Data)
.......................................................... 139
EXTW (Sign Extend from Word Data to Long Word
Data).................................................. 148
INCL (Increment Long Word Data) ................... 154
LSLL (Logical Shift Long Word Data of Accumulator
to Left)............................................... 171
LSRL (Logical Shift Long Word Data of Accumulator
to Right)............................................. 176
MOVL (Move Long Word Data from Accumulator to
Destination)........................................ 195
MOVL (Move Long Word Data from Source to
Accumulator)...................................... 194
ORL (Or Long Word Data of Destination and Source
to Destination) .................................... 232
SUBL (Subtract Long Word Data of Source from
Destination to Destination)................... 272
XORL (Exclusive Or Long Word Data of Destination
and Source to Destination) ................... 288
ZEXTW (Zero Extend from Word Data to Long Word
Data).................................................. 294
LSL
LSL (Logical Shift Byte Data of Accumulator to Left)
.......................................................... 170
LSLL
LSLL (Logical Shift Long Word Data of Accumulator
to Left)............................................... 171
LSLW
LSLW (Logical Shift Word Data of Accumulator to
Left) .......................................... 172, 173
LSR
LSR (Logical Shift Byte Data of Accumulator to
Right) ................................................ 174
LSRL
LSRL (Logical Shift Long Word Data of Accumulator
to Right)............................................. 176
LSRW
LSRW (Logical Shift Word Data of Accumulator to
Right) ........................................ 178, 179
M
Memory Space
CPU Memory Space............................................. 6
Memory Space Divided into Banks and Values in
Each Register Bank................................11
Multi-byte Data Layout in a Memory Space ..........12
Mode
Bank Addressing Mode .........................................9
Linear Addressing Mode .......................................7
MOV
MOV (Move Byte Data from Accumulator to
Destination) ........................................183
MOV (Move Byte Data from AH to Memory).....188
MOV (Move Byte Data from Source to Accumulator)
181
MOV (Move Byte Data from Source to Destination)
..........................................................186
MOV (Move Byte Immediate Data to Destination)
..........................................................184
MOV ea, Ri Instruction
MOV ea, Ri Instruction Map .............................346
MOV Ri, ea Instruction
MOV Ri, ea Instruction Map .............................343
MOVB
MOVB (Move Bit Data from Accumulator to Bit
Address) .............................................191
MOVB (Move Bit Data from Bit Address to
Accumulator) ......................................189
Move
MOV (Move Byte Data from Accumulator to
Destination) ........................................183
MOV (Move Byte Data from AH to Memory).....188
MOV (Move Byte Data from Source to Accumulator)
..........................................................181
MOV (Move Byte Data from Source to Destination)
..........................................................186
MOV (Move Byte Immediate Data to Destination)
..........................................................184
MOVB (Move Bit Data from Accumulator to Bit
Address) .............................................191
MOVB (Move Bit Data from Bit Address to
Accumulator) ......................................189
MOVEA (Move Effective Address to Destination)
..........................................................193
MOVL (Move Long Word Data from Accumulator to
Destination) ........................................195
MOVL (Move Long Word Data from Source to
Accumulator) ......................................194
MOVN (Move Immediate Nibble Data to
Accumulator) ......................................196
MOVS (Move String Byte)................................197
MOVSW (Move String Word) ...........................199
MOVW (Move Immediate Word Data to Destination)
..........................................................205
MOVW (Move Immediate Word Data to io) .......209
MOVW (Move Word Data from Accumulator to
Destination) ........................................203
MOVW (Move Word Data from AH to Memory)
..........................................................210
363
INDEX
MOVW
(Move Word Data from Source to
Accumulator)...................................... 201
MOVW (Move Word Data from Source to
Destination) ........................................ 207
MOVX (Move Byte Data with Sign Extension from
Source to Accumulator) ....................... 211
MOVEA
MOVEA (Move Effective Address to Destination)
.......................................................... 193
MOVEA RWi, ea Instruction
MOVEA RWi, ea Instruction Map ..................... 341
MOVL
MOVL (Move Long Word Data from Accumulator to
Destination) ........................................ 195
MOVL (Move Long Word Data from Source to
Accumulator)...................................... 194
MOVN
MOVN (Move Immediate Nibble Data to
Accumulator)...................................... 196
MOVS
MOVS (Move String Byte) ............................... 197
MOVSW
MOVSW (Move String Word)........................... 199
MOVW
MOVW (Move Immediate Word Data to Destination)
205
MOVW (Move Immediate Word Data to io) ....... 209
MOVW (Move Word Data from Accumulator to
Destination) ........................................ 203
MOVW (Move Word Data from AH to Memory)
.......................................................... 210
MOVW (Move Word Data from Source to
Accumulator)...................................... 201
MOVW (Move Word Data from Source to
Destination) ........................................ 207
MOVW ea, RWi Instruction
MOVW ea, RWi Instruction Map ...................... 348
MOVW RWi, ea Instruction
MOVW RWi, ea Instruction Map ...................... 345
MOVX
MOVX (Move Byte Data with Sign Extension from
Source to Accumulator) ....................... 211
MUL
MUL (Multiply Byte Data of Accumulator) ........ 213
MUL (Multiply Byte Data of Accumulator and
Effective Address)............................... 214
Multi-byte Data
Access to Multi-byte Data ................................... 13
Multi-byte Data Layout in a Memory Space.......... 12
Multiply
MUL (Multiply Byte Data of Accumulator) ........ 213
MUL (Multiply Byte Data of Accumulator and
Effective Address)............................... 214
MULU (Multiply Unsigned Byte Data of
364
Accumulator) ..................................... 217
MULU (Multiply Unsigned Byte Data of Accumulator
and Effective Address) ........................ 218
MULUW (Multiply Unsigned Word Data of
Accumulator) ..................................... 219
MULUW (Multiply Unsigned Word Data of
Accumulator and Effective Address)
......................................................... 220
MULW (Multiply Word Data of Accumulator)
......................................................... 215
MULW (Multiply Word Data of Accumulator and
Effective Address) .............................. 216
MULU
MULU (Multiply Unsigned Byte Data of
Accumulator) ..................................... 217
MULU (Multiply Unsigned Byte Data of Accumulator
and Effective Address) ........................ 218
MULUW
MULUW (Multiply Unsigned Word Data of
Accumulator) ..................................... 219
MULUW (Multiply Unsigned Word Data of
Accumulator and Effective Address)
......................................................... 220
MULW
MULW (Multiply Word Data of Accumulator)
......................................................... 215
MULW (Multiply Word Data of Accumulator and
Effective Address) .............................. 216
N
NCC
Flag Change Inhibit Prefix Code (NCC)............... 37
NEG
NEG (Negate Byte Data of Destination)............. 221
Negate
NEG (Negate Byte Data of Destination)............. 221
NEGW (Negate Word Data of Destination) ........ 222
NEGW
NEGW (Negate Word Data of Destination) ........ 222
No Operation
NOP (No Operation) ........................................ 223
NOP
NOP (No Operation) ........................................ 223
NORMALIZE
NRML (NORMALIZE Long Word) .................. 227
NOT
NOT (Not Byte Data of Destination).................. 224
NOTW
NOTW (Not Word Data of Destination)............. 226
NRML
NRML (NORMALIZE Long Word) .................. 227
INDEX
O
OR
OR (Or Byte Data of Destination and Source to
Destination)........................................ 228
OR (Or Byte Data of Immediate Data and Condition
Code Register to Condition Code Register)
.......................................................... 230
Or
OR (Or Byte Data of Destination and Source to
Destination)........................................ 228
OR (Or Byte Data of Immediate Data and Condition
Code Register to Condition Code Register)
.......................................................... 230
ORL (Or Long Word Data of Destination and Source
to Destination) .................................... 232
ORW (Or Word Data of AH and AL to AL) ....... 234
ORW (Or Word Data of Destination and Source to
Destination)........................................ 235
ORL
ORL (Or Long Word Data of Destination and Source
to Destination) .................................... 232
ORW
ORW (Or Word Data of AH and AL to AL) ....... 234
ORW (Or Word Data of Destination and Source to
Destination)........................................ 235
P
Page Map
Basic Page Map ............................................... 322
PC
Program Counter (PC) ........................................ 26
Physical Address
JMPP (Jump Destination Physical Address)........ 168
RETP (Return from Physical Address) ............... 251
physical Address
CALLP (Call physical Address) ........................ 116
Pop
POPW (Pop Registers from Stack Memory) ....... 242
POPW (Pop Word Data of Accumulator from Stack
Memory) ............................................ 237
POPW (Pop Word Data of AH from Stack Memory)
.......................................................... 239
POPW (Pop Word Data of Program Status from Stack
Memory) ............................................ 240
POPW
POPW (Pop Registers from Stack Memory) ....... 242
POPW (Pop Word Data of Accumulator from Stack
Memory) ............................................ 237
POPW (Pop Word Data of AH from Stack Memory)
.......................................................... 239
POPW (Pop Word Data of Program Status from Stack
Memory) ............................................ 240
Prefix
Bank Select Prefix.............................................. 34
Common Register Bank Prefix (CMR) .................36
Flag Change Inhibit Prefix Code (NCC) ...............37
If Two or More Prefix Codes Appear in Succession
............................................................39
Relationships between Instructions Rejecting Interrupt
Requests and Prefix Codes......................38
Processor Status
Processor Status (PS) ..........................................22
Program Counter
Program Counter (PC).........................................26
Program Status
POPW (Pop Word Data of Program Status from Stack
Memory).............................................240
PS
Processor Status (PS) ..........................................22
Push
PUSHW (Push Registers to Stack Memory) ........246
PUSHW (Push Word Data of Inherent Register to
Stack Memory)....................................244
PUSHW
PUSHW (Push Registers to Stack Memory) ........246
PUSHW (Push Word Data of Inherent Register to
Stack Memory)....................................244
R
RAM
Calling General-purpose Registers in RAM...........31
Register Banks in RAM ......................................30
Register
AND (And Byte Data of Immediate Data and
Condition Code Register) .......................95
Condition Code Register (CCR) ...........................25
Direct Page Register (DPR) .................................27
Extended Intelligent I/O Service Status Register
(ISCS) ..................................................56
Functions of Interrupt Control Registers (ICR0 to
ICR15) .................................................52
Interrupt Control Register (ICR) Bit Configuration 52
Interrupt Level Mask Register (ILM)....................23
Register Bank
Memory Space Divided into Banks and Values in
Each Register Bank................................11
Register Bank Pointer
Register Bank Pointer (RP)..................................24
Register Banks
Register Banks in RAM ......................................30
RET
RET (Return from Subroutine)...........................248
RETI
RETI (Return from Interrupt).............................249
RETP
RETP (Return from Physical Address)................251
Return
RET (Return from Subroutine)...........................248
365
INDEX
RETI (Return from Interrupt) ............................ 249
RETP (Return from Physical Address) ............... 251
Right
ASR (Arithmetic Shift Byte Data of Accumulator to
Right)................................................. 102
ASRL (Arithmetic Shift Long Word Data of
Accumulator to Right) ......................... 104
ASRW (Arithmetic Shift Word Data of Accumulator
to Right) ..................................... 106, 108
LSR (Logical Shift Byte Data of Accumulator to
Right)................................................. 174
LSRL (Logical Shift Long Word Data of Accumulator
to Right) ............................................. 176
LSRW (Logical Shift Word Data of Accumulator to
Right)......................................... 178, 179
RORC (Rotate Byte Data of Accumulator with Carry
to Right) ............................................. 255
ROLC
ROLC (Rotate Byte Data of Accumulator with Carry
to Left) ............................................... 253
RORC
RORC (Rotate Byte Data of Accumulator with Carry
to Right) ............................................. 255
Rotate
ROLC (Rotate Byte Data of Accumulator with Carry
to Left) ............................................... 253
RORC (Rotate Byte Data of Accumulator with Carry
to Right) ............................................. 255
RP
Register Bank Pointer (RP) ................................. 24
S
Sample Configuration
Sample Configuration of an F2MC-16LX Device
.............................................................. 3
SBBS
SBBS (Set Bit and Branch if Bit Set).................. 257
Scan
SCEQ (Scan String Byte Until Equal) ................ 259
SCWEQ (Scan String Word until Equal) ............ 261
SCEQ
SCEQ (Scan String Byte Until Equal) ................ 259
SCWEQ
SCWEQ (Scan String Word until Equal) ............ 261
Set
SBBS (Set Bit and Branch if Bit Set).................. 257
SETB (Set Bit)................................................. 263
SETB
SETB (Set Bit)................................................. 263
Shift Instruction
Shift Instruction ............................................... 313
Sign
EXT (Sign Extend from Byte Data to Word Data)
.......................................................... 147
366
EXTW (Sign Extend from Word Data to Long Word
Data) ................................................. 148
Sign Extension
MOVX (Move Byte Data with Sign Extension from
Source to Accumulator) ....................... 211
Software Interrupt
INT (Software Interrupt (Vector Specification))
......................................................... 159
INT (Software Interrupt)................................... 157
INT9 (Software Interrupt) ................................. 161
INTP (Software Interrupt)................................. 163
Source
ADD (Add Byte Data of Destination and Source to
Destination).......................................... 79
ADDL (Add Long Word Data of Destination and
Source to Destination) ........................... 87
ADDW (Add Word Data of Destination and Source to
Destination).......................................... 91
AND (And Byte Data of Destination and Source to
Destination).......................................... 93
ANDL (And Long Word Data of Destination and
Source to Destination) ........................... 97
ANDW (And Word Data of Destination and Source to
Destination)........................................ 100
CMP (Compare Byte Data of Destination and Source)
......................................................... 123
CMPL (Compare Long Word Data of Destination and
Source) .............................................. 125
CMPW (Compare Word Data of Destination and
Source) .............................................. 127
MOV (Move Byte Data from Source to Accumulator)
......................................................... 181
MOV (Move Byte Data from Source to Destination)
......................................................... 186
MOVL (Move Long Word Data from Source to
Accumulator) ..................................... 194
MOVW (Move Word Data from Source to
Accumulator) ..................................... 201
MOVW (Move Word Data from Source to
Destination)........................................ 207
MOVX (Move Byte Data with Sign Extension from
Source to Accumulator) ....................... 211
OR (Or Byte Data of Destination and Source to
Destination)........................................ 228
ORL (Or Long Word Data of Destination and Source
to Destination) .................................... 232
ORW (Or Word Data of Destination and Source to
Destination)........................................ 235
SUB (Subtract Byte Data of Source from Destination
to Destination) .................................... 264
SUBL (Subtract Long Word Data of Source from
Destination to Destination)................... 272
SUBW (Subtract Word Data of Source from
Destination to Destination)................... 274
XCH (Exchange Byte Data of Source to Destination)
......................................................... 282
INDEX
XCHW (Exchange Word Data of Source to
Destination)........................................ 284
XOR (Exclusive Or Byte Data of Destination and
Source to Destination) ......................... 286
XORL (Exclusive Or Long Word Data of Destination
and Source to Destination) ................... 288
XORW (Exclusive Or Word Data of Destination and
Source to Destination) ......................... 291
SSP
User Stack Pointer (USP) and System Stack Pointer
(SSP) ................................................... 20
Stack
POPW (Pop Registers from Stack Memory) ....... 242
POPW (Pop Word Data of Accumulator from Stack
Memory) ............................................ 237
POPW (Pop Word Data of AH from Stack Memory)
.......................................................... 239
POPW (Pop Word Data of Program Status from Stack
Memory) ............................................ 240
PUSHW (Push Registers to Stack Memory) ....... 246
PUSHW (Push Word Data of Inherent Register to
Stack Memory) ................................... 244
Stack Frame
UNLINK (Unlink and Create New Stack Frame)
.......................................................... 279
LINK (Link and create new stack frame)............ 169
Stack Pointer
ADDSP (Add Word Data of Stack Pointer and
Immediate Data to Stack Pointer) ........... 89
String Byte
FILS (Fill String Byte) ..................................... 149
MOVS (Move String Byte) ............................... 197
SCEQ (Scan String Byte Until Equal) ................ 259
String Word
FILSW (Fill String Word)................................. 151
MOVSW (Move String Word) .......................... 199
SCWEQ (Scan String Word until Equal) ............ 261
SUB
SUB (Subtract Byte Data of Source from Destination
to Destination) .................................... 264
SUBC
SUBC (Subtract Byte Data of AL from AH with Carry
to AL) ................................................ 266
SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator)
.......................................................... 267
SUBCW
SUBCW (Subtract Word Data of Effective Address
from
Accumulator
with
Carry
to
Accumulator)...................................... 269
SUBDC
SUBDC (Subtract Decimal Data of AL from AH with
Carry to AL)....................................... 271
SUBL
SUBL (Subtract Long Word Data of Source from
Destination to Destination) ...................272
Subroutine
RET (Return from Subroutine)...........................248
Subtract
SUB (Subtract Byte Data of Source from Destination
to Destination).....................................264
SUBC (Subtract Byte Data of AL from AH with Carry
to AL) ................................................266
SUBC (Subtract Byte Data of Effective Address from
Accumulator with Carry to Accumulator
) .........................................................267
SUBCW (Subtract Word Data of Effective Address
from
Accumulator
with
Carry
to
Accumulator) ......................................269
SUBDC (Subtract Decimal Data of AL from AH with
Carry to AL) .......................................271
SUBL (Subtract Long Word Data of Source from
Destination to Destination) ...................272
SUBW (Subtract Word Data of AL from AH to AL)
..........................................................276
SUBW (Subtract Word Data of Source from
Destination to Destination) ...................274
SUBW
SUBW (Subtract Word Data of AL from AH to AL)
..........................................................276
SUBW (Subtract Word Data of Source from
Destination to Destination) ...................274
SWAP
SWAP (Swap Byte Data of Accumulator) ...........277
SWAPW
SWAPW (Swap Word Data of Accumulator) ......278
Symbol
Explanation of the Symbols Used in the Instruction
Lists ...................................................299
Symbols (abbreviations) Used in Detailed Execution
Instructions ...........................................70
System Stack Pointer
User Stack Pointer (USP) and System Stack Pointer
(SSP)....................................................20
T
Transfer Instruction
Transfer Instruction ..........................................305
U
Undefined Instruction
Exception Occurrence because of the Execution of an
Undefined Instruction.............................58
UNLINK
UNLINK (Unlink and Create New Stack Frame)
..........................................................279
367
INDEX
Unsigned Byte Data
MULU (Multiply Unsigned Byte Data of Accumulator
and Effective Address)......................... 218
unsigned Byte Data
DIVU (Divide unsigned Word Data by unsigned Byte
Data).................................................. 141
unsigned Long Word Data
DIVUW (Divide unsigned Long Word Data by
unsigned Word Data) ........................... 143
Unsigned Word Data
MULUW (Multiply Unsigned Word Data of
Accumulator)...................................... 219
MULUW (Multiply Unsigned Word Data of
Accumulator and Effective Address)
.......................................................... 220
unsigned Word Data
DIVU (Divide unsigned Word Data by unsigned Byte
Data).................................................. 141
DIVUW (Divide unsigned Long Word Data by
unsigned Word Data) ........................... 143
User Stack Pointer
User Stack Pointer (USP) and System Stack Pointer
(SSP) ................................................... 20
USP
User Stack Pointer (USP) and System Stack Pointer
(SSP) ................................................... 20
V
Vector Specification
INT (Software Interrupt (Vector Specification))
.......................................................... 159
Vectored Subroutine
CALLV (Call Vectored Subroutine)................... 118
W
Wait
WBTc (Wait until Bit Condition Satisfied) ......... 280
WBTc
WBTc (Wait until Bit Condition Satisfied) ......... 280
Word Data
ADDSP (Add Word Data of Stack Pointer and
Immediate Data to Stack Pointer)............ 89
ADDW (Add Word Data of AL and AH to AL) .... 90
ADDW (Add Word Data of Destination and Source to
Destination) .......................................... 91
ANDW (And Word Data of AH and AL to AL) .... 99
ANDW (And Word Data of Destination and Source to
Destination) ........................................ 100
CMPL (Compare Long Word Data of Destination and
Source)............................................... 125
CMPW (Compare Word Data of Destination and
Source)............................................... 127
368
CWBNE (Compare Word Data and Branch if not
Equal) ................................................ 129
DECW (Decrement Word Data) ........................ 135
DIV (Divide Word Data by Byte Data) .............. 137
DIVW (Divide Long Word Data by Word Data)
......................................................... 139
DWBNZ (Decrement Word Data and Branch if not
Zero) ................................................. 145
EXT (Sign Extend from Byte Data to Word Data)
......................................................... 147
EXTW (Sign Extend from Word Data to Long Word
Data) ................................................. 148
INCW (Increment Word Data) .......................... 155
LSLW (Logical Shift Word Data of Accumulator to
Left) .......................................... 172, 173
LSRW (Logical Shift Word Data of Accumulator to
Right) ........................................ 178, 179
MOVW (Move Word Data from Accumulator to
Destination)........................................ 203
MOVW (Move Word Data from AH to Memory) 210
MOVW (Move Word Data from Source to
Accumulator) ..................................... 201
MOVW (Move Word Data from Source to
Destination)........................................ 207
MULW (Multiply Word Data of Accumulator)
......................................................... 215
MULW (Multiply Word Data of Accumulator and
Effective Address) .............................. 216
NEGW (Negate Word Data of Destination) ........ 222
NOTW (Not Word Data of Destination)............. 226
ORW (Or Word Data of AH and AL to AL) ....... 234
ORW (Or Word Data of Destination and Source to
Destination)........................................ 235
POPW (Pop Word Data of Accumulator from Stack
Memory) ............................................ 237
POPW (Pop Word Data of AH from Stack Memory)
......................................................... 239
POPW (Pop Word Data of Program Status from Stack
Memory) ............................................ 240
PUSHW (Push Word Data of Inherent Register to
Stack Memory) ................................... 244
SUBCW (Subtract Word Data of Effective Address
from
Accumulator
with
Carry
to
Accumulator) ..................................... 269
SUBW (Subtract Word Data of AL from AH to AL)
......................................................... 276
SUBW (Subtract Word Data of Source from
Destination to Destination)................... 274
SWAPW (Swap Word Data of Accumulator) ..... 278
XCHW (Exchange Word Data of Source to
Destination)........................................ 284
XORW (Exclusive Or Word Data of AH and AL to
AL) ................................................... 290
XORW (Exclusive Or Word Data of Destination and
Source to Destination) ......................... 291
ZEXT (Zero Extend from Byte Data to Word Data)
......................................................... 293
INDEX
ZEXTW (Zero Extend from Word Data to Long Word
Data).................................................. 294
X
XCH
XCH (Exchange Byte Data of Source to Destination)
282
XCH Ri, ea Instruction
XCH Ri, ea Instruction Map.............................. 351
XCHW
XCHW (Exchange Word Data of Source to
Destination)........................................ 284
XCHW RWi, ea Instruction
XCHW RWi, ea Instruction Map ....................... 352
XOR
XOR (Exclusive Or Byte Data of Destination and
Source to Destination) ......................... 286
XORL
XORL (Exclusive Or Long Word Data of Destination
and Source to Destination)....................288
XORW
XORW (Exclusive Or Word Data of AH and AL to
AL) ....................................................290
XORW (Exclusive Or Word Data of Destination and
Source to Destination)..........................291
Z
Zero Extend
ZEXT (Zero Extend from Byte Data to Word Data
) .........................................................293
ZEXTW (Zero Extend from Word Data to Long Word
Data) ..................................................294
ZEXT
ZEXT (Zero Extend from Byte Data to Word Data
) .........................................................293
ZEXTW
ZEXTW (Zero Extend from Word Data to Long Word
Data) ..................................................294
369
INDEX
370
CM44-00201-3E
FUJITSU MICROELECTRONICS • CONTROLLER MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
PROGRAMMING MANUAL
May 2008 the third edition
Published
FUJITSU MICROELECTRONICS LIMITED
Edited
Strategic Business Development Dept.