A3946 Datasheet

A3946
Half-Bridge Power MOSFET Controller
Features and Benefits
Description
▪ On-chip charge pump for 7 V minimum input
supply voltage
▪ High-current gate drive for driving a wide range of
N-channel MOSFETs
▪ Bootstrapped gate drive with top-off charge pump
for 100% duty cycle
▪ Overtemperature protection
▪ Undervoltage protection
▪ –40ºC to 135ºC ambient operation
The A3946 is designed specifically for applications that require
high power unidirectional DC motors, three-phase brushless DC
motors, or other inductive loads. The A3946 provides two
high-current gate drive outputs that are capable of driving a
wide range of power N-channel MOSFETs. The high-side gate
driver switches an N-channel MOSFET that controls current to
the load, while the low-side gate driver switches an N-channel
MOSFET as a synchronous rectifier.
Package: 16-pin TSSOP with exposed
thermal pad (Suffix LP)
A bootstrap capacitor provides the above-battery supply voltage
required for N-channel MOSFETs. An internal top-off charge
pump for the high side allows DC (100% duty cycle) operation
of the half-bridge.
The A3946 is available in a power package: a 16-lead TSSOP
with exposed thermal pad (suffix LP). It is lead (Pb) free, with
100% matte tin plated leadframe (suffix -T).
Approximate Scale 1:1
Typical Application
VBAT
BOOT
VBB
~FAULT
ECU
IN1
IN2
RESET
DT
29319.150i
GH
A3946
PAD
S
GL
CP1
CP2
VREF
VREG
LGND
PGND
M
A3946
Half-Bridge Power MOSFET Controller
Selection Guide
Part Number
A3946KLPTR-T
Packing
4000 pieces/reel
Package
16-pin TSSOP with exposed thermal pad
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Units
V
Load Supply Voltage
VBB
60
Logic Inputs Voltage
VIN
–0.3 to 6.5
V
Pin S Voltage
VS
–4 to 60
V
VGH
–4 to 75
V
VBOOT
–0.6 to 75
V
Pin GH Voltage
Pin BOOT Voltage
Pin DT Voltage
VDT
VREF
V
Pin VREG Voltage
VREG
–0.6 to 15
V
–40 to 135
ºC
150
ºC
Operating Ambient Temperature
TA
Maximum Junction Temperature
TJ(max)
Storage Temperature
Range K
Tstg
–55 to 150
ºC
ESD Rating, Human Body Model
AEC-Q100-002, all pins
2000
V
ESD Rating, Charged Device Model
AEC-Q100-011, all pins
1050
V
THERMAL CHARACTERISTICS
Characteristic
Symbol
Test Conditions*
Value Units
Mounted on a 2-layer PCB with 3.8 in . 2-oz copper both sides
43
ºC/W
Mounted on a 4-layer PCB based on JEDEC standard
34
ºC/W
2
Package Thermal Resistance
RθJA
*Additional thermal information available on Allegro Web site.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3946
Half-Bridge Power MOSFET Controller
Functional Block Diagram
+VBAT
C1
0.47 uF, X7R
V rated to VBAT
C2
0.47 uF, X7R
V rated to VBAT
P
VBB
CP2
VREF
10
k7
L
VREG
Charge
Pump
+5 Vref
0.1 uF
X7R
10 V
CP1
L
CREG
ILIM
P
P
Top-Off
Charge Pump
BOOT
~FAULT
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
Bootstrap
UVLO
CBOOT
L
VREF
DT
RDEAD
Turn-On
Delay
IN1
P
Control
Logic
L
RGATE
GH
High Side
Driver
S
VREG
L
IN2
RGATE
GL
Low Side
Driver
PGND
L
P
RESET
LGND
L
L
P
PAD
Control Logic Table
IN1
IN2
X
X
0
0
0
1
1
1
DT Pin
RESET
GH
GL
Function
X
0
Z
Z
Sleep mode
RDEAD - LGND
1
L
H
Low-side FET ON following dead time
RDEAD - LGND
1
L
L
All OFF
0
RDEAD - LGND
1
L
L
All OFF
1
RDEAD - LGND
1
H
L
High-side FET ON following dead time
0
0
VREF
1
L
L
All OFF
0
1
VREF
1
L
H
Low-side FET ON
1
0
VREF
1
H
L
High-side FET ON
1
1
VREF
1
H
H
CAUTION: High-side and low-side FETs ON
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3946
Half-Bridge Power MOSFET Controller
ELECTRICAL CHARACTERISTICS at TA = –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted)
Characteristics
Symbol
Test Conditions
Limits
Min.
Typ.
Max.
Units
–
–
3
6
mA
–
10
μA
VBB > 7.75 V, Ireg = 0 mA to 15 mA
12.0
13
13.5
V
VBB = 7 V to 7.75 V, Ireg = 0 mA to 15 mA
11.0
–
13.5
V
–
62.5
–
kHz
RESET = High, Outputs Low
VBB Quiescent Current
IVBB
VREG Output Voltage
VREG
Charge Pump Frequency
FCP
CP1, CP2
VREF Output Voltage
VREF
IREF ≤ 4 mA, CREF = 0.1 μF
4.5
–
5.5
V
Top-Off Charge Pump
Current
ITO
VBOOT – VS = 8.5 V
20
–
–
μA
Turn On Time
trise
CLOAD = 3300 pF, 20% to 80%
60
100
ns
Turn Off Time
tfall
CLOAD = 3300 pF, 80% to 20%
–
–
–
–
–
–
40
80
ns
4
–

6
8

2
–

3
4

VREG – 1.5
–
–
V
VREG – 0.2
–
–
200
350
500
ns
Rdead = 100 kΩ
5
6
7
μs
Logic input to unloaded GH, GL. DT = VREF
–
–
150
ns
RESET = Low
Gate Output Drive
Pullup On Resistance
Pulldown On Resistance
RDSUP
RDSDOWN
GH Output Voltage
VGH
GL Output Voltage
VGL
Tj = 25C
Tj = 135C
Tj = 25C
Tj = 135C
tpw < 10 μs, Bootstrap Capacitor fully charged
–
V
Timing
Dead Time (Delay from
Turn Off to Turn On)
Propagation Delay
tDEAD
tPD
Rdead = 5 kΩ
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3946
Half-Bridge Power MOSFET Controller
ELECTRICAL CHARACTERISTICS at TA = –40 to +135°C, VBB = 7 to 60 V (unless otherwise noted)
Limits
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
7.8
8.3
8.8
V
Protection
VREGOFF
VREG decreasing
VREGON
VREG increasing
8.6
9.1
9.6
V
VBSOFF
VBOOT decreasing
7.25
7.8
8.3
V
VBSON
VBOOT increasing
8
8.75
9.5
V
Thermal Shutdown Temperature
TJTSD
Temperature increasing
170
TJ
Recovery = TJTSD – TJ
15
–
–
°C
Thermal Shutdown Hysteresis
–
–
IIN(1)
IN1 VIN / IN2 VIN = 2.0 V
40
100
μA
IIN(0)
IN1 VIN / IN2 VIN = 0.8 V
–
–
–
16
40
μA
–
–
–
–
–
–
–
1
μA
–
–
V
0.8
V
300
mV
400
mV
1
μA
VREG Undervoltage
BOOT Undervoltage
°C
Logic
Input Current
RESET pin only
Logic Input Voltage
VIN(1)
VIN(0)
Logic Input Hysteresis
Fault Output
IN1 / IN2 logic high
2.0
RESET logic high
2.2
Logic low
–
All digital inputs
Vol
I = 1 mA, fault asserted
Voh
V=5V
–
100
–
–
V
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A3946
Half-Bridge Power MOSFET Controller
Functional Description
VREG. A 13 V output from the on-chip charge pump, used
to power the low-side gate drive circuit directly, provides the
current to charge the bootstrap capacitors for the high-side gate
drive.
possible UVBOOT), FAULT = 0; also the fault latch is cleared
immediately, and remains cleared. If the power is restored
(no UVREG or UVREF), and if no OVERTEMP fault exists,
then the latched fault remains cleared when the RESET line
returns to high. However, FAULT = 1 may still occur because a
UVBOOT fault condition may still exist.
The VREG capacitor, CREG, must supply the instantaneous current to the gate of the low-side MOSFET. A 10 μF, 25 V capacitor should be adequate. This capacitor can be either electrolytic
Charge Pump. The A3946 is designed to accommodate a
or ceramic (X7R).
wide range of power supply voltages. The charge pump output,
VREG, is regulated to 13 V nominal.
Diagnostics and Protection. The fault output pin,
~FAULT, goes low (i.e., FAULT = 1) when the RESET line is
In all modes, this regulator is current-limited. When VBB < 8 V,
high and any of the following conditions are present:
the charge pump operates as a voltage doubler. When 8 V <
• Undervoltage on VREG (UVREG). Note that the outputs
become active as soon as VREG comes out of undervoltage,
even though the ~FAULT pin is latched until reset.
• Undervoltage on VREF (UVREF). Note that this condition
does NOT latch a fault.
• A junction temperature > 170°C (OVERTEMP). This condition sets a latched fault.
• An undervoltage on the stored charge of the BOOT capacitor
(UVBOOT). This condition does NOT set a latched fault.
An overtemperature event signals a latched fault, but does not
disable any output drivers, regulators, or logic inputs. The user
must turn off the A3946 (e.g., force the RESET line low) to
prevent damage.
The power FETs are protected from inadequate gate drive
voltage by undervoltage detectors. Either of the regulator
undervoltage faults (UVREG or UVREF) disable both output
drivers until both voltages have been restored. The high-side
driver is also disabled during a UVBOOT fault condition.
Under many operating conditions, both the high-side (GH)
and low-side (GL) drivers may be off, allowing the BOOT
capacitor to discharge (or never become charged) and create a
UVBOOT fault condition, which in turn inhibits the high-side
driver and creates a FAULT = 1. This fault is NOT latched. To
remove this fault, momentarily turn on GL to charge the BOOT
capacitor.
Latched faults may be cleared by a low pulse, 1 to 10 μs
wide, on the RESET line. Throughout that pulse (despite a
VBB< 15 V, the charge pump operates as a voltage doubler/
PWM, current-controlled, voltage regulator. When VBB>15 V,
the charge pump operates as a PWM, current-controlled, voltage regulator. Efficiency shifts, from 80% at VBB= 7 V, to 20%
at VBB = 50 V.
CAUTION. Although simple paralleling of VREG supplies
from several A3946s may appear to work correctly, such a
configuration is NOT recommended. There is no assurance that
one of the regulators will not dominate, taking on all of the load
and back-biasing the other regulators. (For example, this could
occur if a particular regulator has an internal reference voltage
that is higher that those of the other regulators, which would
force it to regulate at the highest voltage.)
Sleep Mode/Power Up. In Sleep Mode, all circuits are
disabled in order to draw minimum current from VBB. When
powering up and leaving Sleep Mode (the RESET line is high),
the gate drive outputs stay disabled and a fault remains asserted
until VREF and VREG pass their undervoltage thresholds.
When powering up, before starting the first bootstrap charge
cycle, wait until t = CREG ⁄ 4 (where CREG is in μF, and t is in ns)
to allow the charge pump to stabilize.
When powered-up (not in Sleep Mode), if the RESET line is
low for > 10 μs, the A3946 may start to enter Sleep Mode (VREF
< 4 V). In that case, ~FAULT = 1 as long as the RESET line
remains low.
If the RESET line is open, the A3946 should go into Sleep
Mode. However, to ensure that this occurs, the RESET line
must be grounded.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A3946
Half-Bridge Power MOSFET Controller
Dead Time. The analog input pin DT sets the delay to turn
on the high- or low-side gate outputs. When instructed to
turn off, the gate outputs change after an short internal propagation delay (90 ns typical). The dead time controls the time
between this turn-off and the turn-on of the appropriate gate.
The duration, tDEAD, can be adjusted within the range 350 ns
to 6000 ns using the following formula:
tDEAD = 50 + (RDEAD ⁄ 16.7 )
where tDEAD is in ns, and RDEAD is in Ω, and should be in the
range 5 kΩ < RDEAD < 100 kΩ.
Do not ground the DT pin. If the DT pin is left open, dead
time defaults to 12 μs.
Control Logic. Two different methods of control are
possible with the A3946. When a resistor is connected from
DT to ground, a single-pin PWM scheme is utilized by shorting IN1 with IN2. If a very slow turn-on is required (greater
than 6 μs), the two input pins can be hooked-up individually
to allow the dead times to be as long as needed.
The dead time circuit can be disabled by tying the DT pin
to VREF. This disables the turn-on delay and allows direct
control of each MOSFET gate via two control lines. This is
shown in the Control Logic table, on page 2.
Top-Off Charge Pump. An internal charge pump allows
100% duty cycle operation of the high-side MOSFET. This is
a low-current trickle charge pump, and is only operated after
a high-side has been signaled to turn on. A small amount of
bias current is drawn from the BOOT pin to operate the floating high-side circuit. The top-off charge pump simply provides enough drive to ensure that the gate voltage does not
droop due to this bias supply current. The charge required for
initial turn-on of the high-side gate must be supplied by bootstrap capacitor charge cycles. This is described in the section
Application Information.
VREF. VREF is used for the internal logic circuitry and
is not intended as an external power supply. However,
the VREF pin can source up to 4 mA of current. A 0.1 μF
capacitor is needed for decoupling.
Fault Response Table
Fault Mode
No Fault
BOOT Capacitor Undervoltage
Thermal Shutdown
Sleep
5
3
~FAULT
VREG
VREF
GH1
GL1
1
1
ON
ON
(IL)
(IL)
1
0
ON
ON
0
(IL)
3
1
0
ON
ON
0
0
4
1
0
OFF
ON
0
0
1
0
ON
ON
(IL)
(IL)
0
1
OFF
OFF
High Z
High Z
VREG Undervoltage
VREF Undervoltage
RESET
2
(IL) indicates that the state is determined by the input logic.
2
This fault occurs whenever there is an undervoltage on the BOOT capacitor. This fault is not latched.
3
These faults are latched. Clear by pulsing RESET = 0. Note that outputs become active as soon as VREG comes out of undervoltage, even
though ~FAULT = 0.
4
Unspecified VREF undervoltage threshold < 4 V.
5
During power supply undervoltage conditions, GH and GL are instructed to be 0 (low). However, with VREG < 4 V, the outputs start to become high impedance (High Z). Refer to the section Sleep Mode/Power Up.
1
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A3946
Half-Bridge Power MOSFET Controller
Application Information
Bootstrap Capacitor Selection. CBOOT must be correctly selected to ensure proper operation of the device. If
too large, time is wasted charging the capacitor, with the
result being a limit on the maximum duty cycle and PWM
frequency. If the capacitor is too small, the voltage drop can
be too large at the time the charge is transferred from the
CBOOT to the MOSFET gate.
To keep the voltage drop small:
At power-up and when the drivers have been disabled for
a long time, the bootstrap capacitor can be completely
discharged. In this case, Delta_v can be considered to be the
full high-side drive voltage, 12 V. Otherwise, Delta_v is the
amount of voltage dropped during the charge transfer, which
should be 400 mV or less. The capacitor is charged whenever
the S pin is pulled low, via a GL PWM cycle, and current
flows from VREG through the internal bootstrap diode
circuit to CBOOT.
QBOOT >> QGATE
where a factor in the range of 10 to 20 is reasonable. Using
20 as the factor:
and
QBOOT = CBOOT × VBOOT = QGATE × 20
CBOOT = QGATE × 20 / VBOOT
The voltage drop on the BOOT pin, as the MOSFET is being
turned on, can be approximated by:
Delta_v = QGATE / CBOOT
For example, given a gate charge, QGATE, of 160 nC, and the
typical BOOT pin voltage of 12 V, the value of the Boot
capacitor, CBOOT, can be determined by:
CBOOT = (160 nC × 20) / 12 V ≈ 0.266 μF
Power Dissipation. For high ambient temperature
applications, there may be little margin for on-chip power
consumption. Careful attention should be paid to ensure that
the operating conditions allow the A3946 to remain in a safe
range of junction temperature.
The power consumed by the A3946 can be estimated as:
P_total = Pd_bias + Pd_cpump + Pd_switching_loss
where:
Pd_bias = VBB × IVBB , typically 3 mA,
and
Pd_cpump = (2VBB – VREG) IAVE, for VBB < 15 V, or
Pd_cpump = (VBB – VREG) IAVE, for VBB > 15 V,
Therefore, a 0.22 μF ceramic (X7R) capacitor can be chosen
for the Boot capacitor.
in either case, where
In that case, the voltage drop on the BOOT pin, when the
high-side MOSFET is turned on, is:
and
Delta_v = 160 nC / 0.22 μF = 0.73 V
Bootstrap Charging. It is good practice to ensure that the
high-side bootstrap capacitor is completely charged before a
high-side PWM cycle is requested.
IAVE = QGATE × 2 × fPWM
Pd_switching_loss = QGATE
× VREG × 2 × fPWM Ratio,
where
Ratio = 10 Ω / (RGATE + 10 Ω).
The time required to charge the capacitor can be approximated by:
tCHARGE = CBOOT (Delta_v / 100 mA)
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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A3946
Half-Bridge Power MOSFET Controller
Application Block Diagrams
+VBAT
C1
0.47 μF
C2
10 μF
P
VBB
VREF
CP2
VREF
0.1 uF
ILIM
L
L
VREG
Charge
Pump
+5 Vref
10
k7
CP1
P
P
Top-Off
Charge Pump
BOOT
~FAULT
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
Bootstrap
UVLO
CBOOT
0.47 μF
IRF2807
L
DT
RDEAD
15.8 k7
GH
High Side
Driver
Turn-On
Delay
RGATE
IN1
Control
Logic
S
VREG
Forward
IRF2807
L
IN
P
33 7
470
k7
L
IN
CREG
10 μF
IN2
GL
Low Side
Driver
Brake
RGATE
33 7
PGND
External
+5 V
L
RESET
M
LGND
P
L
L
DC
Motor
P
Diagram A. Dependent drivers. Unidirectional motor control with braking and dead time. TDEAD = 1 μs; QTOTAL = 160 nC.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A3946
Half-Bridge Power MOSFET Controller
+VBAT
P
C1
0.47 μF
C2
10 μF
VBB
VREF
CP2
VREF
CP1
0.1 uF
10
k7
L
L
VREG
Charge
Pump
+5 Vref
P
CREG
P 10 μF
ILIM
P
Top-Off
Charge Pump
BOOT
~FAULT
M
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
Bootstrap
UVLO
CBOOT
IRF2807
L
VREF
DT
GH RGATE
High Side
Driver
Turn-On
Delay
33 7
470
k7
DC Motor #1
IN1
Forward
Control
Logic
Slow
Decay
DC Motor #2
Forward
S
VREG
L
IRF2807
IN2
RGATE
GL
Slow
Decay
External
+5 V
DC Motor #2
0.47 μF
Low Side
Driver
33 7
PGND
L
RESET
LGND
P
L
L
470
k7
M
DC Motor #1
P
Diagram B. Independent drivers. One high-side drive and one low-side drive.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
A3946
Half-Bridge Power MOSFET Controller
+VBAT
C1
0.47 μF
C2
10 μF
P
P
VBB
VREF
CP2
VREF
CP1
0.1 uF
10
k7
ILIM
L
L
VREG
Charge
Pump
+5 Vref
P
P
Top-Off
Charge Pump
DC Motor
#1
Bootstrap
UVLO
DT
High Side
Driver
Turn-On
Delay
RGATE
GH
33 7
470
k7
DC Motor #1
IN1
Forward
Control
Logic
Slow
Decay
S
P
VREG
DC Motor #2
Forward
IRF2807
L
IN2
RGATE
GL
Low Side
Driver
Slow
Decay
33 7
470
k7
PGND
External
+5 V
DC Motor
#2
IRF2807
L
VREF
M
M
BOOT
~FAULT
Protection
VREG Undervoltage
Overtemperature
UVLOBOOT
CREG
10 μF
L
P
RESET
LGND
L
L
P
PAD
Diagram C. Independent drivers. Two low-side drives.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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11
A3946
Half-Bridge Power MOSFET Controller
Pin-out Diagram
LP package
VREG
1
16
VBB
CP2
2
15
VREF
CP1
3
14
DT
PGND
4
13
LGND
GL
5
12
RESET
S
6
11
IN2
GH
7
10
IN1
BOOT
8
9
~FAULT
PAD
Terminal List Table
Name
Number
Description
VREG
1
Gate drive supply.
CP2
2
Charge pump capacitor, positive side. When not using the charge pump, leave this pin open.
CP1
3
Charge pump capacitor, negative side. When not using the charge pump, leave this pin open.
PGND*
4
External ground. Internally connected to the power ground.
GL
5
Low-side gate drive output for external MOSFET driver. External series gate resistor can be used to control
slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output.
S
6
Directly connected to the load terminal. The pin is also connected to the negative side of the bootstrap
capacitor and negative supply connection for the floating high-side drive.
GH
7
High-side gate drive output for N-channel MOSFET driver. External series gate resistor can be used to
control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output.
BOOT
8
High-side connection for bootstrap capacitor, positive supply for the high-side gate drive.
~FAULT
9
Diagnostic output, open drain. Low during a fault condition.
IN1
10
Logic control.
IN2
11
Logic control.
RESET
12
Logic control input. When RESET = 0, the chip is in a very low power sleep mode.
LGND*
13
External ground. Internally connected to the logic ground.
DT
14
Dead Time. Connecting a resistor to GND sets the turn-on delay to prevent shoot-through. Forcing this
input high disables the dead time circuit and changes the logic truth table.
VREF
15
5 V internal reference decoupling terminal.
VBB
16
Supply Input.
PAD
–
Exposed thermal pad. Not connected to any pin, but should be externally connected to ground, to reduce
noise pickup by the pad.
The PGND pin (4) and LGND pin (13) grounds are NOT internally connected, and both must be connected to ground externally.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
A3946
Half-Bridge Power MOSFET Controller
LP Package TSSOP with Exposed Thermal Pad
0.45
5.00 ±0.10
4° ±4
16
+0.05
0.15 –0.06
0.65
16
1.70
B
4.40 ±0.10
3.00
6.40 ±0.20
0.60 ±0.15
A
1
6.10
(1.00)
2
3.00
16X
0.25
SEATING
PLANE
0.10 C
+0.05
0.25 –0.06
3.00
0.65
C
SEATING PLANE
GAUGE PLANE
1 2
3.00
C
PCB Layout Reference View
1.20 MAX
0.15 MAX
For Reference Only
(reference JEDEC MO-153 ABT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
A3946
Half-Bridge Power MOSFET Controller
Copyright ©2003-2013 Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
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