EQCO875SC DATA SHEET (04/08/2016) DOWNLOAD

EQCO875SC.3/EQCO850SC.3
EQCO875SC.3/EQCO850SC.3 Single-Coax Transceiver for
Fast Ethernet
Features
Applications
• Combined Transmitter and Receiver with an
Integrated Equalizer to Form a Full-Duplex
Bidirectional Connection over a Single 75Ω Coax
Cable (EQCO875SC.3) or 50Ω Coax Cable
(EQCO850SC.3)
• Compatible with FX Version of Fast Ethernet
• Low-Power: 205 mW from Single 3.3V Supply
• Integrated Termination Resistors for Low External
Discrete Count
• Fully Supports PoE-Based Power and Data
Signal Distribution Over Coax
• 16-Pin, 0.65 mm Pin Pitch, 4 mm QFN Package
• Pb-Free and RoHS Compliant
This solution is useful and economical for many
markets and applications, including the following:
TABLE 1:
• Camera Networks
- Home Security, Surveillance, Industrial/
Inspection, Medical Cameras
• Home Networking over Coax Infrastructure
- When Cat5 or Cat6 cabling is not available
and existing 75Ω coax is not used for analog
TV signals
• TV, STB, PVR Connections Including Inter-Room
Links
TYPICAL DEVICE PERFORMANCE FOR EQCO875SC.3
EQCO875SC.3 Range Using
Version
EQCO875SC.3
TABLE 2:
RG11
RG6 (Ø 5 mm)
225m
150m
TYPICAL DEVICE PERFORMANCE FOR EQCO850SC.3
Version
EQCO850SC.3
 2009-2016 Microchip Technology Inc.
EQCO850SC.3 Range Using
RG174
RTK
RG58
40m
70m
70m
DS60001314A-page 1
EQCO875SC.3/EQCO850SC.3
Table of Contents
1.0
2.0
3.0
4.0
Device Overview .......................................................................................................................................................................... 3
Application Information ................................................................................................................................................................. 7
Electrical Characteristics .............................................................................................................................................................. 9
Packaging................................................................................................................................................................................... 11
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Most Current Data Sheet
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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DS60001314A-page 2
 2009-2016 Microchip Technology Inc.
EQCO875SC.3/EQCO850SC.3
1.0
DEVICE OVERVIEW
The EQCO875SC.3 single-coax transceiver is
designed to simultaneously transmit and receive
signals on a single 75Ω coax cable for Fast Ethernet. A
sister product, the EQCO850SC.3, can achieve similar
performance when used in 50Ω coaxial systems.
The EQCO875SC.3 is ideally suited for Fast Ethernet
connections over a 75Ω coax cable at a 125 Mbps data
rate. The EQCO875SC.3 connects seamlessly to any FXcompliant physical layer controller (PHY). For correct
operation, the signals are expected to be 4B/5B encoded,
DC balanced and to have a bit rate of 125 Mbps.
This EQCO875SC.3 is useful and economical for
connecting remote PoE-enabled Fast Ethernet IP
cameras and other Ethernet over Coax applications.
Figure 1-1 illustrates a typical Ethernet Coaxial
connection:
FIGURE 1-1:
COAXIAL ETHERNET PMD CONNECTION
Up to 225 meters
IEEE 802.3
FX
Compliant
PHY
EQCO875SC
 2009-2016 Microchip Technology Inc.
75Ω Coax
(including inline
connectors as required)
EQCO875SC
IEEE 802.3
FX
Compliant
PHY
DS60001314A-page 3
EQCO875SC.3/EQCO850SC.3
EQCO875SC.3 PIN DIAGRAM (VIEWED FROM TOP)(1)
FIGURE 1-2:
CCUT
DVCC
OPT0
DGND
16
15
14
13
AVCC
1
12
SDOp
SDIO
2
11
SDOn
REF
3
10
SDIp
AGND
4
9
SDIn
EQCO875SC.3
GND TAB
5
6
7
8
OPT1
CLK
DAT
NC
Note 1: Devices named EQCO850SC.2 can be used for all applications contained in this data sheet. They are the
same in all aspects.
TABLE 1-1:
EQCO875SC.3 PIN DESCRIPTIONS
Pin Number
(TAB)
Pin Name
Signal Type
GND
Power
Description
Connect to ground of power supply.
15
DVCC
Power
Digital VCC. Connect to +3.3V of power supply.
13
DGND
Power
Digital GND. Connect to ground of power supply.
1
AVCC
Power
Analog VCC.
Connect to +3.3V of power supply via ferrite bead (RF choke)
and capacitor to cable outer screen.
4
AGND
Power
Analog GND.
Connect to cable outer screen.
2
SDIO
Bidirectional
Serial Input/Output.
Connect to center conductor of 75Ω coax cable.
3
REF
Bidirectional
Reference. Connect through 75Ω resistor (or impedance
matched to cable) to cable outer screen.
8
NC
Output
10, 9
SDIp/SDIn
Input
Positive/negative differential serial input.
Connect to the Ethernet PHY FX Out pins.
12, 11
SDOp/SDOn
Output
Positive/negative differential serial output.
Connect to the Ethernet PHY FX In pins.
14, 5
OPT0, OPT1
Input
Connect Opt0 to DGND and Opt1 to DVCC to enable Fast
Ethernet mode.
6, 7
CLK, DAT
Input
Used for production test. Connect to DGND.
16
CCUT
Analog
DS60001314A-page 4
Do not connect.
Connect to DVCC.
 2009-2016 Microchip Technology Inc.
EQCO875SC.3/EQCO850SC.3
FIGURE 1-3:
EQCO875SC.3 BLOCK DIAGRAM SHOWING ELECTRICAL CONNECTIONS
EQCO875SC.3
SDIp
SDIn
Input
Pre-Driver
Active Signal
Splitter/Combiner
Transmit
Wake-Up
Detection
Equalizer
Core
SDOp
SDOn
1.1
SDIp/SDIn
SDIp/SDIn together form a differential input pair. The
serial data received on these pins will be transmitted on
SDIO. The Input Pre-Driver automatically corrects for
variations in signal levels and different edge slew rates at
these inputs before they go into the Active Splitter/
Combiner for transmission over the coax.
Both SDIp and SDIn inputs are differentially terminated by
110Ω on-chip. The center of the 110Ω is connected to
DGND with a 10 kΩ resistor for DC biasing. The inputs
also have protection diodes to ground for ESD purposes.
These inputs should always be capacitively coupled to the
FX output of the Ethernet PHY. A Transmit Wake-Up
detection circuit puts both the Input Pre-Driver and the
Active Signal Splitter/Combiner into a low-power mode
when no signal is detected on the SDIp/SDIn signal pair.
1.2
SDIO/REF
SDIO
REF
RX Output
Driver
1.3
SDOp/SDOn
SDOp/SDOn together form a differential pair outputting
the reconstructed far-end transmit signal. The
EQCO850SC-HS uses LVDS drivers with source
matching for a 100Ω transmission line. This LVDS
signal can normally be connected (subject to input
common-mode requirements) directly to the RX signal
pair of a standard LVDS receiver.
1.4
OPT0, OPT1
Connect Opt0 to DGND and Opt1 to DVCC to enable
Fast Ethernet mode.
1.5
CLK, DAT Pins
These pins are normally used to access an internal
register during production test. Connect them to DGND
for normal operation. They should not be left floating.
The signal on the SDIO pin is the sum of the incoming
signal (i.e. the signal transmitted by the EQCO875SC on
the far-end side of the coax) and the outgoing signal (i.e.
the signal created based on SDIp/SDIn). The far-end
signal is extracted by subtraction of the near-end signal,
and it is this voltage that the equalizer analyses and
adaptively equalizes for level and frequency response
based on the knowledge that the originating signal is 4B/
5B encoded before transmission.
The REF signal carries a precise anti-phase current to the
transmit current on SDIO. REF must be connected
directly to AGND at the connector (see Figure 3-2) via a
resistor precisely matched to the impedance of the
coaxial cable used.
 2009-2016 Microchip Technology Inc.
DS60001314A-page 5
EQCO875SC.3/EQCO850SC.3
2.0
CIRCUIT OPERATION
2.3
2.1
Pre-Driver
The EQCO875SC-HS has an embedded high-speed
equalizer in the receive path with unique characteristics:
The pre-driver removes any dependency on Ethernet
PHY for the amplitude and rise time of the outgoing
signal on SDIO.
2.2
Active Signal Splitter/Combiner
The Active Splitter/Combiner controls the amplitude
and rise time of the outgoing coax signal and transmits
it via a precise 75Ω output termination resistor. The
output resistor, when balanced with the coax
characteristic impedance, also forms part of a hybrid
splitter circuit which subtracts the TX output from the
signal on the SDIO output to give yield the far-end TX
signal. The return-loss of the coax termination is a key
factor in the performance of the line hybrid.
FIGURE 2-1:
DS60001314A-page 6
Equalizer Core
• Auto-adaptive
The equalizer controls a multiple-pole analog filter
which compensates for attenuation of the cable, as
illustrated in Figure 2-1. The filter frequency response
needed to restore the signal is automatically determined
by the device using a time-continuous feedback loop
that measures the frequency components in the signal.
Upon the detection of a valid signal, the control loop
converges within a few microseconds.
• Variable gain
EQCO875SCs are used in pairs, with one at each end of
the coax cable. The EQCO875SC can be used with any
Fast Ethernet compliant fiber optic PHY; any differences
in transmit amplitude are removed by the input pre-driver.
The receiver equalizer has variable gain to compensate
for attenuation through the coax cable.
PRINCIPLE OF EQUALIZER OPERATION
 2009-2016 Microchip Technology Inc.
EQCO875SC.3/EQCO850SC.3
3.0
APPLICATION INFORMATION
Figure 3-1 illustrates a typical schematic implementation
for the EQCO875SC.3 in Ethernet mode.
FIGURE 3-1:
EQCO875SC.3 TYPICAL APPLICATION CIRCUIT
GND
VCC
48V_DC
13
DGND
14
OPT 0
15
16
SDOn
REF
SDIp
5
GND
SDIn
VCC
C3 100n
11
C4
100n
10
C1
100n
9
C2
100n
SDOp
SDOn
SDIp
SDIn
NC
AGND
12
8
4
SDIO
DA T
3
U1
EQCO850SC.3/EQCO875SC.3
SDOp
7
50R/75R
2
AVCC
CL K
R1
C5 10n
100V
C6 10n
100V
1
6
C9 10n
DV CC
L1
CCUT
TAB
100V
GND
FB1
17
B L M15HD182SN1D
C10 1u
C7 100n
OPT 1
J1
1812PS-103K L B
C8 10u
GND
To improve isolation from noise on the board power
plane and improve EMC immunity and emissions, it is
recommended to power the transmit side of the
equalizer (AVCC) through a ferrite bead (FB1). C9 is
used to reference AVCC to the ground directly at the
connector J1, while AGND is also connected directly to
the connector.
A 100 nF decoupling capacitor (C7) should be placed
as close as possible between the DVCC pin and the
DGND pin. The REF and SDIO signals are AC-coupled
with identical capacitors, C5 and C6. Termination resistor R1 should match the characteristic impedance of
the system, 50Ω for EQCO850SC.3 and 75Ω for
EQCO875SC.3.
A CoilCraft 1812PS-103KLB inductor (L1) is
recommended for best performance when using power
over coax. L1 and C10 can be removed if power over
coax is not required.
 2009-2016 Microchip Technology Inc.
DS60001314A-page 7
EQCO875SC.3/EQCO850SC.3
3.1
Guidelines for PCB Layout
Because signals are strongly attenuated by long cables,
special attention must be paid on the PCB layout
between the coaxial connector and the EQCO875SC.3.
The EQCO875SC.3 should be placed as close as is
practical to the coaxial connector. The trace between
the coaxial connector and the SDIO pin of the
EQCO875SC.3 must be a 75Ω (50Ω for
EQCO850SC.3) trace referenced to GND. To avoid
noise pickup, other traces carrying digital signals or
fast-switching signals should be placed as far away as
possible from this trace.
The ground layout on the EQCO875SC.3 is crucial to
the EMC and EMI performance of the circuit. The
AGND connection should be connected directly to the
body of the connector as shown. Similarly, AVCC
FIGURE 3-2:
DS60001314A-page 8
should be decoupled directly to the connector body
(see the position of C9). The termination resistor (R1
in Figure 3-1 and Figure 3-2) must have its ground
connection at the connector body. The impedance of
all the traces must be well controlled, including on the
connector itself. To compensate for parasitic
capacitances, the ground and power planes
underneath L1 and part of the coax connector need to
be removed, as indicated by the green areas on
Figure 3-2.
The SDIp/SDIn and SDOp/SDOn differential traces
should be laid out as 100Ω differential traces.
The following diagram shows the layout of the critical
section of the PCB corresponding to the circuit of
Figure 3-1 from the coax connector to the twin
differential pairs:
TYPICAL PCB LAYOUT
 2009-2016 Microchip Technology Inc.
EQCO875SC.3/EQCO850SC.3
4.0
ELECTRICAL CHARACTERISTICS
4.1
Absolute Maximum Ratings
Stresses beyond those listed under this section may
cause permanent damage to the device. These are stress
ratings only and are not tested. Functional operation of
the device at these or any other conditions beyond those
indicated in the operational sections is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
TABLE 4-1:
ABSOLUTE MAXIMUM RATINGS
Parameter
Min.
Typ.
Max.
Units
Storage Temperature
-65
—
+150
°C
Ambient Temperature
-55
—
+125
°C
Supply Voltage to Ground
-0.5
—
+4.0
V
DC Input Voltage
-0.5
—
+4.0
V
DC Voltage to Outputs
-0.5
—
+4.0
V
—
—
90
mA
Output Current into Outputs
TABLE 4-2:
Parameter
Conditions
Power Applied
Outputs Low
ELECTRICAL CHARACTERISTICS
Min.
Typ.
Max.
Unit
Description
VCC
3.2
3.3
3.4
V
IS
47.5
62.5
75.5
mA
Supply current, both transmitting and receiving.
ISR
25
35
43
mA
Supply current when not transmitting.
Input amplitude VSDIp,n.
Power Supply
Supply voltage.
SDIp/SDIn Input (LVDS-like)
Vi
250
—
800
mV
Vturnon
100
140
200
mV
Vcmin
—
0
—
V
Common-mode input voltage (terminated to ground
with protection diodes).
Rinput
85
104
115
Ω
Differential input termination.
Minimal Vi to turn on transmit function.
SDIO Connection to Coax
Zcoax
72 (48)
75 (50)
78 (52)
Ω
Required coax cable characteristic impedance.
RSDIO
65 (46)
75 (51)
86 (55)
Ω
Input impedance between SDIO and AGND.
Rloss
20
—
—
dB
Coax return-loss as seen on SDIO pin. Frequency
range = 10 MHz-62.5 MHz.
VTX
250
300
350
mV
Transmit amplitude.
trise_tx
350
450
550
ps
Rise/fall time 20% to 80% of VTX.
Attmax
—
10
—
dB
Cable attenuation budget @ 62.5 MHz.
VRXmin
—
40
—
mV
Minimum input for fully reconstructed output.
 2009-2016 Microchip Technology Inc.
DS60001314A-page 9
EQCO875SC.3/EQCO850SC.3
TABLE 4-2:
ELECTRICAL CHARACTERISTICS (CONTINUED)
SDOp/SDOn Outputs (LVDS-like)
Vo
250
350
450
mV
Vcmout
1.1
1.2
1.3
V
Common-mode output voltage.
Routput
85
102
115
Ω
Differential termination between SDOp and SDOn.
trise_o
150
240
350
ps
Rise/fall time 20% to 80% of VSDOp,n.
TABLE 4-3:
Output amplitude VSDOp,n.
JITTER PERFORMANCE
Parameter
Min.
Typ.
Max.
Units
Conditions
Jitter peak-to-peak on SDO
—
40%
50%
UI
150m RG6 coax; over full VCC, VTX, and temp
range; 125 Mbps; pattern PRBS7
TABLE 4-4:
TEMPERATURE SPECIFICATIONS
Parameter
Symbol
Min.
Typ.
Max.
Unit
Operating Ambient Temperature
TA
-10
–
70
°C
Operating Junction Temperature
TJ
-10
–
85
°C
JT
–
1.2
–
°C/W
Typical Junction to Ambient
JA
–
59
–
°C/W
Typical Junction to Case
JC
–
10
–
°C/W
Temperature Ranges
Thermal Package Resistances
Typical Junction to Package
DS60001314A-page 10
 2009-2016 Microchip Technology Inc.
EQCO875SC.3/EQCO850SC.3
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
16-Lead Plastic Quad Flat, No Lead Package – 4x4x0.9 mm Body [QFN]
16-Lead QFN (4x4x0.9 mm)
PIN 1
Example
PIN 1
EQCO
YYWWNNN
Legend: XX...X
YY
WW
NNN
*e3
Note:
875SC.3
YYWWNNN
Part number
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (optional)
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
e3
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2009-2016 Microchip Technology Inc.
DS60001314A-page 11
EQCO875SC.3/EQCO850SC.3
16-Lead Plastic Quad Flat, No Lead Package (8E) - 4x4x0.9 mm Body [QFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
NOTE 1
1
2
E
(DATUM B)
(DATUM A)
2X
0.20 C
2X
TOP VIEW
0.20 C
0.10 C
C
A1
A
SEATING
PLANE
16X
SIDE VIEW
(A3)
0.10
0.08 C
C A B
D2
(16X K)
0.10
C A B
E2
e
2
2
1
16X L
N
e
BOTTOM VIEW
16X b
0.10
0.05
C A B
C
Microchip Technology Drawing C04-259B Sheet 1 of 2
DS60001314A-page 12
 2009-2016 Microchip Technology Inc.
EQCO875SC.3/EQCO850SC.3
16-Lead Plastic Quad Flat, No Lead Package (8E) - 4x4x0.9 mm Body [QFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
A
Overall Height
Standoff
A1
A3
Terminal Thickness
Overall Width
E
E2
Exposed Pad Width
D
Overall Length
D2
Exposed Pad Length
b
Terminal Width
Terminal Length
L
K
Terminal-to-Exposed-Pad
MIN
0.80
0.00
1.95
1.95
0.25
0.45
MILLIMETERS
NOM
16
0.65 BSC
0.87
0.02
0.20 REF
4.00 BSC
2.05
4.00 BSC
2.05
0.30
0.55
0.425 REF
MAX
0.95
0.05
2.15
2.15
0.35
0.65
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-259B Sheet 2 of 2
 2009-2016 Microchip Technology Inc.
DS60001314A-page 13
EQCO875SC.3/EQCO850SC.3
16-Lead Plastic Quad Flat, No Lead Package (8E) - 4x4x0.9 mm Body [QFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
16
G1
1
X1
2
C2 Y2
Y1
E
SILK SCREEN
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X16)
X1
Contact Pad Length (X16)
Y1
Contact Pad to Center Pad (X16)
G1
MIN
MILLIMETERS
NOM
0.65 BSC
MAX
2.15
2.15
3.625
3.625
0.30
0.725
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2259A
DS60001314A-page 14
 2009-2016 Microchip Technology Inc.
EQCO875SC.3/EQCO850SC.3
APPENDIX A:
REVISION HISTORY
Revision A (April 2016)
This is the initial release of the document in the Microchip
format. This replaces EqcoLogic document version 2.0.
TABLE A-1:
REVISION HISTORY
Version
Date
2v0
1/28/14
Merged 50Ω and 75Ω systems into one data sheet.
1v2
10/25/11
Fixed lower temperature limit.
1v1
6/8/11
Fixed bitrate, temperature range, SDIP/SDIN descriptions.
0v4
2/28/11
Internal quality review. Removed Preliminary status.
0v3
10/26/09
Technical review. Revised Section 5.1
0v2
10/15/09
Internal review.
0v1
10/15/09
Modified from EQCO875SC IEEE1394 data sheet.
 2009-2016 Microchip Technology Inc.
Comments
DS60001314A-page 15
EQCO875SC.3/EQCO850SC.3
NOTES:
DS60001314A-page 16
 2009-2016 Microchip Technology Inc.
EQCO875SC.3/EQCO850SC.3
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 2009-2016 Microchip Technology Inc.
DS60001314A-page 17
EQCO875SC.3/EQCO850SC.3
PRODUCT IDENTIFICATION SYSTEM
To order parts, including industrial, or obtain information, for e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
XXXX
Device
Package
Device:
Examples:
a)
EQCO875SC.3
EQCO850SC.3
Package:
TRAY
b)
EQCO875SC.3-TRAY = 75Ω Coax,
Industrial temperature,
16-Lead QFN package,
Tray packaging
EQCO850SC.3
= 50Ω Coax,
Industrial temperature,
16-Lead QFN package,
Tube packaging
= Tray
“blank” = Tube
DS60001314A-page 18
 2009-2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2009-2016 Microchip Technology Inc.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0468-2
DS60001314A-page 19
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07/14/15
DS60001314A-page 20
 2009-2016 Microchip Technology Inc.
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