FUJITSU SEMICONDUCTOR DATA SHEET DS07-13706-4E 16-bit Proprietary Microcontroller CMOS F2MC-16LX MB90550A/550B Series MB90552A/552B/553A/553B/T552A/T553A MB90F553A/P553A ■ DESCRIPTION The MB90550A/550B series is a line of general-purpose, high-performance, 16-bit microcontrollers designed for applications which require high-speed real-time processing, such as industrial machines, OA equipment, and process control systems. While inheriting the AT architecture of the F2MC*-8 family, the instruction set for the MB90550A/550B series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90550A/550B has an on-chip 32-bit accumulator which enables processing of long-word data. MB90552B and MB90553B are radiation noise decreased type. There are no change in the functional specification. *: F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED. ■ FEATURES • Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, × four times the PLL clock) • Maximum memory space: 16 Mbytes (Continued) ■ PACKAGES 100-pin plastic QFP 100-pin plastic LQFP (FPT-100P-M06) (FPT-100P-M05) MB90550A/550B Series (Continued) • Instruction set optimized for controller applications Supported data types: Bit, byte, word and long word Typical addressing mode: 23 types Enhanced precision calculation realized by 32-bit accumulator Enhanced signed multiplication/division instruction and RETI instruction functions • Instruction set designed for high level language (C) and multi-task operations Adoption of system stack pointer Symmetrical instruction set and barrel shift instructions • Integrated address match detection function (for two address pointers) • Faster execution speed: 4-byte queue • Powerful interrupt functions (Eight priority levels programmable) External interrupt inputs: 8 channels • Data transfer functions (Intelligent I/O service): Up to 16 channels DTP request inputs: 8 channels • Embedded ROM size (EPROM, Flash: 128 Kbytes) Mask ROM: 64 Kbytes/128 Kbytes • Embedded RAM size (EPROM, Flash: 4 Kbytes) Mask ROM: 2 Kbytes/4 Kbytes • General-purpose ports: Up to 83 channels (Input pull-up resistor settable for: 16 channels; Open drain settable for: 8 channels; I/O open drains: 6 channels) • A/D converter (RC successive approximation type): 8 channels (Resolution: 8 or 10 bits selectable; Conversion time of 26.3 µs minimum) • UART: 1 channel • Extended I/O serial interface: 2 channels • I2C interface: 2 channels (Two channels, including one switchable between terminal input and output) • 16-bit reload timer: 2 channels • 8/16-bit PPG timer: 3 channels (8 bits × 2 channels; 16 bits x 1 channel: Mode switching function provided) • 16-bit I/O timer (Input capture × 4 channels, output compare × 4 channels, free run timer ×1 channel) • Clock monitor function integrated (Delivering the oscillation clock divided by 21 to 28) • Timebase timer/watchdog timer: 18 bits • Low power consumption modes (sleep, stop, hardware standby, and CPU intermittent operation modes) • Package: QFP-100, LQFP-100 • CMOS technology 2 MB90550A/550B Series ■ PRODUCT LINEUP Part number Item Classification MB90552A MB90553A MB90F553A MB90P553A MB90T552A MB90T553A MB90V550A MB90552B MB90553B Mask ROM products Flash ROM products OTP External ROM products Evaluation product None None Mass Product ROM size 64 Kbytes 128 Kbytes RAM size 2 Kbytes 4 Kbytes CPU functions 2 Kbytes 4 Kbytes 6 Kbytes The number of instructions: 340 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits Minimum execution time: 62.5 ns (at machine clock of 16 MHz) Interrupt processing time: 1.5 µs (at machine clock of 16 MHz, minimum value) Ports General-purpose I/O ports (CMOS output): 53 General-purpose I/O ports (with pull-up resistor): 16 General-purpose I/O ports (N-channel open-drain output): 6 General-purpose I/O ports (N-channel open-drain function selectable): 8 Total: 83 UART (SCI) Clock synchronized transmission (62.5 Kbps to 2 Mbps) Clock asynchronized transmission (62500 bps to 9615 bps) Transmission can be performed by bi-directional serial transmission or by master/slave connection. 8/10-bit A/D converter Conversion precision: 8/10-bit can be selectively used. Number of inputs: 8 One-shot conversion mode (converts selected channel only once) Scan conversion mode (converts two or more successive channels and can program up to 8 channels.) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) 8/16-bit PPG timer 16-bit free run timer 16-bit Output comI/O pare (OCU) timer Input capture (ICU) Number of channels: 3 (8-bit × 6 channels) PPG operation of 8-bit or 16-bit A pulse wave of given intervals and given duty ratios can be output. Pulse interval: 62.5 ns to 1 ms (at oscillation of 4 MHz, machine clock of 16 MHz) Number of channels: 1 Overflow interrupts Number of channels: 4 Pin input factor: A match signal of compare register Number of channels: 4 Rewriting a register value upon a pin input (rising, falling or both edges) (Continued) 3 MB90550A/550B Series (Continued) Part number Item MB90552A MB90553A MB90F553A MB90P553A MB90T552A MB90552B MB90553B MB90T553A MB90V550A Number of inputs: 8 Started by a rising edge, a falling edge, an “H” level input, or an “L” level input. External interrupt circuit or extended intelligent I/O service (EI2OS) can be used. DTP/external interrupt circuit Extended I/O serial interface Clock synchronized transmission (3125 bps to 1 Mbps) LSB first/MSB first I2C interface Serial I/O port for supporting Inter IC BUS Timebase timer 18-bit counter Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (at oscillation of 4 MHz) Watchdog timer Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Process CMOS Power supply voltage for operation* 4.5 V to 5.5 V *:Varies with conditions such as the operating frequency. (See section “■ ELECTRICAL CHARACTERISTICS”) Assurance for the MB90V550A is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an operating temperature of 0°C to +25°C, and an operating frequency of 1 MHz to 16 MHz. ■ PACKAGE AND CORRESPONDING PRODUCTS Package MB90552A MB90552B MB90553A MB90553B MB90F553A FPT-100P-M05 MB90P553A × FPT-100P-M06 : Available ×: Not available Note:For more information about each package, see section “■ PACKAGE DIMENSIONS” ■ DIFFERENCES AMONG PRODUCTS Memory Size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. • The MB90V550A does not have an internal ROM. However, operations equivalent to those performed by a chip with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by setting the development tool. • In the MB90V550A, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH are mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.) • In the MB90F553A/553A/553B/552A/552B, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank FF only. 4 MB90550A/550B Series ■ PIN ASSIGNMENTS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS (Top View) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PA4/CKOT PA3 PA2 RST PA1/OUT3 PA0/OUT2 P97/PPG5 P96/PPG4 P95/PPG3 P94/PPG2 P93/PPG1 P92/PPG0 P91/OUT1 P90/OUT0 P87/IN3 P86/IN2 P85/IN1 P84/IN0 P83/TOT1 P82/TOT0 P81/TIN1 P80/TIN0 P77/IRQ7 P76/IRQ6 P75/IRQ5 P74/IRQ4 P73/IRQ3 P72/IRQ2 HST MD2 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P53/SCL1 P54/SDA2 P55/SCL2 AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P70/IRQ0 P71/IRQ1 MD0 MD1 P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SCK P41/SOT P42/SIN P43/SCK1 P44/SOT1 VCC P45/SIN1 P46/ADTG P47/SCK0 C P50/SDA0/SOT0 P51/SCL0/SIN0 P52/SDA1 (FPT-100P-M06) (Continued) 5 MB90550A/550B Series (Continued) 100 P21/A17 99 P20/A16 98 P17/AD15 97 P16/AD14 96 P15/AD13 95 P14/AD12 94 P13/AD11 93 P12/AD10 92 P11/AD09 91 P10/AD08 90 P07/AD07 89 P06/AD06 88 P05/AD05 87 P04/AD04 86 P03/AD03 85 P02/AD02 84 P01/AD01 83 P00/AD00 82 VCC 81 X1 80 X0 79 VSS 78 PA4/CKOT 77 PA3 76 PA2 (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P50/SDA0/SOT0 P51/SCL0/SIN0 P52/SDA1 P53/SCL1 P54/SDA2 P55/SCL2 AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P70/IRQ0 P71/IRQ1 MD0 MD1 MD2 HST 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SCK P41/SOT P42/SIN P43/SCK1 P44/SOT1 VCC P45/SIN1 P46/ADTG P47/SCK0 C (FPT-100P-M05) 6 RST PA1/OUT3 PA0/OUT2 P97/PPG5 P96/PPG4 P95/PPG3 P94/PPG2 P93/PPG1 P92/PPG0 P91/OUT1 P90/OUT0 P87/IN3 P86/IN2 P85/IN1 P84/IN0 P83/TOT1 P82/TOT0 P81/TIN1 P80/TIN0 P77/IRQ7 P76/IRQ6 P75/IRQ5 P74/IRQ4 P73/IRQ3 P72/IRQ2 MB90550A/550B Series ■ PIN DESCRIPTION Pin no. Pin name Circuit type 80 X0 A Oscillation pin 83 81 X1 A Oscillation pin 77 75 RST B Reset input pin 52 50 HST C Hardware standby input pin QFP LQFP 82 P00 to P07 85 to 92 83 to 90 93 to 100 D (CMOS) Serve as lower data I/O/lower address output (AD00 to AD07) pins in the external bus mode. P10 to P17 General-purpose I/O ports. A pull-up resistor can be added (RD17 to RD10 = 1) by using the pull-up resistor setting register (RDR1). D17 to D10 = 1: Disabled when the port is set for output. 91 to 98 D (CMOS) Serve as upper data I/O/middle address output (AD08 to AD15) pins in the 16-bit bus-width, external bus mode. P20 to P27 99,100, 1 to 6 E (CMOS) A16 to A23 P30 9 7 ALE P31 10 8 RD P32 12 10 WRL P33 13 General-purpose I/O ports. A pull-up resistor can be added (RD07 to RD00 = 1) by using the pull-up resistor setting register (RDR0). D07 to D00 = 1: Disabled when the port is set for output. AD00 to AD07 AD08 to AD15 1 to 8 Function 11 WRH E (CMOS) E (CMOS) E (CMOS) E (CMOS) General-purpose I/O ports. This function is enabled either in single-chip mode or with the external address output control register set to “Port”. External address bus A16 to A23 output pins. This function is enabled in an external-bus enabled mode with the external address output register set to “Address”. General-purpose I/O port. This function is enabled in single-chip mode. Address latch enable output pin. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. Read strobe output pin for the data bus. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. Write strobe output pin for the lower eight bits of the data bus. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. Write strobe output pin for the upper eight bits of the data bus. This function is enabled in an external-bus enabled mode. (Continued) 7 MB90550A/550B Series Pin no. QFP LQFP Pin name P34 14 12 HRQ P35 15 13 HAK P36 16 14 RDY P37 17 15 CLK P40 18 19 20 21 16 Circuit type E (CMOS) E (CMOS) E (CMOS) E (CMOS) F (CMOS/H) Function General-purpose I/O port. This function is enabled in single-chip mode Hold request input pin. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. Hold acknowledge output pin. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. Ready signal input pin. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. CLK output pin. This function is enabled in an external-bus enabled mode. General-purpose I/O port. Serves as an open-drain output port (OD40 = 1) depending on the setting of the open-drain control setting register (ODR4). (D40 = 0: Disabled when the port is set for input.) SCK UART serial clock I/O pin. This function is enabled with the UART clock output enabled. P41 General-purpose I/O port. Serves as an open-drain output port (OD41 = 1) depending on the setting of the open-drain control setting register (ODR4). (D41 = 0: Disabled when the port is set for input.) 17 F (CMOS/H) SOT UART serial data output pin. This function is enabled with the UART serial data output enabled. P42 General-purpose I/O port. Serves as an open-drain output port (OD42 = 1) depending on the setting of the open-drain control setting register (ODR4). (D42 = 0: Disabled when the port is set for input.) F (CMOS/H) 18 SIN UART serial data input pin. Since this input is used as required while the UART is operating for input, the output by any other function must be off unless used intentionally. P43 General-purpose I/O port. Serves as an open-drain output port (OD43 = 1) depending on the setting of the open-drain control setting register (ODR4). (D43 = 0: Disabled when the port is set for input.) 19 SCK1 F (CMOS/H) Extended I/O serial clock I/O pin. This function is enabled with the extended I/O serial clock output enabled. (Continued) 8 MB90550A/550B Series Pin no. QFP LQFP Pin name Circuit type P44 22 24 25 F (CMOS/H) 20 Extended I/O serial data output pin. This function is enabled with the extended I/O serial data output enabled. P45 General-purpose I/O port. Serves as an open-drain output port (OD45 = 1) depending on the setting of the open-drain control setting register (ODR4). (D45 = 0: Disabled when the port is set for input.) F (CMOS/H) 22 SIN1 Extended I/O serial data input pin. Since this input is used as required while the extended I/O serial interface is operating for input, the output by any other function must be off unless used intentionally. P46 General-purpose I/O port. Serves as an open-drain output port (OD46 = 1) depending on the setting of the open-drain control setting register (ODR4). (D46 = 0: Disabled when the port is set for input.) F (CMOS/H) 23 P47 24 F (CMOS/H) 25 C — P50 SDA0 28 26 SOT0 A/D converter external trigger input pin. Since this input is used as required while the A/D converter is operating for input, the output by any other function must be off unless used intentionally. General-purpose I/O port. Serves as an open-drain output port (OD47 = 1) depending on the setting of the open-drain control setting register (ODR4). D47 = 0: Disabled when the port is set for input. Extended I/O serial clock I/O pin. This function is enabled with the extended I/O serial clock output enabled. SCK0 27 General-purpose I/O port. Serves as an open-drain output port (OD44 = 1) depending on the setting of the open-drain control setting register (ODR4). (D44 = 0: Disabled when the port is set for input.) SOT1 ADTG 26 Function Capacitance pin for regulating the power supply. Connect an external ceramic capacitor of about 0.1 µF. N-channel open-drain I/O port. G (NchOD/H) I2C interface data I/O pin. This function is enabled with the I2C interface enabled for operation. While the I2C interface is operating, place the port output in the Hi-Z state (PDR = 1). Extended I/O serial data output pin. This function is enabled with the extended I/O serial data output enabled. (Continued) 9 MB90550A/550B Series Pin no. QFP LQFP Pin name Circuit type P51 N-channel open-drain I/O port. SCL0 29 G (NchOD/H) 27 P52,P54 28,30 SDA1,SDA2 N-channel open-drain I/O ports. G (NchOD/H) P53,P55 31,33 29,31 38 to 41, 36 to 39, 43 to 46 41 to 44 SCL1,SCL2 P60 to P67 AN0 to AN7 G (NchOD/H) H (CMOS/H) 57,58 TIN0,TIN1 P82,P83 61,62 59,60 TOT0,TOT1 I (CMOS/H) 67,68 65,66 IN0 to IN3 P90,P91 OUT0,OUT1 General-purpose I/O ports. A/D converter analog input pin. This function is enabled with the analog input enabled. External interrupt request input pins. Since this input is used as required while external interrupts remain enabled, the output by any other function must be off unless used intentionally. General-purpose I/O ports. J (CMOS/H) J (CMOS/H) P84 to P87 63 to 66 61 to 64 I2C interface clock I/O pins. This function is enabled with the I2C interface enabled for operation. While the I2C interface is operating, place the port output in the Hi-Z state (PDR = 1). General-purpose I/O ports. P80,P81 59,60 I2C interface data I/O pins. This function is enabled with the I2C interface enabled for operation. While the I2C interface is operating, place the port output in the Hi-Z state (PDR = 1). N-channel open-drain I/O ports. P70 to P77 47,48, 45,46, 53 to 58 51 to 56 IRQ0 to IRQ7 I2C interface clock I/O pin. This function is enabled with the I2C interface enabled for operation. While the I2C interface is operating, place the port output in the Hi-Z state (PDR = 1). Extended I/O serial data input pin. Since this input is used as required while the extended I/O serial interface is operating for input, the output by any other function must be off unless used intentionally. SIN0 30,32 Function Reload timer event input pins. Since this input is used as required while the reload timer is operating for input, the output by any other function must be off unless used intentionally. General-purpose I/O ports. Reload timer output pins.This function is enabled with reroad timer output enabled. General-purpose I/O ports. J (CMOS/H) Input capture trigger input pins. Since this input is used as required while the input capture unit is operating for input, the output by any other function must be off unless used intentionally. J (CMOS/H) General-purpose I/O ports. Output compare event output pins. (Continued) 10 MB90550A/550B Series (Continued) Pin no. QFP LQFP Pin name P92 to P97 69 to 74 67 to 72 75,76 73,74 78,79 76,77 80 78 34 PPG0 to PPG5 PA0,PA1 OUT2,OUT3 PA2,PA3 PA4 Circuit type J (CMOS/H) J (CMOS/H) J (CMOS/H) Function General-purpose I/O ports. PPG output pins. This function is enabled with the PPG output enabled. General-purpose I/O ports. Output compare event output pins. General-purpose I/O ports. General-purpose I/O port. CKOT J (CMOS/H) 32 AVCC A/D converter power-supply pin. 35 33 AVRH A/D converter external reference voltage source pin. 36 34 AVRL A/D converter external reference voltage source pin. 37 35 AVSS A/D converter power-supply pin. 49,50 47,48 MD0,MD1 C Operation mode setting input pins. Connect these pins directly to Vcc or Vss. K Operation mode setting input pin. Connect this pin directly to Vcc or Vss. (MB90552A/552B/553A/ 553B/V550A) C Operation mode setting input pin. Connect this pin directly to Vcc or Vss. (MB90P553A/F553A) 51 49 MD2 Serves as the CKOT output while the CKOT is operating. 23,84 21,82 VCC Power (5 V) input pins. 11,42, 81 9,40, 79 VSS Power (0 V) input pins. 11 MB90550A/550B Series ■ I/O CIRCUIT TYPE Type Circuit Remarks Clock input • 3 MHz to 32 MHz • Oscillator recovery resistor approx. 1MΩ X1 A X0 HARD,SOFT STANDBY CONTROL • CMOS level hysteresis input • Pull-up resistor provided Resistor: About 50 kΩ B • CMOS level hysteresis input C Pull-up resistor control Digital output • • • • CMOS level output CMOS level input Standby control provided Input pull-up resistor control provided Resistor: About 50 kΩ Digital output D Digital input HARD,SOFT STANDBY CONTROL (Continued) 12 MB90550A/550B Series Type Circuit Remarks Digital output • CMOS level output • CMOS level input • Standby control provided Digital output E Digital input HARD,SOFT STANDBY CONTROL Open- drain control signal • CMOS level output • CMOS level hysteresis input • Open-drain control provided Digital input F Digital input HARD,SOFT STANDBY CONTROL Digital output G Digital input HARD,SOFT STANDBY CONTROL Digital output • N-channel open-drain output • CMOS level hysteresis input • Standby control provided Note: Unlike normal CMOS I/O pins, this pin is not provided with any P-channel transistor. Therefore the pin does not allow a current to flow to the Vcc side even when applied with a voltage from an external device with the IC’s power supply left off. • • • • CMOS level output CMOS level hysteresis input Standby control provided Analog input Digital output H Analog input Digital input HARD,SOFT STANDBY CONTROL A/D DISABLE (Continued) 13 MB90550A/550B Series (Continued) Type Circuit Remarks Digital output • CMOS level output • CMOS level hysteresis input • Standby control provided Digital output I Digital input HARD STANDBY CONTROL Digital output • CMOS level output • CMOS level hysteresis input • Standby control provided Digital output J Digital input HARD,SOFT STANDBY CONTROL • CMOS level hysteresis input • Pull-up resistor provided Resistor: About 50 kΩ K 14 MB90550A/550B Series ■ HANDLING DEVICES 1. Preventing Latchup CMOS ICs may cause latchup in the following situations: • When a voltage higher than Vcc or lower than Vss is applied to input or output pins. • When a voltage exceeding the rating is applied between Vcc and Vss. • When AVcc power is supplied prior to the Vcc voltage. If latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let it occur. For the same reason, also be careful not to let the analog power-supply voltage exceed the digital power-supply voltage. 2. Handling unused input pins Leaving unused input pins open may cause a malfunction or latch-up which leads to fatal damage to the device. Therefore they must be pulled up or pulled down through at least 2 kΩ resistance. Also, unused input/output pins should be left open in output state or handled in the same way as unused input pins. 3. Notes on Using External Clock In using the external clock, drive X0 pin only and leave X1 pin unconnected. • Using external clock MB90550A/550B series X0 Open X1 4. Power Supply Pins (VCC/VSS) In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, the pins should be connected to external power and ground lines to lower the electro-magnetic emission level and abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines. It is recommended that a bypass capacitor of around 0.1 µF be placed between the VCC and VSS pins near the device. • Using power supply pins VCC VSS VCC VSS VSS VCC MB90550A/550B series VCC VSS VSS VCC 15 MB90550A/550B Series 5. Crystal Oscillator Circuit Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure that lines of oscillation circuit not cross the lines of other circuits. A printed circuit board artwork surrounding the X0 and X1 pins with grand area for stabilizing the operation is highly recommended. 6. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). 7. Connection of Unused Pins of A/D Converter Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS. 8. N.C. Pin The N.C. (internally connected) pin must be opened for use. 9. Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 µs or more. 10. Indeterminate outputs from ports 0 and 1 The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on. (MB90552A, MB90552B, MB90553A, MB90553B, MB90F553A, MB90V550A) The series without built-in step-down circuit has no oscillation setting time of step-down circuit, so outputs should not become indeterminate. (MB90P553A) Timing chart of indeterminate outputs from ports 0 and 1 Oscillation setting time *2 Step-down circuit setting time *1 VCC (power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operating clock A) signal KB (internal operating clock B) signal PORT (port output) signal Period of indeterminate *1: Step-down circuit setting time 217/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms) *2: Oscillation setting time 16 218/oscillation clock frequency (oscillation clock frequency of 16 MHz: 16.38 ms) MB90550A/550B Series 11. Initialization In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers turning on the power again. 12. Return from standby state If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal state. 13. Precautions for Use of ’DIV A, Ri,’ and ’DIVW A, Ri’ Instructions The signed multiplication-division instructions ’DIV A, Ri,’ and ’DIVW A, RWi’ should be used when the corresponding bank registers (DTB, ADB, USB, SSB) are set to value ’00h.’ If the corresponding bank registers (DTB, ADB, USB, SSB) are set to a value other than ’00h,’ the remainder obtained after the execution of the instruction will not be placed in the instruction operand register. 14. Using of REALOS The use of EI2OS is not possible the REALOS real time operating system. 15. Caution on Operations during PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. 17 MB90550A/550B Series ■ BLOCK DIAGRAM X0, X1 RST 4 CPU Clock control circuit* Core of F2MC-16LX family HST Interrupt controller RAM Port A ROM P00 ~ P07/ AD00 ~AD07 Port 0 P10 ~ P17/ AD08 ~ AD15 Port 1 P20 ~ P27/ A16 ~ A23 Port 2 P30/ALE Port 3 F F M C 16 L X B U S P31/RD Clock monitor function CKOT/PA4 PA2, PA3 OUT2, OUT3/ PA0, PA1 Port 9 PPG5/P97 PPG4/P96 8/16 PPG × 3c h P32/WRL PPG3/P95 PPG2/P94 P33/WRH PPG1/P93 P34/HRQ I/O timer P35/HAK P36/RDY 16-bit output compare unit x 4 channels P37/CLK 16-bit input capture unit x 4 channels 16-bit free-run timer PPG0/P92 OUT0, OUT1/ P90, P91 IN0 ~ IN3/ P84 ~ P87 Port 4 Communication prescaler 16-bit reload timer x 2 channels TOT0, TOT1/ P82, P83 TIN0, TIN1/ P80, P81 P40/SCK P41/SOT UART Port 8 P42/SIN P43/SCK1 P44/SOT1 Port 7 Extended I/O serial interface 1 External interrupt P45/SIN1 IRQ0 ~ IRQ7/ P70 ~ P77 P46/ADTG AVCC P47/SCK0 P50/SDA0/SOT0 Extended I/O serial interface 0 A/D converter (8/10 bits) I2C interface 0 P53/SCL1 P54/SDA2 Port 6 Note: Specifications of evaluation model I2C interface 1 P55/SCL2 Port 5 18 AVSS AN0 ~ AN7/ P60 ~ P67 P51/SCL0/SIN0 P52/SDA1 AVRH, AVRL (MB90V550A) Contains no internal ROM. Contains 6 KB of internal RAM. Contains the same internal resources as the other products in the MB90550A/ 550B series. MB90550A/550B Series *: The clock control circuit contains a watchdog timer, time-base timer, and a low power consumption control circuit. Note : P00 to P07 (8 pins): Input pull-up resistor setting register provided P10 to P17 (8 pins): Input pull-up resistor setting register provided P40 to P47 (8 pins): Open-drain control setting register provided P50 to P55 (6 pins): N-channel open drain Ports 0, 1, 2, 3, 4, 6, 7, 8, 9, and A are CMOS level input/output ports. 19 MB90550A/550B Series ■ MEMORY MAP The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 are assigned to the same address, enabling reference of the table on the ROM without stating “far”. For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are accessed. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 004000H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH. Internal ROM Single chip mode A mirror function is supported external bus mode A mirror function is supported External ROM external bus mode FFFFFFH ROM area ROM area ROM area (image of bank FF) ROM area (image of bank FF) Address#1 FF0000H 010000H Address#2 : Internal access memory 004000H 002000H : External access memory Address#3 RAM 000100H 0000C0H 0000D0H 20 Registor Peripheral RAM Registor Peripheral RAM Registor : Inhibited area Peripheral Parts No. Address#1 Address#2 Address#3 MB90552A/552B FF0000H 004000H 000900H MB90553A/553B FE0000H 004000H 001100H MB90F553A FE0000H 004000H 001100H MB90P553A FE0000H 004000H 001100H MB90V550A (FE0000H) 004000H 001900H MB90550A/550B Series ■ F2MC-16LX CPU PROGRAMMING MODEL • Dedicated registers AH : Accumulator (A) Dual 16-bit register used for storing results of calculation, etc. The two 16-bit registers can be combined and used as a 32-bit register. AL USP : User stack pointer (USP) The 16-bit pointer indicating a user stack address. SSP : System stack pointer (SSP) The 16-bit pointer indicating the status of the system stack address. PS : Processor status (PS) The 16-bit register indicating the system status. PC : Program counter (PC) The 16-bit register indicating storing location of the current instruction code. DPR : Direct page register (DPR) The 8-bit register indicating bits 8 through 15 of the operand address in the short direct addressing mode. PCB : Program bank register (PCB) The 8-bit register indicating the program space. DTB : Data bank register (DTB) The 8-bit register indicating the data space. USB : User stack bank register (USB) The 8-bit register indicating the user stack space. SSB : System stack bank register (SSB) The 8-bit register indicating the system stack space. ADB : Additional data bank register (ADB) The 8-bit register indicating the additional data space. 8 bit 16 bit 32 bit 21 MB90550A/550B Series ■ I/O MAP Address Register name Abbreviated register name Read/write Resource name Initial value 00H Port 0 data register PDR0 R/W Port 0 XXXXXXXX 01H Port 1 data register PDR1 R/W Port 1 XXXXXXXX 02H Port 2 data register PDR2 R/W Port 2 XXXXXXXX 03H Port 3 data register PDR3 R/W Port 3 XXXXXXXX 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXX 05H Port 5 data register PDR5 R/W Port 5 __111111 06H Port 6 data register PDR6 R/W Port 6 XXXXXXXX 07H Port 7 data register PDR7 R/W Port 7 XXXXXXXX 08H Port 8 data register PDR8 R/W Port 8 XXXXXXXX 09H Port 9 data register PDR9 R/W Port 9 XXXXXXXX 0AH Port A data register PDRA R/W Port A _ _ _XXXXX 0BH to 0FH (Disabled) 10H Port 0 direction register DDR0 R/W Port 0 00000000 11H Port 1 direction register DDR1 R/W Port 1 00000000 12H Port 2 direction register DDR2 R/W Port 2 00000000 13H Port 3 direction register DDR3 R/W Port 3 00000000 14H Port 4 direction register DDR4 R/W Port 4 00000000 (Disabled) 15H 16H Port 6 direction register DDR6 R/W Port 6 00000000 17H Port 7 direction register DDR7 R/W Port 7 00000000 18H Port 8 direction register DDR8 R/W Port 8 00000000 19H Port 9 direction register DDR9 R/W Port 9 00000000 1AH Port A direction register DDRA R/W Port A ___00000 1BH Port 4 output pin register ODR4 R/W Port 4 00000000 1CH Port 0 resistor setting register RDR0 R/W Port 0 00000000 1DH Port 1 resistor setting register RDR1 R/W Port 1 00000000 Port 6, A/D converter 11111111 (Disabled) 1EH 1FH Analog input enable register ADER R/W 20H Serial mode register SMR R/W 00000000 21H Serial control register SCR R/W 0 0 0 0 0 10 0 22H Serial input data register / serial output data register SIDR/SODR R/W 23H Serial status register SSR R/W UART XXXXXXXX 00001_00 (Continued) 22 MB90550A/550B Series Address Register name Abbreviated register name Read/write 24H Serial mode control status register 0 25H Serial mode control status register 0 26H Serial data register 0 SDR0 R/W 27H Clock frequency-divider control register CDCR R/W 28H Serial mode control status register 1 29H Serial mode control status register 1 2AH Serial data register 1 R/W SMCS0 R/W! SMCS1 R/W! SDR1 Initial value ____0000 Extended I/O serial interface 0 00000010 XXXXXXXX Communication prescaler R/W 0___1111 ____0000 Extended I/O serial interface 1 R/W 00000010 XXXXXXXX (Disabled) 2BH 2CH Resource name 2 IBSR0 R 00000000 2 00000000 I C bus status register 0 2DH I C bus control register 0 IBCR0 R/W 2EH I2C bus clock select register 0 ICCR0 R/W 2FH I2C bus address register 0 IADR0 R/W _ XXXXXXX IDAR0 R/W XXXXXXXX 30H 2 I C bus data register 0 I2C interface 0 _ _ 0XXXXX (Disabled) 31H 32H I2C bus status register 1 IBSR1 R 00000000 33H I2C bus control register 1 IBCR1 R/W 00000000 34H I C bus clock select register 1 ICCR1 R/W 2 2 I2C interface 1 _ _ 0XXXXX 35H I C bus address register 1 IADR1 R/W 36H I2C bus data register 1 IDAR1 R/W XXXXXXXX 37H I2C bus port select register ISEL R/W _______0 38H Interrupt/DTP enable register ENIR R/W 00000000 39H Interrupt/DTP factor register EIRR R/W Request level setting register ELVR R/W ADCS0 R/W ADCS1 R/W! ADCR0 R ADCR1 R/W! 3AH 3BH 3CH 3DH 3EH 3FH Control status register Data register DTP/external interrupt _ XXXXXXX XXXXXXXX 00000000 00000000 00000000 A/D convertor 00000000 XXXXXXXX 0 0 0 0 1 _XX (Continued) 23 MB90550A/550B Series Address Register name Abbreviated register name Read/write Resource name Initial value 40H Reload register L (ch.0) PRLL0 R/W XXXXXXXX 41H Reload register H (ch.0) PRLH0 R/W XXXXXXXX 42H Reload register L (ch.1) PRLL1 R/W XXXXXXXX 43H Reload register H (ch.1) PRLH1 R/W XXXXXXXX 44H PPG0 operating mode control register PPGC0 R/W 45H PPG1 operating mode control register PPGC1 R/W 0_000001 46H PPG0 and 1 output control register PPGE1 R/W 00000000 8/16-bit PPG0/1 0_000__1 (Disabled) 47H 48H Reload register L (ch.2) PRLL2 R/W XXXXXXXX 49H Reload register H (ch.2) PRLH2 R/W XXXXXXXX 4AH Reload register L (ch.3) PRLL3 R/W XXXXXXXX 4BH Reload register H (ch.3) PRLH3 R/W XXXXXXXX 4CH PPG2 operating mode control register PPGC2 R/W 4DH PPG3 operating mode control register PPGC3 R/W 0_000001 4EH PPG2 and 3 output control register PPGE2 R/W 00000000 8/16-bit PPG2/3 0_000__1 (Disabled) 4FH 50H Reload register L (ch.4) PRLL4 R/W XXXXXXXX 51H Reload register H (ch.4) PRLH4 R/W XXXXXXXX 52H Reload register L (ch.5) PRLL5 R/W XXXXXXXX 53H Reload register H (ch.5) PRLH5 R/W XXXXXXXX 54H PPG4 operating mode control register PPGC4 R/W 55H PPG5 operating mode control register PPGC5 R/W 0_000001 56H PPG4 and 5 output control register PPGE3 R/W 00000000 59H 0_000__1 (Disabled) 57H 58H 8/16-bit PPG4/5 Clock output enable register CLKR R/W Clock monitor function ____0000 (Disabled) (Continued) 24 MB90550A/550B Series Address 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H Register name Control status register 0 Abbreviated register name Read/write TMCSR0 R/W TMR0/ TMRLR0 R/W Control status register 1 TMCSR1 R/W TMR1/ TMRLR1 Initial value 00000000 16-bit reload timer 0 16 bit timer register 0/ 16 bit reload register 0 16 bit timer register 1/ 16 bit reload register 1 Resource name ____0000 XXXXXXXX XXXXXXXX 00000000 16-bit reload timer 1 R/W ____0000 XXXXXXXX XXXXXXXX 62H Input capture register, channel-0 lower bits 63H Input capture register, channel-0 upper bits 64H Input capture register, channel-1 lower bits 65H Input capture register, channel-1 upper bits 66H Input capture register, channel-2 lower bits 67H Input capture register, channel-2 upper bits 68H Input capture register, channel-3 lower bits 69H Input capture register, channel-3 upper bits 6AH Input capture control status register ICS01 R/W 00000000 6BH Input capture control status register ICS23 R/W 00000000 6CH Timer data register, lower bits 6DH Timer data register, upper bits 6EH Timer control status register TCCS R/W 6FH ROM mirroring function selection register ROMM W XXXXXXXX IPCP0 R XXXXXXXX XXXXXXXX IPCP1 R XXXXXXXX IPCP2 R 16-bit I/O timer Input capture (ch.0 to ch.3) XXXXXXXX XXXXXXXX XXXXXXXX IPCP3 R XXXXXXXX TCDT R/W R/W 16-bit I/O timer free run timer ROM mirroring function 00000000 00000000 00000000 _______1 (Continued) 25 MB90550A/550B Series Address Register name Abbreviated register name Read/write Resource name Initial value 70H Compare register, channel-0 lower bits 71H Compare register, channel-0 upper bits 72H Compare register, channel-1 lower bits 73H Compare register, channel-1 upper bits 74H Compare register, channel-2 lower bits 75H Compare register, channel-2 upper bits 76H Compare register, channel-3 lower bits 77H Compare register, channel-3 upper bits 78H Compare control status register, channel-0 OCS0 R/W 0000__00 79H Compare control status register, channel-1 OCS1 R/W ___00000 7AH Compare control status register, channel-2 OCS2 R/W 0000__00 7BH Compare control status register, channel-3 OCS3 R/W ___00000 XXXXXXXX OCCP0 R/W XXXXXXXX XXXXXXXX OCCP1 R/W XXXXXXXX XXXXXXXX OCCP2 OCCP3 R/W 16-bit I/O timer output compare (ch.0 to ch.3) XXXXXXXX XXXXXXXX R/W XXXXXXXX 7CH to 9DH (Disabled) PACSR R/W Address match detection function 00000000 Delayed interrupt factor generation/cancellation register DIRR R/W Delayed interrupt _______0 A0H Low-power consumption mode control register LPMCR R/W! A1H Clock select register CKSCR R/W! 9EH Program address detection control register 9FH A2H to A4H Low power 00011000 consumption control 11111100 circuit (Disabled) A5H Automatic ready function select register ARSR W A6H External address output control register HACR W A7H Bus control signal select register ECSR W 0011__00 External bus pin control circuit 00000000 0000000_ (Continued) 26 MB90550A/550B Series Address Register name Abbreviated register name Read/write Resource name Initial value A8H Watchdog timer control register WDTC R/W! Watchdog timer XXXXX 1 1 1 A9H Timebase timer control register TBTC R/W! Timebase timer 1__00100 Flash memory interface circuit 00000__0 AAH to ADH AEH (Disabled) Flash memory control status register FMCS R/W (Disabled) AFH B0H Interrupt control register 00 ICR00 R/W! 00000111 B1H Interrupt control register 01 ICR01 R/W! 00000111 B2H Interrupt control register 02 ICR02 R/W! 00000111 B3H Interrupt control register 03 ICR03 R/W! 00000111 B4H Interrupt control register 04 ICR04 R/W! 00000111 B5H Interrupt control register 05 ICR05 R/W! 00000111 B6H Interrupt control register 06 ICR06 R/W! 00000111 B7H Interrupt control register 07 ICR07 R/W! B8H Interrupt control register 08 ICR08 R/W! B9H Interrupt control register 09 ICR09 R/W! 00000111 BAH Interrupt control register 10 ICR10 R/W! 00000111 BBH Interrupt control register 11 ICR11 R/W! 00000111 BCH Interrupt control register 12 ICR12 R/W! 00000111 BDH Interrupt control register 13 ICR13 R/W! 00000111 BEH Interrupt control register 14 ICR14 R/W! 00000111 BFH Interrupt control register 15 ICR15 R/W! 00000111 C0H to FFH (External area) 100H to #H (RAM area) #H to 1FEFH (Reserved area) Interrupt controller 00000111 00000111 (Continued) 27 MB90550A/550B Series (Continued) Address Register name Abbreviated register name Read/write 1FF0H Program address detection register 0 1FF1H Program address detection register 1 1FF2H Program address detection register 2 R/W 1FF3H Program address detection register 3 R/W 1FF4H Program address detection register 4 1FF5H Program address detection register 5 1FF6H to 1FFFH PADR0 PADR1 Resource name Initial value R/W XXXXXXXX R/W XXXXXXXX Address match detection function XXXXXXXX XXXXXXXX R/W XXXXXXXX R/W XXXXXXXX (Reserved area) • Initial value representations 0: Initial value of 0 1: Initial value of 1 X: Initial value undefined _: Initial value undefined (none) • Addresses that follow 00FFH are a reserved area. • The boundary #H between the RAM and reserved areas is different depending on each product. Note : For writable bits, the initial value column contains the initial value to which the bit is initialized at a reset. Notice that it is not the value read from the bit. The LPMCR, CKSCR, and WDTC registers may be initialized or not at a reset, depending on the type of the reset. Their initial values in the above list are those to which the registers are initialized, of course. “R/W!” in the access column indicates that the register contains read-only or write-only bits. If a read-modify-write instruction (such as a bit setting instruction) is used to access a register marked “R/ W!”, or “W” in the access column, the bit focused on by the instruction is set to the desired value but a malfunction occurs if the other bits contains a write-only bit. Do not use such instructions to access those registers. 28 MB90550A/550B Series ■ INTERRUPT FACTORS INTERRUPT VECTORS, INTERRUPT CONTROL REGISTERS Interrupt vectors EI2OS Interrupt source support Number Address Interrupt control registers ICR Address Reset × # 08 FFFFDCH — — INT9 instruction × # 09 FFFFD8H — — Exception × # 10 FFFFD4H — — # 11 FFFFD0H # 12 FFFFCCH ICR00 0000B0H DTP0 (external interrupt 0) # 13 FFFFC8H DTP4/5 (external interrupt 4/5) # 14 FFFFC4H ICR01 0000B1H DTP1 (external interrupt 1) # 15 FFFFC0H # 16 FFFFBCH ICR02 0000B2H # 17 FFFFB8H # 18 FFFFB4H ICR03 0000B3H # 19 FFFFB0H # 20 FFFFACH ICR04 0000B4H # 21 FFFFA8H # 22 FFFFA4H ICR05 0000B5H Extended I/O serial interface 1 # 23 FFFFA0H 16-bit free-run timer (I/O timer) overflow # 24 FFFF9CH ICR06 0000B6H 16-bit re-load timer 0 # 25 FFFF98H DTP6/7 (external interrupt 6/7) # 26 FFFF94H ICR07 0000B7H 16-bit re-load timer 1 # 27 FFFF90H # 28 FFFF8CH ICR08 0000B8H Input capture (ch.0) include (I/O timer) # 29 FFFF88H Input capture (ch.1) include (I/O timer) # 30 FFFF84H ICR09 0000B9H Input capture (ch.2) include (I/O timer) # 31 FFFF80H Input capture (ch.3) include (I/O timer) # 32 FFFF7CH ICR10 0000BAH Output compare (ch.0) match (Output timer) #33 FFFF78H Output compare (ch.1) match (Output timer) # 34 FFFF74H ICR11 0000BBH Output compare (ch.2) match (Output timer) # 35 FFFF70H Output compare (ch.3) match (Output timer) # 36 FFFF6CH ICR12 0000BCH UART transmission complete # 37 FFFF68H # 38 FFFF64H ICR13 0000BDH # 39 FFFF60H # 40 FFFF5CH ICR14 0000BEH A/D converter Timebase timer 8/16-bit PPG timer0 counter borrow × × DTP2 (external interrupt 2) 8/16-bit PPG timer 1 counter borrow × DTP3 (external interrupt 3) 8/16-bit PPG timer 2 counter borrow × Extended I/O serial interface 0 8/16-bit PPG timer 3 counter borrow 8/16-bit PPG timer 4/5 counter borrow 2 I C interface 0 × × × UART0 reception complete 2 I C interface 1 × × # 41 FFFF58H ICR15 0000BFH Delayed interrupt generation module × # 42 FFFF54H :The interrupt request flag is cleared by the EI2OS interrupt clear signal. The stop request is available. Flash memory status :The interrupt request flag is cleared by the EI2OS interrupt clear signal. × :The interrupt request flag is not cleared by the EI2OS interrupt clear signal. 29 MB90550A/550B Series Note: On using the EI2OS Function with Extended I/O Serial Interface 2 If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the EI2OS interrupt clear signal. When the EI2OS function is used for one of the two interrupt sources, therefore, the other interrupt function cannot be used. Set the interrupt request enable bit for the relevant resource to “0” for software polling processing. Interrupt source Interrupt No. Extended I/O serial interface 1 # 23 16-bit free-run timer (I/O timer) overflow 30 # 24 Interrupt control register Resource interrupt request Enabled ICR06 Disabled MB90550A/550B Series ■ ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings (VSS = AVSS = 0.0 V) Symbol Parameter Value Unit Remarks Min Max VCC VSS − 0.3 VSS + 6.0 V AVCC VSS − 0.3 VSS + 6.0 V AVRH VSS − 0.3 VSS + 6.0 V AVRL VSS − 0.3 VSS + 6.0 V Input voltage VI VSS − 0.3 VSS + 6.0 V *5 Output voltage VO VSS − 0.3 VSS + 6.0 V *5 − 2.0 + 2.0 mA MB90552A/2B/3A/3B*6 − 200 + 200 µA MB90F553A*6 20 mA MB90552A/2B/3A/3B*6 2 mA MB90F553A*6 IOL1 10 mA Other than P20 to P27 IOL2 20 mA P20 to P27 IOLAV1 4 mA Other than P20 to P27 IOLAV2 12 mA P20 to P27 ∑IOL 150 mA ∑IOLAV 80 mA IOH −15 mA “H” level average output current * IOHAV −4 mA “H” level total maximum output current ∑IOH −100 mA “H” level total average output current *4 ∑IOHAV −50 mA 550 mW MB90P553A 450 mW MB90F553A 200 mW MB90553A/553B 180 mW MB90552A/552B Power supply voltage Maximum clamp current ICLAMP Σ| ICLAMP | Total maximum clamp current “L” level maximum output current *2 “L” level average output current “L” level total maximum output current “L” level total average output current 2 “H” level maximum output current * 3 Power consumption Operating temperature Storage temperature PD TA −40 +85 °C TSTG −55 +150 °C VCC ≥ AVCC *1 AVCC ≥ AVRH ≥ AVRL *1 : Care must be taken that AVcc, AVRH, AVRL do not exceed Vcc. Also, care must be taken that AVRH, AVRL do not exceed AVCC, and AVRL does not exceed AVRH. *2 : The maximum output current is a peak value for a corresponding pin. *3 : Average output current is an average current value observed for a 100 ms period for a corresponding pin. *4 : Total average current is an average current value observed for a 100 ms period for all corresponding pins. *5 : VI and VO should not exceed VCC + 0.3V. *6 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA4 (Continued) 31 MB90550A/550B Series (Continued) • Use within recommended operating conditions. • Use at DC voltae (current) . • The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. • The value of the limiting resistance should be set to so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. • Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. • Note that is the +B input is applied during power-on, the power supply is provided from the pins and resulting supply voltage may not be sufficient to operate the power-on reset. • Care must be taken not to leave the +B input pin open. • Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. • Sample recommended circuits : • Input/output equivalent circuits Protective diode VCC +B input (0 V to 16 V) P-ch Limiting resistance N-ch R Note: Average output current = operating current × operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 32 MB90550A/550B Series 2. Recommended Operating Conditions (VSS = AVSS = 0.0 V) Parameter Power supply voltage Value Symbol VCC AVCC Unit Remarks Min Max 4.5 5.5 V Normal operation (MB90F553A, MB90P553A, MB90V550A) 3.5 5.5 V Normal operation (MB90553A, MB90553B, MB90552A, MB90552B) 3.5 5.5 V Retains status at the time of operation stop * Smoothing capacitor CS 0.1 1.0 µF Operating temperature TA –40 +85 °C * : Use a ceramic capacitor or a capacitor with equivqlent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. For connecting smoothing capacitor CS, see the diagram below: • C pin connection circuit C CS VSS AVSS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 33 MB90550A/550B Series 3. DC Characteristics Parameter “H” level input voltage “L” level input voltage Open-drain output pin voltage “H” level output voltage “L” level output voltage 1 “L” level output voltage 2 Input leakage current (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = –40 °C to +85 °C) Value Symbol Pin name Condition Unit Remarks Min Typ Max VIH CMOS input pin*1 — 0.7VCC — VCC+0.3 V VIHS CMOS hysteresys input pin*2 — 0.8VCC — VCC+0.3 V VIHM MD pin input*3 — VCC − 0.3 — VCC+0.3 V VIL CMOS input pin*1 — VSS − 0.3 — 0.3VCC V VILS CMOS hysteresys input pin*2 — VSS − 0.3 — 0.2VCC V VILM MD pin input*3 — VSS − 0.3 — VSS +0.3 V VD VOH VOL1 VOL2 IIL P50 to P55 Other than P50 to P55 Other than P20 to P27 P20 to P27 All output pins ICC Power supply current *4 VCC ICCS ICCH Input capacitance Open-drain output leakage current Pull-up resistance — VSS – 0.3 — VCC = 4.5V, VCC – 0.5 — IOH = −4.0mA VCC = 4.5V, — — IOL = 4.0mA VCC = 4.5V, — — IOL = 12.0mA VCC = 5.5V, –5 — VSS < VI < VCC Internal — 30 operation at 16 — 80 MHz — 60 VCC = 5.5 V — 30 Normal opera— 25 tion When data written in flash — 100 mode — 7 Internal — 25 operation at 16 MHz — 10 VCC = 5.5 V — 7 In sleep mode — 7 — 5 — 0.1 VCC = 5.5V, TA = +25°C — 5 In stop mode — 5 — 5 VSS + 6.0 V — V 0.4 V 0.4 V 5 µA 40 110 90 40 mA mA mA mA 35 mA MB90552A/B 150 mA MB90F553A 10 30 20 10 10 20 10 20 20 20 mA mA mA mA mA µA µA µA µA µA CIN Other than AVCC, AVSS, C, VCC and VSS — — 10 — pF Ileak P50 to P55 — — 0.1 5 µA RUP P00 to P07 and P10 to P17 (In pull-up setting),RST — 25 50 100 20 40 100 MB90V550A MB90P553A MB90F553A MB90553A/B MB90V550A MB90P553A MB90F553A MB90553A/B MB90552A/B MB90V550A MB90P553A MB90F553A MB90553A/B MB90552A/B Other than MB90V550A kΩ MB90V550A kΩ *1 : P00 to P07, P10 to P17, P20 to P27, P30 to P37 *2 : X0, HST, RST, P40 to P47, P50 to P55, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA4 *3 : MD0, MD1 and MD2 *4 : The current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. The power supply current is measured with an external clock. 34 MB90550A/550B Series 4. AC Characteristics (1) Clock Timing Symbol Parameter (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Unit Unit Min Typ Max Oscillation clock frequency FC X0, X1 3 — 16 MHz Oscillation clock cycle time tC X0, X1 62.5 — 333 ns Frequency fluctuation rate locked* ∆f — — — 5 % Input clock pulse width PWH PWL X0 10 — — ns Recommended duty ratio of 40% to 60% Input clock rising/falling time tCR, tCF X0 — — 5 ns External clock operation Internal operating clock frequency FCP — 8.0 — 16 MHz PLL operation 1.5 — 16 MHz Main clock operation Internal operating clock cycle time tCP — 62.5 — 125 ns PLL operation 62.5 — 666 ns Main clock operation * : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked. + ∆f = α fo +α × 100 (%) Center frequency fo −α − • X0, X1 clock timing tHCYL 0.8 VCC 0.8 VCC 0.8 VCC 0.2 VCC X0 PWH tCF 0.2 VCC PWL tCR 35 MB90550A/550B Series • PLL operation guarantee range Power supply voltage VCC (V) Relationship between internal operating clock frequency and power supply voltage Operation guarantee range MB90F553A, MB90P553A, MB90V550A 5.5 4.5 3.5 PLL Operation guarantee range Operation guarantee range MB90553A/553B, MB90552A/552B 1.5 3 8 12 16 Internal operating clock frequency FCP (MHz) Internal operating clock frequency FCP (MHz) Relationship between oscillation clock frequency and internal operating clock frequency 16 Multiplied- Multipliedby-4 Multiplied-by-2 by-3 Multiplied-by-1 12 9 8 Not multiplied 4 1.5 3 4 8 16 Oscillation clock frequency FC (MHz) The AC ratings are measured for the following measurement reference voltages. • Input signal waveform Hystheresis input pin Output pin 0.8 VCC 2.4 V 0.2 VCC 0.8 V Pins other than hystheresis input / MD input 0.7 VCC 0.3 VCC 36 • Output signal waveform MB90550A/550B Series (2) Clock Output Timing Parameter Symbol Cycle time tCYC CLK ↑ → CLK ↓ time tCHCL (VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Unit Remarks Min Max CLK 62.5 — ns tCP/2 − 20 tCP/2+20 ns tCYC tCHCL 2.4 V CLK 2.4 V 0.8 V 37 MB90550A/550B Series (3) Reset, Hardware Standby Input Timing (VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Unit Remarks Min Max Parameter 16 tCP — ns Under normal operation Reset input time tRSTL RST Oscillation time of oscillator* + 16 tCP — ms In stop mode Hardware standby input time tHSTL HST 16 tCP — ns Under normal operation * : Oscillation time of oscillator is time that the amplitude reached the 90 %. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time is between hundreds of µs to several ms. In the external clock, the oscillation time is 0 ms. • Under normal operation tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC • In stop mode tRSTL RST 0.2 VCC X0 Internal operation clock 0.2 VCC 90% of amplitude Oscillator oscillation time 16 tCP Oscillation stabilize standby time Instruction execution Internal reset 38 MB90550A/550B Series (4) Specification for Power-on Reset Parameter Symbol Power supply rising time (VCC = 5.0 V ± 10 %, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Pin name Unit Remarks Min Max tR 0.05 30 ms — 0.2 V Power-supply start voltage VOFF Power-supply end voltage VON 2.7 — V Power supply cut-off time tOFF 4 — ms VCC Due to repeated operations Note: • VCC must be kept lower than 0.2 V before power-on. • The above values are used for creating a power-on reset. • Some registers in the device are initialized only upon a power-on reset. To initialize these register, turn on the power supply using the above values. tR 2.7 V 0.2 V VCC 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock. VCC 5.0 V 3.0 V It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower. VSS RAM data being held 0V 39 MB90550A/550B Series (5) Bus Read Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Value Pin name Min Max Unit ALE pulse width tLHLL ALE tCP/2 − 20 — ns Effective address → ALE ↓ time tAVLL ALE, A23 to A16, AD15 to AD00 tCP/2 − 20 — ns ALE ↓ → address effective time tLLAX ALE, AD15 to AD00 tCP/2 − 15 — ns Effective address → RD ↓ time tAVRL A23 to A16, AD15 to AD00, RD tCP − 15 — ns Effective address → valid data input tAVDV A23 to A16, AD15 to AD00 — 5 tCP/2 − 60 ns RD pulse width tRLRH RD 3 tCP/2 − 20 — ns RD ↓ → valid data input tRLDV RD, AD15 to AD00 — 3 tCP/2 − 60 ns RD ↑ → data hold time tRHDX RD, AD15 to AD00 0 — ns RD ↑ → ALE ↑ time tRHLH RD, ALE tCP/2 − 15 — ns RD ↑ → address effective time tRHAX ALE, A23 to A16 tCP/2 − 10 — ns Effective address → CLK ↑ time tAVCH A23 to A16, AD15 to AD00, CLK tCP/2 − 20 — ns RD ↓ → CLK ↑ time tRLCH RD, CLK tCP/2 − 20 — ns ALE ↓ → RD ↓ time tLLRL ALE, RD tCP/2 − 15 — ns Remarks • Bus read timing tAVCH tRLCH 2.4 V 2.4 V CLK tRHLH 2.4 V ALE tLHLL 2.4 V 0.8 V tAVLL tLLAX 2.4 V tRLRH RD tLLRL • Multiplex mode tAVRL A23 to A16 2.4 V 0.8 V tRHAX tRLDV 2.4 V 0.8 V 2.4 V 0.8 V tAVDV AD15 to AD00 40 2.4 V 0.8 V Address 2.4 V 0.8 V 0.7 VCC 0.3 VCC Read data tRHDX 0.7 VCC 0.3 VCC MB90550A/550B Series (6) Bus Write Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Value Symbol Pin name Effective address → WR ↓ time tAVWL A23 to A16, AD15 to AD00, WRH, WRL WR pulse width tWLWH valid data output→ WR ↑ time Parameter Unit Min Max tCP – 15 — ns WRH, WRL 3 tCP/2 – 20 — ns tDVWH AD15 to AD00, WRH, WRL 3 tCP/2 – 20 — ns WR ↑ → data hold time tWHDX AD15 to AD00, WRH, WRL 20 — ns WR ↑ → address effective time tWHAX A23 to A16, WRH, WRL tCP/2 – 10 — ns WR ↑ → ALE ↑ time tWHLH WRH, WRL, ALE tCP/2 – 15 — ns WR ↓ → CLK ↑ time tWLCH WRH, WRL, CLK tCP/2 – 20 — ns Remarks Multiplex mode • Bus write timing tWLCH 2.4 V CLK tWHLH 2.4 V ALE tAVWL WR (WRL, WRH) tWLWH 2.4 V 0.8 V • Multiplex mode A23 to A16 tWHAX 2.4 V 2.4 V 0.8 V 0.8 V tDVWH AD15 to AD00 2.4 V 0.8 V Address 2.4 V 0.8 V Write data tWHDX 2.4 V 0.8 V 41 MB90550A/550B Series (7) Ready Input Timing Parameter (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol RDY setup time tRYHS RDY hold time tRYHH Value Pin name Unit Min Max 45 — ns 0 — ns RDY CLK Remarks Note : Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient. • Ready input timing 2.4 V CLK ALE WR (WRL, WRH) 0.8 V tRYHS RDY wait not inserted RDY wait inserted (1 cycle) 42 0.8 VCC 0.2 VCC tRYHH 0.8 VCC MB90550A/550B Series (8) Hold Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pins in floating status → HAK ↓ time tXHAL HAK ↑ → pin valid time tHAHV Pin name HAK Value Unit Min Max 30 tCP ns tCP 2 tCP ns Remarks Note : More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched. • Hold timing HAK tXHAL tHAHV Pins High-Z (9) UART, Extended I/O Serial 0, 1 Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name Serial clock cycle time tSCYC SCK0 to SCK2 SCK ↓ → SOT delay time tSLOV Valid SIN → SCK ↑ tIVSH SCK ↑ → valid SIN hold time tSHIX Serial clock “H” pulse width tSHSL Serial clock “L” pulse width tSLSH SCK ↓ → SOT delay time tSLOV Valid SIN → SCK ↑ tIVSH SCK ↑ → valid SIN hold time tSHIX Parameter Condition Value Unit Min Max 8 tCP — ns –80 80 ns 100 — ns tCP — ns SCK0 to SCK2 4 tCP — ns SCK0 to SCK2 4 tCP — ns — 150 ns 60 — ns 60 — ns SCK0 to SCK2, Internal shift clock SOT0 to SOT2 mode SCK0 to SCK2, CL = 80 pF + 1 TTL for an outSIN0 to SIN2 put pin SCK0 to SCK2, SIN0 to SIN2 External shift clock SCK0 to SCK2, mode SOT0 to SOT2 CL = 80 pF + 1 TTL for an SCK0 to SCK2, output pin SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 Remarks Notes: • These are AC ratings in the CLK synchronous mode. • CL is the load capacitance value connected to pins while testing. 43 MB90550A/550B Series • Internal shift clock mode tSCYC SCK 2.4 V 0.8 V 0.8 V tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC • External shift clock mode tSLSH SCK tSHSL 0.8 VCC 0.2 VCC 0.8 VCC 0.2 VCC tSLOV 2.4 V SOT 0.8 V tIVSH SIN tSHIX 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC (10) Timer Input Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Input pulse width Symbol tTIWH tTIWL Pin name TIN0, TIN1 IN0 to IN3 Value Min Max 4 tCP — Unit Remarks ns • Timer input timing 0.8 VCC 0.8 VCC TIN0 to TIN1 IN0 to IN3 0.2 VCC tTIWH 44 0.2 VCC tTIWL MB90550A/550B Series (11) Timer Output Timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Value Symbol Pin name tTO TOT0,TOT1,OUT0, OUT1,PPG0 to PPG5 CLK ↑ → TOUT transition time Min Max 30 — Unit Remarks ns • Timer output timing 2.4 V CLK tTO TOT0,TOT1 OUT0,OUT1 PPG0 to PPG5 2.4 V 0.8 V (12) Trigger Input Timing Parameter Input pulse width (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name tTRGH tTRGL IRQ0 to IRQ7 Value Unit Remarks — ns Under normal operation — µs In stop mode Min Max 5 tCP 1 • Trigger input timing 0.8 VCC 0.8 VCC 0.2 VCC IRQ0 to IRQ7 tTRGH 0.2 VCC tTRGL 45 MB90550A/550B Series (13) I2C Interface Parameter Internal clock cycle time (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Symbol Pin name tCP — Start condition output tSTAO Stop condition output tSTOO Start condition detection tSTAI Stop condition detection tSTOI SCL output “L” width tLOWO SCL output “H” width tHIGHO SDA output delay time tDOO Setup after SDA output interrupt period tDOSUO SCL input “L” width tLOWI SCL input “H” width tHIGHI SDA input setup time tSUI SDA input hold time tHOI SDA0 to SDA2 SCL0 toSCL2 SCL0 to SCL2 SDA0 to SDA2 SCL0 to SCL2 SCL0 to SCL2 SDA0 to SDA2 SCL0 to SCL2 Value Min Max 62.5 666 Unit ns tCP × m × n/2 – 20 tCP × m × n/2 + 20 ns tCP (m × n/2 + 4) – 20 tCP (m × n/2 + 4) + 20 ns 3 tCP + 40 — ns 3 tCP + 40 — ns tCP × m × n/2 – 20 tCP × m × n/2 + 20 ns tCP (m × n/2 + 4) – 20 tCP (m × n/2 + 4) + 20 ns 2 tCP – 20 2 tCP + 20 ns 4 tCP – 20 — ns 3 tCP + 40 — ns tCP + 40 — ns 40 — ns 0 — ns Remarks All products Only as master Only as slave Only as master Notes: • “m” and“n” in the above table represent the values of shift clock frequency setting bits (CS4 to CS0) in the clock control register “ICCR”. For details, refer to the register description in the hardware manual. • tDOSUO represents the minimum value when the interrupt period is equal to or greater than the SCL “L” width. • The SDA and SCL output values indicate that that rise time is 0 ns. 46 MB90550A/550B Series • I2C interface [data transmitter (master/slave)] tLOWO tHIGHO 0.8 VCC 0.8 VCC 0.8 VCC 0.8 VCC 0.8 VCC SCL 0.2 VCC 0.2 VCC 8 1 tSTAO tDOO 9 tSUI tDOO SDA tHOI tDOSUO ACK • I2C interface [data receiver (master/slave)] tHIGHI 0.8 VCC tLOWI 0.8 VCC 0.8 VCC SCL 0.2 VCC 6 7 tSUI SDA tHOI 0.2 VCC 8 0.2 VCC 0.2 VCC 9 tDOO tDOO tDOSUO tSTOI ACK 47 MB90550A/550B Series 5. A/D Converter (1)Electrical Characteristics (4.5 V ≤ AVRH − AVRL, VCC = AVCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +85 °C) Parameter Symbol Pin name Value Min Typ Max Unit Remarks Resolution — — — 10 — bit Total error — — — — ±5.0 LSB Non-linearity error — — — — ±2.5 LSB Differential linearity error — — — — ±1.9 LSB Zero transition voltage VOT AN0 to AN7 AVRL− 3.5LSB AVRL+ 0.5LSB AVRL+ 4.5LSB V Full-scale transition voltage VFST AN0 to AN7 AVRH− 6.5LSB AVRH− 1.5LSB AVRH+ 1.5LSB V Sampling period tSMP — 64 — 4096 tCP Compare time tCMP — 22 — — µs *1 A/D Conversion time tCNV — 26.3 — — µs *2 Analog port input current IAIN AN0 to AN7 — — 10 µA Analog input voltage VAIN AN0 to AN7 AVRL — AVRH V Reference voltage Power supply current — AVRH AVRL + 4.5 — AVCC V — AVRL 0 — AVRH − 4.5 V — 3.5 7.0 mA — — 5 µA — 300 500 µA — — 5 µA — — 4 LSB IA IAH IR Reference voltage supply current IRH Offset between channels — AVCC AVRH AN0 to AN7 1LSB= (AVRH−AVRL) /1024 *3 *3 *1: When FCP = 8 MHz, tCMP = 176 × tCP. When FCP = 16 MHz, tCMP = 352 × tCP. *2: Equivalent to the time for conversion per channel if “tSMP = 64 × tCP” or “tCMP = 352 × tCP” is selected when FCP = 16 MHz. *3: Specifies the power-supply current (Vcc = AVcc = AVRH = 5.0 V) when the A/D converter is inactive and the CPU has been stopped. Notes: • The error becomes larger relatively as |AVRH-AVRL| becomes smaller. • Use the output impedance rS of the external circuit for analog input under the following condition: External circuit output impedance rS = 10 kΩ Max. • If the output impedance of the external circuit is too high, the analog voltage sampling time may be insufficient. • If you insert a DC-blocking capacitor between the external circuit and the input pin, select a capacitance that is about several thousands times the sampling capacitance CSH in the chip to suppress the effect of capacity potential division with CSH. 48 MB90550A/550B Series • Analog input circuit model Microcontroller internal circuit Input pin AN0 rS RSH CSH Input pin AN7 VS External circuit to Comparator S/H circuit Analog channel selector <Recommended/reference values for device parameters> rS = 10 kΩ or less RSH = About 3 kΩ CSH = About 25 pF Note: Device parameter values are provided as reference values for design purposes; they are not guaranteed. 49 MB90550A/550B Series (2) Definitions of Terms • Resolution: Analog transition identifiable by the A/D converter. Analog voltage can be divided into 1024 (210) components at 10-bit resolution. • Total error: Difference between actual and logical values. This error is the sum of an offset error, gain error, non-linearity error and an error caused by noise. • Linearity error: Deviation of the straight line drawn between the zero transition point (00 0000 0000 <-> 00 0000 0001) and the full-scale transition point (11 1111 1110 <-> 11 1111 1111) of the device from actual conversion characteristics • Differential linearity error: Deviation from the ideal input voltage required to shift output code by one LSB • 10-bit A/D converter conversion characteristics 11 11 11 11 1111 1111 1111 1111 1111 1110 1101 1100 • • 1LSB × N + VOT • Digital output • • • • • • Linearity error • • • • 00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000 VOT VNT V(N + 1)T Analog input VFST − VOT 1022 VNT − (1LSB × N + VOT) Linearity error = [ LSB ] 1LSB V (N + 1) T − VNT − 1 [ LSB ] Differential linearity error = 1LSB 1LSB = 50 VFST MB90550A/550B Series 6. Flash Memory Program/Erase Characteristics Parameter Condition Sector erase time Chip erase time TA = + 25 °C VCC = 5.0 V Word (16-bit width) programming time Program/Erase cycle — Data hold time — Value Unit Remarks 30 s Excludes 00H programming prior erasure 10.5 — s Excludes 00H programming prior erasure — 16 500 µs Excludes system-level overhead 100,000 — — cycle Guaranteed 100,000 cycles 10,000 — — cycle Guaranteed 10,000 cycles 100,000 — — Min Typ Max — 1.5 — h 51 MB90550A/550B Series ■ EXAMPLE CHARACTERISTICS 1. “L” level output voltage VOL − IOL Other than P20 to P27 700 600 VOL (mV) 500 400 300 200 100 0 0 2 4 6 8 10 IOL (mA) VOL − IOL P20 to P27 700 TA = + 25 °C VCC = 3.5 V 600 VCC = 4.0 V VOL (mV) 500 VCC = 5.0 V VCC = 6.0 V 400 300 200 100 0 0 5 10 15 IOL (mA) 52 20 25 30 MB90550A/550B Series 2. “H” level output voltage (VCC − VOH) − IOH Other than P50 to P55 700 TA = + 25 °C 600 VCC = 3.5 V VCC − VOH (mV) 500 VCC = 4.0 V VCC = 5.0 V 400 VCC = 6.0 V 300 200 100 0 −2 0 −4 −6 −8 −10 IOH (mA) 3. “H” level input voltage / “L” level input voltage (CMOS input) VIH / VIL − VCC 5 4.5 TA = + 25 °C 4 VIH/VIL (V) 3.5 3 2.5 2 1.5 1 1.5 0 3.5 4 4.5 5 5.5 VCC (V) 53 MB90550A/550B Series 4. “H” level input voltage / “L” level input voltage (CMOS hysteresis input) VIHS / VILS − VCC 5 4.5 TA = + 25 °C 4 VIHS/VILS (V) 3.5 VIHS 3 2.5 2 VIHL 1.5 1 1.5 0 3.5 4 4.5 VCC (V) 54 5 5.5 MB90550A/550B Series 5. Power supply current (fCP = internal operating clock frequency) • MB90552A/B • Measurement conditions: External clock mode, ROM read loop operation, without resource operation, Typ sample, internal operating frequency = 4MHz (external rectangular wave clock at 8MHz), TA = + 25 °C ICC − VCC 30 TA = + 25 °C fCP = 16 MHz 25 ICC (mA) 20 fCP = 10.6 MHz 15 fCP = 8 MHz 10 fCP = 4 MHz 5 0 3.5 4 4.5 5 5.5 VCC (V) ICCS − VCC 10 9 TA = + 25 °C fCP = 16 MHz 8 ICCS (mA) 7 fCP = 10.6 MHz 6 5 fCP = 8 MHz 4 3 fCP = 4 MHz 2 1 0 3.5 4 4.5 5 5.5 VCC (V) (Continued) 55 MB90550A/550B Series (Continued) • MB90F553A • Measurement conditions: External clock mode, ROM read loop operation, without resource operation, Typ sample, internal operating frequency = 4MHz (external rectangular wave clock at 8MHz), TA = +25 °C ICC − VCC 70 TA = + 25 °C 60 fCP = 16 MHz ICC (mA) 50 40 fCP = 10 MHz 30 fCP = 4 MHz 20 10 4.5 5 5.5 VCC (V) ICCS − VCC 12 TA = + 25 °C 10 fCP = 16 MHz ICCS (mA) 8 fCP = 10 MHz 6 4 fCP = 4MHz 2 0 4.5 5 VCC (V) 56 5.5 MB90550A/550B Series 6. Pull-up resistance Pull-up resistance − VCC 90 Pull-up resistance (kΩ) 80 TA = + 85 °C 70 TA = + 25 °C 60 TA = −40 °C 50 40 30 20 10 4 4.5 5 5.5 VCC (V) 57 MB90550A/550B Series ■ ORDERING INFORMATION Part number 58 Package MB90552APF MB90552BPF MB90553APF MB90553BPF MB90T552APF MB90T553APF MB90F553APF MB90P553APF 100-pin plastic QFP (FPT-100P-M06) MB90552APFV MB90552BPFV MB90553APFV MB90553BPFV MB90T552APFV MB90T553APFV MB90F553APFV MB90P553APFV 100-pin plastic LQFP (FPT-100P-M05) Remarks MB90550A/550B Series ■ PACKAGE DIMENSIONS 100-pin plastic QFP (FPT-100P-M06) 23.90±0.40(.941±.016) 20.00±0.20(.787±.008) 80 51 81 50 0.10(.004) 17.90±0.40 (.705±.016) 14.00±0.20 (.551±.008) INDEX Details of "A" part 100 1 30 0.65(.026) "A" C 0.25(.010) +0.35 3.00 –0.20 +.014 .118 –.008 (Mounting height) 0~8° 31 0.32±0.05 (.013±.002) 0.13(.005) M 0.17±0.06 (.007±.002) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) 0.25±0.20 (.010±.008) (Stand off) 2001 FUJITSU LIMITED F100008S-c-4-4 Dimensions in mm (inches) (Continued) 59 MB90550A/550B Series (Continued) 100-pin plastic LQFP (FPT-100P-M05) 16.00±0.20(.630±.008)SQ 14.00±0.10(.551±.004)SQ 75 51 76 50 0.08(.003) Details of "A" part +0.20 100 26 1 25 C 0.20±0.05 (.008±.002) 0.08(.003) M 0.10±0.10 (.004±.004) (Stand off) 0°~8° "A" 0.50(.020) +.008 1.50 –0.10 .059 –.004 (Mounting height) INDEX 0.145±0.055 (.0057±.0022) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) 2000 FUJITSU LIMITED F100007S-3c-5 Dimensions in mm (inches) 60 MB90550A/550B Series FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. 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The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.