ds90520b-ds07-13707-3e.pdf

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13707-3E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90520A/520B Series
MB90522A/523A/522B/523B/F523B/V520A
■ DESCRIPTION
The MB90520A/520B series is a general-purpose 16-bit microcontroller designed for process control applications
in consumer products that require high-speed real-time processing.
The microcontroller instruction set is based on the AT architecture of the F2MC* family with additional instructions
for high-level languages, extended addressing modes, enhanced multiplication and division instructions, and a
complete range of bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long
word (32-bit) data.
The MB90520A/520B series peripheral resources include an 8/10-bit A/D converter, 8-bit D/A converter, UART
(SCI) , extended I/O serial interfaces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit PPG timers 0 and
1, a range of I/O timers (16-bit free-run timers 1 and 2, input capture (ICU) 0 and 1, and output compare (OCU)
0 and 1) , an LCD controller/driver, 8 external interrupt inputs, and 8 wakeup interrupts.
* : F2MC stands for FUJITSU Flexible MicroController, a registered trademark of FUJITSU LIMITED.
■ FEATURES
• Clock
• Internal PLL clock multiplication circuit
• Selectable machine clock (PLL clock) : Base oscillation divided by two or multiplied by one to four
(For a 4 MHz base oscillation, the machine clock range is 4 MHz to 16 MHz) .
(Continued)
■ PACKAGES
120-pin, Plastic, LQFP
120-pin, Plastic, QFP
(FPT-120P-M05)
(FPT-120P-M13)
MB90520A/520B Series
(Continued)
• Sub-clock (32.768 KHz) operation available
Minimum instruction execution time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = ×4, VCC = 5.0 V)
• 16MB CPU memory space
Internal 24-bit addressing
• Instruction set optimized for controller applications
Rich data types (bit, byte, word, long-word)
Extended addressing modes (23 types)
Enhanced signed multiplication and division instructions and RETI instruction
Enhanced calculation precision using a 32-bit accumulator
• Instruction set designed for high-level language (C) and multi-tasking
System stack pointer
Enhanced pointer-indirect instructions and barrel shift instructions
• Faster execution speed
4-byte instruction queue
ROM mirror function (48 Kbytes of bank FF is mirrored in bank 00)
• Program patch function : An address match detection function (2 × addresses)
• Interrupt function
32 programmable interrupts with 8 levels
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS) : Up to 16 channels
• Low-power consumption (stand-by) modes
Sleep mode (CPU operating clock stops, peripherals continue to operate.)
Pseudo-clock mode (Only oscillation clock and timebase timer continue to operate.)
Clock mode (Main oscillation clock stops, sub-clock and clock timer continue to operate.)
Stop mode (Main oscillation and sub-clock both stop.)
CPU intermittent operation mode
Hardware stand-by mode (Change to stop mpde by operating hardware stand-by pins.)
• Process
CMOS technology
• I/O ports
General-purpose I/O ports (CMOS input/output) : 53 ports
General-purpose I/O ports (inputs with pull-up resistors) : 24 ports
General-purpose I/O ports (Nch open-drain outputs) : 8 ports
• Timers
Timebase timer, clock timer, watchdog timer : 1 channel each
8/16-bit PPG timers 0 and 1 : 8-bit × 2 channels or 16-bit × 1 channel
16-bit reload timers 0 and 1 : 2 channels
16-bit I/O timers :
16-bit free-run timers 0 and 1 : 2 channels
16-bit input capture 0 : 2 channels (2 channels per unit)
16-bit output compare 0 and 1 : 8 channels (4 channels per unit)
8/16-bit up/down counter/timers 0 and 1 : 8-bit × 2 channels or 16-bit × 1 channel
Clock output function : 1 channel
• Communications macro (communication interface)
Extended I/O serial interfaces 0 and 1 : 2 channels
UART (full-duplex, double-buffered, SCI : Can also be used for synchronous serial transfer) : 1 channel
2
MB90520A/520B Series
• External event interrupt control function
DTP/external interrupts : 8 channels (Can be set to detect rising edges, falling edges, “H” levels, or “L” levels)
Wake-up interrupts : 8 channels (Detects “L” levels only)
Delayed interrupt generation module : 1 channel (for task switching)
• Analog/digital conversion
8/10-bit A/D converter : 8 channels (Can be initiated by an external trigger. Minimum conversion time = 10.2
µs for a 16 MHz machine clock)
8-bit D/A converter : 2 channels (R-2R type. Settling time = 12.5 µs for a 16 MHz machine clock)
• Display function
LCD controller/driver : 32 × segment drivers + 4 × common drivers
• Other
Supports serial writing to flash memory. (Only on versions with on-board flash memory.)
Note : The MB90520A and 520B series cannot be used in external bus mode. Always set these devices to singlechip mode.
3
MB90520A/520B Series
■ PRODUCT LINEUP
Part
Number MB90522A
MB90523A
MB90522B
MB90523B
MB90F523B MB90V520A
Parameter
Classification
ROM size
Mask ROM
64 Kbytes
128 Kbytes
RAM size
64 Kbytes
128 Kbytes
Flash ROM
Evaluation
product
128 Kbytes

4 Kbytes
Separate emulator
power supply*1



Process
6 Kbytes


No
CMOS
Operating power
supply voltage*2
Internal regulator circuit
CPU functions
3.0 V to 5.5 V
2.7 V to 5.5 V
not mounted
3.0 V to 5.5 V
mounted
Number of instructions : 340
Instruction sizes : 8-bit, 16-bit
Instruction length : 1 byte to 7 bytes
Data sizes : 1-bit, 8-bit, 16-bit
Minimum instruction execution time : 62.5 ns (for a 16 MHz machine clock)
Interrupt processing time : 1.5 µs min. (for a 16 MHz machine clock)
Low power operation
(standby modes)
Sleep mode, clock mode, pseudo-clock mode, stop mode, hardware standby mode,
and CPU intermittent operation mode
I/O ports
General-purpose I/O ports (CMOS outputs) : 53
General-purpose I/O ports (inputs with pull-up resistors) : 24
General-purpose I/O ports (Nch open drain outputs) : 8
Total : 85
Timebase timer
18-bit counter
Interrupt interval : 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
(for a 4 MHz base oscillation)
Watchdog timer
Reset trigger period
• For a 4 MHz base oscillation : 3.58, 14.33, 57.23, 458.75 ms
• For 32.768 sub-clock operation : 0.438, 3.500, 7.000, 14.000 s
16-bit
I/O
timers
16-bit
freerun
timer
Number of channels : 2
Generates an interrupt on overflow
16-bit
output
compare
Number of channels : 8
Pin change timing : Free run timer register value equals output compare register value.
16-bit
input
capture
Number of channels : 2
Saves the value of the freerun timer register when a pin input occurs (rising edge, falling
edge, either edge) .
16-bit reload timer
Number of channels : 2
Count clock frequency : 0.125, 0.5, or 2.0 µs for a 16 MHz machine clock
Can be used to count an external event clock.
(Continued)
4
MB90520A/520B Series
(Continued)
Part
Number
MB90522A
MB90523A
MB90522B
MB90523B
MB90F523B MB90V520A
Parameter
Clock timer
15-bit timer
Interrupt interval : 0.438, 0.5, or 2.0 µs for sub-clock frequency = 32.768 kHz
8/16-bit PPG timer
Number of channels : 1 (Can be used in 2 × 8-bit channel mode)
Can generate a pulse waveform output with specified period and 0 to 100% duty ratio.
8/16 -bit up/down
counter/timers
Number of channels : 1 (Can be used in 2 × 8-bit channel mode)
External event inputs : 6 channels
Reload/compare function : 8-bit × 2 channels
Clock monitor
Clock output frequency : Machine clock/21 to machine clock/28
Delayed interrupt
generation module
Interrupt generation module for task switching. (Used by REALOS.)
DTP/External
interrupts
Input channels : 8
Generates interrupts to the CPU on rising edges, falling edges with input “H” level, or “L”
level.
Can be used for external event interrupts and to activate EI2OS.
Wakeup interrupts
Input channels : 8
Triggered by “L” level.
8/10-bit A/D converter
(successive
approximation type)
Number of channels : 8
Resolution : 8-bit or 10-bit selectable
Conversion can be performed sequentially for multiple consecutive channels.
• Single-shot conversion mode : Converts specified channel once only.
• Continuous conversion mode : Repeatedly converts specified channel.
• Intermittent conversion mode : Converts specified channel then halts temporarily.
8-bit D/A converter
(R-2R type)
Number of channels : 2
Resolution : 8-bit
UART (SCI)
Number of channels : 1
Clock synchronous transfer : 62.5 Kbps to 1 Mbps
Clock asynchronous transfer : 1202 bps to 31250 bps
Supports bi-directional and master-slave communications.
Extended I/O serial
interface
Number of channels : 2
Clock synchronous transfer : 31.25 Kbps to 1 Mbps (Using internal shift clock)
Transmission format : Selectable LSB-first or MSB-first
LCD controller/driver
Number of common outputs : 4
Number of segment outputs : 32
Number of power supply pins for LCD drive : 4
LCD display memory : 16 bytes
Divider resistor for LCD drive : Internal
*1 : As for the necessity of a DIP switch setting (S2) when using the emulation pod (MB2145-507) .
Refer to the hardware manual for the emulation pod (MB2145-507) fomr details.
*2 : Take note of the maximum operating frequency and A/D converter precision restrictions when operating at 3.0 V
to 3.6 V. See the “Electrical Characteristics” section for details.
5
MB90520A/520B Series
■ PACKAGES AND CORRESPONDING PRODUCTS
Package
MB90522A
MB90523A
MB90522B
MB90523B
MB90V520A
FPT-120P-M05
(LQFP)
×
FPT-120P-M13
(QFP)
×
PGA-256C-A01
(PGA)
×
×
×
: Available, × : Not available
Note : See the “■ PACKAGE DIMENSIONS” section for more details.
6
MB90F523B
×
×
MB90520A/520B Series
■ PIN ASSIGNMENT
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
P30
VSS
P27/ADTG
P26/ZIN0/INT7
P25/BIN0
P24/AIN0
P23/IC11
P22/IC10
P21/IC01
P20/IC00
P17/WI7
P16/WI6
P15/WI5
P14/WI4
P13/WI3
P12/WI2
P11/WI1
P10/WI0
P07
P06/INT6
P05/INT5
P04/INT4
P03/INT3
P02/INT2
P01/INT1
P00/INT0
VCC
X1
X0
VSS
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
RST
MD0
MD1
MD2
HST
V3
V2
V1
V0
P97/SEG31
P96/SEG30
P95/SEG29
P94/SEG28
P93/SEG27
P92/SEG26
P91/SEG25
X0A
X1A
P90/SEG24
P87/SEG23
P86/SEG22
P85/SEG21
P84/SEG20
P83/SEG19
P82/SEG18
P81/SEG17
P80/SEG16
VSS
P77/COM3
P76/COM2
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PA6/SEG14
PA7/SEG15
VSS
C
P50/SIN2/AIN1
P51/SOT2/BIN1
P52/SCK2/ZIN1
DVCC
DVSS
P53/DA0
P54/DA1
AVCC
AVRH
AVRL
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
VCC
P70/TI0/OUT4
P71/TO0/OUT5
P72/TI1/OUT6
P73/TO1/OUT7
P74/COM0
P75/COM1
P31/CKOT
P32/OUT0
P33/OUT1
P34/OUT2
P35/OUT3
P36/PG00
P37/PG01
VCC
P40/PG10
P41/PG11
P42/SIN0
P43/SOT0
P44/SCK0
P45/SIN1
P46/SOT1
P47/SCK1
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
PA0/SEG8
PA1/SEG9
PA2/SEG10
PA3/SEG11
PA4/SEG12
PA5/SEG13
(FPT-120P-M05)
(FPT-120P-M13)
7
MB90520A/520B Series
■ PIN DESCRIPTIONS
Pin No.
LQFP-120*1
QFP-120*2
Pin Name
Circuit
Type
92, 93
X0, X1
A
Oscillator pin
74, 73
X0A, X1A
B
Sub-oscillator pin
89 to 87
MD0 to
MD2
C
Input pins for setting the operation mode.
Connect directly to VCC or VSS.
90
RST
C
External reset input pin
86
HST
C
Hardware standby input pin
D
General-purpose I/O ports
The settings in the pull-up resistor setup register (RDR0) are enabled
when ports are set as inputs.
The RDR0 settings are ignored when ports are set as outputs.
95 to 101
P00 to
P06
INT0 to
INT6
102
103 to 110
P07
P10 to
P17
Event input pins for ch.0 to ch.6 of the DTP/external interrupt circuit
D
D
WI0 to
WI7
IC00, IC01,
IC10, IC11
AIN0
E
BIN0
ZIN0
INT7
Also can be used as the count clock A input to 8/16-bit up/down counter/
timer 0.
General-purpose I/O port
E
P26
117
Trigger input pins for input capture units (ICU) 0 and 1.
Input operates continuously when channels 0 and 1 of input capture units
(ICU) 0 and 1 are operating. Accordingly, output to the pins from other functions that share this pin must be suspended unless performed intentionally.
General-purpose I/O port
E
P25
116
General-purpose I/O ports
The settings in the pull-up resistor setup register (RDR1) are enabled when
ports are set as inputs.
The RDR1 settings are ignored when ports are set as outputs.
General-purpose I/O ports
P24
115
General-purpose I/O port
The settings in the pull-up resistor setup register (RDR0) are enabled when
ports are set as inputs.
The RDR0 settings are ignored when ports are set as outputs.
Event input pins for the wakeup interrupts.
P20, P21,
P22, P23
111, 112,
113, 114
Function
Also can be used as the count clock B input to 8/16-bit up/down counter/
timer 0.
General-purpose I/O port
E
Also can be used as the control clock Z input to 8/16-bit up/down counter/
timer 0.
Event input pin for ch.7 of the DTP/external interrupt circuit
*1 : FPT-120P-M05
*2 : FPT-120P-M13
(Continued)
8
MB90520A/520B Series
Pin No.
LQFP-120*1
QFP-120*2
Pin Name
Circuit
Type
P27
118
ADTG
120
P30
General-purpose I/O port
E
E
P31
1
CKOT
E
E
OUT0
P33
3
E
OUT1
P34
4
E
OUT2
P35
5
E
OUT3
P36
6
E
PG00
P37
7
E
PG01
External trigger input to the 8/10-bit A/D converter
Input operates continuously when the 8/10-bit A/D converter is performing
input. Accordingly, output to the pin from other functions that share this
pin must be suspended unless performed intentionally.
General-purpose I/O port
General-purpose I/O port
P32
2
Function
Output pin for clock monitor function
The clock monitor is output when clock monitor output is enabled.
General-purpose I/O port
Only available when waveform output from output compare 0 is disabled.
Event output pin for ch.0 of output compare unit 0 (OCU)
Only available when event output is enabled for output compare unit 0.
General-purpose I/O port
Only available when waveform output from output compare 1 is disabled.
Event output pin for ch.1 of output compare unit 0 (OCU)
Only available when event output is enabled for output compare unit 0.
General-purpose I/O port
Only available when waveform output from output compare 2 is disabled.
Event output pin for ch.2 of output compare unit 0 (OCU)
Only available when event output is enabled for output compare unit 0.
General-purpose I/O port
Only available when waveform output from output compare 3 is disabled.
Event output pin for ch.3 of output compare unit 0 (OCU)
Only available when event output is enabled for output compare unit 0.
General-purpose I/O port
Only available when waveform output from PG00 is disabled.
Output pin for 8/16-bit PPG timer 0
Only available when waveform output is enabled for PG00.
General-purpose I/O port
Only available when waveform output from PG01 is disabled.
Output pin for 8/16-bit PPG timer 0
Only available when waveform output is enabled for PG01.
*1 : FPT-120P-M05
*2 : FPT-120P-M13
(Continued)
9
MB90520A/520B Series
Pin No.
LQFP-120*1
QFP-120*2
Pin Name
P40, P41
9, 10
Circuit
Type
D
PG10,
PG11
General-purpose I/O ports
Only available when waveform outputs from PG10 and PG11 are disabled.
The settings in the pull-up resistor setup register (RDR4) are enabled
when ports are set as inputs. The RDR4 settings are ignored when ports
are set as outputs.
Output pins for 8/16-bit PPG timer 1
Only available when waveform output is enabled for PG10 and PG11.
P42
11
Function
D
General-purpose I/O port
The settings in the pull-up resistor setup register (RDR4) are enabled
when ports are set as inputs. The RDR4 settings are ignored when ports
are set as outputs.
SIN0
UART (SCI) serial data input pin
Input operates continuously when the UART is performing input.
Accordingly, output to the pin from other functions that share this pin must
be suspended unless performed intentionally.
P43
General-purpose I/O port
The settings in the pull-up resistor setup register (RDR4) are enabled
when ports are set as inputs. The RDR4 settings are ignored when ports
are set as outputs.
12
D
UART (SCI) serial data output pin
Only available when serial data output is enabled for the UART (SCI) .
SOT0
P44
13
D
General-purpose I/O port
The settings in the pull-up resistor setup register (RDR4) are enabled
when ports are set as inputs. The RDR4 settings are ignored when ports
are set as outputs.
SCK0
UART (SCI) serial clock input/output pin
Only available when serial clock output is enabled for the UART (SCI) .
P45
General-purpose I/O port
The settings in the pull-up resistor setup register (RDR4) are enabled
when ports set as inputs. The RDR4 settings are ignored when ports set
are as outputs.
14
D
SIN1
Data input pin for extended I/O serial interface 1
Input operates continuously when the performing serial input. Accordingly,
output to the pin from other functions that share this pin must be
suspended unless performed intentionally.
P46
General-purpose I/O port
The settings in the pull-up resistor setup register (RDR4) are enabled
when ports set as inputs. The RDR4 settings are ignored when ports are
set as outputs.
15
D
SOT1
Data output pin for extended I/O serial interface 1
Only available when serial data output is enabled for SOT1.
*1 : FPT-120P-M05
*2 : FPT-120P-M13
(Continued)
10
MB90520A/520B Series
Pin No.
LQFP-120*1
QFP-120*2
Pin Name
Circuit
Type
P47
16
D
P50
General-purpose I/O port
SIN2
Data input pin for extended I/O serial interface 2
Input operates continuously when the performing serial input.
Accordingly, output to the pin from other functions that share this pin must
be suspended unless performed intentionally.
Also can be used as the count clock A input to 8/16-bit up/down counter/
timer 1.
P51
General-purpose I/O port
E
Also can be used as the count clock B input to 8/16-bit up/down counter/
timer 1.
P52
General-purpose I/O port
E
P53, P54
DA0, DA1
I
P60 to P67
46 to 53
K
AN0 to
AN7
P70, P72
55, 57
TI0, TI1
OUT4,
OUT6
Serial clock input/output pin for extended I/O serial interface 2
Only available when serial clock output is enabled for SCK2.
Also can be used as the control clock Z input to 8/16-bit up/down counter/
timer 1.
ZIN1
40, 41
Data output pin for extended I/O serial interface 2
Only available when serial data output is enabled for SOT2.
BIN1
SCK2
37
E
AIN1
SOT2
36
General-purpose I/O port
The settings in the pull-up resistor setup register (RDR4) are enabled
when ports are set as inputs. The RDR4 settings are ignored when ports
are set as outputs.
Serial clock input/output pin for extended I/O serial interface 1
Only available when serial clock output is enabled for SCK1.
SCK1
35
Function
General-purpose I/O ports
Analog output pins for ch.0 and ch.1 of the 8-bit D/A converter
General-purpose I/O ports
Port input is enabled when the analog input enable register (ADER) is set
to the ports.
Analog inputs for the 8/10-bit A/D converter
Analog input is enabled when the analog input enable register (ADER) is
set.
General-purpose I/O ports
E
Event input pins for 16-bit reload timers 0 and 1
Input operates continuously when 16-bit reload timers 0 and 1 input an
external clock. Accordingly, output to these pins from other functions that
share the pins must be suspended unless performed intentionally.
Event output pins for ch. 4 and ch. 6 of output compare unit 1 (OCU)
Only available when event output from output compare 1 is enabled.
*1 : FPT-120P-M05
*2 : FPT-120P-M13
(Continued)
11
MB90520A/520B Series
Pin No.
LQFP-120*1
QFP-120*2
Pin Name
Circuit
Type
General-purpose I/O ports
Only available when event outputs from 16-bit reload timers 0 and 1 are
disabled.
P71, P73
56, 58
TO0, TO1
E
OUT5,
OUT7
L
17 to 24
General-purpose I/O ports
Only available when the LCD controller/driver control register is set to the
ports.
COM0 to
COM3
Common pins for the LCD controller/driver
Only available when the LCD controller/driver control register is set to the
common outputs.
P80 to P87
General-purpose I/O ports
Only available when the LCD controller/driver control register is set to the
ports.
64 to 71
72,
75 to 81
Output pins for 16-bit reload timers 0 and 1.
Only available when output is enabled for 16-bit reload timers 0 and 1.
Event output pins for ch. 5 and ch. 7 of output compare unit 1 (OCU)
Only available when event output from output compare 1 is enabled.
P74 to P77
59 to 62
Function
L
SEG16 to
SEG23
LCD segment output pins for the LCD controller/driver
Only available when the LCD controller/driver control register is set to the
segment outputs.
P90,
P91 to P97
General-purpose I/O ports (Support up to IOL = 10 mA)
Only available when the LCD controller/driver control register is set to the
ports.
SEG24,
SEG25 to
SEG31
SEG0 to
SEG7
M
F
PA0 to PA7
25 to 32
L
SEG8 to
SEG15
LCD segment output pins for the LCD controller/driver
Only available when the LCD controller/driver control register is set to the
segment outputs.
LCD segment 00 to 07 pins for the LCD controller/driver
General-purpose I/O ports
Only available when the LCD controller/driver control register is set up to
the ports.
LCD segment 08 to 15 pins for the LCD controller/driver
Only available when the LCD controller/driver control register is set to the
segment outputs.
*1 : FPT-120P-M05
*2 : FPT-120P-M13
(Continued)
12
MB90520A/520B Series
(Continued)
Pin No.
LQFP-120*1
QFP-120*2
Pin Name
Circuit
Type
Function
34
C
G
Capacitor connection pin for stabilizing power supply
Connect an external ceramic capacitor of approximately 0.1 µF. If operating at 3.3 V or lower, connect to VCC.
82 to 85
V0 to V3
N
Power supply input pins for the LCD controller/driver
8, 54, 94
VCC
Power
Power supply input pins for the digital circuit
supply
33, 63, 91, 119
VSS
Power
GND level power supply input pins for the digital circuit
supply
42
AVCC
H
Power supply input for the analog circuit
Ensure that a voltage greater than AVCC is applied to VCC before turning
the analog power supply on or off.
43
AVRH
J
“H” reference voltage for the A/D converter
Ensure that a voltage greater than AVRH is applied to AVCC before turning
the power supply to this pin on or off.
44
AVRL
H
“L” reference voltage for the A/D converter
45
AVSS
H
GND level power supply input pin for the analog circuit
38
DVCC
H
“H” reference voltage for the D/A converter
Ensure that this voltage does not exceed VCC.
39
DVSS
H
“L” reference voltage for the D/A converter
Apply the same voltage level as VSS.
*1 : FPT-120P-M05
*2 : FPT-120P-M13
13
MB90520A/520B Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
X0
Clock input
Nch Pch
X1
• High-speed oscillation feedback
resistor
Approx. 1 MΩ
Pch
A
Nch
Standby control signal
X0A
Clock input
Nch Pch
X1A
• Low-speed oscillation feedback
resistor
Approx. 10 MΩ
Pch
B
Nch
Standby control signal
• Hysteresis input
R
Hysteresis input
C
Pch
VCC
Pch
Pull-up connect/
disconnect selection
signal
•
•
•
•
Selectable pull-up option
CMOS hysteresis input
CMOS level output
With standby control
Digital output
D
Nch
Digital output
VSS
R
Hysteresis input
IOL = 4 mA
Standby control
VCC
Pch
E
R
Nch
VSS
Digital output
• CMOS hysteresis input
• CMOS level output
• With standby control
Digital output
Hysteresis input
IOL = 4 mA
Standby control
(Continued)
14
MB90520A/520B Series
Type
Circuit
Remarks
• Segment output pins
VCC
R
F
Nch
VSS
• Capacitor connection pin
(This is an N.C. pin on the
MB90522A and MB90523A.)
VCC
Pch
G
Nch
VSS
• Analog power supply input
protection circuit
VCC
Pch
H
AVP
Nch
VSS
VCC
Pch
Nch
I
IOL = 4 mA
R
Digital output
Digital output
VSS
• CMOS hysteresis input
• CMOS level output
(CMOS output is not available when
analog output is operating.)
• Also used as analog output
(Analog output has priority)
• With standby control
Hysteresis input
Standby control
Analog output
VCC
Pch
Pch
J
ANE
AVP
Nch
Nch
VSS
• A/D converter ref+ power supply
input pin
(Incorporates power supply
protection circuit.)
ANE
(Continued)
15
MB90520A/520B Series
(Continued)
Type
Circuit
VCC
Pch
Nch
K
Remarks
Digital output
•
•
•
•
CMOS hysteresis input
CMOS level output
Also used as analog input.
With standby control
•
•
•
•
CMOS hysteresis input
CMOS level output
Also used as segment output pin.
With standby control
(only available when segment
output is not operating.)
•
•
•
•
CMOS hysteresis input
N-ch open-drain output
Also used as segment output pin.
With standby control
(only available when segment
output is not operaing.)
Digital output
VSS
IOL = 4 mA
R
Hysteresis input
Standby control
Analog input
VCC
Pch
L
IOL = 4 mA
R
Nch
VSS
Digital output
Digital output
Hysteresis input
Standby control
Segment output/common output
VCC
Pch
Nch
M
Open drain
VSS
IOL = 10 mA
R
Hysteresis input
Standby control
Segment output
VCC
Pch
R
N
IOL = 10 mA
16
Nch
VSS
• Reference voltage pin for LCD
controller
MB90520A/520B Series
■ HANDLING DEVICES
Take note of the following points when handling devices :
• Do not exceed maximum rated voltage (to prevent latch-up)
• Supply voltage stability
• Power-on precautions
• Power supply pins
• Crystal oscillator circuit
• Notes on using an external clock
• Precautions when not using sub-clock mode
• Treatment of unused pins
• Treatment of N.C. pins
• Treatment of pins when A/D converter is not used
• Sequence for connecting and disconnecting the A/D converter power supply and analog input pins
• Shared use of general-purpose I/O ports and LCD controller/driver SEG/COM pins
• Conditions when output from ports 0 and 1 is undefined
• Initialization
• Notes on using the DIV A, Ri and DIVW A, RWi instructions
• Notes on using REALOS
Device Handling Precautions
• Do not exceed maximum rated voltage (to prevent latch-up)
Latch-up occurs in CMOS ICs if a voltage greater than VCC or less than VSS is applied to an input or output pin
(other than a high or medium withstand voltage pin) or if the voltage applied between VCC and VSS exceeds
the rating. If latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit
elements. Therefore, ensure that maximum ratings are not exceeded in circuit operation.
Similarly, when turning the analog power supply on or off, ensure the analog power supply voltages (AVCC,
AVRH, DVCC) and analog input voltages do not exceed the digital voltage (VCC) .
Also ensure that the voltages applied to the LCD power supply pins (V3 to V0) do not exceed the power supply
voltage (VCC) .
• Supply voltage stability
Rapid changes in supply voltage may cause the device to misoperate, even if the voltage remains within the
allowed operating range. Accordingly, ensure that the VCC supply is stable.
The standard for power supply voltage stability is a peak-to-peak VCC ripple voltage at the mains supply
frequency (50 to 60 Hz) of 10% or less of VCC and a transient voltage change rate of 0.1 V/ms or less when
turning the power supply on or off.
• Power-on precautions
To prevent misoperation of the internal regulator circuit at power-on, ensure that the power supply rising time
(0.2 V to 2.7 V) is at least 50 µs.
• Power supply pins
When multiple VCC and VSS pins are provided, connect all VCC and VSS pins to power supply or ground externally.
Although pins at the same potential are connected together in the internal device design so as to prevent
misoperation such as latch-up, connecting all VCC and VSS pins appropriately minimizes unwanted radiation,
prevents misoperation of strobe signals due to increases in the ground level, and keeps the overall output
current rating.
Also, ensure that the impedance of the VCC and VSS connections to the power supply are as low as possible.
17
MB90520A/520B Series
Connection of a bypass capacitor of approximately 0.1 µF between VCC and VSS is recommended to prevent
power supply noise. Connect the capacitor close to the VCC and VSS pins.
• Crystal oscillator circuit
Noise on the X0 and X1 pins can be a cause of device misoperation. Place the X0 and X1 pins, crystal oscillator
(or ceramic oscillator) , and bypass capacitor to ground as close together as possible. Also, design the circuit
board so that the X0 and X1 pin wiring does not cross other wiring.
Surrounding the X0/X1 and X0A/X1A pins with ground in the printed circuit board design is recommended to
ensure stable operation.
• Notes on using an external clock
When using an external clock, drive the X0 pin only and leave the X1 pin open.
The figure below shows an example of how to use an external clock.
Example of how to use an external clock
X0
Open circuit
X1
MB90520A/520B series
• Precautions when not using sub-clock mode
Connect an oscillator to X0A and X1A, even if not using sub-clock mode.
• Treatment of unused pins
Leaving unused input pins unconnected can cause misoperation or permanent damage to the device due to
latchup. Always pull-up or pull-down unused pins using a 2 kΩ or larger resistor.
If some I/O pins are unused, either set as outputs and leave open circuit or set as inputs and treat in the same
way as input pins.
• Treatment of N.C. pins
Always leave N.C. (non connect) pins open circuit.
• Treatment of pins when A/D converter not used
When not using the A/D converter and D/A converter, always connect AVCC = DVCC = AVRH = VCC and AVSS =
AVRL = VSS.
• Sequence for connecting and disconnecting the A/D converter power supply and analog input pins
Do not apply voltage to the A/D and D/A converter power supply (AVCC, AVRH, AVRL, DVCC, DVSS) or analog
inputs (AN0 to AN7) until the digital power supply (VCC) is turned on.
When turning the device off, turn off the digital power supply after disconnecting the A/D converter power
supply and analog inputs. When turning the power on or off, ensure that AVRH and DVCC do not exceed AVCC
(turning the analog and digital power supplies on and off simultaneously is OK) .
• Shared use of general-purpose I/O ports and LCD controller/driver SEG/COM pins
The SEG08 to SEG31 and COM0 to COM3 pins are shared with general-purpose I/O ports. The electrical
ratings for SEG08 to SEG23 and COM0 to COM3 are the same as for CMOS outputs and the electrical ratings
for SEG24 to SEG31 are the same as for N-ch open-drain ports.
18
MB90520A/520B Series
• Conditions when output from ports 0 and 1 is undefined
After turning on the power supply, the outputs from ports 0 and 1 are undefined during the oscillation stabilization delay time controlled by the regulator circuit (during the power-on reset) . The figure below shows the
timing.
Note that this undefined output period does not occur on products without an internal regulator circuit as these
products do not have an oscillation stabilization delay time.
Timing chart for undefined output from ports 0 and 1
Oscillation stabilization delay time*2
Regulator circuit stabilization
delay time*1
VCC (Power supply pin)
PONR (Power-on reset) signal
RST (External asynchronous reset) signal
RST (Internal reset) signal
Oscillation clock signal
KA (Internal operating clock A) signal
KB (Internal operating clock B) signal
PORT (port output) signal
Undefined output time
*1 : Regulator circuit oscillation stabilization delay time : 217/Oscillation clock frequency
(approx. 8.19 ms for a 16 MHz oscillation clock frequency)
*2 : Oscillation stabilization delay time : 218/Oscillation clock frequency
(approx. 16.38 ms for a 16 MHz oscillation clock frequency)
Note : See the “■ PRODUCT LINEUP” section for details of which MB90520A/520B series products have an internal
regulator circuit.
• Initialization
The device contains internal registers that are only initialized by a power-on reset. To initialize these registers,
restart the power supply.
• Notes on using the DIV A, Ri and DIVW A, RWi instructions
Set the corresponding bank registers (DTB, ADB, USB, SSB) to “00H” when using the signed division instructions “DIV A, Ri” and “DIVW A, RWi”.
If the corresponding bank registers (DTB, ADB, USB, SSB) are set to other than “00H”, the remainder value
produced by the instruction is not stored in the instruction operand register.
• Notes on using REALOS
The extended intelligent I/O service (EI2OS) cannot be used when using REALOS.
Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
19
MB90520A/520B Series
• BLOCK DIAGRAM
8
Ports 8, 9*3, A
24
F2MC-16LX
CPU
X0, X1
X0A, X1A
Main clock
Sub-clock
RST
HST
LCD
controller/
driver
Clock controller*1
(Includes
timebase timer)
4
8
8
8
4
4
P80/SEG16 to P87/SEG23
P90/SEG24 to P97/SEG31
PA0/SEG08 to PA7/SEG15
SEG00 to SEG07
V0 to V3
P74/COM0 to P77/COM3
Port 7
16-bit
reload
timer 0
Port 0*2
P07
P00/INT0 to P06/INT6
7
7
DTP/
external
interrupt
circuit
16-bit
reload
timer 1
16-bit
I/O timer 2
Port 2
3
8/16-bit
up/down
counter/
timer 0, 1
16-bit
I/O timer 1
P20/IC00
P21/IC01
P22/IC10
P23/IC11
2
Input
capture 0
(ICU)
16-bit
freerun
timer 0
P32/OUT0
P33/OUT1
P34/OUT2
P35/OUT3
4
P30
P36/PG00
P37/PG01
16-bit
freerun
timer 1
Port 6
8
Output
compare 0
(OCU)
Clock
output
P31/CKOT
Output 4
compare 1
(OCU)
Internal data bus
P24/AIN0
P25/BIN0
P26/ZIN0/INT7
P70/TI0/OUT4
P71/TO0/OUT5
P72/TI1/OUT6
P73/TO1/OUT7
8/10-bit
A/D
converter
Port 3
8/16-bit
PPG
2
timer 0, 1
P42/SIN0
P43/SOT0
P44/SCK0
UART
(SCI)
P45/SIN1
P46/SOT1
P47/SCK1
SIO ch.1
Interrupt controller
Port 5
SIO ch.2
Port 1*2
Other pins
MD0 to MD2, C,
VCC, VSS
8
8
AVCC
AVSS
AVRH
AVRL
Port 2
Port 4*2
P10/WI0 to P17/WI7
P60/AN0 to P67/AN7
P27/ADTG
2
P40/PG10
P41/PG11
8
Wakeup
interrupts
2
8-bit
D/A
converter
× 2 ch
P50/SIN2/AIN1
P51/SOT2/BIN1
P52/SCK2/ZIN1
P53/DA0
P54/DA1
DVCC
DVSS
RAM
ROM
*1 : The clock control circuit includes the watchdog timer and timebase timer low power consumption control
circuits.
*2 : Incorporates a pull-up register setting register. CMOS level input and output.
*3 : As this port shares pins with the LCD output, the port uses N-ch open-drain circuits.
20
MB90520A/520B Series
■ MEMORY MAP
Single chip mode with mirror function
FFFFFFH
ROM area
Address #1
FE0000H
010000H
Address #2
ROM area
(image of
FF bank)
004000H
002000H
Address #3
RAM
000100H
0000C0H
000000H
Registers
Peripherals
Part No.
Address #1*
Address #2*
Address #3*
MB90522A/B
FF0000H
004000H
001100H
MB90523A/B
FE0000H
004000H
001100H
MB90F523B
FE0000H
004000H
001100H
MB90V520A


001900H
: Internal memory access
: Access prohibited
* : The values of addresses #1, #2, and #3 vary by product.
Note : The upper part of 00 bank contains a mirror of the ROM data in FF bank. This is called the mirror ROM
function and enables use of the C compiler’s small memory model. As the lower 16 bits of the FF bank and
00 bank addresses are the same, tables located in ROM can be referenced without needing to declare far
pointers.
For example, accessing 00C000H actually accesses the contents of ROM at FFC000H. Note that, as the FF
bank ROM area exceeds 48 KBytes, the entire ROM image cannot be mirrored in 00 bank. Accordingly, as
ROM data from FF4000H to FFFFFFH is mirrored in 004000H to 00FFFFH, always locate ROM data tables in
the range FF4000H to FFFFFFH.
21
MB90520A/520B Series
■ I/O MAP
Address
Abbreviated
Register
Name
000000H
PDR0
000001H
Peripheral Name
Initial Value
Port 0 data register
Port 0
XXXXXXXXB
PDR1
Port 1 data register
Port 1
XXXXXXXXB
000002H
PDR2
Port 2 data register
Port 2
XXXXXXXXB
000003H
PDR3
Port 3 data register
Port 3
XXXXXXXXB
000004H
PDR4
Port 4 data register
Port 4
XXXXXXXXB
000005H
PDR5
Port 5 data register
Port 5
XXXXXXXXB
000006H
PDR6
Port 6 data register
Port 6
XXXXXXXXB
000007H
PDR7
Port 7 data register
Port 7
XXXXXXXXB
000008H
PDR8
Port 8 data register
Port 8
XXXXXXXXB
000009H
PDR9
Port 9 data register
Port 9
XXXXXXXXB
00000AH
PDRA
Port A data register
Port A
XXXXXXXXB
00000BH
LCDCMR
Port 7,
LCD controller/driver
XXXX 0 0 0 0B
00000CH
00000DH
OCP4
Register Name
Port 7/COM pin selection register
OCU compare register ch.4
00000EH
16-bit I/O timer
XXXXXXXXB
XXXXXXXXB
(Access prohibited)
00000FH
EIFR
Wakeup interrupt flag register
000010H
DDR0
000011H
Wakeup interrupts
XXXXXXX0B
Port 0 direction register
Port 0
0 0 0 0 0 0 0 0B
DDR1
Port 1 direction register
Port 1
0 0 0 0 0 0 0 0B
000012H
DDR2
Port 2 direction register
Port 2
0 0 0 0 0 0 0 0B
000013H
DDR3
Port 3 direction register
Port 3
0 0 0 0 0 0 0 0B
000014H
DDR4
Port 4 direction register
Port 4
0 0 0 0 0 0 0 0B
000015H
DDR5
Port 5 direction register
Port 5
XXX 0 0 0 0 0B
000016H
DDR6
Port 6 direction register
Port 6
0 0 0 0 0 0 0 0B
000017H
DDR7
Port 7 direction register
Port 7
0 0 0 0 0 0 0 0B
000018H
DDR8
Port 8 direction register
Port 8
0 0 0 0 0 0 0 0B
000019H
DDR9
Port 9 direction register
Port 9
0 0 0 0 0 0 0 0B
00001AH
DDRA
Port A direction register
Port A
0 0 0 0 0 0 0 0B
00001BH
ADER
Analog input enable register
Port 6, A/D converter
1 1 1 1 1 1 1 1B
OCP5
OCU compare register ch.5
16-bit I/O timer
00001CH
00001DH
00001EH
00001FH
XXXXXXXXB
XXXXXXXXB
(Access prohibited)
EICR
Wakeup interrupt enable register
Wakeup interrupts
0 0 0 0 0 0 0 0B
(Continued)
22
MB90520A/520B Series
Address
Abbreviated
Register
Name
000020H
SMR
Serial mode register
000021H
SCR
Serial control register
000022H
SIDR/
SODR
000023H
SSR
000024H
000025H
SMCS1
Register Name
Serial status register
CDCR
Communication prescaler control
register
SMCS2
Serial mode control status register 2
00002CH
00002DH
00002EH
00002FH
OCS45
OCS67
OCU control status register ch.67
DTP/interrupt request register
ELVR
Request level setting register
OCP6
OCU compare register ch.6
ADCS
A/D control status register
000037H
000038H
A/D data register
00003AH
DADR0
D/A converter data register ch.0
00003BH
DADR1
D/A converter data register ch.1
00003CH
DACR0
D/A control register 0
00003DH
DACR1
D/A control register 1
00003EH
CLKR
Clock output enable register
XXX 0 0 0 0 0B
0 0 0 0 XX 0 0B
XXX 0 0 0 0 0B
0 0 0 0 0 0 0 0B
DTP /external interrupt
circuit
XXXXXXXXB
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
16-bit I/O timer
XXXXXXXXB
XXXXXXXXB
0 0 0 0 0 0 0 0B
8/10-bit A/D converter
ADCR
000039H
0 0 0 0 0 0 1 0B
0 0 0 0 XX 0 0B
16-bit I/O timer
EIRR
000036H
XXXX 0 0 0 0B
Extended I/O serial
interface 2
OCU control status register ch.45
000031H
000035H
0 XXX 1 1 1 1B
(Access prohibited)
DTP/interrupt enable register
000034H
Communication prescaler
register
XXXXXXXXB
ENIR
000033H
0 0 0 0 0 0 1 0B
XXXXXXXXB
000030H
000032H
Extended I/O serial
interface 1
Serial data register 2
00002BH
XXXXXXXXB
XXXX 0 0 0 0B
Serial mode control status register 1
000027H
SDR2
0 0 0 0 0 1 0 0B
0 0 0 0 1 X 0 0B
Serial data register 1
00002AH
UART
(SCI)
Serial input data register/
Serial output data register
SDR1
000029H
Initial Value
0 0 0 0 0 0 0 0B
000026H
000028H
Peripheral Name
0 0 0 0 0 0 0 0B
XXXXXXXXB
0 0 0 0 1 XXXB
XXXXXXXXB
8-bit D/A converter
XXXXXXXXB
XXXXXXX 0B
XXXXXXX 0B
Clock monitor function
XXXX 0 0 0 0B
(Continued)
23
MB90520A/520B Series
Address
Abbreviated
Register
Name
Register Name
00003FH
Peripheral Name
Initial Value
(Access prohibited)
000040H
PRLL0
PPG0 reload register L
XXXXXXXXB
000041H
PRLH0
PPG0 reload register H
XXXXXXXXB
000042H
PRLL1
PPG1 reload register L
XXXXXXXXB
000043H
PRLH1
PPG1 reload register H
000044H
PPGC0
PPG0 operation mode control register
0 X 0 0 0 XX 1B
000045H
PPGC1
PPG1 operation mode control register
0 X 0 0 0 0 0 1B
000046H
PPGOE
PPG0, 1 output control register
0 0 0 0 0 0 0 0B
000047H
000048H
000049H
00004AH
00004BH
00004CH
00004DH
00004EH
00004FH
000050H
000051H
000052H
000053H
000054H
000057H
000058H
TMCSR0
00005BH
00005CH
00005DH
00005EH
00005FH
0 0 0 0 0 0 0 0B
Timer control status register ch.0
16-bit reload timer 0
TMR0/
TMRLR0
16-bit timer register ch.0/
16-bit reload register ch.0
TMCSR1
Timer control status register ch.1
TMR1/
TMRLR1
XXXX 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
0 0 0 0 0 0 0 0B
16-bit reload timer 1
16-bit timer register ch.1/
16-bit reload register ch.1
XXXX 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
IPCP0
ICU data register ch.0
IPCP1
ICU data register ch.1
ICS01
ICU control status register
XXXXXXXXB
16-bit I/O timer
XXXXXXXXB
XXXXXXXXB
0 0 0 0 0 0 0 0B
(Access prohibited)
TCDT0
Freerun timer data register 0
TCCS0
Freerun timer control status register 0
000059H
00005AH
XXXXXXXXB
(Access prohibited)
000055H
000056H
8/16-bit PPG timer 0, 1
0 0 0 0 0 0 0 0B
16-bit I/O timer
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
(Access prohibited)
OCP0
OCU compare register ch.0
OCP1
OCU compare register ch.1
OCP2
OCU compare register ch.2
XXXXXXXXB
XXXXXXXXB
16-bit I/O timer
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
(Continued)
24
MB90520A/520B Series
Address
000060H
000061H
000062H
000063H
000064H
000065H
000066H
000067H
000068H
Abbreviated
Register
Name
Register Name
OCU compare register ch.3
OCS01
OCU control status register ch.0, ch.1
OCS23
OCU control status register ch.2, ch.3
TCDT1
Freerun timer data register 1
TCCS1
Freerun timer control status register 1
XXXXXXXXB
16-bit I/O timer
0 0 0 0 XX 0 0B
XXX 0 0 0 0 0B
0 0 0 0 XX 0 0B
XXX 0 0 0 0 0B
0 0 0 0 0 0 0 0B
16-bit I/O timer
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
(Access prohibited)
00006AH
LCR0
LCDC control register 0
00006BH
LCR1
LCDC control register 1
OCP7
OCU compare register ch.7
00006DH
Initial Value
XXXXXXXXB
OCP3
000069H
00006CH
Peripheral Name
00006EH
LCD controller/driver
16-bit I/O timer
0 0 0 1 0 0 0 0B
0 0 0 0 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
(Access prohibited)
00006FH
ROMM
ROM mirror function selection register
ROM mirror function
selection module
XXXXXXX1B
000070H
to
00007FH
VRAM
Data memory for LCD display
LCD controller/driver
XXXXXXXXB
000080H
UDCR0
Up/down count register 0
000081H
UDCR1
Up/down count register 1
000082H
RCR0
Reload compare register 0
000083H
RCR1
Reload compare register 1
000084H
CSR0
Counter status register 0
000085H
000086H
000087H
000088H
CCR0
Counter control register 0
CSR1
Counter status register 1
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
*3
X 0 0 0 0 0 0 0B
8/16-bit up/down
counter/timer 0, 1
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
(Reserved)
*3
8/16-bit up/down
counter/timer 0, 1
X 0 0 0 0 0 0 0B
Port 0
input pull-up resistor setup register
Port 0
0 0 0 0 0 0 0 0B
Port 1
input pull-up resistor setup register
Port 1
0 0 0 0 0 0 0 0B
CCR1
Counter control register 1
00008CH
RDR0
00008DH
RDR1
00008BH
0 0 0 0 0 0 0 0B
8/16-bit up/down
counter/timer 0, 1
(Reserved)
000089H
00008AH
0 0 0 0 0 0 0 0B
X 0 0 0 0 0 0 0B
(Continued)
25
MB90520A/520B Series
Address
Abbreviated
Register
Name
00008EH
RDR4
00008FH
to
00009DH
Register Name
Port 4
input pull-up resistor setup register
Peripheral Name
Initial Value
Port 4
0 0 0 0 0 0 0 0B
(Access prohibited)
(Area reserved for system use) *4
00009EH
PACSR
00009FH
DIRR
Delayed interrupt request output/clear
register
0000A0H
LPMCR
Low power consumption mode control
register
0000A1H
CKSCR
Clock selection register
0000A2H
to
0000A7H
Address detection control register
Address match detection
function
0 0 0 0 0 0 0 0B
Delayed interrupt
generation module
XXXXXXX 0B
Low power consumption
(standby) mode
0 0 0 1 1 0 0 0B
1 1 1 1 1 1 0 0B
(Access prohibited)
0000A8H
WDTC
Watchdog timer control register
Watchdog timer
XXXXXXXXB
0000A9H
TBTC
Timebase timer control register
Timebase timer
1 XX 0 0 0 0 0B
0000AAH
WTC
Clock timer control register
Clock timer
1 X 0 0 1 0 0 0B
1 Mbit flash memory
0 0 0 X 0 0 0 0B
0000ABH
to
0000ADH
0000AEH
(Access prohibited)
FMCS
0000AFH
Flash memory control status register
(Access prohibited)
0000B0H
ICR00
Interrupt control register 00
0 0 0 0 0 1 1 1B
0000B1H
ICR01
Interrupt control register 01
0 0 0 0 0 1 1 1B
0000B2H
ICR02
Interrupt control register 02
0 0 0 0 0 1 1 1B
0000B3H
ICR03
Interrupt control register 03
0 0 0 0 0 1 1 1B
0000B4H
ICR04
Interrupt control register 04
0 0 0 0 0 1 1 1B
0000B5H
ICR05
Interrupt control register 05
0 0 0 0 0 1 1 1B
0000B6H
ICR06
Interrupt control register 06
0000B7H
ICR07
Interrupt control register 07
0000B8H
ICR08
Interrupt control register 08
0 0 0 0 0 1 1 1B
0000B9H
ICR09
Interrupt control register 09
0 0 0 0 0 1 1 1B
0000BAH
ICR10
Interrupt control register 10
0 0 0 0 0 1 1 1B
0000BBH
ICR11
Interrupt control register 11
0 0 0 0 0 1 1 1B
0000BCH
ICR12
Interrupt control register 12
0 0 0 0 0 1 1 1B
0000BDH
ICR13
Interrupt control register 13
0 0 0 0 0 1 1 1B
Interrupt controller
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
(Continued)
26
MB90520A/520B Series
(Continued)
Address
Abbreviated
Register
Name
0000BEH
ICR14
Interrupt control register 14
0000BFH
ICR15
Interrupt control register 15
Register Name
Peripheral Name
Interrupt controller
0000C0H
to
0000FFH
(Access prohibited) *1
000100H
to
00####H
(RAM area) *2
00####H
to
001FEFH
(Reserved area) *3
001FF0H
001FF1H
PADR0
Detection address setting register 0
(middle byte)
XXXXXXXXB
001FF3H
Detection address setting register 1
(low byte)
001FF5H
0 0 0 0 0 1 1 1B
XXXXXXXXB
Detection address setting register 0
(high byte)
PADR1
0 0 0 0 0 1 1 1B
Detection address setting register 0
(low byte)
001FF2H
001FF4H
Initial Value
Address match
detection function
XXXXXXXXB
XXXXXXXXB
Detection address setting register 1
(middle byte)
XXXXXXXXB
Detection address setting register 1
(high byte)
XXXXXXXXB
001FF6H
to
001FFFH
(Reserved area) *3
Initial value notation
0
: Initial value of bit is “0”.
1
: Initial value of bit is “1”.
X
: Initial value of bit is undefined.
*1 : Access is prohibited to the address range 0000C0H to 0000FFH. See the “■ MEMORY MAP” section.
*2 : See the “■ MEMORY MAP” section for details of the “ (RAM area) ”.
*3 : “ (Reserved areas) ” are addresses used internally by the system and may not be used.
*4 : The “ (Area reserved for system use) ” contains setting registers used by the evaluation tools.
Notes : • LPMCR, CKSCR, and WDTC are initialized by some types of reset and not by others. The initial values
listed are for the case when the registers are initialized.
• The boundary address “####H” between the “ (RAM area) ” and “ (Reserved area) ” differs depending on
the product. See the “■ MEMORY MAP” section for details.
• OCU compare registers ch.0 to ch.3 use 16-bit freerun timer 0 and OCU compare registers ch.4 to ch.7
use 16-bit freerun timer 1. Note that 16-bit freerun timer 0 is also used by input capture 0 and 1 (ICU) .
27
MB90520A/520B Series
■ INTERRUPTS, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt
EI2OS
Support
Interrupt Vector Interrupt Control Register
No.
Address
ICR
Address
Reset
×
#08
FFFFDCH


INT 9 instruction
×
#09
FFFFD8H


Exception
×
#10
FFFFD4H


#11
FFFFD0H
#12
FFFFCCH
ICR00
0000B0H
#13
FFFFC8H
ICR01
0000B1H
#14
FFFFC4H
#15
FFFFC0H
#16
FFFFBCH
ICR02
0000B2H
Extended I/O serial interface 2
#17
FFFFB8H
DTP2/DTP3
(external interrupt 2/external interrupt 3)
#18
FFFFB4H
ICR03
0000B3H
#19
FFFFB0H
DTP4/DTP5
(external interrupt 4/external interrupt 5)
#20
FFFFACH
ICR04
0000B4H
8/16-bit up/down counter/timer 0
compare match
#21
FFFFA8H
8/16-bit up/down counter/timer 0
overflow, up/down direction change
ICR05
0000B5H
#22
FFFFA4H
#23
FFFFA0H
DTP6/DTP7
(external interrupt 6/external interrupt 7)
#24
FFFF9CH
ICR06
0000B6H
Output compare 1 (OCU) ch.4, ch.5 match
#25
FFFF98H
#26
FFFF94H
ICR07
0000B7H
#27
FFFF90H
#28
FFFF8CH
ICR08
0000B8H
8/16-bit up/down counter/timer 1
compare match
#29
FFFF88H
8/16-bit up/down counter/timer 1
overflow, up/down direction change
ICR09
0000B9H
#30
FFFF84H
Input capture 0 (ICU) capture
#31
FFFF80H
Input capture 1 (ICU) capture
#32
FFFF7CH
ICR10
0000BAH
Output compare 0 (OCU) ch.0 match
#33
FFFF78H
Output compare 0 (OCU) ch.1 match
#34
FFFF74H
ICR11
0000BBH
8/10-bit A/D converter
Timebase timer
×
DTP0/DTP1
(external interrupt 0/external interrupt 1)
16-bit freerun timer 0 overflow
×
Extended I/O serial interface 1
Wakeup interrupt
8/16-bit PPG timer 0 counter borrow
8/16-bit PPG timer 1 counter borrow
Clock timer
×
×
×
×
Output compare 1 (OCU) ch.6, ch.7 match
16-bit freerun timer 1 overflow
×
Priority
High
(Continued)
28
MB90520A/520B Series
(Continued)
Interrupt
EI2OS
Support
Interrupt Vector Interrupt Control Register
No.
Address
Output compare 0 (OCU) ch.2 match
#35
FFFF70H
Output compare 0 (OCU) ch.3 match
#36
FFFF6CH
UART (SCI) receive complete
#37
FFFF68H
16-bit reload timer 0
#38
FFFF64H
UART (SCI) send complete
#39
FFFF60H
16-bit reload timer 1
#40
FFFF5CH
Flash memory
×
#41
FFFF58H
Delayed interrupt generation module
×
#42
FFFF54H
ICR
Address
ICR12
0000BCH
ICR13
0000BDH
ICR14
0000BEH
ICR15
0000BFH
Priority
Low
: Supported
× : Not supported
: Supported, includes EI2OS stop function
29
MB90520A/520B Series
■ PERIPHERAL RESOURCES
1. I/O Ports
• The I/O ports can be used as general-purpose I/O ports (parallel I/O ports) . The MB90520A and 520B series
have 11 ports (85 pins) . The ports share pins with the inputs and outputs of the peripheral functions.
• The port data registers (PDR) are used to output data to the I/O pins and capture the input signals from the
I/O ports.
Similarly, the port direction registers (DDR) set the I/O direction (input or output) for each individual port bit.
• The following tables list the I/O ports and peripheral functions with which they share pins.
Pin Name
Pin Name (Peripheral)
Peripheral Function that Shares Pin
(Port)
Port 0
Port 1
Port 2
P00 − P06
INT0 − INT6

P07
External interrupts
Not shared
P10 − P17
WI0 − WI7
Wakeup interrupts
P20 − P23
IN00 − IN11
Input capture (unit 0)
P24, P25
AIN0, BIN0
8/16-bit up/down counter/timer 0
P26
ZIN0/INT7
8/16-bit up/down counter/timer 0, external interrupt

P30
Not shared
P31
CKOT
Clock monitor function
P32 − P35
OUT0 − OUT3
Output compare (unit 0)
P36, P37
PPG00, PPG01
8/16-bit PPG timer 0
P40, P41
PPG10, PPG11
8/16-bit PPG timer 1
P42 − P44
SIN0, SOT0, SCK0
UART (SCI)
P45 − P47
SIN1, SOT1, SCK1
Extended I/O serial interface 0
P50 − P52
SIN2/AIN1,
SOT1/BIN1,
SCK1/ZIN1
8/16-bit up/down counter/timer 0
Extended I/O serial interface 1
P53, P54
DA0, DA1
8-bit D/A converter
P60 − P67
AN0 − AN7
8/16-bit A/D converter
P70 − P73
TIN0/OUT4,
TOT0/OUT5,
TIN1/OUT6,
TOT1/OUT7
16-bit reload timers 0, 1
Output compare (unit 1)
P74 − P77
COM0 − COM3
LCD control driver common output
Port 8
P80 − P87
SEG16 − SEG23
LCD control driver segment output
Port 9
P90 − P97
SEG24 − SEG31
LCD control driver segment output
Port A
PA0 − PA7
SEG8 − SEG15
LCD control driver segment output
Port 3
Port 4
Port 5
Port 6
Port 7
Notes
• Port 9 contains general-purpose I/O ports with N-ch open-drain output circuits.
• Connect an external pull-up resistor when using port 9 pins as outputs.
• Port 6 shares pins with the analog inputs. When using port 6 as a general-purpose port, ensure that the
corresponding analog input enable register (ADER) bits are set to “0”. ADER is initialized to “FFH” after a reset.
30
MB90520A/520B Series
• Block diagrams
P00 to P07, P10 to P17
Pull-up resistor
option connect/
disconnect setting
Peripheral function input
Internal data bus
PDR (Port data register)
Pch
PDR read
Output latch
Pch
PDR write
Pin
DDR (Port direction register)
Direction latch
Nch
DDR write
Standby control (SPL = 1)
DDR read
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
P20 to P27
Peripheral function input
Internal data bus
PDR (Port data register)
PDR read
Output latch
Pch
PDR write
Pin
DDR (Port direction register)
Direction latch
Nch
DDR write
DDR read
Standby control (SPL = 1)
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
31
MB90520A/520B Series
P40 to P47
Pull-up resistor
option connect/
disconnect setting
Peripheral function input*
PDR (Port data register)
Peripheral function output*
Peripheral function
output approval*
Pch
Internal data bus
PDR read
Pch
Output latch
PDR write
Pin
DDR (Port direction register)
Nch
Direction latch
DDR write
Standby control (SPL = 1)
DDR read
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
* : Peripheral function I/O is equivalent to I/O of peripheral function.
P30 to P37, P50 to P52, P70 to P73
Peripheral function input*
PDR (Port data register)
Peripheral function output*
Peripheral function
output approval*
Internal data bus
PDR read
Output latch
Pch
PDR write
Pin
DDR (Port direction register)
Direction latch
Nch
DDR write
Standby control (SPL = 1)
DDR read
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
* : Peripheral function I/O is equivalent to I/O of peripheral function.
32
MB90520A/520B Series
P53, P54
D/A analog pin
output approval
D/A analog output
PDR (Port data register)
Internal data bus
PDR read
Output latch
Pch
PDR write
Pin
DDR (Port direction register)
Direction latch
Nch
DDR write
Standby control (SPL = 1)
DDR read
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
P74 to P77
Common pin
output approval
LCD common output
PDR (Port data register)
Internal data bus
PDR read
Output latch
Pch
PDR write
Pin
DDR (Port direction register)
Direction latch
Nch
DDR write
Standby control (SPL = 1)
DDR read
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
33
MB90520A/520B Series
P60 to P67
Analog input
PDR (Port data register)
Internal data bus
PDR read
Output latch
Pch
PDR write
Pin
DDR (Port direction register)
Direction latch
Nch
DDR write
Standby control (SPL = 1)
DDR read
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
P80 to P87, PA0 to PA7
Segment pin
output approval
LCD Segment output
PDR (Port data register)
Internal data bus
PDR read
Output latch
Pch
PDR write
Pin
DDR (Port direction register)
Direction latch
Nch
DDR write
Standby control (SPL = 1)
DDR read
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
34
MB90520A/520B Series
P90 to P97
Segment pin
output approval
LCD Segment output
PDR (Port data register)
Internal data bus
PDR read
Output latch
PDR write
Pin
DDR (Port direction register)
Direction latch
Nch
DDR write
Standby control (SPL = 1)
DDR read
Standby control : Controls stop mode (SPL = 1) , time-base-timer mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode
35
MB90520A/520B Series
2. Timebase Timer
• The timebase timer is an 18-bit freerun timer (timebase timer/counter) that counts up synchronized with the
main clock (oscillation clock : HCLK divided by 2) .
• The timer can generate interrupt requests at a specified interval, with four different interval time settings
available.
• The timer supplies the operating clock for peripheral functions including the oscillation stabilization delay timer
and watchdog timer.
• Timebase timer interval settings
Internal Count Clock Period
Interval Time
212/HCLK (approx. 1.024 ms)
2/HCLK (0.5 µs)
214/HCLK (approx. 4.096 ms)
216/HCLK (approx. 16.384 ms)
219/HCLK (approx. 131.072 ms)
• HCLK : Oscillation clock frequency
• The values enclosed in ( ) indicate the times for a clock frequency of 4 MHz.
• Period of clocks supplied from timebase timer
Peripheral Function
Clock Period
10
2 /HCLK (approx. 0.256 ms)
Oscillation stabilization delay
for the main clock
213/HCLK (approx. 2.048 ms)
215/HCLK (approx. 8.192 ms)
217/HCLK (approx. 32.768 ms)
212/HCLK (approx. 1.024 ms)
Watchdog timer
214/HCLK (approx. 4.096 ms)
216/HCLK (approx. 16.384 ms)
219/HCLK (approx. 131.072 ms)
PPG timer
29/HCLK (approx. 0.128 ms)
• HCLK : Oscillation clock frequency
• The values enclosed in ( ) indicate the times for a clock frequency of 4 MHz.
36
MB90520A/520B Series
• Block diagram
To PPG timer
To watchdog timer
Timebase timer/counter
HCLK divided
by 2
× 21 × 22 × 23
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
OF
OF
OF
OF
To oscillation
stabilization delay
time selector
in clock controller
Reset*1
Clear stop mode, etc.*2
Switch clock mode*3
Counter clear
circuit
TBOF clear
Timebase timer control register
(TBTC)
Interval timer
selector
TBOF set
TBIE TBOF TBR TBC1 TBC0
Timebase timer interrupt signal
OF
HCLK
*1
*2
*3
: Overflow
: Oscillation clock frequency
: Power-on reset, release of hardware standby mode, watchdog reset
: Clear stop mode, main clock mode, PLL clock mode, and pseudo-clock mode
: Main → PLL clock, Sub → main clock, Sub → PLL clock
The actual interrupt request number for the timebase timer is :
Interrupt request number : #12 (0CH)
37
MB90520A/520B Series
3. Watchdog Timer
• The watchdog timer is a timer/counter used to detect faults such as program runaway.
• The watchdog timer is a 2-bit counter that counts the clock signal from the timebase timer or clock timer.
• Once started, the watchdog timer must be cleared before the 2-bit counter overflows. If an overflow occurs,
the CPU is reset.
• Interval time for the watchdog timer
HCLK : Oscillation Clock (4 MHz)
Clock Period
SCLK : Sub-Clock (8.192 kHz)
Min
Max
Min
Max
Clock Period
Approx. 3.58 ms
Approx. 4.61 ms
214 ± 211 / HCLK Approx. 0.438 s Approx. 0.563 s 212 ± 29 / SCLK
Approx. 14.33 ms
Approx. 18.30 ms
216 ± 213 / HCLK Approx. 3.500 s Approx. 4.500 s 215 ± 212 / SCLK
Approx. 57.23 ms
Approx. 73.73 ms
218 ± 215 / HCLK Approx. 7.000 s Approx. 9.000 s 216 ± 213 / SCLK
Approx. 458.75 ms Approx. 589.82 ms 221 ± 218 / HCLK Approx. 14.00 s Approx. 18.00 s 217 ± 214 / SCLK
* : The difference between the maximum and minimum watchdog timer interval times is due to the timing when the
counter is cleared.
* : As the watchdog timer is a 2-bit counter that counts the carry-up signal from the timebase timer or clock timer,
clearing the timebase timer (when operating on HCLK) or the clock timer (when operating on SCLK) lengthens
the time until the watchdog timer reset is generated.
• Watchdog timer count clock
HCLK : Oscillation clock
WTC : WDCS
PCLK : PLL clock
“0”
Count the clock timer output.
“1”
Count the timebase timer output.
SCLK : Sub-clock
Count the clock timer output.
• Events that stop the watchdog timer
1 : Stop due to a power-on reset
2 : Reset due to recovery from hardware standby mode
3 : Watchdog reset
• Events that clear the watchdog timer
1 : External reset input from the RST pin.
2 : Writing “0” to the software reset bit.
3 : Writing “0” to the watchdog control bit (second and subsequent times) .
4 : Changing to sleep mode (clears the watchdog timer and temporarily halts the count) .
5 : Changing to pseudo-clock mode (clears the watchdog timer and temporarily halts the count) .
6 : Changing to clock mode (clears the watchdog timer and temporarily halts the count) .
7 : Changing to stop mode (clears the watchdog timer and temporarily halts the count) .
38
MB90520A/520B Series
• Block diagram
Watchdog timer control register (WDTC)
PONR STBR WRST ERST SRST WTE
Watchdog timer
WT1
WT0
2
Start
Reset
Change to sleep mode
Change to pseudo-clock mode
Change to clock mode
Change to stop mode
Counter
clear
control circuit
Counter
clock
selector
2-bit
counter
Watchdog timer
reset
generation circuit
To
internal
reset
circuit
Clear
4
4
(Timebase timer/counter)
Main clock
(HCLK divided by 2)
× 21 × 22
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
(Clock counter)
Sub-clock
× 21 × 22
× 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215
HCLK : Oscillation clock frequency
39
MB90520A/520B Series
4. 8/16-bit PPG (Programmable Pulse Generator) Timers 0 and 1
The 8/16-bit PPG timer is a two-channel reload timer module (PPG0 and PPG1) that can generate pulse outputs
with the periods specified in the table below and with duty ratios between 0 and 100%. Note that the pulse
periods are different depending on the operation mode.
Operation
Mode
8-bit
PPG output
Independent
2ch operation
mode
16-bit
PPG output
operation
mode
8 + 8-bit
PPG output
operation
mode*1
PPG00, PPG01 (PPG ch0)
Count Clock
*2
PPG10, PPG11 (PPG ch1)
Interval Time
Output Pulse
Width
Interval Time
Output Pulse
Width
φ/1 (62.5 ns)
1/φ to 28/φ
1/φ to 29/φ
1/φ to 28/φ
1/φ to 29/φ
φ/2 (125 ns)
2/φ to 29/φ
22/φ to 210/φ
2/φ to 29/φ
22/φ to 210/φ
φ/4 (250 ns)
22/φ to 210/φ
23/φ to 211/φ
22/φ to 210/φ
23/φ to 211/φ
φ/8 (500 ns)
23/φ to 211/φ
24/φ to 212/φ
23/φ to 211/φ
24/φ to 212/φ
φ/16 (1000 ns)
24/φ to 212/φ
25/φ to 213/φ
24/φ to 212/φ
25/φ to 213/φ
HCLK/512 (128 µs)
29/HCLK to
217/HCLK
210/HCLK to
218/HCLK
29/HCLK to
217/HCLK
210/HCLK to
218/HCLK
φ/1 (62.5 ns)
1/φ to 216/φ
1/φ to 217/φ
1/φ to 216/φ
1/φ to 217/φ
φ/2 (125 ns)
2/φ to 217/φ
22/φ to 218/φ
2/φ to 217/φ
22/φ to 218/φ
φ/4 (250 ns)
22/φ to 218/φ
23/φ to 219/φ
22/φ to 218/φ
23/φ to 219/φ
φ/8 (500 ns)
23/φ to 219/φ
24/φ to 220/φ
23/φ to 219/φ
24/φ to 220/φ
φ/16 (1000 ns)
24/φ to 220/φ
25/φ to 221/φ
24/φ to 220/φ
25/φ to 221/φ
HCLK/512 (128 µs)
29/HCLK to
225/HCLK
210/HCLK to
226/HCLK
29/HCLK to
225/HCLK
210/HCLK to
226/HCLK
φ/1 (62.5 ns)
1/φ to 26/φ
1/φ to 29/φ
1/φ to 216/φ
1/φ to 217/φ
φ/2 (125 ns)
2/φ to 29/φ
22/φ to 210/φ
2/φ to 217/φ
22/φ to 218/φ
φ/4 (250 ns)
22/φ to 210/φ
23/φ to 211/φ
22/φ to 218/φ
23/φ to 219/φ
φ/8 (500 ns)
23/φ to 211/φ
24/φ to 212/φ
23/φ to 219/φ
24/φ to 220/φ
φ/16 (1000 ns)
24/φ to 212/φ
25/φ to 213/φ
24/φ to 220/φ
25/φ to 221/φ
HCLK/512 (128 µs)
29/HCLK to
217/HCLK
210/HCLK to
218/HCLK
29/HCLK to
225/HCLK
210/HCLK to
226/HCLK
*1 : 8 + 8-bit PPG output operation mode consists of using the lower 8 bits as a prescaler for the PPG timer.
*2 : The values enclosed in ( ) indicate the times for a machine clock frequency of 16 MHz.
40
MB90520A/520B Series
• PPG timer channels and PPG pins
The figure below shows the relationship between the 8/16-bit PPG channels and PPG pins on the MB90520A/
520B series.
PPG0
Pin
PPG00 output pin
Pin
PPG01 output pin
PPG1
Pin
PPG10 output pin
Pin
PPG11 output pin
41
MB90520A/520B Series
• Block diagram
8/16-bit PPG timer 0
"H" level data bus
"L" level data bus
PPG0 reload
register
PPG0 operation mode control register
(PPGC0)
PRLH0
PRLL0
("H" level register) ("L" level register)
PEN0

PE00 PIE0 PUF0


Reserved
Interrupt
request output
R
PPG0 temporary
buffer (PRLBH0)
S
Q
2
Reload register
"L" level/"H" level
selector
Count start value
Reload
Clear
Pulse selector
PPG0 down counter
(PCNT0)
Operation mode control signal
Select signal
PPG1 underflow
PPG0 underflow
(to PPG1)
Underflow
CLK
Invert
PPG0
output latch
Pin
PPG00
PPG output control circuit
Timebase timer output
(HCLK/512)
Peripheral clock (φ/1)
Peripheral clock (φ/2)
Peripheral clock (φ/4)
Peripheral clock (φ/8)
Peripheral clock (φ/16)
Count
clock
selector
Pin
PPG01
3
Select signal
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01
PPG01 output control register (PPGOE)

Reserved
HCLK
φ
42
: Undefined
: Reserved bit
: Oscillation clock frequency
: Machine clock frequency
MB90520A/520B Series
8/16-bit PPG timer 1
"H" level data bus
"L" level data bus
PPG1 operation mode control register
(PPGC1)
PPG1
PRLH1
PRLL1
reload
register ("H" level register) ("L" level register)

PEN1
PE10 PIE1 PUF1 MD1
MD0
Reserved
2
Operation
mode control signal
Interrupt
request output
R
PPG1 temporary
buffer (PRLBH1)
S
Reload selector
"L" level/"H"
level selector
Q
Select signal
Count start value
Reload
PPG1 down counter
(PCNT1)
Clear
Underflow
Invert
CLK
PPG1
output latch
Pin
PPG10
PPG output control circuit
MD0
PPG1 underflow
(to PPG0)
Pin
PPG11
PPG0 underflow
(from PPG0)
Timebase timer output
(HCLK/512)
Peripheral clock (φ/1)
Peripheral clock (φ/2)
Peripheral clock (φ/4)
Peripheral clock (φ/8)
Peripheral clock (φ/16)
Count
clock
selector
3
Select signal
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PE11 PE01
PPG01 output control register (PPGOE)

Reserved
HCLK
φ
: Undefined
: Reserved bit
: Oscillation clock frequency
: Machine clock frequency
43
MB90520A/520B Series
5. 16-bit Reload Timers 0 and 1 (With Event Count Function)
The 16-bit reload timers have the following functions.
• The count clock can be selected from three internal clock and the external event clock.
• Either software trigger or external trigger can be selected as the start signals for 16-bit reload timers 0 and 1.
• An interrupt to the CPU can be generated when an underflow occurs on 16-bit reload timer 0 and 1. This
interrupt allows the timers to be used as interval timers.
• Two different operation modes can be selected when an underflow occurs on 16-bit reload timer 0 and 1 : oneshot mode in which timer operation halts when an underflow occurs or reload mode in which the reload register
value is loaded into the timer and counting continues.
• Extended intelligent I/O service (EI2OS) is supported.
• The MB90520A/520B series contains two 16-bit reload timer channels.
• 16-bit reload timer operation modes
Count Clock
Start Trigger
Software trigger
Internal clock
(3 clocks available)
External trigger
Software trigger
Event clock
External trigger
• Interval times for the 16-bit reload timers
Count Clock
Count Clock Period
Internal clock
One-shot mode
Reload mode
One-shot mode
Reload mode
One-shot mode
Reload mode
One-shot mode
Reload mode
Example Interval Times
21T (0.125 µs)
0.125 µs to 8.192 ms
23T (0.5 µs)
0.5 µs to 32.768 ms
2 T (2.0 µs)
2.0 µs to 131.1 ms
5
Event clock
Operation when an Underflow Occurs
3
2 T or longer
0.5 µs or longer
Note : The values enclosed in ( ) and the example interval times are for a machine clock frequency of 16 MHz.
“T” is the machine cycle and is 1/ (machine clock frequency) .
44
MB90520A/520B Series
• Block diagram
Internal data bus
TMRLR
16-bit reload register
Reload signal
Reload
control circuit
TMR
UF
16-bit timer register
CLK
Count clock generation circuit
Machine
clock
φ
Prescaler
3
Gate
input
Clock
pulse
detection
circuit
Wait signal
Output to internal
peripheral functions
Clear
trigger
Internal
clock
Input
control
circuit
Pin
TIN
Clock
selector
External clock
3
2
Function selection



CLK
Output control circuit
Output signal
generation
circuit
Pin
EN
TOT
Select
signal
Operation
control
circuit
 CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
Timer control status register (TMCSR)
Interrupt
request output
45
MB90520A/520B Series
6. 16-bit I/O Timers
The 16-bit I/O timers consist of a two-channel 16-bit freerun timer, two-channel input capture, and eight-channel
output compare. The output compare channels can be used to generate eight independent waveform outputs
based on the 16-bit freerun timer. The input capture channels can be used to measure input pulse widths and
external clock periods.
• Structure of I/O timers in the MB90520A/520B series
16-bit Freerun Timer
Output Compare
Input Capture
16-bit I/O timer
(unit 0)
16-bit freerun timer 0
Output compare 0 to 3
(unit 0)
Input capture 0 and 1
(unit 0)
16-bit I/O timer
(unit 1)
16-bit freerun timer 1
Output compare 4 to 8
(unit 1)

• 16-bit freerun timer functions
• The count value for the 16-bit freerun timer sets the base time for the input capture and output compare
functions.
• An interrupt can be generated when the 16-bit freerun timer overflows.
• Extended intelligent I/O service (EI2OS) can be generated.
• 16-bit freerun timers 0 and 1 can be cleared to “0000H” when an external reset is input, on setting the timer
clear bit (TCCS : CLR = 1) , and when a compare match occurs on output compare 0 to 4.
• The count clock frequency can be selected from the following four clocks :
4/φ (250 ns) , 16/φ (1.0 µs) , 64/φ (4.0 µs) , 256/φ (16.0 µs)
Note : φ is the machine clock frequency. The values in ( ) are for 16 MHz machine clock.
• Input capture functions
• The input capture saves the value of the 16-bit freerun timer and generates an interrupt request when the
specified edge is detected on the trigger input from the external trigger input pin (IC00 or IC01/IC10 or IC11) .
• Input capture channels 0 and 1 can perform input capture and generate interrupt request independently.
• Extended intelligent I/O service (EI2OS) can be generated.
• Detection of rising edges, falling edges, or either edge can be selected as the trigger edge.
• When using input capture 0, either the IC00 or IC01 pin can be used. Note, however, that masking one pin
only is not possible.
• When using input capture 1, either the IC10 or IC11 pin can be used. Note, however, that masking one pin
only is not possible.
• Output compare functions
• The output compare channels compare the values set in output compare registers 0 to 7 with the 16-bit freerun
timers 0 and 1 count values and invert the level of the corresponding output compare pin and clear the 16-bit
freerun timer to “0000H” when a match is detected.
• Extended intelligent I/O service (EI2OS) can be generated.
• The initial output levels at the output compare pins can be set after the microcontroller boots.
• The output levels from the eight output compare channels are controlled independently. Similarly, interrupt
requests are also generated independently by each channel.
46
MB90520A/520B Series
•
Block diagram
16-bit freerun timer
Counter value output
to input capture
and output compare
Timer data registers
(TCDT0, TCDT1* )
OF
16-bit counter
φ
STOP
CLR
Prescaler
Output compare register 0
(Output compare register 4* )
match signal
2
Timer control
status registers
(TCCS0,TCCS1 *)
Reserved
φ
OF
*
IVF
Internal data bus
CLK
IVFE STOP MODE CLR CLK1 CLK0
Freerun timer
overflow interrupt request
: Machine clock frequency
: Overflow
: Name for 16-bit freerun timer channel 1
Input capture
16-bit freerun timer 0
Edge detection circuit
IN00
Pin
Pin
IN11
Input capture register 0 (IPCP1)
2
2
Internal data bus
Input capture register 1 (IPCP0)
Pin
IN01
IN10
Pin
Input capture
control status register ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
(ICS01)
Input capture
interrupt request
47
MB90520A/520B Series
Output compare
Output compare
interrupt request
Output compare control
status registers
(OSC23, OSC67*)



CMOD OTE1 OTE0 OTD1 OTD0 IOP1 IOP0 IOE1 IOE0


CST1 CST0
2
Timer data registers
(TCDT0, TCDT1* )
2
16-bit freerun timer 0 (1*)
Compare control circuit 3 (7*)
Internal data bus
OCP3 (OCP7*)
Output compare register 3 (7*)
OUT3 (OUT7*)
Compare control circuit 2 (6*)
Output control
circuit 3 (7*)
OCP2 (OCP6*)
Output compare register 2 (6*)
Pin
OUT2 (OUT6*)
Output control
circuit 2 (6*)
Pin
Compare control circuit 1 (5*)
OUT1 (OUT5*)
OCP1 (OCP5*)
Output control
circuit 1 (5*)
Pin
Output compare register 1 (5*)
OUT0 (OUT4*)
Output control
circuit 0 (4*)
Compare control circuit 0 (4*)
Pin
OCP0 (OCP4*)
Output compare register 0 (4*)
Output compare control
status registers
(OSC01, OSC45*)



2
2
CMOD OTE1 OTE0 OTD1 OTD0 IOP1 IOP0 IOE1 IOE0


CST1 CST0
Output compare
interrupt request
* : Name for output compare unit 1
48
MB90520A/520B Series
7. 8/16-bit Up/Down Counter/Timers 0 and 1
• The 8/16-bit up/down counter/timers can operate in timer mode, up/down count mode, and phase difference
count mode.
• The unit can be used as either a 2-channel × 8-bit or 1-channel × 16-bit up/down counter/timer.
• 8/16-bit up/down counter/timer functions
Operation
Count Clock
Count Mode
Mode
(Count Edge)
Timer mode
2/φ, 4/φ
(φ : Machine clock frequency)
Counts up on detecting speciUp/down count fied edge on the AIN pin.
mode
Counts down on detecting specified edge on the BIN pin.
Phase
difference
count
8-bit
mode
× 2-channel
(multiply by 2)
mode
Function of
ZIN Pin

Counter clear
function
Gate function
Reads the AIN pin input level on
detecting a rising or falling edge
on the BIN pin and counts up or
counts down.
Counter clear
function
Reads the AIN pin input level on
detecting a rising or falling edge
Phase
on the BIN pin and counts up or
difference count counts down. Similarly, reads
mode
the BIN pin input level on detect(multiply by 4) ing a rising or falling edge on the
AIN pin and counts up or counts
down.
Counter clear
function
Timer mode
2/φ, 4/φ
(φ : Machine clock frequency)
Counts up on detecting speciUp/down count fied edge on the AIN pin.
mode
Counts down on detecting specified edge on the BIN pin.
Phase
difference
count
16-bit
mode
× 1-channel
(multiply by 2)
mode
Other Functions
Gate function
Gate function

Counter clear
function
Gate function
Reads the AIN pin input level on
detecting a rising or falling edge
on the BIN pin and counts up or
counts down.
Counter clear
function
Reads the AIN pin input level on
detecting a rising or falling edge
Phase
on the BIN pin and counts up or
difference count counts down. Similarly, reads
mode
the BIN pin input level on detect(multiply by 4) ing a rising or falling edge on the
AIN pin and counts up or counts
down.
Counter clear
function
• Compare function
• Reload function
• Compare/reload function
• Compare/reload prohibit
• The direction of the
previous count can be
determined from the up/
down flag.
• Interrupt requests can be
generated on the following
conditions :
1 : Compare match
2 : Underflow or overflow
3 : Count direction
change
Gate function
Gate function
49
MB90520A/520B Series
• Block diagram
8/16-bit up/down counter/timer 0
Internal data bus
RCR0
Reload compare register 0
Reload
control circuit
Carry/
Borrow
(to
channel
1)
UDCR0
Up/down count register 0
Counter control
register 0 (CCR0: L)
Pin
Machine clock
AIN0
Pin
Pin
Counter
clear circuit
Edge/level
detection
circuit
Edge
detection
circuit
Prescaler
Up/down
count
selector
BIN0
Underflow
ZIN0
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
Overflow

Compare
control circuit
Count clock
Counter status
register 0 (CSR0)
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
Interrupt
request
Interrupt
request
M16E CDCF CFIE CLKS CMS1CMS0 CES1 CES0
Counter control register 0 (CCR0: H)
50
M16E
(to channel 1)
MB90520A/520B Series
8/16-bit up/down counter/timer 1
Internal data bus
RCR1
Reload compare register 1
Reload
control circuit
UDCR1
Up/down count register 1
Counter control
register 1 (CCR1: L)
Counter
clear circuit
ZIN1
Edge/level
detection
Pin
circuit
Carry/Borrow
(from channel 0)
Machine clock
AIN1
Pin
Pin
Prescaler
Edge
detection
circuit
Up/down
count clock
selector
BIN1
M16E
(from
channel 1)
Underflow
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
Overflow

Compare
control circuit
Count clock
Counter status
register 1 (CSR1)
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
Interrupt
request
Interrupt
request
 CDCF CFIE CLKS CMS1CMS0 CES1 CES0
Counter control register 1 (CCR1: H)
• Pins and interrupt numbers
8/16-bit up/down counter/timer 0
AIN0 pin : P24/AIN0
BIN0 pin : P25/BIN0
ZIN0 pin : P26/ZIN0
Compare match interrupt number : #21 (15H)
Interrupt number for underflow/overflow interrupt, count direction change interrupt : #2 (16H)
8/16-bit up/down counter/timer 1
AIN1 pin : P50/AIN1
BIN1 pin : P51/BIN1
ZIN1 pin : P52/ZIN1
Compare match interrupt number : #29 (1DH)
Interrupt number for underflow/overflow interrupt, count direction change interrupt : #3 (1EH)
51
MB90520A/520B Series
8. Extended I/O Serial Interfaces 0 and 1
• The extended I/O serial interfaces are serial I/O interfaces that perform clock-synchronized data transfer.
• The MB90520A/520B series contain two internal extended I/O serial interface channels.
• Either LSB-first or MSB-first data transmission format can be selected.
• Extended I/O serial interface functions
Function
Transmission direction
Transmission mode
• Clock synchronous (data transfer only)
Transmission clock
• Internal shift clock mode (Uses the communications prescaler output clock.)
• External shift clock mode (Inputs the clock signal from SCK1 and SCK2.)
Transmission speed
• When using internal shift clock :
Up to 1 MHz operation can be achieved (for a 16 MHz machine clock with the divisor
setting for the communication prescaler set to 8) . Speeds faster than 1 MHz are not
possible.
• When using an external shift clock :
As a minimum of 5 machine cycles are required, when the machine clock is 16 MHz
the maximum input frequency for the external shift clock is 16 MHz / 5 = 3.2 MHz.
Data transmission
format
Interrupt request
generation
EI2OS support
52
• Transmit and receive can be handled simultaneously. (A setting is required to select
transmit or receive.)
• LSB-first or MSB-first, selectable
• Data transfer only
• Number of data bits = 8 (fixed)
• Interrupt generated when transfer completes
• Supports use of the extended intelligent I/O service.
MB90520A/520B Series
• Block diagram
Internal data bus
(MSB-first)
D7 to D0
D7 to D0 (LSB-first)
Transmission direction selection
Read
Write
Serial data register
(SDR)
Pin
SIN
Pin
SOT
Pin
Control circuit
Shift clock counter
SCK
Machine clock
Communications
prescaler
SMD2 SMD1 SMD0 SIE
SIR BUSY STOP STRT
Serial mode control
status register (SMCS)
MD





 MODE BDS SOE SCOE
Interrupt request

DIV3 DIV2 DIV1 DIV0
Communications prescaler
register (CDCR)
53
MB90520A/520B Series
9. UART (SCI : Serial Communication Interface)
• The UART (SCI) is a general-purpose serial communications interface for performing synchronous or asynchronous communications with external devices.
• The interface provides bi-directional communications in both clock synchronous and clock asynchronous
modes.
• Includes a master-slave communication function (multi-processor mode) .
• Can generate interrupt requests at receive complete, receive error detected, and transmit complete timings.
Also supports EI2OS.
• UART (SCI) functions
Function
Data buffer
Transmission modes
Baud rate
Number of data bits
Signal format
Receive error detection
Interrupt requests
• Full-duplex double-buffered
• Clock synchronous (with no start/stop bit, no parity bit)
• Clock asynchronous (start-stop sync)
• Can use dedicated baud rate generator.
• Can use external clock input.
• Can use clock supplied by 16-bit reload timer 0.
• For machine clock speeds of 6 MHz, 8 MHz, 10 MHz, 12 MHz, and 16 MHz :
Available speeds for asynchronous communications : 31250 bps, 9615 bps,
4808 bps, 2404 bps, and 1202 bps
Available speeds for synchronous communications : 1 Mbps, 500 Kbps,
250 Kbps, 125 Kbps, and 62.5 Kbps
• 7 bits (when parity is used for asynchronous normal mode)
• 8 bits (when parity is not used)
• Non return to zero (NRZ) format
• Framing errors (not available in clock synchronous mode)
• Overrun errors
• Parity errors (not available in clock synchronous mode and multi-processor
mode)
• Receive interrupt (Receive complete or receive error detected)
• Transmit interrupt (Transmission complete)
• Both transmit and receive support the extended intelligent I/O service (EI2OS) .
Master/slave communication
function
• Used for 1 (master) to n (slave) communications. (Can only be used as master)
(multi-processor mode)
EI2OS support
54
• Supports the extended intelligent I/O service (EI2OS)
MB90520A/520B Series
• UART (SCI) operation modes
Operation Mode
No. of Data Bits
7 bits
Mode 0
Asynchronous
Normal mode
(1-to-1)
Mode 1
Asynchronous
Multi-processor mode
(1-to-n)
×
Mode 2
Clock
synchronous
Clock synchronous
mode
(one-to-one)
×
8 bits
(+1)
Parity Bit
None
Use
No. of Stop Bits
1 bit
2 bits
×
×
×
×
: Available
× : Not available
+1 : Address/data bit used for communication control
Notes :
• The number of data bits must be set to eight for multi-processor and clock synchronous modes.
• A parity bit cannot be used in multi-processor and clock synchronous modes.
• Only data can be transferred in clock synchronous mode. Start and stop bits cannot be added to the transmission data.
55
MB90520A/520B Series
• Block diagram
Control bus
Dedicated baud rate
generator
16-bit
reload timer 0
Receive
interrupt
request output
Transmit
interrupt
request output
Transmit
clock
Clock
selector
Receive clock
Receive
control
circuit
Pin
Start bit
detection circuit
Transmission
start circuit
Receive bit
counter
Transmit
bit counter
Receive parity
counter
Transmit
parity counter
Receive complete
SCK
Receive
shift register
Pin
Transmission
control circuit
SIN
Pin
SOT
Transmission
shift register
Transmission start
Receive status
evaluation circuit
Serial output
data register
Serial input
data register
Receive error
detection signal
for EI2OS
Internal data bus
MD
Communication
prescaler
register
56
DIV3
DIV2
DIV1
DIV0
Serial
mode
register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
Serial
control
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
Serial
status
register
PE
ORE
FRE
RDRF
TDRE
RIE
TIE
MB90520A/520B Series
10. DTP (Data Transfer Peripheral) /External Interrupt Circuit
The DTP/external interrupt function detects interrupt requests and data transfer requests input from external
devices and passes these to the CPU as external interrupt requests. This block can also activate the extended
intelligent I/O service (EI2OS) .
• DTP/external interrupt functions
External Interrupt
Input pins
Interrupt
conditions
Interrupt control
Interrupt flag
Processing
selection
Interrupt
execution
EI2OS support
DTP Function
• 8 channels (INT0 to INT7)
• Can be set independently for each channel (each pin) in the detection level setup register
(ELVR) .
• “H” level, “L” level,
rising edge, or falling edge input
“H” level or “L” level input
• Interrupts can be enabled or disabled in the DTP/external interrupt enable register (ENIR) .
• The DTP/external interrupt request register (EIRR) stores interrupt requests.
• Set EI2OS to be disabled (ICR : ISE = 0)
• Set EI2OS to be enabled (ICR : ISE = 1)
• Jumps to interrupt handler routine
• Jumps to interrupt handler routine after
automatic data transfer by EI2OS completes.
• Supports the extended intelligent I/O service (EI2OS)
57
MB90520A/520B Series
• Block diagram
Detection level setting register (ELVR)
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4
Pin
INT7
Pin
Internal data bus
INT6
Pin
INT5
Pin
INT4
Level/Edge
selector
Level/Edge
selector
Level/Edge
selector
Level/Edge
selector
LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
Pin
INT3
Pin
INT2
Pin
INT1
Pin
INT0
Level/Edge
selector
Level/Edge
selector
Level/Edge
selector
Level/Edge
selector
DTP/external interrupt input
detection circuit
DTP/external interrupt request
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 register (EIRR)
Interrupt request
signal
Interrupt request
signal
DTP/external interrupt enable
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 register (ENIR)
58
MB90520A/520B Series
11. Wakeup Interrupts
• The wakeup interrupt function detects wakeup interrupt requests from external devices by detecting “L” levels
input to the wakeup interrupt input pins (WI0 to WI7) and passes these to the CPU for interrupt processing.
• Wakeup interrupts can be used to wakeup the microcontroller from standby mode. (However, wakeup interrupts
cannot be used to recover from hardware standby mode.)
• Not supported by the extended intelligent I/O service (EI2OS) .
• Wakeup interrupt functions
Function and Control
• 8 channels (8 pins : WI0 to WI7)
Input pins
Interrupt trigger
• “L” level inputs. One interrupt flag is shared by all eight channels.
Interrupt control
• Interrupt requests can be enabled or disabled in the wakeup interrupt control
register (EICR) .
Interrupt flag
EI2OS support
• Interrupt requests are stored in the wakeup interrupt flag register (EIFR) .
• Not supported by the extended intelligent I/O service (EI2OS) .
• Block diagram
Internal data bus
Wakeup interrupt
control register (EICR)
Wakeup interrupt
flag register (EIFR)
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0







WIF
Interrupt request detection circuit
WI0
Pin
WI1
Pin
WI2
Pin
WI3
Pin
WI4
Pin
WI5
Pin
WI6
Pin
WI7
Pin
Wakeup
interrupt request
 : Undefined
59
MB90520A/520B Series
12. Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Generation of this
hardware interrupt can be specified by software.
• Delayed interrupt generation module functions
Function and Control
Interrupt trigger
• Writing “1” to bit R0 of the delayed interrupt request generation/clear register
(DIRR : R0 = 1) generates an interrupt request.
• Writing “0” to bit R0 of the delayed interrupt request generation/clear register
(DIRR : R0 = 0) clears the interrupt request.
Interrupt control
• No enable/disable register is provided for this interrupt.
• Set in bit R0 of the delayed interrupt request generation/clear register (DIRR : R0) .
Interrupt flag
EI OS support
2
• Not supported by the extended intelligent I/O service (EI2OS) .
• Block diagram
Internal data bus






Delayed interrupt request generation/clear
register (DIRR)
 : Undefined
60

R0
S Interrupt
R request latch
Interrupt request
signal
MB90520A/520B Series
13. 8/10-bit A/D Converter
• The 8/10-bit A/D converter uses RC successive approximation to convert analog input voltages to an 8-bit or
10-bit digital value.
• The input signals can be selected from the eight analog input pin channels.
• Either a software trigger, internal timer output, or external pin trigger can be selected to trigger the start of A/
D conversion.
• 8/10-bit A/D converter functions
Function
A/D conversion
time
• Sampling time : Can be selected from 64, 128, or 4096 machine cycles.
The minimum is 4 µs.
• Compare time : Can be selected from 44, 99, or 176 machine cycles.
The minimum is 4.4 µs.
• A/D conversion time = sampling time + conversion time.
The minimum A/D conversion time is 10.2 µs.
Conversion method • RC successive approximation with sample & hold circuit
Resolution
Analog input pins
Interrupts
• 8-bit or 10-bit, selectable
• Up to eight channels can be used. However, two or more channels cannot be used
simultaneously.
• An interrupt request can be generated when A/D conversion completes.
A/D conversion
start trigger
• Selectable : software, internal timer output, or falling edge on input from external pin
EI2OS support
• Supported by the extended intelligent I/O service (EI2OS) .
• 8/10-bit A/D converter conversion modes
Description
Single-shot
conversion mode
Performs A/D conversion sequentially from the start channel to the end channel. A/D conversion halts after conversion completes for the end channel.
Continuous
conversion mode
Performs A/D conversion sequentially from the start channel to the end channel. A/D conversion starts again from the start channel after conversion completes for the end channel.
Incremental
conversion mode
A/D conversion is performed for one channel then halts until the next trigger. After conversion is performed for the end channel, the next conversion is performed for the start channel, and repeated this operation.
61
MB90520A/520B Series
• Block diagram
Interrupt request output
A/D control
status register
(ADCS)
ReBUSY INT INTE PAUS STS1 STS0 STAT served MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
2
2
Trigger
selector
Decoder
Internal data bus
ADTG
TO
6
φ
Comparator
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Sample &
hold circuit
Control circuit
Analog
channel
selector
AVRH, AVRL
AVCC
AVSS
D/A converter
2
2
A/D data
register
(ADCR) SELB ST1 ST0 CT1 CT0 
TO

Reserved
φ
62
: Internal timer output
: Undefined
: Always set to “0”.
: Machine clock
D9
D8
D7
D6 D5
D4
D3
D2
D1
D0
MB90520A/520B Series
14. 8-bit D/A Converter
• The 8-bit D/A converter performs R-2R D/A conversion with 8-bit resolution.
• Two D/A converter channels with independent analog outputs are provided.
• D/A converter functions
Function
D/A conversion time
•The settling time is 12.5 µs. This is independent of the machine clock.
Conversion method
• R-2R conversion
Resolution
Analog output pins
Interrupts
D/A conversion trigger
EI2OS support
• 8-bit
• Two output pins are provided. Both pins can be used simultaneously.
• None
• Set the digital value in the D/A data register (DADR) , then enable D/A output in the
D/A control register (DACR) to start analog output from the D/A output pin.
• Not supported by the extended intelligent I/O service (EI2OS) .
• D/A converter theoretical output voltage
D/A Data Register Setting
Theoretical Output Voltage Value
00H
0 / 256 × DVCC voltage ( = 0 V)
00H
1 / 256 × DVCC voltage
•••
•••
FEH
254 / 256 × DVCC voltage
FFH
255 / 256 × DVCC voltage
Note : DVCC voltage : D/A converter reference voltage. This must not exceed VCC.
Also, always ensure that DVSS is equipotential to VSS.
63
MB90520A/520B Series
• Block diagram
Internal data bus
D/A data register (DADR)
DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
D/A conversion circuit
DVR
DA7
Pin
DA
2R
R
DA6
2R
R
DA5
2R
R
DA4
2R
R
DA3
2R
R
DA2
2R
R
DA1
2R
R
DA0
2R
2R
DVSS
Standby control (SPL = 1)
D/A control register (DACR)







DAE
Internal data bus
Standby control : Controls stop mode (SPL = 1) , pseudo-clock mode (SPL = 1) , clock mode (SPL = 1) ,
and hardware standby mode.
64
MB90520A/520B Series
15. Clock Timer
•
•
•
•
The clock timer is a 15-bit freerun timer that counts up synchronized with the sub-clock.
Seven different interval time settings are available.
This timer provides the clock for the sub-clock’s oscillation stabilization delay timer and the watchdog timer.
This timer always counts the sub-clock, regardless of the settings in the clock selection register (CKSC) .
• Clock timer functions
Function
Interval time
Clock timer size
• Selectable from the seven settings shown in the table below.
• 15-bit
Clock supply
• Oscillation stabilization delay timer for sub-clock and watchdog timer
Source clock
• Sub-oscillation clock divided by four. (SCLK : Sub-clock)
Interrupts
EI2OS support
• Interval time overflow
• Not supported by the extended intelligent I/O service (EI2OS) .
• Clock timer interval times
Sub-Clock Period
Interval Time
29/SCLK (approx. 62.5 ms)
210/SCLK (approx. 125.0 ms)
211/SCLK (approx. 250.0 ms)
SCLK (122 µs)
212/SCLK (approx. 500.0 ms)
213/SCLK (approx. 1.0 s)
214/SCLK (approx. 2.0 s)
216/SCLK (approx. 4.0 s)
SCLK : Sub-clock frequency
The values enclosed in ( ) are the times for a sub-clock frequency of 8.192 kHz.
Note that the sub-oscillation clock is divided by four to generate the sub-clock frequency. The sub-oscillation clock
operates at 32.768 kHz.
• Clock periods generated by clock timer
Clock Supply
Oscillation stabilization delay timer
for sub-clock
Clock Period
214/SCLK (approx. 2.0 s)
210/SCLK (approx. 125.0 ms)
Watchdog timer
213/SCLK (approx. 1.0 s)
214/SCLK (approx. 2.0 s)
216/SCLK (approx. 4.0 s)
SCLK : Sub-clock frequency
The values enclosed in ( ) are the times for a sub-clock frequency of 8.192 kHz.
Note that the sub-oscillation clock is divided by four to generate the sub-clock frequency. The sub-oscillation clock
operates at 32.768 kHz.
65
MB90520A/520B Series
• Block diagram
To
watchdog
timer
Clock timer counter
SCLK
× 21 × 22 × 23 × 24 × 25 × 26 × 27 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215
OF
OF
OF
OF
OF
OF
Power-on reset
Change to hardware standby mode
Counter
clear circuit
OF
To oscillation stabilization
delay timer for sub-clock
Change to stop mode
Interval
timer selector
Clock timer interrupt
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
Clock timer control register (WTC)
OF
SCLK
66
: Overflow
: Sub-clock frequency
MB90520A/520B Series
16. LCD Controller/Driver
• The LCD controller/driver can drive an LCD (Liquid Crystal Display) directly.
• The LCD is driven by 4 common outputs and 32 segment outputs.
• The output mode can be set to 1/2, 1/3, or 1/4 duty.
• LCD controller/driver functions
Function
Divider resistor for LCD
drive power
• Either the internal resistor (approx. 100 kΩ) or an externally connected resistor
can be selected.
Common outputs
• Max 4 outputs (The corresponding pins cannot be used as I/O ports when using
an LCD.)
Segment outputs
• Max 32 outputs (of these, 24 pins can be used as I/O ports in blocks of 8 pins.)
Display data memory
• 16 bytes of RAM for internal display are provided
Duty
• 1/2, 1/3, or 1/4 can be selected.
Bias
• 1/3 only supported
Drive clock
Interrupts
EI OS support
2
• Either the oscillation clock (HCLK) or sub-clock (SCLK) can be used.
• None
• Not supported by the extended intelligent I/O service (EI2OS) .
• Bias, duty, and common output combinations
Bias
1/2 Duty Output Mode
1/3 bias
COM0 and COM1 outputs
used
1/3 Duty Output Mode
1/4 Duty Output Mode
COM0 to COM2 outputs
used
COM0 to COM3 outputs
used
67
MB90520A/520B Series
• Block diagram
Common pin selection register
(LCDCMR)




COM3 COM2 COM1 COM0
Pin
V0
Pin
V1
Pin
V2
Pin
V3
Pin
COM0
Pin
COM1
Pin
COM2
Pin
COM3
Pin
SEG0
Pin
SEG1
Pin
SEG2
Pin
SEG29
Pin
SEG30
Pin
SEG31
4
LCDC control
register 0
(LCR0)
Internal
divider
resistor
CSS LCEN VSEL BK MS1 MS0 FP1 FP0
2
HCLK
Prescaler
SCLK
Timing
controller
AC
conversion circuit
Internal data bus
2
Display data memory
(16 bytes)
Common
driver
32
6
ReReserved SEG5 SEG4 served SEG3 SEG2 SEG1 SEG0
Segment
driver
LCDC control register 1
(LCR1)
Controller

: Undefined bit
HCLK : Main clock
SCLK : Sub-clock
68
Driver
MB90520A/520B Series
17. Communications Prescaler
• Supplies the clock to the dedicated baud rate generator used by the UART (SCI) and extended I/O serial
interfaces.
• By dividing the machine clock to produce the clock supply to the dedicated baud rate generator, the baud rate
can be specified independently of the machine clock speed.
• The communications prescaler can divide the machine clock frequency φ by the following seven ratios to
generate the clock supply to the dedicated baud rate generator and extended I/O serial interface :
φ/2, φ/3, φ/4, φ/5, φ/6, φ/7, φ/8
• Communications prescaler functions
Function
• Dedicated baud rate generator for the UART (SCI) and the extended I/O serial
interface. However, the same clock is supplied to both peripherals.
Clock supply
Divided clock frequency
• φ/2, φ/3, φ/4, φ/5, φ/6, φ/7, φ/8 (φ : Machine clock frequency)
• None
Interrupts
• Not supported by the extended intelligent I/O service (EI2OS) .
EI2OS support
Note : As the same output from the communications prescaler is supplied to both the UART (SCI) and the extended
I/O serial interface, the transfer clock speed settings must be revised if the communications prescaler settings
are changed.
• Block diagram
CDCR
MD



DIV3 DIV2 DIV1 DIV0
Extended serial I/O
SMCS:SMD2 ∼ SMD0 = 000B ∼ 100B
Communications prescaler
φ

φ
φ/2
φ/3
φ/4
φ/5
UART
φ/6
φ/7
φ/8
SMR:CS2 ∼ CS0 = 000B ∼ 100B
: Undefined
: Machine clock frequency
69
MB90520A/520B Series
18. Address Match Detection Function
• If the program address during program execution matches the value set in one of the detection address setting
registers (PADR) , the address match detection function replaces the instruction being executed with the INT9
instruction and executes the interrupt handler program.
• The address match detection function provides a simple method of correcting programming errors (patching)
using RAM or similar.
• Address match detection functions
Function
No. of address settings
• Two channels (two addresses can be set)
• An interrupt is generated when the program address matches the detection
address setting register.
Interrupts
EI2OS support
• Not supported by the extended intelligent I/O service (EI2OS) .
• Block diagram
Comparator
Internal data bus
Address latch
PADR0 (24 bit)
Detection address setting register
PADR1 (24 bit)
INT9 instruction
(generates an INT9 interrupt)
Detection address setting register
PACSR
Reserved Reserved Reserved Reserved
ADE1
Address detection control register (PACSR)
Reserved : Always set to “0”.
70
ADD1
ADE0
ADD0
MB90520A/520B Series
19. ROM Mirror Function Selection Module
The ROM mirror function selection module enables ROM data in FF bank to be read by accessing 00 bank.
• ROM mirror function selection module functions
Function
Mirror setting address
• Data in FFFFFFH to FF4000H in FF bank can be read from 00FFFFH to 004000H
in 00 bank.
• None
Interrupts
• Not supported by the extended intelligent I/O service (EI2OS) .
EI OS support
2
• Relationship between addresses in the ROM mirror function
004000H
00 bank mirror area
00FFFFH
FE0000H
ROM area in MB90523A, 523B, and F523B
FEFFFFH
FF0000H
ROM area in MB90522A and 522B
FF4000H
FFFFFFH
Mirrored ROM data area
in FF bank
• Block diagram
ROM mirror function selection register (ROMM)







MI
Address
Internal data bus
Address space
FF bank
00 bank
Data
ROM
71
MB90520A/520B Series
20. Low Power Consumption (Standby) Modes
The power consumption of F2MC-16LX devices can be reduced by various settings relating to the operating
clock selection.
• Functions of each CPU operation mode
CPU Operation Operation
Clock
Mode
PLL clock
Normal run
The CPU and peripheral functions operate using the oscillation clock (HCLK) multiplied by the PLL circuit.
Sleep
The peripheral functions only operate using the oscillation clock (HCLK) multiplied
by the PLL circuit.
Pseudoclock
The timebase timer only operates using the oscillation clock (HCLK) multiplied by
the PLL circuit.
Stop
Main clock
The oscillation clock is stopped and the CPU and peripherals halt operation.
Normal run
The CPU and peripheral functions operate using the oscillation clock (HCLK) divided by 2.
Sleep
The peripheral functions only operate using the oscillation clock (HCLK) divided
by 2.
Stop
The oscillation clock is stopped and the CPU and peripherals halt operation.
Normal run
The CPU and peripheral functions operate using the sub-clock (SCLK) . The oscillation clock stops.
Sleep
The peripheral functions only operate using the sub-clock (SCLK) . The oscillation
clock stops.
Clock
The clock timer only operates using the sub-clock (SCLK) . The oscillation clock
stops.
Stop
The oscillation clock and sub-clock are stopped and the CPU and peripherals halt
operation.
CPU
intermittent
operation
Normal run
The oscillation clock (HCLK) divided by 2 operates intermittently for fixed time intervals.
Hardware
standby
Stop
The oscillation clock and sub-clock are stopped and the CPU and peripherals halt
operation.
Sub-clock
72
Explanation
MB90520A/520B Series
21. Clock Monitor Function
The clock monitor function outputs the machine clock divided by a specified amount to the clock monitor pin
(CKOT) .
• Clock monitor functions
Function
• Machine clock divided by 2 to 32 (8 settings available)
Output frequency
• None
Interrupts
• Not supported by the extended intelligent I/O service (EI2OS) .
EI OS support
2
• Output frequency of the clock monitor function
When φ = 16 MHz
FRQ2 - 0
Machine Clock
Bits
Divide Ratio
Period
Frequency
When φ = 8 MHz
When φ = 4 MHz
Period
Frequency
Period
Frequency
8 MHz
250 ns
4 MHz
500 ns
2 MHz
250 ns
4 MHz
500 ns
2 MHz
1.0 µs
1 MHz
φ/23
500 ns
2 MHz
1.0 µs
1 MHz
2.0 µs
500 kHz
011B
φ/2
1.0 µs
1 MHz
2.0 µs
500 kHz
4.0 µs
250 kHz
100B
5
φ/2
2.0 µs
500 kHz
4.0 µs
250 kHz
8.0 µs
125 kHz
101B
φ/26
4.0 µs
250 kHz
8.0 µs
125 kHz
16.0 µs
62.5 kHz
110B
φ/27
8.0 µs
125 kHz
16.0 µs
62.5 kHz
32.0 µs
31.25 kHz
111B
φ/2
16.0 µs
62.5 kHz
32.0 µs
31.25 kHz
64.0 µs
15.625 kHz
000B
1
φ/2
125 ns
001B
φ/22
010B
4
8
Internal data bus
• Block diagram
φ
Prescaler
Pin
CKOT
Output enable
Clock output enable
register (CLKR)


φ
Count
clock
selector


3
 CKEN FRQ2 FRQ1 FRQ0
: Undefined
: Machine clock frequency
73
MB90520A/520B Series
22. 1 Mbit Flash Memory
• This section describes the flash memory on the MB90F523B and does not apply to evaluation products and
MASK ROM versions.
• The flash memory is located in banks FE to FF in the CPU memory map.
• Flash memory functions
Function
Memory size
Memory configuration
Sector configuration
• 1 Mbit (128 KBytes)
• 128 KWords × 8 bits or 64 KWords × 16 bits
• 16 KBytes + 8 KBytes + 8 KBytes + 32 KBytes + 64 KBytes
Sector protect function
• Selectable for each sector
Programming algorithm
• Automatic programming algorithm (Embedded Algorithm* : Equivalent to
MBM29F400TA)
Operation commands
No. of write/erase cycles
Memory write/erase
method
Interrupts
EI OS support
2
• Compatible with JEDEC standard commands
• Includes an erase pause and restart function
• Data polling and toggle bit write/erase completion
• Erasing by sector available (sectors can be combined in any combination)
• Min 10,000 guaranteed
• Can be written and erased using a parallel writer
(Minato Electronics model 1890A, Ando Denki AF9704, AF9705, AF9706,
AF9708, and AF9709)
• Can be written and erased using a dedicated serial writer
(YDC AF200, AF210, AF120, and AF110)
• Can be written and erased by the program
• Write and erase completion interrupts
• Not supported by the extended intelligent I/O service (EI2OS) .
* : Embedded Algorithm is a trademark of Advanced Micro Devices.
• Sector configuration of flash memory
Flash memory
SA0 (64 Kbyte)
SA1 (32 Kbyte)
SA2 (8 Kbyte)
SA3 (8 Kbyte)
SA4 (16 Kbyte)
CPU address
Writer address*
FE0000H
60000H
FEFFFH
6FFFFH
FF0000H
70000H
FF7FFFH
77FFFH
FF8000H
78000H
FF9FFFH
79FFFH
FFA000H
7A000H
FFBFFFH
7BFFFH
FFC000H
7C000H
FEFFFFH
7FFFFH
* : The writer address is the address to use instead of the CPU address when writing data from a parallel
flash memory writer. Use the writer address when programming or erasing using a general-purpose
parallel writer.
74
MB90520A/520B Series
• Pins used for Fujitsu standard serial on-board programming
Pin
Function
Explanation
MD2, MD1,
Mode pins
MD0
Setting MD2 = MD1 = 1, MD0 = 0 selects flash memory serial programming mode.
X0, X1
Oscillation input pin
Flash memory serial programming mode uses the PLL clock with the
multiplier set to 1 as the machine clock. Set the oscillation frequency
used for serial programming to between 3 MHz and 16 MHz.
P00, P01
Write program activation
pins
Input P00 = 0 (“L” level) and P01 = 1 (“H” level)
RST
Reset pin
HST
Hardware standby pin
SIN0
Serial data input pin
SOT0
Serial data output pin
SCK0
Serial clock input pin
C
C pin
Capacitor pin for power supply stabilization. Connect an external capacitor of approx. 0.1 µF.
VCC
Power supply voltage pins
If the user system can provide the programming voltage (5 V ± 10%) ,
do not need to connect to the flash microcontroller writer.
VSS
GND pin
Connect to common GND with the flash microcontroller writer.

Input an “H” level during flash memory serial programming mode.
Uses the UART (SCI) in clock synchronous mode.
• Overall configuration of connection between serial writer and MB90F523A
Fujitsu standard serial on-board programming uses a flash microcontroller writer made by YDC.
Host interface cable (AZ221)
Standard cable (AZ210)
RS232C
Flash microcontroller
writer
+
memory card
Clock synchronous
serial
MB90F523A/B
user system
Can operate standalone
Note : Contact YDC for details of the functions and operation of the flash microcontroller writer (AF220, AF210,
AF120, or AF110) , standard connection cable (AZ210) , and connectors.
75
MB90520A/520B Series
■ Electrical Characteristics\
1. Absolute Maximum Ratings
Parameter
(VSS = AVSS = 0.0 V)
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 6.0
V
AVCC
VSS − 0.3
VSS + 6.0
V
*1
AVRH,
AVRL
VSS − 0.3
VSS + 6.0
V
*1
DVCC
VSS − 0.3
VSS + 6.0
V
*2
Input voltage
VI
VSS − 0.3
VSS + 6.0
V
*3
Output voltage
VO
VSS − 0.3
VSS + 6.0
V
*3
“L” level maximum output current
IOL

15
mA
*4
“L” level average output current
IOLAV

4
mA
*5
“L” level total maximum output current
ΣIOL

100
mA
ΣIOLAV

50
mA
*6
IOH

−15
mA
*4
“H” level average output current
IOHAV

−4
mA
*5
“H” level total maximum output current
ΣIOH

−100
mA
ΣIOHAV

−50
mA
*6

400
mW
MB90522A/523A/
F523B

300
mW
MB90522B/523B
Ta
−40
+85
°C
Tstg
−55
+150
°C
Power supply voltage
“L” level total average output current
“H” level maximum output current
“H” level total average output current
Power consumption
Pd
Operating temperature
Storage temperature
*1 : AVCC, AVRH, AVRL, and DVCC shall never exceed VCC . AVRH and AVRL shall never exceed AVCC.
Also, AVRL shall never exceed AVRH.
*2 : VCC ≥ AVCC ≥ DVCC ≥ 3.0 V.
*3 : VI and VO shall never exceed VCC + 0.3 V.
*4 : The maximum output current is the peak value for a single pin.
*5 : The average output current is the average current value for a single pin during a 100 ms period.
*6 : The total average current is the average current for all pins during a 100 ms period.
Note : Average output current = operating current × operating ratio
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
76
MB90520A/520B Series
2. Recommended Operating Conditions
Parameter
Symbol
(VSS = AVSS = 0.0 V)
Value
Min
Max
Unit
Power supply voltage
VCC
3.0
5.5
V
Smoothing capacitor
CS
0.1
1.0
µF
Operating temperature
Ta
−40
+85
°C
Remarks
Note : Use a ceramic capacitor or other capacitor with equivalent frequency characteristics. The capacitance of
the smoothing capacitor connected to the VCC pin must be greater than CS.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
C pin diagram
C
CS
77
MB90520A/520B Series
3. DC Characteristics
Parameter
“H” level input
voltage
Symbol
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
Pin Name
Condition
Value
Unit
Min
Typ
Max
VIHS
P20 to P27,
P30 to P37,
P53, P54,
P70 to P77,
P80 to P87,
PA0 to PA7
0.8 VCC

VCC +
0.3
V
VIHM
MD0 to MD2
VCC −
0.3

VCC +
0.3
V
VSS −
0.3

0.2 VCC
V
VCC = 3.0 V to 5.5 V
Remarks
VILS
P20 to P27,
P30 to P37,
P53, P54,
P70 to P77,
P80 to P87,
PA0 to PA7
VILM
MD0 to MD2
VSS −
0.3

VSS +
0.3
V
“H” level
output voltage
VOH
All output pins
VCC = 4.5 V
other than P90
IOH = −2.0 mA
to P97
VCC −
0.5


V
“L” level output
voltage
VOL
All output pins


0.4
V
All output pins
VCC = 5.5 V
other than P90
VSS < VI < VCC
to P97
−5

5
µA
Ileak
P90 to P97
output pins

0.1
5
µA
RUP
P00 to P07,
P10 to P17
P40 to P47,
MD0, MD1
50
100
200
kΩ
50
100
200
kΩ

40
65
mA

30
60
mA MB90F523B

30
40
mA
“L” level input
voltage
Input leak
current
Open-drain
output leak
current
Pull-up
resistor
Pull-down
resistor
Power supply
current*
IIL
VCC = 4.5 V
IOL = 2.0 mA


RDOWN MD2
ICC
VCC
For VCC = 5 V,
internal frequency
= 16 MHz,
normal operation
MB90522A/
523A
MB90522B/
523B
(Continued)
78
MB90520A/520B Series
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
Parameter
Symbol
Pin Name
Condition
For VCC = 5 V,
internal frequency
= 8 MHz,
normal operation
For VCC = 5 V,
internal frequency
= 16 MHz,
A/D operation in
progress
For VCC = 5 V,
internal frequency
= 8 MHz,
A/D operation in
progress
ICC
Power supply
current*
VCC
ICCS
ICCL
For VCC = 5 V,
internal frequency
= 16 MHz,
D/A operation in
progress
Value
Unit
Remarks
25
mA
MB90522A/
523A
15
20
mA MB90F523B

15
20
mA
MB90522B/
523B

50
70
mA
MB90522A/
523A

45
65
mA MB90F523B

35
45
mA
MB90522B/
523B

25
30
mA
MB90522A/
523A

20
25
mA MB90F523B

20
25
mA
MB90522B/
523B

55
70
mA
MB90522A/
523A

50
70
mA MB90F523B

40
50
mA
MB90522B/
523B
MB90522A/
523A
Min
Typ
Max

20

For VCC = 5 V,
internal frequency
= 8 MHz,
D/A operation in
progress

30
35
mA

25
30
mA MB90F523B

20
25
mA
Writing or erasing
flash memory

50
75
mA MB90F523B
For VCC = 5 V,
internal frequency
= 16 MHz,
sleep mode

8
15
mA
MB90522A/
523A

15
20
mA
MB90F523B
/522B/523B

7
10
mA
MB90522A/
523A

12
18
mA
MB90F523B
/522B/523B

0.1
1.0
MB90522A/
mA 523A/522B/
523B

4
7
mA MB90F523B
For VCC = 5 V,
internal frequency
= 8 MHz,
sleep mode
For VCC = 5 V,
internal frequency
= 8 kHz,
sub-clock mode,
Ta = 25 °C
MB90522B/
523B
(Continued)
79
MB90520A/520B Series
(Continued)
Parameter
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
Symbol
Pin Name
Value
Unit
Min
Typ
Max
For VCC = 5 V,
internal frequency
= 8 kHz,
sub-sleep mode,
Ta = 25 °C

30
50
µA
ICCT
For VCC = 5 V,
internal frequency
= 8 kHz,
clock mode,
Ta = 25 °C

15
30
µA
ICCH
Sleep mode,
Ta = 25 °C

5
20
µA
ICCLS
Power supply
current*
VCC
Input
capacitance
CIN
LCD divider
resistor
RLCD
Other than
AVCC, AVSS, C,
VCC, and VSS


10
80
pF
V0 − V1,
V1 − V2,
V2 − V3

50
100
200
kΩ


2.5
kΩ


15
kΩ


±5
µA
Output
impedance for
COM0 to
COM3
RVCOM COM0 to COM3
Output
impedance for
SEG00 to
SEG31
RVSEG
SEG00 to
SEG31
ILCDC
V0 to V3,
COM0 to
COM3,
SEG00 to
SEG31
LCDC leak
current
Condition
Remarks
V1 to V3 = 5.0 V

* : Current values are provisional and are subject to change without notice to allow for improvements to the characteristics. The power supply current is measured with an external clock.
80
MB90520A/520B Series
4. AC Characteristics
(1) Reset and Hardware Standby Input Timings
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
Symbol
Pin
Name
Reset input time
tRSTL
RST
Hardware standby input time
tHSTL
HST
Parameter
Condition

Value
Unit
Min
Typ
4 tCP*

ns
4 tCP*

ns
Remarks
* : See “ (3) Clock Timings” for more information about tCP (internal operating clock cycle time) .
tRSTL, tHSTL
RST
HST
0.2 VCC
0.2 VCC
Measurement conditions for AC ratings
Pin
CL is the load capacitance for the pin during testing.
CL
81
MB90520A/520B Series
(2) Power-On Reset
Parameter
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
Symbol
Pin
Name
tR
VCC
tOFF
VCC
Power supply rise time
Power supply cutoff time
Condition

Value
Unit
Remarks
Min
Typ
0.05
30
ms
*
4

ms
For repeated operation
* : VCC must be less than 0.2 V before power-on.
Notes : • The above rating values are for generating a power-on reset.
• When HST = “L”, always apply the power supply in accordance with the above ratings regardless of whether
a power-on reset is required.
• Some internal registers are only initialized by a power-on reset. Always apply the power supply in cordance
with the above ratings if you wish to initialize these registers.
tR
2.7 V
VCC
0.2 V
0.2 V
0.2 V
tOFF
Sudden changes in the power supply voltage may cause a power-on reset.
The recommended practice if you wish to change the power supply voltage while the device is operating is
to raise the voltage smoothly as shown below. Also, changes to the supply voltage should be performed when
the PLL clock is not in use. The PLL clock may be used, however, if the rate of voltage change is 1 V/s or less.
VCC
Recommended rate of voltage
rise is 50 mV/ms or less.
3.0 V
Maintain RAM data
VSS
82
MB90520A/520B Series
(3) Clock Timings
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
Value
Symbol
Pin
Name
Condition
Min
Typ
Max
FC
X0, X1

3

16
MHz
FCL
X0A, X1A


32.768

kHz
tHCYL
X0, X1

62.5

333
ns
tLCYL
X0A, X1A


30.5

µs
PWH
PWL
X0
10


ns
PWLH
PWLL
X0A

15.2

µs
Input clock rise/fall
time
tCR
tCF
X0



5
ns
Internal operating
clock frequency
fCP


1.5

16
MHz When using main clock
fLCP



8.192

kHz
When using sub-clock
tCP


62.5

666
ns
When using main clock
tLCP



122.1

µs
When using sub-clock
Parameter
Clock frequency
Clock cycle time
Input clock pulse width
Internal operating
clock cycle time
Unit

Remarks
Recommended duty
ratio = 30% to 70%
When using an
external clock
X0 and X1 clock timing
tHCYL
X0
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
PWH
PWL
tCR
tCF
X0A and X1A clock timing
tLCYL
X0A
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
PWLH
PWLL
tCF
tCR
83
MB90520A/520B Series
PLL guaranteed operation range
Relationship between internal operating clock frequency and power supply voltage
Guaranteed operation range for MB90V520A
Supply Voltage VCC (V)
5.5
PLL guaranteed
operation range
4.5
A/D, D/A guaranteed
voltage range
3.0
2.7
Guaranteed operation
range for MB90522A, 523A,
MB90522B, 523B, and F523B
1.5
10
8
Internal Clock fCP (MHz)
3
16
Relationship between oscillation frequency and internal operating clock frequency
×4
Internal Clock fCP (MHz)
16
×3
×2
×1
12
9
8
Divided by 2
6
4
3
2
3
4
6
8
12
Source Oscillation Clock fCP (MHz)
16
The AC ratings are measured at the following reference voltages.
Input signal waveform
Hysteresis input pin
Output pin
0.8 VCC
2.4 V
0.2 VCC
0.8 V
Pins other than hysteresis input or MD input pins
0.7 VCC
0.3 VCC
84
Output signal waveform
MB90520A/520B Series
(4) Clock Output Timings
Parameter
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
Symbol
Cycle time
tCYC
CLK ↑ → CLK ↓
tCHCL
Value
Pin
Name
Condition
CLK
VCC = 5.0 V ± 10%
Unit
Min
Typ
62.5

ns
20

ns
Remarks
tCYC
tCHCL
CLK
2.4 V
2.4 V
0.8 V
85
MB90520A/520B Series
(5) UART (SCI) Timings
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
Symbol
Pin Name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOV
Valid SIN → SCK ↑
tIVSH
SCK ↑ → valid SIN hold time
tSHIX
Serial clock “H” pulse width
tSHSL
Parameter
Serial clock “L” pulse width
tSLSH
SCK ↓ → SOT delay time
tSLOV
Valid SIN → SCK ↑
tIVSH
SCK ↑ → valid SIN hold time
tSHIX
Condition
Value
Typ
SCK0 to SCK2
8 tCP*

ns
SCK0 to SCK2
SOT0 to SOT2 Internal shift clock
mode, output pin
SCK0 to SCK2 load is
SIN0 to SIN2 CL = 80 pF + 1 TTL
SCK0 to SCK2
SIN0 to SIN2
−80
80
ns
100

ns
60

ns
SCK0 to SCK2
4 tCP*

ns
SCK0 to SCK2
CP*

ns

150
ns
60

ns
60

ns
SCK0 to SCK2 External shift clock
SOT0 to SOT2 mode, output pin
load is
SCK0 to SCK2
CL = 80 pF + 1 TTL
SIN0 to SIN2
SCK0 to SCK2
SIN0 to SIN2
4t
* : See “ (3) Clock Timings” for more information about tCP (internal operating clock cycle time) .
Notes : • These are the AC ratings for CLK synchronous mode.
• CL is the load capacitor connected to the pin for testing.
86
Unit
Min
Remarks
MB90520A/520B Series
Internal shift clock mode
tSCYC
SCK0 to SCK2
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
SOT0 to SOT2
0.8 V
tSHIX
tIVSH
SIN0 to SIN2
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
External shift clock mode
tSLSH
SCK0 to SCK2
tSHSL
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
tSLOV
2.4 V
SOT0 to SOT2
0.8 V
tIVSH
SIN0 to SIN2
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
87
MB90520A/520B Series
(6) Timer Input Timings
Parameter
Input pulse width
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
Symbol
Pin Name
Condition
tTIWH
tTIWL
IC00/01,
IC10/11
TI0, TI1

Value
Min
Typ
4 tCP*

Unit
Remarks
ns
* : See “ (3) Clock Timings” for more information about tCP (internal operating clock cycle time) .
0.8 VCC
0.8 VCC
IC00/01
IC10/11
TI0, TI1
0.2 VCC
tTIWL
tTIWH
(7) Timer Output Timings
Parameter
CLK ↑ → TOUT change time
0.2 VCC
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
Symbol
Pin Name
Condition
tTO
OUT0 to OUT7
PG00/01
PG10/11
TO0, TO1

Value
Min
Typ
30

2.4 V
CLK
tTO
TOUT
2.4 V
0.8 V
(TOUT : OUT0 to OUT7, PG00/01, PG10/11, TO0, TO1)
88
Unit
ns
Remarks
MB90520A/520B Series
5. Electrical Characteristics for the A/D Converter
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, 3.0 V ≤ AVRH − AVRL, Ta = −40 °C to +85 °C)
Symbol
Pin Name
Resolution

Total error
Parameter
Value
Unit
Remarks
Min
Typ
Max


8/10

bit




±5.0
LSB
Linearity error




±2.5
LSB
Differential linearity error




±1.9
LSB
Zero transition voltage
VOT
AN0 to AN7
AVSS
− 3.5 LSB
AVSS
+ 0.5 LSB
AVSS
+ 4.5 LSB
mV
Full-scale transition voltage
VFST
AN0 to AN7
AVRH
− 6.5 LSB
AVRH
− 1.5 LSB
AVRH
+ 1.5 LSB
mV
A/D conversion time


163 tcp


ns
At machine
clock = 16
MHz
Compare time


99 tcp


ns
At machine
clock = 16
MHz
Analog port input current
IAIN
AN0 to AN7


10
µA
Analog input voltage
VAIN
AN0 to AN7
AVRL

AVRH
V

AVRH
AVRL + 3.0

AVCC
V

AVRL
0

AVRH − 3.0
V
IA
AVCC

5

mA
IAH
AVCC


5
µA
Reference voltage
Power supply current
Reference voltage supply
current
IR
AVRH

400

µA
IRH
AVRH


5
µA
Variation between channels

AN0 to AN7


4
LSB
*
*
* : Current when 8/10-bit A/D converter not used and CPU in stop mode (VCC = AVCC = AVRH = 5.0 V)
Note : See “ (3) Clock Timings” in “4. AC Ratings” for more information about tCP (internal operating clock cycle time) .
89
MB90520A/520B Series
6. A/D Converter Glossary
Resolution
Linearity error
: The change in analog voltage that can be recognized by the A/D converter.
: The deviation between the actual conversion characteristics and the line linking the
zero transition point (“00 0000 0000B” ←→ “00 0000 0001B”) and the full scale transition point (“11 1111 1110B” ←→ “11 1111 1111B”) .
Differential linearity error : The variation from the ideal input voltage required to change the output code by 1 LSB.
Total error
: The total error is the difference between the actual value and the theoretical value.
This includes the zero-transition error, full-scale transition error, and linearity error.
Total Error
3FFH
3FEH
0.5 LSB
Actual conversion
characteristic
Digital Output
3FDH
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(Measured value)
003H
Actual conversion
characteristic
002H
Theoretical characteristic
001H
0.5 LSB
AVRL
1 LSB = (Theoretical value)
AVRH − AVRL
1024*
Total error for digital output N =
Analog Input
AVRH
[V]
VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB
[LSB]
VOT (Theoretical value) = AVRL + 0.5 LSB [V]
VFST (Theoretical value) = AVRH − 1.5 LSB [V]
VNT : Voltage at which digital output changes from (N − 1) to N
* : For 10-bit resolution, this value is 1024 (210) . For 8-bit resolution, this value is 256 (28) .
(Continued)
90
MB90520A/520B Series
(Continued)
Linearity Error
Differential Linearity Error
3FFH
Digital Output
3FDH
Actual conversion characteristic
{1 LSB × (N − 1)
+ VOT}
N+1
VFST
(Measured
value)
VNT
(Measured value)
004H
N
V (N + 1)T
(Measured value)
N−1
003H
002H
Actual conversion
characteristic
Digital Output
3FEH
Theoretical characteristic
Actual conversion
characteristic
Theoretical characteristic
VNT
(Measured value)
Actual conversion
characteristic
N−2
001H
VOT (Measured value)
AVRL
Analog Input
AVRH
AVRL
Analog Input
AVRH
VNT − {1 LSB × (N − 1) + VOT}
[LSB]
1 LSB
Differential linearity error for digital output N = V (N + 1) T − VNT − 1 LSB [LSB]
1 LSB
VFST − VOT
1 LSB =
[V]
1022*
Linearity error for digital output N =
VOT : Voltage at which digital output changes from “000H” to “001H”
VFST : Voltage at which digital output changes from “3FEH” to “3FFH”
* : For 10-bit resolution, this value is 1022 (210 − 2) . For 8-bit resolution, this value is 254 (28 − 2) .
91
MB90520A/520B Series
7. Notes for A/D Conversion
The recommended external circuit impedance of analog inputs for MB90V520 is approximately 5 kΩ or less,
that for MB90F523B is approximately 15.5 kΩ or less, and that for MB90522A/523A/522B/523B is approximately
10 kΩ or less.
If using an external capacitor, the capacitance should be several thousand times the level of the chip’s internal
capacitor to allow for the partial potential between the external and internal capacitance.
If the impedance of the external circuit is too high, the analog voltage sampling interval may be too short. (for
sampling time = 4 µs, machine clock frequency = 16 MHz) .
• Block diagram of analog input circuit model
Analog input
RON
C
Comparator
MB90522A/523A/522B/523B
RON = 2.2 kΩ approx.
C = 45 pF approx.
MB90F523B
RON = 2.6 kΩ approx.
C = 28 pF approx.
Note : The values listed are an indication only.
• Error
The relative error increases as |AVRH − AVRL| becomes smaller.
92
MB90520A/520B Series
8. Electrical Characteristics for the D/A Converter
Parameter
(AVCC = VCC = 5.0 V ± 10%, AVSS = VSS = DVSS = 0.0 V, Ta = −40 °C to +85 °C)
Value
Pin
Symbol
Unit
Remarks
Name
Min
Typ
Max
Resolution



8

bit
Differential linearity error




±0.9
LSB
Absolute accuracy




±1.2
%
Linearity error




±1.5
LSB
Conversion time



10
20
µs
Analog reference voltage

DVCC
VSS + 3.0

AVCC
V
Current consumption for
reference voltage
IDVR

120
300
µA


10
µA

20

kΩ
Analog output impedance
IDVRS
DVCC


For load capacitance
= 20 pF
Stop mode
9. Flash Memory Program/Erase
Parameter
Condition
Sector erase time
Chip erase time
Ta = + 25 °C
VCC = 5.0 V
Word (16-bit width)
programming time
Value
Unit
Remarks
Min
Typ
Max

1
15
s
Excludes 00H programming
prior erasure

5

s
Excludes 00H programming
prior erasure

16
3,600
µs
Excludes system-level overhead
Program/Erase cycle

10,000


cycle
Data hold time

100 K


h
93
MB90520A/520B Series
■ EXAMPLE CHARACTERISTICS
Power supply current (MB90523A)
ICC − VCC
Ta = +25 °C, External clock input
ICCS − VCC
Ta = +25 °C, External clock input
60
20
f = 16 MHz
f = 16 MHz
50
15
f = 10 MHz
30
f = 8 MHz
ICCS (mA)
40
ICC (mA)
f = 12 MHz
f = 12 MHz
f = 10 MHz
10
f = 8 MHz
5
f = 4 MHz
20
f = 2 MHz
f = 4 MHz
10
0
f = 2 MHz
2
3
4
VCC (V)
5
0
2
3
4
VCC (V)
5
6
6
ICCL − VCC
Ta = +25 °C, External clock input
ICCLS − VCC
Ta = +25 °C, External clock input
70
20
60
15
40
f = 8 kHz
30
ICCLS (µA)
ICCL (µA)
50
f = 8 kHz
10
5
20
10
0
0
2
3
4
VCC (V)
5
2
3
4
VCC (V)
5
6
6
(Continued)
94
MB90520A/520B Series
(Continued)
ICCT − VCC
Ta = +25 °C, External clock input
10
ICCT (µA)
8
6
4
f = 8 kHz
2
0
2
3
4
5
6
VCC (V)
Example MB90523A VOH − IOH Characteristics
Ta = +25 °C, VCC = 4.5 V
Example MB90523A VOL − IOL Characteristics
Ta = +25 °C, VCC = 4.5 V
900
900
800
800
700
700
600
600
VOL (mV)
1000
VCC − VOH (mV)
1000
500
500
400
400
300
300
200
200
100
100
0
0
1
2
3
4
5
6
7
IOH (mA)
8
9
10 11
12
0
0
1
2
3
4
5
6
7
IOL (mA)
8
9
10 11
12
95
MB90520A/520B Series
■ ORDERING INFORMATION
Part No.
96
Package
MB90522APFF
MB90523APFF
MB90522BPFF
MB90F523BPFF
120-pin, Plastic LQFP
(FPT-120P-M05)
MB90522APFV
MB90523APFV
MB90522BPFV
MB90F523BPFV
120-pin, Plastic QFP
(FPT-120P-M13)
Remarks
MB90520A/520B Series
■ PACKAGE DIMENSIONS
120-pin Plastic LQFP
(FPT-120P-M05)
* : Pins width and pins thickness include plating thickness.
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
120
31
"A"
0~8°
LEAD No.
1
0.40(.016)
30
0.16±0.03
(.006±.001)
0.07(.003)
M
0.145±0.055
(.006±.002)
0.50±0.20
(.020±.008)
0.45/0.75
(.018/.030)
C
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
1998 FUJITSU LIMITED F120006S-3C-4
Dimensions in mm (inches)
(Continued)
97
MB90520A/520B Series
(Continued)
120-pin Plastic QFP
(FPT-120P-M13)
* : Pins width and pins thickness include plating thickness.
22.60±0.20(.890±.008)SQ
20.00±0.10(.787±.004)SQ
90
0.145±0.055
(.006±.002)
61
91
60
0.08(.003)
Details of "A" part
+0.32
3.53 –0.20
+.013
.139 –.008
(Mouting height)
+0.10
0.20 –0.15
+.004
0°~8°
INDEX
31
120
"A"
LEAD No.
1
30
0.50(.020)
C
.008 –.006
(Stand off)
0.22±0.05
(.009±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
M
2000 FUJITSU LIMITED F120013S-c-3-5
Dimensions in mm (inches)
98
MB90520A/520B Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Marketing Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
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http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
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Europe
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Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fme.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmal.fujitsu.com/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
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Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0203
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
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