FUJITSU SEMICONDUCTOR CM44-10102-7E CONTROLLER MANUAL 2 F MC-16LX 16-BIT MICROCONTROLLER MB90570 series HARDWARE MANUAL 2 F MC-16LX 16-BIT MICROCONTROLLER MB90570 series HARDWARE MANUAL FUJITSU LIMITED PREFACE ■ Objectives and Intended Reader Thank you for your interest in Fujitsu semiconductor products. The MB90570 series was developed as one of the F2MC-16LX series general-purpose versions, or as a proprietary 16-bit one-chip microcontroller capable of supporting an application specific IC (ASIC). This manual, which is intended for engineers designing products using this semiconductor, explains the functions and operations of the MB90570 series. ■ Trademark F2MC is the abbreviation of FUJITSU Flexible Microcontroller. Other system and product names in this manual are trademarks of respective companies or organizations. The symbols ™ and ® are sometimes omitted in this manual. ■ The I2C Licence Purchase of FUJITSU I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ■ Structure of This Manual This manual includes the following 27 chapters and an appendix. CHAPTER 1 "OVERVIEW" This chapter describes an overview of the MB90570 series. CHAPTER 2 "CPU" This chapter describes the CPU functions and operations. CHAPTER 3 "INTERRUPT" This chapter describes the interrupt functions and operations. CHAPTER 4 "CLOCK AND RESET" This chapter describes the functions and operations of the clock and reset. CHAPTER 5 "LOW-POWER CONSUMPTION CONTROL CIRCUIT" This chapter describes the functions and operations of the low-power consumption control circuit. CHAPTER 6 "LOW-POWER CONSUMPTION MODE" This chapter describes the functions and operations of the low-power consumption mode. CHAPTER 7 "MEMORY ACCESS MODE" This chapter describes the functions and operations of the memory access modes. i CHAPTER 8 "I/O PORT" This chapter describes the functions and operations of the I/O port. CHAPTER 9 "TIMEBASE TIMER" This chapter describes the functions and operations of the Timebase Timer. CHAPTER 10 "WATCHDOG TIMER" This chapter describes the functions and operations of the Watchdog Timer. CHAPTER 11 "WATCH TIMER" This chapter describes the functions and operations of the Watch Timer. CHAPTER 12 "16-BIT I/O TIMER" This chapter describes the functions and operations of the 16-bit I/O timer. CHAPTER 13 "8/16-BIT I/O PPG" This chapter describes the functions and operations of the 8/16-bit PPG. CHAPTER 14 "8/16-BIT UP/DOWN COUNTER/TIMER" This chapter describes the functions and operations of the 8/16-bit up/down counter/timer. CHAPTER 15 "DTP/EXTERNAL INTERRUPT" This chapter describes the functions and operations of the DTP/external interrupt. CHAPTER 16 "DELAYED INTERRUPT REQUESTING MODULE" This chapter describes the functions and operations of the delayed interrupt requesting module. CHAPTER 17 "A/D CONVERTER" This chapter describes the functions and operations of the A/D converter. CHAPTER 18 "D/A CONVERTER" This chapter describes the functions and operations of the D/A converter. CHAPTER 19 "UART" This chapter describes the functions and operations of the UART. CHAPTER 20 "EXTENDED SERIAL I/O INTERFACE" This chapter describes the functions and operations of the extended serial I/O interface. CHAPTER 21 "I2C INTERFACE" This chapter describes the functions and operations of the I2C interface. CHAPTER 22 "CHIP SELECT FUNCTION" This chapter describes the functions and operations of the chip select function. CHAPTER 23 "CLOCK MONITOR FUNCTION" This chapter describes the functions and operations of the clock monitor function. CHAPTER 24 "ADDRESS MATCH DETECTION FUNCTION" This chapter describes the functions and operation of the address match detection function. CHAPTER 25 "ROM MIRROR FUNCTION SELECTION MODULE" This chapter describes the functions and operations of the ROM mirror function selection module. ii CHAPTER 26 "2M-BIT FLASH MEMORY" This chapter describes the functions and operations of 2M-bit flash memory. CHAPTER 27 "EXAMPLE OF MB90F574/A SERIAL PROGRAMMING CONNECTION" This chapter describes examples of serial programming connection with the AF220/AF210/ AF120/AF110 flash microcomputer programmer manufactured by YDC Corporation. APPENDIX This appendix describes an I/O map, an instructions list, and other information. iii • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. ©2001 FUJITSU LIMITED Printed in Japan iv CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 OVERVIEW ................................................................................................... 1 Features ................................................................................................................................................ 2 Product Lineup ...................................................................................................................................... 5 Block Diagram ....................................................................................................................................... 6 Pin Assignment ...................................................................................................................................... 7 Package Dimensions ............................................................................................................................. 8 Pin Description ..................................................................................................................................... 11 I/O Circuit Types .................................................................................................................................. 17 Notes on Handling Device ................................................................................................................... 20 CHAPTER 2 CPU ............................................................................................................. 23 2.1 Memory Space ..................................................................................................................................... 24 2.2 Addressing .......................................................................................................................................... 25 2.3 Allocating Many-Byte Length Data in a Memory Space ...................................................................... 28 2.4 Dedicated Registers ............................................................................................................................ 30 2.4.1 Accumulator (A) .............................................................................................................................. 32 2.4.2 User Stack Pointer (USP) and System Stack Pointer (SSP) .......................................................... 34 2.4.3 Processor Status (PS) .................................................................................................................... 36 2.4.4 Program Counter (PC) .................................................................................................................... 38 2.4.5 Direct Page Register (DPR) ........................................................................................................... 39 2.4.6 Bank Register ................................................................................................................................. 40 2.5 General-Purpose Registers ................................................................................................................. 41 2.6 Prefix Codes ........................................................................................................................................ 43 2.6.1 Restrictions on the Use of Prefix Instructions ................................................................................. 46 2.6.2 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions ......................................................... 48 CHAPTER 3 INTERRUPT ................................................................................................ 51 3.1 Overview of the Interrupt ..................................................................................................................... 52 3.2 Interrupt Source ................................................................................................................................... 53 3.3 Interrupt Vector .................................................................................................................................... 55 3.4 Hardware Interrupt ............................................................................................................................... 57 3.4.1 Operation ........................................................................................................................................ 60 3.4.2 Hardware Interrupt Operation Flowchart ........................................................................................ 63 3.4.3 Sample Use Procedure of Hardware Interrupt ............................................................................... 64 3.5 Software Interrupts .............................................................................................................................. 65 3.6 Extended Intelligent I/O Service (EI2OS) ............................................................................................. 67 3.6.1 Interrupt Control Register (ICR) ...................................................................................................... 70 3.6.2 Extended Intelligent I/O Service Descriptor (ISD) .......................................................................... 73 3.6.3 Registers of the Extended Intelligent I/O Service Descriptor (ISD) ................................................ 74 3.6.4 Operation ........................................................................................................................................ 77 3.6.5 Procedure for Using the Extended Intelligent I/O Service (EI2OS) ................................................ 78 3.6.6 EI2OS Execution Time .................................................................................................................... 79 3.7 Exception ............................................................................................................................................. 82 v CHAPTER 4 4.1 4.2 4.3 4.4 CLOCK AND RESET .................................................................................. 83 Clock Generator .................................................................................................................................. Clock Supply Map ............................................................................................................................... Reset Source ...................................................................................................................................... Operation after a Reset is Released .................................................................................................. CHAPTER 5 84 85 86 88 LOW-POWER CONSUMPTION CONTROL CIRCUIT ............................... 89 5.1 Overview of the Low-Power Consumption Control Circuit .................................................................. 90 5.2 Block Diagram of the Low-Power Consumption Control Circuit .......................................................... 93 5.3 Registers of the Low-Power Consumption Control Circuit .................................................................. 94 5.3.1 Low-Power Consumption Mode Control Register (LPMCR) .......................................................... 95 5.3.2 Clock Selection Register (CKSCR) ................................................................................................ 97 5.4 Status Transition for Clock Selection ................................................................................................ 100 CHAPTER 6 LOW-POWER CONSUMPTION MODE .................................................... 103 6.1 Low-Power Consumption Mode ........................................................................................................ 6.1.1 Sleep Mode .................................................................................................................................. 6.1.2 Pseudo Watch Mode ................................................................................................................... 6.1.3 Watch Mode ................................................................................................................................. 6.1.4 Stop Mode ................................................................................................................................... 6.1.5 Hardware Standby Mode ............................................................................................................. 6.2 Status Transition in Low-Power Consumption Mode ........................................................................ 6.3 Status Transition Diagram of Low-Power Consumption Mode ......................................................... CHAPTER 7 MEMORY ACCESS MODE ....................................................................... 125 7.1 Memory Access Modes ..................................................................................................................... 7.1.1 Mode Pins .................................................................................................................................... 7.1.2 Mode Data ................................................................................................................................... 7.1.3 Memory Space for Each Bus Mode ............................................................................................. 7.2 External Memory Access (External Bus Pin Control Circuit) ............................................................ 7.2.1 Automatic Ready Function Selection Register (ARSR) ............................................................... 7.2.2 External Address Output Control Register (HACR) ..................................................................... 7.2.3 Bus Control Signal Selection Register (ECSR) ............................................................................ 7.3 Operation of the External Memory Access Control Signal ................................................................ 7.3.1 Ready Function ............................................................................................................................ 7.3.2 Hold Function ............................................................................................................................... CHAPTER 8 9.1 vi 126 127 128 129 132 134 136 137 140 143 145 I/O PORT ................................................................................................... 147 8.1 Overview of the I/O Port .................................................................................................................... 8.2 Registers of the I/O Port ................................................................................................................... 8.2.1 Port Data Register (PDR) ............................................................................................................ 8.2.2 Port Direction Register (DDR) ...................................................................................................... 8.2.3 Output Pin Register (ODR) .......................................................................................................... 8.2.4 Input Resistor Register (RDR) ..................................................................................................... 8.2.5 Analog Input Enable Register (ADER) ......................................................................................... CHAPTER 9 104 107 108 110 112 114 115 119 148 150 152 155 157 158 160 TIMEBASE TIMER .................................................................................... 161 Overview of the Timebase Timer ...................................................................................................... 162 9.2 9.3 Timebase Timer Control Register (TBTC) ......................................................................................... 164 Operation of the Timebase Timer ...................................................................................................... 166 CHAPTER 10 WATCHDOG TIMER ................................................................................. 167 10.1 Overview of the Watchdog Timer ...................................................................................................... 168 10.2 Watchdog Timer Control Register (WDTC) ....................................................................................... 170 10.3 Operation of the Watchdog Timer ...................................................................................................... 172 CHAPTER 11 WATCH TIMER ......................................................................................... 173 11.1 Overview of the Watch Timer ............................................................................................................ 174 11.2 Watch Timer Control Register (WTC) ................................................................................................ 176 11.3 Operation of the Watch Timer ............................................................................................................ 178 CHAPTER 12 16-BIT I/O TIMER ...................................................................................... 179 12.1 Overview of the 16-Bit I/O Timer ...................................................................................................... 180 12.2 Block Diagram of the 16-Bit I/O Timer ............................................................................................... 182 12.3 16-Bit Input/Output Timer Register .................................................................................................... 183 12.4 16-Bit Free Run Timer ....................................................................................................................... 185 12.4.1 Timer Counter Data Register (TCDT) ........................................................................................... 186 12.4.2 Timer Counter Control Status Register (TCCS) ........................................................................... 187 12.5 Output Compare ................................................................................................................................ 190 12.5.1 Output Compare Register (OCCP0 to OCCP3) ........................................................................... 192 12.5.2 Output Compare Control Status Register (OCS0 to OCS3) ......................................................... 193 12.6 Input Capture ..................................................................................................................................... 196 12.6.1 Input Capture Data Register (IPCP0, IPCP1) ............................................................................... 198 12.6.2 Input Capture Control Status Register (ICS01) ............................................................................ 199 12.7 Operation of the 16-Bit Free Run Timer ............................................................................................ 201 12.8 Operation of the 16-Bit Output Compare ........................................................................................... 203 12.9 Operation of the 16-Bit Input Capture ................................................................................................ 206 CHAPTER 13 8/16-BIT PPG ............................................................................................ 209 13.1 Overview of the 8/16-Bit PPG ............................................................................................................ 210 13.2 Block Diagrams of the 8/16-Bit PPG .................................................................................................. 211 13.3 Registers of the 8/16-Bit PPG ............................................................................................................ 213 13.3.1 PPG0 Operating Mode Control Register (PPGC0) ....................................................................... 214 13.3.2 PPG1 Operating Mode Control Register (PPGC1) ....................................................................... 216 13.3.3 PPG0 and PPG1 Output Pin Control Register (PPG0E) .............................................................. 219 13.3.4 Reload Registers (PRLL and PRLH) ............................................................................................ 221 13.4 Operation of the 8/16-Bit PPG ........................................................................................................... 222 13.4.1 8/16-Bit PPG Operating Modes .................................................................................................... 223 13.4.2 8/16-Bit PPG Output Operation .................................................................................................... 224 13.4.3 Selecting the Count Clock for the 8/16-Bit PPG ........................................................................... 226 13.4.4 Controlling the Pulse Pin Output of the 8/16-Bit PPG .................................................................. 227 13.4.5 Timing of Writing the Reload Registers in the 8/16-Bit PPG ........................................................ 228 13.4.6 8/16-Bit PPG Interrupt .................................................................................................................. 229 13.4.7 Initial Value of Each Hardware Component in the 8/16-Bit PPG .................................................. 230 CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER ................................................... 231 vii 14.1 Overview of the 8/16-Bit Up/Down Counter/Timer ............................................................................ 14.2 Block Diagram of the 8/16-Bit Up/Down Counter/Timer ................................................................... 14.3 Registers of the 8/16-Bit Up/Down Counter/Timer ............................................................................ 14.3.1 Up/Down Count Register Ch.0/1 (UDCR0/1) ............................................................................... 14.3.2 Reload/Compare Register 0/1 (RCR0/1) ..................................................................................... 14.3.3 Counter Status Register 0/1 (CSR0/1) ......................................................................................... 14.3.4 Counter Control Register High Ch.0 (CCRH0) ............................................................................ 14.3.5 Counter Control Register High Ch.1 (CCRH1) ............................................................................ 14.3.6 Counter Control Register Low Ch.0/1 (CCRL0/1) ........................................................................ 14.4 Count Mode Selection for 8/16-Bit Up/Down Counter/Timer ............................................................ 14.5 Reload Function and Compare Function of 8/16-Bit Up/Down Counter/Timer ................................. 14.6 Simultaneous Activation of Reload/Compare Functions of 8/16-Bit Up/Down Counter/Timer .......... 14.7 Writing 8/16-Bit Up/Down Counter/Timer Data to UDCR .................................................................. 232 234 236 237 238 239 241 243 245 247 250 252 254 CHAPTER 15 DTP/EXTERNAL INTERRUPT ................................................................. 257 15.1 Overview of the DTP/External Interrupt ............................................................................................ 15.2 Registers of the DTP/External Interrupt ............................................................................................ 15.2.1 DTP/Interrupt Enable Register (ENIR) ......................................................................................... 15.2.2 DTP/Interrupt Source Register (EIRR) ......................................................................................... 15.2.3 Request Level Setting Register (ELVR) ....................................................................................... 15.3 Operation of the DTP/External Interrupt ........................................................................................... 15.4 Notes on Using the DTP/External Interrupt ....................................................................................... 258 259 260 261 262 264 267 CHAPTER 16 DELAYED INTERRUPT REQUESTING MODULE .................................. 269 16.1 Overview of the Delayed Interrupt Requesting Module .................................................................... 270 16.2 Operation of the Delayed Interrupt Requesting Module .................................................................... 271 CHAPTER 17 A/D CONVERTER ..................................................................................... 273 17.1 Overview of the A/D Converter ......................................................................................................... 17.2 Registers of the A/D Converter ......................................................................................................... 17.2.1 Control Status Register (ADCS1, ADCS2) .................................................................................. 17.2.2 Data Register (ADCR1, ADCR2) ................................................................................................. 17.3 Operation of the A/D Converter ........................................................................................................ 17.3.1 Conversion Using EI2OS ............................................................................................................. 17.3.2 Example of Activating EI2OS in the Single Mode ........................................................................ 17.3.3 Example of Activating EI2OS in the Continuous Mode ................................................................ 17.3.4 Example of Activating EI2OS in the Stop Mode ........................................................................... 17.4 Notes on Using the A/D Converter .................................................................................................... 17.5 Conversion Data Protection Function ............................................................................................... 274 276 277 282 284 286 287 289 291 293 294 CHAPTER 18 D/A CONVERTER ..................................................................................... 297 18.1 Overview of the D/A Converter ......................................................................................................... 298 18.2 Registers of the D/A Converter ......................................................................................................... 300 18.3 Operation of the D/A Converter ........................................................................................................ 302 CHAPTER 19 UART ........................................................................................................ 303 19.1 Overview of the UART ...................................................................................................................... 304 19.2 Block Diagram of the UART .............................................................................................................. 305 viii 19.3 Registers of the UART ....................................................................................................................... 306 19.3.1 Serial Mode Register (SMR) ......................................................................................................... 307 19.3.2 Serial Control Register (SCR) ...................................................................................................... 309 19.3.3 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) ...................................... 312 19.3.4 Serial Status Register (SSR) ........................................................................................................ 313 19.3.5 Communication Prescaler Control Register (CDCR) .................................................................... 316 19.4 UART Baud Rates ............................................................................................................................. 318 19.5 Operation of the UART ...................................................................................................................... 321 19.5.1 Asynchronous (Start-stop Synchronous) Mode ............................................................................ 322 19.5.2 CLK Synchronous Mode ............................................................................................................... 323 19.6 Flags and Interrupt Sources of the UART .......................................................................................... 325 19.6.1 Timing to Set an Interrupt and Flag of the UART ......................................................................... 326 19.7 Applications of the UART and Precautions ........................................................................................ 329 CHAPTER 20 EXTENDED SERIAL I/O INTERFACE ...................................................... 331 20.1 Overview of the Extended Serial I/O Interface .................................................................................. 332 20.2 Registers in the Extended Serial I/O Interface ................................................................................... 334 20.2.1 Serial Mode Control Status Register (SMCS) .............................................................................. 335 20.2.2 Serial Shift Data Register (SDR) .................................................................................................. 339 20.3 Operation of the Extended Serial I/O Interface .................................................................................. 340 20.3.1 Shift Clock .................................................................................................................................... 341 20.3.2 Operating States of the Extended Serial I/O Interface ................................................................. 342 20.3.3 Operation Timings of the Extended Serial I/O Interface ............................................................... 344 20.3.4 Serial Data I/O Shift Timings ........................................................................................................ 346 20.3.5 Interrupt Function of the Extended Serial I/O Interface ................................................................ 347 CHAPTER 21 I2C INTERFACE ........................................................................................ 349 21.1 Overview of the I2C Interface ............................................................................................................. 350 21.2 Block Diagram of the I2C Interface .................................................................................................... 351 21.3 I2C Interface Registers ..................................................................................................................... 352 21.3.1 Bus Status Register (IBSR) .......................................................................................................... 353 21.3.2 Bus Control Register (IBCR) ........................................................................................................ 356 21.3.3 Clock Control Register (ICCR) ..................................................................................................... 359 21.3.4 Address Register (IADR) ............................................................................................................. 362 21.3.5 Data Register(IDAR) ..................................................................................................................... 363 21.4 Operation of the I2C Interface ............................................................................................................ 364 21.4.1 Operation Flow of the I2C Interface .............................................................................................. 366 CHAPTER 22 CHIP SELECT FUNCTION ....................................................................... 369 22.1 22.2 22.3 22.4 Overview of the Chip Select Function ................................................................................................ 370 Register of the Chip Select Function ................................................................................................. 371 Operation of the Chip Select Function ............................................................................................... 372 Decode Address Space of the Chip Select Function ......................................................................... 373 CHAPTER 23 CLOCK MONITOR FUNCTION ................................................................ 377 23.1 Clock Monitor Function ...................................................................................................................... 378 23.2 Clock Output Enable Register (CLKR) .............................................................................................. 379 ix CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION .......................................... 381 24.1 Overview of the Address Match Detection Function ......................................................................... 24.2 Registers of the Address Match Detection Function ......................................................................... 24.2.1 Program Address Detection Registers (PADR0 and PADR1) ..................................................... 24.2.2 Program Address Detection Control Status Register (PACSR) ................................................... 24.3 Operation of the Address Match Detection Function ........................................................................ 24.4 Example of the Address Match Detection Function .......................................................................... 24.5 Example and Flow of Program Patch Processing ............................................................................. 382 383 384 385 386 387 389 CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE ................................. 391 25.1 Overview of the ROM Mirror Function Selection Module .................................................................. 392 25.2 Register of the ROM Mirror Function Selection Module ................................................................... 393 CHAPTER 26 2M-BIT FLASH MEMORY ........................................................................ 395 26.1 Overview of the 2M-Bit Flash Memory .............................................................................................. 26.2 Sector Configuration of the 2M-Bit Flash Memory ............................................................................ 26.3 Flash Memory Control Status Register (FMCS) ............................................................................... 26.4 Method for Activating Flash Memory Automatic Algorithm ............................................................... 26.5 Checking Automatic Algorithm Execution Status .............................................................................. 26.5.1 Data Polling Flag (DQ7) ............................................................................................................... 26.5.2 Toggle Bit Flag (DQ6) .................................................................................................................. 26.5.3 Timing Limit Excess Flag (DQ5) .................................................................................................. 26.5.4 Sector Erase Timer Flag (DQ3) ................................................................................................... 26.6 Detailed Explanation of Flash Memory Write/Erase ......................................................................... 26.6.1 Read/Reset .................................................................................................................................. 26.6.2 Data Write .................................................................................................................................... 26.6.3 Data Erase (All Chip Erase) ......................................................................................................... 26.6.4 Data Erase (Sector Erase) ........................................................................................................... 26.6.5 Sector Erase Temporary Stop ..................................................................................................... 26.6.6 Sector Erase Restart ................................................................................................................... 26.7 Example of Flash Memory Program ................................................................................................. 396 397 398 401 402 404 406 407 408 409 410 411 413 414 416 417 418 CHAPTER 27 EXAMPLES OF MB90F574/A SERIAL PROGRAMMING CONNECTION ..... 423 27.1 27.2 27.3 27.4 27.5 Basic Configuration of MB90F574/A Serial Programming Connection ............................................. Example of Serial Programming Connection (User Power Supply Used) ........................................ Example of Serial Programming Connection (Power Supplied from the Programmer) .................... Example of Minimum Connection to Flash Microcomputer Programmer (User Power Supply Used) Example of Minimum Connection to Flash Microcomputer Programmer (Power Supplied from the Programmer) ............................................................................................ 424 427 429 431 433 APPENDIX .......................................................................................................................... 435 APPENDIX A I/O Map ............................................................................................................................. APPENDIX B INSTRUCTIONS ............................................................................................................... B.1 Instruction Types ............................................................................................................................ B.2 Addressing ..................................................................................................................................... B.3 Direct Addressing ........................................................................................................................... B.4 Indirect Addressing ......................................................................................................................... x 436 443 444 445 447 452 B.5 B.6 B.7 B.8 B.9 Execution Cycle Count .................................................................................................................... 458 Effective Address Field ................................................................................................................... 461 How to Read the Instruction List ..................................................................................................... 462 F2MC-16LX Instruction List ............................................................................................................. 465 Instruction Map ................................................................................................................................ 479 INDEX ...................................................................................................................................501 xi xii CHAPTER 1 OVERVIEW This chapter describes an overview of the MB90570 series. 1.1 "Features" 1.2 "Product Lineup" 1.3 "Block Diagram" 1.4 "Pin Assignment" 1.5 "Package Dimensions" 1.6 "Pin Description" 1.7 "I/O Circuit Types" 1.8 "Notes on Handling the Device" 1 CHAPTER 1 OVERVIEW 1.1 Features MB90570 is a general-purpose Fujitsu 16-bit microcontroller designed for process control requiring high-speed realtime processing for welfare products. ■ Features In addition to inheriting the FMC series AT architecture, the MB90570 series instruction system adds high-level language support instructions, expands addressing modes, enhances multiplication and division instructions, and provides rich bit processing. The system also enables long-word data processing by mounting a 32-bit accumulator. The series contains an I2CBUS interface to enable simplified communication between devices and is suitable for auto audio and VTR systems. ❍ Minimum instruction execution time: 62.5 ns/4 MHz, oscillation frequency multiplied by four (PLL clock multiplication system) ❍ Maximum memory space: 16M bytes ❍ Instruction system optimized for the controller • Data types that can be handled: bits, bytes, words, and long words • Standard addressing modes: 23 types • Enhancing high-precision arithmetic operation using the 32-bit accumulator • Enhancing signed multiplication and division instructions and RETI instructions ❍ Instruction system supporting the high-level language (C) and multitasking • Using the system stack pointer • Instruction set symmetric and barrel shift instructions ❍ Program patch function (For two address pointers) ❍ Execution speed improvement: 4-byte queue ❍ Powerful interrupt function • Programmable setting of eight priority levels • External interrupt input: 8 channels ❍ Data transfer function 2 • Intelligent I/O service • Maximum 16 channels • DTP request input: 8 channels (bidirectional edge can be set for two. No level detection can be set.) 1.1 Features ❍ Internal ROM size and ROM type • MASK-ROM: 128 KB/256 KB • FLASH-ROM: 256 KB • Internal RAM sizes • FLASH: 10 KB • EVA: Max. 10 KB • MASK-ROM: 6 KB/10 KB ❍ General-purpose ports • Up to 97 ports • Input pull-up resistor setting possible: 24 (ports 0, 1, 6) • Open-drain setting possible: 8 (with diode clamps for port 4) ❍ I2CBUS interface: 1 channel ❍ Chip select output: 8 (active level setting possible) ❍ A/D converter (RC successive approximation type) • Resolution: 8 or 10 bits: 8 channels (multiplexing) • Conversion time: 26.3 µ ❍ D/A converter (R-2R system) • Resolution (8 bits): 2 channels (independent) • Setup time: 12.5 µs ❍ UART (full-duplex double buffer system): 2 channels ❍ Extended I/O serial interface: 3 channels ❍ 8/16-bit up/down counter: 1 channel (8 bits x 2 channels) ❍ 8/16-bit PPG timer: 1 channel (8 bits x 2 channels) ❍ I/O timer: 1 channel • 16-bit free-run timer • 16-bit input capture x 2 channels • 16-bit output compare x 4 channels 3 CHAPTER 1 OVERVIEW ❍ Clock output function ❍ Watch timer: 1 channel ❍ 18-bit timebase and watchdog timer (18 bits) ❍ Low-power consumption mode Sleep, stop, hardware standby, CPU intermittent operation mode function ❍ Package • • LQFP-120 • FPT-120P-M21 (lead pitch 0.5 mm): (None for MB90573 and MB90574) • FPT-120P-M05 (lead pitch 0.4 mm): (None for MB90574C) QFP-120 • FPT-120P-M13 (lead pitch 0.5 mm) ❍ CMOS technology 4 1.2 Product Lineup 1.2 Product Lineup Table 1.2-1 "Product Lineup (MB90570 Series)" lists the products available. Products whose product numbers end with the letter A or C are different to those having product numbers without the letter A or C in that a return from standby mode is possible using an interrupt generated by a ch0 to ch1 edge request when a DTP/ external interrupt occurs. ■ roduct Lineup Table 1.2-1 Product Lineup (MB90570 Series) MB90V570 MB90V570A MB90F574/A MB90573 MB90574 MB90574C ROM size - - 256 Kbyte 128 Kbyte 256 Kbyte 256 Kbyte RAM size 10 Kbyte 10 Kbyte 10 Kbyte 6 Kbyte 10 Kbyte 10 Kbyte EVA products EVA products FLASH products MASK products MASK products MASK products None None - - - - Others Exclusive power supply for the emulator* * : Select this dip switch S2 setting when using the evaluation pod MB2145-507. For details, see the "MB2145-507 Hardware Manual (exclusive power supply pin for emulator)". 5 CHAPTER 1 OVERVIEW 1.3 Block Diagram Figure 1.3-1 "Block Diagram" shows the block diagram. ■ Block Diagram Figure 1.3-1 Block Diagram (AD00-AD07) P00-P07 Clock control circuit RAM Interrupt controller ROM Port 7 Port 1 P30-P37 ALE/RDX WRHX/WRLX HRQ/HAKX RDY/CLK Port 3 Port 2 Port 4 SIN0, 1 SOT0, 1 UART x 2ch SCK0, 1 PPG0, 1 PPG x 1ch P50-P57 SIN2, 3 SOT2, 3 SCK2, 3 IN0, 1 D/AC X 2ch Port 0 (AD08-AD15) P10-P17 (A16-A23) P20-P27 P40-P47 CKOT Chip select Port A Up/down counter Port C Input capture P70-P74 DA0, 1 DVCC, SS P80-P87 AVRL, H AN0-7 AVCC, SS P90-P97 CS0-6 PA0-PA7 AIN0, 1 BIN0, 1 ZIN0, 1 SCL, SDA PB0-PB7 ADTG IRQ0-IRQ5 PC0-PC3 Notes: The evaluation device (MB90V570/A) has no internal ROM. The capacity of the internal RAM is 10 KB. The internal resources are shared. The package is PGA-256C-A02. SIO x 1ch Port 6 Clock output P00-P07 (8): P10-P17 (8): P60-P67 (8): P40-P47 (8): 6 Port 9 External interrupt x 8 channels SIO x 2ch Output capture A/DC x 8ch Port B Port 5 OUT0-3 Port 8 I2C bus 16-bit free-run timer SIN4 SOT4 SCK4 P60-P67 F2MC-16LX core Internal data bus X0, X1 X0A, X1A RSTX, HSTX With the input pull-up resistor setting register With the input pull-up resistor setting register With the input pull-up resistor setting register With the open-drain setting register 1.4 Pin Assignment 1.4 Pin Assignment Figure 1.4-1 "Pin Assignment" shows the pin assignment. ■ Pin Assignment Figure 1.4-1 Pin Assignment 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 119 117 115 113 111 109 107 105 103 101 99 97 95 93 91 1 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 TT 23 01 0123 456 7 01234 5 7 CHAPTER 1 OVERVIEW 1.5 Package Dimensions The MB90570 series supports three types of packages. ■ Package Dimensions of FPT-120P-M05 Figure 1.5-1 External Dimensions of FTP-120P-M05 EIAJ code :∗P-LQFP-0120-1414-0.40 120-pin plastic LQFP Lead pitch 0.40 mm Package width × package length 14.0 × 14.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.62 g (FPT-120P-M05) 120-pin plastic LQFP (FPT-120P-M05) ∗Pins width and pins thickness include plating thickness. 16.00±0.20(.630±.008)SQ 14.00±0.10(.551±.004)SQ 90 61 91 60 0.08(.003) Details of "A" part +0.20 1.50 Ð0.10 +.008 (Mounting height) .059 Ð.004 INDEX 120 31 "A" 0~8¡ LEAD No. 1 0.40(.016) 3 0.16±0.03 (.006±.001) 0 0.07(.003) M 0.145±0.055 (.006±.002) 0.50±0.20 (.020±.008) 0.45/0.75 (.018/.030) C 8 1998 FUJITSU LIMITED F120006S-3C-4 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) Dimensions in mm (inches). 1.5 Package Dimensions ■ Package Dimensions of FPT-120P-M13 Figure 1.5-2 External Dimensions of FTP-120P-M13 EIAJ code : P-FQFP120-20 × 20-0.50 120-pin plastic QFP Lead pitch 0.50 mm Package width × package length 20.0 × 20.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.85 mm MAX Weight 2.58g (FPT-120P-M13) 120-pin plastic QFP (FPT-120P-M13) ∗Pins width and pins thickness include plating thickness. 22.60±0.20(.890±.008)SQ 20.00±0.10(.787±.004)SQ 90 0.145±0.055 (.006±.002) 61 91 60 0.08(.003) Details of "A" part +0.32 3.53 Ð0.20 +.013 .139 Ð.008 (Mouting height) +0.10 0.20 Ð0.15 +.004 0¡~8¡ INDEX 31 120 "A" LEAD No. 1 30 0.50(.020) C .008 Ð.006 (Stand off) 2000 FUJITSU LIMITED F120013S-c-3-5 0.22±0.05 (.009±.002) 0.08(.003) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.25(.010) M Dimensions in mm (inches). 9 CHAPTER 1 OVERVIEW ■ Package Dimensions of FPT-120P-M21 Figure 1.5-3 External Dimensions of FTP-120P-M21 EIAJ code :∗P-LQFP-0120-1616-0.50 120-pin plastic LQFP Lead pitch 0.50 mm Package width × package length 16.0 × 16.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 0.88 g (FPT-120P-M21) 120-pin plastic LQFP (FPT-120P-M21) 18.00±0.20(.709±.008)SQ 16.00±0.10(.630±.004)SQ 90 61 60 91 0.08(.003) Details of "A" part +0.20 1.50 Ð0.10 +.008 (Mounting height) .059 Ð.004 INDEX 120 LEAD No. 1 30 0.50(.020) C 10 0~8¡ "A" 31 1998 FUJITSU LIMITED F120033S-2C-2 0.22±0.05 (.009±.002) 0.08(.003) M 0.145 .006 +0.05 Ð0.03 +.002 Ð.001 0.45/0.75 (.018/.030) 0.10±0.05 (.004±.002) (Stand off) 0.25(.010) Dimensions in mm (inches). 1.6 Pin Description 1.6 Pin Description Table 1.6-1 "Pin Description" provides a list of pin function explanations. ■ Pin Description Table 1.6-1 Pin Description Pin No. Pin name Circuit type 92/93 X0/X1 A High-speed oscillation input pin 74/73 X0A/X1A B Low-speed oscillation input pin 90 RSTX C Reset input pin 86 HSTX C Hardware standby input pin D General-purpose output port. At input setting, this port can be set with the pull-up resistor setting register (RDR0). At output setting, this port is invalidated. P00 to 07 95 to 102 Explanation of function AD00 to 07 In external bus mode, function as lower address output and lower data I/O pins. P10 to 17 General-purpose I/O port. At input setting, this port can be set with the pull-up resistor setting register (RDR1). At output setting, this port is invalidated. 103 to 110 D In external bus mode, function as the middle address output and higher data I/O pins. AD08 to 15 P20 to 27 111 to 118 General-purpose I/O port E A16 to 23 P30 120 In external bus mode, function as the higher address output pins. General-purpose I/O port E ALE In external bus mode, used as an address latch enable signal output pin. P31 General-purpose I/O port 1 E RDX In external bus mode, used as a read strobe signal output pin. P32 General-purpose I/O port 2 E WRLX P33 3 General-purpose I/O port E WRHX In external bus mode, used as the pin for outputting the data bus lower 8 bits write strobe signal. In external bus mode, used as the pin for outputting the data bus higher 8 bits write strobe signal. 11 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Description (Continued) Pin No. Pin name Circuit type P34 4 General-purpose I/O port E HRQ In external bus mode, used as a hold request signal input pin. P35 General-purpose I/O port 5 E HAKX P36 6 In external bus mode, used as a hold acknowledge signal output pin. General-purpose I/O port E RDY In external bus mode, used as a ready signal input pin. P37 General-purpose I/O port 7 E CLK In external bus mode, used as a clock (CLK) signal output pin. P40 General-purpose I/O port that can be set in the open-drain by the ODR4 register. SIN0 UART Ch.0 serial data input pin. Because this input pin can be used whenever UART Ch.0 is performing an input operation, the output function must be used for intentional use only. When using this pin together with other function outputs, place in a status in which output is disabled during a SIN operation. P41 General-purpose I/O port. This port can be set in the opendrain with the ODR4 register. 9 F 10 F UART Ch.0 serial data output pin. This pin is validated when UART Ch.0 allows the data output specification. SOT0 General-purpose I/O port. This port can be set in the opendrain with the ODR4 register. P42 11 F SCK0 UART Ch.0 serial clock I/O pin. This pin is validated when UART Ch.0 allows the clock output specification. P43 General-purpose I/O port. This port can be set in the opendrain with the ODR4 register. SIN1 UART Ch.1 serial data input pin. Because this input can be used whenever UART Ch.1 is performing an input operation, use the input function for intentional use only. To use this pin together with other function outputs, place in a status in which the output is disabled during a SIN operation. P44 General-purpose I/O port. This port can be set in the opendrain with the ODR4 register. 12 F 13 F SOT1 12 Explanation of function UART Ch.1 serial data output pin that is validated when UART Ch.1 allows the data output specification. 1.6 Pin Description Table 1.6-1 Pin Description (Continued) Pin No. Pin name Circuit type General-purpose I/O port. This port can be set in the opendrain with the ODR4 register. P45 14 Explanation of function F SCK1 UART Ch.1 serial clock I/O pin that is validated when UART Ch.1 allows the clock output specification. P46 to 47 General-purpose I/O port. This port can be set in the opendrain with the ODR4 register. 15 to 16 F PPG0 and PPG1 output pins that are valid when the output specifications of PPG0 and PPG1 are allowed. PPG0 to 1 P50 General-purpose I/O port SIN2 I/O serial Ch.0 data input pin. Because this input can be used whenever serial data is input, use the output for intentional use only. P51 General-purpose I/O port 17 E 18 E SOT2 P52 19 I/O serial Ch.0 data output pin that is valid when serial data output of serial Ch.0 is allowed. General-purpose I/O port E SCK2 P53 Serial clock I/O pin of I/O serial Ch.0 that is validated when the serial clock output of serial Ch.0 is allowed. General-purpose I/O port SIN3 I/O serial Ch.1 data input pin. Because this data input pin can be used whenever serial data is input, use the output for intentional use only. P54 General-purpose I/O port 20 E 21 E SOT3 P55 22 General-purpose I/O port E SCK3 P56 to 57 23 to 24 Serial clock I/O pin of I/O serial Ch.1 that is validated when the serial clock output of serial Ch.1 is allowed. General-purpose I/O port E IN0 to 1 Input capture Ch.0/1 trigger input pin. Because this trigger input pin function can be used whenever input capture Ch.0/ 1 is performing an input operation. Allow the output for intentional use only. General-purpose I/O port. At input setting, this port can be set with the pull-up resistor setting register (RDR6). At output setting, this port is invalid. P60 25 Data output pin of I/O serial Ch.1 that is validated when the serial data output of serial Ch.1 is allowed. D SIN4 I/O serial Ch.2 data input pin. Because this data input pin can be used whenever serial data is input, use the output for intentional use only. 13 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Description (Continued) Pin No. Pin name Circuit type P61 26 D General-purpose I/O port. At input setting, this port can be set with the pull-up resistor setting register (RDR6). At output setting, this port is invalid. SOT4 Data output pin of I/O serial Ch.2 that is validated when the serial data output of serial Ch.2 is allowed. P62 General-purpose I/O port. At input setting, this port can be set with the pull-up resistor setting register (RDR6). At output setting, this port is invalid. 27 D SCK4 Serial clock I/O pin of I/O serial Ch.2 that is validated when the serial clock output of serial Ch.2 is allowed. P63 General-purpose I/O port. At input setting, this port can be set with the pull-up resistor setting register (RDR6). At output setting, this port is invalid. 28 D CKOT Clock monitor function output pin that is validated when the clock monitor output is allowed. P64 to 67 General-purpose I/O port. At input setting, this port can be set with the pull-up resistor setting register (RDR6). At output setting, this port is invalid. 29 to 32 D Output compare Ch.0-3 event output pins are validated when each channel attains output enable status. OUT0 to 3 34 C G Power supply stabilization capacity pin. Connect an external 0.1 µ ceramic capacitor. This connection is unnecessary for FLASH products (MB90F574/A) and for MB90574C. 35 to 37 P70 to 72 E General-purpose I/O port 38 DVCC H D/A converter Vref input pin. Do not exceed VCC. 39 DVSS H D/A converter GND power supply pin. Set the same VSS voltage. P73 to 74 40 to 41 General-purpose I/O port I DA0 to 1 Analog signal output pins of D/A converter Ch.0,1 42 AVCC H VCC power supply input pin of the analog macro (D/A, A/D, and others) 43 AVRH J A/D converter Vref+ input pin. Do not exceed VCC. 44 AVRL H A/D converter Vref- input pin. Must not be equal to or less than VSS. 45 AVSS H VSS power supply input pin of the analog macro (D/A, A/D, and others) P80 to 87 46 to 53 General-purpose I/O port K AN0 to 7 14 Explanation of function A/D converter analog input pin is a function that is validated when the analog input specification is allowed. 1.6 Pin Description Table 1.6-1 Pin Description (Continued) Pin No. Pin name Circuit type P90 to 97 55 to 62 General-purpose I/O port E CS0 to 7 PA0 64 AIN0 Chip select output pin is a function that is validated when the chip select output is allowed. General-purpose I/O port E Can be used as the count clock A input of 8/16-bit up-down counter Ch.0. IRQ6 Can be used as interrupt request input Ch.6. PA1 General-purpose I/O port 65 E BIN0 Can be used as the count clock B input of 8/16-bit up-down counter Ch.0. PA2 General-purpose I/O port 66 67 Explanation of function E ZIN0 Can be used as the control clock Z input of 8/16-bit up-down counter Ch.0. PA3 General-purpose I/O port AIN1 E Can be used as the count clock A input of 8/16-bit up-down counter Ch.1. IRQ7 Can be used as interrupt request input Ch.7. PA4 General-purpose I/O port 68 E BIN1 Can be used as the count clock B input of 8/16-bit up-down counter Ch.1. PA5 General-purpose I/O port 69 E ZIN1 Can be used as the control clock Z input of 8/16-bit up-down counter Ch.1. PA6 General-purpose I/O port SDA This is the data I/O pin of the I2C interface. Using this pin is effective when the operation of the I2C interface is allowed. Set the port output to input setting (DDRA: bit 6 = 0) while the I2C interface is operating. PA7 General-purpose I/O port 70 L 71 L SCL This is the clock I/O pin of the I2C interface. Using this pin is effective when the operation of the I2C interface is allowed. Set the port output to input setting (DDRA: bit 7 = 0) while the I2C interface is operating. 15 CHAPTER 1 OVERVIEW Table 1.6-1 Pin Description (Continued) Pin No. Pin name Circuit type PB0 to 5 General-purpose I/O port IRQ0 to 5 Because external interrupt input pins IRQ0 and IRQ1 can detect both edges but cannot detect interrupt sources based on levels, these pins cannot be used for the return from STOP in MB90V570, MB90F574, MB90573, and MB90574. However, for MB90V570A, MB90F574A, and MB90574C, a return from STOP is possible by the edge detection of IRQ0 and IRQ1. 72, 75 to 79 E PB6 80 General-purpose I/O port E ADTG 16 Explanation of function Because the A/D converter external trigger input pin can be used whenever the A/D converter is performing an input operation, in cases other than intentional use, place this pin in output stop status. 81 PB7 E General-purpose I/O port 82 to 85 PC0 to 3 E General-purpose I/O port 88, 89 MD1, MD0 C Operating mode selection input pin must be connected directly (direct coupling) to VCC or VSS. 87 MD2 C Operating mode selection input pin must be connected directly (direct coupling) to VCC or VSS. 8, 54, 94 VCC - Power supply (5 V) input pin 33, 63, 91, 119 VSS - Power supply (0 V) input pin 1.7 I/O Circuit Types 1.7 I/O Circuit Types Table 1.7-1 "I/O Circuit Types" lists the I/O circuit types. ■ I/O Circuit Types Table 1.7-1 I/O Circuit Types Classification Circuit Remarks X1 Xout Oscillation circuit • High-speed oscillation feedback resistor = approx. 1 MΩ A X0 Standby control signal X1A Xout B Oscillation circuit • Low-speed oscillation feedback resistor = approx. 1 MΩ X0A Standby control signal R C Hysteresis inputs Pull-up control R Pout D Nout Hysteresis input pin • Resistor value : approx. 50 KΩ (TYP) CMOS hysteresis input pin with input pull-up control • CMOS level output • CMOS hysteresis inputs (With the standby-time input shutdown function) • Pull-up resistor value: Approx. 50 KΩ (TYP), IOL = 4 mA R Hysteresis inputs Standby control for input shutdown 17 CHAPTER 1 OVERVIEW Table 1.7-1 I/O Circuit Types (Continued) Classification Circuit Remarks CMOS hysteresis I/O pin • CMOS level output • CMOS hysteresis inputs (With the standby-time input shutdown function), IOL = 4 mA Pout E Nout R Hysteresis inputs Standby control for input shutdown CMOS hysteresis I/O pin • CMOS level output • CMOS hysteresis inputs (With the standby-time input shutdown function), IOL = 10 mA (Heavycurrent port) Pout F Nout R Hysteresis inputs Standby control for input shutdown C pin output (Capacitor connection pin) N.C. pin for MB90F574/A G Analog power supply input protection circuit H 18 AVR 1.7 I/O Circuit Types Table 1.7-1 I/O Circuit Types (Continued) Classification Circuit Remarks • • Pout • Nout I R CMOS hysteresis I/O Pin for both analog and CMOS outputs (No CMOS output at analog output, Analog output given priority: DAE = 1) With the input shutdown standby control function, IOL = 4 mA Hysteresis inputs Standby control for input shutdown DA0 • A/D converter ref+ (AVRH) power supply input pin, With the power supply protection circuit • Pin for both CMOS hysteresis and analog inputs CMOS output With the input shutdown function for the input shutdown standby ANE J AVR ANE Pout Nout K • • R Hysteresis inputs Standby control for input shutdown Analog inputs Hysteresis inputs N-ch open-drain output With the input shutdown standby control function, IOL = 4 mA L Nout R Hysteresis inputs Standby control for input shutdown 19 CHAPTER 1 OVERVIEW 1.8 Notes on Handling Device Note in particular the following items when handling devices. • Strict observance of the maximum rated voltage (Prevention of latchup) • Stabilization of power supply voltage • When the power is turned on • Handling of unused pins • Handling for the power supply pin of the A/D converter • When using the external clock • Power supply pin • Sequence of voltage application/cut-off to the power supply pins/analog input pins of the A/D converter • Notes on using "DIV A, Ri" and "DIVW A, RWi" instructions • If subclock mode is not used • If the output from ports 0 and 1 is indefinite • When REALOS is used ■ Notes on Handling Device ❍ Strict observance of the maximum rated voltage (Prevention of latchup) • In CMOS IC, a latchup phenomenon may occur if a voltage higher than VCC or that lower than VSS is applied to input pins or output pins, other than medium- to high-voltage, or a voltage exceeding the rated voltage is applied between VCC and VSS. If a latchup phenomenon occurs, the power supply current may increase rapidly, leading to thermal damage of circuit elements. Therefore, care must be taken, when using devices, so that the absolute maximum rating is not exceeded. • When turning on or turning off the analog power supply, care must be taken to ensure that the analog power supply voltages (AVCC, AVRH, DVCC) and analog input voltage do not exceed the digital power supply voltage (VCC). ❍ Stabilization of power supply voltage If the power supply voltage varies acutely even within the operation assurance range of the VCC power supply voltage, a malfunction may occur. The VCC power supply voltage must therefore be stabilized. As stabilization guidelines, stabilize the power supply voltage so that VCC ripple fluctuations (peak to peak value) in the commercial frequencies (50 to 60 Hz) fall within 10% of the standard VCC power supply voltage and the transient fluctuation rate becomes 0.1V/ms or less in instantaneous fluctuation for power supply switching. ❍ When the power is turned on When turning on the power, secure 50ms (between 0.2V and 2.7V) or more for the rising time of the power supply voltage (VCC) to prevent the malfunctioning of the built-in step-down circuits. 20 1.8 Notes on Handling Device ❍ Handling of unused pins Leaving unused input pins open may lead to malfunction or permanent damage due to latchup. Therefore, take steps such as pull-up or pull-down via resistance of at least 2kΩ. If there is any unused I/O pin, open the pin after setting it to the output status or take the same steps as those for the input pins after setting the pin to the input status. ❍ Handling for the power supply pin of the A/D converter Even when the A/D converter is not used, connect it to ensure AVCC = VCC, AVSS = AVRH =AVRL = VSS. ❍ When using the external clock When using the external clock, an oscillation stabilization time is required when releasing power-on reset, subclock mode, and stop mode. When using the external clock as shown in Figure 1.8-1 "Example of Using the External Clock", activate the X0 pin only and set the X1 pin to open. Figure 1.8-1 Example of Using the External Clock X0 OPEN X1 MB90570 Series ❍ Power supply pin • If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latchup. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally. • Connect VCC and VSS to the device from the current supply source at a low impedance. • As a measure against power supply noise, connect a capacitor of about 0.1µF as a bypass capacitor between VCC and VSS in the vicinity of VCC and VSS pins of the device. ❍ Sequence of voltage application/cut-off to the power supply pins/analog input pins of the A/D converter • Be sure to apply voltage to the power supplies (AVCC, AVRH, and AVRL) of the A/D converter and the analog input pins (AN0 to AN7), after applying voltage to the digital power supply pins (VCC). • To turn off the power, first turn off the A/D converter power and the analog input and then turn off the digital power. In this case, carry out voltage applications and power-off so that AVRH do not exceed AVCC. If input ports are used by the pins which also serve as analog inputs, the input voltage do not exceed AVCC. (Voltage can be applied to the analog power supply and digital power supply simultaneously or both types of power supplies can be turned off simultaneously) 21 CHAPTER 1 OVERVIEW ❍ Notes on using "DIV A, Ri" and "DIVW A, RWi" instructions Use the signed multiplication/division instructions "DIV A,Ri" and "DIVW A,RWi" after setting the value of the corresponding bank register (DTB, ADB, USB, and SSB) to "00H". If the value of the corresponding bank register (DTB, ADB, USB, and SSB) is set to a value other than "00H", the remainder obtained as a result of instruction execution is not stored in the register of the instruction operands. For details, see Section 2.6.2 " Notes on Using DIV A, Ri and DIVW A, Rwi Instructions" ❍ If subclock mode is not used Even if subclock mode is not used, connect an oscillator to the X0A and X1A pins. ❍ If the output from ports 0 and 1 is indefinite After the power is turned on, indefinite is output from ports 0 and 1 in the oscillation stabilization wait time (during power-on reset) of the step-down circuit. Note that the timing of output is given as shown in Figure 1.8-2 "Chart of timing in which output from the ports 0 and 1 is indefinite". Still, if the type does not contain any step-down circuit, indefinite is not output because there is no oscillation stabilization wait time for the step-down circuit. Figure 1.8-2 Chart of timing in which output from the ports 0 and 1 is indefinite Oscillation stabilization wait time Stabilization wait time of step-down circuits *2 *1 Vcc (power supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operating clock A) signal KB (internal operating clock B) signal PORT (port output) signal Output indefinite period *1: Oscillation stabilization wait time for step-down circuits 217/oscillation clock frequency (For oscillation clock frequency of 16MHz, about 8.19 ms) *2: Oscillation stabilization wait time 218/oscillation clock frequency (For oscillation clock frequency of 16MHz, about 16.38 ms) ❍ When REALOS is used When REALOS is used, the extended intelligent I/O service (EI2OS) cannot be used. 22 CHAPTER 2 CPU This chapter describes the CPU functions and operations. 2.1 "Memory Space" 2.2 "Addressing" 2.3 "Allocating Many-Byte Length Data in a Memory Space" 2.4 "Dedicated Registers" 2.5 "General-Purpose Registers" 2.6 "Prefix Codes" 23 CHAPTER 2 CPU 2.1 Memory Space The F2MC-16LX CPU core is a 16-bit CPU designed for applications requiring highspeed real-time processing for products related to the general public (non-industrial) and products installed in vehicles. The F2MC-16LX instruction set is designed for controller applications and allows high-speed and high-efficiency processing of various types of control. The internal 32-bit accumulator enables the F2MC-16LX to perform 32-bit data processing in addition to 16-bit data processing. The maximum amount of memory is 16M bytes (expandable), and it can be accessed by the linear or bank method. The instruction system, based on the A-T architecture of the F2MC-8L, has been enhanced by adding high-level language support instructions, expanding the addressing modes, enhancing the multiplication and division instructions, and providing rich bit processing. ■ Memory Space All data items, programs, and I/O operations managed by F2MC-16LX CPU are allocated in the 16M-byte memory space of the F2MC-16LX CPU. Specifying these addresses with a 24-bit address bus enables the CPU to access each resource. Figure 2.1-1 Example of the Relationship between the F2MC-16LX System and Memory Map Program area Program F2MC-16LX Data Data area Interrupt Peripheral circuit [Device] 24 Generalpurpose port Interrupt controller Peripheral circuit General-purpose port 2.2 Addressing 2.2 Addressing The following two methods are used to specify the addresses of F2MC-16LX: • Linear method: All 24-bit addresses are specified by instructions. • Bank method: The higher 8 bits of an address are specified by the bank register associated with an application, and the lower 16 bits of the address are specified by an instruction. ■ Addressing using the linear method The linear method is applied as follows: ❍ 24-bit operand specification: A 24-bit address is specified directly by an operand. ❍ 32-bit register indirect specification: The lower 24 bits of the 32-bit general-purpose register are used as an address. Figure 2.2-1 Example of 24-Bit Operand Specification of the Linear Method JMPP 123456H Old program counter + program bank 17 17452DH 452D 123456H New program counter + program bank 12 JMPP 123456H Next instruction 3456 Figure 2.2-2 Example of 32-Bit Register Indirect Specification of the Linear Method MOV A, @RL1+7 Old AL XXXX 090700H 3A RL1 240906F9 +7 (Higher 8 bits are ignored.) New AL 003A 25 CHAPTER 2 CPU ■ Addressing using the bank method The bank method divides the 16M-byte space into 256 banks for each 64K bytes and specifies the bank associated with each space using the following five bank registers: ❍ Program bank register (PCB): Reset-time initial value FFH The 64K-byte bank specified by the PCB is called a program (PC) space. The program space contains primarily instruction codes, a vector table, and immediate data. ❍ Data bank register (DTB): Reset-time initial value 00H The 64K-byte bank specified by the DTB is called a data (DT) space. The data space contains primarily readable data, data that can be written, and the control and data registers of external and internal resources. ❍ User stack bank register (USB): Reset initial value 00H ❍ System stack bank register (SSB): Reset initial value 00H The 64K-byte bank specified by the USB or SSB is called stack (SP) space. Stack space is accessed when stack access occurs at register saving of push and pop instructions and interrupts. The space to be used is dependent on an S flag in the condition code register. ❍ Additional bank register (ADB): Reset-time initial value 00H The 64K-byte bank specified by the ADB is called an additional (AD) space. The additional space contains primarily data that overflowed from the DT space. To increase instruction code efficiency, default spaces as listed below are determined for instructions for each addressing mode. To use spaces other than default spaces when using an addressing mode, specify the prefix code associated with each bank prior to specifying the instruction, thereby enabling a bank space to be accessed associated with the prefix code. The DTB, USB, SSB, and ADB are initialized to 00H by the reset. The PCB is initialized to a value specified by the reset vector. After the reset, the DT, SP, or AD space is allocated in bank 00H (000000H-00FFFFH). The PC space is allocated in the bank specified by the reset vector. Table 2.2-1 Default Spaces Default space 26 Addressing Program space PC indirectness, program access, branch system Data space Addressing using @RW0, @RW1, @RW4, and @RW5, @A, addr16, dir Stack space Addressing using PUSHW, POPW, @RW3, and @RW7 Additional space Addressing using @RW2 and @RW6 2.2 Addressing Figure 2.2-3 Example of the Physical Address of Spaces Program space Physical addresses : PCB (program bank register) Additional space : ADB (additional bank register) User stack space : USB (user stack bank register) Data space : DTB (data bank register) System stack space : SSB (system stack bank register) 27 CHAPTER 2 CPU 2.3 Allocating Many-Byte Length Data in a Memory Space Data is written into the memory in ascending order of addresses. If data is 32 bits in length, the lower 16 bits are transferred before the higher 16 bits, and then the higher 16 bits are transferred. If a reset signal is input immediately after the lower data is written, the higher data may not be written. To retain the data, the reset signal must be input after the higher data is written. ■ Allocating Many-Byte Length Data in a Memory Space As shown in Figure 2.3-1 "Example of Allocating Many-Byte Length Data in the Memory", the lower eight bits of many-byte length data in a memory space are provided at address n. The remaining bits are provided sequentially at the addresses n+1, n+2, n+3, ... Figure 2.3-1 Example of Allocating Many-Byte Length Data in the Memory MSB 0101010 LSB 1100110 1111111 00010100 01010101 11001100 11111111 Address n 00010100 ■ Access to Many-Byte Length Data As shown in Figure 2.3-2 "Example of Accessing Many-Byte Length Data (Execution of MOVW A, 080FFFFH", all access operations are basically performed within the bank. For instructions that access many-byte length data, the address following address FFFFH is 0000H of the same bank. 28 2.3 Allocating Many-Byte Length Data in a Memory Space Figure 2.3-2 Example of Accessing Many-Byte Length Data (Execution of MOVW A, 080FFFFH) AL before execution AL after execution 29 CHAPTER 2 CPU 2.4 Dedicated Registers A dedicated register exists in the CPU as dedicated hardware, and its use is restricted to the CPU architecture. ■ Dedicated Registers F2MC-16LX supports the following 11 dedicated registers: ❍ Accumulator (A=AH:AL): Two 16-bit accumulators (Can be used as the accumulator of 32 bits in total.) ❍ User stack pointer (USP): 16-bit pointer indicating the user stack area ❍ System stack pointer (SSP): 16-bit pointer indicating the system stack area ❍ Processor status (PS): 16-bit register indicating the system status ❍ Program counter (PC): 16-bit register having addresses at which the program is stored ❍ Program bank register (PCB): 8-bit register indicating the PC space ❍ Data bank register (DTB): 8-bit register indicating the DT space ❍ User stack bank register (USB): 8-bit register indicating the user stack space ❍ System stack bank register (SSB): 8-bit register indicating the system stack space ❍ Additional bank register (ADB): 8-bit register indicating the AD space ❍ Direct page register (DPR): 8-bit register indicating the direct page 30 2.4 Dedicated Registers Figure 2.4-1 Dedicated Registers Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register 31 CHAPTER 2 CPU 2.4.1 Accumulator (A) The A consists of two 16-bit arithmetic operation registers AH and AL and is used as temporary storage for arithmetic operation results or for data transfer. For 32-bit data processing, the AH and AL in a combination are used. Only the AL is used for word processing of 16-bit data or for byte processing of 8-bit data. ■ Accumulator (A) Data in the A can be used for arithmetic operations with data in the memory and registers (Ri, RWi, and RLi). As with F2MC-8, when F2MC-16LX transfers data equal to or less than a word length to the AL, data in the AL before the transfer is transferred automatically to the AH (data retention function), thereby ensuring that the data retention function and AL-AH arithmetic operations will increase processing efficiency. Figure 2.4-2 Example of 32-bit Data Transfer MOVL A, @RW1+6 (This instruction reads a long word length using the results of RW1 content + 8-bit length offset as an address, and stores the read contents in the A.) Memory space A before execution A after execution 1 Figure 2.4-3 Example of AL-AH Transfer MOVW A, @RW1+6 (This instruction reads a word length using the results of RW1 content + 8-bit length offset as an address, and stores the read contents in the A.) Memory space A before execution A after execution 1 As shown in Figures 2.4-4 and 2.4-5, when data with a length not exceeding one byte is transferred to the AL, it is zero-extended or sign-extended to 16 bits and is stored in the AL. Data in the AL is also handled in lengths of words or bytes. If an arithmetic operation instruction for byte processing is executed in the AL, the higher eight 32 2.4 Dedicated Registers bits of the AL before arithmetic operations are ignored. All higher eight bits of the arithmetic operation result are set to 0. The A is not initialized by the reset, immediately after which the values become undefined. Figure 2.4-4 Example of Executing Zero Extension MOV A, 3000H (This instruction extends the content at address 3000 by adding zeros, and stores the result in the AL.) Memory space A before execution A after execution Figure 2.4-5 Example of Executing the Sign Extension MOVX A, 3000H (This instruction extends the content at address 3000H with the sign and stores the result in the AL.) Memory space A before execution A after execution 33 CHAPTER 2 CPU 2.4.2 User Stack Pointer (USP) and System Stack Pointer (SSP) The User Stack Pointer (USP) and the System Stack Pointer (SSP) are 16-bit registers that contain addresses for data saving and return at execution of a push/pop instruction or a subroutine. ■ User Stack Pointer (USP) and System Stack Pointer (SSP) The user stack pointer (USP) and the system stack pointer (SSP) are used by stack instructions. However, if the S flag in the processor status register is 0, the USP register is validated. If the S flag is 1, the SSP register is validated. (See Figure 2.4-6 "Stack Operation Instructions and Stack Pointers (Example of PUSHW A when the S Flag is 0)" and Figure 2.4-7 "Stack Operation Instruction and Stack Pointers (Example of PUSHW A when the S Flag is 1)" If an interrupt is accepted, the S flag is set, thereby ensuring that register saving at the interrupt will be performed in the memory area indicated by the SSP. The SSP is used for stack processing by the interrupt routine. The USP is used for stack processing by a routine other than the interrupt routine. Use only the SSP if the stack space does not have to be split. The higher eight bits of an address at stack processing are indicated by SSP--> SSB and USP --> USB. USP and SSP are not initialized at a reset, and their values become undefined instead. Figure 2.4-6 Stack Operation Instructions and Stack Pointers (Example of PUSHW A when the S Flag is 0) Before execution S flag The user stack is used because the S flag is 0. After execution S flag 34 2.4 Dedicated Registers Figure 2.4-7 Stack Operation Instructions and Stack Pointers (Example of PUSHW A when the S Flag is 1) Before execution S flag After execution S flag The system stack is used because the S flag is 1. Note: In principle, use an even address as the value to be set in the stack pointer. 35 CHAPTER 2 CPU 2.4.3 Processor Status (PS) The PS consists of bits for controlling CPU operations and bits indicating CPU status. ■ Processor Status (PS) The higher bytes of the PS consist of the register bank pointer (RP), which indicates the first address of the register bank, and the interrupt level mask register (ILM). The lower bytes of the PS consist of the condition code register (CCR) formed by flags to be set or reset by instruction execution results or interrupt occurrence. Figure 2.4-8 Structure of the PS Initial value Undefined value ■ Condition Code Register (CCR) Figure 2.4-9 Configuration of the Condition Code Register Initial value Undefined value I: Interrupt enable flag: An interrupt is enabled when the I is 1 for all interrupt requests other than a software interrupt. If the I is 0, the interrupt is masked. The I is cleared at reset. S: Stack flag: When S is 0, the USP is valid as the stack operation pointer. If the S is 1, the SSP is valid. The S is set when an interrupt is accepted or the reset is made. T: Sticky bit flag: This flag is 1 if the data shifted out from the carry contains at least one 1 after the logical right or arithmetic right shift instruction is executed. In other cases, the flag is 0. The flag is also 0 when the shift amount is 0. N: Negative flag: This flag is set when the MSB of the arithmetic operation result is 1 and is cleared if the MSB is 0. Z: Zero flag: This flag is set when all arithmetic operation results are 0 and is cleared in other cases. V: Overflow flag: This flag is set when an overflow occurs to indicate a signed numeric value as a result of an arithmetic operation and is cleared if no overflow occurs. 36 2.4 Dedicated Registers C: Carry flag: This flag is set when a carry-up or carry-down is generated from the MSB as a result of arithmetic operation and is cleared if no carry-up or carry-down occurs. ■ Register Bank Pointer (RP) The RP register indicates the relationship between the general-purpose register of F2MC-16LX and the address of the internal RAM in which the general-purpose register exists. The RP indicates the first memory address of the used register bank as the conversion expression [000180H + (RP)*10H]. The RP consists of 5 bits and can accept a value from 00H to 1FH and can provide a register bank in the memory of 000180H to 00037FH. However, if the memory is not an internal RAM even if this range is satisfied, the register cannot be used as a general-purpose register. The contents of the RP are all initialized to 0 by the reset. An 8-bit immediate value can be transferred to the RP, though only the lower five bits of the data are actually used. Figure 2.4-10 Configuration of the Register Bank Pointer (RP) Initial value ■ Interrupt Level Mask Register (ILM) The ILM consists of three bits to indicate the level of the CPU interrupt mask. Only interrupt requests whose levels are higher than the level indicated by these three bits are accepted. Level 0 is defined as the highest and level 7 is defined as the lowest. Therefore, to enable an interrupt to be accepted, a value smaller than the value retained by the current ILM must be requested. When the interrupt is accepted, its level value is set in the ILM and any subsequent interrupt whose priority is equal or lower is not accepted. The contents of the ILM are all initialized to 0 by the reset. An 8-bit immediate value can be transferred to the ILM, though only the lower three bits of the data are actually used. Figure 2.4-11 Configuration of the Interrupt Level Mask Register (ILM) Initial value Table 2.4-1 High-Low of the Levels Indicated by the Interrupt Level Mask Register (ILM) ILM2 ILM1 ILM0 Level value Interrupt level to be allowed 0 0 0 0 Interrupt prohibited 0 0 1 1 0 only 0 1 0 2 Level whose value is less than 1 0 1 1 3 Level whose value is less than 2 1 0 0 4 Level whose value is less than 3 1 0 1 5 Level whose value is less than 4 1 1 0 6 Level whose value is less than 5 1 1 1 7 Level whose value is less than 6 37 CHAPTER 2 CPU 2.4.4 Program Counter (PC) The PC is a 16-bit counter that indicates the lower 16 bits of the memory address of the instruction code to be executed by the CPU. The higher eight addresses are indicated by the PCB. ■ Program Counter (PC) The PC is updated by a conditional branch instruction, subroutine call instruction, interrupt, or reset and can be used as the base pointer at operand access. Figure 2.4-12 Configuration of the Program Counter Instruction to be executed next 38 2.4 Dedicated Registers 2.4.5 Direct Page Register (DPR) The DPR specifies operands addr8 to addr15 when a direct addressing instruction is executed. The length of the DPR is eight bits and is initialized to 01H by the reset. The DPR can be read or written by an instruction. ■ Direct Page Register (DPR) Figure 2.4-13 "Generating a Physical Address by Direct Addressing" shows a physical address to be created by direct addressing. Figure 2.4-13 Generating a Physical Address by Direct Addressing DTB register DPR register Direct address in an instruction 24-bit physical address 39 CHAPTER 2 CPU 2.4.6 Bank Register The five types of bank register are as follows: • Program Counter Bank Register (PCB) <initial value: value in the reset vector> • Data Bank Register (DTB) <initial value: 00H> • User Stack Bank Register (USB) <initial value: 00H> • System Stack Bank Register (SSB) <initial value: 00H> • Additional Data Bank Register (ADB) <initial value: 00H> ■ Bank Register The bank registers indicate the memory banks in which the PC space, DT space, SP space (user), SP space (system), and AD space are allocated. All bank registers have a byte length. The PCB is initialized to 00H with the reset vector at reset. A bank register other than the PCB is readable and can be written. The PCB is readable but cannot be written. The PCB is rewritten when an interrupt occurs or at execution of JMPP, CALLP, RETP, RETIQ, or RETF instructions branching to all 16M-byte spaces. For register operations, see Section 2.1 "Memory Space". 40 2.5 General-Purpose Registers 2.5 General-Purpose Registers Like a normal memory, a user can specify the use of a general-purpose register. A general-purpose register is the same as a dedicated register in that it coexists with the RAM in the address space of the CPU and can be accessed without specifying an address. ■ General-Purpose Registers The general-purpose registers of F2MC-16LX exist at 000180H to 00037FH (maximum) of the main storage. They specify which part of an address previously mentioned is the register bank being used through the register bank pointer (RP). Each bank contains the three types of registers listed below. These registers are not independent of one another and are related follows: • R0 to R7: 8-bit general-purpose register • RW0 to RW7: 16-bit general-purpose register • RL0 to RL3: 32-bit general-purpose register Figure 2.5-1 General-Purpose Registers Low First address of the general-purpose register High The relationship between higher and lower bytes of the byte and word registers is obtained from the following expression: PW(i+4) = R (i x 2+1) x 256 + R(i x 2) [i = 0 to 3] The relationship between the higher and lower bytes of the RLi and the RW can be obtained from the following expression: RL( i ) = RW (i x 2+1) x 65536 + RW(i x 2) [i = 0 to 3] 41 CHAPTER 2 CPU ■ Register Banks As shown in Table 2.5-1 "Register Bank Functions", a register bank consists of eight words and can be used for arithmetic operations as a general-purpose register of byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. A bank can also be used to store an instruction pointer. RL0 to RL3 can also be used as a linear pointer that accesses all spaces directly. As with the ordinary RAM, the contents of the register bank are not initialized by the reset and the status prior to the reset is retained. The values are undefined at power-on. Table 2.5-1 Register Bank Functions Register Function R0 ~ R7 Used as operands of the instructions. RW0 ~ RW7 Used as operands of the pointer and instructions. RL0 ~ RL3 Used as operands of the long pointer and instructions. Note: R0 is also used as the barrel shift counter and normalize instruction counter. RW0 is also used as the string instruction counter. 42 2.6 Prefix Codes 2.6 Prefix Codes Three types of prefix codes are as follows: bank select prefixes, common register bank prefixes, and flag change suppression prefixes. A part of an instruction operation can be changed by prefixing a prefix code to the instruction. ■ Bank Select Prefixes The memory space to be used at data access is determined for each addressing mode. The memory space for data access by an instruction can be selected arbitrarily by prefixing the bank select prefix to the instruction regardless of an addressing mode. Table 2.6-1 "Bank Select Prefixes" lists the bank select prefixes and the memory areas to be selected. Table 2.6-1 Bank Select Prefixes Bank select prefix Space to be selected PCB PC space DTB Data space ADB Additional area SPB Either the SSP or USP space is used depending on the content of the stack flag. When using the bank select prefixes, note the following instructions: ❍ String instructions [MOVS, MOVSW, SCEQ, SCWEQ, FILS, and FILSW] The bank register specified by an operand is used regardless of whether there is a prefix. ❍ Stack operation instructions [PUSHW, POPW] The SSB or USB is used according to the S flag regardless of whether there is a prefix. ❍ I/O access instructions MOV A, io / MOV io, A / MOVX A, io / MOVW A, io / MOVW io, A / MOV io, #imm8 MOVW io, #imm16 / MOVB A, io:bp / MOVB io:bp, A / SETB io:bp / CLRB io:bp BBC io:bp, rel / BBS io:bp, rel / WBTC, WBTS The I/O space of a bank is used regardless of whether there is a prefix. ❍ Flag change instructions [AND CCR, #imm8, OR CCR, #imm8] The instruction operations are normal, though the effect of a prefix continues until the next instruction. 43 CHAPTER 2 CPU ❍ POPW ps The SSB or USB is used according to the S flag regardless of whether there is a prefix. The effect of the prefix continues until the next instruction. ❍ MOV ILM, #imm8 The operation instructions are normal, though the effect of a prefix continues until the next instruction. ❍ RETI The SSB is used regardless of whether there is a prefix. ■ Common Register Bank Prefix (CMR) To simplify data exchange among two or more tasks, it is necessary to use a means of accessing the same register bank that was easily determined by comparison regardless of the RP value set. All register accesses of instructions accessing a register bank can be changed to the common bank in 000180H to 00018FH (register bank selected for RP = 0) by prefixing the CMR to the instruction regardless of the current RP value. Note the following instructions: ❍ String instructions [MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW] If an interrupt request occurs during execution of a string instruction to which a prefix code was added, a malfunction occurs for a string instruction executed after the return of the interrupt because the prefix is invalid. Do not add the CMR prefix to the above string instructions. ❍ Flag change instruction [AND CCR, #imm8, OR CCR, #imm8, POPW PS] The instruction operations are normal, though the effect of the prefix continues until the next instruction. ❍ MOV ILM, #imm8 The instruction operations are normal, though the effect of the prefix continues until the next instruction. ■ Flag Change Suppression Prefix (NCC) To suppress a flag change, use the flag change suppression prefix code (NCC). A flag change accompanied by instruction execution can be suppressed by prefixing an unnecessary flag change to the instruction. Note the following instructions: ❍ String instructions [MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW] If an interrupt request occurs during execution of a string instruction to which a prefix code was added, a malfunction occurs for a string instruction executed after the return of the interrupt because the prefix is invalid. Do not add the NCC prefix to the above string instructions. ❍ Flag change instruction [AND CCR, #imm8, OR CCR, #imm8, POPW PS] The instruction operations are normal, though the effect of the prefix continues until the next instruction. 44 2.6 Prefix Codes ❍ Interrupt instructions [INT #vct8, INT9, INT addr16, INTP addr24, RETI] The CCR changes according to instruction specifications regardless of whether there is a prefix. ❍ JCTX @A The CCR changes according to instruction specifications regardless of whether there is a prefix. ❍ MOV ILM, imm8 The instruction operations are normal, though the effect of the prefix continues until the next instruction. 45 CHAPTER 2 CPU 2.6.1 Restrictions on the Use of Prefix Instructions The following restrictions apply on the use of prefix instructions: • No interrupt/hold request is accepted during execution of prefix codes and interrupt/ hold suppression instructions. • If a prefix code is prefixed to an interrupt/hold instruction, the effect of the prefix code is delayed. • When competing prefix codes are consecutive, the last prefix code is valid. ■ Prefix Codes and Interrupt/Hold Suppression Instructions The following restriction apply to the interrupt/hold suppression instructions listed in Table 2.6-2 "Prefix Codes and Interrupt/Hold Suppression Instruction": Table 2.6-2 Prefix Codes and Interrupt/Hold Suppression Instructions Prefix code Instructions that do not accept an interrupt or hold request PCB DTB ADB SPB CMR NCC Interrupt/hold suppression instructions (instructions that delay the effect of the prefix code) MOV OR AND POPW LM, #imm8 CCR, #imm8 CCR, #imm8 PS ❍ Interrupt/hold suppression As shown in Figure 2.6-1 "Interrupt/Hold Suppression", any generated interrupts or hold requests are not accepted during execution of prefix codes and interrupt/hold suppression instructions. In such cases, an interrupt or hold request is accepted when an instruction other than a prefix code or interrupt/hold suppression instruction has been executed. Figure 2.6-1 Interrupt/Hold Suppression Interrupt suppression instruction (a) Ordinary instruction (a) Interrupt request generation Acceptance of interrupt ❍ Delaying the effect of the prefix code As shown in Figure 2.6-2 "Interrupt/Hold Suppression Instruction and Prefix Codes", if a prefix code is prefixed to an interrupt or hold suppression instruction, the effect of the prefix code is validated for the first subsequent instruction following the interrupt/hold suppression instruction. 46 2.6 Prefix Codes Figure 2.6-2 Interrupt/Hold Suppression Instructions and Prefix Codes Interrupt suppression instruction The CCR does not change because of the NCC. ■ When Prefix Codes are Consecutive As shown in Figure 2.6-3 "Consecutive Prefix Codes", when the prefix codes (PCB, ADB, DTB, and SPB) in contention are consecutive, the last prefix code is valid. Figure 2.6-3 Consecutive Prefix Codes Prefix code Prefix code PCB is validated. 47 CHAPTER 2 CPU 2.6.2 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions The remainders of instruction execution are stored at the address (lower 16-bit) equivalent to the register of the instruction operand in the memory bank area (higher 8-bit) in accordance with the contents listed in Table 2.6-3 "Note on Using "DIV A, Ri" and "DIVW A, RWi" Instruction". Set the value of the corresponding bank register to "00H" when using "DIV A, Ri" and "DIVW A, RWi" instructions. ■ Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions Table 2.6-3 Notes on Using "DIV A, Ri" and "DIVW A, RWi" Instructions Instruction DIV A, R0 Address at which the remainder is stored Name of the bank register affected when executing the instructions shown in the table DTB (DTB: Higher 8-bit) + (0180H + RP x 10H + 8H : Lower 16-bit) DIV A, R1 (DTB: Higher 8-bit) + (0180H + RP x 10H + 9H : Lower 16-bit) DIV A, R4 (DTB: Higher 8-bit) + (0180H + RP x 10H + CH : Lower 16-bit) DIV A, R5 (DTB: Higher 8-bit) + (0180H + RP x 10H + DH : Lower 16-bit) DIVW A, RW0 (DTB: Higher 8-bit) + (0180H + RP x 10H + 0H : Lower 16-bit) DIVW A, RW1 (DTB: Higher 8-bit) + (0180H + RP x 10H + 2H : Lower 16-bit) DIVW A, RW4 (DTB: Higher 8-bit) + (0180H + RP x 10H + 8H : Lower 16-bit) DIVW A, RW5 (DTB: Higher 8-bit) + (0180H + RP x 10H + AH : Lower 16-bit) DIV A, R2 ADB (ADB: Higher 8-bit) + (0180H + RP x 10H + AH : Lower 16-bit) DIV A, R6 (ADB: Higher 8-bit) + (0180H + RP x 10H + EH : Lower 16-bit) DIVW A, RW2 (ADB: Higher 8-bit) + (0180H + RP x 10H + 4H : Lower 16-bit) DIVW A, RW6 (ADB: Higher 8-bit) + (0180H + RP x 10H +EH : Lower 16-bit) DIV A, R3 DIV A, R7 USB SSB*1 (USB*2: Higher 8-bit) + (0180H + RP x 10H + BH : Lower 16-bit) (USB*2: Higher 8-bit) + (0180H + RP x 10H + FH : Lower 16-bit) DIVW A, RW3 (USB*2: Higher 8-bit) + (0180H + RP x 10H + 6H : Lower 16-bit) DIVW A, RW7 (USB*2: Higher 8-bit) + (0180H + RP x 10H + EH : Lower 16-bit) *1 Depending on the S bit of the CCR register *2 When the S bit of the CCR register is 0 48 2.6 Prefix Codes If the value of corresponding bank registers (DTB, ADB, USB, SSB) is set to "00H", the remainder of division results are stored in the register of the instruction operand. If the value is set to a value other than "00H", the higher 8-bit address is specified by the bank register corresponding to the register of the instruction operand. The lower 16-bit address then becomes the same address as that of the register of the instruction operand at which the remainder is stored. [Example] If "DIV A, R0" instruction is executed in the case of DTB=053H/RP=003H, the address of R0 is as follows: 0180H+RP (003H) x 10H+08H (address equivalent to R0) = 0001B8H The bank register to be specified by "DIV A, R0" is DTB, so the address to which bankspecified 053H is added, that is 05301B8H, is the address at which the remainder of a result is stored. (For an explanation of Ri and RWi registers, see Section 2.5 "General-purpose Register". ■ Evasion of notes In order to evade notes of the "DIV A, Ri" and "DIVW A, RWi" instructions during program development, the compiler modifies the program so that the respective instructions are not generated. The assembler then replaces these instructions by functions equivalent to the instruction strings. Use the following compiler and assembler. • Compiler: Version V02L06 of cc907 or later, and version V30L02 of fcc907s or later • Assembler: Version V03L04 of asm907a or later, and version V30L04 (Rev.30004) of fasm907s or later 49 CHAPTER 2 CPU 50 CHAPTER 3 INTERRUPT This chapter describes the interrupt functions and operations. 3.1 "Overview of the Interrupt" 3.2 "Interrupt Source" 3.3 "Interrupt Vector" 3.4 "Hardware Interrupt" 3.5 "Software Interrupts" 3.6 "Extended Intelligent I/O Service (EI2OS)" 3.7 "Exception" 51 CHAPTER 3 INTERRUPT 3.1 Overview of the Interrupt The F2MC-16LX has an interrupt function that interrupts processing if a suitable event occurs and passes control to a program defined separately. ■ Overview of the Interrupt The interrupt functions support the following four types of interrupts: • Hardware interrupt: Interrupt processing activated by the occurrence of an internal resource event • Software interrupt: Interrupt processing activated by the occurrence of an event occurrence instruction • Extended intelligent I/O service (EI2OS): Transfer processing activated by the occurrence of an internal resource event • Exception: Interrupt processing activated by the occurrence of an operation execution This chapter describes these four types of interrupt functions. 52 3.2 Interrupt Source 3.2 Interrupt Source Table 3.2-1 "Interrupt Source, Interrupt Vector, Interrupt Control Register" shows the interrupt source, the interrupt vector, and the interrupt control register. ■ Interrupt Source Table 3.2-1 Interrupt Source, Interrupt Vector, Interrupt Control Register Interrupt source EI2OS clear Interrupt vector Interrupt control register Number Address Number Address Reset × # 08 FFFFDCH — — INT9 instruction × # 09 FFFFD8H — — Exception × # 10 FFFFD4H — — A/D converter Y2 # 11 FFFFD0H ICR00 0000B0H Input capture 0 fetch Y2 # 12 FFFFCCH DTP0 (external division 0) Y2 # 13 FFFFC8H ICR01 0000B1H Input capture 1 fetch Y2 # 14 FFFFC4H Output compare 0 matching Y2 # 15 FFFFC0H ICR02 0000B2H Output compare 1 matching Y2 # 16 FFFFBCH Output compare 2 matching Y2 # 17 FFFFB8H ICR03 0000B3H Output compare 3 matching Y2 # 18 FFFFB4H I/O serial 0 Y2 # 19 FFFFB0H ICR04 0000B4H × # 20 FFFFACH I/O serial 1 Y2 # 21 FFFFA8H ICR05 0000B5H Watch timer × # 22 FFFFA4H I/O serial 2 Y2 # 23 FFFFA0H ICR06 0000B6H DTP1 (external division 1) Y2 # 24 FFFF9CH DTP2/3 (external division 2/3) Y2 # 25 FFFF98H ICR07 0000B7H 8/16-bit PPG0 counter borrow × # 26 FFFF94H DTP4/5 (external division 4/5) Y2 # 27 FFFF90H ICR08 0000B8H 8/16-bit PPG1 counter borrow × # 28 FFFF8CH Free run timer 53 CHAPTER 3 INTERRUPT Table 3.2-1 Interrupt Source, Interrupt Vector, Interrupt Control Register (Continued) Interrupt source EI2OS clear Interrupt vector Number Address # 29 FFFF88H Up/down counter 0 borrow/overflow/ reverse Y2 Up/down counter 0 compare matching Y2 # 30 FFFF84H Up/down counter 1 borrow/overflow/ reverse Y2 # 31 FFFF80H Up/down counter 1 compare matching Y2 # 32 FFFF7CH DTP6 (external division 6) Y2 # 33 FFFF78H × # 34 FFFF74H Y2 # 35 FFFF70H × # 36 FFFF6CH UART1 reception completion Y1 # 37 FFFF68H UART1 sending completion Y2 # 38 FFFF64H UART0 reception completion Y1 # 39 FFFF60H UART0 sending completion Y2 # 40 FFFF5CH Flash memory × # 41 FFFF58H Delay interrupt × # 42 FFFF54H Time base timer DTP7 (external division 7) I2C interface Interrupt control register Number Address ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH Y1: The interrupt request flag is cleared by the EI2OS interrupt clear signal. There is a stop request. Y2: The interrupt request flag is cleared by the EI2OS interrupt clear signal. ×: The interrupt request flag is not cleared by the EI2OS interrupt clear signal. 54 3.3 Interrupt Vector 3.3 Interrupt Vector Table 3.3-1 "List of Interrupt Vectors" lists the interrupt vectors. ■ Interrupt Vectors Table 3.3-1 List of Interrupt Vectors Software interrupt instruction Vector address L Vector address M Vector address H Mode register Interrupt No. Hardware interrupt INT 0 FFFFFCH FFFFFDH FFFFFEH Not used #0 . . . . . . . . . . . . . . . . . . INT 7 FFFFE0H FFFFE1H FFFFE2H Not used #7 None INT 8 FFFFDCH FFFFDDH FFFFDEH FFFFDF #8 (RESET vector) INT 9 FFFFD8H FFFFD9H FFFFDAH Not used #9 None INT 10 FFFFD4H FFFFD5H FFFFD6H Not used #10 <Exception> INT 11 FFFFD0H FFFFD1H FFFFD2H Not used #11 A/D converter INT 12 FFFFCCH FFFFCDH FFFFCEH Not used #12 ICAP0 INT 13 FFFFC8H FFFFC9H FFFFCAH Not used #13 DTP0 INT 14 FFFFC4H FFFFC5H FFFFC6H Not used #14 ICAD1 INT 15 FFFFC0H FFFFC1H FFFFC2H Not used #15 Output compare #0 INT 16 FFFFBCH FFFFBDH FFFFBEH Not used #16 Output compare #1 INT 17 FFFFB8H FFFFB9H FFFFBAH Not used #17 Output compare #2 INT 18 FFFFB4H FFFFB5H FFFFB6H Not used #18 Output compare #3 INT 19 FFFFB0H FFFFB1H FFFFB2H Not used #19 Extended I/0 serial 0 INT 20 FFFFACH FFFFADH FFFFAEH Not used #20 Free run timer INT 21 FFFFA8H FFFFA9H FFFFAAH Not used #21 Extended I/O serial 1 INT 22 FFFFA4H FFFFA5H FFFFA6H Not used #22 Watch timer INT 23 FFFFA0H FFFFA1H FFFFA2H Not used #23 Extended I/O serial 2 INT 24 FFFF9CH FFFF9DH FFFF9EH Not used #24 DTP1 INT 25 FFFF98H FFFF99H FFFF9AH Not used #25 DTP2/3 None . . . 55 CHAPTER 3 INTERRUPT Table 3.3-1 List of Interrupt Vectors (Continued) Software interrupt instruction Vector address L Vector address M Vector address H Mode register Interrupt No. INT 26 FFFF94H FFFF95H FFFF96H Not used #26 PPG0 INT 27 FFFF90H FFFF91H FFFF92H Not used #27 DTP4/5 INT 28 FFFF8CH FFFF8DH FFFF8EH Not used #28 PPG1 INT 29 FFFF88H FFFF89H FFFF8AH Not used #29 Up/down 0 borrow INT 30 FFFF84H FFFF85H FFFF86H Not used #30 Up/down 0 compare INT 31 FFFF80H FFFF81H FFFF82H Not used #31 Up/down 1 borrow INT 32 FFFF7CH FFFF7DH FFFF7EH Not used #32 Up/down 1 compare INT 33 FFFF78H FFFF79H FFFF7AH Not used #33 DTP6 INT 34 FFFF74H FFFF75H FFFF76H Not used #34 Time base INT 35 FFFF70H FFFF71H FFFF72H Not used #35 DTP7 INT 36 FFFF6CH FFFF6DH FFFF6EH Not used #36 I2C interface INT 37 FFFF68H FFFF69H FFFF6AH Not used #37 UART1 reception completion INT 38 FFFF64H FFFF65H FFFF66H Not used #38 UART1 sending completion INT 39 FFFF60H FFFF61H FFFF62H Not used #39 UART0 reception completion INT 40 FFFF5CH FFFF5DH FFFF5EH Not used #40 UART0 sending completion INT 41 FFFF58H FFFF59H FFFF5AH Not used #41 Flash memory INT 42 FFFF54H FFFF55H FFFF56H Not used #42 Delay interrupt INT 43 FFFF50H FFFF51H FFFF52H Not used #43 None . . . . . . . . . . . . . . . . . . INT 254 FFFC04H FFFC05H FFFC06H Not used #254 None INT 255 FFFC00H FFFC01H FFFC02H Not used #255 None 56 Hardware interrupt . . . 3.4 Hardware Interrupt 3.4 Hardware Interrupt A hardware interrupt has a function that interrupts a program being executed by the CPU according to an interrupt request signal from an internal resource and passes control to user-defined interrupt processing program. ■ Overview of Hardware Interrupts The interrupt level of an interrupt request is compared with the interrupt level mask register (ILM) of the CPU PS and the I flag in the CCR is referenced by hardware to determine if interrupt occurrence conditions are satisfied. If the conditions are satisfied, a hardware interrupt occurs. When a hardware interrupt occurs, the CPU responds as follows: • Saves the descriptions of the PC, PS, A, PCB, DTB, ADB, and DPR registers in the CPU in the system stack. • Sets the ILM in the PS register (the ILM automatically attains the same interrupt level as that of the interrupt request being processed). • Fetches the contents of the corresponding interrupt vector and branches control thereto. ■ Hardware Interrupt Mechanism The following four mechanisms are related to hardware interrupts: ❍ Internal resource Interrupt enable bit, interrupt request bit: control of an interrupt from a resource ❍ Interrupt controller ICR: Level assignment to an interrupt, priority decision of interrupts requested concurrently ❍ CPU I, ILM: Comparison of an interrupt level with the current level, interrupt enable state identification Micro code: Interrupt processing step ❍ Addresses FFFC00H to FFFFFFH in memory Interrupt vector table: The interrupt vector table to be referenced during interrupt processing is allocated to addresses and shared with software interrupts. The internal resource reflects on the resource control register, the interrupt controller, the ICR, the CPU, and the CCR description. To use hardware interrupts, these three mechanisms must be set by software in advance. For the ICR, see Interrupt Control Register (ICR) in Section 3.6.1 "Interrupt Control Register (ICR)" 57 CHAPTER 3 INTERRUPT ■ Interrupt Request during Writing in an Internal Resource Area No hardware interrupt requests are accepted during writing in an internal resource area, thereby preventing the CPU from operating incorrectly for an interrupt request made while resourceinterrupt-control-register-related writing is executed. The internal resource area is not an I/O addressing area (000000H to 0000FFH) but are areas allocated to the control register and data register of the internal resource. Figure 3.4-1 Hardware Interrupt Request during Writing in Internal Resource Area Write instruction in internal resource area . . MOV A,#08 MOV io,A MOV A,2000H Control does not An interrupt request occurs. branch to the interrupt. Interrupt processing Control branches to the interrupt. ■ Interrupt Suppress Instruction The F2MC-16LX provides an interrupt suppress instruction not to detect absence/presence of hardware interrupts. See Section 2.6.1 "Interrupt Suppression Instructions". ■ Multiple Interrupts The F2MC-16LX CPU supports multiple interrupts. If an interrupt having an interrupt level higher than that of the executed instruction occurs, control passes to the former instruction following termination of the latter instruction. Following termination of the higher level instruction, control returns to the previous interrupt processing. If an interrupt having an interrupt level equal to or lower than that of the executed interrupt processing occurs, the new interrupt request is held until the executed interrupt processing terminates if the processing is not changed by the ILM description or I flag instruction. Multiple extended intelligent I/O services are not activated concurrently. While one extended intelligent I/O service is being processed, other interrupt requests and extended intelligent I/O service requests are held. 58 3.4 Hardware Interrupt ■ Registers Saved on Stack When an Interrupt Occurs Figure 3.4-2 Registers Saved in Stack Word (16 bit) (SSP value before interrupt occurrence) (SSP value after interrupt occurrence) ■ Notes on Hardware Interrupts Some internal resources clear interrupt requests by a read operation of control registers and data registers. If an interrupt request is cleared by the read operation before control passes to interrupt processing hardware, a malfunction occurs. Therefore, if an internal resource that clears interrupt requests by a register read operation is to be used, prevent the internal resource from reading registers at an interrupt occurrence. 59 CHAPTER 3 INTERRUPT 3.4.1 Operation This section describes the operations from the occurrence of hardware interrupt request to the completion of the interruption processing. ■ Hardware Interrupt Operation The internal resource with the hardware interrupt request function has an interrupt request flag indicating whether an interrupt is requested and an interrupt enable flag indicating whether the interrupt is requested to the CPU. The interrupt request flag is set when an event peculiar to the internal resource occurs. The resource issues an interrupt to the interrupt controller if the interrupt enable flag indicates enable. In the ICRs, the interrupt controller compares the interrupt levels (IL) of the interrupt requests received concurrently. The controller selects the request with the highest level (the smallest IL value) and posts the request to the CPU. If two or more requests have the same level, the request with the smallest interrupt number is selected. The relationship between interrupts and between ICRs is dependent on hardware. The CPU compares the received interrupt level (IL) with the interrupt mask register (ILM) in the processor status register (PS). If the I-bit in the condition code register (CCR) is set to 1, the CPU activates the interrupt processing macrocode following termination of the executed instruction. The ISE bit in the interrupt controller register (ICR) is referenced at the beginning of the interrupt processing macrocode to ensure that the bit is set to 0. The CPU then activates interrupt processing. The interrupt processing first saves 12 bytes of PS, PC, PCB, DTB, ADB, DPR, and A on the system stack (memory indicated by SSB and SSP). Then, it loads the vector in the interrupt vector program counter (PC and PCB), updates the ILM in the PS to the level of the accepted interrupt request and sets the S flag to 1. to in Figure 3.4-3 "Hardware Interrupt Operation to Release" are explained below. 60 3.4 Hardware Interrupt Figure 3.4-3 Hardware Interrupt Operation Peripheral circuit Enable FF Source FF Check Comparator Interrupt level IL Microcode Level comparator F2MC-16 bus Register file Processor status Interrupt enable flag in the CCR Interrupt level mask register in the PS Instruction register Interrupt controller Peripheral circuit An interrupt source occurs in the peripheral circuit. The interrupt enable bit in the peripheral circuit is checked to determine if an interrupt is to be enabled. If so, the peripheral circuit requests an interrupt to the interrupt controller. Upon receiving the interrupt request, the interrupt controller checks the priorities of interrupts requested concurrently and sends the interrupt level of the request with the highest priority to the CPU. The CPU compares the interrupt level requested from the interrupt controller with the ILM bit in the processor status register. The CPU checks the contents of the I flag in the processor status register only if the priority of the requested interrupt is higher than the current interrupt level. The CPU sets the ILM bit to the requested interrupt level (IL) only if the I flag checked in check indicates the interrupt enabled status. The CPU then processes the interrupt following termination of the executed instruction and passes control to the interrupt processing routine. The interrupt request terminates following clearance of the interrupt source that occurred in by software in the user interrupt processing routine. The execution time of the interrupt processing performed by the CPU in and is shown below. The time elapsed before control is passed to the interrupt sequence is dependent on the address indicated by the stack pointer. ■ Processing Time for Hardware Interrupt When an interrupt request was generated, a wait time for sampling interrupts and time for interrupt handling are required before the interrupt is accepted and the interrupt handling routine activated. ❍ Wait time for sampling interrupt requests This is the time from the generation of the interrupt request to the termination of the instruction during execution. The interrupt request sampled in the final cycle of each instruction is used to determine whether an interrupt request was generated. Consequently, the CPU does not detect an interrupt request during the execution of an instruction, and a wait time occurs. The wait time for sampling interrupt requests is longest when an interrupt request is generated immediately after starting POPW, and after PW0 to PW7 instructions, which have the longest execution cycle (45 machine cycles). 61 CHAPTER 3 INTERRUPT ❍ Interrupt handling time (time required for preparation for interrupt processing) • Interrupt activation: 24 + 6 x Z machine cycles • Return from interrupt: 11 + 6 x Z machine cycles (RETI instruction) Table 3.4-1 Correction Values of Number of Cycles of Interrupt Processing Time Address indicated by stack pointer 62 Correction value of the number of cycles (Z) 8-bit data bus in external area +4 Even-numbered address in external area +1 Odd-numbered address in external area +4 Even-numbered address in internal area 0 Odd-numbered address in internal area +2 3.4 Hardware Interrupt 3.4.2 Hardware Interrupt Operation Flowchart Figure 3.4-4 "Hardware Interrupt Operation Flowchart" shows the operational flowchart for hardware interrupts. ■ Hardware Interrupt Operation Flowchart Figure 3.4-4 Hardware Interrupt Operation Flowchart Flag in the CCR Interrupt level mask register in the PS Interrupt request of the internal resource Interrupt enable flag of the internal resource EI2OS enable flag Interrupt request level of the internal resource Flag in the CCR Fetch and decode next instruction. Save PS, PC, PCB, DTB, ADB, DPR, and A in SSP stack, then set ILM to IL. Extended intelligent I/O service processing INT instruction? Execute ordinary instruction. Repetition of string instructions completed? Save PS, PC, PCB, DTB, ADB, DPR, and A in SSP stack, then set I to 0 and ILM to IL. S 1 Fetch interrupt vector. Update PC. 63 CHAPTER 3 INTERRUPT 3.4.3 Sample Use Procedure of Hardware Interrupt To use the hardware interrupt, a system stack area, peripheral features, and an interrupt control register (ICR) must be set. ■ Flow Chart of Sample Use Procedure Figure 3.4-5 "Sample Use Procedure of Hardware Interrupt" shows how a hardware interrupt is used. Figure 3.4-5 Sample Use Procedure of Hardware Interrupt Start Set system stack area. Interrupt processing program Initialize internal resource. Set ICR in interrupt controller. Set internal resource operation start. Set interrupt enable bit to enable. Set ILM I in PS. Processing for interrupt to internal resource Stack processing Branch to interrupt vector. Processing by hardware Clear interrupt source. Return-from-interrupt instruction (RETI) Main program Interrupt request occurrence Main program Set system stack area. Initialize internal resource that can generate an interrupt request. Set ICR in interrupt controller. Place internal resource in operation start state. Set interrupt enable bit to enable. Set the I flag of the interrupt level mask register (ILM) in the processor status register (PS) and the I flag in the condition code register (CCR) to interrupt enabled. Internal resource interrupt occurs, causing hardware interrupt request to occur. Register is saved by interrupt processing hardware and control branches to interrupt processing program. Perform processing of internal resource for interrupt occurrence by interrupt processing program Release interrupt request of internal resource circuit. Execute return-from-interrupt instruction and return to program executed before branch. 64 3.5 Software Interrupts 3.5 Software Interrupts The software interrupt function passes control to a user-defined interrupt processing program from a program being executed by the CPU according to execution of a dedicated instruction. ■ Overview of Software Interrupts The software interrupt function is always activated by executing a software interrupt instruction. If a software interrupt occurs, the CPU responds as follows: • Saves the descriptions of the PC, PS, A, PCB, DTB, ADB, and DPR registers in the CPU in the system stack. • Sets the I flag in the condition code register (CCR). Interrupts are disabled automatically. • Fetches the contents of the corresponding interrupt vector and branches control. An interrupt caused by execution of an INT instruction (software interrupt) is not requested by interrupt request flag or interrupt enable flag. This interrupt is always requested when an INT instruction is executed. Because the INT instruction has no interrupt level, the INT instruction does not update the ILM and sets the I flag to 0, thereby placing the following interrupt requests in a hold state. ■ Software Interrupt Mechanism All mechanisms related to software interrupts are installed in the CPU. ❍ CPU Microcode: Interrupt processing step To use a software interrupt, the corresponding instruction must be executed. For interrupt vectors, as listed in Table 3.3-1 "List of Interrupt Vectors", hardware interrupts and software interrupts share the same area. For example, because interrupt request number INT 11 is used for an A/D converter interrupt (hardware interrupt) and for software interrupt INT #11, the A/D converter and INT #11 call the same interrupt processing routine for interrupt processing. ■ Software Interrupt Operation When the CPU fetches and executes a software interrupt instruction, the microcode for software interrupt processing is activated. The microcode saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) in the memory areas indicated by SSB and SSP, reads a 3-byte interrupt vector and loads the vector in the program counters (PC and PCB). The microcode also sets the I flag to 0 and the S flag to 1 in the condition code register (CCR), thereby making the user-defined interrupt handling program the next instruction to be executed. Figure 3.5-1 "Software Interrupt Occurrence to Release" shows the processing from the time a software interrupt is generated to the completion of interrupt processing. 65 CHAPTER 3 INTERRUPT Figure 3.5-1 Software Interrupt Occurrence to Release F2MC-16 bus Register file B unit Microcode Queue Fetch : Processor status : Interrupt enable flag in the CCR : Interrupt level mask register in the PS : Instruction register B unit: Bus interface unit Save Instruction bus Executes a software interrupt instruction. Saves the dedicated registers in the CPU in the register file according to the microcode corresponding to the software interrupt instruction. Interrupt processing terminates by a RETI instruction in the user interrupt processing routine. ■ Note on Software Interrupts If the program bank register (PCB) indicates FFH, the vector area of a CALLV instruction overlaps with the INT #vct8 instruction table. Generate a program such that a CALLV instruction and an INT #vct8 instruction do not use the same address. 66 3.6 Extended Intelligent I/O Service (EI2OS) 3.6 Extended Intelligent I/O Service (EI2OS) The extended intelligent I/O service (El2OS) is a type of hardware interrupt operation that transfers data automatically between I/O and memory. It allows a data transfer between I/O and memory as direct memory access (DMA) with the interrupt processing program. ■ Overview of EI2OS Interrupt Processing Compared with the conventional methods applied in interrupt processing programs, the extended intelligent I/O service (EI2OS) has the following advantages: • The size of the program can be reduced because no program for data transfer requires description. • Because internal registers are not used for data transfer, register saving is not required and transfer speeds are increased. • Because I/O can stop data transfer for convenience, unnecessary data is not transferred. • The incrementing or updating of buffer addresses can be selected. • The incrementing or updating of I/O register addresses can be selected. (If buffer address update is specified) Upon terminating data transfer, the EI2OS sets termination conditions to S1 and S0 bits in the interrupt control register (ICR) and branches control to an interrupt processing routine automatically, thereby enabling the user to determine the type of EI2OS termination conditions. To implement the EI2OS, hardware is separated into two blocks, each containing the following register and descriptor. ❍ Interrupt control register (ICR): When installed in the interrupt controller, indicates the status at EI2OS activation, EI2OS channel specification, and EI2OS termination. ❍ Extended intelligent I/O service descriptor (ISD): Installed in RAM. Holds the transfer mode, I/O addresses and transfer counts, and buffer addresses. Note: When REALOS is used, the extended intelligent I/O service (EI2OS) cannot be used. 67 CHAPTER 3 INTERRUPT ■ Operation of the Extended Intelligent I/O Service (EI2OS) Figure 3.6-1 "Outline of the Extended Intelligent I/O Service" outlines the EI2OS operation. Figure 3.6-1 Outline of the Extended Intelligent I/O Service Memory space Peripheral I/O register I/O register circuit Interrupt request Interrupt control register Interrupt controller The I/O requests transfer. The interrupt controller selects a descriptor. Reads a transfer source/destination from the descriptor. Data is transferred between I/O and memory. Buffer The interrupt source is cleared automatically. Note: The IOA can specify areas 000000H to 00FFFFH. The BAP can specify areas 000000H to FFFFFFH. The DCT can specify the transfer count up to 65536. 68 3.6 Extended Intelligent I/O Service (EI2OS) ■ Structure of the extended intelligent I/O service (EI2OS) EI2OS-related structures can be divided into the following 4 categories: ❍ Internal resource Interrupt enable bit, interrupt request bit: Control interrupt requests from resources ❍ Interrupt controller ICR: Assigns levels to interrupts, decides priorities of concurrent interrupt requests, and selects EI2OS operation. ❍ CPU I, ILM: Compares requested interrupt levels with the current level and identifies the interrupt enable state. Microcode: EI2OS processing step ❍ RAM Descriptor: Describes EI2OS transfer information. 69 CHAPTER 3 INTERRUPT 3.6.1 Interrupt Control Register (ICR) Interrupt control registers are installed in the interrupt controller. An ICR register corresponds to each I/O having an interrupt function. An ICR register has the following functions: • Setting an interrupt level of the corresponding peripheral circuit • Selecting an interrupt from the corresponding peripheral circuit as an ordinary interrupt or an extended intelligent I/O service • Selecting the channel of the extended intelligent I/O service Accessing this register by a read modify write instruction will result in a malfunction. ■ Interrupt control register (ICR) Figure 3.6-2 Interrupt Control Register (ICR) Interrupt control register (ICR) Bit number Address: B0H to BFH For write operation Read/write Initial value Address: B0H to BFH Bit number For read operation Read/write Initial value Note: ICS3 to ICS0 are valid only when the EI2OS is to be activated. To activate the EI2OS, set ISE to 1. To not activate the EI2OS, set ISE to 0. When the EI2OS is not activated, ICS3 to ICS0 can be set as required. ICS1 and ICS0 are valid for writing only. S1 and S0 are valid for reading only. [Bits 15 to 12][Bits 7 to 4]: ICS3 to ICS0 (extended intelligent I/O service channel select bits) EI2OS channel select bits. These bits are provided for writing only. EI2OS channels are specified by these bits. The address of an extended intelligent I/O service descriptor in memory is determined by the value set in the bits. The ICS bits are initialized to 0000 by a reset. 70 3.6 Extended Intelligent I/O Service (EI2OS) Table 3.6-1 Correspondence between EI2OS Channel Selection Bits and Descriptor Addresses ICS3 ICS2 ICS1 ICS0 Channel to be selected Descriptor address 0 0 0 0 0 000100H 0 0 0 1 1 000108H 0 0 1 0 2 000110H 0 0 1 1 3 000118H 0 1 0 0 4 000120H 0 1 0 1 5 000128H 0 1 1 0 6 000130H 0 1 1 1 7 000138H 1 0 0 0 8 000140H 1 0 0 1 9 000148H 1 0 1 0 10 000150H 1 0 1 1 11 000158H 1 1 0 0 12 000160H 1 1 0 1 13 000168H 1 1 1 0 14 000170H 1 1 1 1 15 000178H [Bits 13 and 12][Bits 5 and 4]: S0, S1 (extended intelligent I/O service status) EI2OS termination status bit. These bits are provided for reading only. By checking the value of these bits at termination of the EI2OS, the termination conditions can be determined. The bits are initialized to 00 at a reset. Table 3.6-2 Relationship between EI2OS Status Bits and EI2OS Status SI S0 Termination condition 0 0 EI2OS is in operation or not activated. 0 1 Stop status due to count termination 1 0 Reserved 1 1 Stop status due to a request from an internal resource [Bit 11][Bit 3]: ISE (extended intelligent I/O service enable bit) EI2OS enable bit. If this bit is set to 1 at occurrence of an interrupt request, the EI2OS is activated. If the bit is set to 0, the interrupt sequence is activated. The ISE bit is set to 0 when the EI2OS terminates (due to count termination or a request from an internal resource). 71 CHAPTER 3 INTERRUPT If the corresponding internal resource has no EI2OS function, the ISE bit must be set to 0 by software. This bit is readable and can be written. The bit is initialized to 0 by a reset. [Bits 10 to 8][Bits 2 to 0]: IL0, IL1, IL2 (interrupt level setting bits) Interrupt level setting bits. These bits specify the level of a corresponding internal resource interrupt. These bits are readable and can be written. These bits are initialized to level 7 (no interrupt) by a reset. Table 3.6-3 Correspondence between Interrupt Level Setting Bits and Interrupt Levels 72 IL2 IL1 IL0 Interrupt level 0 0 0 0 (highest-level interrupt) 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 (lowest-level interrupt) 1 1 1 7 (No interrupt) 3.6 Extended Intelligent I/O Service (EI2OS) 3.6.2 Extended Intelligent I/O Service Descriptor (ISD) The extended intelligent I/O service descriptor (ISD) is located at 000100H to 00017FH in internal RAM and contains the following data: • Various types of control data for data transfer • Status data • Buffer address pointers ■ Extended intelligent I/O service descriptor (ISD) The ISD is in 000100H to 00017FH in internal RAM and contains: • Various types of control data for data transfer • Status data • Buffer address pointer Figure 3.6-3 "Structure of Extended Intelligent I/O Service Descriptor" shows the structure of the extended intelligent I/O service descriptor. Figure 3.6-3 Structure of Extended Intelligent I/O Service Descriptor Data counter higher 8 bits (DCTH) Data counter lower 8 bits (DCTL) I/O address pointer higher 8 bits (IOAH) I/O address pointer lower 8 bits (IOAL) EI2OS status (ISCS) Buffer address pointer higher 8 bits (BAPH) Buffer address pointer middle 8 bits (BAPM) ISD head address Buffer address pointer lower 8 bits (BAPL) 73 CHAPTER 3 INTERRUPT 3.6.3 Registers of the Extended Intelligent I/O Service Descriptor (ISD) The extended intelligent I/O service descriptor (ISD) contains the following registers: • Data counter (DTC) • I/O register address pointer (IOA) • EI2OS status register (ISCS) • Buffer address pointer (BAP) ■ Data Counter (DCT) A 16 bit register used as a counter for counting transfer data items. After data transfer, this counter is decremented by one. When this counter is 0, the EI2OS terminates. Figure 3.6-4 Structure of Data Counter (DTC) Data counter higher bits Bit number DCTH Initial value Bit number Data counter lower bits DCTL Initial value ■ I/O Register Address Pointer (IOA) A 16 bit register that indicates a lower address (A15 to A0) of the I/O register with which a buffer switches data. All higher address bits (A23 to A16) are set to 0. An I/O from 000000H to 00FFFFH can be specified. Figure 3.6-5 Structure of I/O Register Address Pointer (IOA) I/O address pointer higher bits Bit number IOAH Initial value I/O address pointer lower bits Bit number IOAL Initial value 74 3.6 Extended Intelligent I/O Service (EI2OS) ■ EI2OS Status Register (ISCS) An 8 bit register that updates/fixes the buffer address pointer and I/O register address pointer and indicates a unit of transfer data length (bytes/words) and transfer direction. Figure 3.6-6 Structure of EI2OS Status Register (ISCS) 2 EI OS Status Register (ISCS) Bit number Reserved Reserved Reserved Read/write Initial value [Bits 7 to 5]: Reserved bits Write 0. [Bit 4]: IF Specifies whether the I/O register address pointer is to be updated or fixed. Table 3.6-4 IF Bit Functions IF Function 0 The I/O register address pointer is updated (incremented) after data transfer. 1 The I/O register address pointer is fixed after data transfer. [Bit 3]: BW Specifies a unit of transfer data length. Table 3.6-5 BW Bit Functions BW Function 0 Bytes 1 Words [Bit 2]: BF Specifies whether the buffer address pointer is to be updated or fixed. Table 3.6-6 BF Bit Functions BF Function 0 The buffer address pointer is updated (incremented) after data transfer. 1 The buffer address pointer is fixed after data transfer. Note: Only the buffer address pointer can be incremented because only the lower 16 bits are changed. 75 CHAPTER 3 INTERRUPT [Bit 1]: DIR Specifies the direction of data transfer. Table 3.6-7 DIR Bit Functions DIR Function 0 I/O address pointer --> Buffer address pointer 1 Buffer address pointer --> I/O address pointer. [Bit 0]: SE Controls termination of the extended intelligent I/O service on request from an internal resource. Table 3.6-8 EI2OS Termination Control Bits SE Function 0 The service is not terminated by a request from an internal resource. 1 The service is terminated by a request from an internal resource. ■ Buffer Address Pointer (BAP) A 24 bit register that holds an address to be used next for transfer by the EI2OS. Because a BAP is installed for each EI2OS channel separately, an EI2OS channel can be used for transfer with anywhere in the 16-Mbyte space. Note: If the BF bit in the EI2OS status register (ISCS) is set to "update", the lower 16 bits (BARM and BAPL) of the BAP change, but the higher 8 bits (BAPH) do not change. 76 3.6 Extended Intelligent I/O Service (EI2OS) 3.6.4 Operation When an interrupt request is issued from the peripheral functions and the El2OS activation is specified in corresponding interrupt register (ICR), the CPU transfers the data by El2OS. When all the specified number of data transfers are completed, the hardware interrupt processing automatically starts. ■ Procedure for Extended Intelligent I/O Service (EI2OS) Processing Figure 3.6-7 "EI2OS Operation Flow" shows the operation flow of EI2OS operation using CPUinternal microcode. Figure 3.6-7 EI2OS Operation Flow Interrupt request occurrence from internal resource Interrupt sequence Read ISD/ISCS. Termination request from resource? IOA-indicated data BAP-indicated data (Data transfer) BAP-indicated memory (Data transfer) IOA-indicated memory Update value depends on BW. Update IOA. Update value depends on BW. Update BAP. Decrement DCT. Set S1 and S0 to 01. Set S1 and S0 to 11. Set S1 and S0 to 00. BAP : IOA : ISD : ISCS : DCT : ISE : S1, S0: Clear resource interrupt request. Clear ISE to 0. Return to CPU operation Interrupt sequence Buffer address pointer I/O register address pointer EI2OS descriptor EI2OS status Data counter EI2OS enable bit EI2OS termination status IF : BW: BF : DIR: SE : IOA update/fix selection bit of EI2OS status register (ISCS) Transfer data length specification bit of EI2OS status register (ISCS) BAP update/fix selection bit of EI2OS status register (ISCS) Data transfer direction specification bit of EI2OS status register (ISCS) EI2OS termination control bit of EI2OS status register (ISCS) 77 CHAPTER 3 INTERRUPT 3.6.5 Procedure for Using the Extended Intelligent I/O Service (EI2OS) Use of the extended intelligent I/O service (El2OS) requires that the system stack area, extended intelligent I/O service (El2OS) descriptor, peripheral functions, and interrupt control register (ICR) be specified. ■ Procedure for Using the Extended Intelligent I/O Service (EI2OS) Figure 3.6-8 "EI2OS Use Procedure Flow" shows the processing of the extended intelligent I/O service (EI2OS) in terms of hardware and software. Figure 3.6-8 EI2OS Use Procedure Flow Software processing Hardware processing Start Set system stack area. Initial setting Set EI2OS descriptor. Initialize internal resource. Set ICR in interrupt controller. Set start of internal resource operation. Set interrupt enable bit. Set ILM I in PS. (Interrupt request) and (ISE=1) Execute user program. Transfer data. Branch to interrupt due to count out or termination request from resource? (Branch to interrupt vector) Re-set extended intelligent I/O service (channel switching, etc.) Buffer data processing ISE : EI2OS enable bit of interrupt control register (ICR) S1, S0: EI2OS status of interrupt control register (ICR) 78 3.6 Extended Intelligent I/O Service (EI2OS) 3.6.6 EI2OS Execution Time The execution time for the extended intelligent I/O service (EI2OS) changes depending on the following: • Setting of the EI2OS status register (ISCS) • Address (area) indicated by the I/O register address pointer (IOA) • Address (area) indicated by the buffer address pointer (BAP) • External data bus width for external access operations • Data length of transfer data Moreover, an interrupt handling time is added because a hardware interrupt is activated when the EI2OS terminates data transfer. ■ Execution Time of the Extended Intelligent I/O Service (EI2OS) (Transfer Time for One Operation) ❍ When data transfer continues (the stop conditions are not met) The EI2OS execution time when data transfer continues is determined by the EI2OS status register (ISCS) setting, as shown in Table 3.6-9 "Execution Time when EI2OS Continues". Table 3.6-9 Execution Time when EI2OS Continues Set to 0 Settings of EI2OS termination control bits (ISCS and SE) I/O address pointer Setting of BAP address update/fix selection bit (BF) Unit: Set to 1 Fixed Updated Fixed Updated Fixed 32 34 33 35 Updated 34 36 35 37 Machine cycle (1 machine cycle is equivalent to 1 clock cycle of the machine clock (φ)). Values require correction depending on the conditions at the time of EI2OS execution, as shown in Table 3.6-10 "Correction Value of Data Transfer of EI2OS Execution Time". 79 CHAPTER 3 INTERRUPT Table 3.6-10 Correction Value of Data Transfer of EI2OS Execution Time I/O register address pointer Buffer address pointer Internal access External access B/even Odd B/even 8/odd Internal access B/even 0 +2 +1 +4 Odd +2 +4 +3 +6 External access B/even +1 +3 +2 +5 8/odd +4 +6 +5 +8 B: Byte-data transfer Even: Even-numbered address/word transfer 8: 8-bit external bus width/word transfer Odd: Odd-numbered address/word transfer ❍ At the time of count termination of the data counter (DCT) (at the time of the final data transfer) An interrupt handling time is added because a hardware interrupt is activated when the EI2OS terminates data transfer. EI2OS execution time at the time of count termination is calculated (using the formula) as follows: EI2OS execution time at the time of count termination = EI2OS execution time at the time of data transfer + interrupt handling time (21+ 6 x Z) machine cycles The interrupt handling time depends on the address indicated by the stack pointer. Table 3.611 "Correction Value (Z) of Interrupt Handling Time" lists correction value (Z) of interrupt handling time. Table 3.6-11 Correction Value (Z) of Interrupt Handling Time Address indicated by the stack pointer 80 Correction value (Z) External 8-bit +4 Even address at external access +1 Odd address at external access +4 Even address at internal access 0 Odd address at internal access +2 3.6 Extended Intelligent I/O Service (EI2OS) ❍ At termination following a termination request from the peripheral functions (I/O) When data transfer by the EI2OS terminated in the middle of the execution (ICR: S1, S0 = 11) following a termination request from peripheral functions (I/O), no data is transferred and only a hardware interrupt is thrown. In this case, the EI2OS execution time can be calculated using the following formula. Z in the formula indicates the correction value of the interrupt processing time. (See Table 3.6-11 "Correction Value (Z) of Interrupt Handling Time".) EI2OS execution time when processing terminates midway through = 36 + 6 x Z machine cycles Note: 1 machine cycle is equivalent to 1 clock cycle of the machine clock (φ). 81 CHAPTER 3 INTERRUPT 3.7 Exception In the F2MC-16LX, the execution of an undefined instruction results in an exception and exception processing, which is basically the same as interrupt processing. When an exception is detected at the boundary of an instruction, control passes from ordinary processing to exception processing. Because exception processing generally occurs if an undefined operation is executed, exception processing should be used only for debugging or as an emergency measure to activate recovery software. ■ Exception Occurrence due to Execution of Undefined Instruction The F2MC-16LX treats all codes not defined in the instruction map as undefined instructions. If an undefined instruction is executed, processing equivalent to software interrupt instruction INT 10 is performed. That is, the AL, AH, DPR, DTB, ADB, PCB, PC, and PS descriptions are saved in the system stack. The I flag of the condition code register (CCR) is set to 0 and the S flag is set to 1, and control branches to the routine indicated by the vector of interrupt number 10. The PC value saved in the stack indicates the address storing the undefined instruction. For an instruction code of two bytes or more, because the address stores the code that can be recognized as an undefined code, control can be returned by a RETI instruction, though it is meaningless because the exception occurs again. 82 CHAPTER 4 CLOCK AND RESET This chapter describes the functions and operations of the clock and reset. 4.1 "Clock Generator" 4.2 "Clock Supply Map" 4.3 "Reset Source" 4.4 "Operation after a Reset is Released" 83 CHAPTER 4 CLOCK AND RESET 4.1 Clock Generator The clock generator controls operation of the internal clock, including the sleep, watch, and stop modes and the PLL clock multiplication functions. The internal clock is called a machine clock; one cycle of which is used as a machine cycle. The clock generated by OSC oscillation is called an oscillation clock. The clock generated by internal VCO oscillation is called a PLL clock. ■ Notes for the Clock Generator When the operating voltage is 5 V, the OSC oscillation frequency range is from 3 to 16 MHz, but the maximum operating frequency of the CPU and peripheral circuits is 16 MHz. If the frequency generated by the specified multiplication factor exceeds the maximum operating frequency, the CPU and peripheral circuits do not operate normally. For example, if the frequency of OSC oscillation is 16 MHz, only 1 can be specified as the multiplication factor. The minimum operating frequency of VCO oscillation is 4 MHz; any frequency less than 4 MHz cannot be specified. Figure 4.1-1 Clock Generator Block Diagram Reset Interrupt HSTX S Q Transition to the watch or sleep mode S Q Machine clock Machine clock selection R R S Q Transition to the stop mode R 1 2 3 4 PLL multiplication Oscillation stabilization time selection Time base timer 1/2 X0 X1 1/2048 1/4 1/4 1/8 Watchdog interval selection Monitoring timer Watchdog reset 84 4.2 Clock Supply Map 4.2 Clock Supply Map Figure 4.2-1 "Clock Supply Map" shows the clock supply map. ■ Clock Supply Map Figure 4.2-1 Clock Supply Map Oscillation clock OSC oscillation Time base timer output Time base timer External interrupt channels 0 to 7 8/16-bit PPG 0/1 Multiplication factor selection Machine clock PLL multiplication circuit Main clock PLL clock Selector Two 8-bit DAC channels CPU clock Communication prescaler channels 0.7 Extended serial I/O interface channels 0/1/2 A/D converter Chip select Input capture 16-bit free running timer Output compare Clock monitor function Up/down counter 85 CHAPTER 4 CLOCK AND RESET 4.3 Reset Source The five types of reset sources are as follows: • Occurrence of a power-on reset • Release of the hardware standby state • Watchdog timer overflow • Occurrence of an external reset request by the RSTX pin • Occurrence of a reset request by the software ■ Reset Source When the stop mode is released or a power-on reset occurs, operation starts following elapse of the oscillation stabilization time. When a reset factor occurs, the F2MC-16LX immediately stops executing current processing and enters the reset release wait state. The machine clock and watchdog function initial states differ depending on the reset factor. The reset factor bits in the watchdog control register can be checked to determine the reset factor. Note: Because the external reset input is sampled in synchronization with the internal clock in a mode other than the stop mode, no reset input is accepted when the externally supplied clock stops. When the external bus is used and a reset factor occurs, the address generated by each device during reset is undefined. All external bus access signals, such as RDX and WRX, become inactive. Table 4.3-1 Reset Factors Reset Factor Machine clock Watchdog timer Oscillation stabilization time Power-on The power is turned on. Main clock Stopped Required Hardware standby The HSTX pin input becomes low. Main clock Stopped Required Watchdog timer The watchdog timer overflows. Main clock Stopped Required External pin The RSTX pin input becomes low. Retains the prereset status. Retains the prereset status. Not required Software "0" is written in the RST bit in the STBYC. Retains the prereset status. Retains the prereset status. Not required 86 • When the reset input is received in the stop or hardware standby mode, the oscillation stabilization time is required for a reset factor. • These bits are not initialized by a reset other than a power-on reset. When a power-on reset 4.3 Reset Source occurs, these bits are initialized to "11", and so the oscillation stabilization time for the main clock at power-on is about 218 OSC oscillation cycles for evaluation products and about 217 OSC oscillation cycles for FLASK/MASK products. Other oscillation stabilization times are determined by the WS1/WS0 ratio of the clock selection register (CKSCR). There is a flip-flop corresponding to each reset factor. The status of each flip-flop can be checked by reading the watchdog control register. To identify the reset factor after releasing a reset, ensure that branching of an appropriate program occurs after the value read from the watchdog control register is processed by software. Figure 4.3-1 Reset Factor Bit Block Diagram HSTX pin RSTX pin Not cleared periodically RST bit set Power-on Hardware standby release detection circuit Power-on detection circuit External reset request detection circuit Watchdog timer reset detection circuit STBYC.RST bit write detection circuit WTC register Delay circuit WTC register read F2MC-16LX internal bus When multiple reset factors occur, the corresponding reset factor bits in the watchdog control register are set to "1". When an external reset request and watchdog reset occur simultaneously, the ERST and WRST bits are both set to "1". This rule does not apply to a power-on reset. When the PONR bit is "1", the values of the other bits do not indicate normal reset factors, and so a software program should be created that ignores the values of other bits when the PONR bit is "1". Table 4.3-2 Correspondence between the Reset Factors and the Values of the Reset Factor Bits Reset factor PONR STBR WRST ERST SRST Power-on 1 — — — — Hardware standby * 1 * * * Watchdog timer * * 1 * * External pin * * * 1 * RST bit * * * * 1 (An asterisk (*) indicates that the value before reset is retained.) Note: The reset factor bits are cleared only when the watchdog control register is read. The reset factor bit corresponding to a reset factor that has occurred once remains set to "1" when another reset factor occurs. For the configuration of the watchdog control register and the reset factor bits, see CHAPTER 10 "WATCHDOG TIMER". 87 CHAPTER 4 CLOCK AND RESET 4.4 Operation after a Reset is Released When the reset factor is removed, the F2MC-16LX immediately outputs the address at which the reset vector is stored and fetches the reset vector and mode data. A 4-byte area at FFFFDCH to FFFFDFH is allocated for the reset vector and mode data, which are transferred to the corresponding registers by hardware following a reset release. ■ When Reset is Released Use the mode pins to specify the internal ROM or external memory from which to read the reset vector and mode data. When the external vector mode is specified using the mode pins, the reset vector and mode data are read from the external memory not the internal ROM, and so when the microcontroller is to be used in single chip mode or internal ROM and external bus mode, specifying the internal vector mode using the mode pins is recommended. The bus mode after the reset vector and mode data are read is specified by mode data. Figure 4.4-1 Locations and Destinations of the Reset Vector and of Mode Data Memory space F2MC-16LX CPU core Mode register Mode data Bits 23 to 16 of the reset vector Bits 15 to 8 of the reset vector Bits 7 to 0 of the reset vector Micro ROM Reset sequence Note: The contents of the mode register in the figure above are undefined immediately after reset. Store any mode data in memory space in advance to ensure that a write operation will be performed. 88 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT This chapter describes the functions and operations of the low-power consumption control circuit. 5.1 "Overview of the Low-Power Consumption Control Circuit" 5.2 "Block Diagram of the Low-Power Consumption Control Circuit" 5.3 "Registers of the Low-Power Consumption Control Circuit" 5.4 "Status Transition for Clock Selection" 89 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT 5.1 Overview of the Low-Power Consumption Control Circuit The low-power consumption control circuit normally uses the low-power consumption mode as the operating mode. The intermittent CPU operation function and oscillation stabilization time can be set by setting the corresponding register bits. In the entire block diagram, the low-power consumption control circuit is part of the clock control circuit (see Section 1.3 "Block Diagram" of the MB90570 Series). ■ Operating Modes of the Low-Power Consumption Control Circuit The operating modes are as follows: • PLL clock mode • PLL sleep mode • PLL watch mode • Pseudo watch mode • Main clock mode • Main clock sleep mode • Main clock watch mode • Main clock stop mode • Subclock mode • Subclock sleep mode • Subclock watch mode • Subclock stop mode • Hardware standby mode Operating modes other than the PLL clock mode are categorized as low-power consumption modes. 90 5.1 Overview of the Low-Power Consumption Control Circuit ■ Intermittent CPU Operation Function The intermittent CPU operation function stops the clock provided to the CPU and delays the start of the internal bus cycle when a register, internal memory, internal peripheral, or external bus is accessed. Processing can be performed with low-power consumption because CPU execution speed is reduced with the provision of a high-speed clock to the internal peripherals. Use the CG1 and CG0 bits in the LPMCR to select the temporary stop cycle count for the clock provided to the CPU. The external bus operation itself is performed using the same clock as that used for the peripherals. The execution time required when the intermittent CPU operation function is used can be obtained as follows: • Adds the compensation value obtained by multiplying the number of accesses of registers, internal memories, internal peripherals, and external buses by the temporary stop cycle count of the normal execution time. ■ Setting of the Oscillation Stabilization Time for the Main Clock Use the WS1 and WS0 in the CKSCR bits to select the oscillation stabilization time for the main clock required when the stop or hardware standby mode is released. Select the oscillation stabilization time according to the types and characteristics of the oscillation device and the oscillator connected to the X0 and X1 pins. These bits are not initialized by a reset other than a power-on reset. When a power-on reset occurs, these bits are initialized to "11". and so the oscillation stabilization time for the main clock at power-on is about 218 OSC oscillation cycles for evaluation products and about 217 OSC oscillation cycles for FLASK/MASK products. ■ Switching of the Machine Clock ❍ Switching between the main and the PLL clocks Writing to the MCS bit in the CKSCR register switches between the main and the PLL clocks. Setting the MCS bit from "1" to "0" switches the machine clock from the main clock to the PLL clock after the oscillation stabilization time for the PLL clock (212 machine clock cycles) has elapsed. Setting the MCS bit from "0" to "1" switches the machine clock from the PLL clock to the main clock. This switch occurs when a PLL clock edge coincides with a main clock edge (after one to eight PLL clock cycles). When the MCS bit is rewritten, the machine clock is not switched immediately. Operate each peripheral according to the machine clock after referencing the MCM bit in the CKSCR to confirm that the machine clock has been switched. 91 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT ❍ Switching between the main clock and subclock Writing to the SCS bit in the CKSCR register switches between the main clock and subclock. Setting the SCS bit from "1" to "0" switches the machine clock from the main clock to the subclock. This switch occurs when a subclock edge is detected. Setting the SCS bit from "0" to "1" switches the machine clock from the subclock to the main clock after the oscillation stabilization time for the main clock has elapsed. When the SCS bit is rewritten, the machine clock is not switched immediately. Operate each peripheral after checking whether it is dependent on the machine clock. Note: When tune on the power or hardware standby mode or stop mode is released, the subclock osciliation stabilization time (about 2 seconds) is generated. In the meantime, when switching from the main clock mode to the subclock mode, the osciliation stabilization time is generated. ❍ Machine clock initialization The MCS and SCS bits are not initialized by a reset by an external pin or the RST bit in the LPMCR, but are initialized to "1" by other resets. ■ PLL Clock Multiplication Function A PLL clock multiplication factor can be selected among 2, 4, 6, and 8 using the CS1 and CS0 bits. The clock obtained by dividing the selected clock by 2 is used as the machine clock. 92 5.2 Block Diagram of the Low-Power Consumption Control Circuit 5.2 Block Diagram of the Low-Power Consumption Control Circuit Figure 5.2-1 "Block Diagram of the Low-Power Consumption Control Circuit and Clock Generator" shows a block diagram. ■ Block Diagram of the Low-Power Consumption Control Circuit Figure 5.2-1 Block Diagram of the Low-Power Consumption Control Circuit and Clock Generator Subclock Subclock switch control Main clock (OSC oscillation) PLL multiplication circuit CPU clock generation CPU clock CPU F2MC-16 bus CPU clock selector 0/9/17/33 Intermittent cycle selection Cycle count selection circuit for the intermittent CPU operation function Peripheral clock generation Peripheral clock Main OSC stop Standby control circuit Sub OSC stop HST start Release HSTX pin Interrupt request or RST Clock input Oscillation stabilization time selector Time base timer Pin high impedance control circuit Self refresh control circuit Internal reset generator Pin HI-Z Self refresh RSTX pin Internal RST To the watchdog timer 93 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT 5.3 Registers of the Low-Power Consumption Control Circuit The following two types of low-power consumption control circuit register are provided: • Low-power consumption mode control register • Clock selection register ■ Registers in the Low-Power Consumption Control Circuit Figure 5.3-1 Registers in the Low-Power Consumption Control Circuit Low-power consumption mode control register Bit number Address Read/write Initial value Clock selection register Bit number Address Read/write Initial value 94 5.3 Registers of the Low-Power Consumption Control Circuit 5.3.1 Low-Power Consumption Mode Control Register (LPMCR) This section describes the bit configuration and functions of the low-power consumption mode control register (LPMCR) ■ Low-Power Consumption Mode Control Register (LPMCR) Figure 5.3-2 Low-Power Consumption Mode Control Register (LPMCR) Low-Power Consumption Mode Control Register (LPMCR) Bit number Address Read/write Initial value [Bit 7] STP Writing "1" causes a transition to the pseudo watch mode (when MCS is 0 and SCS is 1 in the CKSCR) or stop mode (when MCS is 1 or SCS is 0 in the CKSCR). Writing "0" does not start an operation. When a reset occurs or the watch or stop mode is released, this bit is cleared to "0" and is a write-only bit. The read value is always "0". [Bit 6] SLP Writing "1" causes a transition to the sleep mode. Writing "0" does not start an operation. When a reset occurs or the sleep or stop mode is released, this bit is cleared to "0". Writing "1" in the STP and SLP bits simultaneously causes a transition to the pseudo watch mode or stop mode. This bit is a write-only bit. The read value is always "0". [Bit 5] SPL When this bit is "0". the external pin levels are retained in the watch or stop mode. When the bit is "1". the external pins are set to high impedance in the watch or stop mode. When a reset occurs, this bit is cleared to "0" and is a read/write bit. [Bit 4] RST Writing "0" generates the internal reset signal for three machine cycles. Writing "1" does not start an operation. When this bit is read, the value is "1". [Bit 3] TMD Writing "0" causes a transition to the watch mode. Writing "1" does not start an operation. When a reset occurs or the watch or stop mode is released, this bit is cleared to "1" and is a write-only bit. The read value is always "1". [Bits 2 and 1] CG1 and CG0 These bits set the temporary stop cycle count for the intermittent CPU operation function. When a reset is caused by power-on, hardware standby, or watchdog, these bits are initialized to "00". These bits are not initialized by a reset as a result of another reset factor and are read/write bits. 95 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT Table 5.3-1 "CG Bit Settings" lists the CG bit settings. Table 5.3-1 CG Bit Settings CG1 CG0 Temporary stop cycle count for the CPU clock 0 0 0 cycle (CPU clock = peripheral clock) 0 1 9 cycles (CPU clock = peripheral clock = 1:about 3 to 4) 1 0 17 cycles (CPU clock = peripheral clock = 1:about 5 to 6) 1 1 33 cycles (CPU clock = peripheral clock = 1:about 9 to 10) [Bit 0] SSR When this bit is "1". DRAMC self refresh control is exercised in the sleep (main or PLL), watch, or stop mode. When a reset occurs, this bit is cleared to "0" and is a read/write bit. ■ Accessing the Low-Power Consumption Mode Control Register (LPMCR) Setting the low-power consumption mode control register enters the low-power consumption mode. Use the instructions listed in Table 5.3-2 "Instructions to Be Used for Switching to LowPower Consumption Mode" for this purpose. Using other instructions to start low-power consumption mode may cause a malfunction. Any instruction can be used to control functions other than switching to low-power consumption mode from the low-power mode control register. To use word length to write data to the low-power mode control register, be sure that even addresses are used. Writing with odd addresses to start low-power consumption mode may cause a malfunction. Table 5.3-2 Instructions to Be Used for Switching to Low-Power Consumption Mode 96 MOV io,#imm8 MOV dir,#imm8 MOV eam,#imm8 MOV eam,#immRi MOV io,A MOV dir,A MOV addr16,A MOV eam,A MOV RLi+dip8,A MOVP addr24,A MOVW io,#imm16 MOVW dir,#imm16 MOVW eam,#imm16 MOVW eam,RWi MOVW io,A MOVW dir,A MOVW addr16,A MOVW eam,RWi MOVW RLi+dip8,A MOPW addr24,A SETB io:bp SETB dir:bp SETB addr16:bp 5.3 Registers of the Low-Power Consumption Control Circuit 5.3.2 Clock Selection Register (CKSCR) This section describes the bit configuration and functions of the clock selection register (CKSCR). ■ Clock Selection Register (CKSCR) Figure 5.3-3 Clock Selection Register (CKSCR) Bit number Address Read/write Initial value [Bit 15] SCM This bit indicates whether the main clock or subclock is selected as the machine clock. When this bit is "0". the subclock is selected. When this bit is "1". the main clock is selected. When SCS is 1 and SCM is 1, the main clock is in the oscillation stabilization wait state. Setting the SCS bit in the CKSCR from "1" to "0" switches the machine clock from the main clock to the subclock mode. This switch occurs in synchronization with the subclock (about 130 µs). Setting the SCS bit in the CKSCR from "0" to "1" switches the machine clock from the subclock to the main clock mode after the oscillation stabilization time for the main clock has elapsed. The timebase timer is automatically cleared. [Bit 14] MCM This bit indicates whether the main or the PLL clock is selected as the machine clock. When this bit is "0". the PLL clock is selected. When this bit is "1". the main clock is selected. When MCS is "0" and MCM is "1", the PLL clock is in the oscillation stabilization wait state. The oscillation stabilization time for the PLL clock is fixed to 213 main clock cycles. [Bits 13 and 12] WS1 and WS0 These bits set the oscillation stabilization time for the main clock after the stop or hardware standby mode is released. These bits are initialized to "11" by a power-on reset, are not initialized by a reset as a result of another reset factor, and are read/write bits. Table 5.3-3 "WS Bit Settings" lists the WS bit settings. Table 5.3-3 WS Bit Settings WS1 WS0 Oscillation stabilization time (OSC oscillation: 4 MHz) 0 0 No oscillation stabilization time 0 1 About 2.05 ms (213 OSC oscillation cycles) 97 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT Table 5.3-3 WS Bit Settings (Continued) WS1 WS0 Oscillation stabilization time (OSC oscillation: 4 MHz) 1 0 About 8.19 ms (215 OSC oscillation cycles) 1 1 About 65.54 ms (218 OSC oscillation cycles) [Initial value] Note: When tune on the power or hardware standby mode or stop mode is released, the subclock osciliation stabilization time (about 2 seconds) is generated. In the meantime, when switching from the main clock mode to the subclock mode, the osciliation stabilization time is generated. [Bit 11] SCS This bit specifies whether the main clock or subclock is to be selected as the machine clock. Writing "0" selects the subclock. Writing "0" selects the main clock. When this bit is "0", writing "1" switches the machine clock from the main clock to the subclock mode. This switch occurs in synchronization with the subclock (about 130 µs). When this bit is "1", writing "0" switches the machine clock from the subclock to the main clock mode after the oscillation stabilization time for the main clock has elapsed. At this time, automatically clears the timebase timer. When both SCS and MCS are "0", the value set for SCS is used and the subclock is selected. [Bit 10] MCS This bit specifies whether the main or the PLL clock is to be selected as the machine clock. Writing "0" selects the PLL clock. Writing "1" selects the main clock. When this bit is "1". writing "0" automatically clears the time base timer to generate the oscillation stabilization time for the PLL clock. The oscillation stabilization time for the PLL clock is fixed to 213 main clock cycles. The clock obtained by dividing the main clock by 2 is used as the operating clock when the main clock is selected (when the OSC oscillation frequency is 4 MHz, the operating clock frequency is 2 MHz). This bit is initialized to "1" by a power-on, hardware standby, or watchdog reset. Note: Before setting the MCS bit from "1" to "0", ensure that the time base timer interrupt is masked by the TBIE bit of the time base timer control register (TBTC) or interrupt level mask register (ILM). Because it may not be possible for eight machine cycles to set the MCS bit to "0" after it was set to "1", set it to "0" after waiting eight or more machine cycles. [Bits 9 and 8] CS1 and CS0 These bits select a multiplication factor for the PLL clock and are not initialized by a reset caused by an external pin or the RST bit. The bits are initialized to "00" by a power-on, hardware standby, or watchdog reset. When the MCS bit is "0". a write operation is suppressed. Set the MCS bit to "1" (main clock mode), then write the CS bits. The CS bits are read/write bits. 98 5.3 Registers of the Low-Power Consumption Control Circuit Table 5.3-4 "CS Bit Settings" lists the CS bit settings. Table 5.3-4 CS Bit Settings CS1 CS0 Machine clock (OSC oscillation: 4 MHz) 0 0 4 MHz (The operating frequency is equal to the OSC oscillation frequency.) 0 1 8 MHz (The operating frequency is equal to the frequency obtained by multiplying the OSC oscillation frequency by 2.) 1 0 12 MHz (The operating frequency is equal to the frequency obtained by multiplying the OSC oscillation frequency by 3.) 1 1 16 MHz (The operating frequency is equal to the frequency obtained by multiplying the OSC oscillation frequency by 4.) 99 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT 5.4 Status Transition for Clock Selection Figure 5.4-1 "Status Transition Diagram for Clock Selection (1)" and Figure 5.4-2 "Status Transition Diagram for Clock Selection (2)" show status transition for clock selection. ■ Status Transition for Clock Selection Figure 5.4-1 Status Transition Diagram for Clock Selection (1) Power-on Main clock Main clock Subclock Main clock Subclock Main clock PLL multiplication factor: 1 Main clock PLL multiplication factor: 2 Main clock PLL multiplication factor: 3 Main clock PLL multiplication factor: 4 The MCS bit is cleared and the SCS bit is set. The oscillation stabilization time for the PLL clock has elapsed and CS1 and CS0 are 00. The oscillation stabilization time for the PLL clock has elapsed and CS1 and CS0 are 01. The oscillation stabilization time for the PLL clock has elapsed and CS1 and CS0 are 10. The oscillation stabilization time for the PLL clock has elapsed and CS1 and CS0 are 11. The MCS bit is set or the SCS bit is cleared. The PLL clock synchronizes with the main clock and SCS is 1. The PLL clock synchronizes with the main clock and SCS is 0. The oscillation stabilization time for the main clock has elapsed and MCS is 0. 100 5.4 Status Transition for Clock Selection Figure 5.4-2 Status Transition Diagram for Clock Selection (2) Power-on Main clock Subclock Main clock Subclock Subclock Main clock Subclock Main clock The SCS bit is cleared. The subclock edge is detected. The SCS bit is set. The oscillation stabilization time for the main clock has elapsed and MCS is 1. The PLL clock synchronizes with the main clock and SCS is 0. The oscillation stabilization time for the main clock has elapsed and MCS is 0. 101 CHAPTER 5 LOW-POWER CONSUMPTION CONTROL CIRCUIT 102 CHAPTER 6 LOW-POWER CONSUMPTION MODE This chapter describes the functions and operations of the low-power consumption mode. 6.1 "Low-Power Consumption Mode" 6.2 "Status Transition in Low-Power Consumption Mode" 6.3 "Status Transition Diagram of Low-Power Consumption Mode" 103 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.1 Low-Power Consumption Mode There are the following operating modes: • PLL clock mode • PLL sleep mode • PLL watch mode • Pseudo watch mode • Main clock mode • Main clock sleep mode • Main clock watch mode • Main clock stop mode • Subclock mode • Subclock sleep mode • Subclock watch mode • Subclock stop mode • Hardware standby mode Operating modes other than the PLL clock mode are categorized as low-power consumption modes. ■ Low-Power Consumption Mode ❍ Main clock mode and main clock sleep mode The microcontroller operates using the main clock (main OSC oscillation clock) and subclock (sub OSC oscillation clock). The clock obtained by dividing the main clock by 2 is used as the operating clock and the subclock (clock obtained by dividing the sub OSC oscillation clock by 4) is used as the watch clock. The PLL clock (VCO oscillation clock) is stopped. ❍ Subclock mode and subclock sleep mode The microcontroller operates using only the subclock. The clock obtained by dividing the subclock by 4 is used as the operating clock. The main and PLL clocks are stopped. ❍ PLL sleep mode and main clock sleep mode Only the CPU operating clock is stopped. Clocks other than the CPU clock are operating. ❍ Pseudo watch mode The pseudo watch mode is the mode for operating the watch or time base timers only. ❍ PLL watch mode, main clock watch mode, and subclock watch mode Only the clock timer is operating. The microcontroller operates using the clock obtained by dividing the subclock by 4. The main and PLL clocks are stopped. In the PLL watch mode, main clock watch mode, and subclock watch mode, only operating modes differ when they are returned from an interrupt (PLL clock mode, main clock mode, and subclock mode). Operation is the same in these watch modes. 104 6.1 Low-Power Consumption Mode ❍ Main clock stop mode, subclock stop mode, and hardware standby mode Oscillation is stopped. Data can be retained with the lowest power consumption. The main clock stop mode and subclock stop mode differ in terms of the operating mode when returned from an interrupt (main clock mode and subclock mode). Operation is the same in these stop modes. ❍ Intermittent CPU operation function The intermittent CPU operation function intermittently operates the clock provided to the CPU when registers, internal memory, internal peripherals, and the external bus are accessed. Processing can be performed with low-power consumption because the CPU execution speed is reduced with the provision of a high-speed clock to the internal peripherals. A PLL clock multiplication factor can be selected among 2, 4, 6, and 8 using the CS1 and CS0 bits. The clock obtained by dividing the selected clock by 2 is used as the machine clock. ■ Operating States in the Low-Power Consumption Mode Table 6.1-1 "Operating States in the Low-Power Consumption Mode" lists the status of chip blocks in operating modes. Table 6.1-1 Operating States in the Low-Power Consumption Mode State Subclock Subclock sleep Transition Sub OSC Main OSC condition oscillation oscillation Operating Stopped Operating Operating Operating Operating Operating Stopped Operating Stopped Operating Operating Operating Operating Operating Stopped Operating Operating Operating Operating Operating Stopped Operating Operating Operating Operating Stopped Stopped Stopped Retained Operating Operating Stopped Stopped Stopped HI-Z Operating Stopped Stopped Stopped Stopped Retained Operating Stopped Stopped Stopped Stopped HI-Z SCS=0 MCS=x Clock CPU Peripherals Pins by SCS=0 MCS=x SLP=1 Main SCS=1 clock MCS=1 sleep SLP=1 SCS=1 PLL sleep MCS=0 SLP=1 Pseudo SCS=1 watch MCS=0 (SPL=0) STP=1 Pseudo SCS=1 watch MCS=0 (SPL=1) STP=1 Watch (SPL=0) Watch (SPL=1) SCS=x MCS=x TMD=0 SCS=x MCS=x TMD=0 Released Reset interrupt Reset interrupt Reset interrupt Reset interrupt Reset interrupt Reset interrupt Reset interrupt Reset interrupt 105 CHAPTER 6 LOW-POWER CONSUMPTION MODE Table 6.1-1 Operating States in the Low-Power Consumption Mode (Continued) State Stop (SPL=0) Stop (SPL=1) Hardware standby Transition Sub OSC Main OSC condition oscillation oscillation Clock CPU Peripherals Pins Stopped Stopped Stopped Stopped Stopped Retained Stopped Stopped Stopped Stopped Stopped HI-Z Stopped Stopped Stopped Stopped Stopped HI-Z by MCS=1 or SCS=0 STP=1 MCS=1 or SCS=0 STP=1 HSTX=L Released Reset interrupt Reset interrupt HSTX=H Note: When tune on the power or hardware standby mode or stop mode is released, the subclock osciliation stabilization time (about 2 seconds) is generated. In the meantime, when switching from the main clock mode to the subclock mode, the osciliation stabilization time is generated. 106 6.1 Low-Power Consumption Mode 6.1.1 Sleep Mode In the sleep mode, only the clock provided to the CPU is stopped. The CPU stops and the peripheral circuits continue operation. ■ Transition to the Sleep Mode Writing "1" in the SLP and TMD bits, and "0" in the STP bit in the low-power consumption mode control register sets the standby control circuit to the sleep mode. When "1" is written in the SLP bit in the LPMCR, an interrupt request may have occurred, in which case the standby control circuit does not enter the sleep mode. The CPU executes the next instruction in the interrupt disable state or immediately causes a branch to the interrupt processing routine in the interrupt enable state. In the sleep mode, the contents of dedicated registers, such as the accumulator and internal RAM, are retained. ■ Releasing the Sleep Mode The standby control circuit releases the sleep mode when a reset is input or an interrupt occurs. After this circuit releases the sleep mode by a reset factor, it enters the reset state. When a peripheral circuit or internal peripheral generates an interrupt request at interrupt level 7 or higher in the sleep mode, the standby control circuit releases the sleep mode. After the sleep mode is released, the interrupt is processed in the same way as normal interrupts. The interrupt enable state may be set by the settings of the I flag, ILM, and interrupt control register (ICR), in which case the CPU executes the not-interrupt-pending instruction following the standby interrupt instruction, then executes interrupt processing. In the interrupt disable state, the CPU continues processing from the instructions that follow the instructions causing the sleep mode. 107 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.1.2 Pseudo Watch Mode In the pseudo watch mode, an operation other than OSC oscillation (main and sub), watch timer, and time base timer is stopped and most chip functions stop. ■ Transition to the Pseudo Watch Mode Under the following conditions, the standby control circuit is set to pseudo watch mode: When the SCS bit is set to "1" and the MCS bit in the clock selection register (CKSCR) to "0" while the TMD and STP bits in the low-power consumption mode control register (LPMCR) are set to "1". Whether to retain the status of each I/O pin before the pseudo watch mode or set it to high impedance in the pseudo watch mode can be specified using the SPL bit in the low-power consumption mode control register. When "1" is written in the STP bit in the LPMCR, an interrupt request may occur, in which case the standby control circuit does not enter the pseudo watch mode. In the pseudo watch mode, the contents of dedicated registers, such as the accumulator and internal RAM, are retained. 108 6.1 Low-Power Consumption Mode ■ Releasing the Pseudo Watch Mode The standby control circuit releases the pseudo watch mode when a reset is input or an interrupt occurs. When this circuit releases the pseudo watch mode by a reset factor, it enters the reset state. At return from the pseudo watch mode, the standby control circuit first releases the pseudo watch mode, then waits for PLL clock oscillation to become stable. For this reason, the reset sequence is also performed using the main clock when the pseudo watch mode is released by a reset factor. When a peripheral circuit generates an interrupt request at interrupt level 7 or higher in the pseudo watch mode, the standby control circuit releases the pseudo watch mode. After the pseudo watch mode is released, the interrupt is processed in the same way as normal interrupts. The interrupt enable state may be set by the settings of the I flag, ILM, or interrupt control register (ICR), in which case the CPU executes the not-interrupt-pending instruction following the standby write instruction, then executes interrupt processing. In the interrupt disable state, the CPU continues processing from the next instruction before the pseudo watch mode. Note: • For the MB90V570, MB90F574, MB90573, and MB90574 • • When releasing the pseudo watch mode by an external interrupt, set the external interrupt request to "H" level. If the external interrupt request is set to "L" level, a malfunction may occur. The pseudo watch mode does not release if an edge of the external interrupt request is set. For the MB90V570A, MB90F574A, and MB90574C • The pseudo watch mode can be released by inputting the external interrupt request set before the standby control circuit enters the pseudo watch mode. The interrupt request of ch2 to ch7 can be selected "H" or "L" level. The interrupt request of ch0 and ch1 can be selected rising edge or falling edge. 109 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.1.3 Watch Mode In the watch mode, an operation other than the sub OSC oscillation and clock timer is stopped. Most chip functions stop. ■ Transition to the Watch Mode Writing "0" in the TMD bit in the low-power consumption mode control register sets the standby control circuit to the watch mode. Whether to retain the status of each I/O pin before the watch mode or set it to high impedance in the pseudo watch mode can be specified using the SPL bit in the low-power consumption mode control register. When "1" is written in the TMD bit in the LPMCR, an interrupt request may occur, in which case the standby control circuit does not enter the watch mode. In the watch mode, the contents of dedicated registers, such as the accumulator and internal RAM, are retained. 110 6.1 Low-Power Consumption Mode ■ Releasing the Watch Mode The standby control circuit releases the watch mode when a reset is input or an interrupt occurs. When this circuit releases the watch mode by a reset factor, it enters the reset state. At return from the subclock watch mode, the standby control circuit releases the watch mode and then immediately enters the subclock mode. For this reason, the reset sequence is also performed using the subclock when the subclock watch mode is released by a reset factor. At return from the main clock or PLL watch mode, the standby control circuit first releases the watch mode, then waits for main clock oscillation to become stable. For this reason, the reset sequence is also performed using the subclock when the watch mode is released by a reset factor. When a peripheral circuit generates an interrupt request at interrupt level 7 or higher in the watch mode, the standby control circuit releases the watch mode. After the watch mode is released, the interrupt is processed in the same way as normal interrupts. The interrupt enable state may be set by the settings of the I flag, ILM, or interrupt control register (ICR), in which case the CPU executes the not-interrupt-pending instruction following the standby write instruction, then executes interrupt processing. In the interrupt disable state, the CPU continues processing from the next instruction before the watch mode. Note: • For the MB90V570, MB90F574, MB90573, and MB90574 • • When releasing the watch mode by an external interrupt, set the external interrupt request to "H" level. If the external interrupt request is set to "L" level, a malfunction may occur. The watch mode does not release if an edge of the external interrupt request is set. For the MB90V570A, MB90F574A, and MB90574C • The watch mode can be released by inputting the external interrupt request set before the standby control circuit enters the watch mode. The interrupt request of ch2 to ch7 can be selected "H" or "L" level. The interrupt request of ch0 and ch1 can be selected rising edge or falling edge. 111 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.1.4 Stop Mode In the stop mode, OSC oscillation (main and sub) is stopped. All chip functions stop. Therefore, data can be retained with the lowest power consumption. ■ Transition to the Stop Mode Under the following conditions, the standby control circuit is set to stop mode: When the SCP bit is set to "0" or the MCS bit in the clock selection register (CKSCR) is set to "1" while the STP bit in the low-power consumption mode control register (LPMCR) is set to "1". Whether to retain the status of each I/O pin before the stop mode or set it to high impedance in the pseudo watch mode can be specified using the SPL bit in the low-power consumption mode control register (LPMCR). When "1" is written in the STP bit in the LPMCR, an interrupt request may occur, in which case the standby control circuit does not enter the stop mode. In the stop mode, the contents of dedicated registers, such as the accumulator and internal RAM, are retained. ■ Releasing the Stop Mode The standby control circuit releases the stop mode when a reset is input or an interrupt occurs. When this circuit releases the stop mode by a reset factor, it enters the reset state. At return from the subclock stop mode, the standby control circuit first waits for subclock oscillation to become stable, then releases the stop mode. For this reason, the reset sequence is also performed after the oscillation stabilization time for the subclock when the stop mode is released by a reset factor. At return from the main clock stop mode, the standby control circuit first waits for main clock oscillation to become stable, then releases the stop mode. For this reason, the reset sequence is also performed after the oscillation stabilization time for the main clock when the stop mode is released by a reset factor. When a peripheral circuit generates an interrupt request at interrupt level 7 or higher in the stop mode, the standby control circuit releases the stop mode. After the subclock stop mode is released, the interrupt is processed in the same way as normal interrupts when the oscillation stabilization time for the subclock has elapsed. The interrupt enable state may be set by the settings of the I flag, ILM, or interrupt control register (ICR), in which case the CPU executes the not-interrupt-pending instruction following the standby write instruction, then executes interrupt processing. In the interrupt disable state, the CPU continues processing from the next instruction before the stop mode. After the main clock stop mode is released, the interrupt is processed in the same way as normal interrupts when the oscillation stabilization time for the main clock has elapsed. The oscillation stabilization time is specified by the WS1 and WS0 bits in the CKSCR. The interrupt enable state may be set by the settings of the I flag, ILM, or interrupt control register (ICR), in which case the CPU executes the not-interrupt-pending instruction following the standby write instruction, then executes interrupt processing. In the interrupt disable state, the CPU continues processing from the next instruction before the stop mode. 112 6.1 Low-Power Consumption Mode Note: • For the MB90V570, MB90F574, MB90573, and MB90574 • • When releasing the stop mode by an external interrupt, set the external interrupt request to "H" level. If the external interrupt request is set to "L" level, a malfunction may occur. The stop mode does not release if an edge of the external interrupt request is set. For the MB90V570A, MB90F574A, and MB90574C • The stop mode can be released by inputting the external interrupt request set before the standby control circuit enters the stop mode. The interrupt request of ch2 to ch7 can be selected "H" or "L" level. The interrupt request of ch0 and ch1 can be selected rising edge or falling edge. 113 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.1.5 Hardware Standby Mode In the hardware standby mode, when the HSTX pin is low, oscillation is stopped and all I/O pins are set to high impedance regardless of other statuses, including resets. ■ Transition to the Hardware Standby Mode In any state, driving the HSTX pin low can set the standby control circuit to the hardware standby mode. In the hardware standby mode, the contents of internal RAM are retained, but dedicated registers such as the accumulator are initialized. ■ Releasing the Hardware Standby Mode The hardware standby mode can be released using the HSTX pin only. When the HSTX pin is driven high, the standby control circuit releases the hardware standby mode, enables the internal reset signal, then enters the oscillation stabilization wait state. When the oscillation stabilization time for the main clock has elapsed, the standby control circuit releases the internal reset. The CPU then starts execution from the reset sequence. 114 6.2 Status Transition in Low-Power Consumption Mode 6.2 Status Transition in Low-Power Consumption Mode In low-power consumption mode, transition to each state occurs according to the settings in the clock selection and low-power consumption mode control registers. ■ Status Transition in Low-Power Consumption Mode Table 6.2-1 "List of Transition Conditions" lists the status transition conditions. The symbols in Table 6.2-1 have the following meanings: • MCS: MCS bit (Clock selection register) (PLL clock mode selected with MSC=0) • SCS: SCS bit (Clock selection register) (Subclock mode selected with SCS=0) • STP: STP bit (Low-power consumption mode control register) (Stop mode selected with STP=0) • SLP: SLP bit (Low-power consumption mode control register) (Sleep mode selected with SLP=0) • TMD: TMD bit (Low-power consumption mode control register) (Clock mode selected with TMD=0) • MCM: MCM bit (Clock selection register) (PLL clock is used with MCM=0) • SCM: SCM bit (Clock selection register) (Subclock is used with SCM=0) • SCD: Subclock oscillation stopped (Subclock oscillation is stopped with SCD=1) • MCD: Main clock oscillation stopped (Main clock oscillation is stopped with MCD=1) • PCD: PLL clock oscillation stopped (PLL clock oscillation is stopped with PCD=1) Table 6.2-1 List of Transition Conditions Status before transition Transition conditions Status after transition Power-on 01 Termination of main clock oscillation stabilization time wait Main mode Main clock oscillation stabilization 05 Termination of main clock oscillation stabilization time wait Main mode Main mode 06 SCS=0 Writing MS transition mode 07 SCS=1 MCS=0 Writing MP transition mode 31 TMD=1 STP=0 Main sleep 32 TMD=0 Writing Main clock transition 33 TMD=1 Main stop SLP=1 Writing STP=1 Writing 115 CHAPTER 6 LOW-POWER CONSUMPTION MODE Table 6.2-1 List of Transition Conditions (Continued) Status before transition PLL mode Subclock mode PM transition mode SM transition mode 116 Transition conditions Status after transition 21 SCS=0 Writing PS transition mode 20 SCS=1 MCS=1 Writing PM transition mode 59 TMD=1 STP=0 PLL sleep 58 TMD=0 Writing PLL clock transition P 57 TMD=1 STP=1 Writing Pseudo watch transition 10 SCS=1 MCS=1 Writing SM transition mode 12 SCS=1 MCS=0 Writing SP transition mode 11 Reset activation 42 TMD=1 43 TMD=0 Writing Subclock 44 TMD=1 Subclock stop 13 PLL--> Termination of main clock switching timing wait Main mode 38 TMD=1 PM transition sleep 39 TMD=0 Writing & PLL--> Termination of main clock switching wait Main clock transition 40 TMD=1 STP=1 Writing & PLL--> Termination of main clock switching wait Main stop 02 Termination of main clock oscillation stabilization time wait Main mode 03 Reset activation or Interrupt Main clock oscillation stabilization 04 SCS=0 Writing Subclock mode 27 TMD=1 28 TMD=0 Writing & Termination of main clock oscillation stabilization time wait Main clock 29 TMD=1 STP=1 Writing & Termination of main clock oscillation stabilization time wait Main stop STP=0 SLP=1 Writing Main clock oscillation stabilization SLP=1 Writing STP=1 Writing STP=0 STP=0 SLP=1 Writing SLP=1 Writing Subclock sleep SM transition sleep 6.2 Status Transition in Low-Power Consumption Mode Table 6.2-1 List of Transition Conditions (Continued) Status before transition MP transition mode Transition conditions Status after transition 16 Termination of PLL oscillation stabilization time wait PLL mode 14 SCS=1 Main mode 15 SCS=0 Writing 68 TMD=1 70 TMD=0 Writing PLL clock transition M 69 TMD=1 STP=1 Writing & Termination of main clock oscillation stabilization time wait Pseudo watch mode 17 Termination of main clock oscillation stabilization time wait MP transition mode 18 MCS=1 Writing SM transition mode 19 Reset activation Main clock oscillation stabilization 75 TMD=1 76 TMD=0 Writing PLL clock 78 TMD=1 STP=1 Writing & Termination of main clock oscillation stabilization time wait Pseudo watch mode 09 Main-->Termination of subclock switching timing wait Subclock mode 08 Reset activation Main mode 51 TMD=1 52 TMD=0 Writing & Termination of Main -->Subclock switching wait Sublcock 53 TMD=1 STP=1 Writing & Termination of Main -->Subclock switching wait Subclock stop 23 PPL-->Termination of main clock switching timing wait MP transition mode 22 SCS=1 Writing PS transition mode 56 TMD=1 Main sleep 26 Interrupt or reset activation Main mode SM transition sleep 24 Termination of main clock oscillation stabilization time wait Main sleep 25 Interrupt or reset activation SM transition mode 34 PLL-->Termination of main clock switching timing wait Main sleep 35 Interrupt or reset activation PM transition mode 63 Interrupt or reset activation PLL mode SP transition mode MS transition mode PS transition mode PM transition sleep PLL sleep MCS=1 Writing STP=0 STP=0 STP=0 STP=0 MS transition mode SLP=1 Writing SLP=1 Writing SLP=1 Writing SLP=1 Writing MP transition sleep SP transition sleep MS transition sleep PS transition sleep 117 CHAPTER 6 LOW-POWER CONSUMPTION MODE Table 6.2-1 List of Transition Conditions (Continued) Status before transition MP transition sleep Transition conditions Status after transition 66 Termination of PLL oscillation stabilization time wait PLL sleep 67 Interrupt or reset activation MP transition mode 73 Termination of main clock oscillation stabilization time wait MP transition sleep 74 Interrupt or reset activation SP transition mode Subclock sleep 46 Interrupt or reset activation Subclock mode MS transition sleep 49 Main-->Termination of subclock switching timing wait Subclock sleep 50 Interrupt or reset activation MS transition mode 54 PLL-->Termination of main clock switching timing wait MS transition sleep 55 Interrupt or reset activation PS transition mode Main clock 30 Interrupt or reset activation SM transition mode Main clock transition 36 Main-->Termination of subclock switching timing wait Main clock 37 Interrupt or reset activation Main mode PLL clock 77 Interrupt or reset activation SP transition mode PLL clock transition M 72 Main-->Termination of subclock switching timing wait PLL clock 71 Interrupt or reset activation MP transition mode PLL clock transition P 65 PLL-->Termination of main clock switching timing wait PLL clock transition M 64 Interrupt or reset activation PLL mode Subclock 47 Interrupt or reset activation Subclock mode Main stop 41 Interrupt or reset activation Stabilization of main clock oscillation Pseudo watch 62 Interrupt or reset activation MP transition mode Pseudo watch transition 61 PLL-->Termination of main clock switching timing wait Pseudo watch mode 60 Interrupt or reset activation PLL mode Subclock stop 48 Interrupt Stabilization of subclock oscillation 79 Reset activation Stabilization of main clock oscillation 45 Termination of subclock oscillation stabilization wait Subclock mode 80 Reset activation Stabilization of main clock oscillation SP transition sleep PS transition sleep Stabilization of subclock oscillation 118 6.3 Status Transition Diagram of Low-Power Consumption Mode 6.3 Status Transition Diagram of Low-Power Consumption Mode Figure 6.3-1 "Low-Power Consumption Mode Status Transition Diagram A" to Figure 6.3-4 "Low-Power Consumption Mode Status Transition Diagram" show a status transition diagram of step-by-step status transitions in accordance with simultaneous events. ■ Status Transition Diagram of Low-Power Consumption Mode For example, assume that MCS and SLP are set simultaneously to 1 in PLL clock mode. In the status transition diagram, a transition to PM transition mode occurs before a transition to PM transition sleep mode. The transition from PLL clock mode to PM transition sleep mode occurs immediately. It is assumed that a reset is activated in subclock sleep mode. In the diagram, a transition to subclock mode occurs before a transition to the main clock oscillation stabilization period. In fact, these transitions occur at the same time. 119 CHAPTER 6 LOW-POWER CONSUMPTION MODE Figure 6.3-1 Low-Power Consumption Mode Status Transition Diagram A Power-on reset SCS=1,MCS=1, STP=0, SLP=0, TMD=1 SCM=1,MCM=1, SCD=0,MCD=0, PCD=1 SM transition mode SCS=1,MCS=1, STP=0, SLP=0, TMD=1 SCM=0,MCM=1, SCD=0,MCD=0, PCD=1 Main clock oscillation stabilization period SCS=1,MCS=1, STP=0, SLP=0, TMD=1 SCM=1,MCM=1, SCD=0,MCD=0, PCD=1 03 04 02 01 05 10 11 Main mode SCS=1,MCS=1, STP=0, SLP=0, TMD=1 SCM=1,MCM=1, SCD=0,MCD=0, PCD=1 06 08 MS transition mode SCS=1,MCS=x, STP=0, SLP=0, TMD=1 SCM=1,MCM=1, SCD=0,MCD=0, PCD=1 Subclock mode SCS=0,MCS=x, STP=0, SLP=0, TMD=1 SCM=0,MCM=1, SCD=0,MCD=1, PCD=1 09 07 12 18 13 PM transition mode SCS=1,MCS=1, STP=0, SLP=0, TMD=1 SCM=1,MCM=0, SCD=0,MCD=0, PCD=1 19 15 14 MP transition mode SCS=1,MCS=0, STP=0, SLP=0, TMD=1 SCM=1,MCM=1, SCD=0,MCD=0, PCD=1 17 SP transition mode SCS=1,MCS=0, STP=0, SLP=0, TMD=1 SCM=0,MCM=1, SCD=0,MCD=0, PCD=1 16 23 20 120 PLL mode SCS=1,MCS=0, STP=0, SLP=0, TMD=1 SCM=1,MCM=0, SCD=0,MCD=0, PCD=0 22 21 PS transition mode SCS=0,MCS=x, STP=0, SLP=0, TMD=1 SCM=1,MCM=0, SCD=0,MCD=0, PCD=0 6.3 Status Transition Diagram of Low-Power Consumption Mode Figure 6.3-2 Low-Power Consumption Mode Status Transition Diagram B Main sleep SCS=1,MCS=1, STP=0, SLP=1, TMD=1 SCM=1,MCM=1, SCD=0,MCD=0, PCD=1 SM transition sleep SCS=1,MCS=1, STP=0, SLP=1, TMD=1 SCM=0,MCM=1, 24 SCD=0,MCD=0, PCD=1 26 25 27 SM transition mode 28 SCS=1,MCS=1, STP=0, SLP=0, TMD=1 SCM=0,MCM=1, SCD=0,MCD=0, PCD=1 31 30 Main mode SCS=1,MCS=1, STP=0, SLP=0, TMD=1 SCM=1,MCM=1, SCD=0,MCD=1, PCD=1 Main clock SCS=1,MCS=1, STP=0, SLP=0, TMD=0 SCM=0,MCM=1, SCD=0,MCD=1, PCD=1 32 29 03 33 37 34 PM transition sleep SCS=1,MCS=1, STP=0, SLP=1, TMD=1 SCM=1,MCM=0, SCD=0,MCD=0, PCD=0 36 05 Main clock oscillation stabilization time SCS=1,MCS=1, STP=0, SLP=0, TMD=1 SCM=1,MCM=1, SCD=0,MCD=0, PCD=1 Main clock transition SCS=1,MCS=1, STP=0, SLP=0, TMD=0 SCM=1,MCM=1, SCD=0,MCD=0, PCD=1 35 38 39 PM transition mode SCS=1,MCS=1, STP=0, SLP=0, TMD=1 40 SCM=1,MCM=0, SCD=0,MCD=0, PCD=0 Main stop SCS=1,MCS=1, STP=1, SLP=0, TMD=1 SCM=1,MCM=1, SCD=1,MCD=1, PCD=1 41 121 CHAPTER 6 LOW-POWER CONSUMPTION MODE Figure 6.3-3 Low-Power Consumption Mode Status Transition Diagram C Subclock mode SCS=0,MCS=x, STP=0, SLP=0, TMD=1 SCM=0,MCM=1, SCD=0,MCD=1, PCD=1 42 44 Subclock oscillation 45 stabilization time SCS=1,MCS=x, STP=0, SLP=0, TMD=1 SCM=0,MCM=1, SCD=0,MCD=1, PCD=1 Main clock oscillation stabilization time SCS=1,MCS=x, STP=0, SLP=0, TMD=1 SCM=1,MCM=1, SCD=0,MCD=0, PCD=1 80 43 46 48 Subclock sleep SCS=1,MCS=x, STP=0, SLP=1, TMD=1 SCM=0,MCM=1, SCD=0,MCD=1, PCD=1 47 49 Subclock stop SCS=0,MCS=x, STP=0, SLP=1, TMD=1 SCM=1,MCM=1, SCD=0,MCD=0, PCD=1 79 PM transition sleep SCS=0,MCS=x, STP=1, SLP=0, TMD=1 SCM=0,MCM=1, SCD=1,MCD=1, PCD=1 Subclock SCS=1,MCS=x, STP=0, SLP=0, TMD=0 SCM=0,MCM=1, SCD=0,MCD=1, PCD=1 52 51 50 MS transition sleep SCS=0,MCS=x, STP=0, SLP=0, TMD=1 SCM=1,MCM=1, SCD=0,MCD=0, PCD=1 53 23 54 PM transition sleep SCS=1,MCS=x, STP=0, SLP=1, TMD=1 SCM=1,MCM=0, SCD=0,MCD=0, PCD=0 55 122 56 PM transition mode SCS=0,MCS=x, STP=0, SLP=0, TMD=1 SCM=1,MCM=0, SCD=0,MCD=0, PCD=0 6.3 Status Transition Diagram of Low-Power Consumption Mode Figure 6.3-4 Low-Power Consumption Mode Status Transition Diagram PLL mode SCS=1, MCS=0, STP=0, SLP=0, TMD=1 SCM=1,MCM=0, SCD=0, MCD=0, PCD=0 60 57 58 Pseudo SCS=1, MCS=0, STP=1, SLP=0, TMD=1 SCM=1,MCM=1, SCD=0, MCD=0, PCD=0 61 Pseudo watch mode SCS=1, MCS=0, STP=1, SLP=0, TMD=1 62 SCM=1,MCM=1, SCD=0, MCD=0, PCD=1 59 63 PLL clock transition P SCS=1, MCS=0, STP=0, SLP=0, TMD=0 SCM=1,MCM=0, SCD=0, MCD=0, PCD=0 PLL sleep SCS=1, MCS=0, STP=0, SLP=1, TMD=1 SCM=1,MCM=0, SCD=0, MCD=0, PCD=1 65 16 66 MS transition sleep SCS=1, MCS=0, STP=0, SLP=1, TMD=1 SCM=1,MCM=1, SCD=0, MCD=0, PCD=0 69 68 67 MP transition mode SCS=1, MCS=0, STP=0, SLP=0, TMD=1 SCM=1,MCM=1, 70 SCD=0, MCD=0, PCD=0 71 PLL clock transition M SCS=1, MCS=0, STP=0, SLP=0, TMD=0 SCM=1,MCM=1, SCD=0, MCD=0, PCD=1 78 73 SP transition sleep SCS=1, MCS=0, STP=0, SLP=1, TMD=1 SCM=0,MCM=1, SCD=0, MCD=0, PCD=1 17 75 74 SP transition mode SCS=1, MCS=0, STP=0, SLP=0, TMD=1 SCM=0,MCM=1, SCD=0, MCD=0, PCD=1 72 77 76 PLL clock SCS=1, MCS=0, STP=0, SLP=0, TMD=0 SCM=0,MCM=1, SCD=0, MCD=1, PCD=1 123 CHAPTER 6 LOW-POWER CONSUMPTION MODE 124 CHAPTER 7 MEMORY ACCESS MODE This chapter describes the functions and operations of the memory access modes. 7.1 "Memory Access Modes" 7.2 "External Memory Access (External Bus Pin Control Circuit)" 7.3 "Operation of the External Memory Access Control Signal" 125 CHAPTER 7 MEMORY ACCESS MODE 7.1 Memory Access Modes F2MC-16LX provides various modes for each access method and access area. ■ Memory Access Modes Table 7.1-1 Memory Access Modes Operating mode Bus mode Single chip RUN Internal ROM external bus External ROM external bus Access mode (external data bus width) — 8 bits 16 bits 8 bits 16 bits ■ Operating Mode The operating mode indicates the mode for controlling device operation status and must be specified by the mode setting pin (MDx). Selecting the operating mode enables the activation of ordinary operation and writing to the flash memory. ■ Bus Mode The bus mode indicates the mode for controlling internal ROM operations and external access function operations and must be specified by the mode setting pin (MDx) and the Mx bit in mode data. The mode setting pin (MDx) specifies the bus mode used when the reset vector or mode data is read. The Mx bit in the mode data specifies the bus mode at normal operation. ■ Access Mode The access mode indicates the mode for controlling the external data bus width and must be specified by the mode setting pin (MDx) and the S0 bit in mode data. Specify eight bits or 16 bits as the external data bus width by selecting an access mode. 126 7.1 Memory Access Modes 7.1.1 Mode Pins A mode can be specified by combining three external pins MD2 to MD0. ■ Mode Pins Table 7.1-2 Relationship among Mode Pins and Modes to Be Set Mode pin setting Mode name Reset vector access area External data bus width Remarks MD2 MD1 MD0 0 0 0 External vector mode 0 External 8 bits — 0 0 1 External vector mode 1 External 16 bits Access to the reset vector 16-bit bus width 0 1 0 (Specification prohibited) 0 1 1 Internal vector mode (Mode data) Controlled with mode data after the reset sequence. 1 0 0 1 0 1 1 1 0 Flash serial writing(*1) — — 1 1 1 Flash memory mode — — Internal (Specification prohibited) — Used when the parallel writer is used. Note: Even if external vector mode 0 is selected, the initial values of IOBS and LMBS of the bus control selection register are set to 1. Therefore, a 16-bit width is set for the 0000C0H to 0000FFH and 002000H to 7FFFFFH areas. To set the 8-bit width for these areas, write 0 in IOBS and LMBS of the bus control selection register. For external vector mode 1, the HMBS bit is set to 0 to enable access to an interface with the 16-bit bus width. Setting the mode pins only is not sufficient for serial writing to flash memory; other pins must be set as well. For details, see CHAPTER 27 "Example of MB90F574/A Serial Programming Connection". *1 Serial writing to the flash memory cannot be performed simply by setting the mode pin (other pins must be set). For details, see an example of flash serial writing connection. 127 CHAPTER 7 MEMORY ACCESS MODE 7.1.2 Mode Data The mode data is allocated in the main storage FFFFDFH and is used to control CPU operations. This data is fetched during reset sequence execution and is stored in the mode register within the device. The reset sequence only can change the contents of the mode register. The setting by this register is validated after the reset sequence. A reserved bit must be set to 0. ■ Mode Data Figure 7.1-1 Mode Data Bit No. Mode data Address:FFFFDFH Reserved Reserved Reserved Reserved Reserved [Bits 7, 6]: M1, M0 Bus mode setting bits Used to specify an operating mode after the reset sequence ends. M1 M0 Function 0 0 Single-chip mode 0 1 Internal ROM external bus mode 1 0 External ROM external bus mode 1 1 (Setting prohibited) [Bit 3]: S0 Access mode setting bit Used to specify the bus mode and access mode after the reset sequence ends. S0 128 Function 0 External data bus 8-bit mode 1 External data bus 16-bit mode 7.1 Memory Access Modes 7.1.3 Memory Space for Each Bus Mode The following figure shows the correspondence between the access areas and physical addresses by specifying bus modes: ■ Memory Space for Each Mode Figure 7.1-2 MB90570 Memory Space for Each Mode ROM area ROM area ROM area ROM area (FF bank image) (FF bank image) Address #1 Address #2 :Internal :External Address #3 :No access RAM RAM Register Mirror function available Part No. RAM Register Peripheral Peripheral Internal ROM external bus Mirror function available External ROM external bus Peripheral Single chip Register Address #1 Address #2 Address #3 B 129 CHAPTER 7 MEMORY ACCESS MODE Note: If "No ROM mirror function" is selected, see CHAPTER 25 "ROM MIRROR FUNCTION SELECTION MODULE" The ROM of the FF bank can be seen as an image in the higher position of the 00 bank. However, the purpose of this method is to make effective use of the small model of the C compiler. The lower 16 bits are made equal, and so the table in the ROM can be referenced without "far" specified in the pointer declaration. For example, if 00C000H is accessed, the contents of the ROM at FFC000H is actually supposed to be accessed. The ROM area of the FF bank here exceeds 48K bytes, and so the entire area cannot be seen in the 00 bank image. Therefore, the ROM data from FF4000H to FFFFFFH is seen as the image from 004000H to 00FFFFH, and so storing the ROM data table in the area from FF4000H to FFFFFFH is recommended. ■ Examples of Recommended Settings Table 7.1-3 Examples of Recommended Settings for Mode Pins and Mode Data Example of setting 130 MD2 MD1 MD0 M1 M0 S0 Single chip 0 1 1 0 0 X Internal ROM external bus and 8bit bus 0 1 1 0 1 0 Internal ROM external bus and 16bit bus 0 1 1 0 1 1 External ROM external bus and 16-bit bus 0 0 1 1 0 1 External ROM external bus and 8bit bus 0 0 0 1 0 0 7.1 Memory Access Modes For an external pin, the signal to be input or output varies depending on the type of mode. Table 7.1-4 Operations of External Pins Relating to Modes Function Pin name External bus extension Single chip 8 bits 16 bits P07~00 AD07~00 P17~10 A15~08 P27~20 A23~16* AD15~08 P30 ALE P31 RDX P32 WRLX* Port P33 P34 Port HRQ* HRHX* P35 HAKX* P36 RDY* P37 CLK* Note: The higher address, WRLX, WRHX, HAKX, HRQ, RDY, and CLK can be used as ports by selecting a function. For details, see Section 7.2 "External Memory Access (External Bus Pin Control Circuit)". 131 CHAPTER 7 MEMORY ACCESS MODE 7.2 External Memory Access (External Bus Pin Control Circuit) The external bus pin control circuit controls the external bus pins used to externally extend the address and data buses of the CPU. ■ External Memory Access (External Bus Pin Control Circuit) To access the external memory and peripherals of the device, F2MC-16LX provides the following addresses, data, and control signals: ❍ CLK (P37): Outputs the machine cycle clock (KBP). ❍ RDY (P36): External ready input pin ❍ WRHX (P33): Signal for writing higher eight bits of the data bus ❍ WRLX (P32): Signal for writing lower eight bits of the data bus ❍ RDX (P31) Read signal ❍ ALE (P30): Address latch enable signal 132 7.2 External Memory Access (External Bus Pin Control Circuit) ■ Configuration of External Memory Access Registers Figure 7.2-1 Configuration of External Memory Access Registers Automatic ready function selection register Bit No. Address:0000A5H Read/write Initial value External address output control register Bit No. Address:0000A6H Read/write Initial value Bus control signal selection register Bit No. Address:0000A7H Read/write Initial value ■ Block Diagram for External Memory Access Figure 7.2-2 Block Diagram for External Memory Access P0 data P0 direction Data control Address control Access control Access control 133 CHAPTER 7 MEMORY ACCESS MODE 7.2.1 Automatic Ready Function Selection Register (ARSR) The automatic ready function selection register (ARSR) sets the automatic wait time of memory access for each area when accessing the external memory. ■ Automatic Ready Function Selection Register (ARSR) Figure 7.2-3 Automatic Ready Function Selection Register (ARSR) Automatic ready function selection register Bit No. Address:0000A5H Read/write Initial value [Bits 15, 14]: IOR1, IOR0 Specify the automatic wait function when an external access is made to the area from 0000C0H to 0000FFH. The following settings are obtained by combining two bits: Table 7.2-1 Setting of IOR1 and IOR0 Bits IOR1 IOR0 Setting 0 0 Automatic wait prohibited [Initial value] 0 1 At external access, an automatic wait of a 1 machine cycle is inserted. 1 0 At external access, an automatic wait of 2 machine cycles is inserted. 1 1 At external access, an automatic wait of 3 machine cycles is inserted. [Bits 13, 12]: HMR1, HMR0 Specify the automatic wait function when an external access is made to the area from 800000H to FFFFFFH. The following settings are obtained by combining two bits: Table 7.2-2 Setting of HMR1 and HMR0 Bits 134 HMR1 HMR0 Setting 0 0 Automatic wait prohibited 0 1 At external access, an automatic wait of a 1 machine cycle is inserted. 1 0 At external access, an automatic wait of 2 machine cycles is inserted. 1 1 At external access, an automatic wait of 3 machine cycles is inserted. [Initial value] 7.2 External Memory Access (External Bus Pin Control Circuit) [Bits 9, 8]: LMR1, LMR0 Specify the automatic wait function when an external access is made to the area from 002000H to 7FFFFFH. The following settings are obtained by combining two bits: Table 7.2-3 Setting of LMR1 and LMR0 Bits LMR1 LMR0 Setting 0 0 Automatic wait prohibited [Initial value] 0 1 At external access, an automatic wait of a 1 machine cycle is inserted. 1 0 At external access, an automatic wait of 2 machine cycles is inserted. 1 1 At external access, an automatic wait of 3 machine cycles is inserted. 135 CHAPTER 7 MEMORY ACCESS MODE 7.2.2 External Address Output Control Register (HACR) The external address output control register (HACR) controls the external output of the addresses A23 to A16. The bits of the register correspond to addresses A23 to A16, respectively, and control the address output pins, as shown in Table 7.2-4 "Control of the External Address Output Control Register (bits A23 to A16)". ■ External Address Output Control Register (HACR) Figure 7.2-4 External Address Output Control Register (HACR) External address output control register Bit No. Address:0000A6H HACR Read/write Initial value This register cannot be accessed when the device is in single-chip mode. In this case, all pins function as the I/O port regardless of the value of this register. All bits of this register are dedicated to writing and are set to 1 for reading. Table 7.2-4 Control of the External Address Output Control Register (bits A23 to A16) A23~16 136 Control 0 The associated pin is the address output (AXX). [Initial value] 1 The associated pin is the I/O port (PXX). 7.2 External Memory Access (External Bus Pin Control Circuit) 7.2.3 Bus Control Signal Selection Register (ECSR) This register sets the bus operation control function in an external bus mode. This register cannot be accessed when the device is in single-chip mode. In this case, all pins function as the I/O port regardless of the value of this register. All bits of this register are dedicated to writing and are set to 1 for reading. ■ Bus Control Signal Selection Register (ECSR) Figure 7.2-5 us Control Signal Selection Register (ECSR) Bus control signal selection register Bit No. Address:0000A7H Read/write Initial value [Bit 15]: CKE Controls the output of the external clock (CLK) as shown below. Table 7.2-5 Control of the CKE Bit CKE Control 0 I/O port (P37) operation (clock output prohibited) [Initial value] 1 Clock signal (CLK) output allowed [Bit 14]: RYE Controls the input of the external ready (RDY) as shown below. Table 7.2-6 Control of the RYE Bit RYE Control 0 I/O port (P36) operation (external RDY input prohibited) [Initial value] 1 External ready (RDY) input allowed [Bit 13]: HDE Specifies that I/O of hold pins is allowed. Setting this bit controls the hold request input (HRQ) and hold acknowledge output (HAKX) as shown below. 137 CHAPTER 7 MEMORY ACCESS MODE Table 7.2-7 Control of the HDE Bit HDE Control 0 I/O port (P35, P34) operation (hold function I/O prohibited [Initial value]) 1 Hold request (HRQ) input allowed or hold acknowledge (HAKX) output allowed [Bit 12]: IOBS Specifies the bus size used when an external access is made to the 0000C0H to 0000FFH area in the external data bus 16-bit mode. Setting this bit enables the following controls: Table 7.2-8 Setting of the the IOBS Bit IOBS Control 0 16-bit bus size access [Initial value] 1 8-bit bus size access [Bit 11]: HMBS Specifies the bus size used when an external access is made to the 800000H to FFFFFFH area in the external data bus 16-bit mode. Setting this bit enables the following controls: Table 7.2-9 Control of the HMBS Bit HMBS Control 0 16-bit bus size access [Initial value for external vector mode 1] 1 8-bit bus size access [Initial value for external vector mode 0] [Bit 10]: WRE Controls the output of the external write signal (WRHX and WRLX pins in the 16-bit bus mode, WRLX pin in the 8-bit bus mode) as shown below. Table 7.2-10 Control of the WRE Bit WRE Control 0 I/O port (P33, P32) operation (write signal output prohibited) [Initial value] 1 Output of the write strobe signal (WRHX and WRLX, or WRLX only) allowed In the external data bus 8-bit mode, P33 functions as the I/O port regardless of the value of this bit. [Bit 9]: LMBS Specifies the bus size used when an external access was made to the 002000H to 7FFFFFH area in the external data bus 16-bit mode. Setting this bit enables the following controls: 138 7.2 External Memory Access (External Bus Pin Control Circuit) Table 7.2-11 Control of the LMBS Bit LMBS Control 0 16-bit bus size access [Initial value] 1 8-bit bus size access Note: To enable the WRHX and WRLX functions using the WRE bit in the 16-bit bus mode, place P33 and P32 in the input mode. (Set bits 3 and 2 of DDR3 to 0.) To enable the WRX function using the WRE bit in the 8-bit bus mode, place P32 in the input mode. (Set bit 2 of DDR3 to 0.) Even if the RDY or HRQ input is allowed using the RYE or HDE bit, the I/O port function of the port is validated. The bit corresponding to the port in DDR3 must be set to 0 (input mode). 139 CHAPTER 7 MEMORY ACCESS MODE 7.3 Operation of the External Memory Access Control Signal The external memory is accessed in three cycles when the ready function is not used. The 8-bit bus width access in the external 16-bit bus mode is used to read or write a peripheral chip 8 bits in width when peripheral chips 8 bits in width and 16 bits in width are connected to the external bus. MB90570 series support various modes for access methods and access areas. See Section 7.1 "Memory Access Modes". ■ External Memory Access Control Signal Because the 8-bit bus width access is executed using the lower eight bits of the data bus, the peripheral chip 8 bits in width must be connected to the lower eight bits of the data bus. Use the HMBS, LMBS, and IOBS bits of the EPCR to specify whether a 16-bit bus width access or an 8-bit bus width access is to be made in the external 16-bit bus mode. A bus operation may not be performed because RDX, WRLX, or WRHX is not asserted. A peripheral chip must not be accessed by the ALE signal only. Figure 7.3-1 External Memory Access Timing Chart (External 8-bit Bus Mode) Write Read Read (Port data) Read address Write address Read address Read address Write address Read address Read address Write address Read data 140 Read address Write data 7.3 Operation of the External Memory Access Control Signal Figure 7.3-2 External Memory Access Timing Chart (External 16-bit Bus Mode) 8-bit bus width byte write Even-address byte write 8-bit bus width byte read Even-address byte read Read address Read address Write address Write address Invalid Read address Read address (Undefined) Write address Read data Read address Write data Odd-address byte read Odd-address byte write Read address Write address Read address Read address Write address Read data Even-address word read Read address Write address Invalid Read address Read address (Undefined) Read address Write data Even-address word write Write address Read address Read address Read address Write address Read address Read address Write address Read address Read data Write data 141 CHAPTER 7 MEMORY ACCESS MODE Note: Design the external circuit so that it is always read with words. Low-speed memory or peripheral circuits can be accessed by setting the P36/RDY pin or the automatic ready function selection register (ARSR). 142 7.3 Operation of the External Memory Access Control Signal 7.3.1 Ready Function Low-speed memory or peripheral circuits can be accessed by setting the P36/RDY pin or the automatic ready function selection register (ARSR). If the RYE bit in the bus control signal selection register (EPCR) is set to 1, a wait cycle occurs while the L level is input in the P36/RDY pin at access to an external area. The access cycle can be extended. ■ Ready Function Figure 7.3-3 Ready Timing Chart Even-address word read Even-address word write Read address Write address Read address Write address Read address Write address RDY pin insertion Even-address word read Write data Read data Even-address word write Read address Write address Write address Read address Write address Read address Write data Cycle extended with auto ready 143 CHAPTER 7 MEMORY ACCESS MODE F2MC-16LX contains two types of auto ready functions for external memory. The auto ready function can automatically insert one to three wait cycles without an external circuit to extend the access cycle in the following cases: generation of an access to a lower-address external area provided at addresses 002000H to 7FFFFFH and generation of a higher-address external area provided at addresses 800000H to FFFFFFH. This function is activated by setting the LMR1 and LMR0 bits in the ARSR (lower-address external area) and the HMR1 and HMR0 bits in the ARSR (higher-address external area). F2MC-16LX contains the auto ready function for external I/O independent of the auto ready function for the memory. The auto ready function for external I/O can automatically insert one to three wait cycles without an external circuit to extend the access cycle when accessing an external area between addresses 0000C0H to 0000FFH. The function is activated by setting the IOR1 and IOR0 bits in the ARSR. Assume that the RYE bit in the EPCR is set to 1 for either the external memory auto ready or the external I/O auto ready. In this case, if the L level is input in the P36/RDY pin after the wait cycle generated by the above auto ready function ends, the wait cycle continues. 144 7.3 Operation of the External Memory Access Control Signal 7.3.2 Hold Function If the HDE bit in the EPCR is set to 1, the external bus hold function by the P34/HRQ and P35/HAKX pins is validated. ■ Hold Function If the H level is input in the P34/HRQ pin, the hold status is entered when the CPU instruction ends (for the string instruction when 1-element data processing ends). The following pins attain high-impedance status by outputting the L level from the P35/HAKX pin. • Address output: P23/A19~P20/A16 • Address and data I/O: P17/D15~P00/D00 • Bus control signal: P30/ALE , P31/RDX ,P32/WRLX, P33/WRHX This enables external buses to be used from the external circuit of the device. If the L level is input in the P34/HRQ pin, the P35/HAKX pin attains H-level output and the external pin status is rendered active so as to restart CPU operation. No hold request input is accepted in the STOP status. Figure 7.3-4 "Hold Timing (in the External 16-bit Mode)" shows the hold timing in external bus 16-bit mode. Figure 7.3-4 Hold Timing (in the External 16-bit Mode) Read cycle Hold cycle (Address) Write cycle (Address) (Address) (Address) Read data Write data 145 CHAPTER 7 MEMORY ACCESS MODE 146 CHAPTER 8 I/O PORT This chapter describes the functions and operations of the I/O port. 8.1 "Overview of the I/O Port" 8.2 "Registers of the I/O Port" 147 CHAPTER 8 I/O PORT 8.1 Overview of the I/O Port Input or output can be specified by setting the port direction register (PDR) individually for the pins in each port if the corresponding peripheral circuit is not using the pin. ■ Overview of the I/O Port Input or output can be specified by setting the port direction register (PDR) individually for the pins in each port if the corresponding peripheral circuit is not using the pin. If a port data register (PDR) is read for data input, the value corresponding to the level of the pin is read. If a port data register (PDR) is read for data output, the latch value of the PDR register is read. This applies also for reading in a read modify write operation. When the pin is used for control output, the signal output as control output is read if a PDR register is read, regardless of the value of the PDR register. Note the following when a pin specified as input pin is changed to become an output pin: If a read modify write instruction (e.g., bit set) is used for presetting output data in a PDR register, input data from the pin, not the latch value of the data, is read out. Figure 8.1-1 "Block Diagram of I/O Port" shows the block diagram of an I/O port. Figure 8.1-1 Block Diagram of I/O Port Internal data bus Data register read Data register Data register write Direction register Direction register write Direction register read 148 Pin 8.1 Overview of the I/O Port ■ Operation of a Port Used as a Resource When Port Output is Set by a PDR Register Figure 8.1-2 State of Pin of Port Used as a Resource When Resource Operation is Enabled/Disabled Resource operation enabled/disabled setting State of a pins which serve as the resource and port Resource operation enabled Dependent on the resource operation Resource operation disabled PDR register setting value is output. 149 CHAPTER 8 I/O PORT 8.2 Registers of the I/O Port Figure 8.2-1 "Configuration of I/O Port Registers" shows the bit configurations of the I/O port registers. ■ Configuration of I/O Port Registers Figure 8.2-1 Configuration of I/O Port Registers Bit No. 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 Address : 000000H P07 P06 P05 P04 P03 P02 P01 P00 Port 0 data register (PDR0) Address : 000001H P17 P16 P15 P14 P13 P12 P11 P10 Port 1 data register (PDR1) Address : 000002H P27 P26 P25 P24 P23 P22 P21 P20 Port 2 data register (PDR2) Address : 000003H P37 P36 P35 P34 P33 P32 P31 P30 Port 3 data register (PDR3) Address : 000004H P47 P46 P45 P44 P43 P42 P41 P40 Port 4 data register (PDR4) Address : 000005H P57 P56 P55 P54 P53 P52 P51 P50 Port 5 data register (PDR5) Address : 000006H P67 P66 P65 P64 P63 P62 P61 P60 Port 6 data register (PDR6) P74 P73 P72 P71 P70 Port 7 data register (PDR7) Address : 000007H Address : 000008H P87 P86 P85 P84 P83 P82 P81 P80 Port 8 data register (PDR8) Address : 000009H P97 P96 P95 P94 P93 P92 P91 P90 Port 9 data register (PDR9) Address : 00000AH PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port A data register (PDRA) Address : 00000BH PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Port B data register (PDRTB) PC3 PC2 PC1 PC0 Port C data register (PDRTC) 8/0 Address : 00000CH Bit No. 15/7 14/6 13/5 12/4 11/3 10/2 9/1 Address : 000010H D07 D06 D05 D04 D03 D02 D01 D00 Port 0 direction register (DDR0) Address : 000011H D17 D16 D15 D14 D13 D12 D11 D10 Port 1 direction register (DDR1) Address : 000012H D27 D26 D25 D24 D23 D22 D21 D20 Port 2 direction register (DDR2) Address : 000013H D37 D36 D35 D34 D33 D32 D31 D30 Port 3 direction register (DDR3) Address : 000014H D47 D46 D45 D44 D43 D42 D41 D40 Port 4 direction register (DDR4) Address : 000015H D57 D56 D55 D54 D53 D52 D51 D50 Port 5 direction register (DDR5) Address : 000016H D67 D66 D65 D64 D63 D62 D61 D60 Port 6 direction register (DDR6) D74 D73 D72 D71 D70 Port 7 direction register (DDR7) Address : 000017H Address : 000018H D87 D86 D85 D84 D83 D82 D81 D80 Port 8 direction register (DDR8) Address : 000019H D97 D96 D95 D94 D93 D92 D91 D90 Port 9 direction register (DDR9) Address : 00001AH DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Port A direction register (DDRA) Address : 00001BH DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Port B direction register (DDRB) DC3 DC2 DC1 DC0 Port C direction register (DDRC) Address : 00001CH 150 8.2 Registers of the I/O Port Bit No. 15 14 13 12 11 10 9 8 Address : 00001DH OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 Port 4 output pin register (ODR4) Bit No. 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 Address : 00008CH RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 Port 0 resistor register (RDR0) Address : 00008DH RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 Port 1 resistor register (RDR1) Address : 00008EH RD67 RD66 RD65 RD64 RD63 RD62 RD61 RD60 Port 6 resistor register (RDR6) Bit No. Address : 00001EH 15 14 13 12 11 10 9 8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Port 8 analog input enable register (ADER) 151 CHAPTER 8 I/O PORT 8.2.1 Port Data Register (PDR) The following figure shows the bit configuration of the port data register (PDR). ■ Port Data Register (PDR) Figure 8.2-2 Port Data Register (PDR) Bit No. PDR0 Address : 000000H Bit No. PDR1 Address : 000001H Bit No. PDR2 Address : 000002H Bit No. PDR3 Address : 000003H Bit No. PDR4 Address : 000004H Bit No. PDR5 Address : 000005H Bit No. PDR6 Address : 000006H PDR7 Address : 000007H 152 7 6 5 4 3 2 1 0 P07 P06 P05 P04 P03 P02 P01 P00 15 14 13 12 11 10 9 8 P17 P16 P15 P14 P13 P12 P11 P10 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 15 14 13 12 11 10 9 8 P37 P36 P35 P34 P33 P32 P31 P30 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 15 14 13 12 11 10 9 8 P57 P56 P55 P54 P53 P52 P51 P50 7 6 5 4 3 2 1 0 P67 P66 P65 P64 P63 P62 P61 P60 15 14 13 12 11 10 9 8 P74 P73 P72 P71 P70 Initial value Access Undefined R/W * Undefined R/W * Undefined R/W * Undefined R/W * Undefined R/W * Undefined R/W * Undefined R/W * Undefined R/W * 8.2 Registers of the I/O Port Bit No. PDR8 Address : 000008H Bit No. PDR9 Address : 000009H Bit No. PDRA Address : 00000AH Bit No. PDRB Address : 00000BH Bit No. PDRC Address : 00000CH 7 6 5 4 3 2 1 0 Initial value Access P87 P86 P85 P84 P83 P82 P81 P80 Undefined R/W * 15 14 13 12 11 10 9 8 P97 P96 P95 P94 P93 P92 P91 P90 Undefined R/W * 7 6 5 4 3 2 1 0 Undefined R/W * PA7 7 PB7 7 PA6 6 PB6 6 PA5 5 PA3 4 PB5 5 PA4 PB4 3 PB3 4 3 PC3 PA2 2 PB2 2 PC2 PA1 1 PB1 1 PC1 PA0 0 PB0 0 PC0 Note: Note that I/O port read/write operations are different than those of memory as follows: [Input mode] Read: The level of a corresponding pin is read out. Write: Data is written in an output latch. [Output mode] Read: The value of a data register latch is read out. Write: Data is output to a corresponding pin Note: • In port input mode, the pin level is read when reading data if an RMW instruction is executed for a port data register (PDR). Note therefore that values of bits used as signal input ports other than the values involved in the bit operation may change. • If an RMW instruction is executed for the data register (PDR) of a port also used as a resource during a resource operation, the pin level is read for the pin operated as a resource when reading. Note therefore that the values of bits used as signal input ports other than the values involved in the bit operation may change. Table 8.2-1 Data to be Read When an RMW Instruction is Executed for a PDR Register When resource operation is enabled When resource operation is disabled When port input is set DDR = 00h Pin level Pin level When port output is set DDR = FFh Pin level PDR register value 153 CHAPTER 8 I/O PORT Figure 8.2-3 State of Port Used also as Resource When an RMW Instruction is Executed Resource operation enabled/disabled setting State of a pins which serve as the resource and port Resource operation enabled Resource operation disabled Dependent on the resource operation For input pin setting (DDR=00h) : Hi-z For output pin setting (DDR=FFh) : The changed PDR value is output. RMW instruction executed RMW instruction execution timing for a PDR register PDR register value Previous data Changed with the pin level when an RMW instruction is executed For details on RMW instructions, see Appendix B.8 "List of F2MC-16LX Instructions". 154 8.2 Registers of the I/O Port 8.2.2 Port Direction Register (DDR) Figure 8.2-4 "Port Direction Register (DDR)" shows the bit configuration of the port direction register (DDR). ■ Port Direction Register (DDR) Figure 8.2-4 Port Direction Register (DDR) Bit No. DDR0 Address : 000010H Bit No. DDR1 Address : 000011H Bit No. DDR2 Address : 000012H Bit No. DDR3 Address : 000013H Bit No. DDR4 Address : 000014H Bit No. DDR5 Address : 000015H Bit No. DDR6 Address : 000016H Bit No. DDR7 Address : 000017H 7 6 5 4 3 2 D07 D06 D05 D04 D03 D02 15 14 13 12 11 10 D17 D16 D15 D14 D13 D12 7 6 5 4 3 2 D27 D26 D25 D24 D23 D22 15 14 13 12 11 10 D37 D36 D35 D34 D33 D32 7 6 5 4 3 2 D47 D46 D45 D44 D43 D42 15 14 13 12 11 10 D57 D56 D55 D54 D53 D52 7 6 5 4 3 2 D67 D66 D65 D64 D63 D62 15 14 13 12 11 10 D74 D73 D72 1 D01 9 D11 1 D21 9 D31 1 D41 9 D51 1 D61 9 D71 0 D00 Initial value Access 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W 00000000B R/W -----000B R/W 8 D10 0 D20 8 D30 0 D40 8 D50 0 D60 8 D70 155 CHAPTER 8 I/O PORT Bit No. DDR8 Address : 000018H Bit No. DDR9 Address : 000019H Bit No. DDRA Address : 00001AH Bit No. DDRB Address : 00001BH Bit No. DDRC Address : 00001CH 7 6 5 4 3 2 1 0 D87 D86 D85 D84 D83 D82 D81 D80 15 14 13 12 11 10 D97 D96 D95 D94 D93 D92 7 6 5 4 3 2 9 D91 1 D90 DA5 DA4 DA3 DA2 DA1 DA0 15 14 13 12 11 10 9 8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 5 4 3 DC3 2 DC2 1 DC1 00000000B R/W --000000B R/W 00000000B R/W ----0000B R/W 0 DC0 While a pin operates as a port, the corresponding pin is controlled as follows: 0: Input mode 1: Output mode Set to 0 by a reset 156 R/W 0 DA6 6 00000000B 8 DA7 7 Initial value Access 8.2 Registers of the I/O Port 8.2.3 Output Pin Register (ODR) Figure 8.2-5 "Bit Configuration of the Output Pin Register (ODR)" shows the bit configuration of the output pin register (ODR). Figure 8.2-6 "Block Diagram of the Output Pin Register (ODR)" is a block diagram. ■ Output Pin Register (ODR) Figure 8.2-5 Bit Configuration of the Output Pin Register (ODR) Port 4 output pin register (ODR4) Bit No. Address : 00001DH 7 6 5 4 3 2 1 0 OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 Initial value 00000000B ■ Block Diagram of the Output Pin Register (ODR) Internal data bus Figure 8.2-6 Block Diagram of the Output Pin Register (ODR) Data register Port I/O Direction register Pin register ■ Notes on the Output Pin Register (ODR) The output pin register (ODR: Readable and writable) effects open drain control in output mode. • 0: Standard output port in output mode • 1: Open drain output port in output mode • Meaningless in input mode (output Hi-z) • The input/output mode is determined by the direction register (DDR). • No pull-up resistor is provided while hardware is standby or stopped (SPL = 1)(high impedance). • This function is inhibited for use in an external bus. Do not write this register. 157 CHAPTER 8 I/O PORT 8.2.4 Input Resistor Register (RDR) Figure 8.2-7 "Bit Configuration of Input Resistor Register (RDR)" shows the bit configuration of the input resistor register (RDR). Figure 8.2-8 "Block Diagram of the Input Resistor Register (RDR)" is a block diagram. ■ Input Resistor Register (RDR) Figure 8.2-7 Bit Configuration of Input Resistor Register (RDR) Bit No. Address : 00008CH Bit No. Address : 00008DH Bit No. Address : 00008EH 7 6 5 4 3 2 1 0 RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 15 14 13 12 11 10 9 6 5 4 3 2 1 Initial value : 00000000B 8 RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 7 Port 0 resistor register (RDR0) Port 1 resistor register (RDR1) Initial value : 00000000B 0 RD67 RD66 RD65 RD64 RD63 RD62 RD61 RD60 Port 6 resistor register (RDR6) Initial value : 00000000B ■ Block Diagram of the Input Resistor Register Figure 8.2-8 Block Diagram of the Input Resistor Register (RDR) Internal data bus Pull-up resistor (approx. 50 k Data register ) Port Input/output Direction register Resistor register ■ Notes on the Input Resistance Register (PDR) The input resistance register (PDR: Readable and writable) effects pull-up resistor control in input mode. 158 • 0: Without pull-up resistor in input mode • 1: With pull-up resistor in input mode 8.2 Registers of the I/O Port • Meaningless in output mode (without pull-up resistor). • The input/output mode is determined by the direction register (DDR). • No pull-up resistor is provided while hardware is standby or stopped (LPMCR: SPL = 1)(high impedance). • This function is inhibited for use in an external bus. Do not write this register. 159 CHAPTER 8 I/O PORT 8.2.5 Analog Input Enable Register (ADER) Figure 8.2-9 "Bit Configuration of the Analog Input Enable Register (ADER)" shows the bit configuration of the analog input enable register (ADER). ■ Analog Input Enable Register (ADER) Figure 8.2-9 Bit Configuration of the Analog Input Enable Register (ADER) 15 Bit No. Address : 00001EH 14 12 11 10 9 8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 R/W R/W Controls port 8 as follows: • 0: Port input mode • 1: Analog input mode Set to 1 by a reset. 160 13 R/W R/W R/W R/W R/W R/W Initial value 11111111B CHAPTER 9 TIMEBASE TIMER This chapter describes the functions and operations of the Timebase Timer. 9.1 "Overview of the Timebase Timer" 9.2 "Timebase Timer Control Register (TBTC)" 9.3 "Operation of the Timebase Timer" 161 CHAPTER 9 TIMEBASE TIMER 9.1 Overview of the Timebase Timer The timebase timer consists of an 18-bit timer and a circuit for controlling the interval interrupt. The timebase timer uses the oscillation clock regardless of the setting of the MCS or SCS bit in the clock selection register (CKSCR). ■ Configuration of the Timebase Timer Register Figure 9.1-1 Configuration of Timebase Timer Register Timebase timer control register 15 Address: 0000A9H Read/Write Initial value 162 14 13 12 11 10 9 8 Reserved TBIE TBOF TBR TBC1 TBC0 (-) (1) (R/W) (R/W) (W) (R/W) (R/W) (1) (0) (0) (0) (0) (-) (-) (-) (-) Bit No. TBTC 9.1 Overview of the Timebase Timer ■ Block Diagram of the Timebase Timer Figure 9.1-2 Timebase Timer Block Diagram Oscillation clock TBTC TBC1 Selector TBC0 Clock input 2 12 2 14 Timebase timer 2 16 2 19 14 19 12 TBTRES 2 2 2 16 2 TBR TBIE AND S R Q TBOF Internal data bus Timebase interrupt WDTC WT1 Selector WT0 2-bit counter OF CLR Watchdog reset generation circuit CLR WTE WDGRST To the internal reset generation circuit WTC WDCS AND SCE Q SCM Power-on reset* subclock stopped S R WTC1 Selector WTC0 WTR WTIE WTOF AND Q S R 210 2 13 2 14 2 15 WTRES 210 2 13 214 215 Watch timer Clock input Subclock Watch interrupt WDTC PONR STBR From the Power-on generator From the hardware standby control circuit WRST ERST RSTX pin SRST From the RST bit of STBYC register 163 CHAPTER 9 TIMEBASE TIMER 9.2 Timebase Timer Control Register (TBTC) The timebase timer control register (TBTC) controls the operation of the timebase timer and the interval interrupt time. ■ Timebase Timer Control Register (TBTC) Figure 9.2-1 Timebase Timer Control Register (TBTC) Configuration Timebase timer control register Address H Bit No. Reserved Read/write Initial value Note: As accessing with a read modify instruction may result in the execution of an incorrect operation, this instruction must not be used. [Bit 15] Testing bit This bit is used for testing. Always write 1 to this bit. [Bits 14 and 13] Unused bit Unused [Bit 12] TBIE This bit is used to enable interval interrupts from the timebase timer. Writing 1 to this bit enables interrupts; writing 0 disables interrupts. This bit is initialized to 0 upon a reset and is a read/write bit. [Bit 11] TBOF This bit is a flag indicating an interrupt request from the timebase timer. When the TBIE bit is 1, an interrupt request is made if the TBOF bit is set to 1. This bit is set to 1 whenever the interval set with the TBC1 and TBC0 bits elapses. The bit is cleared by writing 0 to the bit or upon a transition to stop or hardware standby mode or a reset. Writing 1 to this bit does not affect operation. When a read modify write instruction is used, 1 is read from this bit. [Bit 10] TBR This bit is used to clear all bits of the timebase counter to 0. Writing 0 to this bit clears the timebase counter. Writing 1 to this bit does not affect operation. The number 1 is always read from this bit. [Bits 9 and 8] TBC1, TBC0 These bits are used to set the timebase timer interval. The bits are initialized to 00 upon a reset. The bits are read/write bits. 164 9.2 Timebase Timer Control Register (TBTC) Table 9.2-1 "Timebase Timer Interval Selection" lists interval settings. Table 9.2-1 Timebase Timer Interval Selection TBC1 TBC0 Interval time for oscillation at 4 MHz 0 0 1.024 ms 0 1 4.096 ms 1 0 16.384 ms 1 1 131.072 ms 165 CHAPTER 9 TIMEBASE TIMER 9.3 Operation of the Timebase Timer The timebase timer functions as a clock source for the watchdog timer, a timer for the oscillation stabilization time of the main and PLL clocks, and an interval timer for generating interrupts periodically. ■ Timebase Counter The timebase timer includes an 18-bit counter that counts entered oscillator clocks from which machine clocks are created. The count operation continues while oscillator clocks are being input. The timebase timer is cleared following a power-on reset, a transition to stop or hardware standby mode, a switch from the main clock to PLL clock with the MCS bit of the CKSCR register, a switch from the main clock to subclock with the SCS bit of the CKSCR register, and writing 0 to the TBR bit of the TBTC register. Clearing the timebase timer affects the watchdog counter and interval interrupts using outputs from the timebase timer. ■ Interval Interrupt Function of the Timebase Timer Interrupts are generated periodically by the carry signal from the timebase counter. The TBOF flag is set whenever the interval time set with the TBC1 and TBC0 bits of the TBTC register elapses. The flag is set based on the time the timebase timer was last cleared. When a transition from main clock mode to PLL clock mode occurs, the timebase timer is cleared because it is used as the timer for the oscillation stabilization of the PLL clock. When a transition from main clock mode to subclock mode occurs, the timebase timer is cleared because it is used as the timer for the oscillation stabilization of the subclock. Upon a transition to stop or hardware standby mode, the TBOF flag is cleared because the timebase timer is used as the timer for the oscillation stabilization time for a return. 166 CHAPTER 10 WATCHDOG TIMER This chapter describes the functions and operations of the Watchdog Timer. 10.1 "Overview of the Watchdog Timer" 10.2 "Watchdog Timer Control Register (WDTC)" 10.3 "Operation of the Watchdog Timer" 167 CHAPTER 10 WATCHDOG TIMER 10.1 Overview of the Watchdog Timer The watchdog timer consists of a 2-bit watchdog counter that uses the carry signal of an 18-bit time base timer or 15-bit watch timer as a clock source, a control register, and a watchdog reset control section. ■ Configuration of the Watchdog Timer Control Register Figure 10.1-1 Configuration of Watchdog Timer Control Register Watchdog timer control register 7 Address: 0000A8H Read/Write Initial value 168 6 5 4 3 2 PONR STBR WRST ERST SRST WTE (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (W) (X) 1 0 WT1 WT0 (W) (X) (W) (X) Bit No. WDTC 10.1 Overview of the Watchdog Timer ■ Block Diagram of the Watchdog Timer Figure 10.1-2 Watchdog Timer Block Diagram Main clock TBTC TBC1 Selector TBC0 2 12 2 14 2 16 2 19 TBTRES Clock input Time base timer 2 12 2 14 2 16 2 19 TBR TBIE AND S R Q TBOF Internal data bus Time base interrupt WDTC WT1 Selector WT0 2-bit counter OF CLR Watchdog reset generation circuit CLR WTE WDGRST To the internal reset generation circuit WTC WDCS AND SCE Q SCM Power-on reset* subclock stopped S R WTC1 Selector WTC0 WTR WTIE WTOF AND Q S R 210 2 13 2 14 2 15 WTRES 210 2 13 214 215 Watch timer Clock input Divide-by-four frequency of the subclock Watch interrupt WDTC PONR STBR From the Power-on generator From the hardware standby control circuit WRST ERST RSTX pin SRST From the RST bit of the STBYC register 169 CHAPTER 10 WATCHDOG TIMER 10.2 Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) contains bits to control the watchdog timer and bits to identify reset factors. ■ Watchdog Timer Control Register (WDTC) Figure 10.2-1 Watchdog Timer Control Register (WDTC) Watchdog timer control register Address Bit No. H Read/write Initial value [Bits 7 to 3] PONR, STBR, WRST, ERST, SRST The bits are flags indicating reset factor. When a reset factor occurs, these bits are set as shown in Table 10.2-1 "Correspondence between Bit Values and Reset Factors". These bits are read-only and set to 0 after a WDTC register read operation. Because the values of reset factor bits other than the PONR bit are not assured at Power-on, ensure during software design that the values of bits other than the PONR bit are ignored when this bit is 1. Table 10.2-1 Correspondence between Bit Values and Reset Factors Reset factor PONR STBR WRST ERST SRST Power-on 1 — — — — Hardware standby * 1 * * * Watchdog timer * * 1 * * External pin * * * 1 * RST bit * * * * 1 * The previous value is retained. [Bit 2] WTE While the watchdog timer is being stopped, setting this bit to 0 enables the operation of the watchdog timer. Setting this bit again to 0 clears the watchdog timer counter. Setting it to 1 does not affect the operation. The watchdog timer is stopped upon the reset by the reset factor bits of power-on, hardware standby, or watchdog timer. The number 1 is always read from this bit. [Bits 1 and 0] WT1, WT0 These bits are write-only bits used to select an interval time for the watchdog timer. Only data written when the watchdog timer is started is valid; data written under other conditions is ignored. A clock to be input to the watchdog timer is selected according to the result of 170 10.2 Watchdog Timer Control Register (WDTC) ANDing the WDCS bit of WTC and the SCM bit of LPMCR. When the WDCS is set to 1, the interval time of the time base timer is selected if the main clock and PLL clock are selected as machine clocks. When WDCS is set to 0 or when the subclock is selected, the interval time of the watch timer is selected. Table 10.2-2 "Watchdog Timer Interval Selection Bits" lists interval time settings. Table 10.2-2 Watchdog Timer Interval Selection Bits (WT1 and WT0) WDCS SCM WT1 WT0 Interval time (Oscillation: main clock at 4 MHz, subclock at 32 KHz) Min. Max. 1 0 0 Approx. 3.58 ms Approx. 4.61 ms 1 0 1 Approx. 14.33 ms Approx. 18.43 ms 1 1 0 Approx. 57.23 ms Approx. 73.73 ms 1 1 1 Approx. 458.75 ms Approx. 589.82 ms 0 0 0 0.438 s 0.563 s 0 0 1 3.500 s 4.500 s 0 1 0 7.000 s 9.000 s 0 1 1 14.00 s 18.00 s Note: The above maximum interval values apply when the time base counter or watch counter is not reset during a watchdog operation. 171 CHAPTER 10 WATCHDOG TIMER 10.3 Operation of the Watchdog Timer The watchdog timer can be used to detect program crashes. If 0 is not written to the WTE bit of the watchdog timer within a predetermined time due to a program crash or otherwise, the watchdog timer issues a watchdog reset request. ■ Starting the Watchdog Timer When the watchdog timer has been stopped, 0 can be written to the WTE bit of the WDTC register to start the watchdog timer. At this time, the WT1 and WT0 bits are used to set the interval for watchdog timer reset occurrence. Only data written when the watchdog timer is started is valid as an interval setting. ■ Preventing Watchdog Timer Reset Once the watchdog timer has started, the 2-bit watchdog counter must be cleared regularly with the program. Specifically, 0 must be written to the WTE bit of the WDTC register regularly. The watchdog counter is configured as a 2-bit counter that uses the carry signal from the time base counter as the clock source. Therefore, when the time base timer is cleared, the interval for watchdog reset occurrence may be longer than the set interval. Figure 10.3-1 "Operation of the Watchdog Timer" shows the operation of the watchdog timer. Figure 10.3-1 Operation of the Watchdog Timer Time base Watchdog 00 01 10 00 01 10 11 00 WTE write Watchdog start Watchdog clear Occurrence of watchdog reset ■ Stopping the Watchdog Once started, the watchdog timer is stopped and initialized only upon the reset by the reset factor bits of power-on, hardware standby, or watchdog timer. A reset due to an external pin or software clears the watchdog counter but does not stop the watchdog function. ■ Clearing the Watchdog Counter The watchdog counter is cleared by a reset, a transition to sleep or stop mode, a hold acknowledge signal, or a writing to the WTE bit. (The counter is not cleared by a transition to watch mode.) 172 CHAPTER 11 WATCH TIMER This chapter describes the functions and operations of the Watch Timer. 11.1 "Overview of the Watch Timer" 11.2 "Watch Timer Control Register (WTC)" 11.3 "Operation of the Watch Timer" 173 CHAPTER 11 WATCH TIMER 11.1 Overview of the Watch Timer The watch timer consists of a 15-bit timer and an interval interrupt control circuit. The watch timer uses a subclock regardless of the value of the MCS or SCS bit in the clock selection register (CKSCR). ■ Configuration of the Watch Timer Control Register Figure 11.1-1 Watch Timer Control Register (WTC) Watch timer control register Address: 0000AAH Read/Write Initial value 174 7 6 5 4 3 2 1 0 WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 (R/W) (1) (R) (X) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) Bit No. WTC 11.1 Overview of the Watch Timer ■ Block Diagram of the Watch Timer Figure 11.1-2 Time Base Timer Block Diagram Oscillation clock TBTC TBC1 Selector TBC0 2 12 2 14 2 16 2 19 TBTRES Clock input Time base timer 2 12 2 14 2 16 2 19 TBR TBIE AND Q TBOF S R Time base interrupt Internal data bus WDTC WT1 Selector WT0 2-bit counter OF CLR Watchdog reset generation circuit CLR WDGRST To the internal reset generation circuit WTE WTC WDCS AND SCE Q SCM Power-on reset* subclock stopped S R WTC1 Selector WTC0 WTR WTIE WTOF AND Q S R 210 2 13 2 14 2 15 WTRES 210 2 13 214 215 Watch timer Clock input Subclock Watch interrupt WDTC PONR From the Power-on generation STBR From the hardware standby control circuit WRST ERST RSTX pin SRST From the RST bit of STBYC register 175 CHAPTER 11 WATCH TIMER 11.2 Watch Timer Control Register (WTC) The watch timer control register (WTC) controls the operation of the watch timer and the interval interrupt time. ■ Watch Timer Control Register (WTC) Figure 11.2-1 Watch Timer Control Register (WTC) Watch timer control register Address Bit No. H Read/write Initial value [Bit 7] WDCS When the main clock and PLL clock are selected, this bit is used to select the clock from the watch timer or time base timer as a clock to be input to the watchdog timer. When this bit is 0, the clock from the watch timer is selected; when this bit is 1, the clock from the time base timer is selected. That is, by setting WDCS to 1, the time base timer output can be selected if the main clock and PLL clock are selected, or the watch timer output can be selected if the subclock is selected. This bit is initialized to 1 following a power-on reset. Note: When WDCS is set to 1, the count by the watchdog timer may be incremented because the time base timer output is asynchronous to the watch timer output. Therefore, when WDCS is set to 1, the watchdog timer must be cleared before and after the clock mode is changed. [Bit 6] SCE This bit indicates that the oscillation stabilization period of the subclock has ended. When this bit is 0, the oscillation stabilization period continues. The oscillation stabilization period is fixed to 216 cycles (subclock). This bit is initialized to 0 following a power-on reset, stop, or watchdog reset. [Bit 5] WTIE This bit is used to enable interval interrupts from the watch timer. Writing 1 to this bit enables interrupts; writing 0 disables interrupts. This bit is initialized to 0 upon a reset and is a read/write bit. [Bit 4] WTOF This bit is a flag indicating an interrupt request from the watch timer. When the WTIE bit is 1, an interrupt request is made if the WTOF bit is set to 1. This bit is set to 1 whenever the interval set with the WTC1 and WTC0 bits elapses. The bit is cleared by writing 0 to the bit or upon a transition to stop or hardware standby mode or a reset. Writing 1 to this bit does 176 11.2 Watch Timer Control Register (WTC) not affect operation. When a read, modify, or write instruction is used, 1 is read from this bit. [Bit 3] WTR This bit is used to clear all bits of the watch timer counter to 0. Writing 0 to this bit clears the watch counter. Writing 1 to this bit does not affect operation. The number 1 is always read from this bit. [Bits 2, 1, and 0] WTC 2, WTC1, WTC0 These bits are used to set the watch timer interval. Table 11.2-1 "Watch Timer Interval Selection" lists interval settings. The bits are initialized to 000 following a reset and are read/ write bits. When values are written to these bits, clear bit 4 (WTOF). Table 11.2-1 Watch Timer Interval Selection WTC2 WTC1 WTC0 Interval time * 0 0 0 62.5 ms 0 0 1 125 ms 0 1 0 250 ms 0 1 1 500 ms 1 0 0 1.0 s 1 0 1 2.0 s 1 1 0 4.0 s 1 1 — 1 *: The interval time is the value when the subclock is set to 32KHz (for an operation clock frequency of 8KHz). 177 CHAPTER 11 WATCH TIMER 11.3 Operation of the Watch Timer The watch timer functions as a clock source for the watchdog counter, a timer for the oscillation stabilization time of the subclock, and an interval timer for generating interrupts periodically. ■ Watch Counter The watch timer includes a 15-bit counter that counts entered oscillator clocks from which machine clocks are created. The count operation continues while oscillator clocks are being input. The watch timer is cleared following a power-on reset, a transition to stop or hardware standby mode, and writing 0 to the WTR bit of the WTC register. Clearing the watch timer affects the watchdog counter and interval interrupts using outputs from the watch timer. ■ Interval Interrupt Function of the Watch Timer Interrupts are generated periodically by the carry signal from the watch counter. The WTOF flag is set whenever the interval time set with the WTC1 and WTC0 bits of the WDTC register elapses. The flag is set based on the time the watch timer was last cleared. Upon a transition to stop or hardware standby mode, the WTOF flag is cleared because the watch timer is used as the timer for the oscillation stabilization time for a return. 178 CHAPTER 12 16-BIT I/O TIMER This chapter describes the functions and operations of the 16-bit I/O timer. 12.1 "Overview of the 16-Bit I/O Timer" 12.2 "Block Diagram of the 16-Bit I/O Timer" 12.3 "16-Bit Input/Output Timer Register" 12.4 "16-Bit Free Run Timer" 12.5 "Output Compare" 12.6 "Input Capture" 12.7 "Operation of the 16-Bit Free Run Timer" 12.8 "Operation of the 16-Bit Output Compare" 12.9 "Operation of the 16-Bit Input Capture" 179 CHAPTER 12 16-BIT I/O TIMER 12.1 Overview of the 16-Bit I/O Timer The 16-bit I/O timer consists of one 16-bit free run timer, four output compare modules, and two input capture modules. Using this function enables two independent waveforms to be output based on the 16bit free run timer, enables the input pulse width to be measured, and enables the external clock cycle to be measured. ■ 16-Bit Free Run Timer (x 1) The 16-bit free run timer consists of a 16-bit up counter, control register, and prescaler. The output value of this timer counter is used as the basic time (base timer) for the output compare and input capture. ❍ The counter operation clock (can be selected from the four types) Four types of internal clock (φ/4, φ/16, φ/32, and φ/64) ❍ Interrupt An interrupt can be generated by a counter value overflow or matching by comparison with compare register 0. (The mode must be set for compare match interrupt.) ❍ Initialization The counter can be initialized to 0000H by a reset, software clearance, or matching by comparison with compare register 0. ■ Output Compare (x 4) The output compare consists of two 16-bit compare registers, a compare output latch, and a control register. If the value of the 16-bit free run timer matches the compare register value, the pin output level is reverted and an interrupt occurs. • The four compare registers operate independently. • • An output pin and interrupt flag are provided for each compare register. The four compare registers can be paired to control the output pin. • The four compare registers are used to revert the output pin. • The initial value of the output pin can be set. • An interrupt can be generated when the values match by comparison. ■ Input Capture (x 2) The input capture consists of capture registers, and control register. Detecting an edge of the signal input from the external input pin enables the value of the 16-bit free run timer to be retained in the capture register and an interrupt to be generated simultaneously. • An external input signal edge can be selected. • 180 The external input signal edge can be selected from the rising edge, falling edge, or both edges. 12.1 Overview of the 16-Bit I/O Timer • The two input captures operate independent of each other. • The valid edge of an external input signal can be used to generate an interrupt. • An input capture interrupt starts the intelligent IO service. ■ Registers of Entire 16-Bit I/O Timer Section Figure 12.1-1 "Configuration of 16-Bit Input Capture Registers" shows the configuration of registers in the 16-bit input/output timer section. Figure 12.1-1 Configuration of 16-Bit Input Capture Registers 16-bit free run timer registers 15 Address: 000056H, 57H 0 Timer counter data register TCDT 7 Address: 000058H 0 TCCS Timer counter control status register 16-bit output compare registers 15 Address: 00005AH, 5BH 00005CH, 5DH 00005EH, 5FH 000060H, 61H 15 Address: 000062H, 63H 000064H, 65H 0 Output compare register OCCP0~7 0 OCS01,OCS3 Output compare control status register OCS0,OCS2 16-bit input capture registers 15 Address: 000050H, 51H 000052H, 53H Address: 000054H 0 Input capture data register IPCP0,1 ICS01 Input capture control status register 181 CHAPTER 12 16-BIT I/O TIMER 12.2 Block Diagram of the 16-Bit I/O Timer Figure 12.2-1 "Block Diagram of the 16-Bit I/O Timer" is a block diagram of the 16-bit I/ O timer. ■ Block Diagram of the 16-Bit I/O Timer Figure 12.2-1 Block Diagram of the 16-Bit I/O Timer Control logic Interrupt To each block 16-bit free run timer Internal Data Bus 16-bit timer Clear Output compare 0 Compare register 0 T Q OUT0 T Q OUT1 T Q OUT2 Compare register 3 T Q OUT3 Capture register 0 Edge selection IN0 Capture register 1 Edge selection IN1 Output compare 1 Compare register 1 Output compare 2 Compare register 2 Output compare 3 Input capture 0 182 12.3 16-Bit Input/Output Timer Register 12.3 16-Bit Input/Output Timer Register There are the following 6 types of 16-bit input/output timer registers: • Timer counter data register (TCDT) • Timer counter control status register (TCCS) • Output compare register (OCCP0 to OCCP3) • Output compare control status register (OCS0 to OCS3) • Input capture data register (IPCP0, IPCP1) • Input capture control status register (ICS01) ■ 16-Bit Input/Output Timer Register Figure 12.3-1 16-Bit Input/Output Timer Registers (To be continued) Higher bits of the timer counter data register 15 14 13 Address: 000057H Read/Write Initial value T15 T14 T13 T07 Read/Write Initial value 10 9 8 T10 T09 T08 Bit No. TCDT(High) T06 5 4 3 2 1 0 T05 T04 T03 T02 T01 T00 Bit No. TCDT(Low) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Timer counter control status register 7 Address: 000058H 11 T11 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Lower bits of the timer counter data register 7 6 Address: 000056H Read/Write Initial value 12 T12 Reserved 6 5 IVF 4 3 2 1 IVFE STOP MODE CLR Bit No. 0 CLK1 CLK0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Higher bits of the output compare register 15 Address: ch0 00005BH ch1 00005DH ch2 00005FH C15 C14 ch3 000061H (R/W) (R/W) Read/Write (X) (X) Initial value 14 C13 13 C12 12 11 C11 10 C10 9 C09 8 Bit No. OCCP0~3(High) C08 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) Lower bits of the output compare register 7 6 5 4 3 2 1 0 Address: ch0 00005AH ch1 00005CH C07 C06 C05 C04 C03 C02 C01 C00 ch2 00005EH ch3 000060H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/Write (X) (X) (X) (X) (X) (X) (X) (X) Initial value Higher bits of the output compare control status register 15 14 13 12 11 10 9 8 Address: ch1 000063H CMOD OTE1 OTE0 OTD1 OTD0 ch3 000065H Read/Write (-) (-) (-) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (-) (-) (-) (0) (0) (0) (0) (0) Lower bits of the output compare control status register 7 6 5 4 Address: ch0 000062H ICP1 ICP0 ICE1 ICE0 ch2 000064H Read/Write Initial value TCCS (R/W) (R/W) (R/W) (R/W) (-) (0) (0) (0) (0) (-) 3 2 1 0 CST1 CST0 (-) (-) Bit No. OCCP0~3(Low) Bit No. OCS1,3 Bit No. OCS0,2 (R/W) (R/W) (0) (0) 183 CHAPTER 12 16-BIT I/O TIMER Higher bits of the input capture data register 15 Address: ch0 000051H ch1 000053H Read/Write Initial value 14 13 (R) (X) 184 10 9 8 (R) (X) (R) (X) (R) (X) 5 (R) (X) 4 (R) (X) 3 (R) (X) 2 (R) (X) Bit No. IPCP0,1 (R) (X) 1 0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 Input capture control status registers 7 Address: 000054H Read/Write Initial value 11 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 Lower bits of the input capture data register 7 6 Address: ch0 000050H ch1 000052H Read/Write Initial value 12 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) 6 5 4 3 2 1 0 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Bit No. IPCP0,1 Bit No. ICS01 12.4 16-Bit Free Run Timer 12.4 16-Bit Free Run Timer The 16-bit free run timer consists of the following two components. • Timer Counter Data Register(TCDT) • Timer Counter Control Status Register (TCCS) ■ 16-Bit Free Run Timer The count value of the 16-bit free run timer is used as the basic time (base timer) for the output compare and input capture. • The count clock can be selected from the four types. • A counter overflow interrupt can be generated. • Depending on the mode setting, the counter can be initialized when the value matches the value of the compare register 0 of the output compare. ■ 16-Bit Free Run Timer Registers The configuration of the 16-bit free run timer registers is shown below. Figure 12.4-1 16-Bit Free Run Timer Registers 0 15 Timer counter data register TCDT Address: 000056, 57H 7 0 Timer counter control status register TCCS Address: 000058 ■ Block Diagram of 16-Bit Free Run Timer Figure 12.4-2 "Block Diagram of 16-Bit Free Run Timer" is a block diagram of the 16-bit free run timer. Figure 12.4-2 Block Diagram of 16-Bit Free Run Timer Internal Data Bus Interrupt request IVF IVFE STOP MODE CLR CLK1 CLK0 ø Frequency divider (TCCS) Comparator 0 Clock 16-bit free run timer [timer data register (TCDT)] T15~T00 Count value output 185 CHAPTER 12 16-BIT I/O TIMER 12.4.1 Timer Counter Data Register (TCDT) The timer counter data register (TCDT) can read the count value of the 16-bit free run timer. ■ Timer Counter Data Register (TCDT) In the timer counter data register (TCDT), the counter value is set to "0000H" at reset. Writing data to this register enables to set the timer value. This must be performed in stop status (STOP=1). The 16-bit free run timer is initialized when the following factors occur. • Initialized by a reset. • Initialized by the clear bit (CLR) of the control status register. • Initialized when the value of the compare register 0 of output compare and the timer counter value match (the mode must be set). Figure 12.4-3 Timer Counter Data Register (TCDT) Higher bits of the timer counter data register 15 14 13 Address: 000057H T15 T14 T13 12 11 10 9 8 T12 T11 T10 T09 T08 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) Lower bits of the timer counter data register 7 6 5 4 3 2 1 0 Address: 000056H Read/Write Initial value T07 T06 T05 T04 T02 T01 T00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Note: To access this register, use word access. 186 T03 Bit No. TCDT(High) Bit No. TCDT(Low) 12.4 16-Bit Free Run Timer 12.4.2 Timer Counter Control Status Register (TCCS) The timer counter control status register (TCCS) controls the timer counter of the 16bit free run timer. ■ Timer Counter Control Status Register (TCCS) Figure 12.4-4 Timer Counter Control Status Register (TCCS) Timer counter control status register 7 Address: 000058H Read/Write Initial value Reserved 6 IVF 5 4 3 2 IVFE STOP MODE CLR 1 0 CLK1 CLK0 Bit No. TCCS (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) [Bit 7] Reserved bit Bit 7 is a reserved bit. 0 must be written in this bit. [Bit 6] IVF This bit is a 16-bit free run timer interrupt request flag. When an overflow occurs in the 16-bit free run timer or when the counter is cleared as a result of matching by comparison with compare register 0 according to the mode setting, this bit is set to 1. If the interrupt request enable bit (bit 5: IVFE) is set, an interrupt occurs. This bit is cleared when 0 is written. Writing 1 is ineffectual. Read-modify instructions can read 1. Table 12.4-1 IVF (Interrupt Request Flag) Function IVF Function 0 Interrupt request is not present (initial value) 1 Interrupt request is present [Bit 5] IVFE This bit is the 16-bit free run timer interrupt enable bit. When the interrupt flag (bit 5: IVF) is set to 1 when the bit is 1, an interrupt occurs. 187 CHAPTER 12 16-BIT I/O TIMER Table 12.4-2 IVFE (Interrupt Enable Bit) Funtion IVFE Function 0 Interrupt disabled (initial value) 1 Interrupt enabled [Bit 4] STOP This bit is for stopping the 16-bit free run timer from counting. When 1 is written, the timer stops counting. When 0 is written, the timer starts counting. Table 12.4-3 STOP (Count Stop Bit) Function STOP Function 0 Counting enabled (active) (initial value) 1 Counting disabled (stop) Note: When the 16-bit free run timer stops counting, the output compare also stops operation. [Bit 3] MODE This bit is for setting the initialization condition of the 16-bit free run timer. When this bit is set to 0, the counter value can be initialized by a reset and clear bit (bit 2: CLR). When this bit is set to 1, the counter value can be initialized by a reset, by a clear bit (bit 2: CLR), and by matching with the value of compare register 0 of output compare. Table 12.4-4 MODE (Initialization Condition Setting Bit) Function MODE Function 0 Initialized by reset and clear bit (initial value) 1 Initialized by reset, clear bit, compare register 0 Note: The counter value is initialized at the point at which the count value changes. [Bit 2] CLR This bit is for initializing the active 16-bit free run timer to 0000. When 1 is written, the counter value is initialized to 0000. Writing 0 is ineffectual. The read value is consistently 0. The counter value is initialized at the point at which the count value changes. 188 12.4 16-Bit Free Run Timer Table 12.4-5 CLR (Initializing Bit) Function CLR Function 0 Ineffectual (initial value) 1 Counter value is initialized to 0000 Note: To initialize when the timer is stopped, write 0000 in the data register. [Bits 1 and 0] CLK1, CLK0 These bits are for selecting the count clock of the 16-bit free run timer. The clock changes immediately after the bits are written. Therefore, the clock should be changed when the output compare and input capture are stopped. Table 12.4-6 CLK1, CLK0 (Count Clock Selection Bit) CLK1 CLK1 Count clock φ=16MHz φ=8MHz φ=4MHz φ=1MHz 0 0 φ/4 0.25 µs 0.5 µs 1 µs 4 µs 0 1 φ/16 1 µs 2 µs 4 µs 16 µs 1 0 φ/64 4 µs 8 µs 16 µs 64 µs 1 1 φ/256 16 µ 32 µs 64 µs 256 µs Note: φ: Machine clock 189 CHAPTER 12 16-BIT I/O TIMER 12.5 Output Compare The output compare consists of the following two components. • Output Compare Register (OCCP0 to OCCP3) • Output Compare Control Status Register (OCS0 to OCS3) ■ Output Compare If the value set in the compare register matches the value of the 16-bit free run timer, the pin output level is reverted and an interrupt occurs. • Two compare registers are provided and can operate independent of each other. Depending on the setting, the two compare registers can be used to control pin output. • The pin output initial value can be set. • Matching by comparison can generate an interrupt. ■ Output Compare Registers The configuration of the output compare registers is shown below. Figure 12.5-1 Output Compare Register Configuration 0 15 Address: 00005AH, 5BH 00005CH, 5DH 00005EH, 5FH 000060H, 61H Address: 000062H, 63H 000064H, 65H 190 Output compare register x=0 to 3 OCCPx 15 0 OCSy OCSx Output compare control status register x=0, 2 y=1, 3 12.5 Output Compare ■ Block Diagram of Output Compare Figure 12.5-2 "Block Diagram of Output Compare" is a block diagram of the output compare. Figure 12.5-2 Block Diagram of Output Compare 16-bit timer counter value (T15 to T00) Internal Data Bus Compare control TQ OTE0 OUT0 (OUT2) Compare register 0 (2) 16-bit timer counter value (T15 to T00) CMOD Compare control TQ OTE1 OUT1 (OUT3) Compare register 1 (3) ICP1 Control section ICP0 ICE1 ICE0 Compare 1 (3) interrupt Compare 0 (2) interrupt Each control block 191 CHAPTER 12 16-BIT I/O TIMER 12.5.1 Output Compare Register (OCCP0 to OCCP3) The output compare register (OCCP0 to OCCP3) is a16-bit compare register for comparison with the 16-bit free run timer. ■ Output Compare Register (OCCP0 to OCCP3) The initial value of the register value is undefined and must be set before activation is enabled. When this register value and the value of the 16-bit free run timer match, a compare signal is generated and the output compare interrupt flag is set. If output is enabled, the output level corresponding to the compare register is reverted. Figure 12.5-3 Output Compare Register (OCCP0 to OCCP3) Higher bits of the output compare register Address: ch0 00005BH ch1 00005DH ch2 00005FH ch3 000061H Read/Write Initial value Address: ch0 00005AH ch1 00005CH ch2 00005EH ch3 000060H Read/Write Initial value 15 C15 14 C14 13 C13 12 C12 C11 10 C10 9 C09 8 Bit No. OCCP0 to 3 (High) C08 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 C07 C06 C05 C04 C03 C02 C01 C00 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Note: To access this register, use word access. 192 11 Bit No. OCCP0 to 3 (Low) 12.5 Output Compare 12.5.2 Output Compare Control Status Register (OCS0 to OCS3) The output compare control status register (OCS0 to OCS3) controls the 16-bit free run timer. ■ Output Compare Control Status Register (OCS0 to OCS3) Figure 12.5-4 Output Compare Control Status Register (OCS0 to OCS3) Higher bits of the output compare control status register 15 Address: ch1 000063H ch3 000065H Read/Write Initial value 14 13 12 11 10 9 8 Bit No. CMOD OTE1 OTE0 OTD1 OTD0 (-) (-) (-) (-) (-) (-) OCS1,3 (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) Lower bits of the output compare control status register 7 6 5 4 3 Address: ch0 000062H ICP1 ICP0 ICE1 ICE0 ch2 000064H Read/Write (R/W) (R/W) (R/W) (R/W) (-) Initial value (0) (0) (0) (0) (-) 2 1 0 CST1 CST0 (-) (-) Bit No. OCS0,2 (R/W) (R/W) (0) (0) [Bits 15, 14, and 13] Unused bits [Bit 12] CMOD If pin output is enabled (OTE1 = 1 or OTE0 = 1), the pin output level revert operation mode is switched at matching by comparison. ❍ When CMOD is 0 (Initial value) When CMOD is 0 (initial value), the pin output level corresponding to the compare register is reverted. • OUT0/2: The level is reverted when the value matches compare register 0. • OUT1/3: The level is reverted when the value matches compare register 1. ❍ When CMOD is 1 When CMOD is 1, the output level for compare register 0 is reverted as when CMOD is 0, but the pin (OUT1) output level corresponding to compare register 1 is reverted when the value of compare register 0 matches the value of compare register 1. If compare registers 0 and 1 have the same value, the operation is the same as that when there is only one compare register. • OUT0/2: The level is reverted when the value matches compare register 0. • OUT1/3: The level is reverted when compare registers 0 and 1 match. 193 CHAPTER 12 16-BIT I/O TIMER [Bits 11 and 10] OTE1, OTE0 These are output compare pin output enable bits. The initial value of these bits is 0. Table 12.5-1 OTE1, OTE0 (Pin Output Enable Bit) Function OTE1, OTE0 Funtion 0 Operates as a general-purpose port (initial value) 1 Becomes an output compare pin output Note: OTE1: Corresponds to output compare 1/3. OTE0: Corresponds to output compare 0/2. [Bits 9 and 8] OTD1, OTD0 These bits are used for changing the pin output level when the output compare pin output is enabled. The initial value of compare pin output is 0. To write these bits, compare operation must be stopped. When these bits are read, the output compare pin output value can be read. Table 12.5-2 OTD1, OTD0 (Pin Output Level Change Bit) Function OTD1, OTD0 Funtion 0 Compare pin output becomes 0 (initial value) 1 Compare pin output becomes 1 Note: OTD1: Corresponds to output compare 1/3. OTD0: Corresponds to output compare 0/2. [Bits 7 and 6] ICP1, ICP0 These bits are output compare interrupt flags. When the compare register value matches the value of the 16-bit free run timer, the bits are set to 1. When the bits are set when the interrupt request bits (ICE1, ICE0) are enabled, an output compare interrupt occurs. The bits are cleared when 0 is written. Writing 1 is ineffectual. Read-modify instructions can read 1. Table 12.5-3 ICP1, ICP0 (Output Compare Interrupt Bit) Function ICP1, ICP0 Funtion 0 Did not match by comparison (initial value) 1 Matched by comparison Note: ICP1: Corresponds to output compare 1/3. ICP0: Corresponds to output compare 0/2. [Bits 5 and 4] ICE1, ICE0 These are output compare interrupt enable bits. When the interrupt flag (ICP0, ICP1) is set 194 12.5 Output Compare when these bits are 1, an output compare interrupt occurs. Table 12.5-4 ICE1, ICE0 (Output Compare Interrupt Enable Bit) Function ICE1, ICE0 Funtion 0 Output compare interrupt disabled (initial value) 1 Output compare interrupt enabled Note: ICE1: Corresponds to output compare 1/3. ICE0: Corresponds to output compare 0/2. [Bits 3 and 2] Unused bits [Bits 1 and 0] CST1, CST0 These bits enable a matching operation with the 16-bit free run timer. The compare register value must be set before compare operation is enabled. Table 12.5-5 CST1, CST0 (Matching Operation with the 16-bit Free Run Timer Bit) Function CST1, CST0 Funtion 0 Compare operation disabled (initial value) 1 Compare operation enabled Note: CST1: Corresponds to output compare 1/3. CST0: Corresponds to output compare 0/2. When the 16-bit free run timer stops, the compare operation also stops because the output compare is synchronized with the clock of the 16-bit free run timer. 195 CHAPTER 12 16-BIT I/O TIMER 12.6 Input Capture The input capture unit contains the following two registers: • Input capture data register (IPCP0, IPCP1) • Input capture control status register (ICS01) ■ Input Capture The input capture consists of an input capture data register and control register. Each input capture has the corresponding external input pin. • An external input valid edge can be selected from the three types. Rising edge ( ) / Falling edge ( ) / Both edges ( • ) When an external input valid edge is detected, an interrupt occurs. ■ Entire Input Capture Registers The configuration of the input capture registers is shown below. Figure 12.6-1 Entire Input Capture Register 196 Address: 000050H, 51H 000052H, 53H Input capture data register x=0 1 Address: 000054H Input capture control status register 12.6 Input Capture ■ Block Diagram of Entire Input Capture Figure 12.6-2 Block Diagram of Entire Input Capture Edge detection Internal Data Bus Capture data register 0 16-bit timer counter value (T15 to T00) EG11 EG10 EG01 EG00 Edge detection Capture data register 1 ICP1 ICP0 ICE1 ICE0 Interrupt Interrupt 197 CHAPTER 12 16-BIT I/O TIMER 12.6.1 Input Capture Data Register (IPCP0, IPCP1) When a valid edge of the corresponding external pin input waveform is detected, this register retains the value of the 16-bit free run timer. ■ Input Capture Registers (IPCP0, IPCP1) Figure 12.6-3 Input Capture Data Register (IPCP0, IPCP1) Higher bits of the capture data register 15 Address: ch0 000051H ch1 000053H Read/Write Initial value 14 13 11 10 9 8 (R) (X) (R) (X) (R) (X) (R) (X) 5 (R) (X) 4 (R) (X) 3 (R) (X) 2 (R) (X) 1 0 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) Note: To access, word access must be used. This register cannot be written. 198 Bit No. IPCP0 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 Lower bits of the input capture data register 7 6 Address: ch0 000050H ch1 000052H Read/Write Initial value 12 Bit No. IPCP1 12.6 Input Capture 12.6.2 Input Capture Control Status Register (ICS01) The input capture control status register (ICS01) controls the 16-bit free run timer. ■ Input Capture Control Status Register (ICS01) Figure 12.6-4 Input Capture Control Status Register (ICS01) Input capture control status register 7 6 5 4 3 2 1 0 Address: 000054H ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Read/Write Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Bit No. ICS01 Note: To access the ICS01 register, byte access should be used. [Bits 7 and 6] ICP1, ICP0 These bits indicate an input capture interrupt flag. When a valid edge of the external input pin is detected, these bits are set to 1. When the interrupt enabled bits (ICE0 and ICE1) are set, detecting a valid edge generates an interrupt. Writing 0 clears these bits. Writing 1 is ineffectual. Read-modify write instructions can read 1. Table 12.6-1 ICP1, ICP0 (Input Capture Interrupt Flag) Function ICP1, ICP0 Function 0 Valid edge is not detected (initial value) 1 Valid edge is detected Note: ICP1: Corresponds to input capture 1. ICP0: Corresponds to input capture 0. [Bits 5 and 4] ICE1, ICE0 These bits enable an input capture interrupt. When the interrupt flag (ICP0, ICP1) is set when these bits are 1, an input capture interrupt occurs. Table 12.6-2 ICE1, ICE0 (Input Capture Interrupt Enable Bit) Function ICE1, ICE0 Function 0 Interrupt disabled (initial value) 1 Interrupt enabled 199 CHAPTER 12 16-BIT I/O TIMER Note: ICE1: Corresponds to input capture 1. ICE0: Corresponds to input capture 0. [Bits 3, 2, 1, and 0] EG11, EG10, EG01, EG00 These bits specify the polarity of the external input valid edge and enable an input capture operation. Table 12.6-3 EGx1, EGx0 (External Input Valid Edge Polarity Specifying Bit) Function EG11 EG01 EG10 EG00 0 0 Edges not detected (stopped status) (Initial value) 0 1 Rising edge detected 1 0 Falling edge detected 1 1 Both edges detected Polarity of edge detection Note: EG01, EG00: Correspond to input capture 0. EG11, EG10: Correspond to input capture 1. 200 12.7 Operation of the 16-Bit Free Run Timer 12.7 Operation of the 16-Bit Free Run Timer The 16-bit free run timer starts counting from the counter value 0000 after the reset is released. This counter value becomes the reference time for 16-bit output compare and 16-bit input capture. ■ Operation of the 16-Bit Free Run Timer The counter value is cleared when the following five conditions are met. • When an overflow occurs. • When the value of output compare register 0 matches by comparison (the mode must be set). • When 1 is written in the CLR bit of the TCCS register during operation. • When 0000 is written in the TCDC register during stop. • When reset. An interrupt can be generated when an overflow occurs and when the value of compare register 0 matches by comparison and the counter is cleared. (The mode must be set for compare match interrupt.) Figure 12.7-1 Counter Cleared by Overflow Counter value Overflow FFFFH BFFFH 7FFFH 3FFFH Time 0000H Reset Interrupt Figure 12.7-2 Counter Cleared When the Value of Output Compare Register 0 Matches by Comparison Counter value FFFFH BFFFH Matched Matched 7FFFH 3FFFH 0000H Time Reset Compare register value BFFFH Interrupt 201 CHAPTER 12 16-BIT I/O TIMER ■ Timing for 16-bit Free-running Timer The 16-bit free-running timer is incremented based on the input clock (internal or external clock). When an external clock is selected, the 16-bit free-running timer is incremented at the rising edge. Figure 12.7-3 16-bit free-running timer count timing Machine clock φ External clock input Count clock N Counter value N+1 The counter can be cleared by a reset, software clear, or match with compare register 0. For a reset or software clear, the counter is cleared. For a match with compare register 0, the counter is cleared synchronously with the count timing. Figure 12.7-4 16-bit free-running timer clear timing (match with the compare register 0) Machine clock φ N Compare register value Compare match Counter value 202 N 0000 12.8 Operation of the 16-Bit Output Compare 12.8 Operation of the 16-Bit Output Compare The 16-bit output compare compares the value set in the compare register with the value of the 16-bit free run timer. If the values match, it sets the interrupt request flag and reverts the output level. ■ Operation of the 16-Bit Output Compare Figure 12.8-1 Example of Output Waveform When Compare Registers 0 and 1 Are Used (Initial Value of Output Is Zero) Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset Value of compare register 0 BFFFH Value of compare register 1 7FFFH Compare 0 interrupt Compare 1 interrupt 203 CHAPTER 12 16-BIT I/O TIMER Figure 12.8-2 Example of Output Waveform from Two Pairs of Compare Registers (Initial Value of Output Is Zero) Counter value FFFFH BFFFH 7FFFH 3FFFH Time 0000H Reset BFFFH Value of compare register 0 7FFFH Value of compare register 0 Corresponds to compare 0 Corresponds to compare 0 and 1 Compare 0 interrupt Compare 1 interrupt ■ Timing for 16-bit Output Compare The output compare unit can generate a compare match signal when the free run timer value is consistent with the setting value of the compare register. It can then invert the output value and generate an interrupt. The output invert timing when the compare match is executed synchronously with the count timing of the counter. The counter value when the compare register is rewritten is not compared. Figure 12.8-3 Compare Operation When the Compare Register is Rewritten Counter value Compare register 0 value Compare register 0 write Compare register 1 value Compare register 1 write 204 N M N+1 N+2 No identify signal is generated. N+1 N+3 N+3 M Compare 0 stopped Compare 1 stopped 12.8 Operation of the 16-Bit Output Compare Figure 12.8-4 Output Compare Interrupt Timing Counter value N+1 N Compare register value N Compare match Interrupt Figure 12.8-5 Output Pin Change Timing of Output Compare Counter value Compare register value N N N+1 N+1 N Compare match signal Pin output 205 CHAPTER 12 16-BIT I/O TIMER 12.9 Operation of the 16-Bit Input Capture The 16-bit input capture detects the set valid edge, captures the value of the 16-bit free run timer into the capture register, and generates an interrupt. ■ Operation of the 16-Bit Input Capture Figure 12.9-1 Data Capture Timing of the Input Capture Counter value FFFF BFFF 7FFF 3FFF Time 0000 Reset IN example Capture 0 Undefined Capture 1 Undefined Capture example Undefined Capture 0 interrupt Capture 1 interrupt Capture interrupt Capture 0 = Rising edge Capture 1 = Falling edge Capture example = Both edges (as an example) 206 12.9 Operation of the 16-Bit Input Capture ■ Input Capture Input Timing Figure 12.9-2 Input Signal Capture Timing Counter value Input capture input Valid edge Capture signal Capture register Interrupt 207 CHAPTER 12 16-BIT I/O TIMER 208 CHAPTER 13 8/16-BIT PPG This chapter describes the functions and operations of the 8/16-bit PPG. 13.1 "Overview of the 8/16-Bit PPG" 13.2 "Block Diagrams of the 8/16-Bit PPG" 13.3 "Registers of the 8/16-Bit PPG" 13.4 "Operation of the 8/16-Bit PPG" 209 CHAPTER 13 8/16-BIT PPG 13.1 Overview of the 8/16-Bit PPG The 8/16-bit PPG is an 8-bit reload timer module that performs PPG output by pulse output control according to timer operation. ■ Overview of the 8/16-Bit PPG The 8/16-bit PPG has two 8-bit down counters, four 8-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs as hardware and supports the following functions: ❍ Two independent 8-bit output channel operating mode: Enables PPG output operation with two independent channels. ❍ 16-bit PPG output operating mode: Enables PPG output operation with one 16-bit channel. ❍ 8+8-bit PPG output operating mode: Uses the channel 0 output as the channel 1 clock input to enable 8-bit PPG output operation in any cycle. ❍ PPG output operation: Outputs pulse waves with any duty cycle in any cycle and can be used as a D/A converter with an external circuit. 210 13.2 Block Diagrams of the 8/16-Bit PPG 13.2 Block Diagrams of the 8/16-Bit PPG Figure 13.2-1 "Block Diagram of the 8/16-Bit PPG (Channel 0)" and Figure 13.2-2 "Block Diagram of the 8/16-Bit PPG (Channel 1)" show a block diagram of the 8/16-bit PPG. ■ Block Diagrams of the 8/16-Bit PPG Figure 13.2-1 Block Diagram of the 8/16-Bit PPG (Channel 0) PPG0 output enable PPG0 Peripheral clock/16 Peripheral clock/8 Peripheral clock/4 Peripheral clock/2 Peripheral clock A/D converter PPGO output latch Invert Clear PEN0 Count clock selection IRQ Reload Time base counter output Main clock/512 L/H select S RQ PCNT(down counter) Channel 1 borrow L/H selector PRLL0 PRLBH0 PIE0 PRLH0 PUF0 L data bus H data bus PPGC0 (Operating mode control) 211 CHAPTER 13 8/16-BIT PPG Figure 13.2-2 Block Diagram of the 8/16-Bit PPG (Channel 1) PPG1 output enable Peripheral clock/16 Peripheral clock/8 Peripheral clock/4 Peripheral clock/2 Peripheral clock PPG1 output latch Invert Clear Count clock selection Channel 0 borrow PCNT (down counter) Time base counter output Main clock/512 L/H select Reload L/H selector L data bus H data bus (Operating mode control) 212 13.3 Registers of the 8/16-Bit PPG 13.3 Registers of the 8/16-Bit PPG The 8/16-bit PPG register has three types as follows: • PPG operating mode control register • PPG output control register • Reload register ■ Registers of the 8/16-Bit PPG The register configuration of the 8/16-bit PPG is shown below. Figure 13.3-1 8/16-Bit PPG Registers Bit number PPG0 operating mode control register Address Reserved Read/write Initial value PPG1 operating mode control register Address Bit number Reserved Read/write Initial value Bit number PPG0 and PPG1 output control register Address Read/write Initial value Reload register H Address :ch0 000041H ch1 000043H Read/write Initial value Reload register L Address :ch0 000040H ch1 000042H 15 14 13 12 11 10 9 8 Bit number PRLH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 Bit number PRLL Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) 213 CHAPTER 13 8/16-BIT PPG 13.3.1 PPG0 Operating Mode Control Register (PPGC0) The PPG0 operating mode control register (PPGC0) selects the operating mode, controls pin output, selects count clock, and controls a trigger for the 8/16-bit PPG. ■ PPG0 Operating Mode Control Register (PPGC0) The PPGC0 bit configuration is shown below. Figure 13.3-2 PPG0 Operating Mode Control Register (PPGC0) PPG0 operating mode control register Address:ch0 000044H 7 6 PEN0 Read/write Initial value (R/W) (-) (0) (-) 5 4 PE00 PIE0 3 2 1 PUF0 (R/W) (R/W) (R/W) (-) (0) (0) (0) (-) 0 Bit number Reserved (-) (-) PPGC0 (-) (1) [Bit 7] PPG enable bit (PEN0) This bit selects the start of PPG operation and operating mode as follows. Writing 1 in this bit starts PPG counting. This bit is initialized to "0" by a reset and is a read/write bit. Table 13.3-1 PEN0 (Operating Enable Bit) Function PEN0 Function 0 Operation stopped ("L" level output is retained.) [Initial value] 1 PPG operation enabled [Bit 5] PPG00 output enable bit (PE00) This bit controls pulse output external pin PPG00 as follows. This bit is initialized to "0" by a reset. It is a read/write bit. Table 13.3-2 PEO0 (PPG0 Pin Output Enable Bit) Function PEO0 Function 0 General-purpose port pin (pulse output disabled) [Initial value] 1 PPG0=Pulse output pin (pulse output enabled) [Bit 4] PPG interrupt enable bit (PIE0) This bit controls PPG interrupts as follows. When this bit is "1", setting PUF0 to "1" generates an interrupt request. When this bit is "0", no interrupt request is generated. 214 13.3 Registers of the 8/16-Bit PPG This bit is initialized to "0" by a reset and is a read/write bit. Table 13.3-3 PIE0 (PPG Interrupt Enable Bit) Function PIE0 Function 0 Disables interrupts. [Initial value] 1 Enables interrupts. Note: The same interrupt vector number as for 16-bit reload timer channel 0 is assigned. When EI2OS is to be used for 16-bit reload timer channel 0, set PIE0 to "0". [Bit 3] PPG underflow bit (PUF0) The PPG underflow bit is controlled as follows. In the two 8-bit PPG channel mode or 8-bit prescaler and 8-bit PPG mode, this bit is set to "1" by an underflow caused when the channel 0 counter value changes from 00H to FFH. In the one 16-bit PPG channel mode, this bit is set to "1" by an underflow caused when the channel 1 or 0 counter value changes from 0000H to FFFFH. Writing "0" sets this bit to "0". Writing "1" in this bit has no meaning. When this bit is read by a read-modify-write instruction, the read value is "1". This bit is initialized to "0" by a reset and is a read/write bit. Table 13.3-4 PUF0 (PPG Counter Underflow Bit) Function PUF0 Function 0 A PPG counter underflow is not detected. 1 A PPG counter underflow was detected. [Bit 0] Reserved bit. Always set this bit to 1 when setting the PPGC0. 215 CHAPTER 13 8/16-BIT PPG 13.3.2 PPG1 Operating Mode Control Register (PPGC1) The PPG1 operating mode control register (PPGC1) selects the operating mode, controls pin output, selects count clock, and controls the trigger for the 8/16-bit PPG. ■ PPG1 Operating Mode Control Register (PPGC1) Figure 13.3-3 PPG1 Operating Mode Control Register (PPGC1) PPG1 operating mode control register 000045H Address :ch1 15 14 PEN1 Read/write Initial value (R/W) (-) (0) (X) 13 12 PE10 PIE1 11 10 9 PUF1 MD1 MD0 8 Bit number Reserved PPGC1 (R/W) (R/W) (R/W) (R/W) (R/W) (-) (0) (0) (0) (0) (0) (1) [Bit 15] PPG enable bit (PEN1) This bit selects the start of PPG operation and operating mode as follows. Writing 1 in this bit makes the PWM start counting. This bit is initialized to "0" by a reset and is a read/write bit. Table 13.3-5 Operating Enable Bit (PEN1) Function PEN1 Function 0 Operation stopped ("L" level output is retained.) [Initial value] 1 PPG operation enabled [Bit 13] PPG10 output enable bit (PE10) This bit controls pulse output external pin PPG10 as follows. This bit is initialized to "0" by a reset and is a read/write bit. Table 13.3-6 PE10 (PPG10 Pin Output Enable Bit) Function PE10 Function 0 General-purpose port pin (pulse output disabled) [Initial value] 1 PPG1=Pulse output pin (pulse output enabled) [Bit 12] PPG interrupt enable bit (PIE1) This bit controls PPG interrupts as follows. When this bit is "1", setting PUF1 to "1" generates an interrupt request. When this bit is "0", no interrupt request is generated. 216 13.3 Registers of the 8/16-Bit PPG This bit is initialized to "0" by a reset and is a read/write bit. Table 13.3-7 PIE1 (PPG Interrupt Enable Bit) Function PIE1 Function 0 Disables interrupts. [Initial value] 1 Enables interrupts. Note: The same interrupt vector number as for 16-bit reload timer channel 1 is assigned. When EI2OS is to be used for 16-bit reload timer channel 1, set PIE1 to "0". [Bit 11] PPG underflow bit (PUF1) The PPG underflow bit is controlled as listed below. In the two 8-bit PPG channel mode or 8-bit prescaler and 8-bit PPG mode, this bit is set to "1" by an underflow caused when the channel 0 counter value changes from 00H to FFH. In the one 16-bit PPG channel mode, this bit is set to "1" by an underflow caused when the channel 1 or 0 counter value changes from 0000H to FFFFH. Writing "0" sets this bit to "0". Writing "1" in this bit has no meaning. When this bit is read by a read-modify-write instruction, the read value is "1". This bit is initialized to "0" by a reset and is a read/write bit. Table 13.3-8 PUF1 (PPG Counter Underflow Bit) Function PUF1 Function 0 A PPG counter underflow is not detected. [Initial value] 1 A PPG counter underflow was detected. [Bits 10 and 9] PPG count mode bits (MD2 and MD1) These bits select the PPG timer operating mode as follows. These bits are initialized to "00" by a reset and are read/write bits. Table 13.3-9 MD2, MD1 (Operating Mode Selection Bit) Function MD1 MD0 Operating mode 0 0 Two independent 8-bit PPG channel mode [Initial value] 0 1 8-bit prescaler and one 8-bit PPG channel mode 1 0 Reserved (setting prohibited) 1 1 One 16-bit PPG channel mode Note: • Do not set these bits to "10". • When setting these bits to "01", do not set the PEN0 bit in the PPGC0 and the PEN1 bit in the PPGC1 to "01". Setting the PEN0 and PEN1 bits to "11" or "00" simultaneously is recommended. • To set these bits to "11", rewrite the PPGC0 and PPGC1 by word transfer and set the PEN0 and PEN1 bits to "11" or "00" simultaneously. 217 CHAPTER 13 8/16-BIT PPG [Bit 8] Reserved bit. Always set this bit to 1. 218 13.3 Registers of the 8/16-Bit PPG 13.3.3 PPG0 and PPG1 Output Pin Control Register (PPG0E) PPG0 and PPG1 output pin control register (PPG0E) controls pin output for the 8/16-bit PPG. ■ PPG0 and PPG1 Output Pin Control Register (PPGOE) Figure 13.3-4 PPG0 and PPG1 Output Pin Control Register (PPGOE) PPG0 and PPG1 output control register Address :ch0,1 0046H 7 6 5 4 3 2 1 0 PPGOE PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 Read/write Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (-) (0) (0) (0) (0) (0) (0) (X) Bit number (-) (X) [Bits 7 to 5] PPG count select bits (PCS2 to PCS0) These bits select the operating clock of the channel 1 down counter as listed in Table 13.310 "PCS2 to PCS0 (Count Clock Selection Bit) Function". These bits are initialized to "000" by a reset and are read/write bits. Table 13.3-10 PCS2 to PCS0 (Count Clock Selection Bit) Function PCS2 PCS1 PCS0 Operating mode 0 0 0 Peripheral clock (62.5 ns when the machine clock frequency is 16 MHz) 0 0 1 Peripheral clock/2 (125 ns when the machine clock frequency is 16 MHz) 0 1 0 Peripheral clock/4 (250 ns when the machine clock frequency is 16 MHz) 0 1 1 Peripheral clock/8 (500 ns when the machine clock frequency is 16 MHz) 1 0 0 Peripheral clock/16 (1 µs when the machine clock frequency is 16 MHz) 1 1 1 Clock input from the time base timer (128 µs when the OSC oscillation frequency is 4 MHz) Note: In the 8-bit prescaler and 8-bit PPG mode and 16-bit PPG mode, the channel 1 PPG operates using the count clock received from channel 0. In these modes, the PSC1 bit specification is invalidated. [Bits 4 to 2] PPG count mode bits (PCM2 to PCM0) These bits select the operating clock of the channel 0 down counter as listed in Table 13.311 "PCM2 to PCM0 (Count Clock Selection Bit) Function". 219 CHAPTER 13 8/16-BIT PPG These bits are initialized to "000" by a reset and are read/write bits. Table 13.3-11 PCM2 to PCM0 (Count Clock Selection Bit) Function PCS2 PCS1 PCS0 Operating mode 0 0 0 Peripheral clock (62.5 ns when the machine clock frequency is 16 MHz) 0 0 1 Peripheral clock/2 (125 ns when the machine clock frequency is 16 MHz) 0 1 0 Peripheral clock/4 (250 ns when the machine clock frequency is 16 MHz) 0 1 1 Peripheral clock/8 (500 ns when the machine clock frequency is 16 MHz) 1 0 0 Peripheral clock/16 (1 µs when the machine clock frequency is 16 MHz) 1 1 1 Clock input from the time base timer (128 µs when the OSC oscillation frequency is 4 MHz) [Bit 1] PE11 (Ppg output Enable 11) This bit, which is a read/write bit that is initialized to "0" by a reset, controls the pulse output external pin PG11, as described in Table 13.3-12 "PE11 (PPG11 Pin Output Enable Bit)". Table 13.3-12 PE11 (PPG11 Pin Output Enable Bit) PE11 Function 0 General-purpose port pin (Pulse output disabled) 1 PG11=Pulse output pin (Pulse output enabled) [Bit 0] PE01 (Ppg output Enable 01) This bit, which is a read/write bit that is initialized to 0 by a reset, controls the pulse output external pin PG01, as described in Table 13.3-13 "PE01 (PPG01 Pin Output Enable Bit)". Table 13.3-13 PE01 (PPG01 Pin Output Enable Bit) PE01 220 Function 0 General-purpose port pin (Pulse output disabled) [Initial value] 1 PG01=Pulse output pin (Pulse output enabled) 13.3 Registers of the 8/16-Bit PPG 13.3.4 Reload Registers (PRLL and PRLH) The reload registers (PRLL and PRLH) retain reload values to down counter PCNT. The registers are read/write registers and have the following functions: • PRLH: Retains the H reload value. • PRLL: Retains the L reload value. ■ Reload Registers (PRLL and PRLH) The PRLL and PRLH bit configurations are shown below. Figure 13.3-5 Reload Registers (PRLL and PRLH) Reload register H Address :ch0 000041H ch1 000043H Read/write Initial value Reload register L Address :ch0 000040H ch1 000042H Read/write Initial value 15 14 13 12 11 10 9 8 Bit number PRLH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 Bit number PRLL (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Note: In the 8-bit prescaler and 8-bit PPG mode, when different values are set in the PRLL and PRLH in channel 0, channel 1 PPG waveforms may be different in each cycle. For this reason, setting the same value in the PRLL and PRLH in channel 0 is recommended. 221 CHAPTER 13 8/16-BIT PPG 13.4 Operation of the 8/16-Bit PPG The 8/16-bit PPG has two 8-bit PPG unit channels. The PPG operates in the two independent channel mode. By coupling these units together, the PPG can also operate in the 8-bit prescaler and 8-bit PPG mode and one 16-bit PPG channel mode. The PPG can perform a total of three types of operation. ■ Operation of the 8/16-Bit PPG Each 8-bit PPG unit has two 8-bit reload registers (PRLL and PRLH). Values written in H and L registers are alternately reloaded to the 8-bit down counter (PCNT). The down counter counts down for each count clock. When a counter borrow occurs at reloading, the value of the pin output (PPG) is inverted. By this operation, the pin output (PPG) is the pulse output with L and H widths corresponding to the reload register values. Writing bits in these registers starts or restarts operation. Table 13.4-1 "Relationship between Reload Operation and Pulse Output" shows the relationship between reload operation and pulse output. Table 13.4-1 Relationship between Reload Operation and Pulse Output Reload operation Transition of PG0 and PG1 output pin status PRLH --> PCNT PG0x/1x [0 -->1] Rise PRLL --> PCNT PG0x/1x [1 --> 0] Fall When bit 4 (PIE0) in the PPGC0 and bit 12 (PIE1) in the PPGC1 are 1, a borrow from 00 to FF may occur in each counter. (A borrow from 0000 to FFFF may occur in the 16-bit PPG mode.) At this time, an interrupt request is output. 222 13.4 Operation of the 8/16-Bit PPG 13.4.1 8/16-Bit PPG Operating Modes There are three 8/16-bit PPG operating modes: • Two independent channel mode • 8-bit prescaler and an 8-bit PPG mode • One 16-bit PPG channel mode. ■ 8/16-Bit PPG Operating Modes ❍ Two independent channel mode In the two independent channel mode, two channels are operated as independent 8-bit PPG units. The PPG0 pin is connected to the channel 0 PPG output. The PPG1 pin is connected to the channel 1 PPG output. ❍ 8-bit prescaler and 8-bit PPG mode In the 8-bit prescaler and 8-bit PPG mode, channel 0 is operated as an 8-bit prescaler and channel 1 count signal is output in synchronization with the channel 0 borrow output. This operation enables 8-bit PPG waveforms in any cycle to be output. The PPG0 pin is connected to the channel 0 prescaler output. The PPG1 pin is connected to the channel 0 PPG output. ❍ One 16-bit PPG channel mode In the one 16-bit PPG channel mode, channel 0 is coupled to channel 1 and both operate as a 16-bit PPG. The PPG0 and PPG1 pins are connected to the 16-bit PPG output. 223 CHAPTER 13 8/16-BIT PPG 13.4.2 8/16-Bit PPG Output Operation For the 8/16-bit PPG, setting bit 7 (PEN0) in the PPG0 operating mode control register (PPGC0) to 1 activates channel 0 PPG counting. Setting bit 15 (PEN1) in the PPG1 operating mode control register (PPGC1) to 1 activates channel 1 PPG counting. When the operation starts, setting the PEN1 bit in the PPGC1 register to 0 stops the counting operation, at which time the pulse output level remains at L level. ■ 8/16-Bit PPG Output Operation Note the following with respect to the 8/16-bit PPG output operation: • In the 8-bit prescaler and 8-bit PPG mode, when channel 0 stops, do not place channel 1 in the operating state. • In the 16-bit PPG mode, simultaneously set bit 7 (PEN0) in the PPGC0 register and bit 15 (PEN1) in the PPGC1 register to control start and stop. PPG output operation is explained below. During a PPG operation, a pulse waveform with any frequency and any duty ratio (ratio of the H level period to the total period of the pulse wave) is output continuously. After starting pulse waveform output, the PPG does not stop until an operation stop is set. Figure 13.4-1 "Output Waveform of PPG Output Operation" shows an output waveform of PPG output operation. Figure 13.4-1 Output Waveform of PPG Output Operation Output pin ppg Operation starts by PEN (from L). (Start) L: PRLL value H: PRLH value T: Peripheral clock ( /, /4, or /16) or input from the timer base counter (according to PPGC clock select) ■ Relationship between Reload Values and Pulse Widths The value obtained by multiplying the value obtained by adding 1 to a value written in a reload register by the count clock cycle is the output pulse width. Note that when the reload register value is 00H during 8-bit PPG operation or 0000H during 16bit PPG operation, the pulse width is equivalent to one count clock cycle. In addition, note that when the reload register value is FFH during 8-PPG operation, the pulse width is equivalent to 256 count clock cycles. When the reload register value is FFFFH during 16-bit PPG operation, the pulse width is equivalent to 65536 count clock cycles. The formula for the pulse width is shown below. 224 13.4 Operation of the 8/16-Bit PPG P1= T×(L+1) Ph= T×(H+1) L: PRLL value H: PRLH value T: Input clock cycle Ph: High pulse width P1: Low pulse width 225 CHAPTER 13 8/16-BIT PPG 13.4.3 Selecting the Count Clock for the 8/16-Bit PPG The peripheral clock or time base counter input is used as the count clock for 8/16-bit PPG operation. The count clock can be selected among six types of count clock inputs. ■ Selecting the Count Clock for the 8/16-Bit PPG Select the channel 0 clock using bits 4 to 2 (PCM2 to PCM0) in the PPGOE register and the channel 1 clock using bits 7 to 5 (PCS2 to PCS0). The clock can be selected among peripheral clocks obtained by dividing the machine clock by 1 to 16 and the clock input from the time base counter. In the 8-bit prescaler and 8-bit PPG mode and 16-bit PPG mode, the channel 1 PPG operates using the count clock received from channel 0. In these modes, the value of bit 14 (PCS1) in the PPGC1 register is invalidated. When the time base counter input is used, the first count cycle at activation by a trigger or after a stop may be out of synchronization. If the time base counter is cleared during operation of this module, the cycle may be out of synchronization. Note: In the 8-bit prescaler and 8-bit PPG mode, when channel 0 is in the operating state and channel 1 is in the stopped state, channel 1 may be activated, in which case the first count cycle may be out of synchronization. 226 13.4 Operation of the 8/16-Bit PPG 13.4.4 Controlling the Pulse Pin Output of the 8/16-Bit PPG The pulse output generated by operation of this module can be output from external pins PG00, PG01, PG10, and PG11. ■ Controlling the Pulse Pin Output of the 8/16-Bit PPG Whether to enable the external pin outputs is determined by bit 5 (PE00) in the PPGC0 register for the PPG0 pin and bit 13 (PE10) in the PPGC1 register for the PPG1 pin. When each bit is "0" (initial value), the pulse output is not output from the corresponding external pin and the pin functions as a general-purpose port. When each bit is set to "1", the pulse output is output from the corresponding external pin In the 16-bit PPG mode, the same waveform is output from PPG0 and PPG1. The same output can be obtained by enabling either external pin output. In the 8-bit prescaler and 8-bit PPG mode, the toggle waveform of the 8-bit prescaler is output from PPG0 and the waveform of the 8-bit PPG is output from PPG1. Figure 13.4-2 "Output Waveforms during 8+8 PPG Output Operation" shows sample output waveforms in this mode. Figure 13.4-2 Output Waveforms during 8+8 PPG Output Operation PRLL and PRLH values of channel 0 PRLL value of channel 1 PRLH value of channel 1 Input clock cycle PPG0 high pulse width PPG0 low pulse width PPG1 high pulse width PPG1 high pulse width Note: Setting the same value in the PRLL and PRLH of channel 0 is recommended. 227 CHAPTER 13 8/16-BIT PPG 13.4.5 Timing of Writing the Reload Registers in the 8/16-Bit PPG In a mode other than the 16-bit PPG mode, use of a word transfer instruction for writing the reload registers (PRLL and PRLH) is recommended. If the reload registers are written using two byte transfer instructions, an output with an unexpected pulse width may be generated depending on the timing. ■ Timing of Writing the Reload Registers in the 8/16-Bit PPG Figure 13.4-3 Timing Chart of Writing the Reload Registers in the 8/16-Bit PPG (1) Rewriting the PRLL from A to C before timing (1) and rewriting the PRLH from B to D after (1) generates one pulse with C count cycles for L and B count cycles for H because the PRLL value is C and PRLH value is B at timing (1). In the 16-bit PPG mode, use a long-word transfer instruction to write the PRLs for channels 0 and 1. Alternatively, use word transfer instructions to write the channel 0 PRLs and channel 1 PRLs in this order. In this mode, data to be written in the channel 0 PRLs is written temporarily. When the channel 1 PRLs are written, the data is written in the channel 0 PRLs. In a mode other than the 16-bit PPG mode, the channel 0 PRLs and channel 1 PRLs can be written independently as shown below. Figure 13.4-4 Block Diagram of the PRL Write Block Data to be written in the channel 0 PRLs Channel 0 writing in a mode other than the 16-bit PPG mode Temporary latch Transferred in synchronization with channel 1 writing in the 16-bit PPG mode. Channel 1 writing Channel 0 PRLs 228 Data to be written in the channel 1 PRLs Channel 1 PRLs 13.4 Operation of the 8/16-Bit PPG 13.4.6 8/16-Bit PPG Interrupt The 8/16-bit PPG interrupt becomes active when the count reaches the reload value and a borrow occurs. ■ 8/16-Bit PPG Interrupt In the two 8-bit PPG channel mode or 8-bit prescaler and 8-bit PPG mode, an interrupt request is generated from each channel when a borrow occurs in the counter in the channel. In the 16bit PPG mode, PUF0 and PUF1 are simultaneously set when a borrow occurs in the 16-bit counter. To use one interrupt factor only, enabling either PIE0 and PIE1 is recommended. To clear the interrupt factor, clearing PUF0 and PUF1 simultaneously is also recommended. 229 CHAPTER 13 8/16-BIT PPG 13.4.7 Initial Value of Each Hardware Component in the 8/16-Bit PPG This section shows the initial value of each hardware component in the 8/16-bit PPG after a reset. ■ Initial Value of Each Hardware Component in the 8/16-Bit PPG Each hardware component in the 8/16-bit PPG is initialized by a reset as follows. ❍ Registers PPGC0 --> 0X000001B PPGC1 --> 00000001B PPGOE --> XXXXXX00B ❍ Pulse outputs PPG0 --> "L" PPG1 --> "L" PE00 --> Disables the PPG0 output. PE10 --> Disables the PPG1 output. ❍ Interrupt requests IRQ0 --> "L" IRQ1 --> "L" Hardware components other than the above are not initialized. 230 CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER This chapter describes the functions and operations of the 8/16-bit up/down counter/ timer. 14.1 "Overview of the 8/16-Bit Up/Down Counter/Timer" 14.2 "Block Diagram of the 8/16-Bit Up/Down Counter/Timer" 14.3 "Registers of the 8/16-Bit Up/Down Counter/Timer" 14.4 "Count Mode Selection for 8/16-Bit Up/Down Counter/Timer" 14.5 "Reload Function and Compare Function of 8/16-Bit Up/Down Counter/ Timer" 14.6 "Simultaneous Activation of Reload/Compare Functions of 8/16-Bit Up/ Down Counter/Timer" 14.7 "Writing 8/16-Bit Up/Down Counter/Timer Data to UDCR" 231 CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER 14.1 Overview of the 8/16-Bit Up/Down Counter/Timer The 8/16-bit up/down counter/timer consists of six event input terminals, two 8/16-bit up/down counters, two 8-bit reload/compare registers, and a control circuit. ■ Functions of 8/16-Bit Up/Down Counter/Timer The main functions of the 8/16-bit up/down counter/timer are shown below. ❍ Counting range An 8-bit counter register enables counting in the range from 0 to 256 (The operation mode of 16 bits x 1 enables counting in the range from 0 to 65535). ❍ Count mode Four count modes by count clock selection. • Timer mode • Up/down counter mode • Phase difference count mode (2 times) • Phase difference count mode (8 times) ❍ Count clock In timer mode, two internal clocks can be selected for the count clock. • 125 ns (8 MHz: Divided into two) • 1.0 µs (2 MHz: Divided into eight) ❍ Detection edge selection In up/down count mode, a detection edge of the external terminal input signal can be selected. • Edge detection disabled • Falling edge detection • Rising edge detection • Detection of both falling/rising edges ❍ Phase diffence count mode The phase difference count mode is suitable for counting an encoder such as a motor. Inputting phase A of the encoder, phase B, and phase Z output readily enables a high-precision rotation angle, number of rotations, etc. to be counted. ❍ ZIN terminal For the ZIN terminal, two functions can be selected. 232 • Counter clear function • Gate function 14.1 Overview of the 8/16-Bit Up/Down Counter/Timer ❍ Compare and reload function The 8/16-bit up/down counter/timer has a compare function and a reload function that can be used individually or in combination. Starting both functions enables up/down counting at any width. • Compare function (interrupt output at compare) • Compare function (interrupt output and counter clear at compare) • Reload function (interrupt output and reload at underflow) • Compare/reload function (interrupt output and counter clear at compare, interrupt output and reload at underflow) • Compare/reload disabled ❍ Interrupt control At compare, at reload (underflow), and at overflow, interrupt generations can be controlled individually. ❍ Identifying count direction The count direction flag enables the preceding count direction to be identified. ❍ Count direction and interrupt When the count direction changes, an interrupt occurs. 233 CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER 14.2 Block Diagram of the 8/16-Bit Up/Down Counter/Timer Block diagram of 8/16-Bit Up/Down Counter/Timer is shown. ■ Block Diagram of the 8/16-Bit Up/Down Counter/Timer Figure 14.2-1 "Block Diagram of the 8/16-Bit Up/Down Counter/Timer (Ch.0)" is a block diagram of the 8/16-bit up/down counter/timer Ch.0). Figure 14.2-1 Block Diagram of the 8/16-Bit Up/Down Counter/Timer (Ch.0) Internal Data bus 8 bit RCR0 CGE1 CGE0 C/GS (Reload/compare register 0) CTUT Edge/level detection UCRE Reload control RLDE Counter clear UDCC 8 bit UDCR0 (Up/down count register 0) Carry CMPF UDFF OVFF CES1 CES0 CMS1 CMS0 CITE Count clock Up/down count Clock selection Prescaler CLKS 234 UDF1 UDF0 CDCF CFIE CSTR Interrupt output UDIE 14.2 Block Diagram of the 8/16-Bit Up/Down Counter/Timer Figure 14.2-2 "Block Diagram of the 8/16-Bit Up/Down Counter/Timer (Ch.1)" is a block diagram of the 8/16-bit up/down counter/timer (Ch.1). Figure 14.2-2 Block Diagram of the 8/16-Bit Up/Down Counter/Timer (Ch.1) Internal Data bus 8 bit RCR1 (Reload/compare register 1) CGE1 CGE0 C/GS Reload control CTUT Edge/level detection UCRE RLDE Counter clear UDCC 8 bit UDCR1 (Up/down count register 1) CMPF UDFF OVFF CMS1 CMS0 CES1 CES0 EN16 CITE UDIE Carry Count clock Up/down count Clock selection Prescaler UDF1 UDF0 CDCF CFIE CSTR Interrupt output CLKS 235 CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER 14.3 Registers of the 8/16-Bit Up/Down Counter/Timer Figure 14.3-1 "8/16-Bit Up/Down Counter/Timer Register Configuration" shows the registers of the 8/16-bit up/down counter/timer. ■ Registers of the 8/16-Bit Up/Down Counter/Timer Figure 14.3-1 8/16-Bit Up/Down Counter/Timer Register Configuration Reserved area Reserved area Up/Down count register 1 Address: 000071H Read/Write Initial value Up/Down count register 0 Address: 000070H Read/Write Initial value Reload/Compare register 1 Address: 000073H Read/Write Initial value Reload/Compare register 0 Address: 000072H Read/Write Initial value Counter status registers 0/1 Address: 000074H Address: 000078H Read/Write Initial value Higher bits of the counter control register 0 Address: 000077H Read/Write Initial value Higher bits of the counter control register 1 Address: 00007BH Read/Write Initial value Lower bits of the counter control registers 0/1 Address: 000076H Address: 00007AH Read/Write Initial value 236 15 D17 (R) (0) 7 D07 (R) (0) 15 D17 (W) (0) 7 D07 (W) (0) 14 D16 (R) (0) 6 D06 (R) (0) 14 D16 (W) (0) 6 D06 (W) (0) 7 6 CSTR CITE 13 D15 (R) (0) 5 D05 (R) (0) 13 D15 (W) (0) 5 D05 (W) (0) 12 D14 (R) (0) 4 D04 (R) (0) 12 D14 (W) (0) 4 D04 (W) (0) 11 D13 (R) (0) 3 D03 (R) (0) 11 D13 (W) (0) 3 D03 (W) (0) 10 D12 (R) (0) 2 D02 (R) (0) 10 D12 (W) (0) 2 D02 (W) (0) 9 D11 (R) (0) 1 D01 (R) (0) 9 D11 (W) (0) 1 D01 (W) (0) 8 D10 (R) (0) 0 D00 (R) (0) 8 D10 (W) (0) 0 D00 (W) (0) 5 4 3 2 1 0 UDIE CMPF OVFF UDFF UDF1 UDF0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R) (0) (0) (0) (0) (0) (0) (0) 15 14 13 M16E CDCF CFIE 12 11 10 9 Bit No. UDCR1 Bit No. UDCR0 Bit No. RCR1 Bit No. RCR0 Bit No. CSR0,1 (R) (0) 8 CLKS CMS1 CMS0 CES1 CES0 Bit No. CCRH0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 15 14 13 CDCF CFIE (-) (-) 7 12 11 10 9 8 CLKS CMS1 CMS0 CES1 CES0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) 6 5 4 3 2 1 0 CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 (-) (-) Bit No. CCRH1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) Bit No. CCRL0,1 14.3 Registers of the 8/16-Bit Up/Down Counter/Timer 14.3.1 Up/Down Count Register Ch.0/1 (UDCR0/1) The up/down count register is an 8-bit count register that performs up/down count operations according to the internal prescaler or input of the AIN terminal or BIN terminal. ■ Up/Down Count Register Ch.0/1 (UDCR0/1) Figure 14.3-2 Up/Down Count Register Ch.0/1 (UDCR0/1) Up/Down count register 1 Address: 000071H Read/Write Initial value 15 14 13 12 11 10 9 8 Bit No. D17 D16 D15 D14 D13 D12 D11 D10 UDCR1 (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 7 6 5 4 3 2 1 0 Bit No. D07 D06 D05 D04 D03 D02 D01 D00 UDCR0 (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) Up/Down count register 0 Address: 000070H Read/Write Initial value (R) (0) (R) (0) (R) (0) The up/down count register is an 8-bit count register that performs up/down count operations according to the internal prescaler or input of the AIN terminal or BIN terminal. In 16-bit count mode, the up/down count register operates as a 16-bit count register. The value set in the higher 8-bit side of the control register becomes invalid during operation. The up/down count register must be written via RCR. Write the value to be written to this register in the RCR, then write 1 in the CCRL CTUT bit, thereby transferring the value from the RCR to this register (reload by software). To read this register that started in the 16-bit mode, read by word access. 237 CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER 14.3.2 Reload/Compare Register 0/1 (RCR0/1) This register is an 8-bit reload/compare register. This register sets the reload value and compare value. ■ Reload/Compare Register 0/1 (RCR0/1) Figure 14.3-3 Reload/Compare Register 0/1 (RCR0/1) Reload/Compare register 1 Address: 000073H Read/Write Initial value Address: 000072H Read/Write Initial value 15 14 13 12 11 10 D17 D16 D15 D14 D13 D12 (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) 7 6 5 4 3 2 1 0 Bit No. D07 D06 D05 D04 D03 D02 D01 D00 RCR0 (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) (W) (0) 9 8 Bit No. D11 D10 RCR1 (W) (0) (W) (0) (W) (0) (W) (0) This register is an 8-bit reload/compare register that sets the reload value and compare value. The reload value and compare value are the same. Starting the reload function and compare function enables counting up/down between the 00h to RCR values (16-bit operation mode: 0000h to RCR values). This register is write-only and cannot be read. Writing 1 in the CCR0/1 CTUT bit enables the value in this register to be transferred to the UDCR (reload by software). To write this register, use word access. 238 14.3 Registers of the 8/16-Bit Up/Down Counter/Timer 14.3.3 Counter Status Register 0/1 (CSR0/1) The counter status register 0/1 sets the event flag/interrupt operation control for Ch.0/1 in 8-bit mode. ■ Counter Status Register 0/1 (CSR0/1) The configuration of bits of the counter status register Ch.0/1 (CSR0/1) is shown below. Figure 14.3-4 Counter Status Register ch.0/1 (CSR0/1) Counter status registers 0/1 7 Address: 000074H Address: 000078H Read/Write Initial value 6 5 4 3 2 1 0 CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R) (0) (0) (0) (0) (0) (0) (0) Bit No. CSR0,1 (R) (0) [Bit 7] CSTR This bit is for control of start/stop of the UDCR count operation. Table 14.3-1 CSTR (Count Start Bit) CSTR Function 0 Count operation stop (initial value) 1 Count operation start [Bit 6] CITE This bit is for enable/disable control of the interrupt output to the CPU when CMPF is set (compare occurred). Table 14.3-2 CITE (Compare Interrupt Output Control Bit) CITE Function 0 Compare interrupt output disabled (initial value) 1 Compare interrupt output enabled [Bit 5] UDIE This bit is for enable/disable control of the interrupt output to the CPU when OVFF/UDFF is set (overflow/underflow occurred). Table 14.3-3 UDIE (Overflow/Underflow Interrupt Output Control Bit) UDIE Function 0 Overflow/underflow interrupt output disabled (initial value) 1 Overflow/underflow interrupt output enabled 239 CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER [Bit 4] CMPF This flag indicates that the comparison results reveal that the UDCR value and RCR value are equal. Note that this flag is set simultaneously with the start of the counter if the UDCR and RCR values match when the counter starts. Only 0 can be written, but 1 cannot be written. Table 14.3-4 CMPF (Compare Detection Flag) CMPF Function 0 Comparison results did not match (initial value) 1 Comparison results matched [Bit 3] OVFF This flag indicates that an overflow has occurred. Only 0 can be written, but 1 cannot be written. Table 14.3-5 OVFF (Overflow Detection Flag) OVFF Function 0 Overflow did not occur (initial value) 1 Overflow occurred [Bit 2] UDFF This flag indicates that an underflow has occurred. Only 0 can be written, but 1 cannot be written. Table 14.3-6 UDFF (Underflow Detection Flag) UDFF Function 0 Underflow did not occur (initial value) 1 Underflow occurred [Bits 1 to 0] UDF1, UDF0: Up/down flag This bit indicates the preceding count operation (up/down). This bit is read-only and cannot be written. Table 14.3-7 UDF1, UDF0 (Up/Down Flag) 240 UDF1 UDF0 Detection edge 0 0 No input (initial value) 0 1 Down count 1 0 Up count 1 1 Up/down generated simultaneously 14.3 Registers of the 8/16-Bit Up/Down Counter/Timer 14.3.4 Counter Control Register High Ch.0 (CCRH0) The counter control register high Ch.0 sets the Ch.0 operation control in 8-bit mode and sets switching to the 16-bit mode. The operation is set together with CCRL0. ■ Counter Control Register High Ch.0 (CCRH0) The configuration of bits of the counter control register high ch.0 (CCRH0) is shown below. Figure 14.3-5 Higher Bits of Counter Control Register 0 (CCRH0) Higher bits of the counter control register 0 15 14 13 12 11 10 9 8 Address: 000077H M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 Read/Write Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Bit No. CCRH0 [Bit 15] M16E This bit is for selection (switching) of the 8 bits x 2 ch/16 bits x 1 ch operation mode. Table 14.3-8 M16E (16-Bit Mode Enable Setting Bit) M16E 16-bit mode enable setting 0 8 bits x 2 ch operation mode (initial value) 1 16 bits x 1 ch operation mode [Bit 14] CDCF This flag is set when the count direction changes from up to down or down to up during counting. Only 0 can be written, but 1 cannot be written. Table 14.3-9 CDCF (Count Direction Change Flag) CDCF Direction change detection 0 Direction not changed (initial value) 1 Direction changed at least once 241 CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER [Bit 13] CFIE This bit is for controlling an interrupt output to the CPU when the CDCF is set. An interrupt occurs if the count direction changes even once during counting. Table 14.3-10 CFIE (Count Direction Change Interrupt Enable Bit) CFIE Direction change interrupt output 0 Direction change interrupt output disabled (initial value) 1 Direction change interrupt output enabled [Bit 12] CLKS When the timer mode is selected, this bit is for selection of the frequency of the internal prescaler. This bit is valid only in timer mode, and the count direction is down only. Table 14.3-11 CLKS (Internal Prescaler Selection Bit) CLKS Select internal clock 0 2 machine cycles (initial value) 1 8 machine cycles [Bits 11 to 10] CMS1, CMS0 This bit is for selection of the count mode. Table 14.3-12 CMS1, CMS0 (Count Mode Selection Bit) CMS1 CMS0 Count mode 0 0 Timer mode [down count] (initial value) 0 1 Up/down count mode 1 0 Phase difference count mode (2 times) 1 1 Phase difference count mode (4 times) [Bits 9 to 8] CES1, CES0 This bit is for selection of the detection edge of the external terminals AIN and BIN in up/ down count mode. This setting is invalid in modes other than the up/down count mode. Table 14.3-13 CES1, CES0 (Count Clock Edge Selection Bit) 242 CES1 CES0 Selection edge 0 0 Edge detection disabled (initial value) 0 1 Falling edge detection 1 0 Rising edge detection 1 1 Detection of both falling/rising edges 14.3 Registers of the 8/16-Bit Up/Down Counter/Timer 14.3.5 Counter Control Register High Ch.1 (CCRH1) The counter control register high Ch.1 sets the Ch.1 operation control in 8-bit mode. The operation is set together with CCRL1. ■ Counter Control Register High Ch.1 (CCRH1) The configuration of bits of the counter control register high Ch.1 (CCRH1) is shown below. Figure 14.3-6 Higher Bits of Counter Control Register ch.1 (CCRH1) Higher bits of the counter control register 1 15 Address: 00007BH Read/Write Initial value 14 13 12 11 10 9 8 CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 (-) (-) Bit No. CCRH1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) [Bit 15] Unused bit [Bit 14] CDCF This flag is set when the count direction changes from up to down or down to up during counting. Only 0 can be written, but 1 cannot be written. Table 14.3-14 CDCF (Count Direction Change Flag) CDCF Direction change flag 0 Direction not changed (initial value) 1 Direction changed at least once [Bit 13] CFIE This bit is for control of an interrupt output to the CPU when the CDCF is set. An interrupt occurs if the count direction changes even once during counting. Table 14.3-15 CFIE (Count Direction Change Interrupt Enable Bit) CFIE Direction change interrupt output 0 Direction change interrupt output disabled (initial value) 1 Direction change interrupt output enabled [Bit 12] CLKS When the timer mode is selected, this bit is for selection of the internal prescaler frequency. 243 CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER This bit is valid in timer mode only, and the count direction is down only. Table 14.3-16 CLKS (Internal Prescaler Selection Bit) CLKS Select internal clock 0 2 machine cycles (initial value) 1 8 machine cycles [Bits 11 to 10] CMS1, CMS0 This bit is for selection of the count mode. Table 14.3-17 CMS1, CMS0 (Count Mode Selection Bit) CMS1 CMS0 Count mode 0 0 Timer mode [down count] (initial value) 0 1 Up/down count mode 1 0 Phase difference count mode, 2 times 1 1 Phase difference count mode, 4 times [Bits 9 to 8] CES1, CES0 This bit is for selection of the detection edge of the external terminals AIN and BIN in up/ down count mode. This setting is invalid in modes other than the up/down count mode. Table 14.3-18 CES1, CES0 (Count Clock Edge Selection Bit) 244 CES1 CES0 Selection edge 0 0 Edge detection disabled (initial value) 0 1 Falling edge detection 1 0 Rising edge detection 1 1 Detection of both falling/rising edges 14.3 Registers of the 8/16-Bit Up/Down Counter/Timer 14.3.6 Counter Control Register Low Ch.0/1 (CCRL0/1) The counter control register low Ch.0/1 sets the Ch.0/1 operation control in 8-bit mode. The operation is set together with CCRH0/1. ■ Counter Control Register Low Ch.0/1 (CCRL0/1) The configuration of bits of the counter control register low Ch.0/1 (CCRL0/1) is shown below. Figure 14.3-7 Lower Bits of Counter Control Register ch.0/1 (CCRL0/1) Lower bits of the counter control registers 0/1 7 Address: 000076H Address: 00007AH Read/Write Initial value 6 5 4 3 2 1 0 CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 (-) (-) Bit No. CCRL0,1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) [Bit 7] Unused bit [Bit 6] CTUT This bit is for data transfer from the RCR to the UDCR. When 1 is written in this bit, data is transferred from the RCR to the UDCR. Even if written, 0 is invalid. The read value is always 0. 1 must not be written in this bit during counting (when the CSR0 CSTR bit is 1). [Bit 5] UCRE This bit is for control of UDCR clearance by output from compare. This bit affects clearance caused by the output from compare but does not affect the UDCR clear function (as caused by the ZIN terminal). Table 14.3-19 UCRE (UDCR Clear Enable Bit) UCRE Count clear by compare 0 Counter clear disabled (initial value) 1 Counter clear enabled [Bit 4] RLDE This bit is for control of the reload function. The RCR value is transferred to the UDCR if the UDCR generates an underflow when the reload function is active. Table 14.3-20 RLDE (Reload Enable Bit) RLDE Reload function 0 Reload function disabled (initial value) 1 Reload function enabled 245 CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER [Bit 3] UDCC This bit is for clearance of UDCR. When 0 is written in this bit, the UDCR is cleared to 0000H. Even if written, 1 is invalid. The read value is always 1. [Bit 2] CGSC This bit is for selection of the external terminal ZIN function. Table 14.3-21 CGSC (Counter Clear/Gate Selection Bit) CGSC ZIN function 0 Count clear function (initial value) 1 Gate function [Bits 1 to 0] CGE1, CGE0 This bit is for selection of the detection edge/level of the external terminal ZIN. Table 14.3-22 246 CGE1, CGE0 (Counter Clear/Gate Edge Selection Bit) CGE1 CGE0 When the counter clear function is selected When the gate function is selected 0 0 Edge detection disabled (initial value) Level detection disabled (count disable) 0 1 Falling edge Low level 1 0 Rising edge High level 1 1 Setting disabled Setting disabled 14.4 Count Mode Selection for 8/16-Bit Up/Down Counter/Timer 14.4 Count Mode Selection for 8/16-Bit Up/Down Counter/Timer The 8/16-bit up/down counter/timer has four count modes. CCRH CMS1 and CMS0 are used for control of the count mode selection. ■ Count Mode Selection for the 8/16-Bit Up/Down Counter/Timer Table 14.4-1 "Four Count Modes of the 8/16-Bit Up/Down Counter/Timer" shows the four count modes of the 8/16-bit up/down counter/timer. Table 14.4-1 Four Count Modes of the 8/16-Bit Up/Down Counter/Timer CMS1, CMS0 Count mode 00B Timer mode [down count] 01B Up/down count mode 10B Phase difference count mode (2 times) 11B Phase difference count mode (4 times) ❍ Timer mode [down count] In timer mode, internal prescaler output is counted down. For the internal prescaler, 2 machine cycles/8 machine cycles can be selected through CCRH CLKS. ❍ Up/down count mode In up/down count mode, inputs of external terminals AIN and BIN are counted to count up/down. AIN terminal inputs control counting up. BIN terminal inputs control counting down. AIN terminal and BIN terminal inputs are edge detection. Detection edges can be selected through CCRH CES1 and CES0. Table 14.4-2 "Detection Edge Selection of the 8/16-Bit Up/ Down Counter/Timer" shows the detection edges. Table 14.4-2 Detection Edge Selection of the 8/16-Bit Up/Down Counter/Timer CES1, CES0 Detection edge 00B Edge detection disabled 01B Falling edge detection 10B Rising edge detection 11B Detection of both falling/rising edges ❍ Phase difference count mode (2 times/4 times) In phase difference count mode, when the AIN terminal input edge is detected, the BIN terminal input level is detected to count the phase difference between phase A and phase B of the encoder output signal. When the BIN terminal input edge is detected, the AIN terminal input level is detected to count the phase difference between phase A and phase B of the encoder output signal. In 2 times/4 times mode, if AIN is earlier, the phase difference between phase A and phase B is 247 CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER counted up. If BIN is earlier, the phase difference between phase A and phase B is counted down. In 2 times mode, the AIN terminal value is detected to count in timings of both BIN terminal rising/falling edges. Counting is performed as follows: • When the value of the AIN terminal detected by the BIN terminal rising edge is "H", the counter is counted up. • When the value of the AIN terminal detected by the BIN terminal rising edge is "L", the counter is counted down. • When the value of the AIN terminal detected by the BIN terminal falling edge is "H", the counter is counted down. • When the value of the AIN terminal detected by the BIN terminal falling edge is "L", the counter is counted up. Figure 14.4-1 "Overall Operation in Phase Difference Count Mode (2 Times)" shows the overall operation in phase difference count mode (2 times). Figure 14.4-1 Overall Operation in Phase Difference Count Mode (2 Times) AIN terminal BIN terminal Count value 0 +1 1 +1 2 +1 3 +1 4 +1 5 -1 4 +1 5 -1 4 -1 3 -1 2 -1 1 -1 0 In 4 times mode, the AIN terminal value is detected to count in timings of both BIN terminal rising/falling edges. The BIN terminal value is detected to count in timings of both AIN terminal rising/falling edges. Counting is performed as follows: • When the value of the AIN terminal detected by the BIN terminal rising edge is "H", the counter is counted up. • When the value of the AIN terminal detected by the BIN terminal rising edge is "L", the counter is counted down. • When the value of the AIN terminal detected by the BIN terminal falling edge is "H", the counter is counted down. • When the value of the AIN terminal detected by the BIN terminal falling edge is "L", the counter is counted up. • When the value of the BIN terminal detected by the AIN terminal rising edge is "H", the counter is counted down. • When the value of the BIN terminal detected by the AIN terminal rising edge is "L", the counter is counted up. • When the value of the BIN terminal detected by the AIN terminal falling edge is "H", the counter is counted up. • When the value of the BIN terminal detected by the AIN terminal falling edge is "L", the counter is counted down. Figure 14.4-2 "Overall Operation in Phase Difference Count Mode (4 Times)" shows the overall operation in phase difference count mode (4 times). 248 14.4 Count Mode Selection for 8/16-Bit Up/Down Counter/Timer Figure 14.4-2 Overall Operation in Phase Difference Count Mode (4 Times) AIN terminal BIN terminal Count value 0 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 1 2 3 4 5 6 7 8 9 10 -1 9 +1 10 -1 9 -1 8 -1 -1 -1 7 6 5 -1 4 -1 -1 -1 3 2 1 When the encoder output is counted, inputting phase A in the AIN terminal, phase B in the BIN terminal, and phase Z in the ZIN terminal enables a high-precision rotation angle, number of rotations, etc. to be detected. Note: When this count mode is selected, detection edge selection by CCRH CES1, CCRH CES0, CCRL CGE1, and CCRL CGE0 is invalid. 249 CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER 14.5 Reload Function and Compare Function of 8/16-Bit Up/ Down Counter/Timer The 8/16-bit up/down counter/timer has a reload function and a compare function that can be combined for processing. ■ Reload Function and Compare Function of the 8/16-Bit Up/Down Counter/Timer Table 14.5-1 "Selection of Reload/Compare Functions of 8/16-Bit Up/Down Counter/Timer" shows the settings that can be selected for the reload/compare functions of the 8/16-bit up/down counter/timer. Table 14.5-1 Selection of Reload/Compare Functions of 8/16-Bit Up/Down Counter/Timer RLDE, UCRE Reload/compare functions 00B Reload/compare disabled (initial value) 01B Compare enabled 10B Reload enabled 11B Compare/reload enabled ❍ Reload function When the reload function is active, the RCR value is transferred to the UDCR in the next timing of the down count clock after underflow generation. UDFF is set and an interrupt request is generated. Note: In a mode that does not perform a counting down operation, starting this function is invalidated. Figure 14.5-1 "Overall Operation of the Reload Function" shows the overall operation of the reload function. 250 14.5 Reload Function and Compare Function of 8/16-Bit Up/Down Counter/Timer Figure 14.5-1 Overall Operation of the Reload Function (0FFFF ) 0FF Reload, interrupt generation Reload, interrupt generation RCR 00 Underflow Underflow ❍ Compare function The compare function can be used in all modes except the timer mode. With the compare function active, when the RCR and UDCR values match, the CMPF is set and an interrupt request is generated. When the compare clear function is active, the UDCR is cleared in the next timing of the up count clock. Note: In the mode that does not perform counting up, starting this function is invalidated. Figure 14.5-2 "Overall Operation of the Compare Function" shows the overall operation of the compare function. Figure 14.5-2 Overall Operation of the Compare Function (0FFFF ) 0FF Compare and match Compare and match RCR 0000 Counter cleared, interrupt generation Counter cleared, interrupt generation 251 CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER 14.6 Simultaneous Activation of Reload/Compare Functions of 8/ 16-Bit Up/Down Counter/Timer When the reload/compare functions are simultaneously activated, counting up/down is enabled in any width. ■ Simultaneous Activation of Reload/Compare Functions of 8/16-Bit Up/Down Counter/Timer The reload function that starts at underflow transfers the RCR value to the UDCR. The compare function that starts when the RCR and UDCR values match clears the UDCR. These two functions are used for counting up/down between the 00H to RCR values. Figure 14.6-1 "Overall Operation when the Reload/Compare Functions are Activated Simultaneously" shows the overall operation when the reload/compare functions are activated simultaneously. Figure 14.6-1 Overall Operation when the Reload/Compare Functions are Activated Simultaneously FFFF Compare and match Compare and match Counter cleared Counter cleared Reload Reload Reload Compare and match RCR 0000 Underflow Underflow Underflow Counter cleared When comparison matches or at reloading (underflow), an interrupt can be generated in the CPU. Enabling these interrupt outputs can be controlled individually. The timing for reloading to the UDCR or clearing the UDCR differs depending on whether counting is active or stopped. ❍ Reload/Clear timing during count operation If a reload or clear event occurs during count operation, all events synchronize with the count clock. (Figure 14.6-2 "Reload/Clear Timing during Count Operation" is an example of reloading 80h.) 252 14.6 Simultaneous Activation of Reload/Compare Functions of 8/16-Bit Up/Down Counter/Timer Figure 14.6-2 Reload/Clear Timing during Count Operation Reload/clear event Synchronizes with this clock Count clock ❍ Count value at count disable after reload clear If reload and clear events occur during a count operation and counting stops while waiting for a count clock synchronization, reload and clear are performed when the counter stops. (Figure 14.6-3 "Count Value at Count Disable after Reload Clear" is an example of reloading 80h.) Figure 14.6-3 Count Value at Count Disable after Reload Clear Reload/clear event Count clock Count enable Enable (count enabled) Disable (count disabled) ❍ Reload/clear timing when counting is stopped If reload and clear events occur when counting is stopped, reload and clear are performed when the events occur. (Figure 14.6-4 "Reload/Clear Timing when Counting is Stopped" is an example of reloading 80h.) Figure 14.6-4 Reload/Clear Timing when Counting is Stopped Reload/clear event Regarding clear by comparison, clearance is performed when the UDCR and RCR values match and the counter is counted up. Clearance is not performed even if the UDCR and RCR values match when the counter is counted down or stopped. The clear timing in all events except reset input conform to the above timing. The reload timing in all events conform to the above timing. When a clear event and reload event occur synchronously, priority is given to the clear event. 253 CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER 14.7 Writing 8/16-Bit Up/Down Counter/Timer Data to UDCR Data cannot be written to the UDCR directly from a data bus. To write data in the UDCR, proceed as follows: 1. Write data to be written to UDCR in RCR. (Note that RCR data will be lost.) 2. Writing 1 in the CCRH CTUT enables the data to be transferred from the RCR to the UDCR. Perform the above operation when the counter is stopped (when the CSR CSTR bit is 0). ■ Writing Data to UDCR To clear the counter, the following methods in addition to the above are available. • To clear by reset input (initialize) • To clear by edge input from the ZIN terminal • To clear by writing 0 in CCRH UDCC • To clear by the compare function This writing can be performed regardless of whether counting is active/stopped. ■ Count Clear/Gate Function The ZIN terminal can be selected in the CCRH CGSC and can be used as the count clear function or gate function as shown below. Table 14.7-1 Selection of ZIN Terminal Functions CGSC ZIN terminal function 0B Counter clear function 1B Gate function When the count clear function is active, the counter is cleared according to the edge input from the ZIN terminal. The edge of the ZIN terminal input signal to clear the counter is selected in CCRL CGE1 and CGE0. If this function inputs the encoder Z phase output to this terminal, the UDCR can be cleared at the count start point of the encoder. When the gate function is active, counting is enabled/disabled according to the level input from the ZIN terminal. The level of the ZIN terminal input signal to enable counting is selected in CCRL CGE1 and CGE0. This function is usable in all count modes. 254 14.7 Writing 8/16-Bit Up/Down Counter/Timer Data to UDCR Table 14.7-2 "Selection of Detection Edge by ZIN Terminal Input Signal" shows the selection of ZIN terminal functions. Table 14.7-2 Selection of Detection Edge by ZIN Terminal Input Signal CGE1,C GE0 Counter clear function Gate function 00B Detection disabled Detection disabled 01B Rising edge LOW level 10B Falling edge HIGH level ■ Count Direction Flag, Count Direction Change Flag The count direction flag (UDF1, UDF0) indicates whether the preceding count was counted up or down during counting up/down. The count clock generated from inputs of both AIN and BIN terminals is used for judgment and the flag is rewritten at each counting. The current rotation direction for motor control can be determined from this flag. This function is usable in all count modes. Table 14.7-3 "Count Direction Flag" shows the count direction flag. Table 14.7-3 Count Direction Flag UDF1, FDF0 Count direction 01B Count down 10B Count up 11B Up/down occur simultaneously (count operation is not performed) The count direction change flag (CDCF) is set when the count direction changes from up to down or down to up. When this flag is set, an interrupt occurs in the CPU simultaneously. Referencing this interrupt and the count direction flag (UDF1, UDF0) enables a change in count direction. However, note that the direction indicated by the flag following a direction change may be restored to the original direction if direction changes occur continuously at short intervals. Table 14.7-4 "Count Direction Change Flag" shows the count direction change flag. Table 14.7-4 Count Direction Change Flag CDCF Count direction change detection 0B Direction not changed 1B Direction changed (once or more) ■ Compare Detection Flag The compare detection flag (CMPF) is set when the UDCR value and RCR value become equal during a count operation. This flag is also set when the values match by counting up, when the values match by the generation of a reload event, and when the values already match at the start of a counting. However, even if the values match as a result of counting down (except for compare during a reload following an underflow), the results of comparing these values reveal that they are not equivalent, in which case the flag is not set. 255 CHAPTER 14 8/16-BIT UP/DOWN COUNTER/TIMER ■ 8 Bits × 2 Ch, 16 Bits × 1 Ch Operation This module can be used as an 8-bit up/down counter × 2 ch or 16-bit up/down counter × 1 ch. Writing 0 in the M16E bit of the CCRH0 register sets this module to the 8 bits × 2 ch mode. Writing in the M16E bit of the CCRH0 register sets this module to the 16 bits × 1 ch mode. In 16 bits × 1 ch mode, the CSR0, CCRL0, and CCRH0 registers become valid and the CSR1, CCRL1, and CCRH1 registers cannot be used. The AIN0, BIN0, and ZIN0 terminals become valid input terminals and AIN1, BIN1, and ZIN1 terminals are not used. 256 CHAPTER 15 DTP/EXTERNAL INTERRUPT This chapter describes the functions and operations of the DTP/external interrupt. 15.1 "Overview of the DTP/External Interrupt" 15.2 "Registers of the DTP/External Interrupt" 15.3 "Operation of the DTP/External Interrupt" 15.4 "Notes on Using the DTP/External Interrupt" 257 CHAPTER 15 DTP/EXTERNAL INTERRUPT 15.1 Overview of the DTP/External Interrupt DTP is a peripheral circuit for activating the intelligent I/O service or external interrupt processing. ■ DTP and External Interrupt The DTP is installed between a peripheral circuit outside the device and the F2MC-16LX CPU. The DTP receives a DMA request or an interrupt request from the external peripheral circuit (*1) and posts the request to the F2MC-16LX CPU to activate the intelligent I/O service or external interrupt processing. For the intelligent I/O service, H and L can be selected to indicate the request level. For external interrupt processing, H, L, rising edge, and falling edge can be selected. Although a request indicated by a level cannot be input to ch0 and ch1, both edges can be input. *1 Peripheral function device to be connected outside an MB90570 series device Note: Ch0 and ch1 cannot be used for the intelligent I/O service. ■ Block Diagram of the DTP/External Interrupt Figure 15.1-1 Block Diagram of DTP/External Interrupt Internal Data Bus 4 4 DTP/Interrupt enable register Gate Source F/F 4 DTP/interrupt source register 8 Request level setting register 258 Edge detection circuit 4 Request input 15.2 Registers of the DTP/External Interrupt 15.2 Registers of the DTP/External Interrupt There are the following three types of DTP/External interrupt registers: • DTP/interrupt enable register (ENIR) • DTP/interrupt source register (EIRR) • Request level setting register (ELVR) ■ Registers of the DTP/External Interrupt Figure 15.2-1 DTP/External Interrupt Register DTP/interrupt enable register Address: 000030H DTP/interrupt source register Address: 000031H Read/Write Initial value Address: 000032H Read/Write Initial value 5 4 3 2 1 0 Bit No. EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 ENIR 15 14 13 12 11 10 9 8 Bit No. ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 EIRR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Request level setting register Address: 000033H 6 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Read/Write Initial value Read/Write Initial value 7 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 Bit No. (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 Bit No. LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 ELVR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 259 CHAPTER 15 DTP/EXTERNAL INTERRUPT 15.2.1 DTP/Interrupt Enable Register (ENIR) This register specifies device pins to be used as DTP/external interrupt request input pins to issue a request to the interrupt controller. ■ DTP/Interrupt Enable Register (ENIR) Figure 15.2-2 DTP/Interrupt Enable Register (ENIR) DTP/interrupt enable register 7 Address: 000030H Read/Write Initial value EN7 6 EN6 5 EN5 4 EN4 3 EN3 2 EN2 1 EN1 0 EN0 Bit No. ENIR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) If the pin corresponding to a bit of this register is set to 1, the pin is used as an DTP/external interrupt input pin and generates a request to the interrupt controller. If the pin corresponding to a bit of this register is set to 0, the pin holds an DTP/external interrupt request input source but does not generate a request to the interrupt controller. 260 15.2 Registers of the DTP/External Interrupt 15.2.2 DTP/Interrupt Source Register (EIRR) This register indicates there is a corresponding DTP/external interrupt request during a read operation and clears the flip-flop contents indicating the request during a write operation. ■ DTP/Interrupt Source Register (EIRR) Figure 15.2-3 DTP/Interrupt Source Register (EIRR) DTP/interrupt source register Address: 000031H Read/Write Initial value 15 14 13 12 11 10 ER7 ER6 ER5 ER4 ER3 ER2 9 ER1 8 ER0 Bit No. EIRR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) If this register is read and a bit of this register is set to "1", the corresponding pin indicates an DTP/external interrupt request. Writing "0" in a bit of this register clears the request flip-flop corresponding to the bit. Writing "1" does not effect an operation. During the read of a readmodify-write operation, "1" is read. 261 CHAPTER 15 DTP/EXTERNAL INTERRUPT 15.2.3 Request Level Setting Register (ELVR) This register selects request detection conditions. ■ Request Level Setting Register (ELVR) Figure 15.2-4 Request Level Setting Register (ELVR) Request level setting register Address: 000033H Read/Write Initial value Address: 000032H Read/Write Initial value 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 Bit No. (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 Bit No. ELVR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Two bits are assigned per pin. Table 15.2-1 "Operation of External Level Register (ELVR) (LA2 to LA7, LB2 to LB7)" describes the correspondence between detection conditions and LA2 to LA7 and LB2 to LB7. Table 15.2-2 "Operation of External Level Register (ELVR) (LA0 to LA1, LB0 to LB1)" describes the correspondence between detection conditions and LA0 to LA1 and LB1 to LB1. If an input representing a request level is cleared but the input remains active, the condition is set again. Table 15.2-1 Operation of Request Level Setting Register (ELVR) (LA2 to LA7, LB2 to LB7) 262 LBx LAx Operation 0 0 Request detection at L level 0 1 Request detection at H level 1 0 Request detection at rising edge 1 1 Request detection at falling edge 15.2 Registers of the DTP/External Interrupt Table 15.2-2 Operation of Request Level Setting Register (ELVR) (LA0 to LA1, LB0 to LB1) LBx LAx Operation 0 0 Request detection at both edges 0 1 Request not detected 1 0 Request detection at rising edge 1 1 Request detection at falling edge 263 CHAPTER 15 DTP/EXTERNAL INTERRUPT 15.3 Operation of the DTP/External Interrupt The DTP /external interrupt contains the external interrupt function and the DTP function, both of which are explained in this section. ■ Operation of the DTP/External Interrupt When a request set in a corresponding pin by the ELVR register is input after the external interrupt request is set, this resource generates an interrupt request signal for the interrupt controller. The priorities of interrupts that occurred concurrently are checked in the interrupt controller. If the interrupt from this resource has the highest priority, the interrupt controller generates an interrupt request for the F2MC-16LX CPU. The F2MC-16LX CPU compares the interrupt request with the ILM bit in the CCR register in the CPU. If the request level is higher than the ILM bit value, the CPU activates the hardware interrupt processing microprogram when the instruction being executed terminates. Figure 15.3-1 "External Interrupt Operation" shows the operation of an external interrupt. Figure 15.3-1 External Interrupt Operation DTP/External interrupt ELVR EIRR ENIR Source Another request F MC-16LX CPU Interrupt controller ICR IL yy CMP ICR xx CMP ILM NTA The CPU reads ISE bit information from the interrupt controller in the hardware interrupt processing microprogram to confirm that the request is interrupt processing. The CPU then branches control to the interrupt processing microprogram. The interrupt processing microprogram reads an interrupt vector area and generates interrupt acknowledge to the interrupt controller. The microprogram transfers the jump destination address of a microinstruction generated from the vector to the program counter and executes the user interrupt processing program. ■ DTP Operation As initialization, to activate the intelligent I/O service, the user program sets addresses of registers allocated to 000000H to 0000FFH in the I/O address pointer in the extended intelligent I/O service descriptor and sets the head address of the memory buffer in the buffer address pointer. The DTP operation sequence is exactly the same as that of external interrupts up to the step in which the CPU activates the hardware interrupt processing microprogram. For the DTP, because the ISE bit that is read by the CPU during the hardware interrupt processing that is done by the microprogram indicates the DTP, control is passed to the extended intelligent I/O service processing microprogram. When the intelligent service is activated, a read or a write signal is sent to the addressed external peripheral circuit to switch data with the chip. The external peripheral circuit should cancel the interrupt request to the chip within three machine cycles after data transfer. After completion of data switching, the descriptor is updated and a signal to clear the transfer source is generated by the interrupt controller. The resource receives the signal and clears the flip-flop holding the source for the next request from a pin. 264 15.3 Operation of the DTP/External Interrupt See the "F2MCR-16LX Programming Manual" for more information on extended intelligent I/O service processing. Figure 15.3-2 External Interrupt Cancel Timing at Termination of DTP Operation Request by edge or H-level Interrupt source Internal operation Descriptor select and read Address bus pin When the extended intelligent I/O service is transferred from I/O register to memory Read address Write address Read data Data bus pin Write data Read signal Write signal Canceled within three machine cycles Data, address bus Internal Data Bus Register External peripheral circuit Figure 15.3-3 Outline of an Interface between a DTP and an External Peripheral Circuit Canceled within three machine cycles after data transfer ■ Switching between DTP Request and External Interrupt Request Switching between DTP requests and external interrupt requests is performed in accordance with corresponding ISE bit settings of the ICR register in the interrupt controller. An ICR is allocated to each pin. If the ISE bit of the corresponding ICR is set to 1, it is assumed that the pin treats a DTP request. If the bit is set to 0, it is assumed that the pin treats an external interrupt request. 265 CHAPTER 15 DTP/EXTERNAL INTERRUPT Figure 15.3-4 Switching between DTP Request and External Interrupt Request Interrupt controller Pin DTP/External interrupt External interrupt 266 15.4 Notes on Using the DTP/External Interrupt 15.4 Notes on Using the DTP/External Interrupt Note the following when using DTP/external interrupts. • Conditions of peripheral circuits connected externally when the DTP is used • Return from standby state • Operation procedure of DTP/external interrupt • External interrupt request level ■ Conditions of peripheral circuits connected externally when the DTP is used The DTP can support external peripheral circuits that automatically clear requests after completion of transfer. The request must be canceled within three machine cycles (defined temporarily) after a transfer operation starts. Otherwise, this resource assumes the current request to be the next transfer request. ■ Return from Standby State ❍ Return from standby state (MB90V570, MB90F574, MB90573, MB90574) If an external interrupt is used for a return from the standby state in input clock stop mode, set the request level to "H" level. If the external interrupt request is set to "L" level, a malfunction may occur. The standby state in input clock stop mode does not return if an edge of the external interrupt request is set. ❍ Return from standby state (MB90V570A, MB90F574A, MB90574C) If an external interrupt is used for a return from the standby state in input clock stop mode, select an "H" level or "L" level request for ch2 to ch7 and an edge request for ch0 and ch1. ■ Operation procedure of DTP/external interrupt When using registers in DTP/external interrupts, set the registers as follows: 1. Disable the bit associated with the DTP/interrupt enable register (ENIR). 2. Set the bit associated with the external level register (ELVR). 3. Enable the bit associated with the DTP/external interrupt request register (EIRR). 4. Enable the bit associated with the enable register. (However, for (3) and (4), concurrent writing with word specification is enabled.) When registers in this resource are set, the ENIR register must be placed in the disable state. The ENIR register must be cleared before the ENIR register is placed in the enable state. This processing is required to prevent an interrupt source from occurring at register setting or in the interrupt enable state. ❍ External interrupt request level • If the request level is set to an edge level, at least three machine cycles are required for the pulse width to detect an edge. • When the request input level is set to the detection level, a request to the interrupt controller remains active because an internal source hold circuit is installed, as shown Figure 15.4-1 267 CHAPTER 15 DTP/EXTERNAL INTERRUPT "Clear Operation of the Source Hold Circuit at Level Setting", even if an external request input is received and then canceled. To cancel the request, the external interrupt request flag bit and then the source hold circuit must be cleared as shown in Figure 15.4-2 "Interrupt Source and Interrupt Request to the Interrupt Controller When an Interrupt Is Enabled". Figure 15.4-1 Clear Operation of the Source Hold Circuit at Level Setting Interrupt source Level detection Source F/F (source hold circuit) Enable gate To the interrupt controller Holds the source until the circuit is cleared. Figure 15.4-2 Interrupt Source and Interrupt Request to the Interrupt Controller When an Interrupt Is Enabled "H" level Interrupt source Interrupt request to the interrupt controller Inactivated when the source F/F is cleared. 268 CHAPTER 16 DELAYED INTERRUPT REQUESTING MODULE This chapter describes the functions and operations of the delayed interrupt requesting module. 16.1 "Overview of the Delayed Interrupt Requesting Module" 16.2 "Operation of the Delayed Interrupt Requesting Module" 269 CHAPTER 16 DELAYED INTERRUPT REQUESTING MODULE 16.1 Overview of the Delayed Interrupt Requesting Module The delayed interrupt requesting module is used for generating an interrupt request for task-switching. Using this module, software can be used to generate or cancel the interrupt request to the F2MC-16LX CPU. ■ Block Diagram of the Delayed Interrupt Requesting Module Figure 16.1-1 "Block Diagram of the Delayed Interrupt Requesting Module" shows a block diagram of the delayed interrupt requesting module. Figure 16.1-1 Block Diagram of the Delayed Interrupt Requesting Module Internal Data Bus Delayed interrupt source generation/ release decoder Source latch ■ Register of the Delayed Interrupt Requesting Module The register configuration of the delayed interrupt requesting module [delayed interrupt source generation/release register (DIRR: Delayed Interrupt Request Register)] is shown below. The DIRR is a register that controls the generation and release of a delayed interrupt request. A delayed interrupt request is generated when 1 is written to this register, while the delayed interrupt request is released when 0 is written. The source is released at reset. Although either 0 or 1 can be written to the reserved area, it is recommended to use a set bit or clear bit command to access this register if future extension is expected. Figure 16.1-2 Delayed Interrupt Source Generation/Release Register (DIRR) Delayed interrupt source generation/release register 15 14 13 12 11 10 9 Address: 00009FH Read/Write Initial value 270 8 R0 (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (R/W) (0) Bit No. DIRR 16.2 Operation of the Delayed Interrupt Requesting Module 16.2 Operation of the Delayed Interrupt Requesting Module When the CPU writes 1 to the corresponding bit of the DIRR through software, a request latch in the delayed interrupt requesting module is set and an interrupt request is generated in the interrupt controller. When other interrupt requests have a lower priority over this interrupt or no other interrupt request is generated, the interrupt controller generates an interrupt request for the F2MC-16LX CPU. ■ Operation of the Delayed Interrupting Requesting Module The F2MC-16LX CPU compares the ILM bit of its internal CCR register and the interrupt request. If the interrupt level is higher than the ILM bit, the CPU starts the hardware interrupt processing microprogram upon completion of the command currently executed. As a result, the interrupt processing routine for this interrupt is executed. This interrupt source is cleared and tasks are switched by writing 0 to the corresponding bit of the DDIR in the interrupt processing routine. Figure 16.2-1 "Operation of the Delayed Interrupting Requesting Module" shows the operation of the delayed interrupting requesting module. Figure 16.2-1 Operation of the Delayed Interrupting Requesting Module Delayed interrupting requesting module Interrupt controller F2MC-16LX CPU Other requests ICR IL CMP DDIR ICR CMP ILM NTA ■ Precaution for Using Delayed Interrupting Requesting Module ❍ Delayed interrupting request latch Because this latch is set by writing 1 to the corresponding bit of the DIRR and released by writing 0 to the same bit, software must be created to clear the source in the interrupt processing routine; otherwise re-interrupt processing is started upon recovery from interrupt processing. 271 CHAPTER 16 DELAYED INTERRUPT REQUESTING MODULE 272 CHAPTER 17 A/D CONVERTER This chapter describes the functions and operations of the A/D converter. 17.1 "Overview of the A/D Converter" 17.2 "Registers of the A/D Converter" 17.3 "Operation of the A/D Converter" 17.3 "Notes on Using the A/D Converter" 17.4 "Conversion Data Protection Function" 273 CHAPTER 17 A/D CONVERTER 17.1 Overview of the A/D Converter An A/D converter converts analog input voltage to a digital value. ■ Overview of the A/D Converter The A/D converter has the following characteristics: ❍ Conversion time: 26.3 µs ❍ Sampling time: 64 to 4096 machine cycles per channel (4 µs minimum to 256 µs ) can be selected. (The conversion time and sampling time indicate the values when the machine cycle frequency is 16 MHz.) ❍ Compare time: 176 to 352 machine cycles per channel (Use the 176 machine cycles of the compare time when the machine clock frequency is up to 8 MHz.) ❍ The RC successive approximation mode with a sample hold circuit is used. ❍ A resolution of between eight and ten bits can be selected. ❍ The analog inputs are selected among eight channels by a program. • Single conversion mode: Selects one channel and converts the analog input. • Scan conversion mode: Converts the analog inputs from multiple contiguous channels. Up to eight channels can be programmed. • Continuous conversion mode: repeatedly. • Stop and conversion mode: After converting the analog input from one channel, temporarily stops and waits for the next activation (start of conversion can be synchronized). Converts the analog input from the specified channel ❍ At the end of A/D conversion, an interrupt request indicating the end of A/D conversion can be generated for CPU. EI2OS can be activated by generating this interrupt to transfer A/D conversion result data to memory. Use of interrupts is suitable for continuous processing. ❍ The activation factor can be selected among software, the external trigger (falling edge), and the timer (rising edge). 274 17.1 Overview of the A/D Converter ■ Block Diagram of the A/D Converter Figure 17.1-1 Block Diagram of the A/D Converter H, L Successive approximation register Comparator Decoder Sample hold circuit Internal Data Bus Input circuit D/A converter Data register A/D control register 1 A/D control register 2 Activation by the trigger PPG timer 1 Activation by the timer Operating clock Prescaler 275 CHAPTER 17 A/D CONVERTER 17.2 Registers of the A/D Converter Figure 17.2-1 "Registers for A/D Converter" shows the A/D converter registers. ■ Registers of the A/D Converter Figure 17.2-1 Registers of the A/D Converter Higher control status register Address:000037H Read/write Initial value 15 Read/write Initial value Higher data register Address:000039H Read/write Initial value 12 11 10 9 INTE PAUS STS1 STS0 Bit number 8 STRT Reserved ADCS2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 7 MD1 6 MD0 5 4 3 2 1 0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 Bit number ADCS1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 15 14 13 12 11 DSEL ST1 ST0 CT1 CT0 (W) (0) (W) (0) (W) (1) (W) (0) (W) (0) 10 (-) (-) 9 8 D9 D8 (-) (X) (-) (X) Bit number ADCR2 Lower data register 7 6 5 4 3 2 1 0 Address:000038H D7 D6 D5 D4 D3 D2 D1 D0 (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) (R) (X) Read/write Initial value 276 13 BUSY INT Lower control status register Address:000036H 14 Bit number ADCR1 17.2 Registers of the A/D Converter 17.2.1 Control Status Register (ADCS1, ADCS2) The control status register (ADCS1, ADCS2) controls the A/D converter and indicates the status. ■ ADCS1 and ADCS2 (Control Status Registers) Figure 17.2-2 ADCS1 and ADCS2 (Control Status Register) Higher control status register 15 14 13 12 11 10 9 Address:000037H Read/write Initial value 8 Bit number Reserved (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 7 Lower control status register 6 5 4 3 2 1 0 Address:000036H Read/write Initial value ADCS2 Bit number ADCS1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) Note: Do not rewrite ADCS1 during A/D conversion. [Bit 15] Busy flag and stop (BUSY) This bit indicates respectively controls A/D converter operations. During the read operation: When this bit is "0", this indicates termination of A/D conversion, if it is "1", A/D conversion is executed. During the write operation: When this bit is set to "0" during A/D operation, the A/D operation is forcibly terminated. This can be used for forcible termination in continuous or stop mode. However, this indicator bit cannot be set to "1". Executing an RMW instruction enables the reading of "1". In single mode, this bit is cleared when A/D conversion ends. In continuous or stop mode, the bit is not cleared until the operation is stopped by setting the bit to "0". Note: Do not perform the forced stop simultaneously with the soft activation (BUSY is set to "0" while STRT is set to "1"). [Bit 14] Interrupt (INT) When conversion data is written to the data register (ADCR), this bit is set to "1". When the INTE bit is "1", setting this bit to "1" generates an interrupt request. If EI2OS activation is enabled, EI2OS is activated, and setting this bit to "1" has no effect. This bit is cleared by writing "0" or by the EI2OS interrupt clear signal. Note: Clear this bit by writing "0" when the A/D converter stops. 277 CHAPTER 17 A/D CONVERTER [Bit 13] Interrupt enable (INTE) This bit specifies whether to enable or disable an interrupt at the end of conversion. When EI2OS is to be used, set this bit to "1". EI2OS is designed to be activated when an interrupt request is generated. Table 17.2-1 Function of INTE Bit (Interrupt Enabled/Disabled Specification Bit) INTE Function 0 Disables the interrupt. [Initial value] 1 Enables the interrupt. [Bit 12] A/D converter pause (PAUS) This bit is set to "1" when A/D conversion stops temporarily. Because there is only one register for storing the A/D conversion result, if the conversion result is not transferred using EI2OS, the previous data is destroyed. To avoid losing such data, the A/D converter is designed so that the next conversion data is not stored unless the contents of the data register are transferred using EI2OS. In this status, A/D conversion stops. When the transfer using EI2OS is complete, the A/D converter restarts conversion. Note: This bit is valid only when EI2OS is used. See the section 17.5 "Conversion Data Protection Function". [Bits 11 and 10] Start source select (STS1 and STS0) The A/D activation factor is selected according to the setting of these bits. Table 17.2-2 Functions of the Bits STS1 and STS0 (A/D Activation Source Selection Bits) STS1 STS0 Function 0 0 Activated by software. [Initial value] 0 1 Activated by the external pin trigger and software. 1 0 Activated by the timer and software. 1 1 Activated by the external pin trigger, timer, and software. In the mode in which there are multiple activation factors, the A/D converter is activated by the first factor that occurs. The activation factor is changed at the same time that these bits are rewritten. When these bits are required to be rewritten during A/D converter operation, rewrite the bits when no target conversion activation factor occurs. For the external pin trigger, the falling edge is detected. If the external trigger input level is "L", rewriting these bits to set activation by the external pin trigger may activate the A/D converter. When the timer is selected, the output of the 16-bit reload timer 1 is used. [Bit 9] Start (STRT) Writing "1" in this bit activates the A/D converter. 278 17.2 Registers of the A/D Converter To reactivate the A/D converter, write "1" in this bit again. In the stop mode, the A/D converter is not reactivated for operational reasons. Note: Do not perform the forced stop simultaneously with the soft activation (BUSY is set to 0 while STRT is set to 1). [Bit 8] Reserved bit. Write "0" in this bit. [Bits 7 and 6] A/D converter mode set (MD1 and MD0) These bits set the operating mode. Table 17.2-3 MD1, MD0 Operating Mode MD1 MD0 Operating mode 0 0 Single mode. Reactivation during operation is always enabled. [Initial value] 0 1 Single mode. Reactivation during operation is disabled. 1 0 Continuous mode. Reactivation during operation is disabled. 1 1 Stop mode. Reactivation during operation is disabled. Single mode: Continues A/D conversion starting with the channel set by ANS2 to ANS0 and ending with the channel set by ANE2 to ANE0, and stops when a single A/D conversion is completed. Continuous mode: Repeats A/D conversion starting with the channel set by ANS2 to ANS0 and ending with the channel set by ANE2 to ANE0. Stop mode: Performs A/D conversion starting with the channel set by ANS2 to ANS0 and ending with the channel set by ANE2 to ANE0 and temporarily stops when A/D conversion for each channel is completed. Conversion is restarted when an activation factor occurs. Note: When A/D conversion is activated in the continuous or stop mode, it continues until stopped by the BUSY bit. Writing "0" in the BUSY bit stops A/D conversion. In the mode in which reactivation during operation is disabled (single, continuous, or stop mode), the A/D converter cannot be activated by an activation factor (timer, external trigger, or software). [Bits 5, 4, and 3] Analog start channel set (ANS2, ANS1, and ANS0) Use this bit group to set the A/D conversion start channel. When the A/D converter is activated, A/D conversion starts with the channel selected by these bits. When these bits are read, the channel from which the analog input is being converted is indicated during A/D conversion. When the A/D converter stops in the stop mode, the read 279 CHAPTER 17 A/D CONVERTER value is the channel from which the analog input was previously converted. Table 17.2-4 Start Channel (ANS2, ANS1 and ANS0) ANS2 ANS1 ANS0 Start channel 0 0 0 AN0 [Initial value] 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 [Bits 2, 1, and 0] Analog end channel set (ANE2, ANE1, and ANE0) Use this bit group to set the A/D conversion end channel. Table 17.2-5 End Channel (ANE2, ANE1 and ANE0) ANE2 ANE1 ANE0 End channel 0 0 0 AN0 [Initial value] 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 When the channel set by ANS2 to ANS0 is set, the A/D converter converts the analog input from one channel (single conversion). In the continuous or stop mode, when the A/D converter completes conversion for the channel set by this bit group, it returns to conversion for the start channel set by ANS2 to ANS0. When the channel number set by ANS is greater than the channel number set by ANE, conversion starts with the channel set by ANS. When the A/D converter completes conversion for channel 7, it returns to conversion for channel 0. The A/D converter then continues conversion until the analog input has been converted from the channel set by ANE. 280 17.2 Registers of the A/D Converter Example: When ANS sets channel 6 and ANE sets channel 3 in the single mode Operation: Conversion channels 6ch 7ch 0ch 1ch 2ch 3ch 281 CHAPTER 17 A/D CONVERTER 17.2.2 Data Register (ADCR1, ADCR2) The data register (ADCR1, ADCR2) stores the A/D conversion result, selects the resolution for A/D conversion, and sets the machine cycle. ■ ADCR2 and ADCR1 (data register) Figure 17.2-3 ADCR2 and ADCR1 (Data Register) Higher data register Bit number Address:000039H Read/write Initial value Lower data register Bit number Address:000038H Read/write Initial value Note: For ADCR2, the read value is undefined. [Bit 15] DSEL This bit selects the 8/10-bit mode resolution. Table 17.2-6 SELB (Resolution Selection Bit) SELB Function 0 10-bit mode 1 8-bit mode [Bits 14 and 13] Sampling time (ST1 and ST0) Use these bits to set the sampling machine cycle count. Table 17.2-7 ST1 and ST0 (Sampling Machine Cycle Count Setting Bit) 282 ST1 ST0 Sampling machine cycle count Sampling time 0 0 64 machine cycles 4 µs when the machine clock frequency is 16 MHz 0 1 256 machine cycles 16 µs when the machine clock frequency is 16 MHz 1 0 1024 machine cycles 64 µs when the machine clock frequency is 16 MHz 1 1 4096 machine cycles 256 µs when the machine clock frequency is 16 MHz 17.2 Registers of the A/D Converter [Bits 12 and 11] Compare time (CT1 and CT0) Use these bits to set the compare machine cycle count. Table 17.2-8 CT1 and CT0 (Compare Machine Cycle Count Setting Bit) CT1 CT0 Compare machine cycle count Compare time 0 0 176 machine cycles 22 µs when the machine clock frequency is 8 MHz 0 1 352 machine cycles 22 µs when the machine clock frequency is 16 MHz 1 0 704 machine cycles 44 µs when the machine clock frequency is 16 MHz 1 1 1408 machine cycles 88 µs when the machine clock frequency is 16 MHz Note: Set these bits to "00" only when the machine clock frequency is up to 8 MHz. If the machine clock is faster than 8 MHz, conversion accuracy cannot be guaranteed. [Bits 9 and 8] D9 and D8 These bits are valid when DSEL is 0. The bits store the two higher bits of the conversion result value. [Bits 7 to 0] D7 to D0 These bits make up an A/D conversion storage register containing the digital value indicating the conversion result. The value of this register is updated when conversion is complete. Normally, this register contains the last conversion value. See section 17.5 "Conversion Data Protection Function". The value of this register is undefined at a reset. Note: Do not write data in this register during A/D operation. 283 CHAPTER 17 A/D CONVERTER 17.3 Operation of the A/D Converter The A/D converter is operated in one of the following three modes: • Single mode • Continuous mode • Stop mode ■ Explanation of Operation The A/D converter operates in the successive approximation mode. The resolution can be switched between 8 and 10 bits. Because this A/D converter has only one register (8 bits) for storing the conversion result, the conversion data register (ADCR0) is updated when conversion is complete. For this reason, the A/D converter alone cannot be used for continuous conversion processing. Conversion with conversion data transferred to memory using the EI2OS function is recommended. ■ Single Mode In this mode, the A/D converter sequentially converts the analog inputs set by the ANS and ANE bits. When the A/D converter has converted the analog input from the end channel set by the ANE bit, operation stops. When the same channel is specified for the start and end channels (when ANS is equal to ANE), the A/D converter converts only the analog input from the channel specified by ANS. Example: ANS=000, ANE=011 Start AN0 AN1 AN2 AN3 End ANS=010, ANE=010 Start AN2 End ■ Continuous Mode In this mode, the A/D converter sequentially converts the analog inputs set by the ANS and ANE bits. When the A/D converter has converted the analog input from the end channel set by the ANE bit, it returns to the analog input set by ANS and continues A/D conversion. When the same channel is specified for the start and end channels (when ANS is equal to ANE), the A/D converter continues converting only the analog input from the channel specified by ANS. 284 17.3 Operation of the A/D Converter Example: ANS=000, ANE=011 Start AN0 AN1 AN2 AN3 AN0 Repeat ANS=010, ANE=010 Start AN2 AN2 AN2 Repeat In the continuous mode, the A/D converter repeats conversion until "0" is written in the BUSY bit (writing "0" in the BUSY bit ==> stops operation). Note that a forced operation stop also stops the analog input conversion (at a forced operation stop, the conversion register contains the previous data for which conversion is complete). ■ Stop Mode In this mode, the A/D converter sequentially converts the analog inputs set by the ANS and ANE bits, temporarily stopping when the analog input from each channel is converted. To release the temporary stop state, the A/D converter must be activated again. When the A/D converter has converted the analog input from the end channel set by the ANE bit, it returns to the analog input set by ANS and continues A/D conversion. When the same channel is specified for the start and end channels (when ANS is equal to ANE), the A/D converter converts the analog input from the channel specified by ANS. Example: ANS=000, ANE=011 Start AN0 Stop Activation AN1 AN3 Stop Activation AN0 ANS=010, ANE=010 Start AN2 Stop Activation AN2 Stop Activation Repeat Stop Activation AN2 Stop AN2 Activation Repeat Only the activation factor(s) set by STS1 and STS0 can be used. A conversion start can be synchronized using this mode. 285 CHAPTER 17 A/D CONVERTER 17.3.1 Conversion Using EI2OS The A/D converter can transfer the A/D conversion result to memory using the extended intelligent I/O service (EI2OS). ■ Conversion Using EI2OS When EI2OS is used, the conversion data protection function can safely transfer two or more data items to memory, even during continuous conversion. Figure 17.3-1 Sample Flow from Activation of A/D Conversion to Transfer of Conversion Data (Continuous Mode) Activate A/D conversion Sample hold Activates EI2OS. Conversion Transfer data Interrupt processing End of conversion Generate interrupt Processing marked with 286 Clears the interrupt. depends on EI2OS settings. 17.3 Operation of the A/D Converter 17.3.2 Example of Activating EI2OS in the Single Mode In single mode, EI2OS is activated as follows: • Converts analog inputs AN1 to AN3 and terminates conversion. • Sequentially transfers conversion data to addresses 200H to 206H. • Activates conversion by software. • Uses the highest interrupt level. ■ Example of Activating EI2OS in the Single Mode Table 17.3-1 Example of Activating EI2OS in the Single Mode Setting item EI2OS setting Program example Explanation of operation MOV ICR0, #08H Sets the highest interrupt level, activates EI2OS when an interrupt is generated, and sets the descriptor address. MOV BAPL, #00H Conversion data destination addresses. MOV BAPM, #02H MOV BAPH, #00H MOV ISCS, #18H Transfers word data. Increments the destination address after transfer. Transfers data from I/O to memory. MOV IOAL, #3EH Sets the A/D converter result registers. MOV IOAH, #00H MOV DCTL, #03H MOV DCTH, #00H A/D converter settings MOV ADCS1, #0BH Sets the single mode, the start channel to AN1, and the end channel to AN3. MOV ADCS2, #A2H Activates A/D conversion by software. Other processing EI2OS end and interrupt sequence Performs EI2OS transfer three times (the number of conversion times). : : MOV ADCS2, #80H RETI Returns from the interrupt. ICR3: Interrupt control register BAPL: Lower buffer address pointer BAPM: Middle buffer address pointer BAPH: Higher buffer address pointer ISCS: EI2OS status register 287 CHAPTER 17 A/D CONVERTER IOAL: Lower I/O address register IOAH: Higher I/O address register DCTL: Lower data counter DCTH: Higher data counter Figure 17.3-2 Example of Activating EI2OS in the Continuous Mode Start of activation End Interrupt EI2OS transfer Interrupt EI2OS transfer Interrupt EI2OS transfer Interrupt sequence Parallel processing 288 17.3 Operation of the A/D Converter 17.3.3 Example of Activating EI2OS in the Continuous Mode In continuous mode, EI2OS is activated as follows: • Converts analog inputs AN3 to AN5 and obtains two conversion data items for each channel. • Sequentially transfers conversion data to addresses 600H to 60CH. • Activates conversion by the external edge input. • Uses the highest interrupt level. ■ Example of Activating EI2OS in the Continuous Mode Table 17.3-2 Example of Activating EI2OS in the Continuous Mode Setting item EI2OS setting Program example Explanation of operation MOV ICR0, #08H Sets the highest interrupt level, activates EI2OS when an interrupt is generated, and sets the descriptor address. MOV BAPL, #00H Conversion data destination addresses. MOV BAPM, #06H MOV BAPH, #00H MOV ISCS, #18H Transfers word data. Increments the destination address after transfer. Transfers data from I/O to memory. Terminates processing in response to a request by the peripheral. MOV IOAL, #3EH Source address. MOV IOAH, #00H MOV DCTL, #06H MOV DCTH, #00H A/D converter settings MOV ADCS1, #9DH Sets the continuous mode, the start channel to AN3, and the end channel to AN5. MOV ADCS2, #A4H Activates A/D conversion by external edge input. Other processing EI2OS end and interrupt sequence Performs EI2OS transfer six times (twice for each of the three channels). : : MOV ADCS2, #80H RETI Returns from the interrupt. ICR3: Interrupt control register BAPL: Lower buffer address pointer BAPM: Middle buffer address pointer 289 CHAPTER 17 A/D CONVERTER BAPH: Higher buffer address pointer ISCS: EI2OS status register IOAL: Lower I/O address register IOAH: Higher I/O address register DCTL: Lower data counter DCTH: Higher data counter Figure 17.3-3 Example of Activating EI2OS in the Continuous Mode Start of activation AN3 Interrupt AN4 Interrupt AN5 Interrupt EI2OS transfer EI2OS transfer EI2OS transfer After data is transferred six times Interrupt sequence End 290 17.3 Operation of the A/D Converter 17.3.4 Example of Activating EI2OS in the Stop Mode In stop mode, EI2OS is activated as follows: • Converts analog input AN3 12 times at regular intervals. • Sequentially transfers conversion data to addresses 600H to 618H. • Activates conversion by the external edge input. • Uses the highest interrupt level. ■ Example of Activating EI2OS in the Stop Mode Table 17.3-3 Example of Activating EI2OS in the Stop Mode Setting item EI2OS setting Program example Explanation of operation MOV ICR0, #08H Sets the highest interrupt level, activates EI2OS when an interrupt is generated, and sets the descriptor address. MOV BAPL, #00H Conversion data destination addresses. MOV BAPM, #06H MOV BAPH, #00H MOV ISCS, #19H Transfers word data. Increments the destination address after transfer. Transfers data from I/O to memory. Terminates processing in response to a request by the peripheral. MOV IOAL, #3EH Source address. MOV IOAH, #00H MOV DCTL, #0CH Performs EI2OS transfer 12 times. MOV DCTH, #00H A/D converter settings MOV ADCS1, #DBH Sets the stop mode, the start channel to AN3, and the end channel to AN3 (one channel conversion). MOV ADCS2, #A4H Activates A/D conversion by external edge input. Other processing EI2OS end and interrupt sequence : : MOV ADCS2, #80H RETI Returns from the interrupt. ICR3: Interrupt control register BAPL: Lower buffer address pointer BAPM: Middle buffer address pointer BAPH: Higher buffer address pointer 291 CHAPTER 17 A/D CONVERTER ISCS: EI2OS status register IOAL: Lower I/O address register IOAH: Higher I/O address register DCTL: Lower data counter DCTH: Higher data counter Figure 17.3-4 Example of Activating EI2OS in the Stop Mode Start of activation AN3 Interrupt EI2OS transfer After data is transferred 12 times Stop Activation by the external edge Interrupt sequence End 292 17.4 Notes on Using the A/D Converter 17.4 Notes on Using the A/D Converter This section describes notes on use of A/D converters. ■ Notes on Using the A/D Converter To activate the A/D converter using the external trigger or internal timer, A/D activation factor bits STS1 and STS0 in the ADCS2 register are used. Set these bits in a status in which the input value of the external trigger or internal timer is inactive. If the input value is active, the A/D converter may start operation. Set STS1 and STS0 in a status in which "1" is input to ADTG and "0" is output from the internal timer (16-bit reload timer). Always set the ADER bit corresponding to a pin for use as an analog input to "1". For details, see CHAPTER 8 "I/O PORT". 293 CHAPTER 17 A/D CONVERTER 17.5 Conversion Data Protection Function This A/D converter has a function to protect the converted data. It enables continuous conversion and acquisition of multiple data items using El2OS. ■ Conversion Data Protection Function Because there is only one conversion data register, conversion data is stored at the same time one conversion is complete and previous data is lost by continuous A/D conversion. To prevent losing such data, the A/D converter has a function that does not store the next conversion data in the register unless the previous data is transferred using EI2OS and then stops A/D conversion temporarily. The temporary stop state is released after data is transferred to memory using EI2OS. The A/D converter converts data continuously so long as the previous data is transferred. Figure 17.5-1 Data Protection Function Flow (when EI2OS Is Used) Set EI2OS Activate continuous A/D conversion End of the first conversion Store data in data register End of the second conversion Activate EI2OS NO Temporarily stop A/D conversion Does EI2OS end? (See the Caution below.) YES Store data in data register YES NO Does EI2OS end? End of the third conversion Activate EI2OS Continues. Activate EI2OS End of all conversion Interrupt routine End Stop A/D conversion Note: 294 • This function relates to the INT and INTE bits in ADCS2. • The data protection function is designed to operate in the interrupt enable state only (when INTE is "1"). • In the interrupt disable state (when INTE is "0"), this function does not operate. Continuous 17.5 Conversion Data Protection Function A/D conversion sequentially stores conversion data in the register, and old data is lost. • When the A/D converter is stopped temporarily during EI2OS operation, the A/D converter starts if an interrupt is disabled, thereby ensuring that new data can be written before old data is transferred. • Reactivation in the temporary stop state destroys wait data. 295 CHAPTER 17 A/D CONVERTER 296 CHAPTER 18 D/A CONVERTER This chapter describes the functions and operations of the D/A converter. 18.1 "Overview of the D/A Converter" 18.2 "Registers of theD/A Converter" 18.3 "Operation of the D/A Converter" 297 CHAPTER 18 D/A CONVERTER 18.1 Overview of the D/A Converter The block described below is a D/A converter in the R-2R mode with a resolution of eight bits. This microcontroller has two internal D/A converter channels. The outputs of the two channels can be controlled independently using corresponding D/A control registers. ■ D/A Converter Registers The D/A converter register is shown below. Figure 18.1-1 D/A Converter Registers D/A converter data register 1 Address: 00003BH Read/Write Initial value 15 14 13 12 11 10 9 8 DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 Read/Write Initial value D/A control register 1 7 6 5 4 3 2 1 D/A control register 0 298 Bit No. DADR0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 15 14 13 12 11 10 9 (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) 7 6 5 (-) (-) (-) (-) (-) (-) 4 3 (-) (-) (-) (-) 8 Bit No. DAE1 DACR1 (R/W) (0) 2 1 (-) (-) (-) (-) Address: 00003CH Read/Write Initial value 0 DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 Address: 00003DH Read/Write Initial value DADR1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) D/A converter data register 0 Address: 00003AH Bit No. 0 Bit No. DAE0 DACR0 (R/W) (0) 18.1 Overview of the D/A Converter ■ Block Diagram of the D/A Converter Figure 18.1-2 "Block Diagram of the D/A Converter" is a block diagram of the D/A converter. Figure 18.1-2 Block Diagram of the D/A Converter Internal Data Bus DA DA DA DA DA DA DA DA 17 16 15 14 13 12 11 10 DA DA DA DA DA DA DA DA 07 06 05 04 03 02 01 00 DVR DVR DA17 DA07 2R 2R R DA16 R DA06 2R 2R R R DA15 DA05 DA11 DA01 2R 2R R DA10 R DA00 2R 2R 2R 2R DAE1 DAE0 Standby control Standby control DA output channel 1 DA output channel 0 299 CHAPTER 18 D/A CONVERTER 18.2 Registers of the D/A Converter The two types of D/A converter registers are as follows: • D/A converter registers (DACR0 and DACR1) • D/A control registers (DADR0 and DADR1) ■ D/A Conveter Registers (DACR0 and DACR1) The D/A converter data register (DADR0, DADR1) configuration is shown in Figure 18.2-1 "D/A Converter Data Register (DADR)". Figure 18.2-1 D/A Converter Data Register (DADR) D/A converter data register 1 15 14 13 12 11 Address: 00003BH DA17 DA16 DA15 DA14 DA13 Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) D/A converter data register 0 7 6 5 4 10 9 Bit No. 8 DA12 DA11 DA10 DADR1 (R/W) (R/W) (R/W) (X) (X) (X) 3 2 1 0 Address: 00003AH DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 Read/Write Initial value (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Bit No. DADR0 [Bits 15 to 8] DA17 to DA10 These bits, which are read/write bits that are not initialized by a reset, set the output voltage from channel 1 in the D/A converter. [Bits 7 to 0] DA07 to DA00 These bits, which are read/write bits that are not initialized by a reset, set the output voltage from channel 0 in the D/A converter. ■ D/A Data Registers (DADR0 and DADR1) The D/A control register (DACR0/1) configuration is shown in Figure 18.2-2 "D/A Control Data Register (DACR0/1)". Figure 18.2-2 D/A Control Data Register (DACR0/1) D/A control register 1 Address: 00003DH Read/Write Initial value D/A control register 0 15 14 13 12 11 10 9 8 Bit No. DAE1 DACR1 (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (R/W) (0) 7 6 5 4 3 2 1 0 Bit No. DAE0 DACR0 (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (-) (R/W) (0) Address: 00003CH Read/Write Initial value 300 18.2 Registers of the D/A Converter [Bits 8, 0] DAE1, DAE0 These bits enable or disable D/A converter output. DAE1 controls channel 1, and DAE0 controls channel 0. Setting these bits to "1" enables D/A output. Setting these bits to "0" disables D/A output. These bits are read/write bits that are initialized by a reset. 301 CHAPTER 18 D/A CONVERTER 18.3 Operation of the D/A Converter For starting D/A output, the enabling bit corresponding to the D/A output channel, which is located in the D/A control register (DACR) must be set to 1. ■ Operation of the D/A Converter Disabling D/A output turns off the analog switch serially inserted into the output block of each D/ A converter channel. The circuit in the D/A converter is also cleared to the "0" output state and the path over which direct current flows is cut off. This status also occurs in the stop mode. The output voltage of the D/A converter falls within the range from 0V to 255 respectively 256V times DVR. Adjusting the DVR voltage externally can change the output voltage range. No built-in buffer amplifier is mounted for D/A converter output, and because the analog switch (nearly equal to 100Ω) is inserted serially to the output, sufficient settling time is required for putting an external load on the output. Table 18.3-1 "Theoretical Output Voltage Values of the D/A Converter" lists the theoretical output voltage values of the D/A converter. Table 18.3-1 Theoretical Output Voltage Values of the D/A Converter 302 Setting of DA07 to DA00 and DA17 to DA10 Theoretical output voltage value 00H 0/256 × DVR (= 0V) 01H 1/256 × DVR 02H 2/256 × DVR to to FDH 253/256 × DVR FEH 254/256 × DVR FFH 255/256 × DVR CHAPTER 19 UART This chapter describes the functions and operations of the UART. 19.1 "Overview of the UART" 19.2 "Block Diagram of the UART" 19.3 "Registers of the UART" 19.4 "UART Baud Rates" 19.5 "Operation of the UART" 19.6 "Flags and Interrupt Sources of the UART" 19.7 "Applications of the UART and Precautions" 303 CHAPTER 19 UART 19.1 Overview of the UART The UART is a serial I/O port used for asynchronous (start-stop synchronous) and CLK synchronous communications. ■ Features of the UART Features of the UART are shown below. • Full-duplex double buffer • Can be used for asynchronous (start-stop synchronous) communication and CLK synchronous communication. • Multi-processor mode is supported. • Dedicated baud rate generator is incorporated. Table 19.1-1 Baud Rate Operation Asynchronous communication: 31250/ 9615/ 4808/ 2404/ 1202 bps CLK synchronous communication: 2M/ 1M/ 500K/ 250K/ 125K/ 62.5K bps *: 304 Baud rate* Internal machine clock: At 6, 8, 10, 12, or 16 MHz • Any baud rate can be set using an external clock. • Error detecting function (parity, flaming, overrun) • NRZ code is used as a transfer signal. • Extended intelligent I/O service (EI2OS) is supported. 19.2 Block Diagram of the UART 19.2 Block Diagram of the UART Figure 19.2-1 "Block Diagram of the UART" shows the block diagram of the UART. ■ Block Diagram of the UART Figure 19.2-1 Block Diagram of the UART Control signal Receiving interrupt (for CPU) Dedicated baud rate generator SCK0 PPG timer Upper (internally connected) (PPG1) Clock selection circuit Sending interrupt (for CPU) Sending clock Receiving clock External clock SIN0 Receiving control circuit Sending control circuit Start bit detection circuit Sending start circuit Receiving bit counter Sending bit counter Receiving parity counter Sending parity counter SOT0 Receiving status evaluation circuit Receiving shifter Sending shifter Complete receiving Start sending SIDR SODR Receiving error occurrence signal for EI2OS (for CPU) Internal Data Bus SMR register MD1 MD0 CS2 CS1 CS0 SCKE SOE SCR register PEN P SBL CL A/D REC RXE TXE SSR register PE ORE FRE RDRF TDRE RIE TIE Control signal 305 CHAPTER 19 UART 19.3 Registers of the UART There are the following five types of UART registers: • Serial mode register (SMR) • Serial control register (SCR) • Serial input data register (SIDR)/ Serial output data register (SODR) • Serial status register (SSR) • Communication prescaler control register (CDCR) ■ Registers of the UART Figure 19.3-1 UART Register 15 Serial mode register Address: 000020H 000024H Read/Write Initial value Serial control register Address: 000021H 000025H Read/Write Initial value Serial input data register Serial output data register Address: 000022H 000026H Read/Write Initial value Serial status register Address: 000023H 000027H Read/Write Initial value Communication prescaler control register Address: 000028H 00002AH Read/Write Initial value 306 8 7 0 CDCR (R/W) SCR SMR (R/W) SSR SIDR(R)/SODR(W) (R/W) 7 MD1 6 MD0 5 4 3 2 CS2 CS1 CS0 Reserved 1 0 SCKE SOE Bit No. SMR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 15 14 13 12 11 10 9 8 PEN P SBL CL A/D REC RXE TXE (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 14 13 12 11 PE ORE FRE RDRF TDRE (R) (0) (R) (0) (R) (0) (R) (0) (R) (1) 7 6 5 4 3 | MD (R/W) (0) (-) (-) | (-) (-) | (-) (-) SCR (W) (R/W) (R/W) (0) (0) (1) 7 15 Bit No. 10 (-) (-) 2 DIV3 DIV2 9 8 RIE TIE Bit No. SIDR(read) SODR(write) Bit No. SSR (R/W) (R/W) (0) (0) 1 0 DIV1 DIV0 (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) Bit No. CDCR 19.3 Registers of the UART 19.3.1 Serial Mode Register (SMR) The serial mode register (SMR) specifies the operation mode of the UART. Set the operation mode when the register is not in operation. Also, do not write data in this register when in operation. ■ Serial Mode Register (SMR) Figure 19.3-2 Configuration of the Serial Mode Register (SMR) Serial mode register 7 Address: 000020H 000024H Read/Write Initial value MD1 6 MD0 5 4 3 2 1 CS2 CS1 CS0 Reserved 0 SCKE SOE Bit No. SMR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) [bit 7, 6] MD1, MD0 (MoDe Select): The operation mode of the UART is selected at these bits. Table 19.3-1 Operation Mode Select Setting Mode MD1 MD0 Operation mode 0 0 0 Asynchronous (start-stop synchronous) Normal mode [Initial value] 1 0 1 Asynchronous (start-stop synchronous) Multiprocessor mode 2 1 0 CLK synchronous mode — 1 1 Setting prohibited Note: CLK asynchronous mode (multiprocessor), represented as mode 1, is used when multiple slave CPUs are connected to the host CPU. In this resource, the data format of the receiving data cannot be identified. Thus it supports only the master in the multiprocessor mode. Also, set 0 in the PEN of the SCR register because the parity checking function cannot be used. [bit 5 to 3] CS2, CS1, CS0 (Clock Select): Baud rate clock source is selected at these bits. When the dedicated baud rate generator is selected, a baud rate is selected at the same time. 307 CHAPTER 19 UART Table 19.3-2 Clock Input Select Setting CS2 CS1 CS0 000Bto 100B Clock input Dedicated baud rate generator 1 0 1 Reserved 1 1 0 Internal timer (16-bit reload timer 0) 1 1 1 External clock Note: When the internal timer is selected, 16-bit reload timer 0 output is selected for MB90570 Series. [bit 2] Reserved bit 0 must always be written. [bit 1] SCKE (SCLK Enable): When communicating in CLK synchronous mode (mode 2), specify whether the SCK0 pin is used as a clock input pin or clock output pin. In CLK asynchronous mode or external clock mode, set the bit to 0. When in CLK asynchronous or external clock mode, set the bit to 0 to use the pin as a general-purpose port pin. Table 19.3-3 SCKE (SCLK Enable) Bit Function SCKE Function 0 Functions as a clock input pin. [Initial value] 1 Functions as a clock output pin. Note: To use the SCK0 pin as a clock input pin, the external clock source must be selected. [bit 0] SOE (Serial Output Enable): Specify whether the external pin (SOT0) that is also used as a general-purpose I/O port pin is used as a serial output pin or I/O port pin. Table 19.3-4 SOE (Serial Output Enable) Bit Function SOE 308 Function 0 Functions as a general-purpose I/O port pin. [Initial value] 1 Functions as a serial data output pin (SOT0). 19.3 Registers of the UART 19.3.2 Serial Control Register (SCR) The Serial Control Register (SCR) controls the transfer protocol during the serial communication. ■ Serial Control Register (SCR) Figure 19.3-3 Configuration of the Serial Control Register (SCR) Serial control register Address: 000021H 000025H Read/Write Initial value 15 14 13 12 11 10 9 8 PEN P SBL CL A/D REC RXE TXE (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) Bit No. SCR (W) (R/W) (R/W) (0) (0) (1) [bit 15] PEN (Parity Enable): In the serial communication, specify whether to add a parity bit to data. Table 19.3-5 PEN (Parity Enable) Bit Function PEN Function 0 Parity added [Initial value] 1 Parity not added. Note: A parity bit can be added only in the normal mode (mode 0) of asynchronous (start-stop synchronous) communication mode. A parity bit cannot be added in multiprocessor mode (mode 1) and CLK synchronous mode (mode 2). [bit 14] P (Parity): When transmitting data with a parity bit, specify whether even or odd parity is used. Table 19.3-6 P (Even and Odd Parity Specifying Bit) P Function 0 Even parity [Initial value] 1 Odd parity [bit 13] SBL (Stop Bit Length): When communicating in asynchronous (start-stop synchronous) mode, specify the bit length of the stop bit that is used as the flame end mark. 309 CHAPTER 19 UART Table 19.3-7 SBL (Stop Bit LengthSpecifying Bit) SBL Function 0 One stop bit 1 Two stop bits [bit 12] CL (Character Length): Specify the data length of the flame to be sent or received. Table 19.3-8 CL (Send or Receive Data Length Specifying Bit) CL Function 0 7-bit data [Initial value] 1 8-bit data Note: 7-bit data can be send or received only in the normal mode (mode 0) of asynchronous (startstop synchronous) communications. In the multiprocessor mode (mode 1) and CLK synchronous communication (mode 2), specify 8-bit data. [bit 11] A/D (Address/Data): Specify the data format of the flame to be sent or received in multiprocessor mode (mode 1) of asynchronous (start-stop synchronous) communications. Table 19.3-9 A/D (Address Data) Bit Function A/D Function 0 Data flame 1 Address flame [bit 10] REC (Receiver Error Clear): Clears error flags (PE, ORE, FRE) of the SSR register. Writing 1 is invalid, and the value read is always 1. [bit 9] RXE (Receiver Enable): Controls the receiving operation of the UART. Table 19.3-10 RXE (Receiver Enable) Bit RXE Function 0 Prohibits the receiving operation. 1 Allows the receiving operation. Note: If the receiving operation is prohibited while data is being received (data is being input to the receiving shift register), the receiving operation is stopped when the flame is received 310 19.3 Registers of the UART completely and the received data is stored in the receiving data buffer SIDR register. [bit 8] TXE (Transmitter Enable): Controls the sending operation of the UART. Table 19.3-11 Send Operation Control Bit (TXE) TXE Function 0 Prohibits the sending operation. 1 Allows the sending operation. Note: If the sending operation is prohibited while data is being sent (data is being output from the sending register), the sending operation is stopped when there is no remaining data in the sending data buffer SODR register. After data is written into the SODR, wait for the time described in the following before writing 0. The wait time should be one sixteenth that of the baud rate when in clock asynchronous transfer mode, and equivalent to that of the baud rate when in clock synchronous transfer mode. 311 CHAPTER 19 UART 19.3.3 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) The serial input data register (SIDR) is a data buffer register used for receiving serial data. The serial output data register (SODR) is a data buffer register used for sending serial data. The SIDR and SODR registers are both allocated to the same address. ■ Configuration of Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) Figure 19.3-4 Configuration of Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) Serial input data register (SIDR) Serial output data register (SODR) 7 6 5 4 3 2 1 0 Address: 000022H D7 D6 D5 D4 D3 D2 D1 D0 000026H Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value (X) (X) (X) (X) (X) (X) (X) (X) Bit No. SIDR(read) SODR(write) If the data is 7 bits in length, the high order 1 bit (D7) is invalid. Write data to the SODR register when TDRE of the SSR register is 1. Note: To write to and read from this address means that the write data is output to the SODR register and the read data is input to the SIDR register, respectively. 312 19.3 Registers of the UART 19.3.4 Serial Status Register (SSR) The serial status register (SSR) is configured with flags that indicate the operation status of the UART. ■ Serial Status Register (SSR) Figure 19.3-5 Serial Status Register Configuration Serial status register Address: 000023H 000027H Read/Write Initial value 15 14 13 12 PE ORE FRE RDRF TDRE (R) (0) (R) (0) (R) (0) (R) (0) 11 (R) (1) 10 (-) (-) 9 8 RIE TIE Bit No. SSR (R/W) (R/W) (0) (0) [bit 15] PE (Parity Error): This is an interrupt request flag that is set when a parity error occurs while data is being received. To clear the flag that is set, write 0 to the REC bit (bit 10) of the SCR register. When this bit is set, data in the SIDR becomes invalid. Table 19.3-12 PE (Parity Error) Bit Function PE Function 0 Parity error not occurred [Initial value] 1 Parity error occurred [bit 14] ORE (Over Run Error): This is an interrupt request flag that is set when an overrun error occurs while data is being received. To clear the flag that is set, write 0 to the REC bit (bit 10) of the SCR register. When this bit is set, data in the SIDR becomes invalid. Table 19.3-13 ORE (Over Run Error) Function ORE Function 0 Overrun error not occurred [Initial value] 1 Overrun error occurred [bit 13] FRE (Framing Error): This is an interrupt request flag that is set when a flaming error occurs while data is being received. To clear the flag that is set, write 0 to the REC bit (bit 10) of the SCR register. 313 CHAPTER 19 UART When this bit is set, data in the SIDR becomes invalid. Table 19.3-14 FRE (Framing Error) Function FRE Function 0 Flaming error not occurred [Initial value] 1 Flaming error occurred [bit 12] RDRF (Receiver Data Register Full): This is an interrupt request flag that shows there is receiving data in the SIDR register. It is set when receiving data is loaded to the SIDR register and is cleared automatically when data is read from the SIDR register. Table 19.3-15 RDRF (Receiver Data Register Full) Function SIDR Function 0 No receiving data. 1 Receiving data. [bit 11] TDRE (Transmitter Data Register Empty): This is an interrupt request flag that shows that sending data can be written to the SODR register. It is cleared when sending data is written to the SODR register and is set again when the written data is loaded to the sending shifter and transfer has started, thereby indicating that next sending data can be written. Table 19.3-16 TDRE (Transmitter Data Register Empty) Function TDRE Setting 0 Writing sending data prohibited 1 Writing sending data allowed [bit 9] RIE (Receiver Interrupt Enable): This flag controls the receiving interrupt. Table 19.3-17 RIE (Receiver Interrupt Enable) Function RIE Function 0 Prohibits interrupt. 1 Allows interrupt. Note: Receiving interrupt sources include error occurrence by PE, ORE, and FRE as well as normal reception by RDRF. 314 19.3 Registers of the UART [bit 8] TIE (Transmitter Interrupt Enable): This flag controls the sending interrupt. Table 19.3-18 TIE (Transmitter Interrupt Enable) Function TIE Function 0 Prohibits interrupt 1 Allows interrupt Note: The sending interrupt source is a sending request by TDRE. 315 CHAPTER 19 UART 19.3.5 Communication Prescaler Control Register (CDCR) The communication prescaler control register (CDCR) controls the machine clock frequency divide ratio. ■ Communication Prescaler Control Register (CDCR) The operation clock of the UART is obtained by the frequency divided machine clock. This communication prescaler is designed to obtain a constant baud rate for various machine clocks. This communication prescaler output is used for the operation clock of the extended I/O serial interface. The bit configuration of the CDCR is shown below. Figure 19.3-6 Configuration of the CDCR (Communication Prescaler Control Register) Communication prescaler control register 7 Address: 000028H 00002AH Read/Write Initial value 6 5 4 2 DIV3 DIV2 MD (R/W) (0) 3 (-) (-) (-) (-) (-) (-) 1 0 DIV1 DIV0 Bit No. CDCR (R/W) (R/W) (R/W) (R/W) (1) (1) (1) (1) Note: The CDCR0 (address: 000028H) is a communication prescaler register responsible for channel 0 of the UART and for channels 2, 3, and 4 of the extended serial I/O interface. The use of the common register requires that a common division ratio be selected for channel 0 of the UART and for channels 2, 3, and 4 of the extended serial I/O interface. Note that use of more than one division ratio for these channels is prohibited. The CDCR1 (address: 00002AH) is responsible for channel 1 of the UART. [bit 7] MD (Machine clock devide moDe select) This is the operation allowance bit of the communication prescaler. Table 19.3-19 MD (Machine Clock Divide Mode Select) Bit Function CDCR Function 0 Stops the communication prescaler. 1 Operates the communication prescaler. [bit 3,2,1,0] DIV3 to 0 (DIVide 3 to 0): Determines the division ratio of the machine clock. 316 19.3 Registers of the UART Table 19.3-20 DIV3 to 0 (Divide 3 to 0) Bit Function DIV3 DIV2 DIV1 DIV0 Division ratio (div) 1 1 1 1 Disabled (initial value) 1 1 1 0 Two 1 1 0 1 Three 1 1 0 0 Four 1 0 1 1 Five 1 0 1 0 Six 1 0 0 1 Seven 1 0 0 0 Eight Note: • For actual operation, set this value as a bit sequence other than "1111". • If the division ratio is altered, wait for the time equivalent of two cycles for the clock to stabilize before starting communication. ■ Setting of the Communication Prescaler Register Depending on the machine clock frequency φ used, the communication prescaler register is set as shown below. Table 19.3-21 Setting of the Communication Prescaler Register Machine clock frequency φ div DIV3 DIV2 DIV1 DIV0 φ/div 4 MHz 4 1 1 0 0 1 MHz 6 MHz 6 1 0 1 0 8 MHz 8 1 0 0 0 6 MHz 3 1 1 0 1 8 MHz 4 1 1 0 0 10 MHz 5 1 0 1 1 12 MHz 6 1 0 1 0 14 MHz 7 1 0 0 1 16 MHz 8 1 0 0 0 8 MHz 2 1 1 1 0 12 MHz 3 1 1 0 1 16 MHz 4 1 1 0 0 2 MHz 4 MHz When a combination of machine clock and div value is to be used other than the combinations in the above table, a value not exceeding the maximum value of 4.25 MHz is selected for φ/div. 317 CHAPTER 19 UART 19.4 UART Baud Rates The UART clock can be selected from among the following sources. • Dedicated baud rate generator • Internal timer • External clock ■ Dedicated baud rate generator Tables 19.4-1 "Baud Rates (Asynchronous)" and 19.4-2 "Baud Rates (CLK Synchronous)" show the baud rates when the dedicated baud rate generator is selected. These baud rates are calculated using an assumed machine clock φ value of 16 MHz and a div value (machine clock division ratio) of 8. Table 19.4-3 "Communication Prescaler Settings" shows the communication prescaler settings. Table 19.4-1 Baud Rates (Asynchronous) CS2 CS1 CS0 Asynchronous (start-stop synchronous) Expression 0 0 0 9615 bps (φ/div) / (8×13×2) 0 0 1 4808 bps (φ/div) / (8×13×22) 0 1 0 2404 bps (φ/div) / (8×13×23) 0 1 1 1202 bps (φ/div) / (8×13×24) 1 0 0 31250 bps (φ/div) / 26 Table 19.4-2 Baud Rates (CLK Synchronous) 318 CS2 CS1 CS0 CLK synchronous When φ / div = 2 MHz: Expression 0 0 0 1 M bps (φ/div) / 2 0 0 1 500 K bps (φ/div) / 22 0 1 0 250 K bps (φ/div) / 23 0 1 1 125 K bps (φ/div) / 24 1 0 0 62.5 K bps (φ/div) / 25 19.4 UART Baud Rates Table 19.4-3 Communication Prescaler Settings MD DIV3 DIV2 DIV1 DIV0 div Recommended machine clock 1 1 1 0 1 3 6 MHz 1 1 1 0 0 4 8 MHz 1 1 0 1 1 5 10 MHz 1 1 0 1 0 6 12 MHz 1 1 0 0 0 8 16 MHz ■ Internal timer When the bits CS2 to CS0 in the serial mode register (SMR) are set to a sequence of 110 for an internal timer setting, the 16-bit timer (timer 0) operates in reload mode. To obtain the baud rate, use the following formulas. Asynchronous (start-stop synchronous): ( φ/) / (16 × 2 × (n+1)) CLK synchronous: ( φ/N) / ( 2 × (n+1)) φ: Machine clock N: Count clock source of the timer n: Reload value of the timer Table 19.4-4 "Baud Rates and Reload Values (Asynchronous)" shows baud rates and reload values (in decimal) when the machine clock is set at 7.3728 MHz. Table 19.4-4 Baud Rates and Reload Values (Asynchronous) Reload value Baud rate N=21 Machine clock frequency divided by two N=23 Machine clock frequency divided by eight 38400 2 — 19200 5 — 9600 11 2 4800 23 5 2400 47 11 1200 95 23 600 191 47 300 383 95 When the internal timer (16-bit reload timer 0) is selected as a baud rate clock source, the output (T00) of the 16-bit timer 0 is already connected in this controller. Therefore, the external 319 CHAPTER 19 UART pin (T00) of the 16-bit timer 0 and the external clock input pin SCK0 do not require external connection. Also, the output pin of the timer 0 can be used as an I/O port pin if not used otherwise. ■ External clock When the external clock is selected by setting CS2 to CS0 to 111, baud rates are calculated as follows by expressing the frequency of the external clock as f. Asynchronous (start-stop synchronous): f/16 CLK synchronous: f (up to 1 MHz) Note that the maximum value for f is 1 MHz. 320 19.5 Operation of the UART 19.5 Operation of the UART The UART has two different operation modes: the asynchronous mode and the CLK synchronous mode. The operation mode can be switched by specifying the value for the serial mode register (SMR) or the serial control register (SCR). ■ UART Operation Modes Table 19.5-1 UART Operation Modes Mode Parity Data length Yes/No 7 Yes/No 8 1 No 8+1 2 No 8 0 Operation mode Stop bit length Asynchronous (start-stop synchronous) Normal mode 1 bit or 2 bits Asynchronous (start-stop synchronous) Multiprocessor mode CLK synchronous mode No Note: The stop bit length in asynchronous (start-stop synchronous) mode is specified only for a sending operation. A one-bit length is always specified for a receiving operation. Because the register cannot be operated in a mode other than above, one of above-shown modes must be set. 321 CHAPTER 19 UART 19.5.1 Asynchronous (Start-stop Synchronous) Mode When the UART operates in operation mode 0 (normal mode) or operation mode 1 (multi-processor mode), the asynchronous mode is used for data transfer. Also, the UART manages data in NRZ (Non Return to Zero) format only. ■ Transfer Data Format Figure 19.5-1 Transfer Data Format (Mode 0, 1) SIN0,SOT0 Start LSB MSB Stop A/D Stop (Mode 0) (Mode 1) Data transferred is 01001101 As shown in Figure 19.5-1 "Transfer Data Format (Mode 0, 1)", transfer data always starts with the start bit (L level data), followed by data bits in the LSB first method, and ends with the stop bit (H level data). When the external clock is selected, the clock must be entered. In normal mode (mode 0), data length can be set to either 7 or 8 bits. In multiprocessor mode (mode 1), however, 8 bits must be set. In addition, parity cannot be added in the multiprocessor mode. Instead of a parity, the A/D bit is always added. ■ Receiving Operation If 1 is set in the RXE bit of the SCR register, the receiving operation is performed. When the start bit appears in the receiving line, 1-flame data is received according to the data format specified in the SCR register. When the reception of 1-flame data is completed, (after the error flag is set in the case of an error) the RDRF flag (of the SSR register) is set. If 1 is set in the RIE bit of the SSR register, receiving interrupt occurs to the CPU. Check the flags in the SSR register and read the SIDR register if the receiving operation is completed normally. If an error occurs, respond as required. The RDRF flag is cleared when the SIDR register is read. ■ Sending Operation When the TDRE flag of the SSR register is 1, the sending data is written in the SODR register. If the TXE bit of the SCR register is 1, the data is sent. When the data set in the SODR register is loaded to the sending shift register and sending begins, the TDRE flag is set again and the next sending data can be set. If 1 is set in the TIE bit of the SSR register, a sending interrupt occurs to the CPU and the CPU is required to set the sending data in the SODR register. The TDRE flag is cleared temporarily if the data is set in the SODR register. 322 19.5 Operation of the UART 19.5.2 CLK Synchronous Mode When the UART operates in the operation mode 2 (normal mode), the CLK synchronous mode is used for data transfer. Also, the UART manages data in NRZ (Non Return to Zero) format only. ■ Transfer Data Format of CLK Synchronous Mode Figure 19.5-2 Transfer Data Format SODR write Mark SCLK RXE,TXE SIN0,SOT0 LSB MSB (Mode 2) Data transferred is 01001101 When an internal clock (dedicated baud rate generator or internal timer) is selected, a data receiving synchronous clock is automatically generated when the data is sent. When an external clock is selected, confirm that the data exists in the sending data buffer SODR register when sending the UART side (the TDRE flag is 0) and then provide clock pulses that cover a duration of one byte. Also, confirm that a mark level "H" is set before and after the sending operation. All data must be 8-bits long and parity cannot be added, and because there are no start/stop bits, errors other than overrun errors cannot be detected. 323 CHAPTER 19 UART ■ Settings for the Control Registers When CLK Synchronous Mode Is Used The settings for the control registers when CLK synchronous mode is used are as follows: Table 19.5-2 Setting for the Control Regiser when CLK Synchronous Mode is Used Register name SMR register SCR register SSR register Bit Setting MD1, MD0 "10" CS2, CS1, CS0 Specifies the clock input. SCKE When the dedicated baud rate generator or internal timer is used: "1", when the external clock is used: "0" SOE To send: 1, to receive: 0 PEN "0" P, SBL, A/D These bits have no meaning. CL "1" REC "0" (for initialization) RXE, TXE At least one must be "1". RIE When an interrupt is used: "1", when an interrupt is not used: "0" TIE "0" ■ Starting the Communication in CLK Synchronous Mode Communication can be started by writing in the SODR register. Even when receiving data, temporary sending data must be written in the SODR register. ■ Terminating the Communication in CLK Synchronous Mode The user can confirm termination when the RDRF flag of the SSR register has changed to 1. Determine if the communication was completed normally by checking the ORE bit of the SSR register. 324 19.6 Flags and Interrupt Sources of the UART 19.6 Flags and Interrupt Sources of the UART The UART has five flags, PE, ORE, FRE, RDRF, and TDRE. Interrupt sources are categorized for reception and transmission. ■ Flags of the UART ❍ PE (Parity Error), ORE (Overrun Error), and FRE (Flaming Error) These flags are set when a receiving error occurs and cleared when 0 is written to REC of the SCR register. ❍ RDRF RDRF is set when a receiving data is loaded in the SIDR register and cleared when the SIDR register is read. However, the parity detect function is not supported in mode 1, while the parity detect and flaming error detect functions are not supported in mode 2. ❍ TDRE TDRE is set when the SODR register becomes empty and ready to be written and cleared when written in the SODR register. ■ Interrupt Sources of the UART Interrupt sources of the UART are used for either receiving or sending data. When receiving data, an interrupt is requested by PE, ORE, FRE, or RDRF. When sending data, an interrupt is requested by TDRE. For the timing to set an interrupt and flag in each operation mode, see Section 19.6.1 "Timing to Set an Interrupt and Flag of the UART". 325 CHAPTER 19 UART 19.6.1 Timing to Set an Interrupt and Flag of the UART This section describes the timing to set an interrupt and a flag in each operation mode. ■ Timing to Set an Interrupt and Flag of the UART ❍ In receiving operation of mode 0 PE, ORE, FRE, or RDRF is set when the receiving transfer is completed and the last stop bit is detected. Thereafter, an interrupt request to the CPU is generated. When PE, ORE, or FRE is active, data in SIDR is invalid. Figure 19.6-1 "Timing Chart to Set PE, ORE, FRE, and RDRF (Mode 0)" shows a timing chart to set PE, ORE, FRE, and RDRF (mode 0). Figure 19.6-1 Timing Chart to Set PE, ORE, FRE, and RDRF (Mode 0) Data D6 D7 Stop PE,ORE,FRE RDRF Receiving interrupt ❍ In receiving operation of mode 1 ORE, FRE, or RDRF is set when the receiving transfer is completed and the last stop bit is detected. Thereafter, an interrupt request to the CPU is generated. Since the receivable data length is 8 bits, the data in the ninth bit representing address/data is invalid. When ORE or FRE is active, data in SIDR is invalid. Figure 19.6-2 "Timing Chart to Set ORE, FRE, and RDRF (Mode 1) " shows a timing chart to set ORE, FRE, and RDRF (mode 1). 326 19.6 Flags and Interrupt Sources of the UART Figure 19.6-2 Timing Chart to Set ORE, FRE, and RDRF (Mode 1) Data D7 Address/ Data Stop ORE,FRE RDRF Receiving interrupt ❍ In receiving operation of mode 2 ORE or RDRF is set when the receiving transfer is completed and the last data (D7) is detected. Thereafter, an interrupt request to the CPU is generated. When ORE is active, data in SIDR is invalid. Figure 19.6-3 "Timing Chart to Set ORE and RDRF (Mode 2)" shows a timing chart to set OR and RDRF (mode 2). Figure 19.6-3 Timing Chart to Set ORE and RDRF (Mode 2) Data Receiving interrupt ❍ In sending operation of modes 0, 1, and 2. The TDRE flag is cleared when the sending data is written in the SODR register. Also, the SODR register is ready to be written when the SODR register value is transferred to the internal shift register, so the TDRE flag is set. When this flag is set, an interrupt request to the CPU is generated. If 0 is written to TXE (RXE as well in mode 2) of the SCR register during the sending operation, TDRE of the SSR register turns to 1. As a result, the sending shifter is stopped and the sending operation of the UART is prohibited. Even though 0 is written to TXE (RXE as well in mode 2) of the SCR register during the sending operation, the data is sent if written to the SODR register before the sending operation is stopped. Figure 19.6-4 "Timing Chart to Set TDRE (Mode 0, 1)" shows the timing to set TDRE (mode 0, 1). Also, Figure 19.6-5 "Timing to Set TDRE (Mode 2)" shows a timing chart to set TDRE (mode 2). 327 CHAPTER 19 UART Figure 19.6-4 Timing Chart to Set TDRE (Mode 0, 1) SODR write TDRE Interrupt request to the CPU SOT0 interrupt SOT0 output ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3 A/D ST Start bit D0 to D7 Data bit SP Stop bit A/D Address/Data multiplexer Figure 19.6-5 Timing to Set TDRE (Mode 2) SODR write TDRE Interrupt request to the CPU SOT0 interrupt SOT0 output D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 to D7 Data bit 328 19.7 Applications of the UART and Precautions 19.7 Applications of the UART and Precautions As an application of the UART, this section shows an example of system configuration in mode 1 and communication flow chart. ■ Application of the UART (Example of System Configuration in Mode 1) Mode 1 is used when multiple slave CPUs are connected to one host CPU (see Figure 19.7-1 "Example of System Configuration in Mode 1"). In this resource, only the communication interface of the host is supported. Figure 19.7-1 "Example of System Configuration in Mode 1" shows an example of system configuration in mode 1. Figure 19.7-1 Example of System Configuration in Mode 1 SO SI Host CPU SO SI SO SI Slave CPU#0 Slave CPU#1 ■ Communication Flow Chart of the UART Communication starts when the host CPU transfers the address data. Address data is data when A/D of the SCR register is 1. A slave CPU is selected according to this address data and communication with the host CPU is enabled. The usual data is data when A/D of the SCR register is 0. The parity checking function is not used in this mode, so set 0 in PEN of the SCR register. 329 CHAPTER 19 UART Figure 19.7-2 Communication Flow Chart in Mode 1 Host CPU Set transfer mode to 1 Set data to select a slave CPU in D0 to D7, 1 in A/D, and then transfer one bite Set 0 in A/D Receiving operation allowed Communication with a slave CPU Terminate communication? Communication with another slave CPU Receiving operation prohibited ■ Extened Intelligent I/O Service (EI2OS) For EI2OS, see Section 3.6 "Extended Intelligent I/O Service (EI2OS)". ■ Precautions for Using the UART Select a communication mode when the operation is stopped to guarantee data sent or received during mode setting. 330 CHAPTER 20 EXTENDED SERIAL I/O INTERFACE This chapter describes the functions and operations of the extended serial I/O interface. 20.1 "Overview of the Extended Serial I/O Interface" 20.2 "Registers of the Extended Serial I/O Interface" 20.3 "Operation of the Extended Serial I/O Interface" 331 CHAPTER 20 EXTENDED SERIAL I/O INTERFACE 20.1 Overview of the Extended Serial I/O Interface The extended serial I/O interface is a serial type I/O interface that can transfer data with an 8-bit and 3-channel structure in clock synchronous mode. Also, in data transfer, selection between LSB-first transfer and MSB-first transfer is possible. ■ Overview of Extended Serial I/O Interface The two types of extended serial I/O operating modes are as follows: ❍ Internal shift clock mode: Transfers data in synchronization with the internal clock (communication prescaler). ❍ External shift clock mode: Transfers data in synchronization with the clock input from an external pin (SCK). In this mode, general-purpose ports that share the external pin (SCK) can perform transfer operations using CPU instructions. The unit of this series contains three channels of the extended serial I/O interface. 332 20.1 Overview of the Extended Serial I/O Interface ■ Block Diagram of the Extended Serial I/O Interface Figure 20.1-1 Block Diagram of the Extended Serial I/O Interface Internal data bus D0~D7 (LSB first) (MSB first) D0~D7 Bit direction select SIN2,3,4 Read Write Serial data register (SDR) SOT2,3,4 SCK2,3,4 Control circuit Shift clock counter Internal clock (Communication prescaler) 2 1 0 SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS SOE SCOE Interrupt request Internal data bus 333 CHAPTER 20 EXTENDED SERIAL I/O INTERFACE 20.2 Registers in the Extended Serial I/O Interface The extended serial I/O interface has three registers as follows. • Serial mode control status register (higher order) • Serial mode control status register (lower order) • Serial data register ■ Registers of the Extended Serial I/O Interface Figure 20.2-1 Registers in the Extended Serial I/O Interface Serial mode control status register (higher order) 15 14 13 12 11 10 9 8 Address: ch0 000049H ch1 00004DH SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT ch2 00007DH Read/Write (R/W) (R/W) (R/W) (R/W) (R/W) (R) (R/W) (R/W) Initial value (0) (0) (0) (0) (0) (0) (1) (0) Bit No. SMCS *2 *1 *1: Only 0 can be written. *2: Only 1 can be written. The read value is always "0". Serial mode control status register (lower order) 7 Address: ch0 000048H ch1 00004CH ch2 00007CH Read/Write Initial value 6 5 4 3 2 MODE BDS (-) (-) (-) (-) (-) (-) (-) (-) 1 SOE 0 SCOE Bit No. SMCS (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) Serial shift data register ch0 000004AH ch1 000004EH ch2 000007EH Read/Write Initial value 334 7 6 5 4 3 2 D7 D6 D5 D4 D3 D2 1 0 D1 D0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) Bit No. SDR 20.2 Registers in the Extended Serial I/O Interface 20.2.1 Serial Mode Control Status Register (SMCS) The serial mode control status register (SMCS) controls the serial I/O transfer operating mode. ■ Serial Mode Control Status Register (SMCS) Figure 20.2-2 Serial Mode Control Status Register (SMCS) Serial mode control status register (higher order) 15 Address: ch0 000049H ch1 00004DH ch2 00007DH Read/Write Initial value 14 13 12 10 9 8 Bit No. SMCS SMD2 SMD1 SMD0 SIE SIR (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) *1: Only "0" can be written. *2: Only "1" can be written. The read value is always "0". Serial mode control status register (lower order) 7 Address: ch0 000048H ch1 00004CH ch2 00007CH Read/Write Initial value 11 6 5 BUSY STOP STRT (R) (0) *2 *1 4 3 MODE BDS (-) (-) (-) (-) (-) (-) (-) (-) (R/W) (R/W) (1) (0) 2 1 SOE 0 SCOE Bit No. SMCS (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) Notes: Only "0" can be used in write operation for the SIR (bit No. 11). Only "1" can be used in write operation for the STRT (bit No. 8). The read value is always "0". The function of each bit is explained below. [Bit 3] Serial mode select bit (MODE) Use this bit to select the activation condition in the stopped state. A write operation is prohibited during operation. This bit is initialized to "0" by a reset and is a read/write bit. To activate the intelligent I/O service, set this bit to "1". Table 20.2-1 MODE Function (Activation Condition Select Bit) MODE Function 0 Activated by setting STRT to 1. [Initial value] 1 Activated by reading or writing the serial data register. 335 CHAPTER 20 EXTENDED SERIAL I/O INTERFACE [Bit 2] Bit direction select bit (BDS) This bit selects the bit direction during I/O of serial data as listed in Table 20.2-2 "Settings of the Bit Direction Select Bit". Data can be transferred from the least significant bit (LSB first) or the most significant bit (MSB first). This bit is initialized to "0" and is a read/write bit. Table 20.2-2 Settings of the Bit Direction Select Bit BDS Function 0 LSB first [Initial value] 1 MSB first This bit is initialized to "0" and is a read/write bit. Note: Set the bit direction select bit before writing data in the SDR. [Bit 1] Serial output enable bit (SOE) This bit controls the outputs of the serial I/O output external pins (SOT2, SOT3, and SOT4) as listed in Table 20.2-3 "Functions of the Serial Out Enable Bit (SOE)". Table 20.2-3 Functions of the Serial Out Enable Bit (SOE) SOE Function 0 General-purpose port pins [Initial value] 1 Serial data outputs This bit is initialized to "0" by a reset and is a read/write bit. [Bit 0] SCK1 output enable bit (SCOE) This bit controls the outputs of the shift clock external pins (SCK2, SCK3, and SCK4) as listed in Table 20.2-4 "Functions of the SCK1 (Output Enable) Bit (SCOE)". Set this bit to "0" to transfer data for each instruction in the external shift clock mode. This bit is initialized to "0" by a reset and is a read/write bit. Table 20.2-4 Functions of the SCK1 (Output Enable) Bit (SCOE) SCOE Function 0 General-purpose pins, transfer for each instruction [Initial value] 1 Shift clock output pins [Bits 15, 14, and 13] Serial shift clock mode bits (SMD2, SMD1, and SMD0) These bits select the serial shift clock mode as listed in Table 20.2-5 "Functions of the SMD0 to SMD2 (Serial Shift Clock Mode Selection Bit)". These bits are initialized to "000" by a reset. Writing these bits is prohibited during transfer. A shift clock can be selected among five internal shift clocks and an external shift clock. Do not set SMD2, SMD1, and SMD0 to "110" or "111" because these values are reserved. When SCOE is 0 for clock selection, ports that share the SCK1 or SCK2 pin can perform 336 20.2 Registers in the Extended Serial I/O Interface shift operations for each instruction. Table 20.2-5 Functions of the SMD0 to SMD2 (Serial Shift Clock Mode Selection Bit) φ = 16MHz div=8 φ = 8MHz div=4 φ = 4MHz div=4 SMD2 SMD1 SMD0 Divide factor A 0 0 0 2 1 MHz 1 MHz 500 KHz 0 0 1 4 500 KHz 500 KHz 250 KHz 0 1 0 16 125 KHz 125 KHz 62.5 KHz 0 1 1 32 62.5 KHz 62.5 KHz 31.25 KHz 1 0 0 64 31.25 KHz 31.25 KHz 15.625 KHz 1 0 1 1 External shift clock mode 1 1 0 — Reserved 1 1 1 — Reserved Table 20.2-6 Recommended Machine Cycles by Communication Prescaler (CDCR) Settings Machine clock MD D3 D2 D1 D0 Recommended machine cycle 3 1 1 1 0 1 6 MHz 4 1 1 1 0 0 8 MHz 5 1 1 0 1 1 10 MHz 6 1 1 0 1 0 12 MHz 7 1 1 0 0 1 14 MHz 8 1 1 0 0 0 16 MHz div* Note: • For details on the communication prescaler (CDCR), see Section "Communication Prescaler Control Register (CDCR)". • D3 to D0 are abbreviations for DIV0 to DIV3. [Bit 12] Serial I/O interrupt enable bit (SIE) This bit controls serial I/O interrupt requests as listed in Table 20.2-7 "Functions of the Serial I/O Interrupt Enable Bit". This bit is initialized to "0" by a reset and is a read/write bit. Table 20.2-7 Functions of the Serial I/O Interrupt Enable Bit SIE Function 0 Disables serial I/O interrupts. [Initial value] 1 Enables serial I/O interrupts. 337 CHAPTER 20 EXTENDED SERIAL I/O INTERFACE [Bit 11] Serial I/O interrupt request bit (SIR) When serial data transfer terminates, this bit is set to "1". When this bit is set to "1" in the interrupt enable state (when SIE is "1"), an interrupt request is issued to the CPU. The clear condition is dependent on the setting of the MODE bit. When the MODE bit is "0", the SIR bit is cleared by writing "0" in this bit. When the MODE bit is "1", the SIR bit is cleared by reading or writing the SDR. The SIR bit is also cleared by a reset or by writing "1" in the STOP bit regardless of which value is set in the MODE bit. Writing "1" in the SIR bit has no meaning. When a read-modify-write instruction reads the SIR bit, the read value is always "1". [Bit 10] Transfer status bit (BUSY) This bit indicates whether serial transfer is being executed. This bit is initialized to "0" by a reset and is a read-only bit. Table 20.2-8 Functions of the Transfer Status Bit (BUSY) BUSY Function 0 Stopped or serial data register R/W wait state [Initial value] 1 Serial transfer state [Bit 9] Stop bit (STOP) This bit forcibly stops serial transfer. Setting this bit to "1" places serial transfer in the stopped state with STOP set to 1. This bit is initialized to "1" by a reset and is a read/write bit. Table 20.2-9 Stop Bit Function STOP Function 0 Normal operation 1 Transfer stopped with STOP set to 1 [Initial value] [Bit 8] Start bit (STRT) This bit starts serial transfer. Writing "1" in this bit in the stopped state starts transfer. Writing "1" is ignored and writing "0" has no meaning during serial transfer or in the serial shift register R/W wait state. The read value is always "0". 338 20.2 Registers in the Extended Serial I/O Interface 20.2.2 Serial Shift Data Register (SDR) The serial shift data register (SDR) retains serial I/O transfer data. Writing and reading the SDR is prohibited during transfer. ■ Serial Shift Data Register (SDR) Figure 20.2-3 Serial Shift Data Register (SDR) Serial shift data register ch0 000004AH ch1 000004EH ch2 000007EH Read/Write Initial value 7 6 5 4 3 2 D7 D6 D5 D4 D3 D2 1 0 Bit No. D1 D0 SDR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 339 CHAPTER 20 EXTENDED SERIAL I/O INTERFACE 20.3 Operation of the Extended Serial I/O Interface The extended serial I/O interface consists of the serial mode control status register (SMCS) and shift register (SDR). It is used to input and output 8-bit serial data. ■ Operation of the Extended Serial I/O Interface The contents of the shift register are output to the serial output pin (SOT1 pin) in the bit serial mode in synchronization with the falling edge of the serial shift clock (external or internal clock). Data is input from the serial input pin (SIN1 pin) to the shift register (SDR) in the bit serial mode in synchronization with the rising edge of the clock. The shift direction (transfer from the MSB or LSB) can be selected using the bit direction bit (BDS) in the serial mode control status register (SMCS). When transfer terminates, the extended serial I/O interface enters the stopped state or data register R/W wait state according to the setting of the MODE bit in the serial mode control status register (SMCS). To create a transition from each state to the transfer state, proceed as follows: 340 • To return from the stopped state, write "0" in the STOP bit and "1" in the STRT bit (STOP and STRT can be set simultaneously). • To return from the serial shift data register R/W wait state, read or write the data register. 20.3 Operation of the Extended Serial I/O Interface 20.3.1 Shift Clock The two modes for the shift clock are as follows: internal shift clock mode and external shift clock mode. The mode is specified by SMCS settings. Switch the mode in the serial I/O stopped state. The stopped state can be checked by reading the BUSY bit. ■ Internal Shift Clock Mode By using the output of the communication prescaler, a shift clock with a 50% duty cycle can be delivered as synchronous timing output from the SCK pin. One-bit data is transferred for each clock. The transfer rate can be calculated as follows: transfer-rate (s) = A internal-clock-machine-cycle (Hz) A is the divide factor set by the SMD bits in the SMCS, 2, 4, 16, 32, or 64. ■ External Shift Clock Mode One-bit data is transferred for each clock in synchronization with the external shift clock input from the SCK pin. A transfer rate with a frequency from DC to 1 divided by five machine cycles is available. For example, when one machine cycle is 0.1 µs, a transfer rate of up to 2 MHz is available. Data can also be transferred for each instruction. To transfer data for each operation, effect the following settings: 1. Select the external shift clock mode and set the SCOE bit in the SMCS to "0", 2. Then write "1" in the direction register for one of the ports that share the SCK pin to set the port to the output mode. After effecting the above settings, write "1", then "0" in the port data register (PDR). The port value output to the SCK pin is fetched as the external clock and data is transferred. Start the shift clock from "H". Note: Writing the SMCS and SDR is prohibited during serial I/O operation. 341 CHAPTER 20 EXTENDED SERIAL I/O INTERFACE 20.3.2 Operating States of the Extended Serial I/O Interface The four operating states of the extended serial I/O interface are as follows: • STOP • Stopped • SDR R/W wait • Transfer ■ STOP State When a reset occurs or "1" is written in the STOP bit in the SMCS, the shift counter is initialized and SIR is set to "0". The extended serial I/O interface can return from the STOP state by setting "0" in STOP and "1" in STRT (can be set simultaneously). When STOP is 1, setting STRT to 1 cannot start transfer because the STOP bit has a higher priority than the STRT bit. ■ Stopped state When the MODE bit is "0" and transfer terminates, BUSY is set to "0" and SIR is set to "1" in the SMCS. The counter is initialized and the extended serial I/O interface enters the stopped state. By setting STRT to "1", the extended serial I/O interface returns from the stopped state and restarts transfer. ■ Serial data register R/W wait state When the MODE bit in the SMCS is "1" and serial transfer terminates, BUSY is set to "0" and SIR is set to "1". The extended serial I/O interface enters the serial data register R/W wait state. When the interrupt enable register indicates the enable state, an interrupt signal is output from this block. When the serial data register is read or written, BUSY is set to "1" and the extended serial I/O interface returns from the R/W wait state and restarts transfer. ■ Transfer state BUSY is "1" and the extended serial I/O interface is transferring serial data. A transition to the stopped or R/W wait state occurs depending on the MODE bit setting. Figure 20.3-1 "Diagram of Operation Transition of the Extended Serial I/O Interface" shows a diagram of operation transition from each state. Figure 20.3-2 "Conceptual Diagram of Read from and Write to the Serial Data Register" shows a conceptual diagram of read from and write to the serial data register. 342 20.3 Operation of the Extended Serial I/O Interface Figure 20.3-1 Diagram of Operation Transition of the Extended Serial I/O Interface Reset End of transfer End Transfer Serial data register R/W wait End R/W of the SDR Figure 20.3-2 Conceptual Diagram of Read from and Write to the Serial Data Register Data bus Serial data Data bus Read Write SIN Interrupt output SOT Extended serial I/O interface and Read Write Interrupt input Data bus Interrupt controller in Figure 20.3-2 are explained below. When MODE is 1, transfer terminates according to the shift clock counter. SIR is set to 1 and the extended serial I/O interface enters the read/write wait state. When the SIE bit is "1," the extended serial I/O interface generates an interrupt signal. When SIE indicates that the inactive state or transfer is stopped by writing "1" in STOP, the interface does not generate an interrupt signal. When the serial data register is read or written, the interrupt request is cleared and the interface starts serial transfer. 343 CHAPTER 20 EXTENDED SERIAL I/O INTERFACE 20.3.3 Operation Timings of the Extended Serial I/O Interface To start and stop shift operation, effect the following settings: Start: Set the STOP bit to "0" and STRT bit to "1" in the SMCS. Stop: Shift operation stops when transfer terminates or when STOP is set to 1. [Stop by setting STOP to 1 ] Shift operation stops and SIR remains set to 0 regardless of the value set in the MODE bit. [Stop at end of transfer] SIR is set to 1 and the shift operation stops regardless of the value set in the MODE bit. ■ Shift Operation Start/Stop Timings The BUSY bit is "1" in the serial transfer state or "0" in the stopped or R/W wait state regardless of the value set in the MODE bit. To check the transfer state, read this bit. Figure 20.3-3 Shift Operation Start/Stop Timings (Internal Clock) Internal shift clock mode (LSB first) "1" is output. SCK1,2 (Start of transfer) (End of transfer) When MODE is 0 STRT BUSY D07 (Data is retained.) SOT1,2 Note: DO7 to DO0 indicate output data. Figure 20.3-4 Shift Operation Start/Stop Timings (External Clock) External shift clock mode (LSB first) SCK1,2 STRT (Start of transfer) (End of transfer) When MODE is 0 BUSY SOT1,2 Note: DO7 to DO0 indicate output data. 344 DO7 (Data is retained.) 20.3 Operation of the Extended Serial I/O Interface Figure 20.3-5 Shift Operation Start/Stop Timings (When a Shift Operation is Performed in Accordance with Instructions in the External Shift Clock Mode) When a shift operation is performed in accordance with instructions in the external shift clock mode (LSB first) The SCK bit in the PDR is "0." The SCK bit in the PDR is "1." The SCK bit in the PDR is "0." (End of transfer) When MODE is 0 DO7 (Data is retained.) Note: DO7 to DO0 indicate output data. During a shift operation in accordance with instructions, when "1" is written in the bit corresponding to SCK in the PDR, "H" is output. When "0" is written, "L" is output (only when the external shift clock mode is selected and SCOE is 0). Figure 20.3-6 Stop Timing when the STOP Bit Is Set to "1" Stop by setting STOP to 1 (LSB first, internal clock mode) "1" is output. (Start of transfer) (End of transfer) When MODE is 0 DO5 (Data is retained.) Note: DO7 to DO0 indicate output data. 345 CHAPTER 20 EXTENDED SERIAL I/O INTERFACE 20.3.4 Serial Data I/O Shift Timings During serial data transfer, data from the serial output pin (SOT2) is output at the falling edge of the shift clock and data from the serial input pin (SIN) is input at the rising edge. ■ Serial Data I/O Shift Timings Figure 20.3-7 "Serial Data I/O Shift Timings" shows the serial data I/O shift timings in the LSB and MSB first modes. Figure 20.3-7 Serial Data I/O Shift Timings LSB first (when the BDS bit is "0") SIN input SOT output MSB first (when the BDS bit is "1") SIN input SOT output 346 20.3 Operation of the Extended Serial I/O Interface 20.3.5 Interrupt Function of the Extended Serial I/O Interface The extended serial I/O interface can issue interrupt requests to the CPU. At the end of data transfer, when the SIR bit is set and the SIE bit in the SMCS is "1", the extended serial I/O interface outputs an interrupt request to the CPU. ■ Interrupt Function of the Extended Serial I/O Interface Figure 20.3-8 "Interrupt Signal Output Timing of the Extended Serial I/O Interface" shows the interrupt signal output timing of the extended serial I/O interface. Figure 20.3-8 Interrupt Signal Output Timing of the Extended Serial I/O Interface (End of transfer) (*1) RD/WR of the SDR DO7 (Data is retained.) (*1) When MODE is 1. 347 CHAPTER 20 EXTENDED SERIAL I/O INTERFACE 348 CHAPTER 21 I2C INTERFACE This chapter describes the functions and operations of the I2C interface. 21.1 "Overview of the I2C Interface" 21.2 "Block Diagram of the I2C Interface" 21.3 "I2C Interface Registers" 21.4 "Operation of the I2C Interface" 349 CHAPTER 21 I2C INTERFACE 21.1 Overview of the I2C Interface The I2C interface operates as a master or slave device on the I2C bus at the serial I/O port that supports an inter IC bus. ■ Features of the I2C Interface MB90570 series micro controllers have one channel of I2C built-in interface. The features of the I2C interface are: 350 • Master/slave transmission • Arbitration function • Clock synchronization function • Function to detect the slave address and general call address • Function to detect the transfer direction • Function to repeat or detect the start condition • Detection function of bus errors • The I2C corresponds to the standard mode (serial clock frequency: maximum 100 kHz) for the I2C. 21.2 Block Diagram of the I2C Interface 21.2 Block Diagram of the I2C Interface Figure 21.2-1 "Block Diagram of the I2C Interface" is a block diagram of the I2C Interface. ■ Block Diagram of the I2C Interface Figure 21.2-1 Block Diagram of the I2C Interface I2C enabled Internal Data Bus Clock division 1 Machine clock Clock selection 1 Clock division 2 Generation of the shift clock Clock selection 2 Edge change timing of the shift clock Bus busy Repeat start Detection of start and stop condition Send/ Receive Error Detection of an arbitration loss Interrupt request Termination Start Master ACK allowed GC-ACK allowed Generation of start and stop condition Slave Comparison of Global call the slave address 351 CHAPTER 21 I2C INTERFACE 21.3 I2C Interface Registers The I2C interface has 5 types of register as follows: • Bus status register • Bus control register • Clock control register • Address register • Data register ■ Registers of the I2C Interface Figure 21.3-1 Registers of the I2C Interface Bus status register Address: 000068H Read/write Initial value Bus control register Address: 000069H 7 6 5 4 3 2 1 BB RSC AL LRB TRX AAS GCA FBT Address register Address: 00006BH (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 15 14 13 12 11 10 9 8 Bit No. SCC MSS INT IBCR ACK GCAA INTE (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) 7 6 5 4 3 2 1 0 Bit No. EN CS4 CS3 CS2 CS1 CS0 ICCR (-) (-) (-) (-) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (X) (X) (X) (X) (X) 15 14 13 12 11 10 9 8 Bit No. A6 A5 A4 A3 A2 A1 A0 IADR Read/write (-) Initial value (-) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 Bit No. D7 D6 D5 D4 D3 D2 D1 D0 IDAR Data register Address: 00006CH Read/write Initial value 352 IBSR (R) (0) Clock control register Address: 00006AH Read/write Initial value Bit No. (R) (0) BER BEIE Read/write Initial value 0 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) 21.3 I2C Interface Registers 21.3.1 Bus Status Register (IBSR) The bus status register (IBSR) has the following functions: • • • • • • • • Indicates the status of the I2C Detection of a repeated start condition Detection of arbitration losses Storing acknowledgements Detection of the first byte Detection of addressing Detection of the general call address Data transfer ■ Bus Status Register (IBSR) Figure 21.3-2 Bus Status Register (IBSR) Bus status register Address: 000068 Read/write Initial value 7 6 5 4 3 2 1 BB RSC AL LRB TRX AAS GCA FBT (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) (R) (0) 0 Bit No. IBSR [bit 7]: BB (Bus Busy) This bit shows the status of the I2C bus. Table 21.3-1 BB (Bus Busy) Bit Function BB Function 0 Stop condition is detected. [Initial value] 1 Start condition is detected (indicating that the bus is in use). [bit 6]: RSC (Repeated Start Condition) This bit shows whether the repeated start condition is detected. This bit is cleared when (1) "0" is written to the INT bit, (2) no addressing is made in slave mode, (3) the start condition is detected while the bus stops, or (4) the stop condition is detected. Table 21.3-2 RSC (Repeated Start Condition) Bit Function RSC Function 0 Repeated start condition is not detected. [Initial value] 1 Start condition is detected again when the bus is in use. 353 CHAPTER 21 I2C INTERFACE [bit 5]: AL (Arbitration Lost) This bit shows whether an arbitration loss is detected. This bit is cleared by writing "0" to the INT bit. Table 21.3-3 AL (Arbritration Lost) Bit Function AL Function 0 No arbitration loss is detected. [Initial value] 1 Either an arbitration loss has occurred during transmission by the master, or "1" has been written to the MSS bit when another system is using the bus. [bit 4]: LRB (Last Received Bit) This bit is used to store the acknowledgement. This bit stores the acknowledgement from the receiving side. This bit is cleared upon the detection of the start or stop condition. [bit 3]: TRX (Transfer/Receive) This bit shows the status of data transfer. Table 21.3-4 TRX (Transfer/Receive) Bit Function TRX Function 0 Receiving [Initial value] 1 Sending [bit 2]: AAS (Addressed As Slave) This bit is used to detect addressing. This bit is cleared by the detection of the start or stop condition. Table 21.3-5 ASS (Addressed As Slave) Bit Function AAS Function 0 No addressing is made in slave mode. [Initial value] 1 Addressing is made in slave mode. [bit 1]: GCA (General Call Address) This bit is used to detect the general call address (00H). This bit is cleared by the detection of the start or stop condition. Table 21.3-6 GCA (General Call Address) Bit Function GCA 354 Function 0 The general call address is not received in slave mode. 1 The general call address is received in slave mode. 21.3 I2C Interface Registers [bit 0]: FBT (First Byte Transfer) This bit is used to detect the first byte. If this bit is set to "1" by the detection of the start condition, it is cleared when "0" is written to the INT bit or when no addressing is made in slave mode. Table 21.3-7 FBT (First Byte Transfer) Bit Function FBT Function 0 The received data is not the first byte. 1 The received data is the first byte (the address data). 355 CHAPTER 21 I2C INTERFACE 21.3.2 Bus Control Register (IBCR) The bus control register has the following functions: • Interrupt request and interrupt enable • Generation of the start condition • Selection between the master and slave • Enable to generate acknowledgements ■ Bus Control Register (IBCR) Figure 21.3-3 IBCR (Bus Control Register) Bus control register Address: 000069 Read/write Initial value 15 14 13 12 BER BEIE SCC MSS 11 10 9 ACK GCAA INTE 8 Bit No. INT IBCR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) [bit 15]: BER (Bus ERror) This bit is for the bus error interrupt request flag. When this bit is set, the EN bit of the CCR register is cleared, the I2C interface is suspended, and data transmission is aborted. Table 21.3-8 BER (Bus ERror) Bit Function BER Function For writing For reading 0 Clears the bus error interrupt request flag. [Initial value] 1 No meaning 0 No bus error is detected. [Initial value] 1 An invalid start or stop condition is detected during the data transmission. [bit 14]: BEIE (Bus Error Interrupt Enable) This bit is the interrupt enable bit for bus errors. When this bit is "1" and the BER bit is "1", the interrupt occurs. Table 21.3-9 BEIE (Bus Error Interrupt Enable) Bit Function BEIE 356 Function 0 The bus error interrupt is disabled. [Initial value] 1 The bus error interrupt is enabled. 21.3 I2C Interface Registers [bit 13]: SCC (Start Condition Continue) This bit generates the start condition. The read value of this bit is always "0". Table 21.3-10 SCC (Start Condition Continue) Bit Function when Writing SCC Function 0 No meaning [Initial value] 1 Generates the start condition again when the master is transmitting. [bit 12]: MSS (Master Slave Select) This bit is used for selection between the master and slave. This bit is cleared when an arbitration loss occurs during transmission by the master, thereby enabling slave mode. Table 21.3-11 MSS (Master Slave Select) Function MSS Function 0 Slave mode is turned on after the generation of a stop condition and termination of the transmission. 1 Master mode is turned on, the start condition is generated, and transmission starts [bit 11]: ACK (ACKnowledge) This bit enables the generation of an acknowledgement upon receipt of data. This bit is invalid when address data is received in slave mode. Table 21.3-12 ACK (ACKnowledge) Function ACK Function 0 No acknowledgement is generated. [Initial value] 1 An acknowledgement is generated. [bit 10]: GCAA (General Call Address Acknowledge) This bit enables generation of an acknowledgement upon receipt of the general call address. Table 21.3-13 GCAA (General Call Address Acknowledge) Function GCAA Function 0 No acknowledgement is generated. [Initial value] 1 An acknowledgement is generated. 357 CHAPTER 21 I2C INTERFACE [bit 9]: INTE (INTerrupt Enable) This is the interrupt enable bit. When this bit is "1" and the INT bit is "1", an interrupt occurs. Table 21.3-14 INTE (INTerrupt Enable) Function INTE Function 0 Interrupts are disabled. 1 Interrupts are enabled. [bit 8]: INT (INTerrupt) This bit is for the interrupt request flag for transmission termination. When this bit is "1", the SCL line stays at the "L" level. The next byte is transmitted after this bit is cleared by writing "0" and the SCL line is freed. In master mode, generation of the start or stop condition resets this bit to "0". Table 21.3-15 INT (INTerrupt) Function INT Function For writing For reading 0 Clears the interrupt request flag for transmission termination. [Initial value] 1 No meaning 0 The transmission is not terminated. [Initial value] 1 This is set when transmission of one byte, including the acknowledgement bit, is terminated and any of the following conditions occur: • The device is the bus master. • The device is the addressed slave. • The general call address is received. • An arbitration loss has occurred. • An attempt was made to generate the start condition while another system was using the bus. ■ Competition among the SCC, MSS, and INT Bits When the SCC, MSS, and INT bits are written to at the same time, there is competition for the transmission of the next byte, the start condition generation, and the stop condition generation. Prioritization is as follows: 1. Transmission of the next byte and stop condition generation • When "0" is written to the INT bit and MSS bit, the MSS bit takes precedence and the stop condition is generated. 2. Transmission of the next byte and start condition generation • When "0" is written to the INT bit and "1" to the SCC bit, the SCC bit takes precedence and the start condition is generated. 3. Start condition generation and stop condition generation • 358 Writing "1" to the SCC bit and "0" to the MSS bit at the same time is prohibited. 21.3 I2C Interface Registers 21.3.3 Clock Control Register (ICCR) The clock control register has the following functions: • Enabling I2C interface operation • Setting the frequency for the serial clock ■ Clock Control Register (ICCR) Figure 21.3-4 Clock Control Register (ICCR) Clock control register Address: 00006A 7 6 5 EN Read/write Initial value (-) (-) (-) (-) 4 3 2 1 0 CS4 CS3 CS2 CS1 CS0 Bit No. ICCR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (X) (X) (X) (X) (X) [bit 7], [bit 6]: Unused bits [bit 5]: EN (ENable) This bit enables the I2C interface to operate. When this bit is "0", the bits of the BSR register and the BCR register (except for the BER and BEIE bits) are cleared. When the BER bit is set, this bit is cleared. Table 21.3-16 EN (Enable) Bit Function EN Function 0 Operation disabled 1 Operation enabled [bit 4] to [bit 0]: CS4-0 (Clock Period Select 4-0) This bit is used to set the frequency of the serial clock. The frequency of the shift clock (fsck) is set according to the following calculation: fsck = m×n+4 : Machine clock Note: • Do not set the serial clock frequency to 100 kHz or more. • Four extra (+4) cycles are the minimum overhead for checking the changes of the output level of the SCL pin. When the SCL pin starts up with a long delay, or when the slave device prolongs the clock, the value increases. 359 CHAPTER 21 I2C INTERFACE Table 21.3-17 "Settings of Serial Clock Frequency (CS4 and CS3)"and Table 21.3-18 "Settings of Serial Clock Frequency (CS2 to CS0)" show the values of m and n for CS4 to CS0. Table 21.3-17 Settings of Serial Clock Frequency (CS4 and CS3) m CS4 CS3 5 0 0 6 0 1 7 1 0 8 1 1 Table 21.3-18 Settings of Serial Clock Frequency (CS2 to CS0) n CS2 CS1 CS0 4 0 0 0 8 0 0 1 16 0 1 0 32 0 1 1 64 1 0 0 128 1 0 1 256 1 1 0 512 1 1 1 When the values (m and n) are set, for example, to m=5 and n=32 with (φ=16 MHz, the serial clock frequency is determined to be 97.561 kHz. Notes: According to the setting for the I2C operation enable bit (EN bit), output at the I2C common port pin is determined as described below. • When the operation is enabled (EN bit=1): An I2C output signal is output at the SDA/PA6 pin and the SCL/PA7 pin, irrespective of the input and output setting values for the DDRA (bit No.6) and the DDRA (bit No.7). • When the operation is disabled (EN bit=0): If the output setting is such that the DDRA (bit No.6) equals 1 and the DDRA (bit No.7) equals 1, the setting values of PA6 and PA7 in the PDRA register are output at the SDA/PA6 pin and the SCL/PA7 pin, respectively. Notes: When the I2C is in operation and an RMW-based instruction is executed on the port data register (PDRA) in the same series as the I2C pin, the pin levels of PDRA bit No.6 and PDRA bit No.7 are loaded with a reading operation. Therefore, note that the values for PDRA bit No.6 and PDRA bit No.7 vary depending on the levels at the PA7/SCL pin and the PA6/SDA pin. The following chart shows the change timing for the I2C common port. 360 21.3 I2C Interface Registers Operation timing for the I2C common port I2C operation enabled/disabled I2C operation enabled: EN bit=1 I2C operation disabled: EN bit=0 SCL/PA7 When DDRA7=0: High impedance for input setting When DDRA7=1: Changed value for PDRA is output. SDA/PA6 When DDRA6=0: High impedance for input setting When DDRA6=1: Changed value for PDRA is output. Timing for RMW-based instruction execution on the PDRA register PDRA register Previous data Execution of RMW-based instruction Varies depending on the level in effect when an RMW-based instruction is in operation. See Appendix B.8 "F2MC-16LX Instruction List", for details on RMW-based instructions. 361 CHAPTER 21 I2C INTERFACE 21.3.4 Address Register (IADR) The address register (IADR) is used for specifying the slave address. ■ Address Register (IADR) Figure 21.3-5 IADR (Address Register) Address register Address: 00006B Read/write Initial value 15 (-) (-) 14 13 12 11 10 9 8 A6 A5 A4 A3 A2 A1 A0 Bit No. IADR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) [bit 14] to [bit 8]: Slave address bits(A6-A0) This register is used for specifying the slave address. In slave mode, the received address data is compared with the DAR register and if a match occurs an acknowledgement is sent to the master. 362 21.3 I2C Interface Registers 21.3.5 Data Register(IDAR) The data register (IDAR) is used for serial transmission. ■ Data Register (IDAR) Figure 21.3-6 Data Register (IDAR) Data register Address: 00006C Read/write Initial value 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit No. IDAR (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (X) (X) (X) (X) (X) (X) (X) (X) [bit 7] to [bit 0]: Data bits (D7-D0) The data register is used for serial transmission. Data is transferred, starting from the MSB. The data output value is "1" when data is being received (TRX=0). The writing side of this register is double-buffered. When the bus is in use (BB=1), the written data is loaded in the register for serial transmission whenever one-byte data is transmitted. The data is read directly from the register for serial transmission, indicating the received data is available only when the INT bit is set. 363 CHAPTER 21 I2C INTERFACE 21.4 Operation of the I2C Interface The I2C bus is used for communication with two bi-directional bus lines, a serial data line (SDA) and a serial clock line (SCL). The I2C Interface has two corresponding open drain input-output pins (SDA and SCL) to support the wired logic. ■ Start Condition If "1" is written to the MSS bit when the bus is free (BB=0 and MSS=0), the I2C interface is in master mode and the start condition is generated at the same time. In master mode, the start condition can be regenerated by writing "1" to the SCC bit even if the bus is in use (BB=1). The start condition can be generated as follows: • Write "1" to the MSS bit when the bus is not in use (MSS=0*BB=0*INT=0*AL=0). • Write "1" to the SCC (MSS=1*BB=1*INT=1*AL=0). bit in the interrupt state in bus master mode If "1" is written to the MSS bit when another system (being idle) is using the bus, the AL bit is set to "1". Under other conditions, writing "1" to the MSS bit or the SCC bit is ignored. ■ Stop condition Writing "0" to the MSS bit in master mode (MSS=1) generates the stop condition and the mode switches to slave mode. The condition necessary to generate the stop condition is as follows: • Write "0" to the MSS (MSS=1*BB=1*INT=1*AL=0). bit in the interrupt state in bus master mode Under other conditions, writing "0" to the MSS bit is ignored. ■ Addressing In master mode, after the start condition is generated, the BB and TRX bits are set to "1" and the contents of the IDAR register are output starting from the MSB. When the acknowledgement is received from the slave after the address data is sent, bit 0 of the send data (bit 0 of the sent IDAR register) is reversed and stored in the TRX bit. In slave mode, after the start condition is generated, the BB bit is set to "1", the TRX bit is set to "0", and the send data from the master is received by the IDAR register. After the address data is received, the IDAR register is compared with the IADR register. If a match occurs, the AAS bit is set to "1" and the acknowledgement is sent to the master. Bit 0 of the received data (bit 0 of the received IDAR register) is then stored in the TRX bit. ■ Arbitration Arbitration occurs if another master is sending data at the same time as the master. When the send data is "1" and the data on the SDA line is at "L" level, the sender assumes arbitration is lost and the AL bit is set to "1". As previously described, the AL bit is also set to "1" when the start condition is generated while the bus is in use. When the AL bit is set to "1", the MSS bit and TRX bit are set to "0" and the mode switches to slave receive mode. ■ Acknowledgement An acknowledgement is sent from the receiver to the sender. When data is received, the use of acknowledgement can be selected by setting the ACK bit. When data is sent, the 364 21.4 Operation of the I2C Interface acknowledgement from the receiver is stored in the LRB bit. If the slave does not receive the acknowledgement from the master when sending data, the TRX bit is set to "0" and the mode switches to slave receive mode, thereby enabling the master to generate the stop condition when the slave frees the SCL line. ■ Bus Error If any of the following occur, a bus error is determined and the I2C interface is halted: • A basic specifications error is detected on the I2C bus during data transmission (including the ACK bit). • The stop condition is detected in master mode. • A basic specifications error is detected on the I2C bus when the bus is idle. ■ Execution of Start Condition Generation Instruction When SDA="L" and SCL="L" When a start condition generation instruction (for writing 1 in the MSS bit) is executed under the conditions SDA="L" and SCL="L", BB="0" and AL="1" are established. In this case, the transfer is not completed and so the transfer complete interrupt request flag (INT bit) is not set. This condition is detected by monitoring the BB and AL bits via the program. Figure 21.4-1 Change Timing for Each Flag when a Start Condition Generation Instruction is Executed Under SDA="L" and SCL"L" SCL "L" SDA "L" Set the MSS bit to "1" Start condition Arbitration Interruption Bus busy AL bit of IBSR INT bit of IBCR "L" BB bit of IBSR "L" 365 CHAPTER 21 I2C INTERFACE 21.4.1 Operation Flow of the I2C Interface Figure 21.4-2 "Examples: Operation Flow of Master Send/Receive Program (with Interruption) for I2C Interface" shows example of the operation flow of the master send/receive program (with interruption) for the I2C Interface. Figure 21.4-3 "Examples: Operation Flow of Slave Program (with Interruption) for I2C Interface" shows example of the operation flow of the slave program (with interruption) for the I2C Interface. ■ Operation Flow of the I2C Interface Figure 21.4-2 Examples: Operation Flow of Master Send/Receive Program (with Interruption) for I2C Interface Main routine Interrupt routine Start Start Set the slave address Bus error occurred? YES 2 Stop condition generated Clear the bus error interrupt factor 3 AL occurred? YES Master? Master receive Set the number of receiving data bytes yes BB bit=1? NO Was ACK returned? RETI Acknowledge occurrence enabled NO 1 To the slave program interrupt routine YES Is data direction bit (TRX bit) equal to 1? BB bit=1? NO Is the number of remaining receiving bytes equal to 0? yes YES Is the number of remaining send bytes equal to no Start condition generation in slave address sending Start condition generation in slave address sending 3 YES Receiving the slave address set (data direction bit=1) Sending the slave address set (data direction bit=0) NO Initial setting for I2C 3 no Master send NO Set the number of sending data bytes NO 1 Wait for a certain amount of time Set the sending data YES NO NO I 2C LOOP BB bit=0 and AL bit=1? operation disabled LOOP Is the number of remaining receiving bytes equal to 1? 1 YES NO Acknowledge occurrence enabled Acknowledge occurrence disabled YES Clear the transfer termination interrupt factor I2C operation disabled Is the operation targeted for receiving the first byte? NO RETI Decrement of receiving byte count Store the receiving data onto the RAM Clear the transfer termination interrupt factor RETI 366 yes NO Decrement of sending byte count Wait for a certain amount of time BB bit=0 and AL bit=1? I2C operation enabled YES Master receive operation? YES 2 RETI NO I2C operation enabled 1 YES 21.4 Operation of the I2C Interface Figure 21.4-3 Examples: Operation Flow of Slave Program (with Interruption) for I2C Interface Main routine Start Set the slave address I2C operation enabled Set to the slave mode Interrupt routine 1 2 Clear the transfer termination interrupt factor Clear the bus error interrupt factor Start YES Bus error occurred? 2 NO I2C operation enabled RETI NO Is addressing completed? 1 Initial setting for I2C YES RETI LOOP Is the data direction bit (TRX bit) equal to 1? NO Slave receiving Slave sending YES Does the receiving data mean address? NO Is the ACK returned? 1 YES NO Store the receiving data onto the RAM YES Set the sending data Clear the transfer termination interrupt factor Clear the transfer termination interrupt factor RETI RETI 367 CHAPTER 21 I2C INTERFACE 368 CHAPTER 22 CHIP SELECT FUNCTION This chapter describes the functions and operations of the chip select function. 22.1 "Overview of the Chip Select Function" 22.2 "Register of the Chip Select Function" 22.3 "Operation of the Chip Select Function" 22.4 "Decode Address Space of the Chip Select Function" 369 CHAPTER 22 CHIP SELECT FUNCTION 22.1 Overview of the Chip Select Function This chip select function module generates chip select signals to facilitate connection to memory or an I/O device. ■ Overview of the Chip Select Function There are eight chip select output pins. The area specified by the hardware is set to each pin register, and a select signal is output from a pin upon the detection of access to the address. ■ Block Diagram of the Chip Select Function Figure 22.1-1 Block Diagram of the Chip Select Function Address (from CPU) Address decoder Address decoder Decode signal Program area Decode (for the program ROM area) 370 Chip select control register 0 Select and set Selector Chip select control register 1 Select and set Selector Chip select control register 5 Select and set Selector Chip select control register 6 Select and set Selector 22.2 Register of the Chip Select Function 22.2 Register of the Chip Select Function The following is the only register of the chip select function: • Chip select control register (CSCR0 to CSCR6) ■ Chip Select Control Register (CSCR0 to CSCR6) Figure 22.2-1 Chip Select Control Register (CSCR0 to CSCR6) Address H H H Address H H Chip select control register (Odd numbers: CSCR1/3/5) Chip select control register (Even numbers: CSCR0/2/4/6) H H [bit 15/07 to 12/04]: Unused bits These bits are not used, and the bit read values are not defined. [bit 11/03]: ACTL This bit is used to set the active level of the CS0 to CS6 pins. Operation is set as follows: • "0": The CS0 to CS6 pins output "L" at decoding. • "1": The CS0 to CS6 pins output "H" at decoding. [bit 10/02]: OPEL This bit is used to determine whether to enable the external output of the CS0 to CS6 pins. The settings are as follows: • "0": Decode output from the CS0 to CS6 pins is prohibited. • "1": Decode output from the CS0 to CS6 pins is allowed. [bit 09/01 to 08/00] CSA1, CSA0 These bits render the address decode range (ROM/RAM/external circuit) of each chip select pins selectable. See Table 22.4-1 "Decode Address Spaces" for sizes and ranges. 371 CHAPTER 22 CHIP SELECT FUNCTION 22.3 Operation of the Chip Select Function Chip select is activated according to the settings of the output setting register by decoding the highest and lowest bytes of the address of the data or program to which the CPU obtains access. ■ Operation of the Chip Select Function The chip select function of this module is activating the signals of the CS0 to CS7 pins when the CPU obtains access to the area set in the CSA1 to 0 bits of the output setting register according to Table 22.4-1 "Decode Address Spaces". The output can be masked by the OPEL bit of the output setting register. The active level of the CS0 to 7 pins can be altered using the ACTL bit of the output setting register. Figure 22.3-1 Examples: Operation of the Chip Select Function [Example 1] Address (Active) Select Decode Register setting (CSCR0) [Example 2] Address Register setting (CSCR0) Register setting (CSCR1) 372 Select Decode (Active) 22.4 Decode Address Space of the Chip Select Function 22.4 Decode Address Space of the Chip Select Function Table 22.4-1 "Decode Address Spaces" shows decode address spaces of the chip select function. Figure 22.4-1 "Map of the Decode Address Spaces" shows a map of decode address spaces. Figure 22.4-2 "CS0 Output after a reset is cleared" shows CS0 output after a reset is cleared. ■ Decode Address Spaces of the Chip Select Function Table 22.4-1 Decode Address Spaces CSA Pin Decode space Bytes of the area 1 0 0 0 F00000h to FFFFFFh 1 Mbyte 0 1 F80000h to FFFFFFh 512 Kbyte 1 0 FE0000h to FFFFFFh 128 Kbyte 1 1 — Prohibited 0 0 E00000h to EFFFFFh 1 Mbyte 0 1 F00000h to F7FFFFh 512 Kbyte 1 0 FC0000h to FDFFFFh 128 Kbyte 1 1 68FF80h to 68FFFFh 128 byte 0 0 003000h to 003FFFh 4 Kbyte 0 1 FA0000h to FBFFFFh 128 Kbyte 1 0 68FF80h to 68FFFFh 128 byte 1 1 68FF00h to 68FF7Fh 128 byte 0 0 F80000h to F9FFFFh 128 Kbyte 0 1 68FF00h to 68FF7Fh 128 byte 1 0 68FE80h to 68FEFFh 128 byte 1 1 — 0 0 002800h to 002FFFh 2 Kbyte 0 1 68FE80h to 68FEFFh 128 byte 1 0 — Prohibited 1 1 — Prohibited CS0 CS1 CS2 CS3 Prohibited CS4 Remark This decode address apace selection is activated when the program area or the program vector is to be fetched. This decode address space selection is used for the ROM or RAM area connection, or the external memory circuit connection. This decode address space selection is used for the ROM or RAM area connection, or the external memory circuit connection. This decode address space selection is used for the ROM or RAM area connection, or the external memory circuit connection. This decode address space selection is used for the ROM or RAM area connection, or the external memory circuit connection. 373 CHAPTER 22 CHIP SELECT FUNCTION Table 22.4-1 Decode Address Spaces (Continued) CSA Pin Decode space Bytes of the area 0 0 0 68FF80h to 68FFFFh 0 1 — Prohibited 1 0 — Prohibited 1 1 — Prohibited 0 0 68FF00h to 68FF7h 0 1 — Prohibited 1 0 — Prohibited 1 1 — Prohibited This decode address space selection is used for the ROM or RAM area connection, or the external memory circuit connection. * * — Prohibited Prohibited 128 byte CS5 128 byte CS6 CS7 Remark 1 This decode address space selection is used for the ROM or RAM area connection, or the external memory circuit connection. Note: When the mode pin is set to external ROM, the CS0 pin outputs a decode signal in the space of addresses F00000H to FFFFFFH (one megabyte), the area for program ROM, to fetch program vector immediately after reset (the initial status). In such a case, the CS0 pin must be dedicated to be used for the program ROM selection. The active level of this pin is "L" output. In the initial status, the chip select decode signal pin is set to an input pin by the port function. Rewrite setting registers before using. 374 22.4 Decode Address Space of the Chip Select Function Figure 22.4-1 Map of the Decode Address Spaces CS0 CS1 CS2 CS3 CS4 1 001 - 0011 0 010 - 0101 0011 0101 001 010 - Pin CSA CS5 CS6 00 -- 0 --- 0 --- 01 -- 0 --- 0 --- FFFFFFh FE0000h FC0000h FA0000h Address space F80000h F00000h E00000h 690000h 68FF80h 68FF00h 68FE80h 004000h 003000h 002800h 000100h Figure 22.4-2 CS0 Output after a reset is cleared RSTX CS Address output FFFFDCH 375 CHAPTER 22 CHIP SELECT FUNCTION 376 CHAPTER 23 CLOCK MONITOR FUNCTION This chapter describes the functions and operations of the clock monitor function. 23.1 "Overview of the Clock Monitor Function" 23.2 "Clock Output Enable Register (CLKR)" 377 CHAPTER 23 CLOCK MONITOR FUNCTION 23.1 Clock Monitor Function The clock monitor function is output a division clock (a clock for monitoring) from the clock monitor CKOT pin. ■ Block Diagram of the Clock Monitor Internal Data Bus Figure 23.1-1 Block Diagram of the Clock Monitor 378 Machine clock Division circuit 23.2 Clock Output Enable Register (CLKR) 23.2 Clock Output Enable Register (CLKR) The clock output enable register (CLKR) selects the CKOT output enable and the clock output frequency. ■ Clock Output Enable Register (CLKR) Figure 23.2-1 Clock Output Enable Register (CLKR) Clock output enable register Bit No. Address: 0003EH Read/write Initial value [bit 7, 6, and 5] Unused bit [bit 3] CKEN This is the CKOT output enable bit. Table 23.2-1 CKEN Bit Function CKEN Function 0 Normal port 1 CKOT output [bit 2, 1, 0] FRQ2, FRQ1, FRQ0 This bit is used to select the clock output frequency. Table 23.2-2 FRQ2, FRQ1, FRQ0 (Clock Output Frequency Selection Bit) Function FRQ2 FRQ1 FRQ0 Output clock φ=16 MHz φ=8 MHz φ=4 MHz 0 0 0 21/φ 125 ns 250 ns 500 ns 0 0 1 21/φ 250 ns 500 ns 1 µs 0 1 0 23/φ 500 ns 1 µs 2 µs 0 1 1 24/φ 1 µs 2 µs 4 µs 1 0 0 25/φ 2 µs 4 µs 8 µs 1 0 1 26/φ 4 µs 8 µs 16 µs 1 1 0 27/φ 8 µs 16 µs 32 µs 1 1 1 28/φ 16 µs 32 µs 64 µs 379 CHAPTER 23 CLOCK MONITOR FUNCTION 380 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION This chapter describes the functions and operation of the address match detection function. 24.1 "Overview of the Address Match Detection Function" 24.2 "Registers of the Address Match Detection Function" 24.3 "Operation of the Address Match Detection Function" 24.4 "Example of the Address Match Detection Function" 24.5 "Example and Flow of Program Patch Processing" 381 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.1 Overview of the Address Match Detection Function When an address matches the value set in the address detection register, the instruction code to be read by the CPU is replaced with the INT9 instruction code (01H). The CPU then executes the INT9 instruction when executing a specified instruction. Program patching is enabled by processing the INT9 interrupt routine. Each of the two address detection registers has an interrupt enable bit. When an address matches the value set in the address detection register and the interrupt enable bit is "1", instruction code to be read by the CPU is replaced with the INT9 instruction code. ■ Block Diagram of the Address Match Detection Function Address latch Address detection register Enable bit Comparison Internal Data Bus Figure 24.1-1 Block Diagram of the Address Match Detection Function INT9 instruction MB90570 Series CPU core Note: If the address detection register is set with a value other than the address of the first byte of the instruction, this function does not work normally, which causes the data of the set address to change to "01H", which in turn results in the execution of an incorrect instruction or access to an incorrect address. Confirm that the interrupt enable bit is "0" before changing the settings of the address detection registers. If the setting is changed when the interrupt enable bit is "1", an incorrect address detection is performed during writing and an illegal operation may occur. 382 24.2 Registers of the Address Match Detection Function 24.2 Registers of the Address Match Detection Function There are two registers for the address match detection function. • Program address detection register (PADR0 and PADR1). • Program address detection control status register (PACSR). ■ Registers of the Address Match Detection Function Figure 24.2-1 Registers of the Address Match Detection Function Program address detection register bit23 bit16 bit15 bit8 bit7 bit0 PADR0 Address: 1FF2H/ 1FF1H/ 1FF0H bit23 bit16 bit15 bit8 bit7 Address: 009EH Read/Write Initial value Reserved Reserved Reserved Reserved (-) (0) (-) (0) (-) (0) (-) (0) 3 AD1E 2 Reserved Initial value R/W Not defined R/W Not defined bit0 PADR1 Address: 1FF5H/ 1FF4H/ 1FF3H Program address detection control status register 7 6 5 4 Access 1 AD0E 0 Reserved Bit No. PACSR (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) 383 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.2.1 Program Address Detection Registers (PADR0 and PADR1) These registers compare the address with the value written in each register. If a match occurs when the interrupt enable bit corresponding to PACSR register is "1", and the CPU is requested to issue the INT9 instruction. When the corresponding interrupt enable bit is "0", an event does not occur. ■ Program Address Detection Registers (PADR0 and PADR1) Figure 24.2-2 Program Address Detection Registers (PADR0 and PADR1) Program address detection register bit23 bit16 bit15 bit8 bit7 bit0 PADR0 Address: 1FF2H/ 1FF1H/ 1FF0H bit23 bit16 bit15 bit8 bit7 Access Initial value R/W Not defined R/W Not defined bit0 PADR1 Address: 1FF5H/ 1FF4H/ 1FF3H The correspondence of PADR0/1 Register and PACSR Register is as shown below: Table 24.2-1 Correspondence of PADR0/1 Register and PACSR Register Address detection register Program address detection control status register (PACSR) Interrupt enable bit 384 PADR0 AD0E PADR1 AD1E 24.2 Registers of the Address Match Detection Function 24.2.2 Program Address Detection Control Status Register (PACSR) This register controls the operation of the address detection function. ■ Program Address Detection Control Status Register (PACSR) Figure 24.2-3 Program Address Detection Control Status Register (PACSR) Program address detection control status register 7 Address: 009EH Read/Write Initial value 6 5 4 Reserved Reserved Reserved Reserved (-) (0) (-) (0) (-) (0) (-) (0) 3 AD1E 2 Reserved 1 AD0E 0 Reserved Bit No. PACSR (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) [bit 7 to 4] Reserved bit These bits are reserved. Always write "0". [bit 3] AD1E (Address Detect register 1 Enable) This is the interrupt enable bit of PADR1. When this bit is "1", the address is compared with the PADR1 register. If a match occurs, the INT9 instruction is issued. [bit 2] Reserved bit These bits are reserved. Always write "0". [bit 1] AD0E (Address Detect register 0 Enable) This is the interrupt enable bit of PADR0. When this bit is "1", the address and the PADR0 register are compared. If a match occurs, the INT9 instruction is issued. [bit 0] Reserved bit These bits are reserved. Always write "0". 385 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.3 Operation of the Address Match Detection Function If the address is equal to the value specified in the address detection register, the address match detection function replaces the instruction code to be loaded into the CPU with the INT9 instruction code, "01H". As a result, when the CPU executes a specified instruction, the INT9 instruction is executed. Performing interrupt processing with the INT #9 interruption routine will enable the patch application function. ■ Operation of the Address Match Detection Function Each of the two address detection registers has an interruption enable bit. When the interruption enable bit is set to "1", the value specified in the address detection register is compared with the address. If the address comparison indicates matching, the instruction code to be loaded into the CPU is replaced with the INT9 instruction code. ■ Notes on the Address Match Detection Function If the address specified for the address detection register does not match the address at the first byte of the instruction, the function does not operate correctly. Because the data at the specified address is changed to "01H", execution of an unwanted instruction or access to an unwanted address will occur. Also, changes to the address detection register should be made after the interruption enable bit is set to "0". If a write operation is performed when the interruption enable bit has the value "1", erroneous address detection will occur and the wrong operation may be executed. 386 24.4 Example of the Address Match Detection Function 24.4 Example of the Address Match Detection Function The configuration of a system is shown as an example of the address match detection function. ■ System Configuration of the Address Match Detection Function Figure 24.4-1 System Configuration Example of the Address Match Detection Function MCU E2PROM MB90570 Series SIN Connector (UART) ■ E2PROM Memory Map Table 24.4-1 E2PROM Memory Map Address Description 0000H Number of bytes of patch program No.0 (If 0, no program error exists.) 0001H Program Address No.0 bits 7 to 0 0002H Program Address No.0 bits 15 to 8 0003H Program Address No.0 bits 24 to 16 0004H Number of bytes of patch program No.1 (If 0, no program error exists.) 0005H Program Address No.1 bits 7 to 0 0006H Program Address No.1 bits 15 to 8 0007H Program Address No.1 bits 24 to 16 Up to 0010H plus the number of bytes of patch program No. 0 Main body of patch program No. 0 ■ Initial Status E2PROM is set to all "0"s. 387 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION ■ When a program error occurs: The main body of the patch program and program address are transferred to the MCU through the connector (UART). The MCU writes the information to E2PROM. ■ Reset Sequence The MCU reads the data of E2PROM after a reset. If the number of bytes of the patch program is not "0", the MCU reads the main body of the patch program and writes it to RAM. The program address is set to either PADR0 or ADR1, and the operation is allowed. The first address of the program written in RAM is held in the specified RAM of each address detection register. ■ INT9 Interrupt The interrupt routine determines the address detection interrupted using the program counter (PC) value saved in stack and makes a branch to the corresponding program. The information stuck by the interrupt is discarded. 388 24.5 Example and Flow of Program Patch Processing 24.5 Example and Flow of Program Patch Processing Figure 24.5-1 "Program Patch Processing" is an example of program patch processing, and Figure 24.5-2 "Flow of the Program Patch Processing" shows the flow of program patch processing. ■ Example and Flow of Program Patch Processing Figure 24.5-1 Program Patch Processing FFFFFFH PC = generation address Abnormal program External E2PROM Register set for program patch Number of bytes of the program Address where the interrupt occurs Corrected program Data transfer through UART Corrected program 000000H 389 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION Figure 24.5-2 Flow of the Program Patch Processing Reset Reads 00H of E2PROM To the patch program 0000H (E2PROM) = 0 JMP 000400H Executes the patch program Reads address 0001H to 0003H (E2PROM) 000400H to 000480H Terminates the patch program JMP FF0050H Reads the patch program 0010H to 0090H (E2PROM) 000400H to 000480H (MCU) Enables the patch program MOV PACSR, #02H Executes the normal program FFFFFFH MB90574C FF0050H Abnormal program FF0000H FFFFH FC0000H 0090H Patch program 0010H 002900H Stack area 0003H 0002H 0001H 0000H 390 Program address low-order: 00 Program address middle-order: 00 Program address high-order: 00 Number of bytes of the patch program: 80 RAM area 000480H Patch program 000400H 000100H RAM and register area I/O area 000000H CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE This chapter describes the functions and operations of the ROM mirror function selection module. 25.1 "Overview of the ROM Mirror Function Selection Module" 25.2 "Register of the ROM Mirror Function Selection Module" 391 CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE 25.1 Overview of the ROM Mirror Function Selection Module The ROM mirror function selection module makes it possible to select whether to see the ROM data in the FF bank on the 00 bank side by setting the register. ■ Block Diagram of the ROM Mirror Function Selection Module Figure 25.1-1 Block Diagram of the ROM Mirror Function Selection Module Internal Data Bus ROM mirror function selection register Address Data 392 Address area 00 bank FF bank ROM 25.2 Register of the ROM Mirror Function Selection Module 25.2 Register of the ROM Mirror Function Selection Module This section describes the register of the ROM mirror function selection module (ROMM). ■ Registers of the ROM Mirror Function Selection Module (ROMM) Figure 25.2-1 Registers of the ROM Mirror Function Selection Module (ROMM) Bit No. Address: MI 00006FH Read/write Initial value ROMM W 1 Note: Do not obtain access to this register during operation between 004000H and 00FFFFH. [bit 15 to 9] Unused bit [bit 8] MI When "1" is written in this bit, the ROM data in the FF bank can be read from the 00 bank. When this bit is "0", this function of the 00 bank does not work. This bit is for write only. Figure 25.2-2 "Registers of the ROM Mirror Function Selection Module (ROMM)" shows the memory space in single chip mode shows the memory space in single chip mode. Note: Because the 00 bank is allocated at addresses 004000 to 00FFFF only and is mirrored at addresses FF4000 to FFFFFF, addresses FFF000 to FF3FFF are not mirrored regardless of the selection of the mirror function. Table 25.2-1 Memory Space Address MB90573 MB90574/C MB90F574/A MB90V570/A Address 1 FE0000H FC0000H FC0000H (FC0000H) Address 2 001800H 002900H 002900H 002900H 393 CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE Figure 25.2-2 Memory Space in Single Chip Mode Address ROM area ROM area Address 1 ROM area Address 2 RAM area RAM area I/O area I/O area When MI="1" Internal area When MI="0" Figure 25.2-3 Memory Space in Internal ROM External Bus Mode Address ROM area ROM area Address 1 ROM area Address 2 RAM area RAM area I/O area I/O area When MI="1" 394 When MI="0" Internal area External bus area CHAPTER 26 2M-BIT FLASH MEMORY This chapter describes the functions and operations of 2M-bit flash memory. The following three methods are available for writing data to and erasing data from the flash memory: 1. Parallel programmer 2. Dedicated serial programmer 3. Executing programs to write/erase data This chapter describes "Executing programs to write/erase data". 26.1 "Overview of the 2M-Bit Flash Memory" 26.2 "Sector Configuration of the 2M-Bit Flash Memory" 26.3 "Flash Memory Control Status Register (FMCS)" 26.4 "Method for Activating Flash Memory Automatic Algorithm" 26.5 "Checking Automatic Algorithm Execution Status" 26.6 "Detailed Explanation of Flash Memory Write/Erase" 26.7 "Example of Flash Memory Program" 395 CHAPTER 26 2M-BIT FLASH MEMORY 26.1 Overview of the 2M-Bit Flash Memory The 2M-bit flash memory is mapped to the FCH to FFH bank in the CPU memory map. The functions of the flash memory interface circuit enable read-access and programaccess from the CPU in the same way as mask ROM. Instructions from the CPU can be used via the flash memory interface circuit to write data to and erase data from the flash memory. Internal CPU control therefore enables rewriting of the flash memory while it is mounted. As a result, improvements in programs and data can be performed efficiently. ■ Features of the 2M-Bit Flash Memory • Sector configuration of "256K words x 8/128K words x 16 bits (16K + 512 x 2 + 7K + 8K + 32K + 64K + 64K + 64K)" • Use of automatic program algorithm (Embedded Algorithm: Equivalent to MBM29F400TA) • Erase pause/restart functions provided • Detection of completion of writing/erasing using data polling or toggle bit functions • Detection of completion of writing/erasing using CPU interrupts • Compatible with JEDEC standard commands • Sector erase function (any combination of sectors) • Minimum of 10,000 write/erase operations Embedded Algorithm is a trademark of Advanced Micro Device Corporation. ■ Flash Memory Write/Erase Method Data write and read cannot be performed simultaneously in flash memory. That is, for data write and erase to and from flash memory, only a write operation without program access from flash memory is enabled by copying the program temporarily from flash memory to RAM and executing RAM. ■ Flash Memory Register ❍ Flash memory control status register (FMCS) Figure 26.1-1 Flash memory control status register (FMCS) FMCS bit7 396 bit6 bit5 bit4 bit3 Address : 0000AEH INTE RDYINT WE RDY Reserved Read/write Initial value (R/W) (R/W) (R/W) (R/W) (W) (0) (0) (0) (1) (0) bit2 bit1 bit0 Bit No. LPM FMCS (W) (W) (R/W) (-) (-) (0) 26.2 Sector Configuration of the 2M-Bit Flash Memory 26.2 Sector Configuration of the 2M-Bit Flash Memory Figure 26.2-1 "Sector Configuration of the 2M-Bit Flash Memory" shows the sector configuration of 2M-bit flash memory. The addresses in the figure indicate the highorder and low-order addresses of each sector. ■ Sector Configuration of the 2M-Bit Flash Memory For access from the CPU, SA0 is allocated to the FC bank register, SA1 is allocated to the FD bank register, SA2 is allocated to the FE bank register, and SA3 to SA8 are allocated to the FF bank register. Figure 26.2-1 Sector Configuration of the 2M-Bit Flash Memory Flash memory CPU address Programmer address(*1) FFFFFFH 7FFFFH FFC000 H 7C000 H FFBFFFH 7BFFFH FFBE00 H 7BE00H FFBDFFH 7BDFFH FFBC00H 7BC00H FFBBFFH 7BBFFH FFA000H 7A000 H FF9FFFH 79FFFH FF8000 H 78000H FF7FFFH 77FFFH FF0000 H 70000H FEFFFFH 6FFFFH FE0000H 60000H FDFFFFH 5FFFFH FD0000H 50000 H FCFFFFH 4FFFF H FC0000 H 40000 H SA8 (16K bytes) SA7 (512 bytes) SA6 (512 bytes) SA5 (7K bytes) SA4 (8K bytes) SA3 (32K bytes) SA2 (64K bytes) SA1 (64K bytes) SA0 (64K bytes) *1 Programmer address When data is written to flash memory by the parallel programmer, the addresses corresponding to CPU addresses are programmer addresses. The general-purpose programmer uses programmer addresses to write and erase data. 397 CHAPTER 26 2M-BIT FLASH MEMORY 26.3 Flash Memory Control Status Register (FMCS) The FMCS, which exists in the flash memory interface circuit, is used when data is written to or erased from flash memory. ■ Flash Memory Control Status Register (FMCS) Figure 26.3-1 Flash Memory Control Status Register (FMCS) FMCS bit7 bit6 bit5 bit4 bit3 Address : 0000AEH INTE RDYINT WE RDY Reserved Read/write nitial value (R/W) (R/W) (R/W) (R/W) (W) (0) (0) (0) (1) (0) bit2 bit1 bit0 Bit No. LPM FMCS (W) (W) (R/W) (-) (-) (0) ❍ Description of bits [bit 7] INTE (INTerrupt Enable) Bit 7 interrupts the CPU when flash memory read/erase terminates. When this bit and the RDYINT bit are "1", the CPU is interrupted. When this bit is "0", the CPU is not interrupted. 0 Interrupts are enabled when write/erase terminates. 1 Interrupts are disabled when write/erase terminates. [Bit 6] RDYINT (ReaDY INTerrupt) Bit 6 represents the operating status of flash memory. When flash memory write/erase terminates, this bit is set to "1". When this bit is "0" after flash memory read/erase has terminated, data cannot be written to and erased from flash memory. After setting this bit to "1" (i.e., after flash memory write/erase has terminated), data write to and erase from flash memory is enabled. This bit is cleared to "0" when "0" is written. Writing "1" is ignored. This bit is set to "1" when flash memory automatic algorithm (see Section 26.4 "Method for Activating Flash Memory Automatic Algorithm") terminates. When the read modify write (RMW) instruction is used, "1" is always read. 0 Write/erase operation is being executed. 1 Write/erase operation terminated (an interrupt request was issued). [Bit 5] WE (Write Enable) Write enable bit to the flash memory area. When this bit is 1, writing after the command sequence (see Section 26.4 "Method for Activating Flash Memory Automatic Algorithm") is issued to the FC to FF bank writes to the flash memory area. When this bit is "0", write/erase signal is not issued. 398 26.3 Flash Memory Control Status Register (FMCS) This bit is used to activate the write/erase command for flash memory. If write/erase is not performed, this bit should always be set to "0" so that data is not inadvertently written to flash memory. 0 Flash memory write/erase is prohibited. 1 Flash memory write/erase is allowed. [Bit 4] RDY (ReaDY) The RDY bit allows flash memory write/erase. When this bit is "0", flash memory write/erase cannot be performed. Even if this bit is "0", the read/reset command and suspend commands (e.g., sector erase temporary stop) are accepted. 0 Write/erase operation is being executed. 1 Write/erase operation terminated (write/erase of subsequent data was allowed). [Bit 3] Reserved bit Bit 3 is reserved for tests. For normal use, set this bit to "0". [Bits 2 and 1] Free bits For normal use, set these bits to "0". [Bit 0] LPM (Low Power Mode) Setting LPM bit to "1" minimizes the select signal to flash memory when flash memory is accessed, thereby suppressing the power consumption of the main unit of flash memory. However, because the access time when this bit is 1 is considerably longer than the access time when this bit is 0, flash memory access is impossible when the CPU operates at high speed. Operate the CPU at a frequency of 4 MHz or lower when using this mode. When the low power mode switches to the sub-block mode, setting by software is unnecessary because this bit is set to "1" automatically. 0 Normal power consumption mode 1 Low-power consumption mode (The CPU operates at an internal operating frequency of 4 MHz or lower.) Note: The RDYINT bit and RDY bit do not change at the same time. Code the program so that a decision is made in accordance with one of these bits. 399 CHAPTER 26 2M-BIT FLASH MEMORY Automatic algorithm termination timing RDYINT bit RDY bit 1 machine cycle 400 26.4 Method for Activating Flash Memory Automatic Algorithm 26.4 Method for Activating Flash Memory Automatic Algorithm There are four commands (read/reset, write program, chip erase, and sector erase) for activating flash memory automatic algorithm. The sector erase command is further divided into a sector erase temporary stop command and a sector erase restart command. ■ Command Sequence Table Table 26.4-1 "Command Sequence Table" lists the commands used when data is written to and erased from flash memory. All data to be written to the command register is represented in bytes but the data must be written by using word access. In this case, high-order byte data is ignored. Table 26.4-1 Command Sequence Table Command sequence Bus write cycle 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle Address Data Address Data Address Data Address Data Address Data Address Data Read/ reset(*1) 1 FxXXXX XXF0 — — — — — — — — — — Read/ reset(*1) 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXF0 RA RD — — — — Write program 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXA0 PA (even) PD (wor d) — — — — Chip erase 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXA A Fx5554 XX55 FxAAAA XX10 Sector erase 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXA A Fx5554 XX55 SA (even) XX30 Sector erase temporary stop When Address "FxXXXX" Data (xxB0H) is entered, sector erase is temporarily stopped. Sector erase restart When Address "FxXXXX" Data (xx30H) is entered, sector erase is temporarily stopped and then restarted. Note: Address Fx in the table indicates FF, FE, FD, or FC. When specifying these addresses, use the relevant value that indicates the bank to be accessed. Addresses in the table are values on the CPU memory map. All addresses and data are represented as hexadecimal numbers. "X", however, is an arbitrary value. RA: Read address PA: Only write addresses and even-number addresses can be specified. SA: Sector address. See Section 26.2 "Sector Configuration of the 2M-Bit Flash Memory". RD: Read data PD: Only write data and word data can be specified. *1: Both of these read/reset commands can reset flash memory in the read mode. 401 CHAPTER 26 2M-BIT FLASH MEMORY 26.5 Checking Automatic Algorithm Execution Status Flash memory has hardware for reporting the operating status in flash memory and the completion of operation because write/erase is executed by automatic algorithm. This algorithm can use the hardware sequence flag explained below to check the operating status of flash memory. ■ Hardware Sequence Flag The hardware sequence flag consists of the outputs of four bits (DQ7, DQ6, DQ5, and DQ3). The DQ7 bit has a data polling flag function. The DQ6 bit has a toggle bit flag function. The DQ5 bit has a timing limit excess flag function. The DQ3 bit has a sector erase timer flag function. These functions enable the user to check whether write/chip, sector erase termination, and erase code write are valid. The hardware sequence flag can be referenced by read-accessing the target sector address in flash memory after setting the command sequence (see Table 26.5-1 "Bit Assignment of Hardware Sequence Flag" in Section 26.4 "Method for Activating Flash Memory Automatic Algorithm"). Table 26.5-1 "Bit Assignment of Hardware Sequence Flag" shows the bit assignment of the hardware sequence flag. Table 26.5-1 Bit Assignment of Hardware Sequence Flag Bit No. 7 6 5 4 3 2 1 0 Hardware sequence flag DQ7 DQ6 DQ5 — DQ3 — — — It can be determined whether an automatic write/chip or sector erase is being executed or a write is being terminated by checking the hardware sequence flag or the RDY bit of the flash memory control register (FMCS). When the automatic write/chip or sector erase has terminated, the read/reset status is restored. When creating a program, determine whether the automatic write/chip or sector erase terminated with a flag and then execute the next processing, such as data read. The validity of the second and subsequent sector erase code write operations can also be determined by the hardware sequence flag. Table 26.5-2 "Hardware Sequence Flag Functions" lists hardware sequence flag functions. 402 26.5 Checking Automatic Algorithm Execution Status Table 26.5-2 Hardware Sequence Flag Functions Status Status change at normal operation DQ7 DQ6 DQ5 DQ3 DQ7 ---> DATA:7 Toggle ---> DATA:6 0 ---> DATA:5 0 ---> DATA:3 0 ---> 1 Toggle ---> DATA:6 0 ---> 1 1 Sector erase wait --->erase start 0 Toggle 0 0 ---> 1 Erase operation ---> sector erase temporary stop (Sector being erased) 0 ---> 1 Toggle ---> 1 0 1 ---> 0 Sector erase temporary stop ---> erase restart (Sector being erased) 1 ---> 0 1 ---> Toggle 0 0 ---> 1 Sector erase temporary stop in progress (Sector not being erased) DATA:7 DATA:6 DATA:5 DATA:3 DQ7 Toggle 1 0 0 Toggle 1 0 Write operation ---> write completion (Valid when a write address is specified) Chip or sector erase operation ---> erase completion Abnormal operation Write operation Chip or sector erase operation The hardware sequence flag is explained in the next and subsequent sections. 403 CHAPTER 26 2M-BIT FLASH MEMORY 26.5.1 Data Polling Flag (DQ7) The data polling flag indicates whether an automatic algorithm is being executed or is in the termination state. ■ At Write Operation If read access is attempted when automatic write algorithm is being executed, flash memory outputs the reverse data of bit 7 of the most recent written data without reference to the indicated address. If read access is attempted when automatic write algorithm terminates, flash memory outputs bit 7 of the read value of the indicated address. ■ At Chip Erase or Sector Erase Operation If read access is attempted when chip erase algorithm is being executed, flash memory outputs "0" without reference to the indicated address. If read access is attempted when sector erase algorithm is being executed, flash memory outputs "0" from the sector being erased, and when chip or sector erase operation terminates, flash memory outputs "1". ■ At Sector Erase Temporary Stop If read access is attempted when sector erase is stopped temporarily, flash memory outputs "1" when the indicated address is being erased. If the sector is not being erased, flash memory outputs bit 7 (DATA:7) of the read value of the indicated address. A temporary stop or an erase of a sector can be detected by referencing this flag with the toggle bit flag (DQ6). ■ Transition of Data Polling Flag States Table 26.5-3 "Transition of Data Polling Flag States at Normal Operation" shows the transition of data polling flag states at normal operation. Table 26.5-4 "Transition of Data Polling Flag States at Abnormal Operation" shows the transition of data polling flag states at abnormal operation. Table 26.5-3 Transition of Data Polling Flag States at Normal Operation Operating state DQ7 404 Write operation ---> completion DQ7 ---> DATA:7 Chip or sector erase --> completion Sector erase wait ---> start Sector erase ---> erase temporary stop (sector being erased) Sector erase temporary stop ---> restart (sector being erased) Sector erase temporary stop in progress (sector not being erased) 0 ---> 1 0 0 ---> 1 1 ---> 0 DATA:7 26.5 Checking Automatic Algorithm Execution Status Table 26.5-4 Transition of Data Polling Flag States at Abnormal Operation Operating state Write operation Chip or sector erase operation DQ7 DQ7 0 Note: When automatic algorithm is activated, read access to the specified address is ignored. For data read, output of other bits is enabled when the data polling flag (DQ7) terminates. For this reason, a data read after automatic algorithm termination must be executed following the read access that checked data polling. 405 CHAPTER 26 2M-BIT FLASH MEMORY 26.5.2 Toggle Bit Flag (DQ6) As with the data polling flag, the toggle bit flag (function) indicates whether automatic algorithm is being executed or is in the termination state. ■ At Write/Chip or Sector Erase Operation If read access is continuously attempted when automatic write algorithm or chip or sector erase algorithm is being executed, flash memory outputs the toggle state in which "1" and "0" are alternately output for each read. Flash memory performs this output without reference to the indicated address. If read access is continuously attempted after automatic write algorithm or chip or sector erase algorithm has terminated, flash memory stops the toggle operation of bit 6 and outputs bit 6 (DATA:6) of the read value of the indicated address. ■ At Sector Erase Temporary Stop If read access is attempted when sector erase is temporarily stopped, flash memory outputs "1" when the indicated address belongs to the sector being erased. If the indicated address does not belong to the sector being erased, flash memory outputs bit 6 (DATA:6) of the read value of the indicated address. Tip: If the sector to be written is write-protected, the toggle bit performs a toggle operation for about 2 µs and then terminates the operation without rewriting data. If all of the selected sectors are write-protected, the toggle bit performs a toggle operation for about 100 µs and then returns to the read/reset state without rewriting data. ■ Transition of Toggle Bit Flag States Table 26.5-5 "Transition of Toggle Bit Flag States at Normal Operation" shows the transition of toggle bit flag states at normal operation. Table 26.5-6 "Transition of Toggle Bit Flag States at Abnormal Operation" shows the transition of toggle bit flag states at abnormal operation. Table 26.5-5 Transition of Toggle Bit Flag States at Normal Operation Operating state DQ6 Write operation ---> completion Chip or sector erase ---> completion Sector erase wait ---> start Sector erase ---> erase temporary stop (sector being erased) Sector erase temporary stop ---> restart (sector being erased) Sector erase temporary stop in progress (sector not being erased) Toggle ---> DATA:6 Toggle ---> Stop Toggle Toggle ---> 1 1 ---> Toggle DATA:6 Table 26.5-6 Transition of Toggle Bit Flag States at Abnormal Operation 406 Operating state Write operation Chip or sector erase operation DQ6 Toggle Toggle 26.5 Checking Automatic Algorithm Execution Status 26.5.3 Timing Limit Excess Flag (DQ5) The timing limit excess flag indicates that automatic algorithm execution exceeds the specified time (internal pulse count) in flash memory. ■ At Write/Chip or Sector Erase If read access is attempted after write automatic algorithm or chip or sector erase automatic algorithm has been activated, flash memory outputs "0" when automatic algorithm execution does not exceed the specified time (time required for write or erase). If automatic algorithm execution exceeds the specified time, flash memory outputs "1". Because this output processing is performed without reference to whether automatic algorithm is being executed or is in the termination state, it can be determined whether write or erase is successful or unsuccessful. If automatic algorithm is being executed by the data polling function or toggle bit function when "1" is output, it can be determined that write is unsuccessful. If an attempt is made to write "1" to the flash memory address to which "0" is already written, for example, a fail occurs. In this case, flash memory is locked but automatic algorithm is not terminated, and so valid data is not output from the data polling flag (DQ7). The time limit is also exceeded because the toggle bit flag (DQ6) does not stop toggle operation. In this case, the timing limit excess flag (DQ5) outputs "1". This state indicates that flash memory was not used correctly, but does not indicate that flash memory is defective. If this state occurs, execute the reset command. ■ Transition of Timing Limit Excess Flag States Table 26.5-7 "Transition of Timing Limit Excess Flag States at Normal Operation" shows the transition of timing limit excess flag states at normal operation. Table 26.5-8 "Transition of Timing Limit Excess Flag States at Abnormal Operation" shows the transition of timing limit excess flag at abnormal operation. Table 26.5-7 Transition of Timing Limit Excess Flag States at Normal Operation Operating state DQ5 Write operation ---> completion Chip or sector erase ---> completion Sector erase wait ---> start Sector erase ---> erase temporary stop (sector being erased) Sector erase temporary stoop ---> restart (sector being erased) Sector erase temporary stop in progress (sector not being erased) 0 ---> DATA:5 0 ---> 1 0 0 0 DATA:5 Table 26.5-8 Transition of Timing Limit Excess Flag States at Abnormal Operation Operating state Write operation Chip or sector erase operation DQ5 1 1 407 CHAPTER 26 2M-BIT FLASH MEMORY 26.5.4 Sector Erase Timer Flag (DQ3) The sector erase timer flag indicates whether the sector erase wait period is exceeded after the sector erase command has been activated. ■ At Sector Erase Operation If read access is attempted after the sector erase command has been activated, flash memory outputs "0" when the sector erase wait period is not exceeded. If the sector erase wait period is exceeded, flash memory outputs "1". Flash memory performs this output processing without reference to the address indicated by the address signal of the sector issuing the sector erase command. If this flag is "1" when erase algorithm is being executed by the data polling function or toggle bit function, erase has already started in flash memory. In this case, the subsequent writing of sector erase codes and commands other than the erase temporary stop command are ignored. When this flag is "0", flash memory accepts the writing of additional sector erase codes. To check this acceptance, the state of this flag should be checked before the subsequent sector erase codes are written. If this flag is found to be "1" as a result of the second check, the erase codes of additional sectors may not be accepted. ■ At Sector Erase Operation If read access is attempted when sector erase is temporarily stopped, flash memory outputs "1" when the indicated address belongs to the sector being erased. If the indicated address does not belong to the sector being erased, flash memory outputs bit 3 (DATA:3) of the read value of the indicated address. ■ Transition of Sector Erase Timer Flag States Table 26.5-9 "Transition of Sector Erase Timer Flag States at Normal Operation" shows the transition of sector erase timer flag states at normal operation. Table 26.5-10 "Transition of Sector Erase Timer Flag States at Abnormal Operation" shows the transition of sector erase timer flag states at abnormal operation. Table 26.5-9 Transition of Sector Erase Timer Flag States at Normal Operation Operating state DQ3 Write operation ---> completion Chip or sector erase ---> completion Sector erase wait ---> start Sector erase ---> erase temporary stop (sector being erased) Sector erase temporary stoop ---> restart (sector being erased) Sector erase temporary stop in progress (sector not being erased) 0 ---> DATA:3 1 0 ---> 1 1 ---> 0 0 ---> 1 DATA:3 Table 26.5-10 Transition of Sector Erase Timer Flag States at Abnormal Operation 408 Operating state Write operation Chip or sector erase operation DQ3 0 1 26.6 Detailed Explanation of Flash Memory Write/Erase 26.6 Detailed Explanation of Flash Memory Write/Erase This section describes how to perform read/reset, data write, chip erase, sector erase, sector erase temporary stop, and sector erase restart for flash memory by issuing the commands for activating automatic algorithm. ■ Detailed Explanation of Flash Memory Write/Erase Flash memory can execute automatic algorithm by executing the write cycles to the buses of command sequences (see Section 26.4 "Method for Activating Flash Memory Automatic Algorithm") for read/reset, data write, chip erase, sector erase, sector erase temporary stop, and sector erase restart. The write cycles to these buses must always be executed continuously. Automatic algorithm can also use the data polling function to determine if a termination occurs. Automatic algorithm returns to the read/reset state after terminating. Flash memory write/erase is explained as follows: 1. Read/reset (See Section 26.6.1 "Read/Reset".) 2. Data write (See Section 26.6.2 "Data Write".) 3. Data erase (all chip erase) (See Section 26.6.3 "Data Erase (All Chip Erase)".) 4. Data erase (sector erase) (See Section 26.6.4 "Data Erase (Sector Erase)".) 5. Sector erase temporary stop (See Section 26.6.5 "Sector Erase Temporary Stop".) 6. Sector erase restart (See Section 26.6.6 "Sector Erase Restart".) 409 CHAPTER 26 2M-BIT FLASH MEMORY 26.6.1 Read/Reset This section describes how to put flash memory into the read/reset state by issuing the read/reset command. ■ Putting Flash Memory into Read/Reset State Flash memory can be put into the read/reset state by continuously transmitting the read/reset command shown in the command sequence table (see Section 26.4 "Method for Activating Flash Memory Automatic Algorithm") to the target sector in flash memory. The read/reset command provides the two command sequences that perform one and three bus operations. These sequences are essentially the same. The read/reset state indicates that flash memory is in the initial state. When power is turned on or when a command terminates normally, flash memory enters the read/reset state. When flash memory is in the read/reset state, other commands are in the input wait state. In the read/reset state, normal read access can be used to read data. Like mask ROM, program access from the CPU is possible. The read/reset command is unnecessary for normal read access. This command is used primarily to initialize automatic algorithm when a command does not terminate normally. 410 26.6 Detailed Explanation of Flash Memory Write/Erase 26.6.2 Data Write This section describes how to write data to flash memory by issuing the write command. ■ Writing Data to Flash Memory Automatic algorithm for flash memory can be activated by continuously transmitting the write command shown in the command sequence table (see Section 26.4 "Method for Activating Flash Memory Automatic Algorithm") to the target sector in flash memory. When data write to the target address terminates at the 4th cycle, automatic algorithm is activated to start automatic writing. ■ Addressing In the write data cycle, only an even-number address can be specified as a write address. If an odd-number address is specified, data cannot be written to flash memory correctly. That is, data must be written to even-number addresses in words. Data can be written to flash memory in any address order. Data can also be written beyond a sector boundary, but only one word can be written by one write command. ■ Notes on Data Write Data "0" cannot be restored to data "1" by the write command. If data "1" is written to data "0", the flash memory element is determined to be faulty because the data polling algorithm (DQ7) or toggle operation (DQ6) does not terminate. The timing limit excess flag (DQ6) is determined to be an error because the specified write time was exceeded or data "1" was written. However, even if data is read in the read/reset state, it remains "0". Only an erase operation enables data to be changed from "0" to "1". All commands are ignored during automatic write execution. Note that if hardware reset is activated during automatic write execution, data at the written address is not guaranteed. ■ Flash Memory Write Procedure The hardware sequence flag (see Section 26.5 "Checking Automatic Algorithm Execution Status") enables the determination of the automatic algorithm state in flash memory. Figure 26.6-1 "Example of Flash Memory Write Procedure" is an example of the flash memory write procedure. In this example, the data polling flag (DQ7) is used to check data write termination. Data for flag check is read into the most recent written address. The data polling flag (DQ7) and timing limit excess flag (DQ5) change at the same time. For this reason, even if DQ5 is "1", DQ7 must be re-checked. When DQ5 changes to "1", the toggle bit flag (DQ6) also stops toggle operation. DQ6 must also be re-checked. 411 CHAPTER 26 2M-BIT FLASH MEMORY Figure 26.6-1 Example of Flash Memory Write Procedure Data polling flag (DQ7) Timing limit (DQ5) Data polling flag (DQ7) Last address 412 26.6 Detailed Explanation of Flash Memory Write/Erase 26.6.3 Data Erase (All Chip Erase) This section describes how to erase all data in flash memory by issuing the chip erase command. ■ Erasing Data (Erasing All Chips) All data can be erased from flash memory by continuously issuing the chip erase command shown in the command sequence table (see Section 26.4 "Method for Activating Flash Memory Automatic Algorithm") to the target sector in flash memory. The chip erase command performs a bus operation six times. When a write operation in the 6th cycle is completed, a chip erase operation is started. In chip erase, the user does not have to write data to flash memory before erase. Flash memory writes "0" for verification before all cells are erased automatically. 413 CHAPTER 26 2M-BIT FLASH MEMORY 26.6.4 Data Erase (Sector Erase) This section describes how to erase an arbitrary sector from flash memory by issuing the sector erase command. Data can be erased per sector and several sectors can be specified at the same time. ■ Erasing Data (Erasing Sector) An arbitrary sector can be erased from flash memory by continuously transmitting the sector erase command shown in the command sequence table (see Section 26.4 "Method for Activating Flash Memory Automatic Algorithm") to the target sector in flash memory. ■ Sector Specification Method The sector erase command performs bus operation six times. When the sector erase code (30H) is written to an accessible even-number address in the target sector at the 6th cycle, a 50µs sector erase wait is started. To erase several sectors, write the erase code (30H) to an address in the sector to be erased as explained in the above processing. ■ Notes on Specification of Several Sectors Data erase is started when the 50 µs sector erase wait period from the write of the last sector erase code terminates. That is, to erase several sectors at the same time, the address and erase code (6th cycle of the command sequence) of the next erase sector must be entered within 50 µs. If these address and erase code are not entered within 50 µs, they may not be accepted. The validity of a write of the subsequent sector erase codes can be determined by the sector erase timer (hardware sequence flag DQ3). In this case, the address from which the sector erase timer is to be read must indicate the sector to be erased. ■ Sector Erase Procedure The hardware sequence flag (see Section 26.5 "Checking Automatic Algorithm Execution Status") enables the determination of the automatic algorithm state in flash memory. Figure 26.6-2 "Example of Sector Erase Procedure" is an example of the flash memory sector erase procedure. In this example, the toggle bit flag (DQ6) is used to check sector erase termination. Note that data for flag check is read into the sector to be erased. The toggle bit flag (DQ6) stops toggle operation when the timing limit excess flag (DQ5) changes to "1", and so even if DQ5 is "1", DQ6 must be re-checked. When DQ5 changes, the data polling flag (DQ7) also changes. DQ7 must also be re-checked. 414 26.6 Detailed Explanation of Flash Memory Write/Erase Figure 26.6-2 Example of Sector Erase Procedure Start of erase Allow flash memory erase Erase command sequence Sector erase timer (DQ3) Sector address <--erase code (30H) Read internal address Are there other erase sectors? Read internal address 1 Read internal address 2 Next sector Does data 1 (DQ6) match data 2 (DQ6) in toggle bit (DQ6)? Timing limit (DQ5) Read internal address 1 Read internal address 2 Does data 1 (DQ6) match data 2 (DQ6) in toggle bit (DQ6)? Erase error Last sector? Prohibit flash memory erase Check by hardware sequence flag End of erase 415 CHAPTER 26 2M-BIT FLASH MEMORY 26.6.5 Sector Erase Temporary Stop This section describes how to stop flash memory sector erase temporarily by issuing the sector erase temporary stop command. Data can also be read from the sector not being erased. ■ Stopping Sector Erase Temporarily Flash memory sector erase can be stopped temporarily by continuously transmitting the sector erase temporary stop command shown in the command sequence table (see Section 26.4 "Method for Activating Flash Memory Automatic Algorithm") to flash memory. The sector erase temporary stop command stops sector erase temporarily to enable data to be read from the sector not being erased. In this state, a read is possible, but a write is not possible. This command can be used only when a sector is being erased (sector erase time including the erase wait time). The command is ignored when a chip is being erased or when data is being written to flash memory. This command is executed by writing the erase temporary stop code (B0H). In this case, however, the address must indicate an address in flash memory. In sector erase temporary stop, re-issuance of the sector erase temporary stop command is ignored. If the sector erase temporary stop command is entered during the sector erase wait period, flash memory immediately terminates sector erase wait, interrupts erase operation, and enters the erase top state. If the sector erase temporary stop command is entered when sector erase operation is in progress after the sector erase wait period has elapsed, flash memory enters the erase temporary stop state within 15 µs. 416 26.6 Detailed Explanation of Flash Memory Write/Erase 26.6.6 Sector Erase Restart This section describes how to restart the temporarily stopped flash memory sector erase operation by issuing the sector erase restart command. ■ Restarting Sector Erase Operation The temporarily stopped sector erase operation can be restarted by transmitting the sector erase restart command shown in the command sequence table (see Section 26.4 "Method for Activating Flash Memory Automatic Algorithm") continuously to flash memory. The sector erase restart command restarts the sector erase operation temporarily stopped by the sector erase temporary stop command. This command is executed by writing the erase restart code (30H). In this case, however, the address must indicate any address in flash memory. In sector erase operation, issuance of the sector erase restart command is ignored. 417 CHAPTER 26 2M-BIT FLASH MEMORY 26.7 Example of Flash Memory Program This section provides an example of a flash memory program. ■ Example of Flash Memory Program NAME FLASHWE TITLE FLASHWE ;------------------------------------------------------------------------------;MB90F574/A-FLASH test program ; ;1: Transmits the program (address: FFBC00H, sector: SA6) from FLASH to RAM ; (address: 001500H). ;2: Executes the program on RAM. ;3: Writes the PDR1 value to FLASH (address: FD0000H, sector: SA1). ;4: Reads the written value (address: FD0000H, sector: SA1) and outputs it to PDR2. ;5: Erases the written sector (SA1). ;6: Checks and outputs erase data. ;Conditions ; - Number of bytes transmitted to RAM: 100H (256B) ; - Write/erase termination judgment ; Judgment according to DQ5 (timing limit excess flag) ; Judgment according to DQ6 (toggle bit flag) ; Judgment according to RDY (FMCS) ; - Error handling ; Hi output to P00 to P07 ; Reset command issuance ;------------------------------------------------------------------; RESOUS IOSEG ABS=00 ;"RESOUS" I/O segment definition ORG 0000H PDR0 RB 1 PDR1 RB 1 PDR2 RB 1 PDR3 RB 1 ORG 0010H DDR0 RB 1 DDR1 RB 1 DDR2 RB 1 DDR3 RB 1 ORG 00A1H CKSCR RB 1 ORG 00AEH FMCS RB 1 ORG 006FH ROMM RB 1 RESOUS ENDS ; SSTA SSEG RW 0127H STA_T RW 1 SSTA ENDS ; DATA DSEG ABS=0FFH ;FLASH command address ORG 5554H COMADR2 RW 1 ORG 0AAAAH COMADR1 RW 1 DATA ENDS ;///////////////////////////////////////////////////////////// 418 26.7 Example of Flash Memory Program ;Main program (SA3) ;///////////////////////////////////////////////////////////// CODE CSEG START: ; ///////////////////////////////////////////////////// ; Initialization ; ///////////////////////////////////////////////////// MOV CKSCR,#0BAH ;3-multiple setting MOV RP,#0 MOV A,#!STA_T MOV SSB,A MOVW A,#STA_T MOVW SP,A MOV ROMM,#00H ;Mirror OFF MOV PDR0,#00H ;For error check MOV DDR0,#0FFH MOV PDR1,#00H ;Port for data input MOV DDR1,#00H MOV PDR2,#00H ;Port for data output MOV DDR2,#0FFH ; ////////////////////////////////////////////////////////////// ; Transfer of "FLASH write erase program (FFBC00H)" to RAM (1500H address) ; ////////////////////////////////////////////////////////////// MOVW A,#1500H ;Transfer destination RAM area MOVW A,#0BC00H ;Transfer source address (program position) MOVW RW0,#100H ;Number of bytes to be transferred MOVS ADB,PCB ;Transfer of 100H from FFBC00H to 001500H CALLP 001500H ;Jump to the address containing the transferred ; program ; ///////////////////////////////////////////////////// ; Data output ; ///////////////////////////////////////////////////// OUT MOV A,#0FDH MOV ADB,A MOVW RW2,#0000H MOVW A,@RW2+00 MOV PDR2,A END JMP * CODE ENDS ;//////////////////////////////////////////////////////////// ;FLASH write erase program (SA6) ;//////////////////////////////////////////////////////////// RAMPRG CSEG ABS=0FFH ORG 0BC00H ; //////////////////////////////////////////// Initialization ; //////////////////////////////////////////// MOVW RW0,#0500H ;RW0:RAM space for input data acquisition 00:0500~ MOVW RW2,#0000H ;RW2:Flash memory write address FD:0000~ MOV A,#00H ;DTB modification MOV DTB,A ;Bank specification for @RW0 MOV A,#0FDH ;ADB modification 1 MOV ADB,A ;Bank specification for write mode specification ; address MOV PDR3,#00H ;Switch initialization MOV DDR3,#00H ; WAIT1 BBC PDR3:0,WAIT1 ;PDR3: 0(write start at high level) ; ;//////////////////////////////////////////////// ;Write (SA1) ;//////////////////////////////////////////////// MOV A,PDR1 MOVW @RW0+00,A ;PDR1 data allocation to RAM MOV FMCS,#20H ;Write mode setting MOVW ADB:COMADR1,#00AAH ;Flash write command 1 MOVW ADB:COMADR2,#0055H ;Flash write command 2 MOVW ADB:COMADR1,#00A0H ;Flash write command 3 419 CHAPTER 26 2M-BIT FLASH MEMORY ; WRITE ; ; ; ; ; ; ; ; NTOW ; ; ; MOVW A,@RW0+00 ;Input data (RW0) write to flash memory (RW2) MOVW @RW2+00,A ;Wait time check /////////////////////////////////////////////////////////////////// ERROR when the time limit excess check flag is set and toggle operation is in progress /////////////////////////////////////////////////////////////////// MOVW A,@RW2+00 AND A,#20H ;DQ5 time limit check BZ NTOW ;Time limit over MOVW A,@RW2+00 ;AH MOVW A,@RW2+00 ;AL XORW A ;XOR of AH and AL (1 when the values differ) AND A,#40H ;Is the DQ6 toggle bit different? BNZ ERROR ;To ERROR when the DQ6 toggle bit is different /////////////////////////////////////// Write termination check (FMCS-RDY) /////////////////////////////////////// /////////////////////////////////////// MOVW A,FMCS AND A,#10H ;Extraction of FMCS RDY bit (bit 4) BZ WRITE ;End of write? MOV FMCS,#00H ;Write mode release ///////////////////////////////////////////////////// Write data output ///////////////////////////////////////////////////// MOVW RW2,#0000H ;Write data output MOVW A,@RW2+00 MOV PDR2,A ; WAIT2 BBC PDR3:1,WAIT2 ;PDR3: 1(sector erase start at high level) ; ;///////////////////////////////////////////// ;Sector erase (SA1) ;///////////////////////////////////////////// MOV @RW2+00,#0000H ;Address initialization MOV FMCS,#20H ;Erase mode setting MOVW ADB:COMADR1,#00AAH ;Flash erase command 1 MOVW ADB:COMADR2,#0055H ;Flash erase command 2 MOVW ADB:COMADR1,#0080H ;Flash erase command 3 MOVW ADB:COMADR1,#00AAH ;Flash erase command 4 MOVW ADB:COMADR2,#0055H ;Flash erase command 5 MOV @RW2+00,#0030H ;Issuance of erase command 6 to the sector to be erased ELS ;Wait time check ; /////////////////////////////////////////////////////////////////// ; ERROR when the time limit excess check flag is set and toggle operation is ; in progress ; /////////////////////////////////////////////////////////////////// MOVW A,@RW2+00 AND A,#20H ;DQ5 time limit check BZ NTOE ;Time limit over MOVW A,@RW2+00 ;AH High and Low are alternately output from MOVW A,@RW2+00 ;AL DQ6 per read during write operation. XORW A ;XOR of AH and AL (If the DQ6 value differs, ; write operation is in progress (1)). AND A,#40H ;Is the DQ6 toggle bit High? BNZ ERROR ;ERROR when the DQ6 toggle bit is High ; /////////////////////////////////////// ; Erase termination check (FMCS-RDY) ; /////////////////////////////////////// NTOE MOVW A,FMCS ; AND A,#10H ;Extraction of FMCS RDY bit (bit 4) BZ ELS ;End of sector erase? MOV FMCS,#00H ;FLASH erase mode release RETP ;Return to the main program ;////////////////////////////////////////////// 420 26.7 Example of Flash Memory Program ;Error ;////////////////////////////////////////////// ERROR MOV ADB:COMADR1,#0F0H ;Reset command (read is enabled) MOV PDR0,#0FFH ;Error handling check MOV FMCS,#00H ;FLASH mode release RETP ;Return to the main program RAMPRG ENDS ;///////////////////////////////////////////// VECT CSEG ABS=0FFH ORG 0FFDCH DSL START DB 00H VECT ENDS ; 421 CHAPTER 26 2M-BIT FLASH MEMORY 422 CHAPTER 27 EXAMPLES OF MB90F574/A SERIAL PROGRAMMING CONNECTION This chapter describes examples of serial programming connection with the AF220/ AF210/AF120/AF110 flash microcomputer programmer manufactured by YDC Corporation. 27.1 "Basic Configuration of MB90F574/A Serial Programming Connection" 27.2 "Example of Serial Programming Connection (User Power Supply Used)" 27.3 "Example of Serial Programming Connection (Power Supplied from the Programmer)" 27.4 "Example of Minimum Connection to the Flash Microcomputer Programmer (User Power Supply Used)" 27.5 "Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Programmer)" 423 CHAPTER 27 EXAMPLES OF MB90F574/A SERIAL PROGRAMMING CONNECTION 27.1 Basic Configuration of MB90F574/A Serial Programming Connection The MB90F574/A supports the serial on-board programming (Fujitsu standard) of flash ROM. This section describes the specifications. ■ Basic Configuration of MB90F574/A Serial Programming Connection The AF220/AF210/AF120/AF110 flash microcomputer programmer of YDC Corporation is used as Fujitsu standard serial on-board programming. Figure 27.1-1 "Basic Configuration of MB90F574/A Serial Programming Connection" shows the basic configuration of MB90F574/A serial programming connection. Figure 27.1-1 Basic Configuration of MB90F574/A Serial Programming Connection Host interface cable RS232C General-purpose common cable (AZ210) AF220/AF210/ AF120/AF110 flash microcomputer programmer + memory card CLK synchronous serial MB90F574/A user system Stand-alone operation enabled Note: Ask YDC Corporation for information about the functions and operations of the AF220/ AF210/AF120/AF110 flash microcomputer programmer, general-purpose common cable (AZ210) for connection, and connectors. Table 27.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming Pin 424 Function Additional information MD2, MD1, MD0 Mode pin Controls programming mode from the flash microcomputer programmer. X0, X1 Oscillation pins In programming mode, the CPU internal operation clock signal is one multiple of the PLL clock signal frequency. Therefore, because the oscillation clock frequency becomes the internal operation clock signal, the resonator used for serial reprogramming is 1 MHz to 16 MHz. P00, P01 Programming activation pins - RSTX Reset pin - SIN0 Serial data input pin SOT0 Serial data output pin SCK0 Serial clock input pin The UART0 is used in CLK synchronous mode. 27.1 Basic Configuration of MB90F574/A Serial Programming Connection Table 27.1-1 Pins Used for Fujitsu Standard Serial Onboard Programming (Continued) Pin Function Additional information This external capacitor pin is used to stabilize the power supply. Connect a ceramic capacitor of approximately 0.1µF to the outside. C C pin VCC Power voltage supply pin If the programming voltage (5 V 10%) is supplied from the user system, the flash microcomputer programmer need not be connected. Connect so that the power supply of the user side is not short-circuited. VSS GND pin Common to the ground of the flash microcomputer programmer. HSTX Hardware standby pin Input high level during serial programming mode. Even if the P00, SIN0, SOT0, and SCK0 pins are used for the user system, the control circuit shown in the figure below is required. (The /TICS signal of the flash microcomputer programmer can be used to disconnect the user circuit during serial Programming). Figure 27.1-2 Control Circuit AF220/AF210/AF120/AF110 programming control pin MB90F574/F programming control pin 10K AF220/AF210/AF120/AF110 TICS pin User Section 27.2 "Example of Serial Programming Connection (User Power Supply Used)" to 27.5 "Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the Programmer)" present examples the following four types of serial programming connection. See each Section as required. • Internal vector mode (single chip mode and internal ROM external bus mode) [user power supply used] • Internal vector mode (single chip mode and internal ROM external bus mode) [power supplied from the programmer] • Example of minimum connection to the flash microcomputer programmer [user power supply used] • Example of minimum connection to the flash microcomputer programmer [power supplied from the programmer] 425 CHAPTER 27 EXAMPLES OF MB90F574/A SERIAL PROGRAMMING CONNECTION Table 27.1-2 System Configuration of AF220/AF210/AF120/AF110 Flash Microcomputer Programmer (YDC Corporation) Model Mainframe Function AF220/AC4P Built-in Ethernet interface model (100 to 220 V power adapter) AF210/AC4P Standard model (100 to 220 V power adapter) AF120/AC4P Single-key Ethernet interface model (100 to 220 V power adapter) AF110/AC4P Single-key model (100 to 220 V power adapter) AZ221 PC/AT RS232C cable only for programmer AZ210 Standard target probe (a), length: 1 m FF201 Fujitsu F2MC-16LX flash microcomputer control model AZ290 Remote controller /P2 2 MB PC card (option) for flash memory sizes of up to 128 KB /P4 4 MB PC card (option) for flash memory sizes of up to 512 KB Inquiries: YDC Corporation Telephone number: (81) 42-333-6224 Note: The AF200 flash microcomputer programmer, which is not supported now, can be used by using control module FF201. Section 27.2 "Example of Serial Programming Connection (User Power Supply Used)". to 27.5 "Example of Minimum Connection to the Flash Microcomputer Programmer (Power Supplied from the programmer)" present examples the following four types of serial Programming connection. ■ Oscillation Clock Frequency and Serial Clock Input Frequency The formula shown below can be used to calculate the maximum serial clock frequency that can be input to the MB90F574/A. Maximum serial clock frequency that can be input = 0.125 x oscillation clock frequency Consequently, change the serial clock input frequency by setting the serial clock frequency of the flash microcomputer programmer according to the current oscillation clock frequency. Table 27.1-3 Examples of the Maximum Serial Clock Frequency That Can Be Input Oscillation clock frequency Maximum serial clock frequency that can be input for the microcomputer Maximum serial clock frequency that can be set with AF220/AF210/ AF120/AF110 Maximum serial clock frequency that can be set with AF200 4 MHz 500 kHz 500 kHz 500 kHz 8 MHz 1 MHz 850 kHz 500 kHz 16 MHz 2 MHz 1.25 MHz 500 kHz 426 27.2 Example of Serial Programming Connection (User Power Supply Used) 27.2 Example of Serial Programming Connection (User Power Supply Used) Figure 27.2-1 "Example of Serial Programming Connection in MB90F574/A Internal Vector Mode (User Power Supply Used)" is an example of a serial programming connection (when the power for the microcomputer is supplied from the user power supply.) Note that mode pins MD2 and MD0 receive input signals MD2=1 and MD0=0, respectively, from the TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer. Serial reprogramming mode pins MD2, MD1, and MD0 are set to 110. ■ Example of Serial Programming Connection (User Power Supply Used) Figure 27.2-1 Example of Serial Programming Connection in MB90F574/A Internal Vector Mode (User Power Supply Used) User system AF220/AF210/ AF120/AF110 Connector flash microcomputer programmer 1 MHz to 16 MHz User User User User power supply - Pins 3, 4, 9, 11, 16, 17, 18, 20, 24, 25, and 26 are open. - DX10-28S: Right angle type - The Pin Numbers of the written microcomputer correspond to those of the FTP-120P-M05, FTP-120P-M13, and FTP-120P-M21 packages. Pin 14 Pin 1 Pin 15 Pin 28 Pin assignment of connector (HIROSE Electric) 427 CHAPTER 27 EXAMPLES OF MB90F574/A SERIAL PROGRAMMING CONNECTION • When the SIN0, SOT0, and SCK0 pins are used in the user system, the control circuit shown in the figure below is necessary, as with P00. (The user circuit can be disconnected by the / TICS signal of the flash microcomputer programmer during serial programming.) MB90F574/A programming control pin AF220/AF210/AF120/AF110 programming control pin AF220/AF210/AF120/AF110 /TICS pin User • 428 Connect pins to AF220/AF210/AF120/AF110 when the user power supply is off. 27.3 Example of Serial Programming Connection (Power Supplied from the Programmer) 27.3 Example of Serial Programming Connection (Power Supplied from the Programmer) Figure 27.3-1 "Example of Serial Programming Connection in MB90F574/A Internal Vector Mode (Power Supplied from the Programmer)" is an example of serial programming connection (when the power for the microcomputer is supplied from the programmer.) Note that mode pins MD2 and MD0 receive input signals MD2=1 and MD0=0, respectively, from the TAUX3 and TMODE of the AF220/AF210/AF120/AF110. Serial programming mode pins MD2, MD1, and MD0 are set to 110. ■ Example of Serial Programming Connection (Power Supplied from the Programmer) Figure 27.3-1 Example of Serial Programming Connection in MB90F574/A Internal Vector Mode (Power Supplied from the Programmer) AF220/AF210/ AF120/AF110 flash microcomputer programmer User system Connector 1 MHz to 16 MHz User User User Pin 14 - Pins 4, 9, 11, 17, 18, 20, 24, 25, and 26 are open. - DX10-28S: Right angle type - The Pin Numbers of the written microcomputer correspond to those of the FTP-120P-M05, FTP-120P-M13, and FTP-120P-M21 packages. Pin 1 Pin 28 Pin 15 Pin assignment of connector (HIROSE Electric) 429 CHAPTER 27 EXAMPLES OF MB90F574/A SERIAL PROGRAMMING CONNECTION • When the SIN0, SOT0, and SCK0 pins are used in the user system, the control circuit shown in the figure below is necessary, as with P00. (The user circuit can be disconnected by the / TICS signal of the flash microcomputer programmer during serial programming.) MB90F574/A programming control pin AF220/AF210/AF120/AF110 programming control pin AF220/AF210/AF120/AF110 /TICS pin User 430 • Connect pins to AF220/AF210/AF120/AF110 when the user power supply is off. • When programming power is supplied from AF220/AF210/AF120/AF110, do not connect the circuit between the programming power and user power supplies. 27.4 Example of Minimum Connection to Flash Microcomputer Programmer (User Power Supply Used) 27.4 Example of Minimum Connection to Flash Microcomputer Programmer (User Power Supply Used) Figure 27.4-1 "Example of Minimum Connection to Flash Microcomputer Programmer (User Power Supply Used)" is an example of minimum connection to the flash microcomputer programmer (when the power for the microcomputer is supplied from the user power supply.) Serial programming mode pins MD2, MD1, and MD0 are set to 110. ■ Example of Minimum Connection to Flash Microcomputer Programmer (User Power Supply Used) Setting each pin as shown in Figure 27.4-1 "Example of Minimum Connection to Flash Microcomputer Programmer (User Power Supply Used)" when flash memory is written eliminates the need to connect MD2, MD1, MD0, and P00 to the flash microcomputer programmer. Figure 27.4-1 Example of Minimum Connection to Flash Microcomputer Programmer (User Power Supply Used) AF220/AF210/ AF120/AF110 User system flash microcomputer programmer 1 at serial reprogramming 1 at serial reprogramming 0 at serial reprogramming 1 MHz to 16 MHz 0 at serial reprogramming User circuit 1 at serial rewriting User circuit Connector 12 13 User power supply Pin 14 Pin 1 - Pins 3, 4, 9, 10, 11, 12, 16, 17, 18, 19, 20, 23, 24, 25, and 26 are open. - DX10-28S: Right angle type - The pin Numbers of the written microcomputer correspond to those of the FTP-120P-M05, FTP-120P-M13, and FTP-120P-M21 packages. Pin 28 Pin 15 Pin assignment of connector (HIROSE Electric) 431 CHAPTER 27 EXAMPLES OF MB90F574/A SERIAL PROGRAMMING CONNECTION • When the SIN0, SOT0, and SCK0 pins are used in the user system, the control circuit shown in the figure below is necessary, as with P00. (The user circuit can be disconnected by the / TICS signal of the flash microcomputer programmer during serial programming.) MB90F574/A programming control pin AF220/AF210/AF120/AF110 programming control pin AF220/AF210/AF120/AF110 /TICS pin User • 432 Connect pins to AF220/AF210/AF120/AF110 when the user power supply is off. 27.5 Example of Minimum Connection to Flash Microcomputer Programmer (Power Supplied from the 27.5 Example of Minimum Connection to Flash Microcomputer Programmer (Power Supplied from the Programmer) Figure 27.5-1 "Example of Minimum Connection to Flash Microcomputer Programmer (Power Supplied from the Programmer)" is an example of minimum connection to the flash microcomputer programmer (when the power for the microcomputer is supplied from the programmer.) Serial programming mode pins MD2, MD1, and MD0 are set to 110. ■ Example of Minimum Connection to Flash Microcomputer Programmer (Power Supplied from the Programmer) Setting each pin as shown in Figure 27.5-1 "Example of Minimum Connection to Flash Microcomputer Programmer (Power Supplied from the Programmer)" when flash memory is written eliminates the need to connect MD2, MD1, MD0, and P00 to the flash microcomputer programmer. Figure 27.5-1 Example of Minimum Connection to Flash Microcomputer Programmer (Power Supplied from the Programmer) AF220/AF210/ AF120/AF110 User system flash microcomputer programmer 1 at serial reprogramming 1 at serial reprogramming 0 at serial reprogramming 1 MHz to 16 MHz 0 at serial reprogramming User circuit 1 at serial rewriting User circuit Connector Pin 14 Pin 1 - Pins 4, 9, 10, 11, 12, 17, 18, 19, 20, 23, 24, 25, and 26 are open. - DX10-28S: Right angle type - The pin Numbers of the written microcomputer correspond to those of the FTP-120P-M05, FTP-120P-M13, and FTP-120P-M21 packages. Pin 28 Pin 15 Pin assignment of connector (HIROSE Electric) 433 CHAPTER 27 EXAMPLES OF MB90F574/A SERIAL PROGRAMMING CONNECTION • When the SIN0, SOT0, and SCK0 pins are used in the user system, the control circuit shown in the figure below is necessary, as with P00. (The user circuit can be disconnected by the / TICS signal of the flash microcomputer programmer during serial programming.) MB90F574/A programming control pin AF220/AF210/AF120/AF110 programming control pin AF220/AF210/AF120/AF110 /TICS pin User 434 • Connect pins to AF220/AF210/AF120/AF110 when the user power supply is off. • When programming power is supplied from AF220/AF210/AF120/AF110, do not connect the circuit between the programming power and user power supplies. APPENDIX This appendix describes an I/O map, an instructions list, and other information. APPENDIX A "I/O Map" APPENDIX B "Instructions" 435 APPENDIX A I/O Map APPENDIX A I/O Map Individual registers for the peripheral functions incorporated in the MB90570 Series are assigned addresses as shown in Table A-1 "I/O Map". ■ I/O Map Table A-1 I/O Map Address Register Access Peripheral Initial value 00H Port 0 data register PDR0 R/W Port 0 XXXXXXXXB 01H Port 1 data register PDR1 R/W Port 1 XXXXXXXXB 02H Port 2 data register PDR2 R/W Port 2 XXXXXXXXB 03H Port 3 data register PDR3 R/W Port 3 XXXXXXXXB 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXXB 05H Port 5 data register PDR5 R/W Port 5 XXXXXXXXB 06H Port 6 data register PDR6 R/W Port 6 XXXXXXXXB 07H Port 7 data register PDR7 R/W Port 7 XXXXXXXXB 08H Port 8 data register PDR8 R/W Port 8 XXXXXXXXB 09H Port 9 data register PDR9 R/W Port 9 XXXXXXXXB 0AH Port A data register PDRA R/W Port A XXXXXXXXB 0BH Port B data register PDRB R/W Port B XXXXXXXXB 0CH Port C data register PDRC R/W Port C XXXXXXXXB 0DH to 0FH 436 Name Not available 10H Port 0 direction register DDR0 R/W Port 0 00000000B 11H Port 1 direction register DDR1 R/W Port 1 00000000B 12H Port 2 direction register DDR2 R/W Port 2 00000000B 13H Port 3 direction register DDR3 R/W Port 3 00000000B 14H Port 4 direction register DDR4 R/W Port 4 00000000B 15H Port 5 direction register DDR5 R/W Port 5 00000000B 16H Port 6 direction register DDR6 R/W Port 6 00000000B 17H Port 7 direction register DDR7 R/W Port 7 -----000B 18H Port 8 direction register DDR8 R/W Port 8 00000000B 19H Port 9 direction register DDR9 R/W Port 9 00000000B APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address Register Name Access Peripheral Initial value 1AH Port A direction register DDRA R/W Port A --000000B 1BH Port B direction register DDRB R/W Port B 00000000B 1CH Port C direction register DDRC R/W Port C ----0000B 1DH Port 4 output pin register ODR4 R/W Port 4 00000000B 1EH Analog input enable register ADER R/W Port 8, A/D 11111111B UART0 00000000B 1FH Not available 20H Serial mode register 0 SMR0 R/W 21H Serial control register 0 SCR0 R/W 22H Serial input data register 0/serial output data register 0 SIDR0/ SODR0 R/W 23H Serial status register 0 SSR0 R/W 00001-00B 24H Serial mode register 1 SMR1 R/W 00000000B 25H Serial control register 1 SCR1 R/W 00000100B 26H Serial input data register 1/serial output data register 1 SIDR1/ SODR1 R/W XXXXXXXXB 27H Serial status register 1 SSR1 R/W 00001-00B 28H Communication prescaler control register 0 CDCR0 R/W 29H 2AH UART0 UART1 Communication prescaler control register 1 CDCR1 R/W UART0 DTP/interrupt enable register ENIR R/W 31H DTP/interrupt source register EIRR R/W Request level setting register ELVR R/W UART1 DTP/ external interrupt XXXXXXXXB 00000000B 00000000B 34H to 35H Not available Control status register 37H 39H 0---1111B 00000000B 33H 38H 0---1111B Not available 30H 36H XXXXXXXXB Not available 2BH to 2FH 32H 00000100B Data register ADCS1 ADCS2 R/W ADCR1 ADCR2 R 00000000B A/D converter 00000000B XXXXXXXXB 00001-XXB 437 APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address Register Name Access 3AH D/A converter data register 0 DADR0 R/W 3BH D/A converter data register 1 DADR1 R/W 3CH D/A control register 0 DACR0 R/W 3DH D/A control register 1 DACR1 R/W 3EH Clock output enable register CLKR R/W 3FH Initial value XXXXXXXXB D/A converter XXXXXXXXB -------0B -------0B Clock monitor function ----0000B Not available 40H Reload register L (channel 0) PRLL0 R/W XXXXXXXXB 41H Reload register H (channel 0) PRLH0 R/W XXXXXXXXB 42H Reload register L (channel 1) PRLL1 R/W XXXXXXXXB 43H Reload register H (channel 1) PRLH1 R/W XXXXXXXXB 8/16bit PPG0/1 44H PPG0 operating mode control register PPGC0 R/W 45H PPG1 operating mode control register PPGC1 R/W 0X000001B 46H PPG0 and PPG1 output pin control register PPGOE R/W 000000XXB 47H 48H 4AH Serial mode control status register 0 Serial shift data register 0 4BH 4CH SMCS0 R/W SDR0 R/W Serial mode control status register 1 Serial shift data register 1 4FH 50H SMCS1 R/W SDR1 R/W Input capture register (channel 0) IPCP0 55H Extended serial I/O interface 1 00000010B XXXXXXXXB ----0000B 00000010B XXXXXXXXB Input capture register (channel 1) IPCP1 Input capture control status register ICS01 Not available XXXXXXXXB R R 53H 54H ----0000B Not available 51H 52H Extended serial I/O interface 0 Not available 4DH 4EH 0X000XX1B Not available 49H 438 Peripheral R/W 16-bit I/O timer (input capture block) XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address 56H Register Timer counter data register Name Access TCDT R/W 57H 58H Timer counter control status register 59H 5AH TCCS R/W Output compare register (channel 0) OCCP0 16-bit I/O timer (free run timer block) 00000000B Output compare register (channel 1) OCCP1 R/W Output compare register (channel 2) OCCP2 16-bit I/O timer (output compare block) R/W 5FH 60H 00000000B 00000000B XXXXXXXXB R/W 5DH 5EH Initial value Not available 5BH 5CH Peripheral XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Output compare register (channel 3) OCCP3 XXXXXXXXB R/W 61H XXXXXXXXB 62H Output compare control status register (channel 0) OCS0 R/W 63H Output compare control status register (channel 1) OCS1 R/W 64H Output compare control status register (channel 2) OCS2 R/W 0000--00B 65H Output compare control status register (channel 3) OCS3 R/W ---00000B 00000000B 66H to 67H 16-bit I/O timer (output compare block) 0000--00B ---00000B Not available 68H Bus status register IBSR R/W 69H Bus control register IBCR R/W 00000000B I2C interface 6AH Clock control register ICCR R/W 6BH Address register IADR R/W -XXXXXXXB 6CH Data register IDAR R/W XXXXXXXXB 6DH to 6EH Not available 6FH ROM mirror function selection register ROMM 70H Up/Down count register 0 UDCR0 71H --0XXXXXB Up/Down count register 1 UDCR1 W ROM mirror function R 8/16-bit up/ down timer counter -------1B 00000000B 00000000B 439 APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address Register Name Access Initial value 00000000B 72H Reload/Compare register 0 73H Reload/Compare register 1 RCR1 74H Counter status register 0 CSR0 R/W 00000000B 75H Reserved area - - - 76H R/W CCRH0 Counter status register 1 79H Reserved area - - -0000000B R/W CCRH1 Serial shift data register 2 7FH 00000000 00000000 CCRL1 Serial mode control status register 2 -0000000B R/W SMCS2 -0000000B R/W 7DH 7EH 8/16-bit up/ down timer counter CSR1 Counter control register 1 7BH 7CH 00000000B CCRL0 Counter control register 0 78H 7AH RCR0 W 77H SDR2 R/W Extended serial I/O interface 2 ----0000B 00000010B XXXXXXXXB Not available 80H Chip select control register 0 CSCR0 R/W ----0000B 81H Chip select control register 1 CSCR1 R/W ----0000B 82H Chip select control register 2 CSCR2 R/W ----0000B 83H Chip select control register 3 CSCR3 R/W 84H Chip select control register 4 CSCR4 R/W ----0000B 85H Chip select control register 5 CSCR5 R/W ----0000B 86H Chip select control register 6 CSCR6 R/W ----0000B 87H to 8BH Chip select ----0000B Not available 8CH Port 0 resistor register RDR0 R/W Port 0 00000000B 8DH Port 1 resistor register RDR1 R/W Port 1 00000000B 8EH Port 6 resistor register RDR6 R/W Port 6 00000000B R/W Address match detection function 00000000B R/W Delayed interrupt requesting module 8FH to 9DH 440 Peripheral Not available 9EH Program address detection control status register 9FH Delayed interrupt source generation/ release register PACSR DIRR -------0B APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address Register Name Access A0H Low power consumption mode control register LPMCR R/W A1H Clock selection register CKSCR R/W A2H to A4H Peripheral Low-power consumption control circuit Initial value 00011000B 11111100B Not available A5H Automatic ready function selection register ARSR W A6H External address output control register HACR W A7H Bus control signal selection register ECSR W A8H Watchdog timer control register WDTC R/W Watchdog timer XXXXXXXXB A9H Timebase timer control register TBTC R/W Time-base timer 1--00100B AAH Watch timer control register WTC R/W Watch timer 1X000000B R/W Flash memory 00010--0B ABH to ADH AEH External bus pin control circuit 0011--00B 00000000B 0000000-B Not available Flash memory control status register AFH FMCS Not available B0H Interrupt control register 00 ICR00 R/W 00000111B B1H Interrupt control register 01 ICR01 R/W 00000111B B2H Interrupt control register 02 ICR02 R/W 00000111B B3H Interrupt control register 03 ICR03 R/W 00000111B B4H Interrupt control register 04 ICR04 R/W 00000111B B5H Interrupt control register 05 ICR05 R/W 00000111B B6H Interrupt control register 06 ICR06 R/W 00000111B B7H Interrupt control register 07 ICR07 R/W B8H Interrupt control register 08 ICR08 R/W B9H Interrupt control register 09 ICR09 R/W 00000111B BAH Interrupt control register 10 ICR10 R/W 00000111B BBH Interrupt control register 11 ICR11 R/W 00000111B BCH Interrupt control register 12 ICR12 R/W 00000111B BDH Interrupt control register 13 ICR13 R/W 00000111B BEH Interrupt control register 14 ICR14 R/W 00000111B BFH Interrupt control register 15 ICR15 R/W 00000111B Interrupt controller 00000111B 00000111B 441 APPENDIX A I/O Map Table A-1 I/O Map (Continued) Address Register Name C0H to FFH External area 100H to #H RAM area #H to 1FEFH Reserved area 1FF0H 1FF1H Access R/W Program address detection register 0 PADR0 R/W 1FF3H R/W Program address detection register 1 PADR1 1FF5H 1FF6H to 1FFFH Initial value XXXXXXXXB R/W 1FF2H 1FF4H Peripheral XXXXXXXXB Address match detection function XXXXXXXXB XXXXXXXXB R/W XXXXXXXXB R/W XXXXXXXXB Reserved area Note: Note: for programmable bits, initial individual values show values at initialization by reset, not at read-out. In addition, parts or all of LPMCR, CKSCR, and WDTC are not always initialized, depending on the type of reset. The initial values shown above indicate values at initialization. • Addresses 00FFH and later are reserved. External bus access signals are not generated. • The boundary address #H between the RAM area and reserved area is 1900H for the MB90573 and 1FEFH for the MB90574 and MB90574C. In the latter case, no reserved area exists. • Explanation on read/write • 442 • R/W: Read and write allowed • R: Read only • W: Write only Explanation on the initial value • 0: The initial value of this bit is 0. • 1: The initial value of this bit is 1. • X: The initial value of this bit is unpredictable. • *: This bit is unused. The initial value is undefined. APPENDIX B INSTRUCTIONS APPENDIX B INSTRUCTIONS Appendix B describes the instructions used by the F2MC-16LX. B.1 "Instruction Types" B.2 "Addressing" B.3 "Direct Addressing" B.4 "Indirect Addressing" B.5 "Number of Execution Cycles" B.6 "Effective Address Field" B.7 "How to Read the Instruction List" B.8 "F2MC-16LX Instruction List" B.9 "Instruction Map" 443 APPENDIX B INSTRUCTIONS B.1 Instruction Types The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. ■ Instruction Types The F2MC-16LX supports the following 351 types of instructions: 444 • 41 transfer instructions (byte) • 38 transfer instructions (word or long word) • 42 addition/subtraction instructions (byte, word, or long word) • 12 increment/decrement instructions (byte, word, or long word) • 11 comparison instructions (byte, word, or long word) • 11 unsigned multiplication/division instructions (word or long word) • 11 signed multiplication/division instructions (word or long word) • 39 logic instructions (byte or word) • 6 logic instructions (long word) • 6 sign inversion instructions (byte or word) • 1 normalization instruction (long word) • 18 shift instructions (byte, word, or long word) • 50 branch instructions • 6 accumulator operation instructions (byte or word) • 28 other control instructions (byte, word, or long word) • 21 bit operation instructions • 10 string instructions APPENDIX B INSTRUCTIONS B.2 Addressing With the F2MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used. Some instructions permit the user to select several types of addressing. ■ Addressing The F2MC-16LX supports the following 23 types of addressing: • Immediate (#imm) • Register direct • Direct branch address (addr16) • Physical direct branch address (addr24) • I/O direct (io) • Abbreviated direct address (dir) • Direct address (addr16) • I/O direct bit address (io:bp) • Abbreviated direct bit address (dir:bp) • Direct bit address (addr16:bp) • Vector address (#vct) • Register indirect (@RWj j = 0 to 3) • Register indirect with post increment (@RWj+ j = 0 to 3) • Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj+ disp16 j = 0 to 3) • Long register indirect with displacement (@RLi + disp8 i = 0 to 3) • Program counter indirect with displacement (@PC + disp16) • Register indirect with base index (@RW0 + RW7, @RW1 + RW7) • Program counter relative branch address (rel) • Register list (rlst) • Accumulator indirect (@A) • Accumulator indirect branch address (@A) • Indirectly-specified branch address (@ear) • Indirectly-specified branch address (@eam) 445 APPENDIX B INSTRUCTIONS ■ Effective Address Field Table B.2-1 "Effective Address Field" lists the address formats specified by the effective address field. Table B.2-1 Effective Address Field Code 446 Representation 00 01 02 03 04 05 06 07 R0 R1 R2 R3 R4 R5 R6 R7 08 09 0A 0B @RW0 @RW1 @RW2 @RW3 0C 0D 0E 0F RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Address format Default bank Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. None Register indirect DTB DTB ADB SPB @RW0+ @RW1+ @RW2+ @RW3+ Register indirect with post increment DTB DTB ADB SPB 10 11 12 13 @RW0+disp8 @RW1+disp8 @RW2+disp8 @RW3+disp8 Register indirect with 8-bit displacement DTB DTB ADB SPB 14 15 16 17 @RW4+disp8 @RW5+disp8 @RW6+disp8 @RW7+disp8 Register indirect with 8-bit displacement DTB DTB ADB SPB 18 19 1A 1B @RW0+disp16 @RW1+disp16 @RW2+disp16 @RW3+disp16 Register indirect with 16-bit displacement DTB DTB ADB SPB 1C 1D 1E 1F @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address DTB DTB PCB DTB APPENDIX B INSTRUCTIONS B.3 Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct Addressing ❍ Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of immediate addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution A 2233 4455 After execution A 4 4 5 5 1 2 1 2 (Some instructions transfer AL to AH.) ❍ Register direct addressing Specify a register explicitly as an operand. Table B.3-1 "Direct Addressing Registers" lists the registers that can be specified. Figure B.3-2 "Example of Register Direct Addressing" shows an example of register direct addressing. Table B.3-1 Direct Addressing Registers General-purpose register Special-purpose register Byte R0, R1, R2, R3, R4, R5, R6, R7 Word RW0, RW1, RW2, RW3, RW4, R5W, RW6, RW7 Long word RL0, RL1, RL2, RL3 Accumulator A, AL Pointer SP* Bank PCB, DTB, USB, SSB, ADB Page DPR Control PS, CCR, RP, ILM *1 One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on the value of the S flag bit in the condition code register (CCR). For branch instructions, the program counter (PC) is not specified in an instruction operand but is specified implicitly. 447 APPENDIX B INSTRUCTIONS Figure B.3-2 Example of Register Direct Addressing MOV R0, A (This instruction transfers the eight low-order bits of A to the general-purpose register R0.) Before execution A 0716 2534 After execution A 0716 2564 Memory space R0 ?? Memory space R0 34 ❍ Direct branch addressing (addr16) Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which indicates the branch destination in the logical address space. Direct branch addressing is used for an unconditional branch, subroutine call, or software interrupt instruction. Bits 23 to 16 of the address are specified by the program bank register (PCB). Figure B.3-3 Example of Direct Branch Addressing (addr16) JMP 3B20H (This instruction causes an unconditional branch by direct branch addressing in a bank.) Before execution After execution PC 3 C 2 0 PCB 4 F PC 3 B 2 0 Memory space 4F3C22H 4F3C21H 4F3C20H 3B 20 62 4F3B20H Next instruction JMP 3B20H PCB 4 F ❍ Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure B.3-4 Example of Direct Branch Addressing (addr24) JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit addressing.) Before execution After execution 448 PC 3 C 2 0 PC 3 B 2 0 PCB 4 F Memory space 4F3C23H 4F3C22H 4F3C21H 4F3C20H 33 3B 20 63 333B20H Next instruction PCB 3 3 JMPP 333B20H APPENDIX B INSTRUCTIONS ❍ I/O direct addressing (io) Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB) and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an instruction using I/O direct addressing. Figure B.3-5 Example of I/O Direct Addressing (io) MOVW A, i:0C0H (This instruction reads data by I/O direct addressing and stores it in A.) Before execution A 0716 2534 Memory space 0000C1H 0000C0H After execution A FF EE 2534 FFEE ❍ Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Figure B.3-6 Example of Abbreviated Direct Addressing (dir) MOVW S;20H, A (This instruction writes the contents of the eight low-order bits of A in abbreviated direct addressing mode.) Before execution 4455 A 66 After execution A DTB 7 7 4455 66 Memory space 1212 776620H 1212 DTB 7 7 ?? Memory space 776620H 12 ❍ Direct addressing (addr16) Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for this mode of addressing. Figure B.3-7 Example of Direct Addressing (addr16) BRA 3B20H (This instruction causes an unconditional relative branch.) Before execution PC 3C20 PCB 4 F Memory space 4F3C22H 4F3C21H 4F3C20H After execution PC 3B20 FF FE 60 BRA 3B20H PCB 4 F 4F3B20H 449 APPENDIX B INSTRUCTIONS ❍ I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp) SETB I:0C1H: (This instruction sets bits by I/O direct bit addressing.) Memory space Before execution 0000C1H 00 After execution 0000C1H 01 ❍ Abbreviated direct bit addressing (dir:bp) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-9 Example of Abbreviated Direct Bit Addressing (dir:bp) SETB S:10H:0 (This instruction sets bits by abbreviated direct bit addressing.) Memory space Before execution DTB 5 5 DPR 6 6 556610H 00 Memory space After execution DTB 5 5 DPR 6 6 556610H 01 ❍ Direct bit addressing (addr16:bp) Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-10 Example of Direct Bit addressing (addr16:bp) SETB 2222H:0 (This instruction sets bits by direct bit addressing.) Memory space Before execution DTB 5 5 552222H 00 Memory space After execution 450 DTB 5 5 552222H 01 APPENDIX B INSTRUCTIONS ❍ Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure B.3-11 Example of Vector Addressing (#vct) CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector specified in an operand.) Before execution PC 0000 PCB F F After execution PC Memory space FFFFE1H FFFFE0H D0 00 FFC000H EF D000 PCB F F CALLV #15 Table B.3-2 CALLV Vector List Instruction Vector address L Vector address H CALLV #0 XFFFEH XXFFFFH CALLV #1 XFFFCH XXFFFDH CALLV #2 XFFFAH XXFFFBH CALLV #3 XFFF8H XXFFF9H CALLV #4 XFFF6H XXFFF7H CALLV #5 XFFF4H XXFFF5H CALLV #6 XFFF2H XXFFF3H CALLV #7 XFFF0H XXFFF1H CALLV #8 XFFEEH XXFFEFH CALLV #9 XFFECH XXFFEDH CALLV #10 XFFEAH XXFFEBH CALLV #11 XFFE8H XXFFE9H CALLV #12 XFFE6H XXFFE7H CALLV #13 XFFE4H XXFFE5H CALLV #14 XFFE2H XXFFE3H CALLV #15 XFFE0H XXFFE1H Note: A PCB register value is set in XX. Note: When the program bank register (PCB) is FFH, the vector area overlaps the vector area of INT #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2 "CALLV Vector List"). 451 APPENDIX B INSTRUCTIONS B.4 Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect Addressing ❍ Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. Figure B.4-1 Example of Register Indirect Addressing (@RWj j = 0 to 3) MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores it in A.) Before execution A 0716 2534 RW1 D 3 0 F DTB 7 8 After execution A Memory space 78D310H 78D30FH FF EE 2534 FFEE RW1 D 3 0 F DTB 7 8 ❍ Register indirect addressing with post increment (@RWj+ j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. After operand operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word). Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. If the post increment results in the address of the register that specifies the increment, the incremented value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to writing by an instruction and, therefore, the register that would be incremented becomes write data. 452 APPENDIX B INSTRUCTIONS Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj + j = 0 to 3) MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F DTB 7 8 After execution A 78D310H 78D30FH FF EE 2534 FFEE RW1 D 3 1 1 DTB 7 8 ❍ Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) Memory is accessed using the address obtained by adding an offset to the contents of generalpurpose register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is used, or additional data bank register (ADB) when RW2 or RW6 is used. Figure B.4-3 Example of Register Indirect Addressing with Offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F DTB 7 8 78D320H 78D31FH FF EE (+10H) After execution A 2534 FFEE RW1 D 3 0 F DTB 7 8 ❍ Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value. Figure B.4-4 Example of Long Register Indirect Addressing with Offset (@RLi + disp8 i = 0 to 3) MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with an offset and stores it in A.) Before execution A RL2 0716 2534 F382 4B02 Memory space 824B28H 824B27H FF EE (+25H) After execution A 2534 FFEE RL2 F382 4B02 453 APPENDIX B INSTRUCTIONS ❍ Program counter indirect addressing with offset (@PC + disp16) Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one word long. Address bits 16 to 23 are specified by the program bank register (PCB). Note that the operand address of each of the following instructions is not deemed to be (next instruction address + disp16): • DBNZ eam, rel • DWBNZ eam, rel • CBNE eam, #imm8, rel • CWBNE eam, #imm16, rel • MOV eam, #imm8 • MOVW eam, #imm16 Figure B.4-5 Example of Program Counter Indirect Addressing with Offset (@PC + disp16) MOVW A, @PC+20H (This instruction reads data by program counter indirect addressing with a offset and stores it in A.) Before execution A 0716 2534 PCB C 5 PC 4 5 5 6 After execution A 2534 FFEE PCB C 5 PC 4 5 5 A Memory space C5457BH C5457AH FF EE C5455AH +20H C54559H +4 C54558H C54557H C54556H 00 20 9E 73 MOVW A, @PC+20H ❍ Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) Memory is accessed using the address determined by adding RW0 or RW1 to the contents of general-purpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB). Figure B.4-6 Example of Register Indirect Addressing with Base Index (@RW0 + RW7, @RW1 + RW7) MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a base index and stores it in A.) Before execution A 0716 RW1 D 3 0 F 2534 DTB 7 8 + RW7 0 1 0 1 After execution A 2534 FFEE RW1 D 3 0 F RW7 0 1 0 1 454 DTB 7 8 Memory space 78D411H 78D410H FF EE APPENDIX B INSTRUCTIONS ❍ Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to 23 are indicated by the program bank register (PCB). Figure B.4-7 Example of Program Counter Relative Branch Addressing (rel) BRA 3B20H (This instruction causes an unconditional relative branch.) Before execution PC 3C20 PCB 4 F Memory space 4F3C22H 4F3C21H 4F3C20H After execution PC 3B20 FF FE 60 BRA 3B20H PCB 4 F 4F3B20H Next instruction ❍ Register list (rlst) Specify a register to be pushed onto or popped from a stack. Figure B.4-8 Configuration of the Register List MSB LSB RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0 A register is selected when the corresponding bit is 1 and deselected when the bit is 0. 455 APPENDIX B INSTRUCTIONS Figure B.4-9 Example of Register List (rlist) POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) SP 34FA SP RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 SP 02 01 04 03 Memory space Memory space SP 34FEH 34FDH 34FCH 34FBH 34FAH 04 03 02 01 34FE 04 03 02 01 34FEH 34FDH 34FCH 34FBH 34FAH After execution Before execution ❍ Accumulator indirect addressing (@A) Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB). Figure B.4-10 Example of Accumulator Indirect Addressing (@A) MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.) Before execution A 0716 2534 DTB B B After execution A Memory space BB2535H BB2534H FF EE 0716 FFEE DTB B B ❍ Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program bank register (PCB). For the Jump Context (JCTX) instruction, however, address bits 16 to 23 are specified by the data bank register (DTB). This addressing 456 APPENDIX B INSTRUCTIONS is used for unconditional branch instructions. Figure B.4-11 Example of Accumulator Indirect Branch Addressing (@A) JMP @A (This instruction causes an unconditional branch by accumulator indirect branch addressing.) Before execution PC 3C20 PCB 4 F A 6677 3B20 PC 3B20 PCB 4 F A 6677 3B20 Memory space 4F3C20H 4F3B20H After execution 61 JMP @A Next instruction ❍ Indirect specification branch addressing (@ear) The address of the branch destination is the word data at the address indicated by ear. Figure B.4-12 Example of Indirect Specification Branch Addressing (@ear) JMP @@RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution 3C20 PCB 4 F PW0 7 F 4 8 DTB 2 1 PC Memory space 4F3C21H 4F3C20H 4F3B20H After execution 3B20 PCB 4 F PW0 7 F 4 8 DTB 2 1 PC 217F49H 217F48H 08 73 JMP @@RW0 Next instruction 3B 20 ❍ Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam) JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution PC 3C20 PCB 4 F 4F3C21H 4F3C20H PW0 3 B 2 0 After execution PC 3B20 Memory space PCB 4 F 4F3B20H 00 73 JMP @RW0 Next instruction PW0 3 B 2 0 457 APPENDIX B INSTRUCTIONS B.5 Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. ■ Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments. Therefore, intervening in data access increases the execution cycle count. Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the program fetches every byte of an instruction being executed. Therefore, intervening in data access increases the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register, internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register. Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add the "access count x cycle count for the halt" as a correction value to the normal execution count. ■ Calculating the Execution Cycle Count Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" lists execution cycle counts and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" and Table B.53 "Cycle Count Correction Values for Counting Instruction Fetch Cycles" summarize correction value data. 458 APPENDIX B INSTRUCTIONS Table B.5-1 Execution Cycle Counts in Each Addressing Mode Code (a)* Operand *: 00 | 07 Ri Rwi RLi 08 | 0B Execution cycle count in each addressing mode Register access count in each addressing mode See the instruction list. See the instruction list. @RWj 2 1 0C | 0F @RWj+ 4 2 10 | 17 @RWi+disp8 2 1 18 | 1B @RWi+disp16 2 1 1C 1D 1E 1F @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 4 4 2 1 2 2 0 0 (a) is used for ~ (cycle count) and B (correction value) in B-8, "F2MC-16LX Instruction List". 459 APPENDIX B INSTRUCTIONS Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles Operand (b) byte(*1) (c) word(*1) (d) long(*1) Cycle count Access count Cycle count Access count Cycle count Access count Internal register +0 1 +0 1 +0 2 Internal memory Even address +0 1 +0 1 +0 2 Internal memory Odd address +0 1 +2 2 +4 4 External data bus 16-bit even address +1 1 +1 1 +2 2 External data bus 16-bit odd address +1 1 +4 2 +8 4 External data bus 8 bits +1 1 +4 2 +8 4 *1: (b), (c), and (d) are used for ~ (cycle count) and B (correction value) in B.8, "F2MC16LX Instruction List". Note: When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. Table B.5-3 Cycle Count Correction Values for Counting Instruction Fetch Cycles Instruction Byte boundary Word boundary Internal memory — +2 External data bus 16 bits — +3 External data bus 8 bits +3 — Notes: 460 • When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. • Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the correction values to calculate the worst case. APPENDIX B INSTRUCTIONS B.6 Effective Address Field Table B.6-1 "Effective Address Field" shows the effective address field. ■ Effective Address Field Table B.6-1 Effective Address Field Code Representation 00 01 02 03 04 05 06 07 R0 R1 R2 R3 R4 R5 R6 R7 08 09 0A 0B RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Address format Byte count of extended address part (*1) Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. — @RW0 @RW1 @RW2 @RW3 Register indirect 0 0C 0D 0E 0F @RW0+ @RW1+ @RW2+ @RW3+ Register indirect with post increment 0 10 11 12 13 14 15 16 17 @RW0+disp8 @RW1+disp8 @RW2+disp8 @RW3+disp8 @RW4+disp8 @RW5+disp8 @RW6+disp8 @RW7+disp8 Register indirect with 8-bit displacement 1 18 19 1A 1B @RW0+disp16 @RW1+disp16 @RW2+disp16 @RW3+disp16 Register indirect with 16-bit displacement 2 1C 1D 1E 1F @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address 0 0 2 2 *1: Each byte count of the extended address part applies to + in the # (byte count) column in the "F2MC-16LX Instruction List" in Appendix B.8. 461 APPENDIX B INSTRUCTIONS B.7 How to Read the Instruction List Table B.7-1 "Description of Items in the Instruction List" describes the items used in the F2MC-16LX Instruction List, and Table B.7-2 "Explanation on Symbols in the Instruction List" describes the symbols used in the same list. ■ Description of instruction presentation items and symbols Table B.7-1 Description of Items in the Instruction List Item Mnemonic Uppercase, symbol: Represented as is in the assembler. Lowercase: Rewritten in the assembler. Number of following lowercase: Indicates bit length in the instruction. # Indicates the number of bytes. ~ Indicates the number of cycles. See Table B.2-1 "Effective Address Field" for the alphabetical letters in items. RG B Operation 462 Description Indicates the number of times a register access is performed during instruction execution. The number is used to calculate the correction value for CPU intermittent operation. Indicates the correction value used to calculate the actual number of cycles during instruction execution. The actual number of cycles during instruction execution can be determined by adding the value in the ~ column to this value. Indicates the instruction operation. LH Indicates the special operation for bits 15 to 08 of the accumulator. Z: Transfers 0. X: Transfers after sign extension. -: No transfer AH Indicates the special operation for the 16 high-order bits of the accumulator. *: Transfers from AL to AH. -: No transfer Z: Transfers 00 to AH. X: Transfers 00H or FFH to AH after AL sign extension. APPENDIX B INSTRUCTIONS Table B.7-1 Description of Items in the Instruction List (Continued) Item Description I S T N Z Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry). *: Changes upon instruction execution. -: No change Z: Set upon instruction execution. X: Reset upon instruction execution. V C RMW Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory). *: Read Modify Write instruction -: Not Read Modify Write instruction Note: Cannot be used for an address that has different meanings between read and write operations. Table B.7-2 Explanation on Symbols in the Instruction List Symbol A Explanation The bit length used varies depending on the 32-bit accumulator instruction. Byte: Low-order 8 bits of byte AL Word: 16 bits of word AL Long word: 32 bits of AL and AH AH AL 16 high-order bits of A 16 low-order bits of A SP Stack pointer (USP or SSP) PC Program counter PCB Program bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register (SSB or USB) DPR Direct page register brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB Ri R0, R1, R2, R3, R4, R5, R6, R7 463 APPENDIX B INSTRUCTIONS Table B.7-2 Explanation on Symbols in the Instruction List (Continued) Symbol RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3 RLi RL0, RL1, RL2, RL3 dir Abbreviated direct addressing addr16 addr24 ad24 0-15 ad24 16-23 io #imm4 #imm8 #imm16 #imm32 ext (imm8) disp8 disp16 bp Direct addressing Physical direct addressing Bits 0 to 15 of addr24 Bits 16 to 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data obtained by sign extension of 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset vct4 vct8 Vector number (0 to 15) Vector number (0 to 255) ( )b Bit address rel ear eam PC relative branch effective addressing (code 00 to 07) Effective addressing (code 08 to 1F) rlst 464 Explanation Register list APPENDIX B INSTRUCTIONS B.8 F2MC-16LX Instruction List Table B.8-1 "41 Transfer Instructions (byte)" to Table B.9-19 "MOVW ea, Rwi Instruction (first byte = 7DH)" list the instructions used by the F2MC-16LX. ■ Table B.8-1 41 Transfer Instructions (byte) Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RLi+disp8 A,#imm4 2 3 1 2 2+ 2 2 2 3 1 3 4 2 2 3+(a) 3 2 3 10 1 0 0 1 1 0 0 0 0 2 0 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 byte (A) <-- (dir) byte (A) <-- (addr16) byte (A) <-- (Ri) byte (A) <-- (ear) byte (A) <-- (eam) byte (A) <-- (io) byte (A) <-- imm8 byte (A) <-- ((A)) byte (A) <-- ((RLi)+disp8) byte (A) <-- imm4 Z Z Z Z Z Z Z Z Z Z * * * * * * * * * - - * * * * * * * * * R * * * * * * * * * * - - - - MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX A,dir A,addr16 A,Ri A,ear A,eam A,io A,#imm8 A,@A A,@RWi+disp8 A,@RLi+disp8 2 3 2 2 2+ 2 2 2 2 3 3 4 2 2 3+(a) 3 2 3 5 10 0 0 1 1 0 0 0 0 1 2 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) byte (A) <-- (dir) byte (A) <-- (addr16) byte (A) <-- (Ri) byte (A) <-- (ear) byte (A) <-- (eam) byte (A) <-- (io) byte (A) <-- imm8 byte (A) <-- ((A)) byte (A) <-- ((RWi)+disp8) byte (A) <-- ((RLi)+disp8 X X X X X X X X X X * * * * * * * * * - - - * * * * * * * * * * * * * * * * * * * * - - - MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV dir,A addr16,A Ri,A ear,A eam,A io,A @RLi+disp8,A Ri,ear Ri,eam ear,Ri eam,Ri Ri,#imm8 io,#imm8 dir,#imm8 ear,#imm8 eam,#imm8 @AL,AH/ MOV 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 3 4 2 2 3+(a) 3 10 3 4+(a) 4 5+(a) 2 5 5 2 4+(a) 3 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) byte (dir) <-- (A) byte (addr16) <-- (A) byte (Ri) <-- (A) byte (ear) <-- (A) byte (eam) <-- (A) byte (io) <-- (A) byte ((RLi)+disp8) <-- (A) byte (Ri) <-- (ear) byte (Ri) <-- (eam) byte (ear) <-- (Ri) byte (eam) <-- (Ri) byte (Ri) <-- imm8 byte (io) <-- imm8 byte (dir) <-- imm8 byte (ear) <-- imm8 byte (eam) <-- imm8 byte ((A)) <-- (AH) - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - 2 2+ 2 2+ 4 5+(a) 7 9+(a) 2 0 4 2 0 2×(b) 0 2×(b) byte (A) <--> (ear) byte (A) <--> (eam) byte (Ri) <--> (ear) byte (Ri) <--> (eam) Z Z - - - - - - - - - - @A,T XCH XCH XCH XCH A,ear A,eam Ri,ear Ri,eam Note: See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) in the table. 465 APPENDIX B INSTRUCTIONS Table B.8-2 38 Transfer Instructions (byte) Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A,dir A,addr16 A,SP A,RWi A,ear A,eam A,io A,@A A,#imm16 A,@RWi+disp8 A,@RLi+disp8 2 3 1 1 2 2+ 2 2 3 2 3 3 4 1 2 2 3+(a) 3 3 2 5 10 0 0 0 1 1 0 0 0 0 1 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) word (A) <-- (dir) word (A) <-- (addr16) word (A) <-- (SP) word (A) <-- (RWi) word (A) <-- (ear) word (A) <-- (eam) word (A) <-- (io) word (A) <-- ((A)) word (A) <-- imm16 word (A) <-- ((RWi)+disp8) word (A) <-- ((RLi)+disp8) - * * * * * * * * * * - - - * * * * * * * * * * * * * * * * * * * * * * - - - MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW dir,A addr16,A SP,A RWi,A ear,A eam,A io,A @RWi+disp8,A @RLi+disp8,A RWi,ear RWi,eam ear,Rwi eam,Rwi RWi,#imm16 io,#imm16 ear,#imm16 eam,#imm16 @AL,AH/MOVW @A,T 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 3 4 1 2 2 3+(a) 3 5 10 3 4+(a) 4 5+(a) 2 5 2 4+(a) 3 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 (c) (c) 0 0 0 (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) word (dir) <-- (A) word (addr16) <-- (A) word (SP) <-- (A) word (RWi) <-- (A) word (ear) <-- (A) word (eam) <-- (A) word (io) <-- (A) word ((RWi)+disp8) <-- (A) word ((RLi)+disp8) <-- (A) word (RWi) <-- (ear) word (RWi) <-- (eam) word (ear) <-- (RWi) word (eam) <-- (RWi) word (RWi) <-- imm16 word (io) <-- imm16 word (ear) <-- imm16 word (eam) <-- imm16 word ((A)) <-- (AH) - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - XCHW XCHW XCHW XCHW A,ear A,eam RWi, ear RWi, eam 2 2+ 2 2+ 4 5+(a) 7 9+(a) 2 0 4 2 0 2 x (c) 0 2 x (c) word (A) <--> (ear) word (A) <-- >(eam) word (RWi) <--> (ear) word (RWi) <--> (eam) - - - - - - - - - - MOVL MOVL MOVL A,ear A,eam A,#imm32 2 2+ 5 4 5+(a) 3 2 0 0 0 (d) 0 long (A) <-- (ear) long (A) <-- (eam) long (A) <-- imm32 - - - - - * * * * * * - - - MOVL MOVL ear,A eam,A 2 2+ 4 5+(a) 2 0 0 (d) long (ear1) <-- (A) long(eam1) <-- (A) - - - - - * * * * - - - Note: See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) in the table. 466 APPENDIX B INSTRUCTIONS Table B.8-3 42 Addition/subtraction Instructions (byte, word, long word) Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W byte (A) <-- (A) + imm8 byte (A) <-- (A) + (dir) byte (A) <-- (A) + (ear) byte (A) <-- (A) + (eam) byte (ear) <-- (ear) + (A) byte (eam) <-- (eam) + (A) byte (A) <-- (AH) + (AL) + (C) byte (A) <-- (A) + (ear)+ (C) byte (A) <-- (A) + (eam)+ (C) byte (A) <-- (AH) + (AL) + (C) (decimal) byte (A) <-- (A) - imm8 byte (A) <-- (A) - (dir) byte (A) <-- (A) - (ear) byte (A) <-- (A) - (eam) byte (ear) <-- (ear) - (A) byte (eam) <-- (eam) - (A) byte (A) <-- (AH) - (AL) - (C) byte (A) <-- (A) - (ear) - (C) byte (A) <-- (A) - (eam) - (C) byte (A) <-- (AH) - (AL) - (C) (decimal) Z Z Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - Z Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+(a) 3 5+(a) 2 3 4+(a) 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2×(b) 0 0 (b) 0 SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+(a) 3 5+(a) 2 3 4+(a) 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2×(b) 0 0 (b) 0 ADDW ADDW ADDW ADDW ADDW ADDW ADDCW ADDCW SUBW SUBW SUBW SUBW SUBW SUBW SUBCW SUBCW A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2×(c) 0 (c) 0 0 (c) 0 0 2×(c) 0 (c) word (A) <-- (AH) + (AL) word (A) <-- (A) + (ear) word (A) <-- (A) + (eam) word (A) <-- (A) + imm16 word (ear) <-- (ear) + (A) word (eam) <-- (eam) + (A) word (A) <-- (A) + (ear) + (C) word (A) <-- (A) + (eam) + (C) word (A) <-- (AH) - (AL) word (A) <-- (A) - (ear) word (A) <-- (A) - (eam) word (A) <-- (A) - imm16 word (ear) <-- (ear) - (A) word (eam) <-- (eam) - (A) word (A) <-- (A) - (ear) - (C) word (A) <-- (A) - (eam) - (C) - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - ADDL ADDL ADDL SUBL SUBL SUBL A,ear A,eam A,#imm32 A,ear A,eam A,#imm32 2 2+ 5 2 2+ 5 6 7+(a) 4 6 7+(a) 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (A) <-- (A) + (ear) long (A) <-- (A) + (eam) long (A) <-- (A) + imm32 long (A) <-- (A) - (ear) long (A) <-- (A) - (eam) long (A) <-- (A) - imm32 - - - - - * * * * * * * * * * * * * * * * * * * * * * * * - Note: See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) in the table. 467 APPENDIX B INSTRUCTIONS Table B.8-4 12 Increment/decrement Instructions (byte, word, long word) Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W 0 2×(b) 0 2×(b) byte (ear) <-- (ear) + 1 byte (eam) <-- (eam) + 1 - - - - - * * * * * * - * byte (ear) <-- (ear) - 1 byte (eam) <-- (eam) - 1 - - - - - * * * * * * - * 2 0 0 2×(c) word (ear) <-- (ear) + 1 word (eam) <-- (eam) + 1 - - - - - * * * * * * - * 3 5+(a) 2 0 0 2×(c) word (ear) <-- (ear) - 1 word (eam) <-- (eam) - 1 - - - - - * * * * * * - * 2 2+ 7 9+(a) 4 0 0 2×(d) long (ear) <-- (ear) + 1 long (eam) <-- (eam) + 1 - - - - - * * * * * * - * 2 2+ 7 9+(a) 4 0 0 2×(d) long (ear) <-- (ear) - 1 long (eam) <-- (eam) - 1 - - - - - * * * * * * - * INC INC ear eam 2 2+ 3 5+(a) 2 0 DEC DEC ear eam 2 2+ 3 5+(a) 2 0 INCW INCW ear eam 2 2+ 3 5+(a) DECW DECW ear eam 2 2+ INCL INCL ear eam DECL DECL ear eam Note: See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) in the table. Table B.8-5 11 Compare Instructions (byte, word, long word) Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W CMP CMP CMP CMP A A,ear A,eam A,#imm8 1 2 2+ 2 1 2 3+(a) 2 0 1 0 0 0 0 (b) 0 byte (AH) - (AL) byte (A) - (ear) byte (A) - (eam) byte (A) - imm8 - - - - - * * * * * * * * * * * * * * * * - CMPW CMPW CMPW CMPW A A,ear A,eam A,#imm16 1 2 2+ 3 1 2 3+(a) 2 0 1 0 0 0 0 (c) 0 word (AH) - (AL) word (A) - (ear) word (A) - (eam) word (A) - imm16 - - - - - * * * * * * * * * * * * * * * * - CMPL CMPL CMPL A,ear A,eam A,#imm32 2 2+ 5 6 7+(a) 3 2 0 0 0 (d) 0 long (A) - (ear) long (A) - (eam) long (A) - imm32 - - - - - * * * * * * * * * * * * - Note: See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) in the table. 468 APPENDIX B INSTRUCTIONS Table B.8-6 11 unsigned multiplication/division instructions (word, long word) Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W word (AH) / byte (AL) quotient --> byte (AL) remainder --> byte (AH) word (A) / byte (ear) quotient --> byte (A) remainder --> byte (ear) word (A) / byte (eam) quotient --> byte (A) remainder --> byte (eam) long (A) / word (ear) quotient --> word(A) remainder --> word(ear) long (A) / word (eam) quotient --> word(A) remainder --> word(eam) - - - - - - - * * - - - - - - - - * * - - - - - - - - * * - - - - - - - - * * - - - - - - - - * * - byte (AH) * byte (AL) --> word (A) byte (A) * byte (ear) --> word (A) byte (A) * byte (eam) --> word (A) word (AH) * word (AL) --> Long (A) word (A) * word (ear) --> Long (A) word (A) * word (eam) --> Long (A) - - - - - - - - - - DIVU A 1 *1 0 0 DIVU A,ear 2 *2 1 0 DIVU A,eam 2+ *3 0 *6 DIVUW A,ear 2 *4 1 0 DIVUW A,eam 2+ *5 0 *7 MULU MULU MULU MULUW MULUW MULUW A A,ear A,eam A A,ear A,eam 1 2 2+ 1 2 2+ *8 *9 *10 *11 *12 *13 0 1 0 0 1 0 0 0 (b) 0 0 (c) *1 3: Division by 0 7: Overflow 15: Normal *2 4: Division by 0 8: Overflow 16: Normal *3 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal *4 4: Division by 0 7: Overflow 22: Normal *5 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal *6 (b): Division by 0 or overflow 2 x (b): Normal *7 (c): Division by 0 or overflow 2 x (c): Normal *8 3: Byte (AH) is 0. 7: Byte (AH) is not 0. *9 4: Byte (ear) is 0. 8: Byte (ear) is not 0. *10 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0. *11 3: Word(AH) is 0. 11: Word (AH) is not 0. *12 4: Word(ear) is 0. 12: Word (ear) is not 0. *13 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0. Note: See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) in the table. 469 APPENDIX B INSTRUCTIONS Table B.8-7 11 Signed Multiplication/Division Instructions (word, long word) Mnemonic # ~ RG B DIVU A 2 *1 0 0 DIVU A,ear 2 *2 1 0 DIVU A,eam 2+ *3 0 *6 DIVUW A,ear 2 *4 1 0 DIVUW A,eam 2+ *5 0 *7 MUL MUL MUL MULW MULW MULW A A,ear A,eam A A,ear A,eam 2 2 2+ 2 2 2+ *8 *9 *10 *11 *12 *13 0 1 0 0 1 0 0 0 (b) 0 0 (c) Operation L H A H I S T N Z V C R M W word (AH) / byte (AL) quotient --> byte (AL) remainder --> byte (AH) word (A) / byte (ear) quotient --> byte (A) remainder --> byte (ear) word (A) / byte (eam) quotient --> byte (A) remainder --> byte (eam) long (A) / word (ear) quotient --> word(A) remainder --> word(ear) long (A) / word (eam) quotient --> word(A) remainder --> word(eam) Z - - - - - - * * - Z - - - - - - * * - Z - - - - - - * * - - - - - - - - * * - - - - - - - - * * - byte (AH) * byte (AL) --> word (A) byte (A) * byte (ear) --> word (A) byte (A) * byte (eam) --> word (A) word (AH) * word (AL) --> Long (A) word (A) * word (ear) --> Long (A) word (A) * word (eam) --> Long (A) - - - - - - - - - - - *1 3: Division by 0, 8 or 18: Overflow, 18: Normal *2 4: Division by 0, 11 or 22: Overflow, 23: Normal *3 5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal *4 When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal *5 When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal *6 (b): Division by 0 or overflow, 2 x (b): Normal *7 (c): Division by 0 or overflow, 2 x (c): Normal *8 3: Byte (AH) is 0, 12: result is positive, 13: result is negative *9 4: Byte (ear) is 0, 13: result is positive, 14: result is negative *10 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative *11 3: Word(AH) is 0, 16: result is positive, 19: result is negative *12 4: Word(ear) is 0, 17: result is positive, 20: result is negative *13 5+(a): Word(eam) is 0, 18+(a): result is positive, 21+(a): result is negative Note: • The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a pre-operation count or a post-operation count depending on the detection timing. Note: • When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed. Note: See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) 470 APPENDIX B INSTRUCTIONS in the table. Table B.8-8 39 Logic 1 Instructions (byte, word) Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W AND AND AND AND AND A,#imm8 A,ear A,eam ear,A eam,A 2 2 2+ 2 2+ 2 3 4+(a) 3 5+(a) 0 1 0 2 0 0 0 (b) 0 2×(b) byte (A) <-- (A) and imm8 byte (A) <-- (A) and (ear) byte (A) <-- (A) and (eam) byte (ear) <-- (ear)and (A) byte (eam) <-- (eam)and (A) - - - - - * * * * * * * * * * R R R R R - * OR OR OR OR OR A,#imm8 A,ear A,eam ear,A eam,A 2 2 2+ 2 2+ 2 3 4+(a) 3 5+(a) 0 1 0 2 0 0 0 (b) 0 2×(b) byte (A) <-- (A) or imm8 byte (A) <-- (A) or (ear) byte (A) <-- (A) or (eam) byte (ear) <-- (ear)or (A) byte (eam) <-- (eam)or (A) - - - - - * * * * * * * * * * R R R R R - * XOR XOR XOR XOR XOR NOT NOT NOT A,#imm8 A,ear A,eam ear,A eam,A A ear eam 2 2 2+ 2 2+ 1 2 2+ 2 3 4+(a) 3 5+(a) 2 3 5+(a) 0 1 0 2 0 0 2 0 0 0 (b) 0 2×(b) 0 0 2×(b) byte (A) <-- (A) xor imm8 byte (A) <-- (A) xor (ear) byte (A) <-- (A) xor (eam) byte (ear) <-- (ear)xor (A) byte (eam) <-- (eam)xor (A) byte (A) <-- not (A) byte (ear) <-- not (ear) byte (eam) <-- not (eam) - - - - - * * * * * * * * * * * * * * * * R R R R R R R R - * * ANDW ANDW ANDW ANDW ANDW ANDW A A,#imm16 A,ear A,eam ear,A eam,A 1 3 2 2+ 2 2+ 2 2 3 4+(a) 3 5+(a) 0 0 1 0 2 0 0 0 0 (c) 0 2×(c) word (A) <-- (AH) and (A) word (A) <-- (A) and imm16 word (A) <-- (A) and (ear) word (A) <-- (A) and (eam) word (ear) <-- (ear)and (A) word (eam) <-- (eam)and (A) - - - - - * * * * * * * * * * * * R R R R R R - * ORW ORW ORW ORW ORW ORW A A,#imm16 A,ear A,eam ear,A eam,A 1 3 2 2+ 2 2+ 2 2 3 4+(a) 3 5+(a) 0 0 1 0 2 0 0 0 0 (c) 0 2×(c) word (A) <-- (AH) or (A) word (A) <-- (A) or imm16 word (A) <-- (A) or (ear) word (A) <-- (A) or (eam) word (ear) <-- (ear)or (A) word (eam) <-- (eam)or (A) - - - - - * * * * * * * * * * * * R R R R R - * XORW XORW XORW XORW XORW XORW NOTW NOTW NOTW A A,#imm16 A,ear A,eam ear,A eam,A A ear eam 1 3 2 2+ 2 2+ 1 2 2+ 2 2 3 4+(a) 3 5+(a) 2 3 5+(a) 0 0 1 0 2 0 0 2 0 0 0 0 (c) 0 2×(c) 0 0 2×(c) word (A) <-- (AH) xor (A) word (A) <-- (A) xor imm16 word (A) <-- (A) xor (ear) word (A) <-- (A) xor (eam) word (ear) <-- (ear)xor (A) word (eam) <-- (eam)xor (A) word (A) <-- not (A) word (ear) <-- not (ear) word (eam) <-- not (eam) - - - - - * * * * * * * * * * * * * * * * - * * R R R R R R R R R Note: See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) in the table. 471 APPENDIX B INSTRUCTIONS Table B.8-9 Six Logic 2 Instructions (long word) Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W ANDL ANDL A,ear A,eam 2 2+ 6 7+(a) 2 0 0 (d) long (A) <-- (A) and (ear) long (A) <-- (A) and (eam) - - - - - * * * * R R - - ORL ORL A,ear A,eam 2 2+ 6 7+(a) 2 0 0 (d) long (A) <-- (A) or (ear) long (A) <-- (A) or (eam) - - - - - * * * * R R - - XORL XORL A,ear A,eam 2 2+ 6 7+(a) 2 0 0 (d) long (A) <-- (A) xor (ear) long (A) <-- (A) xor (eam) - - - - - * * * * R R - - Note: See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) in the table. Table B.8-10 Six Sign Inversion Instructions (byte, word) Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W NEG A 1 2 0 0 byte (A) <-- 0 - (A) X - - - - * * * * - NEG NEG ear eam 2 2+ 3 5+(a) 2 0 0 2×(b) byte (ear) <-- 0 - (ear) byte (eam) <-- 0 - (eam) - - - - - * * * * * * * * * NEGW A 1 2 0 0 word (A) <-- 0 - (A) - - - - - * * * * - NEGW NEGW ear eam 2 2+ 3 5+(a) 2 0 0 2×(c) word (ear) <-- 0 - (ear) word (eam) <-- 0 - (eam) - - - - - * * * * * * * * * Note: See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) in the table. Table B.8-11 One Normalization Instruction (long word) Mnemonic # ~ RG B NRML A,R0 2 *1 1 0 *1 4 when all accumulators have a value of 0; otherwise, 6+(R0) 472 Operation long (A) <-- Shifts to the position where '1' is set for the first time. byte (RD) <-- Shift count at that time L H A H I S T N Z V C R M W - - - - - - * - - - APPENDIX B INSTRUCTIONS Table B.8-12 18 Shift Instructions (byte, word, long word) Mnemonic # ~ R G B Operation L H A H I S T N Z V C R M W RORC ROLC A A 2 2 2 2 0 0 0 0 byte (A) <-- With right rotation carry byte (A) <-- With left rotation carry - - - - - * * * * - * * - RORC RORC ROLC ROLC ear eam ear eam 2 2+ 2 2+ 3 5+(a) 3 5+(a) 2 0 2 0 0 2×(b) 0 2×(b) byte (ear) <-- With right rotation carry byte (eam) <-- With right rotation carry byte (ear) <-- With left rotation carry byte (eam) <-- With left rotation carry - - - - - * * * * * * * * - * * * * * * ASR LSR LSL A,R0 A,R0 A,R0 2 2 2 *1 *1 *1 1 1 1 0 0 0 byte (A) <-- Arithmetic right shift (A, 1 bit) byte (A) <-- Logical right barrel shift (A, R0) byte (A) <-- Logical left barrel shift (A, R0) - - - - * - * * * * * * - * * * - ASRW LSRW LSLW A A/SHRW A A/SHLW A 1 1 1 2 2 2 0 0 0 0 0 0 word (A) <-- Arithmetic right shift (A, 1 bit) word (A) <-- Logical right shift (A, 1 bit) word (A) <-- Logical left shift (A, 1 bit) - - - - * * - * R * * * * - * * * - ASRW LSRW LSLW A,R0 A,R0 A,R0 2 2 2 *1 *1 *1 1 1 1 0 0 0 word (A) <-- Arithmetic right barrel shift (A, R0) word (A) <-- Logical right barrel shift (A, R0) word (A) <-- Logical left barrel shift (A, R0) - - - - * * - * * * * * * - * * * - ASRL LSRL LSLL A,R0 A,R0 A,R0 2 2 2 *2 *2 *2 1 1 1 0 0 0 long (A) <-- Arithmetic right barrel shift (A, R0) long (A) <-- Logical right barrel shift (A, R0) long (A) <-- Logical left barrel shift (A, R0) - - - - * * - * * * * * * - * * * - *1 6 when R0 is 0; otherwise, 5 + (R0) *2 6 when R0 is 0; otherwise, 6 + (R0) Note: See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) in the table. 473 APPENDIX B INSTRUCTIONS Table B.8-13 31 Branch 1 Instructions Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN BP BV BNV BT BNT BLT BGE BLE BGT BLS BHI BRA rel rel rel rel rel rel rel rel rel rel rel rel rel rel rel rel rel 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Branch on (Z) = 1 Branch on (Z) = 0 Branch on (C) = 1 Branch on (C) = 0 Branch on (N) = 1 Branch on (N) = 0 Branch on (V) = 1 Branch on (V) = 0 Branch on (T) = 1 Branch on (T) = 0 Branch on (V) nor (N) = 1 Branch on (V) nor (N) = 0 Branch on ((V) xor (N)) or (Z) = 1 Branch on ((V) xor (N)) or (Z) = 0 Branch on (C) or (Z) = 1 Branch on (C) or (Z) = 0 Unconditional branch - - - - - - - - - - JMP JMP JMP JMP JMPP JMPP JMPP @A addr16 @ear @eam @ear *3 @eam *3 addr24 1 3 2 2+ 2 2+ 4 2 3 3 4+(a) 5 6+(a) 4 0 0 1 0 2 0 0 0 0 0 (c) 0 (d) 0 word (PC) <-- (A) word (PC) <-- addr16 word (PC) <-- (ear) word (PC) <-- (eam) word (PC) <-- (ear), (PCB) <-- (ear+2) word (PC) <-- (eam), (PCB) <-- (eam+2) word(PC) <-- ad24 0-15,(PCB) <-- ad24 16-23 - - - - - - - - - - CALL CALL CALL CALLV CALLP @ear *4 @eam *4 addr16 *5 #vct4 *5 @ear *6 2 2+ 3 1 2 6 7+(a) 6 7 10 1 0 0 0 2 (c) 2×(c) (c) 2×(c) 2×(c) - - - - - - - - - - CALLP @eam *6 2+ 11+(a) 0 *2 word (PC) <-- (ear) word (PC) <-- (eam) word (PC) <-- addr16 Vector call instruction word(PC) <-- (ear)0-15,(PCB) <-(ear)16-23 word(PC) <-- (eam)0-15,(PCB) <-(eam)16-23 - - - - - - - - - - CALLP addr24 *7 4 10 0 2×(c) word(PC) <-- addr0-15, (PCB) <-addr16-23 - - - - - - - - - - *1 4 when a branch is made; otherwise, 3 *2 3 x (c) + (b) *3 Read (word) of branch destination address *4 W: Save to stack (word) R: Read (word) of branch destination address *5 Save to stack (word) *6 W: Save to stack (long word), R: Read (long word) of branch destination address *7 Save to stack (long word) Note: See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) in the table. 474 APPENDIX B INSTRUCTIONS Table B.8-14 19 Branch 2 Instructions Mnemonic # ~ R G B Operation L H A H I S T N Z V C R M W CBNE CWBNE A,#imm8,rel A,#imm16,rel 3 4 *1 *1 0 0 0 0 Branch on byte (A) not equal to imm8 Branch on word (A) not equal to imm16 - - - - - * * * * * * * * - CBNE CBNE CWBNE CWBNE ear,#imm8,rel eam,#imm8,rel *9 ear,#imm16,rel eam,#imm16,rel*9 4 4+ 5 5+ *2 *3 *4 *3 1 0 1 0 0 (b) 0 (c) Branch on byte (ear) not equal to imm8 Branch on byte (eam) not equal to imm8 Branch on word (ear) not equal to imm16 Branch on word (eam) not equal to imm16 - - - - - * * * * * * * * * * * * * * * * - DBNZ ear,rel 3 *5 2 0 Branch on byte (ear) = (ear) - 1, (ear)not equal to 0 Branch on byte (eam) = (eam) - 1, (eam) not equal to 0 - - - - - * * - - - - - * Branch on word (ear) = (ear) - 1, (ear) not equal to 0 Branch on word (eam) = (eam) - 1, (eam) not equal to 0 - - - - - - - - - - - * * * - * * * * - - - * * * - * DBNZ eam,rel 3+ *6 2 2×(b) DWBNZ ear,rel 3 *5 2 0 DWBNZ eam,rel 3+ *6 2 2×(c) INT INT INTP INT9 RETI #vct8 addr16 addr24 2 3 4 1 1 20 16 17 20 *8 0 0 0 0 0 8×(c) 6×(c) 6×(c) 8×(c) *7 Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt - - R R R R * S S S S * * * * * * - LINK #imm8 2 6 0 (c) Saves the old frame pointer in the stack upon entering the function, then sets the new frame pointer and reserves the local pointer area. - - - - - - - - - - 1 5 0 (c) Recovers the old frame pointer from the stack upon exiting the function. - - - - - - - - - - 1 1 4 6 0 0 (c) (d) Return from subroutine Return from subroutine - - - - - - - - - - UNLINK RET RETP *10 *11 *1 5 when a branch is made; otherwise, 4 *2 13 when a branch is made; otherwise, 12 *3 7+(a) when a branch is made; otherwise, 6+(a) *4 8 when a branch is made; otherwise, 7 *5 7 when a branch is made; otherwise, 6 *6 8+(a) when a branch is made; otherwise, 7+(a) *7 3 x (b) + 2 x (c) when jumping to the next interruption request; 6 x (c) when returning from the current interruption *8 15 when jumping to the next interruption request; 17 when returning from the current interruption *9 Do not use RWj+ addressing mode with a CBNE or CWBNE instruction. *10 Return from stack (word) *11 Return from stack (long word) Note: See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) in the 475 APPENDIX B INSTRUCTIONS table. Table B.8-15 31 28 Other Control Instructions (byte, word, long word) Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W PUSHW PUSHW PUSHW PUSHW A AH PS rlst 1 1 1 2 4 4 4 *3 0 0 0 +& (c) (c) (c) *4 word (SP) <-- (SP) - 2 , ((SP)) <-- (A) word (SP) <-- (SP) - 2 , ((SP)) <-- (AH) word (SP) <-- (SP) - 2 , ((SP)) <-- (PS) (SP) <-- (SP) - 2n , ((SP)) <-- (rlst) - - - - - - - - - - POPW POPW POPW POPW A AH PS rlst 1 1 1 2 3 3 4 *2 0 0 0 +& (c) (c) (c) *4 word (A) <-- ((SP)) , (SP) <-- (SP) + 2 word (AH) <-- ((SP)) , (SP) <-- (SP) + 2 word (PS) <-- ((SP)) , (SP) <-- (SP) + 2 (rlst) <-- ((SP)) , (SP) <-- (SP) - * - * - * - * - * - * - * - * - - JCTX @A 1 14 0 6×(c) Context switch instruction - - * * * * * * * - AND OR CCR,#imm8 CCR,#imm8 2 2 3 3 0 0 0 0 byte (CCR) <-- (CCR) and imm8 byte(CCR) <-- (CCR) or imm8 - - * * * * * * * * * * * * * * - MOV MOV RP,#imm8 ILM,#imm8 2 2 2 2 0 0 0 0 byte (RP) <-- imm8 byte (ILM) <-- imm8 - - - - - - - - - - MOVEA MOVEA MOVEA MOVEA RWi,ear RWi,eam A,ear A,eam 2 2+ 2 2+ 3 2+(a) 1 1+(a) 1 1 0 0 0 0 0 0 word (RWi) <-- ear word (RWi) <-- eam word (A) <-- ear word (A) <-- eam - * * - - - - - - - - ADDSP ADDSP #imm8 #imm16 2 3 3 3 0 0 0 0 word (SP) <-- ext(imm8) word (SP) <-- imm16 - - - - - - - - - - MOV MOV A,brg1 brg2,A 2 2 *1 1 0 0 0 0 byte (A) <-- (brg1) byte (brg2) <-- (A) Z - * - - - - * * * * - - - 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 No operation Prefix code for AD space access Prefix code for DT space access Prefix code for PC space access Prefix code for SP space access Prefix code for flag no-change Prefix code for common register bank - - - - - - - - - - NOP ADB DTB PCB SPB NCC CMR *1 PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2 *2 7 + 3×(POP count) + 2×(POP last register number), 7 when RLST = 0 (no transfer register) *3 29 + 3×(PUSH count) - 3×(PUSH last register number), 8 when RLST = 0 (no transfer register) *4 (POP count)×(c) or (PUSH count)×(c) Note: See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) in the table. 476 APPENDIX B INSTRUCTIONS Table B.8-16 21 Bit Operand Instructions Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W MOVB MOVB MOVB A,dir:bp A,addr16:bp A,io:bp 3 4 3 5 5 4 0 0 0 (b) (b) (b) byte (A) <-- ( dir:bp )b byte (A) <-- ( addr16:bp )b byte (A) <-- ( io:bp )b Z Z Z * * * - - - * * * * * * - - - MOVB MOVB MOVB dir:bp,A addr16:bp,A io:bp,A 3 4 3 7 7 6 0 0 0 2×(b) 2×(b) 2×(b) bit ( dir:bp )b <-- (A) bit ( addr16:bp )b <-- (A) bit ( io:bp )b <-- (A) - - - - - * * * * * * - - * * * SETB SETB SETB dir:bp addr16:bp io:bp 3 4 3 7 7 7 0 0 0 2×(b) 2×(b) 2×(b) bit ( dir:bp )b <-- 1 bit ( addr16:bp )b <-- 1 bit ( io:bp )b <-- 1 - - - - - - - - - * * * CLRB CLRB CLRB dir:bp addr16:bp io:bp 3 4 3 7 7 7 0 0 0 2×(b) 2×(b) 2×(b) bit ( dir:bp )b <-- 0 bit ( addr16:bp )b <-- 0 bit ( io:bp )b <-- 0 - - - - - - - - - * * * BBC BBC BBC dir:bp,rel addr16:bp,rel io:bp,rel 4 5 4 *1 *1 *2 0 0 0 (b) (b) (b) Branch on (dir:bp) b = 0 Branch on (addr16:bp) b = 0 Branch on (io:bp) b = 0 - - - - - - * * * - - - BBS BBS BBS dir:bp,rel addr16:bp,rel io:bp,rel 4 5 4 *1 *1 *1 0 0 0 (b) (b) (b) Branch on (dir:bp) b = 1 Branch on (addr16:bp) b = 1 Branch on (io:bp) b = 1 - - - - - - * * * - - - SBBS addr16:bp,rel 5 *3 0 2×(b) Branch on (addr16:bp) b = 1, bit = 1 - - - - - - * - - * WBTS io:bp 3 *4 0 *5 Waits until (io:bp) b = 1 - - - - - - - - - - WBTC io:bp 3 *4 0 *5 Waits until (io:bp) b = 0 - - - - - - - - - - *1 8 when a branch is made; otherwise, 7 *2 7 when a branch is made; otherwise, 6 *3 10 when the condition is met; otherwise 9 *4 Undefined count *5 Until the condition is met( dir:bp )b Note: See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) in the table. Table B.8-17 Six Accumulator Operation Instructions (byte, word) Mnemonic SWAP SWAPW/XCHW A,T EXT EXTW ZEXT ZEXTW # 1 1 1 1 1 1 ~ 3 2 1 2 1 1 RG 0 0 0 0 0 0 B 0 0 0 0 0 0 Operation byte (A)0-7 <--> (A)8-15 word (AH) <--> (AL) Byte sign extension Word sign extension Byte zero extension Word zero extensionbyte L H X Z - A H * X z I S T N Z V C R M W - - - * * R R * * * * - - - 477 APPENDIX B INSTRUCTIONS Table B.8-18 Ten String Instructions Mnemonic # ~ RG B Operation L H A H I S T N Z V C R M W MOVS / MOVSI MOVSD 2 2 *2 *2 +& +& *3 *3 byte transfer @AH+ <-- @AL+, counter = RW0 byte transfer @AH- <-- @AL-, counter = RW0 - - - - - - - - - - SCEQ / SCEQI SCEQD 2 2 *1 *1 +& +& *4 *4 byte search @AH+ <-- AL, counter RW0 byte search @AH- <-- AL, counter RW0 - - - - - * * * * * * * * - FILS / FILSI 2 6m+6 +& *3 byte fill @AH+ <-- AL, counter RW0 - - - - - * * - - - MOVSW / MOVSWI 2 *2 +) *6 word transfer @AH+ <-- @AL+, counter = RW0 - - - - - - - - - - MOVSWD 2 *2 +) *6 word transfer @AH- <-- @AL-, counter = RW0 - - - - - - - - - - SCWEQ / SCWEQI 2 *1 +) *7 word search @AH+ - AL, counter = RW0 - - - - - * * * * - SCWEQD 2 *1 +) *7 word search @AH- - AL, counter = RW0 - - - - - * * * * - FILSW / FILSWI 2 6m+6 +) *6 word fill @AH+ <-- AL, counter = RW0 - - - - - * * - - - *1 5 when RW0 is 0, 4 + 7 × (RW0) when the counter expires, or 7n + 5 when a match occurs *2 5 when RW0 is 0; otherwise, 4 + 8 × (RW0) *3 (b) × (RW0) + (b) × (RW0) When the source and destination access different areas, calculate the (b) item individually. *4 (b) × n *5 2 × (R × W0) *6 (c) × (RW0) + (c) × (RW0) When the source and destination access different areas, calculate the (c) item individually. *7 (c) × n *8 2 × 0(RW0) Note: m: RW0 value (counter value), n: Loop count See Table B.5-1 "Execution Cycle Counts in Each Addressing Mode" and Table B.5-2 "Cycle Count Correction Values for Counting Execution Cycles" for information on (a) to (d) in the table. 478 APPENDIX B INSTRUCTIONS B.9 Instruction Map Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 "Basic Page Map" to Table B.9-21 "XCHW RWi, ea Instruction (first byte = 7FH)" summarize the F2MC-16LX instruction map. ■ Structure of Instruction Map Figure B.9-1 Structure of Instruction Map Basic page map : Byte 1 Bit operation instructions Character string operation instructions 2-byte instructions ea instructions x 9 : Byte 2 An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2 "Correspondence between Actual Instruction Code and Instruction Map" shows the correspondence between an actual instruction code and instruction map. 479 APPENDIX B INSTRUCTIONS Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map Some instructions do not contain byte 2. Length varies depending on the instruction. Instruction code Byte 1 Byte 2 Operand Operand ... [Basic page map] XY +Z [Extended page map] (*1) UV +W *1 The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions. Actually, there are multiple extended page maps for each type of instructions. An example of an instruction code is shown in Table B.9-1 "Example of an Instruction Code". Table B.9-1 Example of an Instruction Code Instruction 480 Byte 1 (from basic page map) Byte 2 (from extended page map) NOP 00 +0=00 - AND A, #8 30 +4=34 - MOV A, ADB 60 +F=6F 00 +0=00 @RW2+d8, #8rel 70 +0=70 F0 +2=F2 2-byte instruction Character string operation instruction Bit operation instruction Ri,ea ea instruction 9 ea instruction 8 ea instruction 7 ea instruction 6 ea instruction 5 ea instruction 4 ea instruction 3 ea instruction 2 ea instruction 1 APPENDIX B INSTRUCTIONS Table B.9-2 Basic Page Map 481 APPENDIX B INSTRUCTIONS Table B.9-3 Bit Operation Instruction Map (first byte = 6CH) 482 APPENDIX B INSTRUCTIONS Table B.9-4 Character String Operation Instruction Map (first byte = 6EH) 483 APPENDIX B INSTRUCTIONS 484 A A DIVU MULW MUL A Table B.9-5 2-byte Instruction Map (first byte = 6FH) Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited APPENDIX B INSTRUCTIONS Table B.9-6 ea Instruction 1 (first byte = 70H) 485 APPENDIX B INSTRUCTIONS Table B.9-7 ea Instruction 2 (first byte = 71H) 486 APPENDIX B INSTRUCTIONS Table B.9-8 ea Instruction 3 (first byte = 72H) 487 APPENDIX B INSTRUCTIONS Table B.9-9 ea Instruction 4 (first byte = 73H) 488 APPENDIX B INSTRUCTIONS Table B.9-10 ea Instruction 5 (first byte = 74H) 489 APPENDIX B INSTRUCTIONS Table B.9-11 ea Instruction 6 (first byte = 75H) 490 APPENDIX B INSTRUCTIONS Table B.9-12 ea Instruction 7 (first byte = 76H) 491 APPENDIX B INSTRUCTIONS Table B.9-13 ea Instruction 8 (first byte = 77H) 492 APPENDIX B INSTRUCTIONS Table B.9-14 ea Instruction 9 (first byte = 78H) 493 APPENDIX B INSTRUCTIONS Table B.9-15 MOVEA RWi, ea Instruction (first byte = 79H) 494 APPENDIX B INSTRUCTIONS Table B.9-16 MOV Ri, ea Instruction (first byte = 7AH) 495 APPENDIX B INSTRUCTIONS Table B.9-17 MOVW RWi, ea Instruction (first byte = 7BH) 496 APPENDIX B INSTRUCTIONS Table B.9-18 MOV ea, Ri Instruction (first byte = 7CH) 497 APPENDIX B INSTRUCTIONS Table B.9-19 MOVW ea, Rwi Instruction (first byte = 7DH) 498 APPENDIX B INSTRUCTIONS Table B.9-20 XCH Ri, ea Instruction (first byte = 7EH) 499 APPENDIX B INSTRUCTIONS Table B.9-21 XCHW RWi, ea Instruction (first byte = 7FH) 500 INDEX INDEX The index follows on the next page. This is listed in alphabetic order. 501 INDEX Index Numerics 16-bit free run timer .............................................. 185 16-bit free run timer (x 1)......................................180 16-bit free run timer register ................................. 185 16-bit free run timer, block diagram of.................. 185 16-bit free run timer, operation of .........................201 16-bit free-running timer, timing for ...................... 202 16-bit I/O timer selection, register of entire .......... 181 16-bit input capture, operation of .........................206 16-bit input/output timer register .......................... 183 16-bit output compare, operation of ..................... 203 16-bit output compare, timing for .........................204 2M-bit flash memory, feature of............................ 396 2M-bit flash memory, sector configuration of ....... 397 8 bits x 2 ch, 16 bits x 1 ch operation ...................256 8/16-bit PPG interrupt .......................................... 229 8/16-bit PPG operating mode............................... 223 8/16-bit PPG output operation.............................. 224 8/16-bit PPG, block diagram of ............................ 211 8/16-bit PPG, controlling pulse pin output of........ 227 8/16-bit PPG, initial value of each hardware component in ............................................. 230 8/16-bit PPG, operation of.................................... 222 8/16-bit PPG, overview of .................................... 210 8/16-bit PPG, register of....................................... 213 8/16-bit PPG, selecting count clock for ................ 226 8/16-bit PPG, timing of writing reload register in ...................................................228 8/16-bit up/down counter/timer, block diagram of .................................................. 234 8/16-bit up/down counter/timer, count mode selection for................................................ 247 8/16-bit up/down counter/timer, function of .......... 232 8/16-bit up/down counter/timer, register of........... 236 8/16-bit up/down counter/timer, reload function and compare function ...................250 8/16-bit up/down counter/timer, simultaneous activation of reload/compare function ........ 252 A A/D converter, block diagram of........................... 275 A/D converter, note on using................................ 293 A/D converter, overview of ................................... 274 A/D converter, register of ..................................... 276 access mode ........................................................ 126 502 access to many-byte length data ........................... 28 accessing low-power consumption mode control register (LPMCR)......................................... 96 accumulator (A)...................................................... 32 acknowledgement ................................................ 364 activating EI2OS in continuous mode, example of ................................................. 289 activating EI2OS in single mode, example of....... 287 activating EI2OS in stop mode, example of ......... 291 ADCR2 and ADCR1............................................. 282 ADCS1 and ADCS2 ............................................. 277 address field, effective ................................. 446, 461 address match detection function, block diagram of.................................................. 382 address match detection function, note on .......... 386 address match detection function, operation of ... 386 address match detection function, register of ...... 383 address match detection function, system configuration of .......................................... 387 address register (IADR) ....................................... 362 addressing ................................................... 364, 445 addressing in write data cycle.............................. 411 addressing using bank method .............................. 26 addressing using linear method ............................. 25 addressing, direct................................................. 447 addressing, indirect.............................................. 452 allocating many-byte length data in memory space ............................................. 28 analog input enable register (ADER) ................... 160 application of UART (example of system configuration in mode 1) ............................ 329 arbitration ............................................................. 364 ARSR ................................................................... 134 asynchronous mode, receiving operation of ........ 322 asynchronous mode, sending operation of .......... 322 asynchronous mode, transfer data format of ....... 322 automatic ready function selection register (ARSR) ...................................................... 134 B bank method, addressing using ............................. 26 bank register .......................................................... 40 bank select prefix ................................................... 43 basic configuration of MB90F574/A serial programming connection.................. 424 INDEX baud rate generator, dedicated............................ 318 block diagram of MB90570 series............................ 6 buffer address pointer (BAP) ................................. 76 bus control register (IBCR) .................................. 356 bus control signal selection register (ECSR) ....... 137 bus error............................................................... 365 bus mode ............................................................. 126 bus status register (IBSR).................................... 353 C calculating execution cycle count......................... 458 CCRH0................................................................. 241 CCRH1................................................................. 243 CCRL0/1 .............................................................. 245 chip erase or sector erase operation, at .............. 404 chip select control register (CSCR0 to CSCR6) .. 371 chip select function, block diagram of .................. 370 chip select function, decode address space of .... 373 chip select function, operation of ......................... 372 chip select function, overview of .......................... 370 clearing watchdog counter ................................... 172 CLK synchronous mode being used, setting for control register when ................................. 324 CLK synchronous mode, starting communication in....................................... 324 CLK synchronous mode, terminating communication in....................................... 324 CLK synchronous mode, transfer data format of . 323 clock control register (ICCR) ................................ 359 clock generator ...................................................... 84 clock generator, note for ........................................ 84 clock mode, external shift .................................... 341 clock mode, internal shift ..................................... 341 clock monitor, block diagram of ........................... 378 clock output enable register (CLKR) .................... 379 clock selection register (CKSCR)........................... 97 clock selection, status transition for ..................... 100 clock supply map ................................................... 85 command sequence table.................................... 401 common register bank prefix (CMR) ...................... 44 communication flow chart of UART...................... 329 communication prescaler control register (CDCR) ...................................................... 316 compare detection flag......................................... 255 competition among SCC, MSS, and INT bits ....... 358 condition code register (CCR)................................ 36 condition of peripheral circuits connected externally when DTP being used ............... 267 continuous mode.................................................. 284 control register, timebase timer (TBTC) ...............164 control register, watch timer (WTC)......................176 control register, watchdog timer (WDTC) .............170 control signal, external memory access ...............140 control status register ...........................................277 control status register, output compare ................193 controlling pulse pin output of 8/16-bit PPG .........227 conversion data protection function......................294 conversion using EI2OS .......................................286 count clear/gate function ......................................254 count direction flag, count direction change flag ..255 count mode selection for 8/16-bit up/down counter/timer ..............................................247 counter control register high ch.0 (CCRH0) .........241 counter control register high ch.1 (CCRH1) .........243 counter control register low ch.0/1 (CCRL0/1) .....245 counter status register 0/1 (CSR0/1) ....................239 CSR0/1 .................................................................239 cycle count, execution ..........................................458 D D/A converter register...........................................298 D/A converter register (DACR0 and DACR1).......300 D/A converter, block diagram of ...........................299 D/A converter, operation of...................................302 D/A data register (DADR0 and DADR1)...............300 data counter (DCT).................................................74 data polling flag state, transition of .......................404 data register..........................................................282 data register (IDAR)..............................................363 data write, note on ................................................411 decode address space of chip select function......373 dedicated baud rate generator .............................318 dedicated register ...................................................30 delayed interrupt requesting module, block diagram of ..................................................270 delayed interrupt requesting module, operation of ................................................271 delayed interrupt requesting module, precaution for using....................................271 delayed interrupt requesting module, register of ..270 direct addressing ..................................................447 direct page register (DPR)......................................39 DIV A, Ri and DIVW A, RWi instruction, note on using..........................................48, 49 DTP and external interrupt ...................................258 DTP operation ......................................................264 DTP request and external interrupt request, switching between ......................................265 503 INDEX DTP/external interrupt, block diagram of.............. 258 DTP/external interrupt, operation of ..................... 264 DTP/external interrupt, operation procedure of .... 267 DTP/external interrupt, register of ........................ 259 DTP/interrupt enable register (ENIR) ...................260 DTP/interrupt source register (EIRR) ...................261 E E2PROM memory map ........................................ 387 ECSR ................................................................... 137 effective address field .................................. 446, 461 EI2OS , conversion using ..................................... 286 EI2OS in continuous mode, example of activating .................................................... 289 EI2OS in single mode, example of activating ....... 287 EI2OS in stop mode, example of activating.......... 291 EI2OS interrupt processing, overview of ................ 67 EI2OS status register (ISCS).................................. 75 EI2OS, execution time of ........................................ 79 EI2OS, operation of ................................................ 68 EI2OS, procedure for.............................................. 77 EI2OS, procedure for using .................................... 78 EI2OS, structure of ................................................. 69 entire 16-bit I/O timer, block diagram of ............... 182 erasing all chips ...................................................413 erasing data (erasing all chips) ............................ 413 erasing data (erasing sector) ............................... 414 erasing sector....................................................... 414 exception occurrence due to execution of undefined instruction .................................... 82 execution cycle count ........................................... 458 execution cycle count, calculating ........................ 458 explanation of operation....................................... 284 extended intelligent I/O service (EI2OS)......... 67, 330 extended intelligent I/O service descriptor (ISD) .... 73 extended intelligent I/O service, execution time of .......................................... 79 extended intelligent I/O service, operation of ......... 68 extended intelligent I/O service, procedure for....... 77 extended intelligent I/O service, procedure for using ...................................... 78 extended intelligent I/O service, structure of .......... 69 extended serial I/O interface, block diagram of .... 333 extended serial I/O interface, interrupt function of .................................................. 347 extended serial I/O interface, operation of ........... 340 extended serial I/O interface, overview of ............332 extended serial I/O interface, register of .............. 334 external address output control register (HACR) . 136 504 external bus pin control circuit ............................. 132 external clock ....................................................... 320 external memory access ...................................... 132 external memory access control signal................ 140 external memory access register, configuration of .......................................... 133 external memory access, block diagram of.......... 133 external shift clock mode ..................................... 341 F flag change suppression prefix (NCC) ................... 44 flag of UART ........................................................ 325 flag, compare detection........................................ 255 flag, count direction/count direction change......... 255 flash memory control status register (FMCS) ...... 398 flash memory program, example of ..................... 418 flash memory register .......................................... 396 flash memory write procedure.............................. 411 flash memory write/erase method........................ 396 flash memory write/erase, detailed explanation of ............................................ 409 flash memory, writing data to ............................... 411 FMCS................................................................... 398 FPT-120P-M05, package dimension of ................... 8 FPT-120P-M13, package dimension of ................... 9 FPT-120P-M21, package dimension of ................. 10 function of 8/16-bit up/down counter/timer........... 232 G general-purpose register........................................ 41 generator, clock ..................................................... 84 H HACR................................................................... 136 handling device, note on ........................................ 20 hardware interrupt mechanism .............................. 57 hardware interrupt operation.................................. 60 hardware interrupt operation flowchart .................. 63 hardware interrupt, note on.................................... 59 hardware interrupt, overview of.............................. 57 hardware interrupt, processing time for ................. 61 hardware sequence flag....................................... 402 hardware standby mode, releasing...................... 114 hardware standby mode, transition to.................. 114 hold function......................................................... 145 I I/O circuit type ........................................................ 17 INDEX I/O map ................................................................ 436 I/O port register, configuration of ......................... 150 I/O port, overview of............................................. 148 I/O register address pointer (IOA).......................... 74 I/O service descriptor, extended intelligent (ISD)... 73 I2C Interface, block diagram of ............................ 351 I2C Interface, feature of........................................ 350 I2C interface, operation flow of............................. 366 I2C Interface, register of....................................... 352 IADR .................................................................... 362 IBCR .................................................................... 356 IBSR..................................................................... 353 ICCR .................................................................... 359 ICR......................................................................... 70 IDAR .................................................................... 363 indirect addressing............................................... 452 initial status .......................................................... 387 initial value of each hardware component in 8/16-bit PPG .............................................. 230 input capture ........................................................ 196 input capture (x 2) ................................................ 180 input capture control status register (ICS01) ....... 199 input capture input timing..................................... 207 input capture register (IPCP0, IPCP1) ................. 198 input capture register, entire ................................ 196 input capture, block diagram of entire.................. 197 input resistance register (PDR), note on.............. 158 input resistor register (RDR) ................................ 158 input resistor register, block diagram of ............... 158 instruction map, structure of................................. 479 instruction presentation item and symbol, description of ............................................. 462 instruction type..................................................... 444 INT9 interrupt ....................................................... 388 intelligent I/O service (EI2OS), extended ............. 330 intermittent CPU operation function ....................... 91 internal shift clock mode ...................................... 341 internal timer ........................................................ 319 interrupt control register (ICR) ............................... 70 interrupt function of extended serial I/O interface ............................................... 347 interrupt level mask register (ILM) ......................... 37 interrupt request during writing in internal resource area............................................... 58 interrupt source ...................................................... 53 interrupt source of UART ..................................... 325 interrupt suppress instruction................................. 58 interrupt vector ....................................................... 55 interrupt, overview of.............................................. 52 interrupt, software...................................................65 interrupt/hold suppression instruction and prefix code....................................................46 interval interrupt function of timebase timer..........166 interval interrupt function of watch timer...............178 ISCS .......................................................................75 L linear method, addressing using.............................25 low-power consumption control circuit, block diagram of ....................................................93 low-power consumption control circuit, operating mode of ........................................90 low-power consumption control circuit, register in..94 low-power consumption mode..............................104 low-power consumption mode control register (LPMCR) ......................................................95 low-power consumption mode control register (LPMCR), accessing ....................................96 low-power consumption mode, operating state in 105 low-power consumption mode, status transition diagram of ..................................................119 low-power consumption mode, status transition in .................................................115 M machine clock, switching of ....................................91 main clock, setting of oscillation stabilization time for .........................................................91 many-byte length data in memory space, allocating ......................................................28 many-byte length data, access to...........................28 MB90570 series, block diagram ...............................6 MB90570 series, feature of ......................................2 MB90570 series, pin assignment .............................7 MB90F574/A serial write connection, basic configuration of .................................424 memory access mode ..........................................126 memory space ........................................................24 memory space for mode.......................................129 minimum connection to flash microcomputer programmer (power supplied from the programmer), example of ...........................433 minimum connection to flash microcomputer programmer (User Power Supply Used), example of..................................................431 mode data.............................................................128 mode pin...............................................................127 multiple interrupts ...................................................58 505 INDEX O operating mode .................................................... 126 operating mode of low-power consumption control circuit ................................................ 90 operating state in low-power consumption mode .......................................................... 105 operation after reset is released............................. 88 operation flow of I2C interface .............................. 366 operation of chip select function........................... 372 operation of delayed interrupting requesting module ....................................................... 271 operation procedure of DTP/external interrupt ..... 267 operation, explanation of ......................................284 operation, hardware interrupt ................................. 60 oscillation clock frequency and serial clock input frequency .......................................... 426 oscillation stabilization time for main clock, setting of ...................................................... 91 output compare .................................................... 190 output compare (x 4) ............................................180 output compare control status register (OCS0 to OCS3) ........................................ 193 output compare register ....................................... 190 output compare register (OCCP0 to OCCP3) ......192 output compare, block diagram of ........................ 191 output control register, external address .............. 136 output pin register (ODR) ..................................... 157 output pin register (ODR), block diagram of......... 157 output pin register (ODR), note on ....................... 157 overview of I/O port .............................................. 148 overview of the interrupt......................................... 52 P package dimension of FPT-120P-M05..................... 8 package dimension of FPT-120P-M13..................... 9 package dimension of FPT-120P-M21................... 10 peripheral circuits connected externally when DTP being used, condition of ..................... 267 pin assignment of MB90570 series .......................... 7 pin description ........................................................ 11 PLL clock multiplication function ............................ 92 port data register (PDR) ....................................... 152 port direction register (DDR) ................................ 155 port output being set by PDR register, operation of port used as resource when... 149 port used as resource when port output being set by PDR register, operation of ............... 149 PPG0 and PPG1 output pin control register (PPGOE) .................................................... 219 PPG0 operating mode control register (PPGC0) . 214 506 PPG1 operating mode control register (PPGC1) . 216 precaution for using delayed interrupting requesting module ..................................... 271 Precautions .......................................................... 330 prefix code and interrupt/hold suppression instruction .................................................... 46 prefix code being consecutive................................ 47 preventing watchdog timer reset.......................... 172 processing time for hardware interrupt .................. 61 processor status (PS) ............................................ 36 product lineup .......................................................... 5 program address detection control status register (PACSR) ....................................... 385 program address detection register (PADR0 and PADR1) ................................ 384 program counter (PC) ............................................ 38 program error occurs ........................................... 388 program patch processing, example and flow of . 389 pseudo watch mode, releasing ............................ 109 pseudo watch mode, transition to ........................ 108 putting flash memory into read/reset state........... 410 R R/W wait state, serial data register ...................... 342 RCR0/1 ................................................................ 238 read/reset state, putting flash memory into.......... 410 ready function ...................................................... 143 receiving operation of asynchronous (start-stop synchronous) mode ................................... 322 recommended setting, example of....................... 130 register ................................................................. 276 register bank .......................................................... 42 register bank pointer (RP)...................................... 37 register in low-power consumption control circuit .. 94 register of 8/16-bit up/down counter/timer ........... 236 register of address match detection function ....... 383 register of delayed interrupt requesting module... 270 register of entire 16-bit I/O timer section.............. 181 register of I2C interface ........................................ 352 register of ROM mirror function selection module (ROMM) ........................................ 393 register saved on stack when interrupt occurs....... 59 register, dedicated ................................................. 30 relationship between reload value and pulse width................................................. 224 releasing hardware standby mode....................... 114 releasing pseudo watch mode ............................. 109 releasing sleep mode........................................... 107 releasing stop mode............................................. 112 releasing watch mode .......................................... 111 INDEX reload function and compare function of 8/16-bit up/down counter/timer .................. 250 reload register (PRLL and PRLH) ........................ 221 reload value and pulse width, relationship between ..................................................... 224 reload/compare register 0/1 (RCR0/1)................. 238 request level setting register (ELVR) ................... 262 reset being released .............................................. 88 reset factor ............................................................. 86 reset released, operation after ............................... 88 reset sequence .................................................... 388 reset source ........................................................... 86 restarting sector erase operation ......................... 417 return from standby state ..................................... 267 ROM mirror function selection module (ROMM), register of ................................... 393 ROM mirror function selection module, block diagram of.................................................. 392 S sample use procedure, flow chart of ...................... 64 SCC, MSS, and INT bit, competiton among ........ 358 sector configuration of 2M-bit flash memory ........ 397 sector erase operation, at .................................... 408 sector erase procedure ........................................ 414 sector erase temporarily, stopping....................... 416 sector erase temporary stop, at ................... 404, 406 sector erase timer flag state, transition of ............ 408 sector specification method ................................. 414 selecting count clock for 8/16-bit PPG ................. 226 selection register, automatic ready function (ARSR) ...................................................... 134 selection register, bus control signal (ECSR) ...... 137 sending operation of asynchronous (start-stop synchronous) mode .................. 322 serial control register (SCR)................................. 309 serial data I/O shift timing .................................... 346 serial data register R/W wait state ....................... 342 serial input data register (SIDR)/serial output data register (SODR), configuration of ...... 312 serial mode control status register (SMCS) ......... 335 serial mode register (SMR) .................................. 307 serial programming connection (power supplied from the programmer), example of ............ 429 serial programming connection (user power supply used), example of........................... 427 serial shift data register (SDR)............................. 339 serial status register (SSR) .................................. 313 setting of oscillation stabilization time for main clock.................................................... 91 settings for control register when CLK synchronous mode being used ..................324 shift operation start/stop timing.............................344 SIDR/SODR..........................................................312 simultaneous activation of reload/compare function of 8/16-bit up/down counter/timer ..............................................252 single mode ..........................................................284 sleep mode, releasing ..........................................107 sleep mode, transition to ......................................107 software interrupt....................................................65 software interrupt mechanism ................................65 software interrupt operation....................................65 software interrupt, note on......................................66 software interrupt, overview of................................65 specification of several sectors, note on...............414 stack pointer, user (USP) and system (SSP) .........34 standby state, return from.....................................267 start condition .......................................................364 start/stop timing, shift operation............................344 starting communication in CLK synchronous mode .....................................324 starting watchdog timer ........................................172 status transition diagram of low-power consumption mode .....................................119 status transition for clock selection.......................100 status transition in low-power consumption mode .....................................115 stop condition .......................................................364 stop mode.............................................................285 stop mode, releasing ............................................112 stop mode, transition to ........................................112 STOP state ...........................................................342 stopped state ........................................................342 stopping sector erase temporarily ........................416 stopping watchdog................................................172 structure of instruction map ..................................479 switching between DTP request and external interrupt request ...........................265 switching of machine clock .....................................91 system configuration in mode 1, example of ........329 system configuration of address match detection function .......................................387 T TCCS....................................................................187 TCDT ....................................................................186 terminating communication in CLK synchronous mode .....................................324 Timebase..............................................................166 507 INDEX timebase counter.................................................. 166 timebase timer control register (TBTC) ................ 164 timebase timer register, configuration of .............. 162 timebase timer, block diagram of .........................163 timebase timer, interval interrupt function of ........ 166 timer counter control status register (TCCS)........ 187 timer counter data register (TCDT) ...................... 186 timer register, 16-bit input/output .........................183 timing for 16-bit free-running timer ....................... 202 timing for 16-bit output compare .......................... 204 timing limit excess flag state, transition of ............407 timing of writing reload register in 8/16-bit PPG ... 228 timing to set interrupt and flag of UART ............... 326 toggle bit flag state, transition of .......................... 406 transfer data format of asynchronous (start-stop synchronous) mode ................................... 322 transfer data format of CLK synchronous mode... 323 transfer state ........................................................ 342 transfer time one operation .................................... 79 transition of data polling flag state........................ 404 transition of sector erase timer flag state ............. 408 transition of timing limit excess flag state............. 407 transition of toggle bit flag state ........................... 406 transition to hardware standby mode ...................114 transition to pseudo watch mode .........................108 transition to sleep mode ....................................... 107 transition to stop mode......................................... 112 transition to watch mode ......................................110 type of instruction ................................................. 444 U UART operation mode ......................................... 321 UART, application of ............................................329 UART, block diagram of ....................................... 305 UART, communication flow chart of ..................... 329 508 UART, feature of .................................................. 304 UART, flag of ....................................................... 325 UART, interrupt source of .................................... 325 UART, precaution for using.................................. 330 UART, register of ................................................. 306 UART, timing to set interrupt and flag of.............. 326 UDCR, writing data to .......................................... 254 UDCR0/1.............................................................. 237 undefined instruction, exception occurance due to execution of ...................................... 82 up/down count register ch.0/1 (UDCR0/1) ........... 237 user stack pointer (USP) and system stack pointer (SSP) ............................................... 34 W watch counter....................................................... 178 watch mode, releasing ......................................... 111 watch mode, transition to ..................................... 110 watch timer block diagram, block diagram of....... 175 watch timer control register (WTC) ...................... 176 watch timer control register, configuration of ....... 174 watch timer, interval interrupt function of ............. 178 watchdog timer control register (WDTC).............. 170 watchdog timer control register, configuration of .......................................... 168 watchdog timer counter, clearing ......................... 172 watchdog timer reset, preventing......................... 172 watchdog timer, block diagram of ........................ 169 watchdog timer, starting....................................... 172 watchdog timer, stopping ..................................... 172 write operation, at ................................................ 404 write/chip or sector erase operation, at................ 406 write/chip or sector erase, at................................ 407 writing data to flash memory ................................ 411 writing data to UDCR ........................................... 254 CM44-10102-7E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL F2MC-16LX 16-BIT MICROCONTROLLER MB90570 series HARDWARE MANUAL April 2001 the seventh edition Published FUJITSU LIMITED Edited Technical Information Dept. Electronic Devices FUJITSU SEMICONDUCTOR F2MC-16LX 16-BIT MICROCONTROLLER MB90570 series HARDWARE MANUAL