A3903 Low Voltage DC Motor Driver Features and Benefits Description ▪ ▪ ▪ ▪ The A3903 is a low voltage bidirectional DC motor driver with a typical input voltage range of 3 to 5.5 V and output currents up to 500 mA. The unique output full-bridge incorporates sourceside linear operation to allow a constant voltage across the motor coil. This regulated output minimizes motor voltage change due to I × RDS(on) variation and battery voltage tolerance. ▪ ▪ ▪ ▪ Constant voltage operation (adjustable) 500 mA output peak rating Low power standby mode Small 2 mm × 2 mm, 0.55 mm nominal height DFN package Typical input voltage range of 3 to 5.5 V Adjustable constant voltage or PWM operation Less than 500 nA standby mode current –40 to 85 operating temperature range Logic input pins are provided to control the motor direction of rotation, brake, and standby (< 500 nA supply current) modes and to allow optional PWM of the sink drivers. Internal protection circuitry includes thermal shutdown, undervoltage lockout, and crossover current (shoot-through) protection. The A3903 is supplied in a 2 mm x 2 mm, 0.55 mm nominal height, 8-lead DFN package, with exposed thermal pad (package suffix EE). This small footprint package is lead (Pb) free, with 100% matte tin leadframe plating. Package: 8 Contact DFN (suffix EE) Applications include: ▪ ▪ ▪ ▪ ▪ Robotic actuators and pumps Portable printers/scanners Camera lens/shutter control Battery powered toys and games Low noise test instrumentation systems Approximate Scale 1:1 Typical Application +VBAT VDD IN1 IN2 CPU VREF OUTA A3903 OUTB VSET GND 3903-DS, Rev. 2 M A3903 Low Voltage DC Motor Driver Selection Guide Part Number A3903EEETR-T Packing Tape and reel, 3000 pieces/reel Absolute Maximum Ratings Parameter Symbol Conditions Min. Typ. Max. Units Supply Voltage VDD – – 6 V Logic Input Voltage Range VIN –0.3 – 6 V Output Current IOUT 500 mA Junction Temperature TJ – – 150 °C Storage Temperature Range Tstg –40 – 150 °C Operating Temperature Range TA –40 – 85 °C Range E Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A3903 Low Voltage DC Motor Driver Functional Block Diagram VDD VREF VBG R1 3 to 5.5V 10 MF CHARGE PUMP VCP VSET VSET R2 3R OUTA 3R OUTB OUTA R R OUTB Sink Drive Sink Drive IN1 GND Control Logic IN2 Terminal Diagram OUTB 1 8 IN2 GND 2 7 IN1 VDD 3 6 VREF OUTA 4 5 VSET (Top View) Number 1 2 3 4 5 6 7 8 Name OUTB GND VDD OUTA VSET VREF IN1 IN2 Description Motor terminal Ground Input supply Motor terminal Select source-side output voltage Bandgap reference Control logic input Control logic input Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A3903 Low Voltage DC Motor Driver ELECTRICAL CHARACTERISTICS at TA =25°C, and VDD = 3 to 5.5 V, unless otherwise noted Characteristics Symbol Test Conditions Min. Supply Current IDD IDDSTB UVLO Enable Threshold VDDUVLO UVLO Hysteresis VUVHYS Typ. Max. Units – 0.5 2 mA Standby mode – – 500 nA VDD rising – – 2.6 V – 120 – mV Thermal Shutdown Temperature TJTSD Temperature increasing. – 165 – °C Thermal Shutdown Hysteresis TJHYS Recovery = TJTSD – TJHYS – 15 – °C Logic Input Low Level VIL – – VDDx0.3 V Logic Input High Level VIH VDD x 0.7 – – V Input Hysteresis Logic Input Current – VDD x 7% – mV VIN = 0 to 5 V –1 0 1 μA VHYS IIN Output Driver Sink Driver Output Resistance RDS Source Driver On Resistance RDS(on) Bandgap Reference VOUT Accuracy (VOUTA –VOUTB) VDD = 5 V, IOUT = 500 mA – 0.6 – Ω VDD = 3 V, IOUT = 500 mA – 0.8 – Ω VDD = 5 V, IOUT = 500 mA – 0.6 – Ω VDD = 3 V, IOUT = 500 mA – 0.65 – Ω VBG VOUT 1.235 1.285 1.335 V VSET = 1.2 V 4.608 4.8 4.992 V VSET = 825 mV 3.135 3.3 3.465 V VSET = 500 mV 1.84 2 2.16 V THERMAL CHARACTERISTICS Characteristics Package Thermal Resistance* *Additional Symbol RθJA Test Conditions Measured on 4-layer board based on JEDEC standard Rating Unit 49 °C/W thermal information is available on the Allegro Web site. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A3903 Low Voltage DC Motor Driver Functional Description Voltage Regulation The A3903 regulates the voltage Dropout Mode The source and sink drivers have a across the motor coil. The voltage across the OUTA and OUTB terminal is sensed and compared to an internal threshold voltage. The high-side switch will be driven in linear mode to keep the applied voltage maintained at the calculated level, as follows: total RDS(on) of approximately 1.2 Ω total. When the motor supply voltage, VDD, drops too low compared to the regulated value, the IC enters dropout mode. In this case, the voltage across the motor coil will be: VMOTOR = VDD – ILOAD (RDS(sink) + RDS(src)) VOUT = 4 × VREF (R2 / [R1+R2]) , where VREF (VBG) is 1.285 V typical. Brake Mode When both inputs are high, the A3903 Then, for forward mode: goes into high-side brake mode (turns on both source drivers). There is no protection during braking, so care must be taken to ensure that the peak current does not exceed the absolute maximum current, IOUT. VOUT = VOUTA – VOUTB , and for reverse mode: VOUT = VOUTB – VOUTA . The alternative method is to provide a tightly regulated voltage to the motor supply pin and run the source and sink drivers as switches. The voltage drop across these switches will vary linearly with temperature and current, therefore the voltage across the motor coil also will vary. The A3903 will eliminate these sources of error for a system where controlling the motor voltage is the optimum means of control. Thermal Shutdown The A3903 will disable the out- puts if the junction temperature, TJ , reaches 165°C. There is 15°C of hysteresis, so when the junction temperature drops below 150°C, the device will begin to operate normally. Standby Mode To minimize battery drain, standby mode will turn off all of the circuitry and draw typically less than 100 nA from the VDD line. There will be a very short delay, approximately 2 μs, before enabling the output drivers after release of standby mode. Power Dissipation. Power can be approximated based on the below three components: PD(src) = ILOAD (VDD –VREG) , PD(sink) = ILOAD × RDS(sink) , and Pbias = VDD × IDD. Control Logic Table Settings OUTA OUTB Resulting Mode IN1 IN2 0 0 Off Off Standby 0 1 Low VREG Reverse 1 0 VREG Low Forward 1 1 High High Brake Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A3903 Low Voltage DC Motor Driver Application Information Layout The printed circuit board should use a heavy groundplane for optimum thermal performance. The A3903 must be soldered directly onto the board. On the underside of the A3903 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. Thermal vias should not have any thermal relief and should be con- U1 bounce and offset issues, it is important to have a low impedance, single-point ground, known as a star ground, located very close to the device. By making the connection between the exposed thermal pad and the groundplane directly under the A3903, that area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce IN2 CVDD IN1 VDD OUTA Grounding In order to minimize the effects of ground GND OUTB GND nected to internal layers, if available, to maximize the dissipation area. R2 R1 GND IN2 OUTB CVDD 10 MF GND A3903 VDD PAD OUTA IN1 VREF R1 VSET R2 A3903 Evaluation Board Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A3903 Low Voltage DC Motor Driver during PWM operation and ensure that the supply voltage remains stable at the input terminal. Bulk capacitance is often located at a non-ideal distance from the device. If the recommended capacitance of 10 μF cannot be located very close to the supply terminal on the A3903, it is recommended that a 0.1 μF capacitor be placed as close to the VDD terminal as possible to provide a path for transient currents. PWM Operation In some applications current control may be desired. Pulse width modulating the inputs will allow the output current to be regulated. When external PWM control is used, the VREF pin should be connected directly to the VSET pin. This effectively disables voltage control on the source driver, and allows maximum current to flow through the driver. Current is then controlled using enable chopping, described below. Enable Chopping By PWMing the logic inputs between enable and brake modes, the current in the motor winding can be controlled. It is accomplished by holding one input high while PWMing the other input. During the on-cycle, current flows in the bridge consistent with the direction programmed on the input pins. During the off-cycle, the A3903 enters brake mode. Enable chopping is illustrated in figure 1. Current in the motor winding is controlled by changing the duty cycle on the PWM input. As shown in figure 2, the average current is still positive but, because the duty cycle is less, the average current is much lower. IOUT IOUT C3 VIN1 C3 VIN1 VIN2 C1 C2 VIN2 C1 C2 t Symbol C1 C2 C3 t Parameter VIN1 VIN2 IOUT time t Units/Division 2V 2V 100 mA 20 μs Figure 1. Enable chopping. Forward direction, output duty cycle 90%. Symbol C1 C2 C3 t Parameter VIN1 VIN2 IOUT time Units/Division 2V 2V 100 mA 20 μs Figure 2. Enable chopping. Forward direction, output duty cycle 20%. Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A3903 Low Voltage DC Motor Driver Package EE, 8-contact DFN 0.30 0.50 8 2.00 ±0.15 8 0.83 2.00 ±0.15 0.90 2.13 A 1 9X 2 D SEATING PLANE 0.08 C +0.05 0.55 –0.04 0.25 ±0.05 0.50 1 C 1.60 PCB Layout Reference View All dimensions nominal, not for tooling use (reference JEDEC MO-229UCCD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown 2 0.325 ±0.050 0.90 B 8 1 C 1.60 A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 SON50P200X200X100-9M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals Copyright ©2007-2013, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8