FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
Version 1.1
F2MC-16LX
16-BIT MICROCONTROLLER
MB90820 Series
HARDWARE MANUAL
PREFACE
■ Objectives and intended reader
Thank you for purchasing Fujitsu semiconductor products.
The MB90820 series was developed as a group of general-purpose models in the F²MC-16LX
series, which is a family of original 16-bit single-chip microcontrollers that can be used for
application specific ICs (ASICs).
This manual is intended for engineers who design products using the MB90820 series of
microcontrollers. The manual describes the functions and operation of the MB90820 series.
■ Trademarks
F²MC is a registered trademark of Fujitsu Limited and stands for FUJITSU Flexible
Microcontroller.
■ Organization of this manual
This manual consists of the following 22 chapters and 3 appendices:
Chapter 1 Overview
This chapter describes the features and basic specifications of the MB90820 series.
Chapter 2 CPU
This chapter describes the memory space of the MB90820 series.
Chapter 3 Reset
This chapter describes the reset function of the MB90820 series.
Chapter 4 Clock
This chapter describes the clocks of the MB90820 series.
Chapter 5 Low Power Consumption Mode
This chapter describes the energy-saving mode of the MB90820 series.
Chapter 6 Interrupt
This chapter describes the interrupts and extended intelligent I/O services of the MB90820
series.
Chapter 7 Mode Setting
This chapter describes the operating modes and memory access mode of the MB90820
series.
Chapter 8 I/O Port
This chapter describes the functions and operation of the MB90820 series I/O ports.
Chapter 9 Timebase Timer
This chapter describes the functions and operation of the MB90820 series timebase timer.
Chapter 10 Watchdog Timer
This chapter describes the functions and operation of the MB90820 series watchdog timer.
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Chapter 11 16-bit Reload Timer
This chapter describes the functions and operation of the MB90820 series 16-bit reload
timer.
Chapter 12 PWC Timer
This chapter describes the functions and operation of the MB90820 series PWC timer.
Chapter 13 16-BIT PPG Timer
This chapter describes the functions and operation of the MB90820 series 16-bit PPG timer.
Chapter 14 Multi-functional Timer
This chapter describes the functions and operation of the MB90820 series multi-functional
timer.
Chapter 15 Delayed Interrupt Generator Module
This chapter describes the functions and operation of the MB90820 series multi-pulse
generator.
Chapter 16 DTP/External Interrupt Circuit
This chapter describes the functions and operation of the MB90820 series DTP/external
interrupt circuit.
Chapter 17 8/10-bit A/D Converter
This chapter describes the functions and operation of the MB90820 series 8/10-bit A/D
Converter.
Chapter 18 8-bit D/A Converter
This chapter describes the functions and operation of the MB90820 series 8-bit D/A
Converter.
Chapter 19 UART
This chapter describes the functions and operation of the MB90820 series UART.
Chapter 20 ROM Correction Function
This chapter describes the functions and operation of the MB90820 series ROM correction
function.
Chapter 21 ROM Mirroring Function Selection Module
This chapter describes the functions and operation of the MB90820 series ROM mirroring
function selection module.
Chapter 22 512K / 1024K bit Flash Memory
This chapter describes the functions and operation of the MB90820 series 512K / 1024K bit
flash memory.
Appendix A I/O Map
The appendix A contains an I/O map and instruction overview.
Appendix B Example of F2MC-16LX for Serial Writing
This chapter describes the examples of F2MC-16LX MB90F822/F823 connections for 512K /
1024K bit flash serial writing.
Appendix C Instructions
The appendix C contains an instruction overview.
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The contents of this document are subject to change without notice. Customers are advised to consult
with FUJITSU sales representatives before ordering.
The information and circuit diagrams in this document are presented as examples of semiconductor
device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is
unable to assume responsibility for infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
The products described in this document are designed, developed and manufactured as contemplated
for general use, including without limitation, ordinary industrial use, general office use, personal use, and
household use, but are not designed, developed and manufactured as contemplated (1) for use
accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious
effect to the public, and could lead directly to death, personal injury, severe physical damage or other
loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass
transport control, medical life support system, missile launch control in weapon system), or (2) for use
requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages
arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage
or loss from such failures by incorporating safety design measures into your facility and equipment such
as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or technologies subject to certain
restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export of those products from Japan.
c 2003 FUJITSU LIMITED Printed in Japan
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iv
CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
OVERVIEW ....................................................................................................1
MB90820 Series Features .................................................................................................................2
MB90820 Series Product line-up .......................................................................................................6
Block Diagram of MB90820 Series ....................................................................................................8
Pin Assignment ................................................................................................................................10
Package Dimensions .......................................................................................................................12
I/O Pins and Pin Functions ..............................................................................................................15
I/O Circuit Types ..............................................................................................................................18
Notes on Handling Devices .............................................................................................................22
CHAPTER 2
CPU ..............................................................................................................25
2.1 CPU .................................................................................................................................................26
2.2 Memory Space ................................................................................................................................28
2.3 Memory Maps ..................................................................................................................................30
2.4 Addressing .......................................................................................................................................31
2.4.1
Address specification by linear addressing .............................................................................32
2.4.2
Address specification by bank addressing ..............................................................................33
2.5 Memory Location of Multibyte Data .................................................................................................36
2.6 Registers .........................................................................................................................................38
2.7 Dedicated Registers ........................................................................................................................40
2.7.1 Accumulator (A) .........................................................................................................................42
2.7.2 Stack Pointers (USP, SSP) .......................................................................................................46
2.7.3 Processor Status (PS) ...............................................................................................................48
2.7.4 Condition code register (PS: CCR) ..........................................................................................49
2.7.5 Register bank pointer (PS: RP) .................................................................................................51
2.7.6 Interrupt level mask register (PS: ILM) ......................................................................................52
2.7.7 Program Counter (PC) ..............................................................................................................53
2.7.8 Direct Page Register (DPR) ......................................................................................................54
2.7.9 Bank Registers (PCB, DTB, USB, SSB, ADB) ..........................................................................55
2.8 General-purpose Registers .............................................................................................................56
2.9 Prefix Codes ....................................................................................................................................58
2.9.1 Bank select prefix (PCB, DTB, ADB, SPB) ................................................................................60
2.9.2 Common register bank prefix (CMR) .........................................................................................62
2.9.3 Flag change suppression prefix (NCC) .....................................................................................63
2.9.4 Restrictions on Prefix Codes .....................................................................................................64
CHAPTER 3
3.1
3.2
3.3
3.4
3.5
3.6
RESET ..........................................................................................................67
Reset ...............................................................................................................................................68
Reset Causes and Oscillation Stabilization Wait Intervals ..............................................................70
External Reset Pin ...........................................................................................................................71
Reset Operation ..............................................................................................................................72
Reset Cause Bits .............................................................................................................................74
Status of Pins in a Reset .................................................................................................................76
MB90820 series
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CHAPTER 4
CLOCK ........................................................................................................ 77
4.1 Clock ............................................................................................................................................... 78
4.2 Block Diagram of the Clock Generation Block ................................................................................ 80
4.3 Clock Selection Registers ............................................................................................................... 82
4.3.2 PLL Clock Control Register (PCKCR) ...................................................................................... 86
4.4 Clock Mode ..................................................................................................................................... 88
4.5 Oscillation Stabilization Wait Interval .............................................................................................. 90
4.6 Connection of an Oscillator or an External Clock to the Microcontroller ......................................... 91
CHAPTER 5
LOW POWER CONSUMPTION MODE ...................................................... 93
5.1 Low Power Consumption Mode ...................................................................................................... 94
5.2 Block Diagram of the Low Power Consumption Control Circuit ...................................................... 96
5.3 Low Power Consumption Mode Control Register (LPMCR) ........................................................... 98
5.4 CPU Intermittent Operation Mode ................................................................................................ 101
5.5 Standby Mode ............................................................................................................................... 102
5.5.1 Sleep mode ............................................................................................................................ 103
5.5.2 Timebase timer mode ............................................................................................................. 106
5.5.3 Stop mode .............................................................................................................................. 108
5.6 State Change Diagram ................................................................................................................. 110
5.7 State of Pins in Standby Mode and during Reset ......................................................................... 113
5.8 Usage Notes on Low Power Consumption Mode ......................................................................... 114
CHAPTER 6
.............................................................................................. INTERRUPT 117
6.1 Interrupt ........................................................................................................................................ 118
6.2 Interrupt Causes and Interrupt Vectors ......................................................................................... 120
6.3 Interrupt Control Registers and Peripheral Functions ................................................................... 123
6.3.1
Interrupt control registers (ICR00 to ICR15) .......................................................................... 124
6.3.2 Interrupt control register functions .......................................................................................... 126
6.4 Hardware Interrupt ........................................................................................................................ 130
6.4.1 Operation of hardware interrupt .............................................................................................. 134
6.4.2 Processing for interrupt operation .......................................................................................... 136
6.4.3 Procedure for using hardware interrupt .................................................................................. 137
6.4.4 Multiple interrupts ................................................................................................................... 138
6.4.5 Hardware interrupt processing time ........................................................................................ 140
6.5 Software Interrupt ......................................................................................................................... 142
6.6 Interrupt of Extended Intelligent I/O Service (EI²OS) .................................................................... 144
6.6.1 Extended intelligent I/O service (EI²OS) descriptor (ISD) ....................................................... 146
6.6.2 Registers of EI2OS descriptor (ISD) ....................................................................................... 147
6.6.3 Operation of the extended intelligent I/O service (EI²OS) ....................................................... 150
6.6.4 Procedure for using the extended intelligent I/O service (EI²OS) ........................................... 151
6.6.5 Processing time of the extended intelligent I/O service (EI²OS) ............................................. 152
6.7 Exception Processing Interrupt ..................................................................................................... 154
6.8 Stack Operations for Interrupt Processing .................................................................................... 156
6.9 Sample Programs for Interrupt Processing ................................................................................... 158
CHAPTER 7
7.1
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MODE SETTING ........................................................................................ 161
Mode Setting ................................................................................................................................. 162
MB90820 series
7.2
7.3
Mode Pins (MD2 to MD0) ..............................................................................................................163
Mode Data .....................................................................................................................................164
CHAPTER 8
I/O PORTS ..................................................................................................167
8.1 Overview of I/O Ports ....................................................................................................................168
8.2 Registers of I/O Ports ....................................................................................................................170
8.3
Port 0 ............................................................................................................................................172
8.3.1 Port 0 Registers (PDR0, DDR0 and RDR0) ............................................................................176
8.3.2 Operation of Port 0 ..................................................................................................................178
8.4 Port 1 .............................................................................................................................................180
8.4.1 Port 1 Registers (PDR1, DDR1 and RDR1) ............................................................................183
8.4.2 Operation of Port 1 ..................................................................................................................184
8.5 Port 2 .............................................................................................................................................186
8.5.1 Port 2 Registers (PDR2, DDR2 and RDR2) ............................................................................189
8.5.2 Operation of Port 2 ..................................................................................................................190
8.6 Port 3 .............................................................................................................................................192
8.6.1 Port 3 Registers (PDR3, DDR3 and RDR3) ............................................................................195
8.6.2 Operation of Port 3 ..................................................................................................................196
8.7 Port 4 .............................................................................................................................................198
8.7.1 Port 4 Registers (PDR4 and DDR4) ........................................................................................201
8.7.2 Operation of Port 4 ..................................................................................................................202
8.8 Port 5 .............................................................................................................................................204
8.8.1 Port 5 Registers (PDR5 and DDR5) ........................................................................................207
8.8.2 Operation of Port 5 ..................................................................................................................208
8.9 Port 6 .............................................................................................................................................210
8.9.1 Port 6 Registers (PDR6, DDR6 and ADER0) ..........................................................................212
8.9.2 Operation of Port 6 ..................................................................................................................214
8.10 Port 7 .............................................................................................................................................216
8.10.1 Port 7 Registers (PDR7, DDR7 and ADER1) ..........................................................................222
8.10.2 Operation of Port 7 ..................................................................................................................224
8.11 Port 8 .............................................................................................................................................226
8.11.1 Port 8 Registers (PDR8 and DDR8) ........................................................................................229
8.11.2 Operation of Port 8 ..................................................................................................................230
8.12 Sample Program for the I/O Port ...................................................................................................232
CHAPTER 9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
TIMEBASE TIMER .....................................................................................233
Overview of the Timebase Timer ...................................................................................................234
Configuration of the Timebase Timer ............................................................................................236
Timebase Timer Control Register (TBTC) .....................................................................................238
Timebase Timer Interrupts ............................................................................................................240
Operation of the Timebase Timer ..................................................................................................241
Usage Notes on the Timebase Timer ............................................................................................243
Sample Program for the Timebase Timer Program .......................................................................245
CHAPTER 10 WATCHDOG TIMER ..................................................................................247
10.1 Overview of the Watchdog Timer ..................................................................................................248
10.2 Configuration of the Watchdog Timer ............................................................................................249
MB90820 series
vii
10.3
10.4
10.5
10.6
Watchdog Timer Control Register (WDTC) .................................................................................. 250
Operation of the Watchdog Timer ................................................................................................. 252
Usage Notes on the Watchdog Timer ........................................................................................... 254
Sample Program for the Watchdog Timer .................................................................................... 255
CHAPTER 11 16-BIT RELOAD TIMER ............................................................................ 257
11.1 Overview of 16-Bit Reload Timer .................................................................................................. 258
11.2 Configuration of 16-Bit Reload Timer ........................................................................................... 261
11.3 Pins of 16-Bit Reload Timer .......................................................................................................... 263
11.4 Registers of 16-Bit Reload Timer .................................................................................................. 264
11.4.1 Upper Bits of Timer Control Status Registers
(TMCSRH0/1) ..................................................................................................................... 266
11.4.2 Lower Bits of Timer Control Status Registers
(TMCSRL0/1) ......................................................................................................................... 268
11.4.3 16-Bit Timer Registers (TMR0/1) ............................................................................................ 270
11.4.4 16-Bit Reload Registers (TMRDL0/1, TMRDH0/1) ................................................................. 271
11.5 Interrupts of 16-Bit Reload Timer .................................................................................................. 272
11.6 Operation of 16-Bit Reload Timer ................................................................................................. 274
11.6.1 Internal Clock Mode (Reload Mode) ....................................................................................... 276
11.6.2 Internal Clock Mode (One-Shot Mode) ................................................................................... 278
11.6.3 Event Count Mode .................................................................................................................. 282
11.7 Notes on Using the 16-Bit Reload Timer ...................................................................................... 284
11.8 Sample Programs for the 16-Bit Reload Timer ............................................................................. 285
CHAPTER 12 PWC Timer ................................................................................................ 289
12.1 Overview of the PWC Timer ......................................................................................................... 290
12.2 Block Diagram of the PWC Timer ................................................................................................. 291
12.3 PWC Timer Pins ........................................................................................................................... 292
12.4 PWC Timer Registers ................................................................................................................... 295
12.4.1 PWC control status register (PWCSH0/1, PWCSL0/1) .......................................................... 296
12.4.2 PWC data buffer register (PWC0/1) ....................................................................................... 302
12.4.3 Division rate control register (DIV0/1) ..................................................................................... 303
12.5 PWC Timer Interrupts ................................................................................................................... 304
12.6 Operation of the PWC Timer ........................................................................................................ 306
12.6.1 Operation mode selection ....................................................................................................... 310
12.6.2 Starting and stopping the timer and pulse-width measurement and clearing the timer .......... 311
12.6.3 Timer Mode Operation ............................................................................................................ 313
12.6.4 Pulse Width Measurement Mode Operation ........................................................................... 317
12.7 Usage Notes on the PWC Timer .................................................................................................. 324
12.8 Sample Programs for the PWC Timer .......................................................................................... 326
CHAPTER 13 16-BIT PPG TIMER ................................................................................... 329
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13.1 Overview of 16-bit PPG Timer ...................................................................................................... 330
13.2 Block Diagram of 16-bit PPG Timer .............................................................................................. 331
13.3 16-bit PPG Timer Pins .................................................................................................................. 332
13.4 16-bit PPG Timer Registers .......................................................................................................... 334
13.4.1 PPG Down Counter Register (PDCR0 ~ 2) ............................................................................ 336
13.4.2 PPG Period Setting Buffer Register (PCSR0 ~ 2) .................................................................. 337
MB90820 series
13.4.3 PPG Duty Setting Buffer Register (PDUT0 ~ 2) ......................................................................338
13.4.4 PPG Control Status Register (PCNTL0 ~ 2, PCNTH0 ~ 2) .....................................................340
13.5 16-bit PPG Timer Interrupts ...........................................................................................................344
13.6 Operation of 16-bit PPG Timer ......................................................................................................346
13.7 Usage Notes on the 16-bit PPG Timer ..........................................................................................350
13.8 Sample Programs for the 16-bit PPG Timer ..................................................................................352
CHAPTER 14 MULTI-FUNCTIONAL TIMER ....................................................................355
14.1 Overview of Multi-functional Timer ................................................................................................356
14.2 Block Diagram of Multi-functional Timer ........................................................................................358
14.3 Multi-functional Timer Pins ............................................................................................................362
14.4 Registers of Multi-functional Timer ................................................................................................365
14.4.1 Compare Clear Buffer Register (CPCLRB) and Compare Clear Register (CPCLR) ...............369
14.4.2 Timer Data Register (TCDT) ...................................................................................................370
14.4.3 Timer Control Status Register (TCCSH, TCCSL) ....................................................................372
14.4.4 Output Compare Buffer Registers (OCCPB0 ~ 5) / Output Compare Registers (OCCP0 ~ 5) 376
14.4.5 Compare Control Registers (OCS0/1/2/3/4/5) .........................................................................378
14.4.6 Input Capture Register (IPCP0 ~ 3) ........................................................................................383
14.4.7 Input Capture Control Status Registers (ICS23, PICS01) .......................................................384
14.4.8 16-bit Timer Register (TMRR0/1/2) .........................................................................................392
14.4.9 16-bit Timer Control Register (DTCR0/1/2) .............................................................................394
14.4.10 Waveform Control Register (SIGCR) ......................................................................................398
14.5 Multi-functional Timer Interrupts ....................................................................................................400
14.6 Operation of Multi-functional Timer ...............................................................................................404
14.6.1 Operation of 16-bit free-running timer .....................................................................................405
14.6.2 Operation of 16-bit Output Compare .......................................................................................411
14.6.3 Operation of 16-bit Input Capture ............................................................................................416
14.6.4 Operation of Waveform Generator ..........................................................................................418
14.6.4.1 Operation in Timer Mode ....................................................................................................422
14.6.4.2 Operation in Dead-time Timer Mode ..................................................................................424
14.6.4.3 Operation of DTTI Pin Control ............................................................................................428
14.7 Usage Notes on the Multi-functional Timer ...................................................................................430
14.8 Sample Programs for the Multi-functional Timer ...........................................................................432
CHAPTER 15 DELAYED INTERRUPT GENERATOR MODULE ....................................435
15.1
15.2
15.3
15.4
Overview of the Delayed Interrupt Generator Module ...................................................................436
Delayed Interrupt Generator Module Register ...............................................................................437
Operation of the Delayed Interrupt Generator Module ..................................................................438
Usage Notes on the Delayed Interrupt Generator Module ............................................................439
CHAPTER 16 DTP/EXTERNAL INTERRUPT CIRCUIT ...................................................441
16.1 Overview of the DTP/External Interrupt Circuit ..............................................................................442
16.2 Block Diagram of the DTP/External Interrupt Circuit .....................................................................444
16.3 DTP/External Interrupt Circuit Pins ................................................................................................446
16.4 DTP/External Interrupt Circuit Registers .......................................................................................448
16.4.1 DTP/interrupt cause register (EIRR) ........................................................................................449
16.4.2 DTP/interrupt enable register (ENIR) ....................................................................................450
MB90820 series
ix
16.4.3 Request level setting register (ELVR) .................................................................................. 452
16.5 Operation of the DTP/External Interrupt Circuit ............................................................................ 454
16.5.1 External interrupt function ..................................................................................................... 458
16.5.2 DTP function ......................................................................................................................... 459
16.6 Usage Notes on the DTP/External Interrupt Circuit ...................................................................... 460
16.7 Sample Programs for the DTP/External Interrupt Circuit .............................................................. 462
17.1 Features of A/D Converter ............................................................................................................ 466
17.2 Block Diagram of A/D Converter ................................................................................................... 469
17.3 Registers for A/D Converter .......................................................................................................... 470
17.4 Operation of A/D Converter .......................................................................................................... 482
17.5 Conversion Using EI2OS .............................................................................................................. 484
17.6 Converted-data Protection Function ............................................................................................. 492
CHAPTER 18 D/A CONVERTER ..................................................................................... 495
18.1 Overview of D/A Converter ........................................................................................................... 496
18.2 Block Diagram of D/A Converter ................................................................................................... 497
18.3 D/A Converter Pins ....................................................................................................................... 498
18.4 D/A Converter Registers ............................................................................................................... 499
18.4.1 D/A converter register 1 (DAT1) ............................................................................................. 500
18.4.2 D/A Converter Register 0 (DAT0) ........................................................................................... 501
18.4.3 D/A Control Register 1 (DACR1) ............................................................................................ 502
18.4.4 D/A Control Register 0 (DACR0) ............................................................................................ 503
18.5 Sample Programs for the D/A Converter ...................................................................................... 504
CHAPTER 19 UART ......................................................................................................... 505
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19.1 Overview of UART ........................................................................................................................ 506
19.2 Block Diagram of UART ................................................................................................................ 508
19.3 UART Pins .................................................................................................................................... 512
19.4 UART Registers ............................................................................................................................ 515
19.4.1 Serial Control Register (SCR0/1) ............................................................................................ 516
19.4.2 Serial Mode Register (SMR0/1) ............................................................................................ 518
19.4.3 Serial Status Register (SSR0/1) ........................................................................................... 520
19.4.4 Input Data Register (SIDR0/1) and Output Data Register (SOR0/1) ...................................... 522
19.4.5 Communication Prescaler Control Register (CDCR) .............................................................. 524
19.5 UART Interrupts ............................................................................................................................ 526
19.5.1 Reception Interrupt Generation and Flag Set Timing ............................................................. 528
19.5.2 Transmission Interrupt Generation and Flag Set Timing ........................................................ 529
19.6 UART Baud Rates ........................................................................................................................ 530
19.6.1 Baud Rates Determined Using the Dedicated Baud Rate Generator ..................................... 532
19.6.2 Baud Rates Determined Using the Internal Timer (16-bit Reload Timer 0) ............................ 536
19.6.3 Baud Rates Determined Using the External Clock ................................................................. 538
19.7 Operation of UART ....................................................................................................................... 540
19.7.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) .............................................. 542
19.7.2 Operation in Synchronous Mode (Operation Mode 2) ............................................................ 544
19.7.3 Bidirectional Communication Function (Normal Mode) .......................................................... 546
19.7.4 Master-slave Communication Function (Multiprocessor Mode) .............................................. 548
19.8 Usage Notes on UART ................................................................................................................. 552
19.9 Sample Program for UART ........................................................................................................... 554
MB90820 series
CHAPTER 20 ROM CORRECTION FUNCTION ...............................................................557
20.1 Overview of the ROM Correction Function ....................................................................................558
20.2 Block Diagram of ROM Correction Function .................................................................................559
20.3 ROM Correction Function Registers ..............................................................................................560
20.3.1 Program address detection register (PADR0/PADR1) ...........................................................561
20.3.2 Program address detection control status register (PACSR) .................................................562
20.4 Operation of the ROM Correction Function ...................................................................................564
20.5 Example of Using ROM Correction Function .................................................................................565
CHAPTER 21 ROM MIRRORING FUNCTION SELECTION MODULE ............................569
21.1 Overview of the ROM Mirroring Function Selection Module ..........................................................570
21.2 ROM Mirroring Function Selection Register (ROMM) ...................................................................571
CHAPTER 22 512K / 1024K BIT FLASH MEMORY .........................................................573
22.1 Overview of the 512K / 1024K Bit Flash Memory ..........................................................................574
22.2 512K / 1024K Bit Flash Memory Sector Configuration ..................................................................575
22.3 Flash Memory Control Status Register (FMCS) ............................................................................576
22.4 Method of Starting the Automatic Algorithm in Flash Memory ......................................................578
22.5 Verifying Automatic Algorithm Execution Status ...........................................................................580
22.5.1 Data Polling Flag (DQ7) ........................................................................................................582
22.5.2 Toggle Bit Flag (DQ6) ...........................................................................................................584
22.5.3 Time limit Exceeded Flag (DQ5) ............................................................................................585
22.5.4 Sector Deletion Timer Flag (DQ3) ...........................................................................................586
22.6 Detailed Explanation on the Flash Memory Write/Delete ..............................................................587
22.6.1 Setting the Read/Reset Status ................................................................................................588
22.6.2 Writing the Data .......................................................................................................................590
22.6.3 Deleting the Data (Chip Deletion) ............................................................................................592
22.6.4 Deleting the Data (Sector Deletion) .........................................................................................594
22.6.5 Temporarily Stopping the Sector Deletion ...............................................................................596
22.6.6 Restarting the Sector Deletion ................................................................................................597
22.7 Flash Security Feature ..................................................................................................................598
22.8 Programming Example of 512K Bit Flash Memory ........................................................................599
APPENDIX A I/O MAP ......................................................................................................603
APPENDIX B EXAMPLE OF F²MC-16LX MB90F822/F823 CONNECTION FOR SERIAL
WRITING ....................................................................................................609
B.1
B.2
B.3
B.4
B.5
Standard Configuration for Serial On-board Writing (Fujitsu Standard) ........................................610
Example of Connection for Serial Writing (When Power Supplied by User) .................................612
Example of Connection for Serial Writing (When Power Supplied from Writer) ............................614
Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied by
User) ..............................................................................................................................................616
Example of Minimum Connection with Flash Microcomputer Programmer (When Power Supplied from
Writer) ............................................................................................................................................618
APPENDIX C INSTRUCTIONS .........................................................................................621
C.1
Instructions ....................................................................................................................................622
MB90820 series
xi
C.2
C.3
C.4
C.5
C.6
C.7
C.8
C.9
xii
Addressing .................................................................................................................................... 623
Direct Addressing ......................................................................................................................... 625
Indirect Addressing ....................................................................................................................... 631
Number of Execution Cycles ........................................................................................................ 638
Effective-address Field ................................................................................................................. 641
Reading the Instruction List .......................................................................................................... 642
List of F²MC-16LX Instructions ..................................................................................................... 645
Instruction Maps ........................................................................................................................... 659
MB90820 series
FIGURES
Figure 1.3-1
MB90820 Series Overall Block Diagram .................................................................................8
Figure 1.4-1
FPT-64P-M06 Pin Assignment ..............................................................................................10
Figure 1.4-2
FPT-80P-M05/FPT-80P-M11 Pin Assignment ......................................................................11
Figure 1.5-1
FPT-80P-M05 Package Dimensions .....................................................................................12
Figure 1.5-2
FPT-80P-M06 Package Dimensions .....................................................................................13
Figure 1.5-3
FPT-80P-M11 Package Dimensions .....................................................................................14
Figure 1.8-1
Sample application of external clock .....................................................................................23
Figure 2.2-1
Sample relationship between the F2MC-16LX system and the memory map ......................28
Figure 2.3-1
Memory maps ........................................................................................................................30
Figure 2.4-1
Linear addressing and bank addressing memory management ...........................................31
Figure 2.4.1-1
Example of direct specification of a 24-bit physical address in linear addressing .................32
Figure 2.4.1-2
Example of indirect specification with a 32-bit general-purpose register
in linear addressing ...............................................................................................................32
Figure 2.4.2-1
Sample bank addressing .......................................................................................................34
Figure 2.5-2
Storage of a multibyte operand .............................................................................................36
Figure 2.5-3
Storage of multibyte data in a stack ......................................................................................37
Figure 2.5-4
Multibyte data access on a bank boundary ...........................................................................37
Figure 2.7.1-1
Data transfer to the accumulator ...........................................................................................42
Figure 2.7.1-2
Example of AL-AH transfer in the accumulator (A) (8-bit immediate value, zero extension) 43
Figure 2.7.1-3
Example of AL-AH transfer in the accumulator (A) (8-bit immediate value, sign extension) .43
Figure 2.7.1-4
Example of 32-bit data transfer to the accumulator (A) (register indirect) .............................43
Figure 2.7.1-5
Example of AL-AH transfer in the accumulator (A) (16 bits, register indirect) .......................44
Figure 2.7.2-1
Stack operation instruction and stack pointer ........................................................................47
Figure 2.7.3-1
Processor status (PS) configuration ......................................................................................48
Figure 2.7.4-1
Condition code register (CCR) configuration .........................................................................49
Figure 2.7.5-1
Configuration of the register bank pointer (RP) .....................................................................51
Figure 2.7.5-2
Conversion rules for physical address of general-purpose register area ..............................51
Figure 2.7.6-1
Configuration of the interrupt level mask register (ILM) ........................................................52
Figure 2.7.7-1
Program counter (PC) ...........................................................................................................53
Figure 2.7.8-1
Physical address generation by the direct page register (DPR) ............................................54
Figure 2.7.8-2
Example of direct page register (DPR) setting and data access ...........................................54
Figure 2.8-1
Location and configuration of the general-purpose register banks in the memory space .....56
Figure 2.9.4-1
Interrupt/hold suppression .....................................................................................................64
Figure 2.9.4-2
Interrupt/hold suppression instructions and prefix codes ......................................................65
Figure 2.9.4-3
Consecutive prefix codes ......................................................................................................65
MB90820 series
xiii
Figure 3.2-1
Oscillation stabilization wait interval at power-on reset ........................................................ 70
Figure 3.3-1
Block diagram of external reset ............................................................................................ 71
Figure 3.4-1
Reset operation flow ............................................................................................................. 72
Figure 3.4-2
Transfer of reset vector and mode data ............................................................................... 73
Figure 3.5-1
Block diagram of reset cause bits ......................................................................................... 74
Figure 3.5-2
Configuration of reset cause bits (watchdog timer control register) ..................................... 75
Figure 4.1-1
Clock supply map ................................................................................................................. 79
Figure 4.2-1
Block diagram of the clock generation block ........................................................................ 80
Figure 4.3-1
Clock selection registers ....................................................................................................... 82
Figure 4.3.1-1
Configuration of the clock selection register (CKSCR) ......................................................... 84
Figure 4.3.2-1
Configuration of the PLL clock control register (PCKCR) ..................................................... 86
Figure 4.4-1
Status change diagram for machine clock selection ............................................................ 89
Figure 4.5-1
Operation when oscillation starts .......................................................................................... 90
Figure 4.6-1
Example of connecting a crystal or ceramic oscillator to the microcontroller ....................... 91
Figure 4.6-3
Example of connecting an external clock to the microcontroller ........................................... 91
Figure 5.1-1
CPU operating modes and current consumption .................................................................. 94
Figure 5.2-1
Block diagram of the low power consumption control circuit ................................................ 96
Figure 5.3-1
Configuration of the low power consumption mode control register (LPMCR) ..................... 98
Figure 5.4-1
Clock pulses during CPU intermittent operation ................................................................. 101
Figure 5.5.1-1
Release of sleep mode for an interrupt .............................................................................. 104
Figure 5.5.1-2
Release of PLL sleep mode (by external reset) ................................................................. 105
Figure 5.5-2-1
Release of timebase timer mode (by an external reset) ..................................................... 107
Figure 5.5.3-1
Release of main stop mode (by external reset) .................................................................. 109
Figure 5.6-1
State change diagram ........................................................................................................ 110
Figure 6.1-1
Overall flow of interrupt operation ....................................................................................... 119
Figure 6.3.1-1
Interrupt control registers (ICR00 to ICR15) during writing ................................................ 124
Figure 6.3.1-2
Interrupt control registers (ICR00 to ICR15) during reading ............................................... 125
Figure 6.3.2-1
Configuration of interrupt control registers (ICR) ................................................................ 126
Figure 6.4-1
Hardware interrupt request while writing to the peripheral function
control register area ............................................................................................................ 132
Figure 6.4.1-1
Hardware interrupt operation .............................................................................................. 135
Figure 6.4.2-1
Flow of interrupt processing ............................................................................................... 136
Figure 6.4.3-1
Procedure for using hardware interrupt .............................................................................. 137
Figure 6.4.4-1
Example of multiple interrupts ............................................................................................ 139
Figure 6.4.5-1
Interrupt processing time .................................................................................................... 140
Figure 6.5-1
Software interrupt operation ............................................................................................... 143
Figure 6.6-1
Extended intelligent I/O service (EI²OS) operation ............................................................. 145
Figure 6.6.1-1
Configuration of EI²OS descriptor (ISD) ............................................................................. 146
xiv
MB90820 series
Figure 6.6.2-1
Configuration of DCT ...........................................................................................................147
Figure 6.6.2-2
Configuration of I/O register address pointer (IOA) .............................................................147
Figure 6.6.2-3
Configuration of EI²OS status register (ISCS) .....................................................................148
Figure 6.6.2-4
Configuration of buffer address pointer (BAP) ....................................................................149
Figure 6.8-1
Stack operations at the start of interrupt processing ...........................................................156
Figure 6.8-2
Stack area ...........................................................................................................................157
Figure 7.1-1
Mode classification ..............................................................................................................162
Figure 7.3-1
Mode data configuration ......................................................................................................164
Figure 7.3-2
Correspondence between access areas and physical addresses in single-chip mode ......165
Figure 8.3-1
Block diagram of P00 to P06/PWI0 pins .............................................................................173
Figure 8.3-2
Block diagram of P07/PWO0 pins .......................................................................................173
Figure 8.4-1
Block diagram of P10/DTTI/INT0 to P16/INT6 pins .............................................................181
Figure 8.4-2
Block diagram of P17 ..........................................................................................................181
Figure 8.5-1
Block diagram of port 2 (excluding P21/TO1) pins ..............................................................187
Figure 8.5-2
Block diagram of P21/TO1 pin ............................................................................................187
Figure 8.6-1
Block diagram of port 3 (excluding P37/PPG0) pins ...........................................................193
Figure 8.6-2
Block diagram of P37/PPG0 pin ..........................................................................................193
Figure 8.7-1
Block diagram of port 4 (excluding P41/TIN0, P45/SIN0, P46/PWI1) pins .........................199
Figure 8.7-2
Block diagram of P41/TIN0 and P46/PWI1 pins ..................................................................199
Figure 8.7-3
Block diagram of P45/SIN0 pin ...........................................................................................200
Figure 8.8-1
Block diagram of P50/PPG2 pin ..........................................................................................205
Figure 8.8-2
Block diagram of P51/INT7 pin ............................................................................................205
Figure 8.9-1
Block diagram of P60/AN0 to P67/AN7 ...............................................................................211
Figure 8.10-1
Block diagram of P70/DA0/AN8 and P71/DA1/AN9 pins ....................................................217
Figure 8.10-2
Block diagram of P72/SIN1/AN10 pin .................................................................................218
Figure 8.10-3
Block diagram of P73/SOT1/AN11 to P74/SCK1/AN12 pins ..............................................219
Figure 8.10-4
Block diagram of P73/SOT1/AN11 to P77/IN1/AN15 pins ..................................................220
Figure 8.11-1
Block diagram of P80/IN2 to P81/IN3 ..................................................................................227
Figure 8.11-2
Block diagram of P82/RTO0 to P87/RTO5 ..........................................................................227
Figure 8.12-1
Example of eight-segment LED connection ........................................................................232
Figure 9.2-1
Block diagram of the timebase timer ...................................................................................236
Figure 9.3-1
Timebase timer control register (TBTC) ..............................................................................238
Figure 9.5-1
Setting of the timebase timer ...............................................................................................241
Figure 9.6-1
Timebase timer operations ..................................................................................................244
Figure 10.2-1
Block diagram of the watchdog timer ..................................................................................249
Figure 10.3-1
Watchdog timer control register (WDTC) ............................................................................250
Figure 10.4-1
Setting of the watchdog timer ..............................................................................................252
Figure 10.4-2
Clear timing and watchdog timer intervals ..........................................................................253
MB90820 series
xv
Figure 11.2-1
Block Diagram of 16-bit Reload Timer ............................................................................. 261
Figure 11.4-1
Registers of 16-bit Reload Timer ..................................................................................... 264
Figure 11.4.1-1 Upper Bits and Bit 7 of Timer Control Status Registers (TMCSRH0/1) .............................. 266
Figure 11.4.2-1 Lower Bits of Timer Control Status Registers (TMCSRL0/1) ............................................. 268
Figure 11.4.3-1 Bit Configuration of 16-bit Timer Registers (TMR0/1) ........................................................ 270
Figure 11.4.4-1 Bit Configuration of 16-bit Reload Registers (TMRDL0/1, TMRDH0/1) .............................. 271
Figure 11.6-1
Internal Clock Mode Settings .............................................................................................. 274
Figure 11.6-2
Event Count Mode Settings ................................................................................................ 274
Figure 11.6-3
State Transition Diagram of Counter States ....................................................................... 275
Figure 11.6.1-1 Count Operation (Software Trigger Operation) in Reload Mode ........................................ 276
Figure 11.6.1-2 Count Operation in Reload Mode (External Trigger Operation) ......................................... 277
Figure 11.6.1-3 Count Operation in Reload Mode (Software Trigger, Gate Input Operation) ..................... 277
Figure 11.6.2-1 Count Operation in One-shot Mode (Software Trigger Operation) ..................................... 278
Figure 11.6.2-2 Count Operation in One-shot Mode (External Trigger Operation) ...................................... 279
Figure 11.6.2-3 Count Operation in One-shot Mode (Software Trigger, Gate Input Operation) .................. 280
Figure 11.6.3-1 Count Operation in Reload Mode (Event Count Mode) ...................................................... 282
Figure 11.6.3-2 Counter Operation in One-shot Mode (Event Count Mode) ............................................... 283
Figure 12.2-1
PWC timer block diagram ................................................................................................... 291
Figure 12.3-1
Block diagram of the PWC timer 0 input pin ....................................................................... 292
Figure 12.3-2
Block diagram of the PWC timer 0 output pin ..................................................................... 293
Figure 12.3-3
Block diagram of the PWC timer 1 input pin ....................................................................... 293
Figure 12.3-4
Block diagram of the PWC timer 1 output pin ..................................................................... 294
Figure 12.4.1-1 PWC control status register (PWCSH0/1) .......................................................................... 296
Figure 12.4.1-2 PWC control status register (PWCSL0/1) ........................................................................... 300
Figure 12.4.2-1 PWC data buffer register (PWC0/1) ................................................................................... 302
Figure 12.4.3-1 Division rate control register (DIV0/1) ................................................................................. 303
Figure 12.6-1
Timer operation (single mode) ............................................................................................ 306
Figure 12.6-2
Timer operation (reload mode) ........................................................................................... 307
Figure 12.6-3
Pulse-width measurement operation (single measurement mode, H width measurement
mode) ................................................................................................................................. 308
Figure 12.6-4
Pulse-width measurement operation (continuous measurement mode, H-width measurement
mode) ................................................................................................................................. 309
Figure 12.6.3-1 Flowchart of timer mode operation ..................................................................................... 315
Figure 12.6.4-1 Flowchart of pulse-width measurement mode operation .................................................... 322
Figure 13.2-1
Block diagram of 16-bit PPG Timer .................................................................................... 331
Figure 13.3-1
Block diagram of the 16-bit PPG timer 1 & 2 output pins ................................................... 332
Figure 13.3-2
Block diagram of the 16-bit PPG timer 0 pin ...................................................................... 333
Figure 13.4-1
Registers of 16-bit PPG timer ............................................................................................. 335
xvi
MB90820 series
Figure 13.4.1-1 PPG down counter register (PDCR0 ~ 2) ............................................................................336
Figure 13.4.2-1 PPG period setting buffer register (PCSR0 ~ 2) ..................................................................337
Figure 13.4.3-1 PPG duty setting buffer register (PDUT0 ~ 2) .....................................................................338
Figure 13.4.4-1 PPG0 ~ 2 control register (PCNTH0 ~ 2) ............................................................................340
Figure 13.4.4-2 PPG control register (PCNTL0 ~ 2) .....................................................................................342
Figure 13.6-1
Retriggering is disabled in PWM mode ...............................................................................346
Figure 13.6-2
Retriggering is enabled in PWM mode ................................................................................347
Figure 13.6-3
Retriggering is disabled in single-shot mode .......................................................................347
Figure 13.6-4
Retriggering is enabled in single-shot mode .......................................................................348
Figure 13.6-5
Gate trigger in PWM mode when retriggering is enable ......................................................348
Figure 13.6-6
PPG interrupt timing ............................................................................................................349
Figure 14.2-1
Block diagram of multi-functional timer ...............................................................................358
Figure 14.2-2
Block diagram of 16-bit free-running timer ..........................................................................359
Figure 14.2-3
Block diagram of 16-bit output compare ..............................................................................360
Figure 14.2-4
Block diagram of 16-bit input capture ..................................................................................360
Figure 14.2-5
Waveform generator block diagram ....................................................................................361
Figure 14.3-1
Block diagram of P10/INT0/DTTI ........................................................................................363
Figure 14.3-2
Block diagram of P75/FRCK/AN13 ~ P77/IN1/AN15 ..........................................................363
Figure 14.3-3
Block diagram of P80/IN2 ~ P81/IN3 ...................................................................................364
Figure 14.3-4
Block diagram of P82/RTO0 ~ P87/RTO5 ...........................................................................364
Figure 14.4-1
Registers of 16-bit free-running timer ..................................................................................365
Figure 14.4-2
Registers of output compare ...............................................................................................366
Figure 14.4-3
Registers of 16-bit input capture .........................................................................................367
Figure 14.4-4
Registers of waveform generator ........................................................................................368
Figure 14.4.1-1 Compare clear buffer register (CPCLRB) ............................................................................369
Figure 14.4.1-2 Compare clear register (CPCLR) ........................................................................................369
Figure 14.4.2-1 Timer data register ..............................................................................................................370
Figure 14.4.3-1 Timer control status register (TCCSH) ................................................................................372
Figure 14.4.3-2 Timer control status register (TCCSL) .................................................................................374
Figure 14.4.4-1 Output compare buffer registers (OCCPB0 ~ 5) .................................................................376
Figure 14.4.4-2 Output compare registers (OCCP0 ~ 5) ..............................................................................377
Figure 14.4.5-1 Compare control register (OCS1/3/5) ..................................................................................378
Figure 14.4.5-2 Compare control register (OCS0/2/4) ..................................................................................381
Figure 14.4.6-1 Input capture data registers (IPCP0 ~ 3) .............................................................................383
Figure 14.4.7-1 Input capture control status register (ICSH23) ....................................................................384
Figure 14.4.7-2 Input capture control status register (ICSL23) .....................................................................386
Figure 14.4.7-3 PPG output control/input capture control status register (PICSH01) ..................................388
Figure 14.4.7-4 Input capture control status register (PICSL01) ..................................................................390
MB90820 series
xvii
Figure 14.4.8-1 16-bit timer registers (TMRR0/1/2) ..................................................................................... 392
Figure 14.4.9-1 16-bit timer control register (DTCR1) ................................................................................. 394
Figure 14.4.9-2 16-bit timer control register (DTCR1) ................................................................................. 396
Figure 14.4.10-1 Waveform control register (SIGCR) .................................................................................... 398
Figure 14.6.1-1 16-bit free-running timer clear timing .................................................................................. 405
Figure 14.6.1-2 Change timer mode while timer is operating ...................................................................... 406
Figure 14.6.1-3 Operation in up-count mode with compare clear buffer is disabled (TCCSL:BFE=0) ........ 406
Figure 14.6.1-4 Operation in up-count mode with compare clear buffer is enabled (TCCSL:BFE=1) ......... 407
Figure 14.6.1-5 Operation in up-down count mode with compare clear buffer enabled (TCCSL:BFE=1) ... 407
Figure 14.6.1-6 Interrupts generated in up-count mode (TCCSL:MODE=0) ............................................... 408
Figure 14.6.1-7 Interrupts generated in up-down count mode (TCCSL:MODE=1) ...................................... 408
Figure 14.6.1-8 Compare clear interrupt masked in up-count mode ........................................................... 409
Figure 14.6.1-9 Zero detect interupt masked in up-down count mode ........................................................ 409
Figure 14.6.1-10 16-bit free-running timer count timing ................................................................................. 410
Figure 14.6.2-1 Sample output waveform when compare registers 0 and 1 are used individually when the initial
output value is “0” (free-running timer in up-count mode). ................................................. 411
Figure 14.6.2-2 Sample output waveform when compare registers 0 and 1 are used individually when the initial
output value is “0” (free-running timer in up-down count mode). ........................................ 412
Figure 14.6.2-3 Sample output waveform when compare registers 0 and 1 are used in a pair when the initial
output value is “0” (free-running timer in up-count mode). ................................................. 412
Figure 14.6.2-4 Sample output waveform when compare register 0 and 1 are used in a pair when the initial
output value is “0” (free-running timer in up-down count mode). ........................................ 413
Figure 14.6.2-5 Sample output waveform when compare buffer is disabled (free-running timer in up-count
mode). ................................................................................................................................ 413
Figure 14.6.2-6 Sample output waveform when compare buffer is enable (free-running timer in up-down count
mode). ................................................................................................................................ 414
Figure 14.6.2-7 Compare operation upon update of compare registers ...................................................... 415
Figure 14.6.2-8 Compare interrupt timing .................................................................................................... 415
Figure 14.6.2-9 Output pin change timing .................................................................................................... 415
Figure 14.6.3-1 Sample input capture timing ............................................................................................... 416
Figure 14.6.3-2 16-bit input capture timing for input signals ........................................................................ 417
Figure 14.6.4-1 Generating GATE signal during RTx is at “H” level ............................................................ 420
Figure 14.6.4-2 Generating GATE signal from rising edge of RTx until 16-bit timer underflow ................... 421
Figure 14.6.4.1-1Waveform generated when TMD2~0=010B ....................................................................... 422
Figure 14.6.4.2-1Non-overlap signal generation by RT1/3/5 in normal polarity ............................................. 424
Figure 14.6.4.2-2Non-overlap signal generation by RT1/3/5 in inverted polarity ........................................... 425
Figure 14.6.4.2-3Non-overlap signal generation by PPG0 in normal polarity ................................................ 426
Figure 14.6.4.2-4Non-overlap signal generation by PPG0 in inverted polarity .............................................. 427
Figure 14.6.4.3-1Operation when DTTI input is enabled ............................................................................... 428
Figure 14.6.4.3-2DTTI interrupt timing ........................................................................................................... 429
xviii
MB90820 series
Figure 15.1-1
Block diagram of the delayed interrupt generator module ...................................................436
Figure 15.2-1
Delayed interrupt generator module register (DIRR) ...........................................................437
Figure 15.3-1
Operation of the delayed interrupt generator module ..........................................................438
Figure 16.2-1
Block diagram of the DTP/external interrupt circuit .............................................................444
Figure 16.3-1
Block diagram of the DTP/external interrupt circuit pins (INT0 ~ INT6) ..............................447
Figure 16.3-2
Block diagram of the DTP/external interrupt circuit pins (INT7) ..........................................447
Figure 16.4-1
DTP/external interrupt circuit registers ................................................................................448
Figure 16.4.1-1 DTP/interrupt cause register (EIRR) ...................................................................................449
Figure 16.4.2-1 DTP/interrupt enable register (ENIR) ..................................................................................450
Figure 16.4.3-1 Request level setting register (ELVR) .................................................................................452
Figure 16.5-1
DTP/external interrupt circuit ...............................................................................................454
Figure 16.5-2
Operation of the DTP/external interrupt circuit ....................................................................456
Figure 16.5.2-1 Example of interfacing to the external peripheral ................................................................459
Figure 16.6-1
Clearing the cause retention circuit when a level is specified .............................................460
Figure 16.6-2
DTP/external interrupt cause and interrupt request when the output
of interrupt requests is enabled ...........................................................................................460
Figure 17.2-1
..........................................................................................Block diagram of A/D converter 469
Figure 17.3-1
Registers for A/D Converter ................................................................................................470
Figure 17.3.1-1 A/D control status register (ADCS0) ....................................................................................472
Figure 17.3.2-1 A/D control status register (ADCS1) ....................................................................................474
Figure 17.3.3-1 Data register (IBCR) ............................................................................................................477
Figure 17.3.4-1 Setting register (ADSR) .......................................................................................................478
Figure 17.3.5-1 Analog Input Enable register (ADER) ..................................................................................480
Figure 17.5-1
Example of flow (continuous mode) from activation of A/D conversion
to transfer of converted data ...............................................................................................484
Figure 17.5.1-1 Example of starting of EI2OS in single mode .............................................................................. 487
Figure 17.5.2-1 Example of starting of EI2OS in continuous mode ..............................................................489
Figure 17.5.3-1 Example of starting of EI2OS in stop mode .........................................................................491
Figure 17.6-1
Example of flow of data protection function (when EI2OS is used) .....................................493
Figure 18.2-1
Block diagram of D/A converter ...........................................................................................497
Figure 18.3-1
Shows the block diagram of the D/A converter pins. ...........................................................498
Figure 18.4-1
D/A converter registers ........................................................................................................499
Figure 18.4.1-1 D/A converter register 1 (DAT1) ..........................................................................................500
Figure 18.4.2-1 D/A converter register 0 (DAT0) ..........................................................................................501
Figure 18.4.3-1 D/A control register 1 (DACR1) ...........................................................................................502
Figure 18.4.4-1 D/A control register 0 (DACR0) ...........................................................................................503
Figure 19.2-1
Block diagram of UART .......................................................................................................508
Figure 19.3-1
Block diagram of UART serial data input pin(P45) ..............................................................513
MB90820 series
xix
Figure 19.3-2
Block diagram of UART serial clock input/output pin(P43) & serial data output pin(P44) .. 513
Figure 19.3-3
Block diagram of UART serial data input pin(P72) ............................................................. 514
Figure 19.3-4
Block diagram of UART serial clock input/output pin(P74) & serial data output pin(P73) .. 514
Figure 19.4-1
UART registers ................................................................................................................... 515
Figure 19.4.1-1 Serial control register (SCR0/1) .......................................................................................... 516
Figure 19.4.2-1 Serial mode register (SMR0/1) ........................................................................................... 518
Figure 19.4.3-1 Serial status register (SSR0/1) ........................................................................................... 520
Figure 19.4.4-1 Input data register (SIDR0/1) .............................................................................................. 522
Figure 19.4.4-2 Output data register (SODR0/1) ......................................................................................... 522
Figure 19.4.5-1 Communication prescaler control register .......................................................................... 524
Figure 19.5.1-1 Reception operation and flag set timing ............................................................................. 528
Figure 19.5.2-1 Transmission operation and flag set timing ........................................................................ 529
Figure 19.6-1
Baud rate selection circuit .................................................................................................. 531
Figure 19.6.2-1 Baud rate selection circuit for the internal timer (16-bit reload timer 0) .............................. 536
Figure 19.6.3-1 Baud rate selection circuit for the external clock ................................................................ 538
Figure 19.7.1-1 Transfer data format (operation modes 0 and 1) ................................................................ 542
Figure 19.7.1-2 Transmission data when parity is enabled ......................................................................... 543
Figure 19.7.2-1 Transfer data format (operation mode 2) ............................................................................ 544
Figure 19.7.3-1 Settings for UART operation mode 0 .................................................................................. 546
Figure 19.7.3-2 Connection example of UART bidirectional communication ............................................... 546
Figure 19.7.3-3 Example of bidirectional communication flowchart ............................................................. 547
Figure 19.7.4-1 Settings for UART operation mode 1 .................................................................................. 548
Figure 19.7.4-2 Connection example of UART master-slave communication ............................................. 548
Figure 19.7.4-3 Master-slave communication flowchart .............................................................................. 550
Figure 20.2-1
Block diagram of ROM correction function ......................................................................... 559
Figure 20.3-1
Registers of ROM Correction Function ............................................................................... 560
Figure 20.3.1-1 Program address detection register .............................................................................. 561
Figure 20.3.2-1 Program address detection control status register ........................................................ 562
Figure 20.5-1
System configuration example ........................................................................................... 565
Figure 20.5-2
System configuration example ........................................................................................... 566
Figure 20.5-3
Flowchart of program patch processing ............................................................................. 567
Figure 21.1-1
ROM mirroring function selection module block diagram ................................................... 570
Figure 21.2-1
ROM mirroring function selection register .......................................................................... 571
Figure 21.2-2
Memory space .................................................................................................................... 572
Figure 22.2-1
512K Bit Flash Memory Sector Configuration .................................................................... 575
Figure 22.2-2
1024K Bit Flash Memory Sector Configuration .................................................................. 575
Figure 22.6.2-1 Example of Procedure of Writing the Data to the Flash Memory ....................................... 591
Figure 22.6.4-1 Example of Procedure of Deleting the Sector from the Flash Memory .............................. 595
xx
MB90820 series
Figure B.1-1
Control circuit ......................................................................................................................611
Figure B.2-1
Example of connection for serial writing in MB90F822/F823 internal vector mode (when power
supplied by user) .................................................................................................................612
Figure B.3-1
Example of connection for serial writing in MB90F822/F823 internal vector mode
(when power supplied from writer) .....................................................................................614
Figure B.4-1
Example of minimum connection with flash microcomputer programmer
(when power supplied by user) ..........................................................................................616
Figure B.5-1
Example of minimum connection with flash microcomputer programmer
(when power supplied from writer) ......................................................................................618
Figure C.3-1
Example of immediate addressing (#imm) ..........................................................................625
Figure C.3-2
Example of register direct addressing .................................................................................626
Figure C.3-3
Example of direct branch addressing (addr16) ...................................................................626
Figure C.3-4
Example of physical direct branch addressing (addr24) .....................................................627
Figure C.3-5
Example of I/O direct addressing (io) ..................................................................................627
Figure C.3-6
Example of condensed direct addressing (dir) ....................................................................627
Figure C.3-7
Example of direct addressing (addr16) ...............................................................................628
Figure C.3-8
Example of I/O direct bit addressing (io:bp) ........................................................................628
Figure C.3-9
Example of condensed direct bit addressing (dir:bp) ..........................................................629
Figure C.3-10
Example of direct bit addressing (addr16:bp) ......................................................................629
Figure C.3-11
Example of vector addressing (#vct) ...................................................................................629
Figure C.4-1
Example of register indirect addressing (@RWj j = 0 to 3) ................................................631
Figure C.4-2
Example of register indirect addressing with post-incrementing (@RWj+ j = 0 to 3) .........631
Figure C.4-3
Example of register indirect addressing with displacement (@RWi+disp8 i = 0 to 7,
@RWj+disp16 j = 0 to 3) ....................................................................................................632
Figure C.4-4
Example of long-word register indirect addressing with displacement(@RLi+disp8 i = 0 to 3)
632
Figure C.4-5
Example of program counter indirect addressing with displacement (@PC+disp16) .........633
Figure C.4-6
Example of register indirect addressing with base index (@RW0+RW7, @RW1+RW7) ....634
Figure C.4-7
Example of program counter relative branch addressing (rel) ............................................634
Figure C.4-8
Register list configuration ....................................................................................................635
Figure C.4-9
Example of register list (rlst) ................................................................................................635
Figure C.4-10
Example of accumulator indirect addressing (@A) .............................................................635
Figure C.4-11
Example of accumulator indirect branch addressing (@A) .................................................636
Figure C.4-12
Example of indirect designation branch addressing (@ear) ................................................636
Figure C.4-13
Example of indirect designation branch addressing (@eam) ..............................................637
Figure C.9-1
Configuration of instruction maps ........................................................................................659
Figure C.9-2
Relationship between actual instruction codes and instruction maps .................................660
MB90820 series
xxi
TABLES
Table 1.6-1
Pin Description (Continued) .................................................................................................. 16
Table 2.4.2-1
Access space and main function of each bank register ....................................................... 33
Table 2.4.2-2
Addressing and default spaces ............................................................................................ 34
Table 2.7-1
Initial values of the dedicated registers ................................................................................ 41
Table 2.7.2-1
Stack address specification .................................................................................................. 46
Table 2.7.6-1
Interrupt level mask register (ILM) and interrupt level priority .............................................. 52
Table 2.8-1
Typical functions of general-purpose registers ..................................................................... 57
Table 2.9.1-1
Bank select prefix codes and selected memory spaces ....................................................... 60
Table 2.9.1-2
Instructions not affected by bank select prefix codes ........................................................... 60
Table 2.9.1-3
Instructions whose use requires caution when bank select prefix
codes are used ..................................................................................................................... 61
Table 2.9.2-1
Instructions whose use requires caution when the common register bank prefix (CMR) is used
62
Table 2.9.3-1
Instructions whose use requires caution when the flag change suppression prefix (NCC) is
used ...................................................................................................................................... 63
Table 2.9.4-1
Prefix codes and interrupt/hold suppression instructions .................................................... 64
Table 3.1-1
Reset causes ........................................................................................................................ 68
Table 3.2-1
Reset causes and oscillation stabilization wait intervals ...................................................... 70
Table 3.5-1
Correspondence between reset cause bits and reset causes .............................................. 75
Table 4.3.1-1
Function description of each bit of the clock selection register (CKSCR) ............................ 85
Table 4.3.2-1
Function description of each bit of the PLL clock control register (PCKCR) ........................ 87
Table 5.3-1
Function description of each bit of the low power consumption mode control register (LPMCR)
99
Table 5.3-2
Instructions to be used for switching to low power consumption mode .............................. 100
Table 5.5-1
Operation statuses during standby mode ........................................................................... 102
Table 5.6-1
Low power consumption mode operating states ................................................................ 111
Table 5.6-2
Clock mode switching and release ..................................................................................... 111
Table 5.6-3
Switching to and release of standby mode ......................................................................... 112
Table 5.7-1
State of pins in single-chip mode ........................................................................................ 113
Table 6.2-1
Interrupt vectors .................................................................................................................. 120
Table 6.2-2
Interrupt causes, interrupt vectors, and interrupt control registers ..................................... 121
Table 6.3-1
Interrupt control registers .................................................................................................... 123
Table 6.3.2-1
Correspondence between the interrupt level setting bits and interrupt levels .................... 127
Table 6.3.2-2
Correspondence between the EI2OS channel selection bits and
descriptor addresses .......................................................................................................... 127
Table 6.3.2-3
Relationship between EI2OS status bits and the EI2OS status ......................................... 128
Table 6.4-1
xxiii
Mechanisms used for hardware interrupt .......................................................................... 131
MB90820series
Table 6.4-2
Hardware interrupt suppression instruction .........................................................................132
Table 6.4.5-1
Interpolation values (Z) for the interrupt handling time ........................................................141
Table 6.6.1-1
Correspondence between channel numbers and descriptor addresses .............................146
Table 6.6.5-2
Data transfer interpolation value for EI2OS execution time ................................................152
Table 6.6.5-3
Interpolation value (Z) for the interrupt handling time ..........................................................153
Table 7.2-1
Mode pin settings ................................................................................................................163
Table 7.3-1
Bus mode setting bits and functions ....................................................................................164
Table 7.3-2
Relationship between mode pins and mode data ...............................................................165
Table 8.1-1
Functions of individual port ..................................................................................................169
Table 8.2-1
Registers and corresponding port .......................................................................................170
Table 8.3-1
Port 0 pins ...........................................................................................................................172
Table 8.3-2
Port 0 pins and their corresponding register bits .................................................................174
Table 8.3.1-1
Port 0 register functions ......................................................................................................177
Table 8.3.2-1
States of port 0 pins ............................................................................................................179
Table 8.4-1
Port 1 pins ...........................................................................................................................180
Table 8.4-2
Port 1 pins and their corresponding register bits .................................................................182
Table 8.4.1-1
Port 1 register functions ......................................................................................................183
Table 8.4.2-1
States of port 1 pins ............................................................................................................185
Table 8.5-1
Port 2 pins ...........................................................................................................................186
Table 8.5-2
Port 2 pins and their corresponding register bits .................................................................188
Table 8.5.1-1
Port 2 register functions ......................................................................................................189
Table 8.5.2-1
States of port 2 pins ............................................................................................................191
Table 8.6-1
Port 3 pins ...........................................................................................................................192
Table 8.6.1-1
Port 3 register functions ......................................................................................................195
Table 8.6.2-1
States of port 3 pins ............................................................................................................197
Table 8.7-1
Port 4 pins ...........................................................................................................................198
Table 8.7-2
Port 4 pins and their corresponding register bits .................................................................200
Table 8.7.1-1
Port 4 register functions ......................................................................................................201
Table 8.7.2-1
States of port 4 pins ............................................................................................................203
Table 8.8-1
Port 5 pins ...........................................................................................................................204
Table 8.8-2
Port 3 pins and their corresponding register bits .................................................................206
Table 8.8.1-1
Port 5 register functions ......................................................................................................207
Table 8.8.2-1
States of port 5 pins ............................................................................................................209
Table 8.9-1
Port 6 pins ...........................................................................................................................210
Table 8.9-2
Port 6 pins and their corresponding register bits .................................................................211
Table 8.9.1-1
Port 6 register functions ......................................................................................................213
Table 8.9.2-1
States of port 6 pins ............................................................................................................215
Table 8.10-1
Port 7 pins ...........................................................................................................................216
MB90820series
xxiv
Table 8.10-2
Port 7 pins and their corresponding register bits ................................................................ 220
Table 8.10.1-1
Port 7 register functions ...................................................................................................... 223
Table 8.10.2-1
States of port 7 pins ............................................................................................................ 225
Table 8.11-1
Port 8 pins .......................................................................................................................... 226
Table 8.11-2
Port 8 pins and their corresponding register bits ................................................................ 228
Table 8.11.1-1
Port 8 register functions ...................................................................................................... 229
Table 8.11.2-1
States of port 8 pins ............................................................................................................ 231
Table 9.1-1
Intervals for the timebase timer .......................................................................................... 234
Table 9.1-2
Clock cycle time supplied from the timebase timer ............................................................ 235
Table 9.3-1
Function description of each bit in the timebase timer control register (TBTC) .................. 239
Table 9.4-1
Timebase interrupts and EI2OS ......................................................................................... 240
Table 9.5-1
Timebase timer counter clearing and oscillation settling times .......................................... 242
Table 10.1-1
Intervals for the watchdog timer ........................................................................................ 248
Table 10.3-1
Function description of each bit of the watchdog timer control register (WDTC) ............... 251
Table 11.1-1
Operation Modes of 16-bit Reload Timer ........................................................................ 258
Table 11.1-2
Interval Time of 16-bit Reload Timer ............................................................................... 259
Table 11.1-3
Interval Time of 16-bit Reload Timer .............................................................................. 259
Table 11.3-1
Pins of the 16-bit Reload Timer ...................................................................................... 263
Table 11.4.1-1
Function of the Upper Bits and Bit 7 of Timer Control Status Registers:
(TMCSRH0,
TMCSRH1) ......................................................................................................................... 267
Table 11.4.2-1
Function of the Lower Bits of the Timer Control Status Registers (TMCSRL0/1) ............... 269
Table 11.5-1
Interrupt Control Bits and Interrupt Sources of 16-bit Reload Timer .................................. 272
Table 11.5-2
Interrupts of 16-bit Reload Timer and EI2OS ..................................................................... 272
Table 12.3-1
16-bit PWC timer pins ......................................................................................................... 292
Table 12.4.1-1
PWC control status register (PWCSH0/1) .......................................................................... 297
Table 12.4.1-2
PWC control status register (PWCSL0/1) ........................................................................... 301
Table 12.4.3-1
Division rate control register (DIV0/1) ................................................................................. 303
Table 12.5-1
Interrupt control bits and interrupt causes of the PWC timer .............................................. 304
Table 12.5-2
16-bit PWC timer interrupts and EI²OS .............................................................................. 304
Table 12.6.1-1
Operation mode selection .................................................................................................. 310
Table 12.6.2-1
Pulse-width measurement operation (single measurement mode, H width measurement
mode) ................................................................................................................................. 311
Table 12.6.2-2
Functions of operation state indication bits ...................................................................... 312
Table 12.6.3-1
Count clock and period ..................................................................................................... 314
Table 12.6.4-1
Pulse width measurement range ...................................................................................... 319
Table 12.6.4-2
Measurement mode operation .......................................................................................... 320
Table 13.3-1
16-bit PPG timer pins ......................................................................................................... 332
Table 13.4.4-1
PPG control register (PCNTH0 ~ 2) bit ............................................................................... 341
xxv
MB90820series
Table 13.4.4-2
PPG control register (PCNTL0 ~ 2) .....................................................................................343
Table 13.5-1
Interrupt control bits and interrupt causes of the 16-bit PPG timer .....................................344
Table 13.5-2
16-bit PPG timer interrupts and EI2OS ...............................................................................345
Table 14.3-1
Multi-functional timer pins ....................................................................................................362
Table 14.4.3-1
Timer control status register (TCCSH) ................................................................................373
Table 14.4.3-2
Timer control status register (TCCSL) .................................................................................375
Table 14.4.5-1
Compare control register (OCS1/3/5) bit .............................................................................379
Table 14.4.5-2
Compare control register (OCS0/2/4) ..................................................................................381
Table 14.4.7-1
Input capture control status register (ICSH23) ....................................................................384
Table 14.4.7-2
Input capture control status register (ICSL23) .....................................................................387
Table 14.4.7-3
PPG output control/input capture control status register (PICSH01) ..................................389
Table 14.4.7-4
Input capture control status register (PICSL01) ..................................................................391
Table 14.4.9-1
16-bit timer control registers (DTCR0/2) bit .........................................................................395
Table 14.4.9-2
16-bit timer control registers (DTCR1) bit ............................................................................397
Table 14.4.10-1 Waveform control register (SIGCR) ....................................................................................399
Table 14.5-1
Interrupt control bits and interrupt causes of the 16-bit free-running timer ..........................400
Table 14.5-2
16-bit free-running timer interrupts and EI²OS ....................................................................400
Table 14.5-3
Interrupt control bits and interrupt causes of the 16-bit output compare 0~5 ......................401
Table 14.5-4
16-bit output compare interrupts and EI²OS ........................................................................401
Table 14.5-5
Interrupt control bits and interrupt causes of the 16-bit input capture 0~3 ..........................402
Table 14.5-6
16-bit input capture interrupts and EI²OS ............................................................................402
Table 14.5-7
Interrupt control bits and interrupt causes of the waveform generator ................................402
Table 14.5-8
Waveform generator interrupts and EI²OS ..........................................................................403
Table 14.6.4-1
Output condition of RTO0~5, GATE and register bit setting ...............................................418
Table 15.2-1
Delayed interrupt generator module register (DIRR) ...........................................................437
Table 16.1-1
Overview of the DTP/external interrupt circuit .....................................................................442
Table 16.1-2
Interrupt of the DTP/external interrupt circuit and EI²OS ....................................................443
Table 16.3-1
DTP/external interrupt circuit pins .......................................................................................446
Table 16.4.1-1
Function description of each bit of the DTP/interrupt cause register (EIRR) ...................449
Table 16.4.2-1
Function description of each bit of the DTP/interrupt enable register (ENIR) ....................450
Table 16.4.2-2
Correspondence between the DTP/interrupt control registers (EIRR, ENIR) and each channel
............................................................................................................................................451
Table 16.4.3-1
Function description of each bit of the request level setting register (ELVR) .....................452
Table 16.4.3-2
Correspondence between request level setting register (ELVR) and each channel ..........453
Table 16.5-1
Control bit and interrupt cause of the DTP/external interrupt circuit ...................................455
Table 17.1-1
Analog input pins .................................................................................................................467
Table 18.1-1
Theoretical values of output voltage of the D/A converter ...................................................496
Table 18.3-1
D/A converter pins ...............................................................................................................498
MB90820series
xxvi
Table 18.4.3-1
D/A control register 1 (DACR1) .......................................................................................... 502
Table 18.4.4-1
D/A control register 0 (DACR0) .......................................................................................... 503
Table 19.1-1
UART functions .................................................................................................................. 506
Table 19.1-2
UART operation mode ........................................................................................................ 507
Table 19.1-3
UART interrupt and EI²OS ................................................................................................. 507
Table 19.3-1
UART pins .......................................................................................................................... 512
Table 19.4.1-1
Serial control register (SCR0/1) .......................................................................................... 517
Table 19.4.2-1
Serial mode register (SMR0/1) ........................................................................................... 519
Table 19.4.3-1
Functions of each bit of status register (SSR0/1) ............................................................... 521
Table 19.4.5-1
Communication prescaler control register .......................................................................... 525
Table 19.5-1
Interrupt control bits and interrupt causes of UART ........................................................... 526
Table 19.5-2
UART interrupts and EI²OS ................................................................................................ 527
Table 19.6.1-1
Selection of each division ratio for the machine clock prescaler ........................................ 532
Table 19.6.1-2
Selection of synchronous baud rate division ratios ............................................................ 533
Table 19.6.1-3
Selection of asynchronous baud rate division ratios .......................................................... 533
Table 19.6.2-1
Baud rates and reload values ............................................................................................. 537
Table 19.7-1
UART operation mode ........................................................................................................ 540
Table 19.7.4-1
Selection of the master-slave communication function ...................................................... 549
Table 20.3.1-1
Correspondence between program address detection register and PACSR ..................... 561
Table 20.3.2-1
Program address detection control status register ............................................................. 563
Table 20.5-1
E2PROM memory map ...................................................................................................... 565
Table 21.2-1
ROM mirroring function selection register ......................................................................... 571
Table 22.4-1
Command Sequence Table ................................................................................................ 578
Table 22.5-1
Hardware Sequence Flag Bit Allocation ............................................................................. 580
Table 22.5-2
Hardware Sequence Flag Function List ............................................................................. 581
Table 22.5.1-1
Data Polling Flag Station Transition ................................................................................... 583
Table 22.5.2-1
Toggle Bit Flag Status Transition ....................................................................................... 584
Table 22.5.3-1
Transition of the Time Limit Exceeded Flag Status ............................................................ 585
Table 22.5.4-1
Sector Deletion Timer Flag Status Transition ..................................................................... 586
Table C.2-1
Effective-address field ........................................................................................................ 624
Table C.3-1
CALLV vectors .................................................................................................................... 630
Table C.5-1
Number of execution cycles for each type of addressing .................................................. 638
Table C.5-2
Number of execution cycles for each type of addressing (continued) ............................... 639
Table C.5-3
Compensation values for calculating the number of execution cycles ............................... 639
Table C.5-4
Compensation values for calculating number of cycles for program fetch ......................... 639
Table C.6-1
Effective-address field ........................................................................................................ 641
Table C.7-1
Items covered in instruction list ......................................................................................... 642
Table C.7-2
xxvii
Symbols used in the instruction list (continued) ................................................................. 643
MB90820series
Table C.7-3
Symbols used in the instruction list (continued) ..................................................................644
Table C.8-1
Transfer instructions (byte): 41 instructions .......................................................................645
Table C.8-2
Transfer instructions (word, long-word): 38 instructions ....................................................646
Table C.8-3
Addition/subtraction (byte, word, long-word): 42 instructions .............................................647
Table C.8-4
Increment/decrement (byte, word, long-word): 12 instructions .........................................648
Table C.8-5
Comparison (byte, word, long-word): 11 instructions] ........................................................648
Table C.8-6
Unsigned multiplication/division (word, long-word): 11 instructions] ..................................649
Table C.8-7
Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] ..650
Table C.8-8
Logical 1 (byte, word): 39 instructions] ...............................................................................651
Table C.8-9
Logical 2 (long-word): 6 instructions] ..................................................................................652
Table C.8-10
Sign inversion (byte, word): 6 instructions ..........................................................................652
Table C.8-11
Normalization (long-word): 1 instruction] ............................................................................652
Table C.8-12
Shift instructions (byte, word, long-word): 18 instructions] .................................................653
Table C.8-13
Branching instructions (1): 31 instructions .........................................................................654
Table C.8-14
Branch instructions (2): 19 instructions .............................................................................655
Table C.8-15
Other control instructions (byte, word, long-word): 28 instructions ....................................656
Table C.8-16
Bit operation instructions: 21 instructions ...........................................................................657
Table C.8-17
Accumulator operation instructions (byte, word): 6 instructions] ........................................657
Table C.9-1
Example instruction codes ..................................................................................................660
Table C.9-2
Basic page map ...................................................................................................................661
Table C.9-3
Bit operation instruction map (1st byte = 6CH) ....................................................................662
Table C.9-4
Character string operation instruction map (1st byte = 6EH) ..............................................663
Table C.9-5
2-byte instruction map (1st byte = 6FH) ..............................................................................664
Table C.9-6
ea instruction map (1) (1st byte = 70H) ...............................................................................665
Table C.9-7
ea instruction map (2) (1st byte = 71H) ...............................................................................666
Table C.9-8
ea instruction map (3) (1st byte = 72H) ...............................................................................667
Table C.9-9
ea instruction map (4) (1st byte = 73H) ...............................................................................668
Table C.9-10
ea instruction map (5) (1st byte = 74H) ...............................................................................669
Table C.9-11
ea instruction map (6) (1st byte = 75H) ...............................................................................670
Table C.9-12
ea instruction map (7) (1st byte = 76H) ...............................................................................671
Table C.9-13
ea instruction map (8) (1st byte = 77H) ...............................................................................672
Table C.9-14
ea instruction map (9) (1st byte = 78H) ...............................................................................673
Table C.9-15
MOVEA RWi,ea instruction map (1st byte = 79H) ...............................................................674
Table C.9-16
MOV Ri,ea instruction map (1st byte = 7AH) ......................................................................675
Table C.9-17
MOVW RWi,ea instruction map (1st byte = 7BH) ...............................................................676
Table C.9-18
MOV ea,Ri instruction map (1st byte = 7CH) ......................................................................677
Table C.9-19
MOVW ea,Rwi instruction map (1st byte = 7DH) ................................................................678
Table C.9-20
XCH Ri,ea instruction map (1st byte = 7EH) .......................................................................679
MB90820series
xxviii
Table C.9-21
xxix
XCHW RWi,ea instruction map (1st byte = 7FH) ................................................................ 680
MB90820series
CHAPTER 1
OVERVIEW
This chapter describes the main features and basic specifications of the MB90820
series.
1.1
MB90820 Series Features
1.2
MB90820 Series Product line-up
1.3
Block Diagram of MB90820 Series
1.4
Pin Assignment
1.5
Package Dimensions
1.6
I/O Pins and Pin Functions
1.7
I/O Circuit Types
1.8
Notes on Handling Devices
MB90820 series
1
1.1
MB90820 Series Features
The MB90820 series is a line of general-purpose, 16-bit microcontrollers designed for
those applications which require high-speed real-time processing, proving to be
suitable for various industrial machines and motor control (AC induction motor and
brushless DC motor). These microcontrollers consist of a multi-functional timer for AC/
DC motor control and a multi-pulse generator for DC motor control, which can
generate various type of waveform.
The instruction set is designed to be optimized for controller applications which
inheriting the AT architecture of F2MC-16LX series and allow a wide range of control
tasks to be processed efficiently at high speed.
■ MB90820 Series Features
● Clock
•
Embedded PLL clock multiplication circuit
•
Operating clock (PLL clock) can selected from divided-by-2 of oscillation, one to four times or
six times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz or 24MHz)
•
Minimum instruction execution time of 42 ns (at oscillation of 4 MHz, six times the PLL clock,
operation at Vcc of 5.0 V)
● CPU addressing space of 16 Mbytes
•
Internal 24-bit addressing
● Instruction set optimized for controller applications
•
Rich data types (bit, byte, word, long word)
•
Rich addressing mode (23 types)
•
High code efficiency
•
Enhanced precision calculation realized by the 32-bit accumulator
● Instruction set designed for high level language (C) and multi-task operations
•
Adoption of system stack pointer
•
Enhanced pointer indirect instructions
•
Barrel shift instructions
● Program patch function (2 address pointer)
● Improved execution speed
•
4-byte instruction queue
● Powerful interrupt function
2
•
Priority level programmable: 8 levels
•
32 factors of stronger interrupt function
MB90820 series
● Automatic data transmission function independent of CPU operation
•
Extended intelligent I/O service function (EI2OS)
•
Maximum 16 channels
● Low-power consumption (standby) mode
•
Sleep mode (mode in which CPU operating clock is stopped)
•
Timebase timer mode (mode in which other than oscillation and timebase timer are stopped)
•
Stop mode (mode in which oscillation is stopped)
•
CPU intermittent operation mode
● Package
•
LQFP-80 (FPT-80P-M05: 0.50 mm pitch)
•
LQFP-80 (FPT-80P-M11: 0.65 mm pitch)
•
QFP-80 (FPT-80P-M06: 0.80 mm pitch)
● Process
•
CMOS technology
■ Internal Peripheral Features
● I/O port
•
Maximum of 66 ports
● 18-bit timebase counter/watchdog timer: 1 channel
● Watchdog timer: 1 channel
● PWC: 2 channels
● 16-bit reload timer: 2 channels
● 16-bit PPG timer: 3 channels
● Multi-functional timer (for AC/DC motor control): 1 channel
•
16-bit free-running timer with up or up-down mode selection and buffer: 1 channel
•
16-bit output compare with buffer: 6 channels
•
16-bit input capture: 4 channels
•
16-bit PPG timer: 1 channel
•
Waveform generator (16-bit timer: 3 channels, 3-phase waveform or dead time)
● UART: 2 channels
•
With full-duplex double buffer (8-bit length)
•
Clock asynchronized or clock synchronized transmission (with start and stop bits) can be
selectively used
● DTP/External interrupt circuit: 8 channels
•
A module for starting extended intelligent I/O service (EI2OS) and generating an external
interrupt triggered by an external input
MB90820 series
3
● Delayed interrupt generation module
•
Generates an interrupt request for switching tasks
● 8/10-bit A/D converter: 16 channels
•
Selectable 8/10-bit resolution
● 8-bit D/A converter: 2 channels
4
MB90820 series
Memo
MB90820 series
5
1.2
MB90820 Series Product line-up
The MB90820 series contains 3 different devices. Table 1.2-1 lists the product line-up.
■ MB90820 Series Product Line-up
Table 1.2-1 MB90820 Series Product Line-up
Part number
MB90V820
MB90F822
MB90F823
MB90822
Item
Classification
Development /evaluation
product
ROM size
—
RAM size
16K Bytes
CPU function
I/O port
PWC
UART
16-bit reload
timer
16-bit PPG
timer
Mass-produced products
(Flash ROM with flash
security)
64K Bytes
Mass-produced product
(Mask ROM)
128K Bytes
64K Bytes
4K Bytes
Number of instruction
Minimum execution time
Addressing mode
Data bit length
Maximum memory space
: 351
: 42 ns / 4 MHz (PLL x 6)
: 23
: 1, 8, 16 bits
: 16 MBytes
I/O port (CMOS)
: 66
Pulse width counter timer
: 2 channels
Timer function (select the counter timer from three internal clocks)
Various pulse width measuring function (H pulse width, L pulse width, rising edge to falling edge
period, falling edge to rising edge period, rising edge to rising edge period and falling edge to
falling edge period)
UART
: 2 channels
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used
Transmission can be one-to-one (bidirectional commuication) or one-to-n (master-slave communication)
Reload timer
: 2 channels
Reload mode, single-shot mode or event count mode selectable
PPG timer
: 3 channels
PWM mode or single-shot mode selectable
Channel 0 can be worked with multi-functional timer or individually
16-bit free-running timer with up or up-down mode selection and buffer: 1 channel
Multi-functional
16-bit output compare
: 6 channels
timer
16-bit input capture
: 4 channels
(for AC/DC
16-bit PPG timer
: 1 channel
motor control)
Waveform generator (16-bit timer: 3 channels, 3-phase waveform or dead time)
8/10-bit A/D
converter
8-bit D/A
converter
6
8/10-bit resolution (16 channels)
Conversion time
: Min. 3 µs (24 MHz internal clock, including sampling time)
8-bit resolution (2 channels)
MB90820 series
Table 1.2-1 MB90820 Series Product Line-up
Part number
MB90V820
MB90F822
MB90F823
MB90822
Item
DTP/External
interrupt
8 independent channels
Selectable causes
Low-power
consumption
Stop mode / Sleep mode / CPU intermittent operation mode
Package
Power supply
voltage for
operation*
Process
MB90820 series
PGA299
: Rising edge, falling edge, “L” level or “H” level
LQFP-80 (FPT-80P-M05 : 0.50 mm pitch)
LQFP-80 (FPT-80P-M11 : 0.65 mm pitch)
QFP-80 (FPT-80P-M06 : 0.80 mm pitch)
3.5 V to 5.5 V : other than conditions listed below
4.0 V to 5.5 V : if A/D converter is used
4.5 V to 5.5 V : if D/A converter is used / writing to FLASH
4.5 V to 5.5 V*
CMOS
7
1.3
Block Diagram of MB90820 Series
■ MB90820 Series Block Diagram
X0
Clock control
circuit
X1
CPU
F2MC-16LX series core
Timebase timer
Reset circuit
(Watchdog timer)
RSTX
Other pins
Vss x 2, Vcc x 2, MD0-2, C
Delayed interrupt generator
7
Interrupt controller
P37/PPG0
16-bit PPG
(Ch0)
P51/INT7
6
8
P45/SIN0
P44/SOT0
P43/SCK0
DTP/External interrupt
16-bit input capture
(Ch0/1/2/3)
UART
(Ch0)
P72/SIN1/AN10
P73/SOT1/AN11
P74/SCK1/AN12
UART
(Ch1)
16-bit PPG
P40/PPG1
(Ch1)
16-bit PPG
P50/PPG2
(Ch2)
PWC
(Ch1)
P46/PWI1
P47/PWO1
P42/TO0
P41/TIN0
16-bit reload timer
(Ch0)
P21/TO1
P20/TIN1
16-bit reload timer
(Ch1)
4
4
16-bit free-running
timer
F2MC-16LX bus
P16/INT6 to
P11/INT1
P30 to P36
Multi-functional timer
P76/IN0/AN14
P77/IN1/AN15
P80/IN2
P81/IN3
P75/FRCK/AN13
P82/RTO0 (U)*
P83/RTO1 (X)*
P84/RTO2 (V)*
P85/RTO3 (Y)*
P86/RTO4 (W)*
P87/RTO5 (Z)*
16-bit output
compare
(Ch0~5)
Waveform
generator
P10/INT0/DTTI
P17
P06/PWI0*
P07/PWO0*
PWC
(Ch0)
6
CMOS I/O port 0, 1, 3, 7, 8
CMOS I/O port 6
A/D converter
16
(8/10 bit)
CMOS I/O port 1, 2, 4, 5, 7
RAM
P00 to P05*
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
AVR
AVCC
AVSS
ROM
8-bit D/A converter
ROM correction
ROM mirroring
P70/DA0/AN8
P71/DA1/AN9
CMOS I/O port 7
Note: P00 to P07, P10 to P17,P20 to P27 and P30 to P37: With selectable registers that can be used as input pull-up resistors.
*: High current drive pin.
Figure 1.3-1 MB90820 Series Overall Block Diagram
8
MB90820 series
Memo
MB90820 series
9
1.4
Pin Assignment
Figure 1.4-1 to Figure 1.4-2 show the pin assignment diagrams for the MB90820 series.
P76/IN0/AN14
P77/IN1/AN15
P80/IN2
P81/IN3
P82/RTO0(U)*
P83/RTO1(X)*
P84/RTO2(V)*
P85/RTO3(Y)*
P86/RTO4(W)*
P87/RTO5(Z)*
P72/SIN1/AN10
P73/SOT1/AN11
P74/SCK1/AN12
P75/FRCK/AN13
P71/DA1/AN9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
P70/DA0/AN8
■ FPT-80P-M06 Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
QFP-80
(TOP VIEW)
(FPT-80P-M06)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
C
Vss
Vcc
P00*
P01*
P02*
P03*
P04*
P05*
P06/PWI0*
P07/PWO0*
P10/INT0/DTTI
P11/INT1
P12/INT2
P13/INT3
P14/INT4
P15/INT5
P16/INT6
P17
P20/TIN1
P21/TO1
P22
Vcc
P23
MD0
MD1
MD2
P40/PPG1
P37/PPG0
P36
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AVR
AVcc
AVss
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P51/INT7
P50/PPG2
P47/PWO1
P46/PWI1
P45/SIN0
P44/SOT0
P43/SCK0
RST
P42/TO0
P41/TIN0
Vss
X0
X1
*:High current pin
Figure 1.4-1 FPT-64P-M06 Pin Assignment
10
MB90820 series
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P76/IN0/AN14
P77/IN1/AN15
P80/IN2
P81/IN3
P82/RTO0(U)*
P83/RTO1(X)*
P84/RTO2(V)*
P85/RTO3(Y)*
P86/RTO4(W)*
P87/RTO5(Z)*
C
Vss
P72/SIN1/AN10
P73/SOT1/AN11
P74/SCK1/AN12
P75/FRCK/AN13
P71/DA1/AN9
P70/DA0/AN8
LQFP-80
(TOP VIEW)
(FPT-80P-M05)
(FPT-80P-M11)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
Vcc
P00*
P01*
P02*
P03*
P04*
P05*
P06/PWI0*
P07/PWO0*
P10/INT0/DTTI
P11/INT1
P12/INT2
P13/INT3
P14/INT4
P15/INT5
P16/INT6
P17
P20/TIN1
P21/TO1
P22
X0
X1
MD0
MD1
MD2
P40/PPG1
P37/PPG0
P36
P35
P34
P33
P32
P31
P30
P27
P26
P25
P24
P23
Vcc
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
AVss
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P51/INT7
P50/PPG2
P47/PWO1
P46/PWI1
P45/SIN0
P44/SOT0
P43/SCK0
RST
P42/TO0
P41/TIN0
Vss
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
AVcc
AVR
■ FPT-80P-M05/FPT-80P-M11 Pin Assignment
*:High current pin
Figure 1.4-2 FPT-80P-M05/FPT-80P-M11 Pin Assignment
MB90820 series
11
1.5
Package Dimensions
Three types of packages are available for MB90820 series.
Figure 1.5-1 to Figure 1.5-3 show the package dimensions.
■ FPT-80P-M05 Package Dimensions
Lead pitch
Plastic, LQFP, 80-pin
0.50mm
Package width
x length
12 x 12 mm
Lead shape
Gullwing
Sealing method
Plastic mould
Mounting height
1.70 mm MAX
0.47g
Weight
(FPT-80P-M05)
Note: Pins width and pins thickness include plating thickness
80-pin Plastic LQFP
(FPT-80P-M05)
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
60
0.145±0.055
(.006±.002)
41
40
61
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
.059 –.004
INDEX
0°~8°
0.10±0.10
(.004±.004)
(Stand off)
21
80
"A"
LEAD No.
1
20
0.50(.020)
C
(Mounting height)
0.20±0.05
(.008±.002)
0.08(.003)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
M
2000 FUJITSU LIMITED F80008S-c-3-7
© 2000 FUJITSU LIMITED F80008S-c-3-7
Dimensions mm (inches)
Figure 1.5-1 FPT-80P-M05 Package Dimensions
12
MB90820 series
■ FPT-80P-M06 Package Dimensions
0.80 mm
Lead pitch
80-pin Plastic QFP
Package width
× length
14 × 20 mm
Lead shape
Gull-wing
Sealing method
Plastic mould
Mounting height
3.35 mm MAX
(FPT-80P-M06)
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
64
41
40
65
0.10(.004)
17.90±0.40
(.705±.016)
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
25
80
0.25(.010)
+0.30
3.05 –0.20
+.012
.120 –.008
(Mounting height)
1
24
0.80(.031)
0.37±0.05
(.015±.002)
0.20(.008)
0~8°
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
"A"
C
+0.10
0.30 –0.25
+.004
.012 –.010
(Stand off)
2001 FUJITSU LIMITED F80010S-c-4-4
Figure 1.5-2 FPT-80P-M06 Package Dimensions
MB90820 series
13
■ FPT-80P-M11 Package Dimensions
0.65 mm
Lead pitch
80-pin Plastic SQFP
Package width
× length
14 × 14 mm
Lead shape
Gull-wing
Sealing method
Plastic mould
Mounting height
1.70 mm MAX
Weight
0.65g
(FPT-80P-M11)
80-pin Plastic SQFP
(FPT-80P-M11)
Note: Pins width and pins thickness include plating thickness
+0.20
16.00±0.20(.630±.008)SQ
1.50 –0.10
+.008
14.00±0.10(.551±.004)SQ
60
.059 –.004
41
61
(Mounting height)
40
12.35
(.486)
REF
15.00
(.591)
NOM
1 PIN INDEX
80
LEAD No.
21
1
0.65(.0256)TYP
Details of "A" part
"A"
0.30±0.10
(.012±.004)
20
0.13(.005)
M
+.002
.005 –.001
0.10(.004)
C
0.10±0.10
(STAND OFF)
(.004±.004)
+0.05
0.127 –0.02
0
10°
0.50±0.20
(.020±.008)
2000 FUJITSU LIMITED F80016S-1C-4
Figure 1.5-3 FPT-80P-M11 Package Dimensions
14
MB90820 series
1.6
I/O Pins and Pin Functions
Table 1.6-1 lists the MB90820 series I/O pins and their functions. Table 1.7-1 lists the
I/O circuit types.
The letter in the “I/O circuit type” column in Table 1.6-1 refers to the letter in the “Type”
column Table 1.7-1.
■ I/O Pins and Pin Functions
Table 1.6-1 Pin Description
Pin no.
Pin name
I/O circuit
Pin status
during
reset
Function
LQFP*1
QFP*2
21,22
23,24
X0,X1
A
Oscillating Oscillation input pins.
17
19
RST
B
Reset input External reset input pin.
59~54
61~56
P00 ~ P05
C
53
55
General-purpose I/O ports.
P06
General-purpose I/O ports.
C
PWC 0 signal input pin.
PWI0
P07
52
54
General-purpose I/O ports.
C
PWO0
PWC 0 signal output pin.
P10
51
53
INT0
General-purpose I/O ports.
Can be used as interrupt request input channel 0. Input is
enabled when 1 is set in EN0 in standby mode.
D
RTO0~5 pins for fixed-level input. This function is enabled
when the waveform generator enables its input bits.
DTTI
P11~P16
50~45
52~47
General-purpose I/O ports.
D
Can be used as interrupt request input channels 1 to 6. Input
is enabled when 1 is set in EN1 to EN6 in standby mode.
INT1~INT6
44
46
43
45
P17
D
P20
General-purpose I/O ports.
External clock input pin for reload timer 1.
P21
44
General-purpose I/O ports.
D
TO1
41, 39~35
43, 41~37
34~28
36~30
Event output pin for reload timer 1.
P22~P27
D
General-purpose I/O ports.
P30~P36
E
General-purpose I/O ports.
P37
27
29
General-purpose I/O ports.
E
PPG0
P40
26
28
Output pins for PPG channel 0. This function is enabled
when PPG channel 0 enables output.
General-purpose I/O ports.
F
PPG1
MB90820 series
General-purpose I/O ports.
D
TIN1
42
Port input
Output pins for PPG channel 1. This function is enabled
when PPG channel 1 enables output.
15
Table 1.6-1 Pin Description (Continued)
Pin no.
Pin name
LQFP*1
QFP*2
19
21
I/O circuit
Pin status
during
reset
P41
General-purpose I/O ports.
F
TIN0
External clock input pin for reload timer 0.
P42
18
20
General-purpose I/O ports.
F
TO0
Event output pin for reload timer 0.
P43
16
18
General-purpose I/O ports.
F
Serial clock I/O pin for UART channel 0. This function is enabled when UART channel 0 enables clock output.
SCK0
P44
15
17
General-purpose I/O ports.
F
Serial data output pin for UART channel 0. This function is
enabled when UART channel 0 enables data output.
SOT0
P45
14
16
General-purpose I/O ports.
G
Port Input Serial data input pin for UART channel 0. While UART channel 0 is operating for input, the input of this pin is used as
required and must not be used for any other input.
CMOS input can be selected by user program.
SIN0
P46
13
15
General-purpose I/O ports.
F
PWI1
PWC 1 signal input pin.
P47
12
14
General-purpose I/O ports.
F
PWO1
PWC 1 signal output pin.
P50
11
13
General-purpose I/O ports.
F
Output pins for PPG channel 2. This function is enabled
when PPG channel 2 enables output.
PPG2
P51
10
12
General-purpose I/O ports.
F
Usable as interrupt request input channel 7. Input is enabled when 1 is set in EN7 in standby mode.
INT7
P60~P67
9~2
78~77
11~4
80~79
General-purpose I/O ports.
H
AN0~AN7
A/D converter analog input pins. This function is enabled
when the analog input is enabled (ADER0).
P70~P71
General-purpose I/O ports.
DA0~DA1
D/A converter analog output pins. This function is enabled
when D/A converter is enabled.
I
A/D converter analog input pins. This function is enabled
when the analog input is enabled (ADER1).
AN8~AN9
P72
76
78
SIN1
Analog
input
J
P73
77
SOT1
AN11
16
General-purpose I/O ports.
Serial data input pin for UART channel 1. While UART channel 1 is operating for input, the input of this pin is used as
required and must not be used for any other input.
CMOS input can be selected by user program.
A/D converter analog input pins. This function is enabled
when the analog input is enabled (ADER1).
AN10
75
Function
General-purpose I/O ports.
K
Serial data output pin for UART channel 1. This function is
enabled when UART channel 1 enables data output.
A/D converter analog input pins. This function is enabled
when the analog input is enabled (ADER1).
MB90820 series
Table 1.6-1 Pin Description (Continued)
Pin no.
Pin name
LQFP*1
I/O circuit
QFP*2
Pin status
during
reset
P74
74
76
SCK1
General-purpose I/O ports.
Serial clock I/O pin for UART channel 1. This function is enabled when UART channel 1 enables clock output.
K
A/D converter analog input pins. This function is enabled
when the analog input is enabled (ADER1).
AN12
P75
73
75
FRCK
General-purpose I/O ports.
K
AN13
Analog
input
P76~P77
72~71
74~73
IN0~IN1
A/D converter analog input pins. This function is enabled
when the analog input is enabled (ADER1).
General-purpose I/O ports.
F
IN2~IN3
Port input
P82~P87
68~63
70~65
RTO0
~RTO5
23
25
MD0
26, 27
MD1, MD2
80
2
AVCC
Trigger input pins for input capture channels 2 to 3.
When input capture channels 2 to 3 are used for input operation, these pins are enabled as required and must not be
used for any other I/P.
General-purpose I/O ports.
L
M
24, 25
A/D converter analog input pins. This function is enabled
when the analog input is enabled (ADER1).
Trigger input pins for input capture channels 0 to 1.
When input capture channels 0 to 1 are used for input operation, these pins are enabled as required and must not be
used for any other I/P.
K
P80~P81
72~71
External clock input pin for free-running timer.
General-purpose I/O ports.
AN14~AN15
70~69
Function
Waveform generator output pins. These pins output the
waveforms specified at the waveform generator. Output is
generated when waveform generator output is enabled.
Mode
input
–
Input pin for operation mode specification. Connect this pin
directly to Vcc or Vss.
Input pins for operation mode specification. Connect these
pins directly to Vcc or Vss.
Vcc power input pin for analog circuits.
Power
input
79
1
AVR
–
1
3
AVSS
–
20, 61
22, 63
Vss
–
40, 60
42, 62
Vcc
–
Power
input
62
64
C
–
–
Vref+ input pin for the A/D converter. This voltage must not
exceed AVcc. Vref- is fixed to AVss.
Vss power input pin for analog circuits.
Power (0 V) input pin.
Power (5 V) input pin.
Capacity pin for power stabilization. Please connect to an
approximately 0.1 µF ceramic capacitor.
*1: FPT-80P-M05, FPT-80P-M11
*2: FPT-80P-M06
MB90820 series
17
1.7
I/O Circuit Types
Table 1.7-1 summarize the I/O circuit types of MB90820 series
■ I/O Circuit Types
Table 1.7-1 I/O Circuit Type
Classification
Type
Remarks
X1
Xout
N-ch P-ch
A
P-ch
X0
N-ch
Main clock (main clock crystal
oscillator)
• At an oscillation feedback
resistor of approximately 1
MΩ
Standby mode control
B
• Hysteresis input
• Resistor approximately 50 kΩ
R
R
P-ch
Pull-up control
P-ch
Pout
C
Nout
N-ch
• CMOS output
• Hysteresis input
• Selectable pull-up resistor
approximately 50 kΩ
• IOL = 12 mA
Hysteresis input
Standby mode control
R
P-ch
Pull-up control
P-ch
D
N-ch
Pout
Nout
• CMOS output
• Hysteresis input
• Selectable pull-up resistor
approximately 50 kΩ
• IOL = 4 mA
Hysteresis input
Standby mode control
18
MB90820 series
Table 1.7-1 I/O Circuit Type (Continued)
Classification
Type
R
P-ch
Remarks
Pull-up control
P-ch
E
N-ch
Pout
Nout
• CMOS output
• CMOS input
• Selectable pull-up resistor
approximately 50 kΩ
• IOL = 4 mA
CMOS input
Standby mode control
P-ch
F
N-ch
Pout
Nout
•
•
•
CMOS output
Hysteresis input
IOL = 4 mA
Hysteresis input
Standby mode control
P-ch
N-ch
Pout
Nout
Hysteresis input
G
CMOS input
• CMOS output
• Hysteresis input
• CMOS input(selectable for
UART 0 data input pin)
• IOL = 4 mA
Standby mode control
P-ch
H
N-ch
Pout
Nout
CMOS input
•
•
•
•
CMOS output
CMOS input
Analog input
IOL = 4 mA
Analog input control
Analog input
MB90820 series
19
Table 1.7-1 I/O Circuit Type (Continued)
Classification
Type
P-ch
Remarks
Pout
Nout
N-ch
I
CMOS input
Analog I/O control
•
•
•
•
•
CMOS output
CMOS input
Analog output
Analog input
IOL = 4 mA
Analog output
Analog input
P-ch
N-ch
Pout
Nout
Hysteresis input
J
CMOS input
• CMOS output
• Hysteresis input
• CMOS input (selectable for
UART1 data input pin)
• IOL = 4 mA
Analog input control
Analog input
P-ch
N-ch
Pout
Nout
K
CMOS input
•
•
•
•
CMOS output
Hysteresis input
Analog input
IOL= 4 mA
Analog input control
Analog input
P-ch
N-ch
Pout
Nout
L
Hysteresis input
• CMOS output
• Hysteresis input
• IOL= 12 mA
Standby mode control
M
20
• Hysteresis input
MB90820 series
Memo
MB90820 series
21
1.8
Notes on Handling Devices
When handling devices, pay special attention to the following eight items or
procedures:
• Strict observation of maximum rated voltage (latch-up prevention)
• Stabilization of supply voltage
• Power-on
• Treatment of unused input pins
• Treatment of A/D converter and D/A converter pins
• External clock
• Power supply pin
• Analog power-on sequence of A/D converter and D/A converter
■ Notes on handling devices
●
Be sure that the maximum rated voltage is not exceeded (latch-up prevention)
A latch-up may occur on a CMOS IC if a voltage higher than Vcc or lower than Vss is applied
to an input or output pin other than medium-to-high voltage pins. A latch-up may also occur if
a voltage higher than the rating is applied between Vcc and Vss. A latch-up causes a rapid
increase in the power supply current, which can result in thermal damage to an element.
Take utmost care that the maximum rated voltage is not exceeded.
When turning the power on or off to analog circuits, be sure that the analog supply voltages
(AVcc and AVR) and analog input voltage do not exceed the digital supply voltage (Vcc).
●
Stabilize the supply voltages
Even within the operation guarantee range of the Vcc supply voltage, a malfunction can be
caused if the supply voltage undergoes a rapid change. For voltage stabilization guidelines,
the Vcc ripple fluctuations (P-P value) at commercial frequencies (50 to 60 Hz) should be
suppressed to "10%" or less of the reference Vcc value. During a momentary change such
as when switching a supply voltage, voltage fluctuations should also be suppressed so that
the "transient fluctuation rate" is 0.1 V/ms or less.
●
Power-on
To prevent a malfunction in the built-in voltage drop circuit, secure "50 µs (between 0.2 V and
2.7 V)" or more for the voltage rise time during power-on.
●
Treatment of unused input pins
An unused input pin may cause a malfunction if it is left open. Every unused input pin should
be pulled up or down.
●
Treatment of A/D converter and D/A converter power pins
When the A/D converter and D/A converter are not used, connect the pins as follows: AVcc
= Vcc, AVss = AVR = Vss.
22
MB90820 series
●
Notes on external clock
When an external clock is used, the oscillation stabilization wait time is required at power-on
reset or at cancellation of sub-clock mode or stop mode. As shown in Figure 1.8-1, when an
external clock is used, connect only the X0 pin and leave the X1 pin open.
X0
MB90820 series
Open
X1
Figure 1.8-1 Sample application of external clock
●
Power supply pins
When a device has two or more Vcc or Vss pins, the pins that should have equal potential
are connected within the device in order to prevent a latch-up or other malfunction. To
reduce extraneous emission, to prevent a malfunction of the strobe signal due to an increase
in the group level, and to maintain the local output current rating, connect all these power
supply pins to an external power supply and ground them.
The current source should be connected to the Vcc and Vss pins of the device with minimum
impedance. It is recommended that a bypass capacitor of about 0.1 µF be connected near
the terminals between Vcc and Vss.
●
Analog power-on sequence of A/D converter and D/A converter
The power to the A/D converter and D/A converter(AVcc, AVR) and analog inputs (AN0 ~
AN15) must be turned on after the power to the digital circuits (Vcc) is turned on. When
turning off the power, turn off the power to the digital circuits (Vcc) after turning off the power
to the A/D converter, D/A converter and analog inputs. When the power is turned on or off,
AVR should not exceed AVcc. Also, when a pin that is used for A/D analog input is also used
as an input port, the input voltage should not exceed AVcc. (The power to the analog circuits
and the power to the digital circuits can be simultaneously turned on or off.)
MB90820 series
23
24
MB90820 series
CHAPTER 2
CPU
This chapter describes memory space for the MB90820 series.
2.1 CPU
2.2 Memory Space
2.3 Memory Maps
2.4 Addressing
2.5 Memory Location of Multibyte Data
2.6 Registers
2.7 Dedicated Registers
2.8 General-purpose Registers
2.9 Prefix Codes
MB90820 series
25
2.1
CPU
The F²MC-16LX CPU is a 16-bit CPU designed for use in applications, such as welfare
and mobile equipment, which require high-speed real-time processing. The instruction
set of the F²MC-16LX was designed for controllers so that it can perform various types
of control at high speed and efficiency.
The F²MC-16LX CPU process not only 16-bit data but also 32-bit data using a built-in
32-bit accumulator. Memory space, which can be extended up to 16M bytes, can be
accessed in either linear or bank access mode. The instruction set inherits the AT
architecture of F²MC-8L, and has additional instructions supporting high-level
languages. In addition, it has an extended addressing mode, enhanced multiply/divide
instructions and reinforced bit manipulation instructions. The features of the F²MC16LX CPU are shown below:
■ CPU
●
Minimum instruction execution time: 42 ns (when the source oscillation is 4 MHz and the
PLL clock is multiplied by 6)
●
Maximum memory address space: 16M bytes. Access in linear or bank addressing mode
●
Instruction set optimum for controller applications
Many data types (bit, byte, word and long word)
As many as 23 addressing modes
Enhanced high-precision arithmetic operation by a 32-bit accumulator
Enhanced signed multiply/divide instructions and RETI instruction function
●
Enhanced interrupt function
Eight programmable priority levels
●
Automatic transfer function independent of CPU
Extended intelligent I/O service using up to 16 channels
●
Instruction set supporting high-level language (C) and multitasking
System stack pointer, instruction set symmetry and barrel shift instructions
●
Increased execution speed: 4-byte instruction queue
<Check>
The MB90820 series runs only in single-chip mode so only internal ROM and RAM and
internal peripheral address space can be accessed.
26
MB90820 series
Memo
MB90820 series
27
2.2
Memory Space
All I/O, programs and data are located in the 16-megabyte memory space of the F2MC16LX. A part of the memory space is used for special purposes, such as extended
intelligent I/O service (EI²OS) descriptors, general-purpose registers and vector tables.
■ Memory space
All I/O, programs, and data are located in the 16-megabyte memory space of the F2MC-16LX
CPU. The CPU is able to access each resource through an address indicated by the 24-bit
address bus.
Figure 2.2-1 shows a sample relationship between the F2MC-16LX system and the memory map.
FFFFFFH
Programs
Vector table area
ROM
area
FFFC00H
*1
FF0000H
Program area
Data
F2MC-16LX
CPU
Internal bus
010000H
008000H
EI2OS
Peripheral circuits
Interrupts
ROM area
(FF bank image)
004000H
*2
001100 H
Data area
000380H
General-purpose
register
000180H
2
EI OS descriptor area
000100H
RAM
area
External area*3
Peripheral circuits
General-purpose
ports
F2MC-16LX device
0000F0H
0000C0H
0000B0H
000000H
peripheral function
control register
Interrupt controller
I/O port and
peripheral function
control register
I/O
area
*1: The size of internal ROM differs for each model.
*2: The size of internal RAM differs for each model.
*3: There is no access in single-chip mode.
Figure 2.2-1 Sample relationship between the F2MC-16LX system and the memory map
28
MB90820 series
■ ROM area
● Vector table area (address: FFFC00H to FFFFFFH)
•
This area is used as a vector table for vector call instructions, interrupt vectors and reset
vectors.
•
This area is allocated at the highest addresses of the ROM area. The start address of the
corresponding processing routine is set as data in each vector table address.
● Program area (address: up to FFFBFFH)
•
ROM is built in as an internal program area.
•
The size of internal ROM differs for each model.
■ RAM area
● Data area (address: from 000100H)
•
The static RAM is built in as an internal data area.
•
The size of internal RAM differs for each model.
● General-purpose register area (address: 000180H to 00037FH)
•
Auxiliary registers used for 8-bit, 16-bit and 32-bit arithmetic operations and transfer are
allocated in this area.
•
Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM.
•
When this area is used as a general-purpose register, general-purpose register addressing
enables high-speed access with short instructions.
● Extended intelligent I/O service (EI²OS) descriptor area (address: 000100H to 00017FH)
•
This area retains the transfer modes, I/O addresses, transfer count and buffer addresses.
•
Since this area is allocated to a part of the RAM area, it can be used as ordinary RAM.
■ I/O area
● Interrupt control register area (address: 0000B0H to 0000BFH)
The interrupt control registers (ICR00 to ICR15) correspond to all peripheral functions that have an interrupt
function. These registers set interrupt levels and control the extended intelligent I/O service (EI²OS).
● Peripheral function control register area (address: 000020H to 0000AFH, 0000C0H to
0000EFH)
This register controls the built-in peripheral functions, inputs and outputs data. Instruction using I/O
addressing e.g. MOV A, io, is not supported for registers area 003FE0H to 003FFFH
● I/O port control register area (address: 000000H to 00001FH)
This register controls I/O ports, inputs and outputs data.
MB90820 series
29
2.3
Memory Maps
This section shows the memory map for each MB90820 series model.
■ Memory maps
Figure 2.3-1 shows the memory maps for the MB90820series.
Single-chip mode
(with ROM mirroring function)
FFFFFFH
ROM area
Address #1
010000H
ROM area
(FF bank image)
Address #2
004000H
Address #3
RAM
area
Register
: Internal access memory
000100H
: Access not allowed
0000F0H
Peripheral area
000000H
Model
Address #1
Address #2
Address #3
MB90822
FF0000H
008000H
001100H
MB90F822
FF0000H
008000H
001100H
MB90F823
FE0000H
008000H
001100H
MB90V820
FE0000H
*1
008000H
*1
004100H
*1: The MB90V820 does not contain ROM. Assume that the development tool uses these area
for its ROM decode areas.
Figure 2.3-1 Memory maps
Notes:
30
•
If single-chip mode (without ROM mirroring function) is selected, see Chapter 21, "ROM
Mirroring Function Selection Module".
•
ROM data in the FF bank can be seen as an image in the higher 00 bank to validate the small
model C compiler. Because addresses of the 16 low order bits in the FF bank are the same, the
table in ROM can be referenced without the "far" specification. For example, when 00C000H is
accessed, the contents of ROM at FFC000H are actually accessed. The ROM area in the FF
bank exceeds 32 kilobytes, and all areas cannot be seen as images in the 00 bank. Because
ROM data from FF8000H to FFFFFFH is seen as an image at 008000H to 00FFFFH, the ROM
data table should be stored in the area from FF8000H to FFFFFFH.
MB90820 series
2.4
Addressing
The methods for generating addresses are linear addressing and bank addressing.
In linear addressing, the complete 24-bit address is specified directly by an instruction.
In bank addressing, the upper 8 bits of the address are specified by a bank register for
the required purpose, and the lower 16 bits of the address are specified by the
instruction.
The F2MC-16LX series generally uses bank addressing.
■ Linear addressing and bank addressing
In linear addressing, the 16-megabyte space is accessed as consecutive address spaces. In
bank addressing, the 16-megabyte space is divided into and managed as 256 64-kilobyte banks.
Figure 2.4-1 is an overview of linear addressing and bank addressing memory management.
Linear addressing
Bank addressing
FF bank
64 kilobytes
FE bank
FD bank
12 bank
04 bank
03 bank
02 bank
01 bank
00 bank
Specified entirely by an instruction
Specified by an instruction
Specified by a bank register for the required purpose
Figure 2.4-1 Linear addressing and bank addressing memory management
MB90820 series
31
2.4
Addressing
2.4.1
Address specification by linear addressing
The two types of address specification by linear addressing are specification of a 24-bit
address directly in the operand and specification of the lower 24 bits of a 32-bit
general-purpose register.
■ Linear addressing by 24-bit operand specification
JMPP 123456H
Old program counter
+ program bank
New program counter
+ program bank
17
12
17452DH
JMPP 123456H
123456H
Next instruction
452D
3456
Figure 2.4.1-1 Example of direct specification of a 24-bit physical address in linear addressing
■ Addressing by indirect specification with a 32-bit register
MOV A,@RL1+7
Old AL
090700H
XXXX
3AH
+7
New AL
003A
RL1
240906F9H
(Upper 8 bits are ignored)
RL1: 32-bit (long-word) general-purpose register
Figure 2.4.1-2 Example of indirect specification with a 32-bit general-purpose register
in linear addressing
32
MB90820 series
2.4
Addressing
2.4.2
Address specification by bank addressing
In address specification by bank addressing, the 16-megabyte memory space is
divided into 256 64-kilobyte banks. A bank address that corresponds to each space is
specified in the bank register to determine the upper 8 bits of the address. The lower
16 bits of the address are specified by the instruction.
The five types of bank registers classified by function are as follows:
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional bank register (ADB)
■ Bank registers and access space
Table 2.4.2-1 lists the access space and main function of each bank register.
Table 2.4.2-1 Access space and main function of each bank register
Bank register
name
Program bank
register (PCB)
Data bank
register (DTB)
User stack bank
register (USB)
System stack
bank register
(SSB) *1
Additional bank
register (ADB)
Access
space
Main function
Program Instruction codes, vector tables and immediate-value data
(PC) space are stored.
Data (DT)
space
Read/write data is stored. Internal or external peripheral
control registers and data registers are accessed.
Stack (SP)
space
This area is used for stack accesses such as when PUSH/
POP instructions and interrupt registers are saved. The
SSB is used when the stack flag in the condition register
(CCR: S) is 1. The USB is used when the stack flag in the
condition register (CCR: S) is 0. *1
Additional
(AD) space
Data that overflows from the data (DT) space is stored.
Initial value
after a reset
FFH
00H
00H
00H
00H
*1: The SSB is always used as an interrupt stack.
MB90820 series
33
Figure 2.4.2-1 shows the relationship between the memory space divisions and each register.
See Section 2.7.9, "Bank registers (PCB, DTB, USB, SSB, ADB)", for details.
FFFFFFH
Program space
FF0000H
Physical address
0FFFFFH
: ADB (Additional Bank Register)
0DH
: USB (User Stack Bank Register)
0BH
: DTB (Data Bank Register)
07H
: SSB (System Stack Bank Register)
Data space
0B0000H
7FFFFFH
0FH
User stack space
0D0000H
0BFFFFH
: PCB (Program Bank Register)
Additional space
0F0000H
0DFFFFH
FFH
System stack space
070000H
000000H
Figure 2.4.2-1 Sample bank addressing
■ Bank addressing and default space
To improve instruction coding efficiency, each instruction has a defined default space for each
addressing method, as shown in Table 2.4.2-2. To use a space other than the default space,
specify a prefix code for a bank before the instruction. This enables the bank space that
corresponds to the specified prefix code to be accessed. See Section 2.9, "Prefix Codes", for
details about prefix codes.
Table 2.4.2-2 Addressing and default spaces
Default space
Addressing
Program space
PC indirect, program access, branching
Data space
Addressing using @RW0, @RW1, @RW4, and @RW5, @A,
addr16, dir
Stack space
Addressing using PUSHW, POPW, @RW3, and @RW7
Additional space Addressing using @RW2 and @RW6
34
MB90820 series
Memo
MB90820 series
35
2.5
Memory Location of Multibyte Data
Multibyte data is written to memory sequentially from the lower address. If multibyte
data is 32-bit data, the lower 16 bits are transferred followed by the upper 16 bits.
If a reset signal is input immediately after the low-order data is written, the high-order
data may not be written.
■ Storage of multibyte data in RAM
Figure 2.5-1 shows the data configuration of multibyte data in memory. The lower 8 bits of the
data is located at address n, and subsequent data is located at address n + 1, address n + 2,
address n + 3 and so on, in this sequence.
MSB
01010101B
H
LSB
11001100B
11111111B
00010100B
01010101B
11001100B
11111111B
Address ‘n’
00010100B
L
Figure 2.5-1 Storage of multibyte data in RAM
■ Storage of multibyte operand
Figure 2.5-2 shows the configuration of a multibyte operand in memory.
JMPP 123456H
H
JMPP 12 34 56H
12H
34H
Address ‘n’
56H
63H
L
Figure 2.5-2 Storage of a multibyte operand
36
MB90820 series
■ Storage of multibyte data in a stack
Figure 2.5-3 shows the configuration of multibyte data in a stack.
PUSH RW1,RW3
H
PUSHW RW1, RW3
(35A4H) (6DF0H)
SP
6DH
F0H
Address ‘n’
35H
A4H
L
RW1: 35A4H
RW3: 6DF0 H
*: Stack status after execution of the PUSHW instruction
Figure 2.5-3 Storage of multibyte data in a stack
■ Multibyte data access
Accessing is generally performed within a bank. For an instruction that accesses multibyte data,
the address following FFFFH is 0000H in the same bank.
Figure 2.5-4 shows an example of executing an instruction that accesses multibyte data on a
bank boundary.
H
01H
……..
80FFFFH
800000H
AL before execution
??
??
AL after execution
23H
01H
23H
L
Figure 2.5-4 Multibyte data access on a bank boundary
MB90820 series
37
2.6
Registers
F2MC-16LX registers are classified into internal dedicated CPU registers and built-in
RAM general-purpose registers.
■ Dedicated registers and general-purpose registers
Dedicated registers are dedicated hardware inside the CPU with limited use in the CPU
architecture.
General-purpose registers exist together with RAM in the CPU address space. Just like
dedicated registers, general-purpose registers can be accessed without addressing. Just like
ordinary memory, the user can specify how the register is used.
Figure 2.6-1 shows the location of the dedicated registers and general-purpose registers in the
device.
Dedicated register
General-purpose
register
Accumulator
User stack pointer
Processor status
Program counter
Direct page register
Internal bus
System stack pointer
Program bank register
Data bank register
User stack bank register
System stack bank register
Additional data bank register
Figure 2.6-1 Dedicated registers and general-purpose registers
38
MB90820 series
Memo
MB90820 series
39
2.7
Dedicated Registers
The following 11 registers are dedicated registers in the CPU.
• Accumulator (A)
• System stack pointer (SSP)
• Program counter (PC)
• Program bank register (PCB)
• User stack bank register (USB)
• Additional data bank register (ADB)
• User stack pointer (USP)
• Processor status (PS)
• Direct page register (DPR)
• Data bank register (DPP)
• System stack bank register (SSB)
■ Configuration of dedicated registers
Figure 2.7-1 shows the configuration of dedicated registers; Table 2.7-1 lists the initial values of
the dedicated registers.
AH
AL
Accumulator (A)
USP
User Stack Pointer (USP)
SSP
System Stack Pointer (SSP)
PS
Processor Status (PS)
PC
Program Counter (PC)
DPR
Direct Page Register (DPR)
PCB
Program Bank Register (PBR)
DPB
Data Bank Register (DBR)
USB
User Stack Bank Register (USB)
SSB
System Stack Bank Register (SSB)
ADB
Additional Data Bank Register (ADB)
8 bits
16 bits
32 bits
Figure 2.7-1 Configuration of dedicated registers
40
MB90820 series
Table 2.7-1 Initial values of the dedicated registers
Dedicated register
Initial value
Accumulator (A)
Undefined
User stack pointer (USP)
Undefined
System stack pointer (SSP)
Undefined
Processor status (PS)
15
PS
Default value
Program counter (PC)
Direct page register (DPR)
Program bank register (PCB)
⇒
13 12
87
ILM
RP
CCR
000
00000
-01xxxxx
Value in reset vector (contents of FFFFDCH, FFFFDDH)
01H
Value in reset vector (contents of FFFFDEH)
Data bank register (DTB)
00H
User stack bank register (USB)
00H
System stack bank register (SSB)
00H
Additional data bank register (ADB)
00H
-:
Not used
x:
Undefined
0
<Check>
The above initial values are the initial values for the device. They are different from the ICE
(emulator, etc.) values.
MB90820 series
41
2.7
Dedicated Registers
2.7.1 Accumulator (A)
The accumulator (A) consists of two 16-bit arithmetic operation registers (AH and AL).
The accumulator is used to temporarily store the results of an arithmetic operation and
data.The A register can be used as a 32-bit, 16-bit or 8-bit register. Various arithmetic
operations can be performed between memory and other registers or between the AH
register and the AL register. The A register has a data retention function that
automatically transfers pre-transfer data from the AL register to the AH register when
data of word length or less is transferred to the AL register. (Data is not retained with
some instructions.)
■ Accumulator (A)
● Data transfer to the accumulator
The accumulator can process 32-bit (long word), 16-bit (word) and 8-bit (byte) data. The 4-bit
data transfer instruction (MOVN) is an exception. The explanation of 8-bit data also applies to 4bit data.
•
For 32-bit data processing, the AH register and AL register are combined.
•
For 16-bit data and 8-bit data, only the AL register is used.
•
When data of byte length or less is transferred to the AL register, data becomes 16 bits long
by sign extension or zero extension, and is stored in the AL register. Data in the AL register
can be handled as word-length or byte-length data.
Figure 2.7.1-1 shows data transfer to the accumulator. Figures 2.7.1-2 to 2.7.1-5 show specific
transfer examples.
32-bit
32-bit data transfer
Data transfer Data transfer
16-bit data transfer
Data save
Data transfer
8-bit data transfer
Data save
00H or FFH (*1)
Data transfer
(Zero extension or sign extension)
*1 Becomes 000H or FFFH for a 4-bit transfer instruction.
Figure 2.7.1-1 Data transfer to the accumulator
42
MB90820 series
MOV A,3000H
(An instruction that zero-extends the contents at address 3000H and
stores the result in the AL register)
MSB
A before execution
XXXXH
2456H
DTB
A after execution
2456H
AH
B53000H
Memory space
77H
LSB
88H
B5H
0088H
AL
Figure 2.7.1-2 Example of AL-AH transfer in the accumulator (A) (8-bit immediate value, zero extension)
MOVX A,3000H
(An instruction that stores the contents at address 3000H
in the AL register)
MSB
A before execution
XXXXH
2456H
DTB
A after execution
2456H
AH
B53000H
Memory space
77H
LSB
88H
B5H
7788H
AL
Figure 2.7.1-3 Example of AL-AH transfer in the accumulator (A) (8-bit immediate value, sign extension)
MOVL A,@RW1+6
(Instruction that perform a long-word-length read using the result
of the RW1 contents + an 8-bit offset as the address and stores
the read value in the A register)
Memory space
MSB
A before execution
XXXXH
XXXXH
DTB
A after execution
8F74H
AH
A6 H
2B52H
AL
LSB
A61540H
8FH
74H
A6153EH
2BH
52H
RW1
15H
38H
+6
Figure 2.7.1-4 Example of 32-bit data transfer to the accumulator (A) (register indirect)
MB90820 series
43
MOVW A,@RW1+6
(Instruction that performs a word-length read using the result of
the RW1 contents + an 8-bit offset as the address and stores the
read value in the A register)
Memory space
MSB
A before execution
XXXXH
1234H
DTB
A after execution
1234H
AH
A6H
2B52H
AL
LSB
A61540H
8FH
74H
A6153EH
2BH
52H
RW1
15H
38H
+6
Figure 2.7.1-5 Example of AL-AH transfer in the accumulator (A) (16 bits, register indirect)
● Accumulator byte-processing arithmetic operation
When a byte-processing arithmetic operation instruction is executed for the AL register, the
upper 8 bits of the AL register before the arithmetic operation is executed are ignored. The
upper 8 bits of the arithmetic operation results are all zeros.
● Initial value of the accumulator
The initial value after a reset is undefined.
44
MB90820 series
Memo
MB90820 series
45
2.7
Dedicated Registers
2.7.2 Stack Pointers (USP, SSP)
There are two types of stack pointers: a user stack pointer (USP) and a system stack
pointer (SSP). Each stack pointer is a register that indicates the memory address of
the location of the destination for saved data or a return address when PUSH
instructions, POP instructions and subroutines are executed. The upper 8 bits of the
stack address are specified by the user stack bank register (USB) or system stack bank
register (SSB).
When the S flag of the condition code register (CCR) is 0, the USP and USB registers
are valid. When the S flag is 1, the SSP and SSB registers are valid.
■ Stack selection
The F2MC-16LX uses two types of stack: a system stack and a user stack.
The stack address is determined, as shown in Table 2.7.2-1, by the S flag in the processor
status (PS: CCR).
Table 2.7.2-1 Stack address specification
Stack address
S flag
Upper 8 bits
Lower 16 bits
0
User stack bank register (USB)
1
System stack bank register (SSB) System stack pointer (SSP)
User stack pointer (USP)
: Initial value
Because the S flag is initialized to 1 by a reset, the system stack is used as the default.
Ordinarily, the system stack is used for interrupt routine stack operations, and the user stack is
used for all other types of stack operation. When separation of the stack space is not particularly
necessary, only the system stack should be used.
<Check>
Since the S flag is set to 1 when an interrupt is accepted, the system stack is always used for
interrupts.
46
MB90820 series
Figure 2.7.2-1 shows an example of stack operation with the system stack.
PUSHW A with the S flag set to 0
Before execution
⇒
AL
A624H
S flag
After execution
⇒
AL
MSB
0
A624H
S flag
0
USB C6H
USP
F328H
SSB 56H
SSP
1234H
USB C6H
USP
F326H
SSB 56H
SSP
1234H
C6F326 H
LSB
XXH
XXH
⇐ User stack is used
because S flag is 0
C6F326 H
A6H
24H
PUSHW A with the S flag set to 1
MSB
Before execution
⇒
AL
A624 H
S flag
After execution
⇒
AL
1
A624 H
S flag
1
USB C6H
USP
F328H
SSB 56H
SSP
1234H
USB C6H
USP
F328H
SSB 56H
SSP
1232H
LSB
561232H
XXH
XXH
561232H
A6H
24H
⇐ System stack is used
because S flag is 1
Figure 2.7.2-1 Stack operation instruction and stack pointer
<Notes>
•
To set a value for the stack pointer, generally use an even-numbered address. If an oddnumbered address is used, a word access is split into two parts, lowering efficiency.
•
The initial values of the USP register and SSP register after a reset are undefined.
■ System stack pointer (SSP)
To use the system stack pointer (SSP), set the S flag in the condition code register (CCR) of the
processor status (PS) to 1. The upper 8 bits of the address that will be used for the stack
operation are indicated by the system stack bank register (SSB).
■ User stack pointer (USP)
To use the user stack pointer (USP), set the S flag in the condition code register (CCR) of the
processor status (PS) to 0. The upper 8 bits of the address that will be used for the stack
operation are indicated by the user stack bank register (USB).
MB90820 series
47
2.7
Dedicated Registers
2.7.3 Processor Status (PS)
The processor status (PS) consists of CPU control bits and bits that indicate the CPU
status. The PS register consists of the following three registers:
• Interrupt level mask register (ILM)
• Register bank pointer (RP)
• Condition code register (CCR)
■ Processor status (PS) configuration
The processor status (PS) consists of CPU control bits and bits that indicate the CPU status.
Figure 2.7.3-1 shows the configuration of the processor status (PS).
15
13 12
PS
Default value ⇒
Default value ⇒
87
ILM
RP
CCR
000
00000
-01xxxxx
7
6
5
4
3
2
1
0
–
I
S
T
N
Z
V
C
–
0
1
x
x
x
x
x
B4 B3 B2 B1 B0
Default value ⇒
Default value ⇒
0
0
0
0
0
: CCR
: RP
0
ILM2
ILM1
ILM0
0
0
0
: ILM
- : Not used
x : Undefined
Figure 2.7.3-1 Processor status (PS) configuration
● Interrupt level mask register (ILM)
This register indicates the level of the interrupt currently accepted by the CPU. The value is
compared with the value of the interrupt level setting bits (ICR: IL0 ~ IL2) in the interrupt control
register set for the peripheral resource interrupt request.
● Register bank pointer (RP)
This pointer points to the first address of the memory block (register bank) used as the generalpurpose register in the RAM area.
There are 32 banks for general-purpose registers. Values 0 to 31 are set in the RP to specify a
bank.
● Condition code register (CCR)
This register consists of flags that are set to 1 or reset to 0 by instruction execution results and
by interrupts.
48
MB90820 series
2.7
Dedicated Registers
2.7.4 Condition code register (PS: CCR)
The condition code register (CCR) is an 8-bit register that consists of the bits that
indicate the results of an arithmetic operation and the contents of transfer data and bits
that control interrupt request acceptance.
■ Condition code register (CCR) configuration
Figure 2.7.4-1 shows the configuration of the CCR register. Refer to the programming manual for
details about the status of the condition code register (CCR) during instruction execution.
Default value ⇒
7
6
5
4
3
2
1
0
–
I
S
T
N
Z
V
C
–
0
1
x
x
x
x
x
: CCR
Interrupt enable flag
Stack flag
Sticky flag
Negative flag
Zero flag
Overflow flag
Carry flag
- : Not used
x : Undefined
Figure 2.7.4-1 Condition code register (CCR) configuration
● Interrupt enable flag (I)
In response to all interrupt requests other than software interrupts, when the I flag is 1, interrupts
are enabled. When the I flag is 0, interrupts are disabled. Cleared by a reset.
● Stack flag (S)
This flag indicates the pointer used for a stack operation.
When the S flag is 0, the user stack pointer (USP) is valid. When the S flag is 1, the system
stack pointer (SSP) is valid. Set when an interrupt is accepted or when a reset occurs.
● Sticky bit flag (T)
Set to 1 when the data shifted out by the carry contains at least one 1 during execution of a
logical right shift instruction or arithmetic right shift instruction. Otherwise, set to 0. Also set to 0
when the shift amount is zero.
● Negative flag (N)
Set to 1 when the MSB is 1 as the result of an arithmetic calculation. Cleared to 0 when the
MSB is 0.
● Zero flag (Z)
Set to 1 when the result of an arithmetic calculation is all zeros. Otherwise, set to 0.
MB90820 series
49
● Overflow flag (V)
Set to 1 if a signed numeric value overflows because of an arithmetic calculation. Cleared to 0 if
no overflow occurs.
● Carry flag (C)
Set to 1 when there is an overflow from the MSB or an underflow from the LSB because of an
arithmetic calculation. Cleared to 0 when there is no overflow or underflow because of an
arithmetic calculation.
50
MB90820 series
2.7
Dedicated Registers
2.7.5 Register bank pointer (PS: RP)
The register bank pointer (RP) is a register that indicates the first address of the
general-purpose register bank currently being used. The RP is used for real address
conversion when general-purpose register addressing is used.
■ Register bank pointer (RP)
Figure 2.7.5-1 shows the configuration of the register bank pointer (RP) register.
B4 B3 B2 B1 B0
Default value ⇒
0
0
0
0
: RP
0
Figure 2.7.5-1 Configuration of the register bank pointer (RP)
■ General-purpose register area and register bank pointer
The register bank pointer points to the relationship between the general-purpose register of the
F2MC-16LX and the address in internal RAM where the general-purpose register exists. Figure
2.7.5-2 shows the conversion rules used for the relationship between the contents of the RP and
the real address.
Conversion formula [000180 H + (RP) X 10H]
When RP = 10H
000370H
Register bank 31
Register bank 16
000280H
000180H
Register bank 0
Figure 2.7.5-2 Conversion rules for physical address of general-purpose register area
•
Since the RP takes a value from 00H to 1FH, the first address of the register bank can be set
in the range from 000180H to 00037FH.
•
Although an assembler instruction can use an 8-bit immediate value transfer instruction for
transfer to the RP, in actuality only the lower 5 bits of the data are used.
•
The initial value of the RP register after a reset is 00H.
MB90820 series
51
2.7
Dedicated Registers
2.7.6 Interrupt level mask register (PS: ILM)
The interrupt level mask register (ILM) is a 3-bit register that indicates the level of the
interrupt currently accepted by the CPU.
■ Interrupt level mask register (ILM)
Figure 2.7.6-1 shows the configuration of the interrupt level mask register (ILM). See Chapter 6,
"Interrupt", for details about interrupts.
Default value ⇒
ILM2
ILM1
ILM0
0
0
0
: ILM
Figure 2.7.6-1 Configuration of the interrupt level mask register (ILM)
The interrupt level mask register (ILM) indicates the level of the interrupt currently accepted by
the CPU. The level is compared with the value of the IL0 to IL2 bits of the interrupt control
register (ICR00 to ICR15) set according to the interrupt request from the peripheral function. If
the interrupt enable flag has been set to enable (CCR: I = 1), the CPU processes the instruction
only when the value (interrupt level) of the interrupt request is smaller than the value indicated by
these bits.
•
When an interrupt is accepted, the interrupt level value is set in the interrupt level mask
register (ILM). Thereafter, interrupts with the same or lower level are not accepted.
•
The interrupt level is set to the highest level, which is the interrupts disabled status, because
the interrupt level mask register (ILM) is initialized to all 0’s by a reset.
•
Although an assembler instruction can use an 8-bit immediate value transfer instruction for
transfer to the interrupt level mask register (ILM), only the lower 3 bits of the data are used.
Table 2.7.6-1 Interrupt level mask register (ILM) and interrupt level priority
52
ILM2
ILM1
ILM0
Interrupt level
Interrupt level priority
0
0
0
0
Highest (interrupts disabled)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Lowest
MB90820 series
2.7
Dedicated Registers
2.7.7 Program Counter (PC)
The program counter (PC) is a 16-bit counter that indicates the lower 16 bits of the
memory address of the next instruction code to be executed by the CPU.
■ Program counter (PC)
The program bank register (PCB) specifies the upper 8 bits of the address where the next
instruction code to be executed by the CPU is stored. The PC specifies the lower 16 bits.
Before being used, the actual address is combined to become 24 bits, as shown in
Figure 2.7.7-1.
The contents of the PC are updated by conditional branch instructions, subroutine call
instructions, interrupts and resets.
The PC can be used as a bus pointer for reading operands.
Upper 8 bits
Upper 16 bits
PCB
PC
FE H
ABCDH
FEABCDH
Next instruction
to be executed
Figure 2.7.7-1 Program counter (PC)
<Check>
The PC and PCB cannot be rewritten directly by a program (such as by MOV PC and #FF).
MB90820 series
53
2.7
Dedicated Registers
2.7.8 Direct Page Register (DPR)
The direct page register (DPR) is an 8-bit register that specifies bits 8 to 15 (addr8 to
addr15) of the operand address when a short direct addressing instruction is executed.
■ Direct page register (DPR)
As shown in Figure 2.7.8-1, the DPR specifies bits 8 to 15 (addr8 to addr15) of the operand
address when a short direct addressing instruction is executed. The DPR is 8-bits long. The
DPR is initialized to 01H by a reset. The DPR can be read and written using an instruction.
DTB register
DDR register
αααααααα
ββββββββ
MSB
24-bit physical address
Direct address in instruction
γγγγγγγγ
LSB
ααααααααββββββββγγγγγγγγ
Figure 2.7.8-1 Physical address generation by the direct page register (DPR)
Figure 2.7.8-2 shows an example of direct page register (DPR) setting and data access.
Instruction execution results
Memory space
MOV S:56H, #5AH
Upper
8 bits
DTB register
12H
123458H
123456H
DPR register
34H
Lower
8 bits
5AH
123454H
MSB
LSB
Figure 2.7.8-2 Example of direct page register (DPR) setting and data access
54
MB90820 series
2.7
Dedicated Registers
2.7.9 Bank Registers (PCB, DTB, USB, SSB, ADB)
Bank registers specify the highest 8-bit address by bank addressing. The five bank
registers are as follows:
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional bank register (ADB)
The PCB, DTB, USB, SSB and ADB registers indicate the individual memory banks
where the program space, data space, user stack space, system stack space and
additional space are located.
■ Bank registers (PCB, DTB, USB, SSB, ADB)
●
Program bank register (PCB)
The PCB is a bank register that specifies the program (PC) space.
The PCB is rewritten when a software interrupt instruction is executed, when the JMPP,
CALLP, RETP and RETI instructions that branch anywhere within the 16-megabyte space
are executed, or when a hardware interrupt or exception occurs.
●
Data bank register (DTB)
The DTB is a bank register that specifies the data (DT) space.
●
User stack bank register (USB), system stack bank register (SSB)
The USB and SSB are bank registers that specify the stack (SP) space. Whether the USB or
the SSB is used depends on the S flag value in the processor status (PS: CCR). See Section
2.7.2, "Stack pointers (USP, SSP)", for details.
●
Additional bank register (ADB)
The ADB is a bank register that specifies the additional (AD) space.
●
Bank setting and data access
All bank registers are byte length. The PCB is initialized to FFH by a reset. The other bank
registers are initialized to 00H by a reset. The PCB can be read, but cannot be written to.
The other bank registers can be read and written to.
<Check>
The MB90820 series supports up to the memory space contained in the device.
See Section 2.4.2, "Address specification by bank addressing", for the operation of each
register.
MB90820 series
55
2.8
General-purpose Registers
The general-purpose registers are a memory block allocated in RAM at 000180H to
00037FH as banks, each of which consists of eight 16-bit segments.
The general-purpose registers can be used as general-purpose 8-bit registers (byte
registers R0 to R7), 16-bit registers (word registers RW0 to RW7) or 32-bit registers
(long-word registers RL0 to RL7).
General-purpose registers can access RAM with a short instruction at high speed.
Since general-purpose registers are blocked into register banks, protection of register
contents and division into function units can readily be performed. When a generalpurpose register is used as a long-word register, it can be used as a linear pointer that
directly accesses the entire space.
■ Configuration of a general-purpose register
All general-purpose registers exist in RAM at 000180 H to 00037FH and are configured as 32
banks. The register bank pointer (RP) specifies the bank that is to be used for a generalpurpose register. The RP points to the bank currently being used.
The RP determines the first address of each bank with the following formula:
Address of first general-purpose register = 000180 H + RP x 10H
Figure 2.8-1 shows the location and configuration of the general-purpose register banks in the
memory space.
Built-in RAM
Register bank 31
Byte address
Byte address
Register bank 30
Register bank 21
Register bank 20
Register bank 19
Register bank 2
Register bank 1
Register bank 0
Conversion formula [000180H + RP x 10H]
R0 to R7:
RW0 to RW7:
RL0 to RL3:
MSB:
LSB:
Byte registers
Word registers
Long-word registers
Most Significant Bit
Least Significant Bit
Figure 2.8-1 Location and configuration of the general-purpose register banks in the memory space
<Check>
The register bank pointer (RP) is initialized to 00H after a reset.
56
MB90820 series
■ Register bank
A register bank can be used as general-purpose registers (byte registers R0 to R7, word
registers RW0 to RW7, long-word registers RL0 to RL3) for various arithmetic operations and
pointers. A long-word register can be used as a linear pointer that directly accesses the entire
memory space.
The contents of the register bank, like ordinary RAM, are not initialized by a reset. The status
before a reset is retained. At power-on, however, the contents are undefined.
Table 2.8-1 lists the typical functions of general-purpose registers.
Table 2.8-1 Typical functions of general-purpose registers
Register name
MB90820 series
Function
R0 to R7
Used as an operand in various instructions
<Caution>
R0 is also used as a barrel shift counter and an instruction
normalization counter
RW0 to RW7
Used as a pointer
Used as an operand in various instructions
<Caution>
RW0 is used also as a string instruction counter
RL0 to RL3
Used as a long pointer
Used as an operand in various instructions
57
2.9
Prefix Codes
Prefix codes are placed before an instruction to partially change the operation of the
instruction. The three types of prefix codes are as follows:
• Bank select prefix (PCB, DTB, ADB, SPB)
• Common register bank prefix (CMR)
• Flag change suppression prefix (NCC)
■ Prefix codes
● Bank select prefix (PCB, DTB, ADB, SPB)
A bank select prefix is placed before an instruction to select the memory space to be accessed
by the instruction regardless of the addressing method.
● Common register bank prefix (CMR)
The common register bank prefix is placed before an instruction that accesses a register bank to
change the register accessed by the instruction to the common bank (register bank selected
when RP = 0) at 000180H to 00018FH regardless of the current register bank pointer (RP) value.
● Flag change suppression prefix (NCC)
The flag change suppression prefix code is placed before an instruction to suppress a flag
change accompanying the execution of the instruction.
58
MB90820 series
Memo
MB90820 series
59
2.9
Prefix Codes
2.9.1 Bank select prefix (PCB, DTB, ADB, SPB)
A bank select prefix is placed before an instruction to select the memory space
accessed by the instruction regardless of the addressing method.
■ Bank select prefixes (PCB, DTB, ADB, SPB)
The memory space used for data access is defined for each addressing method. If a bank select
prefix is placed before an instruction, the memory space accessed by the instruction can be
selected regardless of the addressing method. Table 2.9.1-1 lists the bank select prefix codes
and selected memory spaces.
Table 2.9.1-1 Bank select prefix codes and selected memory spaces
Bank select prefix
Selected space
PCB
Program space
DTB
Data space
ADB
Additional space
SPB
When the value of the S flag in the condition code register (CCR) is
0 and the user stack space is 1, the system stack space is used.
If a bank select prefix is used, some instructions perform an unexpected operation.
Table 2.9.1-2 lists the instructions that are not affected by bank select prefix codes. Table 2.9.13 lists instructions that require caution when they are used.
Table 2.9.1-2 Instructions not affected by bank select prefix codes
Instruction
type
String
instruction
60
Instruction
MOVS
SCEQ
FILS
Stack
operation
PUSHW
I/O access
instruction
MOV
MOVW
MOV
MOV
MOVB
SETB
BBC
WBTC
Interrupt
return
instruction
RETI
Effect of bank select prefix
MOVSW
SCWEQ
FILSW
The bank register specified by the
operand is used whether or not a prefix
is used.
POPW
When the S flag is 0, the user stack bank
(USB) is used whether or not there is a
prefix. When the S flag is 1, the system
stack bank (SSB) is used regardless of
whether a prefix is used.
A
A, io
io, A
io, #imm8
A, io : bp
io : bp
io : bp, rel
io, bp
MOVX
A, io
MOVW
MOVW
MOVB
CLRB
BBS
WBTS
io, A
io, #imm16
io : bp, A
io : bp
io : bp, rel
io : bp
The I/O space (000000 H to 0000FFH) is
accessed whether or not there is a
prefix.
The system stack bank (SSB) is used
whether or not a prefix is used.
MB90820 series
Table 2.9.1-3 Instructions whose use requires caution when bank select prefix
codes are used
Instruction type
MB90820 series
Instruction
Explanation
Flag change instruction
AND
OR
CCR, #imm8
CCR, #imm8
The effect of the prefix extends to the next
instruction.
ILM setting instruction
MOV
ILM, #imm8
The effect of the prefix extends to the next
instruction.
PS return instruction
POPW
PS
Do not place a bank select prefix before the
PS return instruction.
61
2.9
Prefix Codes
2.9.2 Common register bank prefix (CMR)
The common register bank (CMR) prefix is placed before an instruction that accesses a
register bank to change the register accessed by the instruction to the common bank
(register bank selected when RP = 0) at 000180H to 00018FH regardless of the current
register bank pointer (RP) value.
■ Common register bank prefix (CMR)
To facilitate data exchange between multiple tasks, a relatively simple means of accessing a
fixed register bank regardless of the current register bank pointer (RP) value is necessary. This
is the reason that the F2MC-16LX provides a common register bank for tasks, which is called the
common bank. The common bank is located at address 000180H to 00018FH.
If the common register bank prefix (CMR) is placed before an instruction that accesses a register
bank, registers accessed by the instruction can be changed to the common bank (register bank
selected when RP = 0) at 000180H to 00018FH regardless of the current register bank pointer
(RP) value.
Note that caution is required when this prefix is used with the instructions listed in Table 2.9.2-1.
Table 2.9.2-1 Instructions whose use requires caution when the common register bank
prefix (CMR) is used
Instruction
type
62
Instruction
MOVSW
SCWEQ
FILSW
Explanation
String
instruction
MOVS
SCEQ
FILS
Flag change
instruction
AND
PS return
instruction
POPW PS
The effect of the prefix extends to the next
instruction.
ILM setting
instruction
MOV
The effect of the prefix extends to the next
instruction.
CCR, #imm8
ILM, #imm8
OR CCR, #imm8
Do not place the CMR prefix before the
string instruction.
The effect of the prefix extends to the next
instruction.
MB90820 series
2.9
Prefix Codes
2.9.3 Flag change suppression prefix (NCC)
The flag change suppression prefix (NCC) code is placed before an instruction to
suppress a flag change accompanying the execution of the instruction.
■ Flag change suppression prefix (NCC)
The flag change suppression prefix (NCC) is used to suppress unnecessary flag changes. If a
flag change suppression prefix code is placed before an instruction, a flag change
accompanying the execution of the instruction is suppressed. Changes of the T, N, Z, V and C
flags are suppressed.
Note that caution is required when this prefix is used with the instructions listed in Table 2.9.3-1.
Table 2.9.3-1 Instructions whose use requires caution when the flag change suppression
prefix (NCC) is used
Instruction
type
String
instruction
Flag change
instruction
MOVS
SCEQ
FILS
AND
CCR, #imm8
Explanation
MOVSW
SCWEQ
FILSW
Do not place the NCC prefix before the
string instruction.
OR CCR, #imm8
The condition code register (CCR) changes
as defined in the instruction specification
whether or not a prefix is used.
The effect of prefix extends to the next
instruction.
PS return
instruction
POPW PS
The condition code register (CCR) changes
as defined in the instruction specification
whether or not a prefix is used.
The effect of prefix extends to the next
instruction.
ILM setting
instruction
MOV
ILM, #imm8
The effect of prefix extends to the next
instruction.
INT
INT
RETI
#vct8
INT9
adder16
INTP
Interrupt
instruction
Interrupt
return
instruction
Context
switch
instruction
MB90820 series
Instruction
JCTX
@A
addr24
The condition code register (CCR)
changes as defined in the instruction
specification whether or not a prefix is
used.
The condition code register (CCR)
changes as defined in the instruction
specification whether or not a prefix is
used.
63
2.9
Prefix Codes
2.9.4 Restrictions on Prefix Codes
The following three restrictions are imposed on the use of prefix codes:
• Interrupt/hold requests are not accepted during the execution of prefix codes
and interrupt/hold suppression instructions.
• If a prefix code is placed before an interrupt/hold instruction, the effect of the
prefix code is delayed.
• If consecutively placed prefix codes conflict, the last prefix code is valid.
■ Prefix codes and interrupt/hold suppression instructions
Table 2.9.4-1 lists the interrupt/hold suppression instructions and prefix codes that have
restrictions.
Table 2.9.4-1 Prefix codes and interrupt/hold suppression instructions
Prefix codes
PCB
DTB
ADB
SPB
CMR
NCC
Instructions that do not
accept interrupt and hold
requests
Interrupt/hold suppression instructions (instructions that
delay the effect of prefix codes)
MOV
OR
AND
POPW
ILM , #imm8
CCR, #imm8
CCR, #imm8
PS
● Interrupt/hold suppression
As shown in Figure 2.9.4-2, an interrupt or hold request generated during the execution of prefix
codes and interrupt/hold instructions is not accepted. The interrupt/hold is not processed until
the first instruction that is not governed by a prefix code or that is not an interrupt/hold
suppression instruction is executed.
Interrupt/hold
suppression
instruction
(a) Ordinary instruction
…………
↑
Interrupt request generated
……
(a)
↑
Interrupt accepted
Figure 2.9.4-1 Interrupt/hold suppression
64
MB90820 series
● Delay of the effect of prefix codes
As shown in Figure 2.9.4-2, if a prefix code is placed before an interrupt/hold suppression
instruction, the prefix code takes effect with the first instruction executed after the interrupt/hold
suppression instruction.
Interrupt suppression instructions
MOV A, FFH
…
MOV ILM, #imm8
NCC
CCR: XXX10XXB
ADD A, 01H
CCR: XXX10XXB
CCR is not changed due to NCC prefix
Figure 2.9.4-2 Interrupt/hold suppression instructions and prefix codes
■ Consecutive prefix codes
As shown in Figure 2.9.4-3, when consecutive conflicting prefix codes (PCB, ADB, DTB and
SPB) are specified, the last prefix code is valid.
Prefix
codes
……
ADB
DTB
PCB
ADD A, 01H
……
↑ The PCB prefix code is valid
Figure 2.9.4-3 Consecutive prefix codes
MB90820 series
65
66
MB90820 series
CHAPTER 3
RESET
This chapter describes the reset for the MB90820 series microcontrollers.
3.1 Reset
3.2 Reset Causes and Oscillation Stabilization Wait Intervals
3.3 External Reset Pin
3.4 Reset Operation
3.5 Reset Cause Bits
3.6 Status of Pins in a Reset
MB90820 series
67
3.1
Reset
If a reset cause is generated, the CPU immediately stops the current execution process
and waits for the reset to be cleared. When the reset is cleared, the CPU begins
processing at the address indicated by the reset vector.
There are four causes of a reset:
Power-on reset
Watchdog timer overflow
External reset request via the RSTX pin
Software reset request
■ Reset causes
Table 3.1-1 lists the reset causes.
Table 3.1-1 Reset causes
Type of reset
Cause
Machine clock
Watchdog timer
Oscillation
stabilization
wait
External pin
Low level input to RSTX pin
Previous state
retained
Previous state
retained
No
Software
A “0” is written to the RST bit of
the low power consumption
mode control register (LPMCR)
Previous state
retained
Previous state
retained
No
Watchdog timer
Watchdog timer overflow
MCLK
Stop
Yes
Power-on
When the power is turned on
MCLK
Stop
Yes
MCLK: Main clock (oscillation clock frequency divided by 2)
● External reset
An external reset is generated by the L level input to an external reset pin (RSTX pin). The
minimum required period of the L level input to the RSTX pin is 16 machine cycles (16/φ). The
oscillation stabilization wait interval is not required for external resets.
68
MB90820 series
[Reference]
For external reset requests via the RSTX pin, if the reset cause is generated during a write
operation (during the execution of a transfer instruction such as MOV), the CPU waits for the
reset to be cleared after the instruction is completed. The normal write operation is therefore
completed even though a reset is input concurrently.
Note, however, that waiting for the reset to be cleared may start before the transfer of the
contents of a counter specified by a string-processing instruction (such as MOVS) is
completed.
● Software reset
A software reset is an internal reset of three machine cycles (3/φ) generated by writing 0 to the
RST bit of the low power consumption mode control register (LPMCR). The oscillation
stabilization wait interval is not required for software resets.
● Watchdog timer reset
A watchdog timer reset is generated by a watchdog timer overflow that occurs when a 0 is not
written to the WTE bit of the watchdog timer control register (WDTC) within a given time after the
watchdog timer is activated. The oscillation stabilization wait interval can be set by the clock
selection register (CKSCR).
● Power-on reset
A power-on reset is generated when the power is turned on. The oscillation stabilization wait
interval is fixed at 216 oscillation clock cycles (216/HCLK). After the oscillation stabilization wait
interval has elapsed, the reset is executed.
See also
•
Definition of clocks
HCLK: Oscillation clock frequency
MCLK: Main clock frequency
φ: Machine clock (CPU operating clock) frequency
1/φ: Machine cycle (CPU operating clock cycle)
See Section 4.1, "Clock", for details.
MB90820 series
69
3.2
Reset Causes and Oscillation Stabilization Wait Intervals
The F2MC-16LX has four reset causes. The oscillation stabilization wait interval for a
reset depends on the reset cause.
■ Reset causes and oscillation stabilization wait intervals
Table 3.2-1 summarizes reset causes and oscillation stabilization wait intervals.
Table 3.2-1 Reset causes and oscillation stabilization wait intervals
Oscillation stabilization wait interval
The corresponding time interval for an oscillation clock
frequency of 4 MHz is given in parentheses.
Reset cause
Power-on reset
216/HCLK (approximately 16.39 ms)
Watchdog timer
216/HCLK (approximately 16.39 ms)
External reset via the RSTX pin
None. However the WS1 & WS0 bits are initialized to “11”.
Software reset
None. However the WS1 & WS0 bits are initialized to “11”.
HCLK:
Oscillation clock frequency, source oscillation
Figure 3.2-1 shows the oscillation stabilization wait interval of the product at power-on reset.
Vcc
2 15 /HCLK
2 16 /HCLK
CLK
CPU operation
Regulator stabilization
wait interval
Oscillation stabilization
wait interval
HCLK: oscillation clock
Figure 3.2-1 Oscillation stabilization wait interval at power-on reset
<Check>
Ceramic and crystal oscillators generally require an oscillation stabilization wait interval of a
few to several dozen milliseconds until they stabilize at their natural frequency. Be sure to
set a proper oscillation stabilization wait interval for the specific oscillator used.
See Section 3.2, “Oscillation Stabilization Wait Interval,” for detail about Oscillation
Stabilization Wait Interval.
■ Oscillation stabilization wait and reset state
A reset operation in response to a power-on reset and other externally activated resets during
stop mode and hardware standby mode is performed after the oscillation stabilization wait
interval has elapsed. This time interval is generated by the timebase timer. If the external reset
has not been cleared after the interval, the reset operation is performed after the external reset
is cleared.
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MB90820 series
3.3
External Reset Pin
The external reset pin (RSTX pin) is a dedicated pin for inputting, with an L level signal,
a reset and generating an internal reset by the L level input.
For MB90820 series microcontrollers, resets are generated in synchronization with the
CPU operating clock. Asynchronous resets are generated only for the external
terminals.
■ Block diagram of the external reset pin
● Block diagram of external reset
RSTX
R
P-ch
Pin
N-ch
CPU operating clock
(PLL multiplier circuit with a frepuency of HCLK divided by 2)
Synchronization
curcuit
HCLK: Oscillation clock frequency
Internal reset signal
Input buffer
Figure 3.3-1 Block diagram of external reset
<Check>
Inputs to the RSTX pin are accepted during cycles in which memory is not affected to prevent
memory from being destroyed by a reset during a write operation.
A clock is required to initialize the internal circuit. In particular, an operation with an external
clock requires clock input together with reset input.
MB90820 series
71
3.4
Reset Operation
When a reset is cleared, the memory locations from which the mode data and the reset
vector are read are selected according to the setting of the mode pins, and the mode
setting data is fetched. Mode setting data determines the CPU operating mode and the
execution start address after a reset operation ends.
For power-on or recovery from stop mode by a reset, the mode is fetched after the
oscillation stabilization wait time has elapsed.
■ Overview of reset operation
Figure 3.4-1 shows the reset operation flow.
Power-on reset
Stop mode reset
Watchdog timer reset
External reset
Software reset
During a reset
Oscillation stabilization wait
and reset state
Fetching the mode data
Mode fetch
(Reset operation)
Pin state and function
change associated with
external bus mode
Fetching the reset vector
Normal operation
(Run state)
CPU executes an instruction,
fetching instruction codes from
the address indicates by the
reset vector
Figure 3.4-1 Reset operation flow
■ Mode pins
Setting the mode pins (MD0 ~ MD2) specifies how to fetch the reset vector and the mode data.
Fetching the reset vector and the mode data is performed in the reset sequence. See Section
7.1, "Setting a Mode", for details about mode pins.
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MB90820 series
■ Mode fetch
When the reset is cleared, the CPU transfers the reset vector and the mode data stored in the
hardware memory to the appropriate registers in the CPU core. The reset vector and mode data
are allocated to the four bytes from FFFFDCH to FFFFDFH. The CPU outputs these addresses
to the bus immediately after the reset is cleared and fetches the reset vector and mode data.
Using mode fetching, the CPU can begin processing at the address indicated by the reset
vector.
Figure 3.4-2 shows the transfer of the reset vector and mode data.
F2MC-16LX CPU
Memory space
FFFFDFH
Mode
register
Mode data
FFFFDEH
Reset vector bits 23 to 16
FFFFDDH
Reset vector bits 15 to 8
FFFFDCH
Reset vector bits 7 to 0
Micro-ROM
Reset sequence
PCB
PC
Figure 3.4-2 Transfer of reset vector and mode data
[Reference]
Whether the reset vector and the mode data are read from internal ROM or from external
memory is specified by the setting of the mode pins. If external vector mode is specified by
the mode pin settings, the CPU will always read the reset vector and the mode data from
external memory instead of from internal ROM. If single-chip mode and internal ROM
external bus mode are used, setting the mode pins to specify internal vector mode is
recommended.
● Mode data (address: FFFFDFH)
Only the reset operation changes the contents of the mode register. The mode register setting
is valid after a reset operation. See Section 7.1, "Setting a Mode", for details about mode data.
● Reset vector (address: FFFFDCH to FFFFDEH)
The execution start address after the reset operation ends is written as the reset vector.
Execution starts at the address contained in the reset vector.
MB90820 series
73
3.5
Reset Cause Bits
A reset cause can be identified by reading the watchdog timer control register (WDTC).
■ Reset cause bits
As shown in Figure 3.5-1 , a flip-flop is associated with each reset cause. The contents of the
flip-flops are obtained by reading the watchdog timer control register (WDTC). If it is necessary
to identify the cause of a reset after the reset has been cleared, the value read from the WDTC
should be processed by the software and a branch made to the appropriate program.
RSTX
Pin
RSTX = L
Without periodic clear
Power-on
RST bit set
Power-on
detection circuit
External reset
request detection
circuit
Watchdog timer
reset detection circuit
LPMCR RST bit
write detection circuit
Watchdog timer
control register
(WDTC)
S
R
F/F
Q
S
R
F/F
Q
S
R
F/F
Q
S
R
F/F
Q
WDTC register
Delay
circuit
WDTC register read
F2MC-16LX internal bus
S : Set
R : Reset
:Q : Output
F/F : Flip Flop
Figure 3.5-1 Block diagram of reset cause bits
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MB90820 series
■ Correspondence between reset cause bits and reset causes
Figure 3.5-2 shows the configuration of the reset cause bits of the watchdog timer control
register (WDTC). Table 3.5-1 maps the correspondence between the reset cause bits and reset
causes.
Watchdog timer control register
Address : 0000A8H
Read/write
Default value
⇒
⇒
7
6
PONR
-
(R)
(X)
(-)
(X)
5
4
3
2
1
0
⇐ Bit number
WRSTERST SRST WTE WT1 WT0
(R)
(X)
(R)
(X)
(R)
(X)
(W)
(1)
(W)
(1)
WDTC
(W)
(1)
Figure 3.5-2 Configuration of reset cause bits (watchdog timer control register)
Table 3.5-1 Correspondence between reset cause bits and reset causes
Reset cause
PONR
WRST
ERST
SRST
Power-on reset
1
X
X
X
Watchdog timer overflow
*
1
*
*
External reset request via RSTX pin
*
*
1
*
Software reset request
*
*
*
1
*:
Previous state retained
X: Undefined
■ Notes about reset cause bits
● Multiple reset causes generated at the same time
When multiple reset causes are generated at the same time, the corresponding reset cause bits
of the watchdog timer control register (WDTC) are set to 1.
If, for example, an external reset request via the RSTX pin and the watchdog timer overflow
occur at the same time, both the ERST bit and the WRST bit are set to 1.
● Power-on reset
For a power-on reset, the PONR bit is set to 1, but all other reset cause bits are undefined.
Consequently, program the software so that it will ignore all reset cause bits except the PONR
bit if it is 1.
● Clearing the reset cause bits
The reset cause bits are cleared only when the watchdog timer control register (WDTC) is read.
Any bit that corresponds to a reset cause that has already been generated once is not cleared
even though another reset is generated (its setting of 1 is retained).
MB90820 series
75
3.6
Status of Pins in a Reset
This section describes the status of pins when a reset occurs.
■ Status of pins during a reset
The status of pins during a reset depends on the settings of mode pins (MD2 to MD0 = "011B").
● When internal vector mode has been set:
All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM.
■ Status of pins after mode data is read
The status of pins after mode data has been read depends on the mode data (M1 and M0 =
“00B”).
● When single-chip mode has been selected (M1, M0 = 00B):
All I/O pins (resource pins) are high impedance, and mode data is read from the internal ROM.
<Check>
For those pins that change to high impedance when a reset cause is generated, take care
that devices connected to them do not malfunction.
See Table 5.7-1 for information about the state of pins during a reset.
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MB90820 series
CHAPTER 4
CLOCK
This chapter describes the clock used by MB90820 series microcontrollers.
4.1 Clock
4.2 Block Diagram of the Clock Generation Block
4.3 Clock Selection Registers
4.4 Clock Mode
4.5 Oscillation Stabilization Wait Interval
4.6 Connection of an Oscillator or an External Clock to the Microcontroller
MB90820 series
77
4.1
Clock
The clock generation block controls the operation of the internal clock that controls
operation of the CPU and peripheral functions. This internal clock is called the
machine clock. One internal clock cycle is regarded as one machine cycle.
Other clocks include a clock generated by source oscillation, called an oscillation
clock, and a clock generated by the internal PLL oscillation, called a PLL clock.
■ Clock
The clock generation block contains the oscillation circuit that generates the oscillation clock. An
external oscillator is attached to this circuit. The oscillation clock can also be supplied by
inputting an external clock to the clock generation block.
The clock generation block also contains the PLL clock multiplier circuit, which generates five
clocks that are multiples of the oscillation clock.
The clock generation block controls the oscillation stabilization wait interval and PLL clock
multiplication as well as controls internal clock operation by changing the clock with a clock
selector.
● Oscillation clock (HCLK)
The oscillation clock is generated either from an external oscillator attached to the oscillation
circuit or by input of an external clock.
● Main clock (MCLK)
The main clock, which is the oscillation clock divided by 2, supplies the clock input to the
timebase timer and the clock selector.
● PLL clock (PCLK)
The PLL clock is obtained by multiplying the oscillation clock with the internal PLL clock
multiplier circuit (PLL oscillation circuit). Selection can be made from among four different PLL
clocks.
● Machine clock (φ)
The machine clock controls the operation of the CPU and peripheral functions. One clock cycle
is regarded as one machine cycle (1/φ). An operating machine clock can be selected from
among the main clock that is generated from the source clock frequency divided by 2 and the
five clocks that are multiples of the source clock frequency.
<Check>
Although an oscillation clock of 3 MHz to 48 MHz can be generated when the operating
voltage is 5 V, the maximum operating frequency for the CPU and peripheral functions is
24 MHz. If a frequency multiplier rate exceeding the operating frequency is specified,
devices will not operate correctly.
If, for example, a source oscillation of 12 MHz is generated, only a multiplier of 2 can be
specified.
A PLL oscillation of 4 to 24 MHz is possible, but this range depends on the operating voltage
and multiplier. See "Data Sheet", for details.
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MB90820 series
■ Clock supply map
Since the machine clock generated in the clock generation block is supplied as the clock that
controls operation of the CPU and peripheral functions, the operation of the CPU and peripheral
functions is affected by switching of the main clock and the PLL clock (clock mode) and a
change in the PLL clock multiplier.
Since some peripheral functions receive frequency-divided output from the timebase timer, a
peripheral unit can select the clock best suited for its operation.
Figure 4.1-1 shows the clock supply map.
Peripheral function
4
Watchdog timer
16-bit PPG
timer 0
16-bit PPG
timer 1
Timebase timer
16-bit PPG
timer 2
Clock generation block
16-bit reload
timer 0
1 2 3 4 6
PLL multiplier circuit
X0
Pin
System
Divide-by-2
clock
generation
HCLK
MCLK
circuit
X1
Pin
PPG1
Pin
PPG2
Pin
TIN0
Pin
TO0
Pin
SCK0,SIN0
Pin
PCLK
Clock selecter
PPG0
Pin
φ
UART0
UART1
CPU
16-bit reload
timer 1
Waveform
generator
SOT0
Pin
SCK1,SIN1
Pin
SOT1
Pin
TIN1
Pin
TO1
Pin
DTTI
Pin
RTO0 to RTO5
Pin
16-bit output
compare (Ch0~5)
16-bit free-running
timer
16-bit input capture
(Ch0~3)
HCLK:
MCLK:
PCLK:
φ :
8/10-bit A/D
converter
Oscillation clock
Main clock
PLL clock
Machine clock
8-bit D/A
converter
φ : Machine clock
DTP / external
interrupt
FRCK
Pin
IN0 to IN3
Pin
DA0
Pin
DA1
Pin
INT0 to INT7
Pin
PWI0, PWI1
Pin
PWC (Ch0~1)
3
PWO0, PWO1
Pin
Oscillation stabilization
wait control
Figure 4.1-1 Clock supply map
MB90820 series
79
4.2
Block Diagram of the Clock Generation Block
The clock generation block consists of five blocks:
• System clock generation circuit
• PLL multiplier circuit
• Clock selector
• Clock selection register (CKSCR)
• Oscillation stabilization wait interval selector
■ Block diagram of the clock generation block
Figure 4.2-1 shows a block diagram of the clock generation block.
Figure 4.2-1 also includes the standby control circuit and timebase timer circuit.
Low power mode control register (LPMCR)
STP
SLP
SPL
RST
TMD
CG1
CG0 RESV
RSTX Pin
Pin high
impedance
control circuit
Pin Hi-z control
Internal reset
generation
circuit
Internal reset
CPU intermittent
operation selecter
Select intermittent cycles
CPU clock
control circuit
Release reset
CPU clock
RST
3
Stop and sleep signals
Standby control
circuit
Cancel interrupt
Stop signal
Machine clock
Peripheral clock
control circuit
Oscillation stabiliz-ation wait is passed
Clock generator
Peripheral clock
Clock selector
Oscillation stabilization
wait interval selector
3
2
x1 x2 x3 x4 x6
PLL multipiler
circuit
RESV MCM WS1
WS0 RESV MCS
CS1
CS0
Clock selection register (CKSCR)
X0
Divideby-2
Pin
Main clock
X1
Pin
Divideby-512
Divideby-2
CS2
PLL Clock control
register (PCKCR)
Divideby-4
Divideby-2
Divideby-2
Timebase timer
System clock
generation circuit
Figure 4.2-1 Block diagram of the clock generation block
80
MB90820 series
● System clock generation circuit
The system clock generation circuit generates an oscillation clock (HCLK) from an external
oscillator attached to it. Alternatively, an external clock can be input to this circuit.
● PLL multiplier circuit
The PLL multiplier circuit multiplies the oscillation clock through PLL oscillation and supplies a
clock that is a multiple of the frequency to the CPU clock selector.
● Clock selector
From among the main clock and five different PLL clocks, the clock selector selects the clock
that is supplied to the CPU and peripheral clock control circuits.
● Clock selection register (CKSCR) and PLL clock control register (PCKCR)
The clock selection register is used to set switching between the oscillation clock and a PLL
clock, selection of an oscillation stabilization wait interval, and selection of a PLL clock multiplier.
● Oscillation stabilization wait interval selector
This selector selects an oscillation stabilization wait interval for the oscillation clock when stop
mode is released or when a watchdog timer reset occurs. Selection is made from among three
kinds timebase timer output. In all other cases, an oscillation stabilization wait interval is not
selected.
MB90820 series
81
4.3
Clock Selection Registers
The clock selection registers consist of Clock Selection Register (CKSCR) and PLL
Clock Control Register (PCKCR).
■ Clock Selection Registers
Figure 4.3-1 shows the clock selection register (CKSCR) and PLL clock control register
(PCKCR).
Address: 0000A1H
Read / Write :
Initial value :
Address: 00002FH
Read / Write :
Initial value :
(R)
(W)
(R/W)
-
RESV
MCM
WS1
WS0
RESV
MCS
CS1
CS0
(R)
1
(R)
1
(R/W)
1
(R/W)
1
(R/W)
1
(R/W)
1
(R/W)
0
(R/W)
0
-
-
-
-
X
X
X
X
RESV RESV RESV
(W)
0
(W)
0
(W)
0
CS2
CKSCR
PCKCR
(W)
0
: Read only
: Write only
: Read / write
: Unused
Figure 4.3-1 Clock selection registers
82
MB90820 series
Memo
MB90820 series
83
4.3.1 Clock Selection Register (CKSCR)
The clock selection register (CKSCR) is used to set switching between the main clock
and a PLL clock, selection of an oscillation stabilization wait interval, and selection of a
PLL clock multiplier.
■ Configuration of the clock selection register (CKSCR)
Figure 4.3.1-1 shows the configuration of the clock selection register (CKSCR). Table 4.3.1-1
describes the function of each bit of the clock selection register (CKSCR).
Address
0000A1H
bit15
bit14
bit10
bit9
bit8
RESV MCM WS1
WS0 RESV MCS
CS1
CS0
R/W
R/W
R/W
R/W
R
bit13
R/W
bit12
bit11
R/W
R/W
bit7
(LPMCR)
CS1 CS0
Initial value
11111100B
Multiplier selection bits
0
0
0
1
Refer to PLL clock control register
1
0
(PCKCR)
1
1
Machine clock selection bit
MCS
0
PLL clock selected.
1
Main clock selected.
WS1 WS0
Oscillation stabilization wait interval selection bits
The corresponding time interval for an oscillation clock
frequency of 4 MHz is given in parentheses.
0
0
210/ HCLK (Approx. 0.256ms)
0
1
2 / HCLK (Approx. 2.05ms)
1
0
2 / HCLK (Approx. 4.10ms)
1
1
2 / HCLK (Approx. 8.19ms)*
13
14
15
MCM
Machine clock indication bit
0
A PLL clock is used as the machine clock.
1
The main clock is used as the machine clock.
RESV
HCLK: Oscillation clock frequency
R/W: Read/write
R:
Read only
-:
Unused
: Initial value
bit0
Reserved bit
1 must always be written to these bits.
16
* At power-on reset, the oscillation stabilization wait interval is 2 /HCLK.
Figure 4.3.1-1 Configuration of the clock selection register (CKSCR)
84
MB90820 series
<Check>
If the machine clock selection bit is not set, the main clock is used as the machine clock.
Table 4.3.1-1 Function description of each bit of the clock selection register (CKSCR)
Bit name
bit15
bit11
RESV:
Reserved bit
Function
<Caution>
• 1 must always be written to these bits.
• This bit indicates whether the main clock or a PLL clock has been selected
bit14
MCM:
Machine clock
indication bit
as the machine clock.
• When this bit is set to 0, a PLL clock has been selected. When it is set to
1, the main clock has been selected.
• If MCS = 0 and MCM = 1, the PLL clock oscillation stabilization wait period
is in effect.
• These bits select an oscillation stabilization wait interval of the oscillation
bit13
bit12
clock after stop mode has been released.
WS1, WS0:
• These bits are initialized to 11B by all reset causes.
Oscillation
<Caution>
stabilization wait
The oscillation stabilization wait interval must be set to a value appropriate
interval
for the oscillator used. See Section 3.2, "Reset Causes and Oscillation
selection bits
Stabilization Wait Intervals".
[Reference]
The oscillation stabilization period for all PLL clocks is fixed at 214/HCLK.
• This bit specifies whether the main clock or a PLL clock is selected as the
machine clock.
• When this bit is 0, a PLL clock is selected. When this bit is 1, the main
clock is selected.
• If this bit has been set to 1 and 0 is written to it, the oscillation stabilization
bit10
bit9
bit8
MCS:
Machine clock
selection bit
CS1, CS0:
Multiplier
selection bits
wait interval for the PLL clock starts. As a result, the timebase timer is
automatically cleared, and the TBOF bit of the timebase timer control
register (TBTC) is also cleared.
• For PLL clocks, the oscillation stabilization period is fixed at 214/HCLK (the
oscillation stabilization wait interval is approx. 2 ms for an oscillation clock
frequency of 4 MHz).
• When the main clock has been selected, the operating clock frequency is
the frequency of the oscillation clock divided by 2 (e.g., the operating clock
is 2 MHz when the oscillation clock frequency is 4 MHz).
• This bit is initialized to 1 by power-on or watchdog reset.
<Caution>
When the MCS bit is 1, write 0 to it only when the timebase timer interrupt
is masked by the TBIE bit of the timebase timer control register (TBTC) or
the interrupt level register (ILM). For 8 machine cycles after 1 is written to
the MCS bit, writing 0 to it may be disabled. Write to the bit after 8
machine cycles have passed.
• These bits, combine with CS2 bit of PCKCR, select a PLL clock multiplier.
• Selection can be made from among five different multipliers.
• These bits are initialized to 00B by all reset causes.
•
Refer to PCKCR for the relationship between setting CS2, CS1 and CS0
bits and the PLL clock multiplier selection,
<Caution>
When the MCS bit is 0, writing to these bits is not allowed. Write to the
CS1 and CS0 bits only after setting the MCS bit to 1 (main clock mode).
HCLK: Oscillation clock frequency
MB90820 series
85
4.3.2 PLL Clock Control Register (PCKCR)
The PLL clock control register (PCKCR), combine with CS1 and CS0 bits in CKSCR, is
used to select a PLL clock multiplier.
■ Configuration of the PLL clock control register (PCKCR)
Figure 4.3.2-1 shows the configuration of the PLL clock control register (PCKCR). Table 4.3.2-1
describes the function of each bit of the PLL clock control register (PCKCR).
Address: 00002FH
-
-
-
-
RESV RESV RESV
X
X
X
X
(W)
0
CS2
(W)
: Write only
-
: Unused
(W)
0
(W)
0
CS2
PCKCR
(W)
0
Multiplier selection bit
0
Select PLL clock as 1 to 4 times the oscillator clock
depending on CS1 and CS0 bit of CKSCR.
1
Possible to select six times the oscillator clock as
PLL clock depending on CS1 and CS0 bit of CKSCR.
: Initial value
Figure 4.3.2-1 Configuration of the PLL clock control register (PCKCR)
86
MB90820 series
Table 4.3.2-1 Function description of each bit of the PLL clock control register (PCKCR)
Bit name
Function
bit 15
to
bit 12
Not used
• When read, the value is undefined.
• Writing has no effect on operation.
bit 11
to
bit 9
Reserved
• When read, the value is undefined.
• Always write “0” to these bits
•
•
•
•
•
bit8
CS2:
Multiplier
selection bit
These bits, and CS2 bit of PCKCR, select a PLL clock multiplier.
Selection can be made from among five different multipliers.
This bit is initialized to “0” by all reset causes.
The read value is undefined.
Recommended setting of CS2, CS1 and CS0 bits:
CS2
CS1
CS0
0
0
0
1 x HCLK (4 MHz)
0
0
1
2 x HCLK (8 MHz)
0
1
0
3 x HCLK (12 MHz)
0
1
1
4 x HCLK (16 MHz)
1
1
0
6 x HCLK (24 MHz)
( other )
PLL clock multiplex time
Setting not allowed
<Caution>
When the MCS bit of CKSCR is 0, writing to this bit is not allowed. Write to
the CS2 bits only after setting the MCS bit of CKSCR to 1 (main clock
mode).
MB90820 series
87
4.4
Clock Mode
Two clock modes are provided: main clock mode and PLL clock mode.
■ Main clock mode and PLL clock mode
● Main clock mode
In main clock mode, the main clock, whose frequency is the oscillation clock divided by 2, is
used as the operating clock for the CPU and peripheral resources, and the PLL clocks are
disabled.
● PLL clock mode
In PLL clock mode, a PLL clock is used as the operating clock for the CPU and peripheral
resources. A PLL clock multiplier is selected with the clock selection register (CKSCR: CS1 and
CS0) and PLL clock control register(PCKCR: CS2).
■ Clock mode transition
Switching between main clock mode and PLL clock mode is done by writing to the MCS bit of
the clock selection register (CKSCR).
● Switching from main clock mode to PLL clock mode
When the MCS bit of CKSCR is 1 and 0 is written to it, the switch from the main clock to a PLL
clock occurs after the PLL clock oscillation stabilization wait period (214/HCLK).
● Switching from PLL clock mode to main clock mode
When the MCS bit of CKSCR is 0 and 1 is written to it, the switch from the PLL clock to the main
clock occurs when the edges of the PLL clock and the main clock coincide (after 1 to 12 PLL
clocks).
<Check>
Even though the MCS bit of CKSCR is rewritten, machine clock switching does not occur
immediately. When operating a resource that depends on the machine clock, make sure that
machine clock switching has been done by referring to the MCM bit of CKSCR before
operating the resource.
■ Selection of a PLL clock multiplier
Writing a value from “000 B” to “011B” or “110B” to the CS2 bit of PCKCR, the CS1 and CS0 bits
of CKSCR selects one to the five PLL clock multipliers.
■ Machine clock
The machine clock may be either a PLL clock output from the PLL multiplier circuit or the clock
that is the source oscillation frequency divided by 2. This machine clock is supplied to the CPU
and peripheral functions.
Either the main clock or a PLL clock can be selected by writing to the MCS bit of CKSCR.
88
MB90820 series
Figure 4.4-1 shows the status change caused by the machine clock switching.
Power-on
(1)
Main
MCS = 1
MCM = 1
CS2, CS1, CS0 = xxx
Main
PLLx
MCS = 0
MCM = 1
(7)
CS2, CS1, CS0 = xxx
(2)
(3)
(4)
(5)
(6)
PLL1
Main
(8) MCS = 1
MCM = 0
CS2, CS1, CS0 = 000
PLL1: Multiplied
by 1
MCS = 0
(7) MCM = 0
CS2, CS1, CS0 = 000
(8)
PLL2
Main
MCS = 1
MCM = 0
CS2, CS1, CS0 = 001
(8)
PLL3
Main
MCS = 1
MCM = 0
CS2, CS1, CS0 = 010
(8)
PLL4
Main
MCS = 1
MCM = 0
CS2, CS1, CS0 = 011
(8)
PLL6
Main
MCS = 1
MCM = 0
CS2, CS1, CS0 = 110
PLL2: Multiplied
by 2
(7) MCS = 0
MCM = 0
CS2, CS1, CS0 = 001
PLL3: Multiplied
by 3
(7) MCS = 0
MCM = 0
CS2, CS1, CS0 = 010
(7)
PLL4: Multiplied
by 4
MCS = 0
MCM = 0
CS2, CS1, CS0 = 011
PLL6: Multiplied
by 4
MCS = 0
(7) MCM = 0
CS2, CS1, CS0 = 110
(1) The MCS bit is cleared.
(2) The PLL clock oscillation stabilization wait ends with CS2, CS1 and CS0 = 000.
(3) The PLL clock oscillation stabilization wait ends with CS2, CS1 and CS0 = 001.
(4) The PLL clock oscillation stabilization wait ends with CS2, CS1 and CS0 = 010.
(5) The PLL clock oscillation stabilization wait ends with CS2, CS1 and CS0 = 011.
(6) The PLL clock oscillation stabilization wait ends with CS2, CS1 and CS0 = 110.
(7) The MCS bit is set (including also hardware standby and watchdog timer resets).
(8) PLL clock and main clock synchronization timing.
MCS:
Machine clock selection bit of CKSCR
MCM:
Machine clock indication bit of CKSCR
CS1, CS0: Multiplier selection bits of CKSCR
CS2:
Multiplier selection bit of PCKCR
Figure 4.4-1 Status change diagram for machine clock selection
<Check>
The initial value for the machine clock setting is main clock (MCS of CKSCR = 1).
MB90820 series
89
4.5
Oscillation Stabilization Wait Interval
When the power is turned on, when stop mode is released, or when a watchdog timer
reset occurs, the oscillation clock starts, oscillation is unstable initially. Therefore, an
oscillation stabilization wait interval is required. When the switch from the main clock
to a PLL clock occurs, an oscillation stabilization wait interval is also required when
PLL oscillation starts.
■ Oscillation stabilization wait interval
Ceramic and crystal oscillators generally require an oscillation stabilization wait interval of a few
to several dozen milliseconds until they stabilize at their natural frequency when oscillation
starts.
For this reason, CPU operation is not allowed as soon as oscillation starts and is allowed only
after full stabilization of oscillation. After the oscillation stabilization wait interval has elapsed, the
clock is supplied to the CPU.
Because the oscillation stabilization time depends on the type of the oscillator (crystal, ceramic,
etc.), the proper oscillation stabilization wait interval for the oscillator used must be selected. An
oscillation stabilization wait interval is selected by setting the clock selection register (CKSCR).
In a switch from the main clock to a PLL clock, the CPU continues to operate on the main clock
during the oscillation stabilization wait interval. After this interval, the operating clock switches to
the PLL clock.
Figure 4.5-1 shows the operation after oscillation starts.
Oscillator-activated Oscillation stabilization Normal operation start
wait interval
oscillation time
or change to PLL clock
Start of oscillation
Stable oscillation
Figure 4.5-1 Operation when oscillation starts
90
MB90820 series
4.6
Connection of an Oscillator or an External Clock to the
Microcontroller
The F2MC-16LX microcontroller contains a system clock generation circuit.
Connecting an external oscillator to this circuit generates the system clock.
Alternatively, an externally generated clock can be input to the microcontroller.
■ Connection of an oscillator or an external clock to the microcontroller
● Example of connecting a crystal or ceramic oscillator to the microcontroller
Connect a crystal or ceramic oscillator as shown in the example in Figure 4.6-1.
X0
MB90820 series
X1
Figure 4.6-1 Example of connecting a crystal or ceramic oscillator to the microcontroller
● Example of connecting an external clock to the microcontroller
As shown in Figure 4.6-2, connect an external clock to pin X0. Pin X1 must be open.
X0
MB90820 series
Open
X1
Figure 4.6-3 Example of connecting an external clock to the microcontroller
MB90820 series
91
92
MB90820 series
CHAPTER 5
LOW POWER CONSUMPTION MODE
This chapter describes the low power consumption mode of MB90820 series
microcontrollers.
5.1 Low Power Consumption Mode
5.2 Block Diagram of the Low Power Consumption Control Circuit
5.3 Low Power Consumption Mode Control Register (LPMCR)
5.4 CPU Intermittent Operation Mode
5.5 Standby Mode
5.6 State Change Diagram
5.7 State of Pins in Standby Mode and during Reset
5.8 Usage Notes on Low Power Consumption Mode
MB90820 series
93
5.1
Low Power Consumption Mode
F2MC-16LX microcontrollers have the following CPU operating modes, any of which
can be used depending on the operating clock selection and clock operation control:
• Clock mode (PLL clock mode and main clock mode)
• CPU intermittent operation mode (PLL clock intermittent operation mode and
main clock intermittent operation mode)
• Standby mode (sleep, timebase timer and stop modes)
All modes other than PLL clock mode are low power consumption mode.
■ CPU operating modes and current consumption
Figure 5.1-1 shows the relation between the CPU operating modes and current consumption
Current consumption
Several tens
of mA
CPU operating
mode
Multiplied-by-six clock
PLL clock mode
Multiplied-by-four clock
Multiplied-by-three clock
Multiplied-by-two clock
Multiplied-by-one clock
Multiplied-by-six clock
PLL clock intermittent
operation mode
Multiplied-by-four clock
Multiplied-by-three clock
Multiplied-by-two clock
Multiplied-by-one clock
Main clock mode (1/2 clock mode)
Main clock intermittent operation mode
Several mA
Standby mode
Sleep mode
Timebase timer mode
Stop mode
Several uA
Low power consumption mode
Note:
This figure is only an indication of the degree of power consumption for each mode. Actual current consumption values
may not agree with those in the figure.
Figure 5.1-1 CPU operating modes and current consumption
94
MB90820 series
■ Clock mode
● PLL clock mode
A PLL clock that is a multiple of the oscillation clock (HCLK) frequency is used to operate the
CPU and peripheral functions.
● Main clock mode
The main clock, with a frequency one-half that of the oscillation clock (HCLK), is used to operate
the CPU and peripheral functions. In main clock mode, the PLL multiplier circuit is inactive.
[Reference]
See Section 4.1, "Clock", for details about clock mode.
■ CPU intermittent operation mode
CPU intermittent operation mode causes the CPU to operate intermittently, while high-speed
clock pulses are supplied to peripheral functions, reducing power consumption. In CPU
intermittent operation mode, intermittent clock pulses are only applied to the CPU when it is
accessing a register, internal memory, a peripheral function, or an external unit.
■ Standby mode
In standby mode, the low power consumption control circuit stops supplying the clock to the CPU
(sleep mode) or the CPU and peripheral functions (timebase timer mode), or stops the oscillation
clock itself (stop mode), reducing power consumption.
● PLL sleep mode
PLL sleep mode is activated to stop the CPU operating clock when the microcontroller enters
PLL clock mode; other components continue to operate on the PLL clock.
● Main sleep mode
Main sleep mode is activated to stop the CPU operating clock when the microcontroller enters
main clock mode; other components continue to operate on the main clock.
● PLL timebase timer mode
PLL timebase timer mode causes microcontroller operation, with the exception of the oscillation
clock, PLL clock and timebase timer, to stop. All functions other than the timebase timer are
deactivated.
● Main timebase timer mode
Main timebase timer mode causes microcontroller operation, with the exception of the oscillation
clock, main clock and the timebase timer, to stop. All functions other than the timebase timer are
deactivated.
● Stop mode
Stop mode causes the source oscillation to stop. All functions are deactivated.
<Check>
Because stop mode turns the oscillation clock off, this mode saves most power while data is
being retained.
MB90820 series
95
5.2
Block Diagram of the Low Power Consumption Control
Circuit
The low power consumption control circuit consists of the following seven blocks:
• CPU intermittent operation selector
• Standby clock control circuit
• CPU clock control circuit
• Peripheral clock control circuit
• Pin high-impedance control circuit
• Internal reset generation circuit
• Low power consumption mode control register (LPMCR)
■ Block diagram of the low power consumption control circuit
Figure 5.2-1 shows the block diagram of the low power consumption control circuit.
Low power mode control register (LPMCR)
STP
SLP
SPL
RST
TMD
CG1
CG0 RESV
RSTX Pin
Pin high
impedance
control circuit
Pin Hi-z control
Internal reset
generation
circuit
Internal reset
CPU intermittent
operation selecter
Select intermittent cycles
CPU clock
control circuit
Release reset
CPU clock
RST
3
Stop and sleep signals
Standby control
circuit
Cancel interrupt
Stop signal
Machine clock
Peripheral clock
control circuit
Oscillation stabiliz-ation wait is passed
Clock generator
Peripheral clock
Clock selector
Oscillation stabilization
wait interval selector
3
2
x1 x2 x3 x4 x6
PLL multipiler
circuit
RESV MCM WS1 WS0 RESV MCS
CS1
CS0
X0
Divideby-2
Pin
Main clock
X1
Pin
Divideby-512
Divideby-2
CS2
PLL Clock control
register (PCKCR)
Clock selection register (CKSCR)
Divideby-4
Divideby-2
Divideby-2
Timebase timer
System clock
generation circuit
Figure 5.2-1 Block diagram of the low power consumption control circuit
96
MB90820 series
● CPU intermittent operation selector
This selector selects the number of clock pulses the CPU is to be halted during CPU intermittent
operation mode.
● Standby control circuit
The standby control circuit controls the CPU clock control circuit and the peripheral clock control
circuit, and turns the low power consumption mode on and off.
● CPU clock control circuit
This circuit controls the clocks supplied to the CPU. This circuit controls the clocks supplied to
peripheral functions for the peripheral clock control.
● Peripheral clock control circuit
This circuit controls the clocks supplied to peripheral functions.
● Pin high-impedance control circuit
This circuit makes the external pins high-impedance when the microcontroller enters timebase
timer mode and stop mode.
For the pins with the pull-up option, this circuit disconnects the pull-up resistor when the
microcontroller enters stop mode.
● Internal reset generation circuit
This circuit generates an internal reset signal.
● Low power consumption mode control register (LPMCR)
This register is used to switch to and release standby mode and to set the CPU intermittent
operation function.
MB90820 series
97
5.3
Low Power Consumption Mode Control Register (LPMCR)
The low power consumption mode control register (LPMCR) switches to or releases
low power consumption mode. It is also used to set the number of CPU clock pulses
the CPU is to be halted during CPU intermittent mode.
■ Low power consumption mode control register (LPMCR)
Figure 5.3-1 shows the configuration of the low power consumption mode control register
(LPMCR).
bit15
Address
0000A0H
(CKSCR)
bit7
bit6
bit5
bit4
STP
SLP
SPL
W
W
R/W
bit3
bit2
RST TMDX CG1
W
W
R/W
bit0
bit1
CG0 RESV
R/W
RESV
Initial value
00011000B
R/W
Reserved bit
1 must always be written to this bit.
CPU halt clock pulses selection bits
CG1 CG0
0
0
0 clock pulse (CPU clock = Peripheral clock)
0
1
9 clock pulses (CPU clock: Peripheral clock = 1: 3 to 4 approx.)
1
0
17 clock pulses (CPU clock: Peripheral clock = 1: 5 to 6 approx.)
1
1
33 clock pulses (CPU clock: Peripheral clock = 1: 9 to 10 approx.)
TMDX
Timebase timer bit
0
Switch to timebase timer mode
1
No change, no effect on operation
RST
Internal reset signal generation bit
0
Generates an internal reset signal of 3 machine cycles.
1
No change, no effect on operation
SPL
Pin state setting bit (for timebase timer mode and stop mode)
0
Retained
1
High-impedance
SLP
R/W:
W:
Read/write
Write-only
: Initial value
Sleep bit
0
No change, no effect on operation
1
Switch to sleep mode
STP
Stop bit
0
No change, no effect on operation
1
Switch to stop mode
Figure 5.3-1 Configuration of the low power consumption mode control register (LPMCR)
98
MB90820 series
Table 5.3-1 Function description of each bit of the low power consumption mode control
register (LPMCR)
Bit name
Function
STP:
Stop bit
•
•
•
•
•
This bit indicates switching to stop mode.
When 1 is written to this bit, a switch to stop mode.
Writing 0 to this bit has no effect on operation.
This bit is cleared to 0 by a reset or by release of stop state.
The read value of this bit is always 0.
bit6
SLP:
Sleep bit
•
•
•
•
•
This bit indicates switching to sleep mode.
When 1 is written to this bit, the mode switches to sleep mode.
Writing 0 to this bit has no effect on operation.
This bit is cleared to 0 by a reset or by release of sleep mode.
The read value of this bit is always 0.
bit5
SPL:
Pin state setting bit
(for timebase timer
mode and stop mode)
bit7
• This bit is enabled while either timebase timer mode or stop
bit4
RST:
Internal reset signal
generation bit
mode is in effect.
• When this bit is 0, the level of the external pins is retained.
• When this bit is 1, the status of the external pins changes to
high-impedance.
• This bit is initialized to 0 by a reset.
• When 0 is written to this bit, an internal reset signal of 3 machine
cycles is generated.
• Writing 1 to this bit has no effect on operation.
• The read value of this bit is always 1.
• This bit indicates switching to timebase timer mode.
• When 0 is written to this bit, the mode switches to timebase timer
bit3
TMDX:
Timebase timer bit
mode.
• Writing 1 to this bit has no effect on operation.
• This bit is set to 1 by a reset or by release of timebase timer
mode.
• The read value of this bit is always 1.
• These bits set the number of CPU halt clock pulses for the CPU
intermittent operation function.
bit2
bit1
CG1, CG0:
CPU halt clock pulses
selection bits
• The clock supplied to the CPU is stopped after the execution of
every instruction for the specified number of clock pulses.
• Selection can be made from among four different clock pulses.
• These bits are initialized to 00B by a power-on or watchdog timer
reset. Other resets do not initialize these bits.
bit0
RESV:
Reserved bit
<Caution>
1 must always be written to this bit.
Note:If “1” is written to the STP bit, SLP bit and 0 is written to TMDX bit at the same time, switching to stop
mode takes the highest priority, then timebase timer mode and sleep mode has the lowest priority.
MB90820 series
99
■ Access to the low power consumption mode control register
Switching to low power consumption mode (including stop mode and sleep mode) is performed
by writing to the low power consumption mode control register. Only the instructions listed in
Table 5.3-2 should be used for this purpose. If other instructions are used for switching to low
power consumption mode, operation cannot be assured. To control functions not listed in Table
5.3-2, any instruction can be used.
When word-length is used for writing to the low power consumption mode control register, even
addresses must be used. Writing with odd addresses to switch to low power consumption mode
may cause a malfunction.
Table 5.3-2 Instructions to be used for switching to low power consumption mode
100
MOV io,#imm8
MOV io,A
MOV @RLi+disp8,A
MOVW io,#imm16
MOVW io,A
MOVW @RLi+disp8,A
MOV dir,#imm8
MOV dir,A
MOV addr24,A
MOVW dir,#imm16
MOVW dir,A
MOVPW addr24,A
MOV eam,#imm8
MOV addr,A
MOV eam,Ri
MOV eam,A
MOVW eam,#imm16
MOVW addr16,A
MOVW eam,RWi
MOVW eam,AA
SETB io:bp
SETB dir:bp
SETB addr16:bp
MB90820 series
5.4
CPU Intermittent Operation Mode
CPU intermittent operation mode is used for intermittent operation of the CPU while
external buses and peripheral functions continue to operate at high speed. Its purpose
is to reduce power consumption.
■ CPU intermittent operation mode
CPU intermittent operation mode halts the supply of the clock to the CPU for a certain period.
The halt occurs after the execution of every instruction that accesses a register, internal memory
(ROM and RAM), I/O, peripheral functions and the external bus. Internal bus cycle activation is
therefore delayed. While a steady rate of peripheral clock pulses are supplied to the peripheral
functions, the rate of CPU execution is reduced, enabling processing with low power
consumption.
•
The CG1 and CG0 bits of the low power consumption mode control register (LPMCR) are
used to select the number of clock pulses per halt cycle of the clock supplied to the CPU.
•
External bus operation uses the same clock as that used for peripheral functions.
•
Instruction execution time in CPU intermittent mode can be calculated. A correction value
should be obtained by multiplying the number of times instructions that access a register,
internal memory, internal peripheral functions, and the external bus are executed by the
number of clock pulses per halt cycle. Add this correction value to the normal execution time.
Figure 5.4-1 shows the operating clock pulses during CPU intermittent operation mode.
Peripheral clock
CPU clock
Intermittent operation halt cycle
One instruction
execution cycle
Internal bus activation cycle
Figure 5.4-1 Clock pulses during CPU intermittent operation
MB90820 series
101
5.5
Standby Mode
Standby mode includes the sleep (PLL sleep and main sleep), timebase timer and stop
modes.
■ Operating status during standby mode
Table 5.5-1 summarizes the operating statuses during standby mode.
Table 5.5-1 Operation statuses during standby mode
Standby mode
Sleep
mode
PLL sleep
mode
MCS = 0
SLP = 1
Main sleep
mode
MCS = 1
SLP = 1
PLL timebase
timer mode
(SPL = 0)
Timebase
timer
mode
PLL timebase
timer mode
(SPL = 1)
Oscillation
Clock
CPU
Peripheral
Pin
Active
Active
Main/PLL stop
mode
(SPL = 0)
Main/PLL stop
mode
(SPL = 1)
*:
Release
event
Hold
MCS = 0
TMDX = 0
Active
Active
Hi-Z
Inactive *
Main timebase
timer mode
(SPL = 0)
Main timebase
timer mode
(SPL = 1)
Stop
mode
Condition
for switch
In-active
Hold
Reset
or
Interrupt
MCS = 1
STP = 1
Hi-Z
Hold
MCS = x
STP = 1
Inactive
Inactive
Inactive
Hi-Z
Only the timebase timer is active.
SPL: Pin state setting bit of low power consumption mode control register (LPMCR)
SLP: Sleep bit of LPMCR
STP: Stop bit of LPMCR
TMDX: Timebase timer bit of LPMCR
MCS: Machine clock selection bit of clock selection register (CKSCR)
Hi-Z: High-impedance
102
MB90820 series
5.5
Standby Mode
5.5.1 Sleep mode
Sleep mode causes the CPU operating clock to stop while other components continue
to operate.
When the low power consumption mode control register (LPMCR) indicates a switch to
sleep mode, a switch to PLL sleep mode occurs if PLL clock mode has been set.
Alternatively, a switch to main sleep mode occurs if main clock mode has been set.
■ Switching to sleep mode
Writing 1 to the SLP and TMDX bit of LPMCR and 0 to the STP bit of LPMCR triggers a switch to
sleep mode.
At this time, if the MCS bit of the clock selection register (CKSCR) is 0, the microcontroller enters
PLL sleep mode. If the MCS bit of CKSCR is 1, the microcontroller enters main sleep mode.
<Check>
Since the STP/TMDX bit setting overrides the SLP bit setting when 1 is written to the SLP,
STP and 0 to TMDX bit at the same time, the mode switches to stop/timebase timer mode.
● Data retention function
In sleep mode, the contents of dedicated registers, such as accumulators and internal RAM, are
retained.
● Operation during an interrupt request
Writing 1 to the SLP bit of LPMCR during an interrupt request does not trigger a switch to sleep
mode. If the CPU does not accept the interrupt, the CPU executes the next instruction. If the
CPU accepts the interrupt, CPU operation immediately branches to the interrupt processing
routine.
● Status of pins
During sleep mode, all pins retain the state they had immediately before the switch to sleep
mode. The once exceptions are the pins used for bus input/output or bus control.
■ Release of sleep mode
The low power consumption control circuit releases sleep mode. Releasing is caused by the
input of a reset or by an interrupt.
● Return to normal mode by a reset
When sleep mode is released by a reset, the microcontroller is placed in the reset state on
release from sleep mode.
MB90820 series
103
● Return to normal mode by an interrupt
If an interrupt request higher than level 7 is issued from a peripheral circuit during sleep mode,
sleep mode is released. After release, the CPU handles the interrupt as it would any other
interrupt. The CPU executes processing according to the settings of the I flag of the condition
code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR). If
that interrupt is accepted, the CPU executes interrupt processing. If the interrupt is not
accepted, the CPU resumes execution with the instruction that follows the instruction in which
switching to sleep mode was specified.
Figure 5.5.1-1 shows the release of sleep mode for an interrupt.
Interrupt from a peripheral circuit
Enable flag is set
INT occurs
(IL < 7)
No
Sleep mode is not
released
Yes
Execution of the
next instruction
Sleep mode is not
released
Yes
I=0
Sleep mode is
released
No
Yes
ILM < IL
Execution of the
next instruction
No
Interrupt execution
Figure 5.5.1-1 Release of sleep mode for an interrupt
<Check>
When interrupt processing is executed normally, the CPU first executes the instruction that
follows the instruction in which switching to sleep mode was specified. The CPU then
proceeds to interrupt processing.
● Return to normal mode from PLL sleep mode by an external reset
During PLL sleep mode, the main clock and the PLL clock generate clock pulses. Since an
external reset does not initialize the MCS bit in the clock selection register (CKSCR) to 1, PLL
clock mode remains selected (MCS of CKSCR = 0). On return from PLL sleep mode by an
external reset, the CPU starts operation using the PLL clock immediately after PLL sleep mode
is released as shown in Figure 5.5.1-2.
104
MB90820 series
RSTX pin
Sleep mode
Main clock
Oscillating
PLL clock
Oscillating
PLL clock
CPU clock
CPU operation
Inactive
Sleep mode released.
Reset sequence
Execution
Reset cleared.
Figure 5.5.1-2 Release of PLL sleep mode (by external reset)
MB90820 series
105
5.5
Standby Mode
5.5.2 Timebase timer mode
Timebase timer mode causes the microcontroller operation to stop with the exception
of the source oscillation and the timebase timer. All functions other than timebase
timer are deactivated.
■ Switching to timebase timer mode
Writing 0 to the TMDX and STP bit of LPMCR triggers a switch to timebase timer mode.
At this time, if the MCS bit of the clock selection register (CKSCR) is 0, the microcontroller enters
PLL timebase timer mode. If the MCS bit of CKSCR is 1, the microcontroller enters main
timebase timer mode.
<Check>
Since the STP bit setting overrides the TMDX bit setting when 0 is written to the TMDX and
STP bits at the same time, the mode switches to stop mode.
● Data retention function
In timebase timer mode, the contents of dedicated registers, such as accumulators and internal
RAM, are retained.
● Operation during an interrupt request
Writing 0 to the TMDX bit of LPMCR during an interrupt request does not trigger switching to
timebase timer mode.
● Status of pins
Selection of whether the external pins retain the state they had immediately before switching to
timebase timer mode or go to high-impedance with switching to this mode can be controlled by
the SPL bit of LPMCR.
■ Release of timebase timer mode
The low power consumption control circuit releases timebase timer mode. Release is caused by
input of a reset or an interrupt. If timebase timer mode is released by a reset, the microcontroller
is placed in the reset state after its release from timebase timer mode.
● Return to normal mode by a reset
If timebase timer mode is released by a reset, the microcontroller is placed in the reset state
after release from timebase timer mode. The timerbase timer mode is initialized to the main
clock mode by a reset.
Figure 5.5.2-1 shows the operation for return to normal mode from timebase timer mode
triggered by an external reset.
106
MB90820 series
RSTX pin
Timebase timer
mode
Main clock
Oscillating
PLL clock
Main clock
CPU clock
CPU operation
Inactive
Reset sequence
Execution
Reset cleared.
Timebase timer mode released.
Figure 5.5-2-1 Release of timebase timer mode (by an external reset)
● Return to normal mode by an interrupt
If an interrupt request higher than level 7 is issued from a peripheral circuit in timebase timer
mode (when IL2, IL1 and IL0 of the interrupt control register (ICR) are set to a value other than
111B), the low power consumption control circuit releases timebase timer mode. After the
release, the CPU handles the interrupt as it would any other interrupt. The CPU executes
processing according to the settings of the I flag of the condition code register (CCR), interrupt
level mask register (ILM), and interrupt control register (ICR). If the interrupt is accepted, the
CPU executes interrupt processing. If the interrupt is not accepted, the CPU resumes execution
with the instruction that follows the instruction in which switching to timebase timer mode was
specified.
<Check>
When interrupt processing is executed normally, the CPU first executes the instruction that
follows the instruction in which switching to timebase timer mode was specified. The CPU
then proceeds to interrupt processing.
MB90820 series
107
5.5
Standby Mode
5.5.3 Stop mode
Stop mode causes the source oscillation to stop and deactivates all functions. It
therefore saves the most power saving while data is being retained.
■ Switching to stop mode
Writing 1 to the STP bit of LPMCR triggers a switch to stop mode.
At this time, if the MCS bit of the clock selection register (CKSCR) is 0, the microcontroller enters
PLL stop mode. If the MCS bit of CKSCR is 1, the microcontroller enters main stop mode.
● Data retention function
In stop mode, the contents of dedicated registers, such as accumulators and internal RAM, are
retained.
● Operation during an interrupt
Writing 1 to the STP bit of LPMCR during an interrupt request does not trigger switching to stop
mode.
● Pin state setting
Selection of whether the external pins retain the state they had immediately before switching to
stop mode or go to high-impedance with switching to stop mode can be controlled by the SPL bit
of LPMCR.
■ Release of stop mode
The low power consumption control circuit releases stop mode. The release is caused by input
of a reset or by an interrupt.
Because the oscillation of the operating clock is halted before return to normal mode from stop
mode, the low power consumption control circuit puts the microcontroller into the oscillation
stabilization wait state, then releases stop mode.
● Return to normal mode by a reset
When stop mode is released by a reset cause, the microcontroller is placed in the oscillation
stabilization wait and reset state after release from stop mode. The reset sequence proceeds
after the oscillation stabilization wait interval has elapsed.
● Return to normal mode by a interrupt
If an interrupt request higher than level 7 is issued from a peripheral circuit during stop mode
(when IL2, IL1 and IL0 of the interrupt control register (ICR) are set to a value other than 111B),
the low power consumption control circuit releases stop mode. After release, the CPU handles
the interrupt as it would any other interrupts. However, the CPU starts after the main clock
oscillation stabilization wait interval specified by the WS1 and WS0 bits of the clock selection
register (CKSCR) has elapsed. The CPU executes processing according to the settings of the I
flag of the condition code register (CCR), interrupt level mask register (ILM), and interrupt control
register (ICR). If the interrupt is accepted, the CPU executes interrupt processing. If the
interrupt is not accepted, the CPU resumes the execution with the instruction that follows the
instruction in which switching to stop mode was specified.
<Check>
108
When interrupt processing is executed normally, the CPU first executes the instruction that
follows the instruction in which switching to stop mode was specified. The CPU then
MB90820 series
proceeds to interrupt processing.
Figure 5.5.3-1 shows the operation of return to normal mode from stop mode.
RSTX pin
Stop mode
Main clock
Oscillation stabilization wait time
Oscillating
PLL clock
Oscillation stabilization wait time
Oscillating
CPU clock
Main/PLL clock
CPU operation
Inactive
Stop mode released
Reset
sequence
Execution
Reset cleared
Figure 5.5.3-1 Release of main stop mode (by external reset)
MB90820 series
109
5.6
State Change Diagram
Figure 5.6-1 shows the state change diagram of F²MC-16LX operation and gives change
conditions.
■ State change diagram
Power-on
Main clock mode
Source Osc. stabilization wait and
reset state
[9]
Main clock
reset state
[1]
[4]
[13]
Source clock osc.
stabilization wait
state
[8]
[2]
Main Stop
state
[11]
[5]
PLL stop
state
[16]
[18]
Source Osc. stabilization wait and
reset state
[23]
[6]
Main sleep
state
[22]
[20]
<1>
PLL run
state
<10>
[15]
[21]
Main run
state
[19]
[14]
[6]
[3]
[10]
[7]
Source clock osc.
stabilization wait
state
Main timebase timer
state
[12]
[7]
<3>
PLL sleep
state
<7>
<4>
<5>
PLL clock
reset state
<8>
PLL timebase
timer state
[17]
Main clock
reset state
PLL clock mode
Figure 5.6-1 State change diagram
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MB90820 series
■ Low power consumption mode operating states
Table 5.6-1 lists the operating states of low power consumption mode.
Table 5.6-1 Low power consumption mode operating states
Low power
consumption
mode
Condition
for
transition
Oscillation
Clock
CPU
Peripheral
Pin
Release
event
Main sleep
MCS = 1
SLP = 1
Active
Active
Inactive
Active
Active
Reset or
interrupt
PLL sleep
MCS = 0
SLP = 1
Active
Active
Inactive
Active
Active
Reset or
interrupt
Main/PLL
timebase timer
(SPL = 0)
MCS = x
TMDX = 0
Active
Active
Inactive
Inactive
Hold
Reset or
interrupt
Main/PLL
timebase timer
(SPL = 1)
MCS = x
TMDX = 0
Active
Active
Inactive
Inactive
Hi-Z
Reset or
interrupt
Main/PLL stop
(SPL = 0)
MCS = x
STP = 1
Inactive
Inactive
Inactive
Inactive
Hold
Reset or
interrupt
Main/PLL stop
(SPL = 1)
MCS = x
STP = 1
Inactive
Inactive
Inactive
Inactive
Hi-Z
Reset or
interrupt
● Clock mode switching and release (excluding standby mode)
Table 5.6-2 lists clock mode switching and release.
Table 5.6-2 Clock mode switching and release
Transition
Conditions
After power-on, transition to
the main run state
[1] Source clock oscillation stabilization wait interval ends. (Timebase
timer output)
[2] Reset input has been cleared.
Reset during main run state
[3] External reset, software reset, or watchdog timer reset
Transition from main run
state to PLL run state
[19] MCS = 0 (After PLL clock oscillation stabilization wait, switch to PLL
clock) *
Return to main run state from
PLL run state
[20] MCS = 1 (PLL clock deactivated)
Reset during PLL run state
[6] External reset or software reset ([7] After reset, return to PLL run
state)
[13] Watch dog reset ([2] After reset, return to main run state)
*: The microcontroller operates using the main clock during the PLL clock oscillation
stabilization wait state.
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111
● Switching to and release of standby mode
Table 5.6-3 lists switching to and release of standby mode.
Table 5.6-3 Switching to and release of standby mode
Transition
Transition to main sleep
mode
[21] SLP = 1, MCS = 1 (Transition from main run state)
[2] SLP =1, MCS = 1 (Transition from PLL run state)
Release of main sleep mode
[22] Interrupt input
[4] External reset
Transition to main stop mode
*
112
Conditions
[5] STP =1, MCS = 1 (Transition from main run state)
Transition to PLL stop mode
<10>STP =1, MCS = 0 (Transition from PLL run state)
Release of main stop mode
[7] Interrupt input ([10] indicates return to main run state after oscillation
stabilization wait)
[8] External reset ([9] indicates external reset during oscillation stabilization wait state)
Release of PLL stop mode
[14] Interrupt input ([15] indicates return to PLL run state after oscillation
stabilization wait)
[16] External reset ([18] indicates external reset during oscillation stabilization wait state)
Transition to PLL sleep mode
<1>SLP = 1, MCS = 0 (Transition from PLL run state)
<2>SLP = 1, MCS = 0 (Transition from main run state, switch to PLL
clock after PLL clock oscillation stabilization wait) *
Release of PLL sleep mode
<3>Interrupt input
<4>External reset
Transition to main timebase
timer mode
[6] STP = 1, MCS = 1 (Transition from main run state)
Transition to PLL timebase
timer mode
<5>STP = 1, MCS = 0 (Transition from PLL run state)
Release of main timebase
timer mode
[11] Interrupt input
[12] External reset ([2] After reset, return to main run state)
Release of PLL timebase
timer mode
<7>Interrupt input
<8>External reset ([7] After reset, return to PLL run state)
The microcontroller operates using the main clock during the PLL clock oscillation
stabilization wait state.
MB90820 series
5.7
State of Pins in Standby Mode and during Reset
The state of pins in standby mode and during reset are summarized below for each
memory access mode.
■ Software pull-up resistor
For pins with a pull-up resistor selected by software, the pull-up resistor is disconnected during L
level output.
■ State of pins in single-chip mode
Table 5.7-1 lists the state of pins in single-chip mode.
Table 5.7-1 State of pins in single-chip mode
Standby mode
Pin name
Stop
Reset
Sleep
SPL = 0
P00 ~ P07
P17
P20 ~ P27
P30 ~ P37
P40~P47
P50
P60 ~ P63
P70 ~ P77
P80 ~ P87
P10 ~ P16
P51
The preceding
state is retained*2
The preceding
state is retained*2
SPL = 1
Input shut
off*3 / output
Hi-Z
Input disabled /
output Hi-Z
Input enabled*1
*1 "Input enabled" means that the input function is enabled when corresponding external
interrupt pin is enable. Select either the pull-up or the pull-down option. Alternatively, an
external input is required. Pins used as output ports are the same as other ports.
*2 "The preceding state is retained" means that the state of the pin output existing immediately
before switching to this mode is retained. Note that input is disabled if the preceding state
was input.
•
"State of the pin output is retained" means that the pin retains the value output from an
operating internal peripheral unit or the value output from the port if the pin is used as a
port.
•
"Input disabled" means that the input to the pin is not accepted because the internal circuit
is inactive, although operation of the input gate adjacent to the pin is enabled.
*3 "Input shut off" indicates the state in which operation of the input gate adjacent to the pin is
disabled. "Output Hi-Z" means that the pin state is high-impedance because driving of the
pin driving transistor is disabled.
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5.8
Usage Notes on Low Power Consumption Mode
Note the following six items to use low power consumption mode:
• Switching to standby mode and interrupts
• Release of standby mode by an interrupt
• Setting of standby mode
• Release of stop mode
• Release of timebase timer mode
• Oscillation stabilization wait time
■ Notes on standby mode
● Switching to standby mode and interrupts
During an interrupt request to the CPU from a peripheral function, the CPU ignores the STP and
SLP bits of the low power consumption mode control register (LPMCR) even though 1 has been
written to these bits. Thus, switching to any standby mode is disabled (even after processing the
interrupt is completed, there is no switch to standby mode). If the interrupt level is higher than 7,
this action does not depend on whether the interrupt request is accepted by the CPU.
However, during execution of interrupt processing by the CPU, if the interrupt request flag for the
interrupt is cleared and no other interrupt requests have been issued, switching to standby mode
can be done.
● Release of standby mode caused by an interrupt
If an interrupt request higher than level 7 is issued from a peripheral function during the sleep,
timebase timer, or stop modes, the standby mode is released. This action does not depend on
whether the CPU accepts that interrupt.
After the release of standby mode, normal interrupt processing is performed. The CPU
branches to the interrupt handling routine provided that the priority of the interrupt request
indicated by the interrupt level setting bits (IL2, IL1 and IL0 of ICR) is higher than the interrupt
level mask register (ILM); and the interrupt enable flag (I) of the condition code register (CCR) is
set to 1 (enabled). If the interrupt is not accepted, the CPU starts the execution with the
instruction that follows the instruction in which switching to standby mode was specified.
When interrupt processing is executed normally, the CPU first executes the instruction that
follows the instruction in which switching to standby mode was specified. The CPU then
proceeds to interrupt processing. Depending on the condition when switching to standby mode
was performed, however, the CPU may proceed to interrupt processing before executing the
next instruction.
If the CPU should not branch to the interrupt processing routine immediately on return to normal
mode from standby mode, action must be taken to disable interrupts before standby mode is set.
● Setting of standby mode
When 1 is written to the STP bit and SLP bit of LPMCR at the same time, switching to standby
mode is performed. If the MCS bit of the clock selection register (CKSCR) is 0, switching to
timebase timer mode is performed; if this bit is 1, switching to stop mode is performed.
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MB90820 series
■ Release of stop mode
To use an external interrupt for releasing stop mode, use an input that has been set as an
interrupt input cause before the system enters stop mode. As an input cause, H level, L level,
rising edge or falling edge can be selected.
■ Release of timebase timer mode
When timebase timer mode is released, the microcontroller is placed in the PLL clock oscillation
stabilization wait state. If the PLL clock is not used, change the MCS bit of the clock selection
register (CKSCR) to 1 with the instruction that is to be executed immediately after a reset or on
return from an interrupt.
If an external interrupt is used to release timebase timer mode, the input cause can be selected
as H level, L level, rising edge or falling edge.
■ Oscillation stabilization wait interval
● Source clock oscillation stabilization wait interval
Because the oscillator for source oscillation is halted in stop mode, an oscillation stabilization
wait interval is required. A time period selected by the WS1 and WS0 bits of CKSCR is used as
the oscillation stabilization wait interval.
● PLL clock oscillation stabilization wait interval
The CPU may be working with the main clock and the PLL clock may be stopped. If the
microcontroller will enter a mode in which the CPU and peripheral functions work with the PLL
clock, the PLL clock initially enters the oscillation stabilization wait state. In this state, the CPU
still operates using the main clock.
The PLL clock oscillation stabilization wait interval is fixed at 214/HCLK (HCLK: oscillation clock
frequency).
However, this interval may range from 214/HCLK to 2 x 214/HCLK depending on the status of the
timebase timer, if the timebase timer is not cleared before the PLL clock oscillation stabilization
wait state is entered. (For example, return to the PLL run state from timebase timer mode
occurs because of an external reset.)
MB90820 series
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MB90820 series
CHAPTER 6
INTERRUPT
This chapter explains the interrupt and extended intelligent I/O service (EI2OS) in the
MB90820 series.
6.1 Interrupt
6.2 Interrupt Causes and Interrupt Vectors
6.3 Interrupt Control Registers and Peripheral Functions
6.4 Hardware Interrupt
6.5 Software Interrupt
6.6 Interrupt of Extended Intelligent I/O Service (EI²OS)
6.7 Exception Processing Interrupt
6.8 Stack Operations for Interrupt Processing
6.9 Sample Programs for Interrupt Processing
MB90820 series
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6.1
Interrupt
This chapter explains the interrupt and extended intelligent I/O service (EI2OS) in the
MB90820 series.
• Hardware interrupt
• Software interrupt
• Interrupt from extended intelligent I/O service (EI2OS)
• Exception processing
■ Interrupt types and functions
● Hardware interrupt
A hardware interrupt transfers control to a user-defined interrupt processing program in response
to an interrupt request from a peripheral function.
● Software interrupt
A software interrupt transfers control to a user-defined interrupt processing program triggered by
the execution of a dedicated software interrupt instruction (such as the INT instruction).
● Interrupt from extended intelligent I/O service (EI2OS)
The EI2OS function automatically transfers data between a peripheral function and memory.
Data transfer, which has ordinarily been executed by an interrupt processing program, can be
handled like a direct memory access (DMA). When the specified number of data transfers has
been terminated, the interrupt processing program is automatically executed.
An instruction from EI2OS is a type of hardware interrupt.
● Exception processing
Exception processing is basically the same as an interrupt. When an exception event (execution
of an undefined instruction) is detected on the instruction boundary, ordinary processing is
interrupted and exception processing is performed. This is equivalent to software interrupt
instruction INT10.
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MB90820 series
■ Interrupt operation
Figure 6.1-1 shows the activation and return processing for the four types of interrupt functions.
Main program
Is there
a valid hardware
interrupt
request?
String type (*1)
instruction being
executed
Interrupt activation/return
processing
EI2OS?
Fetch the next instruction and decode
INT instruction?
EI2OS
EI²OS processing
Software
interrupt/
exception
processing
Save the dedicated
register on the system
stack
Disable acceptance of
hardware interrupts
(I = 0)
Hardware
Interrupt
Specified
count terminated?
Alternatively, is there
an end request from the
peripheral
function?
Save the dedicated
register on the system
stack
Update the CPU interrupt processing level
(ILM)
RETI instruction?
Execute ordinary
instruction
Return
processing
Return the dedicated
register from the system
stack, call the interrupt
routine, and return to
the previous routine
Read the interrupt
vector, update PC and
PCB, and branch to
the interrupt routine
Repetition
of string type (*1) instruction completed?
Move the pointer to the
next instruction by PC
update
*1 When a string type instruction is being executed, the interrupt is evaluated in each step.
Figure 6.1-1 Overall flow of interrupt operation
MB90820 series
119
6.2
Interrupt Causes and Interrupt Vectors
The F2MC-16LX has functions for handling 256 types of interrupt causes. The 256
interrupt vector tables are allocated to the memory at the highest addresses. These
interrupt vectors are shared by all interrupts.
Software interrupt can use all these interrupt vectors (INT0 to INT256). Software
interrupt shares same interrupt vectors with the hardware interrupt and exception
processing interrupt. Hardware interrupt uses a fixed interrupt vector and interrupt
control register (ICR) for each peripheral function.
■ Interrupt vectors
Interrupt vector tables referenced during interrupt processing are allocated to the highest
addresses in the memory area (FFFC00H to FFFFFFH). Interrupt vectors share the same area
with EI2OS, exception processing, hardware and software interrupt.
Table 6.2-1 shows the assignment of interrupt numbers and interrupt vectors.
Table 6.2-1 Interrupt vectors
Software
interrupt
instruction
Vector
address L
Vector
address M
Vector
address H
Mode data
Interrupt
no.
Hardware interrupt
INT0
FFFFFCH
FFFFFD H
FFFFFEH
Not used
#0
None
:
:
:
:
:
:
:
INT7
FFFFE0H
FFFFE1H
FFFFE2H
Not used
#7
None
INT8
FFFFDCH
FFFFDD H
FFFFDEH
FFFFDFH
#8
(RESET vector)
INT9
FFFFD8H
FFFFD9H
FFFFDAH
Not used
#9
None
INT10
FFFFD4H
FFFFD5H
FFFFD6H
Not used
#10
<Exception processing>
INT11
FFFFD0H
FFFFD1H
FFFFD2H
Not used
#11
Hardware interrupt #0
INT12
FFFFCCH
FFFFCD H
FFFFCEH
Not used
#12
Hardware interrupt #1
INT13
FFFFC8H
FFFFC9H
FFFFCAH
Not used
#13
Hardware interrupt #2
INT14
FFFFC4H
FFFFC5H
FFFFC6H
Not used
#14
Hardware interrupt #3
:
:
:
:
:
:
:
INT254
FFFC04H
FFFC05H
FFFC06H
Not used
#254
None
INT255
FFFC00H
FFFC01H
FFFC02H
Not used
#255
None
[Reference]
Unused interrupt vectors should be set as the exception processing address.
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MB90820 series
■ Interrupt causes and interrupt vectors/interrupt control registers
Table 6.2-2 shows the relationship among interrupt causes (excluding software interrupt),
interrupt vectors, and interrupt control registers.
Table 6.2-2 Interrupt causes, interrupt vectors, and interrupt control registers
Interrupt cause
Interrupt control
register
Interrupt vector
EI2OS
support
Address
ICR
Address
Reset
X
#08
Number
08H
FFFFDCH
-
-
INT9 instruction
X
#09
09H
FFFFD8H
-
-
Exception processing
X
#10
0AH
FFFFD4H
-
-
A/D converter conversion termination
O
#11
0BH
FFFFD0H
Output compare channel 0 match
O
#12
0CH
FFFFCCH
ICR00
0000B0H*1
End of measurement by PWC timer 0 /
PWC timer 0 overflow
O
#13
0DH
FFFFC8H
ICR01
0000B1H*1
16-bit PPG timer 0
O
#14
0EH
FFFFC4H
Output compare channel 1 match
O
#15
0FH
FFFFC0H
16-bit PPG timer 1
O
#16
10H
FFFFBCH
ICR02
0000B2H*1
Output compare channel 2 match
O
#17
11H
FFFFB8H
16-bit reload timer 1 underflow
O
#18
12H
FFFFB4H
ICR03
0000B3H*1
Output compare channel 3 match
O
#19
13H
FFFFB0H
DTP/ext. interrupt channels 0/1 detection
O
14H
FFFFACH
ICR04
0000B4H*1
ICR05
0000B5H*1
ICR06
0000B6H*1
ICR07
0000B7H*1
ICR08
0000B8H*1
ICR09
0000B9H*1
ICR10
0000BAH*1
ICR11
0000BBH*1
ICR12
0000BCH*1
ICR13
0000BDH*1
ICR14
0000BEH*1
ICR15
0000BFH*1
DTTI
∆
#20
Output compare channel 4 match
O
#21
15H
FFFFA8H
DTP/ext. interrupt channels 2/3 detection
O
#22
16H
FFFFA4H
Output compare channel 5 match
O
#23
17H
FFFFA0H
End of measurement by PWC timer 1 /
PWC timer 1 overflow
O
#24
18H
FFFF9CH
DTP/ext. interrupt channels 4 detection
O
#25
19H
FFFF98H
DTP/ext. interrupt channels 5 detection
O
#26
1AH
FFFF94H
DTP/ext. interrupt channels 6 detection
O
#27
1BH
FFFF90H
DTP/ext. interrupt channels 7 detection
O
#28
1CH
FFFF8CH
Waveform generator 16-bit timer 0/1/2
underflow
∆
#29
1DH
FFFF88H
16-bit reload timer 0 underflow
O
#30
1EH
FFFF84H
16-bit free-running timer zero detect
∆
#31
1FH
FFFF80H
16-bit PPG timer 2
O
#32
20H
FFFF7CH
Input capture channels 0/1
O
#33
21H
FFFF78H
16-bit free-running timer compare clear
∆
#34
22H
FFFF74H
Input capture channels 2/3
O
#35
23H
FFFF70H
Timebase timer
∆
#36
24H
FFFF6CH
#37
25H
FFFF68H
#38
26H
FFFF64H
#39
27H
FFFF60H
#40
28H
FFFF5CH
#41
29H
FFFF58H
#42
2AH
FFFF54H
UART1 receive
∆
UART1 send
UART0 receive
UART0 send
Flash memory status
Delayed interrupt generator module
∆
∆
∆
Priority
*2
High
Low
2
O: Can be used and interrupt request flag is cleared by EI OS interrupt clear signal.
X: Cannot be used.
:
Can be used and support the EI2OS stop request.
∆: Usable when an interrupt cause that shares the ICR is not used.
MB90820 series
121
*1: -
For peripheral functions that share the ICR register, the interrupt level will be the same.
-
If the extended intelligent I/O service is to be used with a peripheral function that shares
the ICR register with another peripheral function, the service can be started by either of
the function. And if EI2OS clear is supported, both interrupt request flags for the two
interrupt causes are cleared by EI2OS interrupt clear signal. It is recommended to mask
either of the interrupt request during the use of EI2OS.
-
EI2OS service cannot be started multiple times simultaneously. Interrupt other than the
operating interrupt is masked during EI2OS operation. It is recommended to mask either
of the interrupt requests during the use of EI2OS.
*2: This priority is applied when interrupts of the same level occur simultaneously.
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MB90820 series
6.3
Interrupt Control Registers and Peripheral Functions
Interrupt control registers (ICR00 to ICR15) are located inside the interrupt controller.
The interrupt control registers correspond to all peripheral functions that have the
interrupt function. These registers control interrupts and the extended intelligent I/O
service (EI2OS).
■ Interrupt control registers
Table 6.3-1 lists the interrupt control registers and corresponding peripheral functions.
Table 6.3-1 Interrupt control registers
Address
Register
Abbreviation
Corresponding peripheral function
0000B0H
Interrupt control register 00
ICR00
A/D converter conversion termination, Output compare channel 0 match
0000B1H
Interrupt control register 01
ICR01
End of measurement by PWC timer 0 /PWC timer 0 overflow
0000B2H
Interrupt control register 02
ICR02
Output compare channel 1 match, 16-bit PPG timer 1
0000B3H
Interrupt control register 03
ICR03
Output compare channel 2 match, 16-bit reload timer 1 underflow
0000B4H
Interrupt control register 04
ICR04
Output compare channel 3 match, DTP/ext. interrupt channels 0/1 detection,
DTTI
0000B5H
Interrupt control register 05
ICR05
Output compare channel 4 match, DTP/ext. interrupt channels 2/3 detection
0000B6H
Interrupt control register 06
ICR06
Output compare channel 5 match, End of measurement by PWC timer 1 /
PWC timer 1 overflow
0000B7H
Interrupt control register 07
ICR07
DTP/ext. interrupt channels 4 detection, DTP/ext. interrupt channels 5 detection
0000B8H
Interrupt control register 08
ICR08
DTP/ext. interrupt channels 6 detection, DTP/ext. interrupt channels 7 detection
0000B9H
Interrupt control register 09
ICR09
Waveform generator 16-bit timer 0/1/2 underflow, 16-bit reload timer 0
underflow
0000BAH
Interrupt control register 10
ICR10
16-bit free-running timer zero detect, 16-bit PPG timer 2
0000BBH
Interrupt control register 11
ICR11
Input capture channels 0/1, 16-bit free-running timer compare clear
0000BCH Interrupt control register 12
ICR12
Input capture channels 2/3, Timebase timer
0000BDH Interrupt control register 13
ICR13
UART1 receive, UART1 send
0000BEH
Interrupt control register 14
ICR14
UART0 receive, UART0 send
0000BFH
Interrupt control register 15
ICR15
Flash memory status, Delayed interrupt generator module
■ Interrupt control register functions
All interrupt control registers (ICR) do the following:
• Set the interrupt level of the corresponding peripheral function
• Select ordinary interrupt or the extended intelligent I/O service as interrupt of the
corresponding peripheral function
• Select an extended intelligent I/O service (EI2OS) channel
• Display the status of the extended intelligent I/O service (EI2OS)
Some of the functions of the interrupt control registers (ICR) differ during writing and reading, as
shown in Figures 6.3-1 and 6.3-2.
<Check>
Do not use a read-modify-write instruction to access the interrupt control registers (ICR),
since operation will not be correct.
MB90820 series
123
6.3
Interrupt Control Registers and Peripheral Functions
6.3.1 Interrupt control registers (ICR00 to ICR15)
Interrupt control registers correspond to all peripheral functions that have the interrupt
function. The interrupt control registers control the processing when an interrupt
request occurs. The functions of these registers partially differ at writing and reading.
■ Interrupt control registers (ICR00 to ICR15)
Writing
Address
0000B0H
to
0000BFH
bit7
bit6
bit5
bit4
ICS3
ICS2
ICS1
ICS0
ISE
IL2
IL1
IL0
W
W
W
R/W
R/W
R/W
R/W
W
bit3
bit2
bit1
bit0
Initial value
00000111B
IL2
IL1
IL0
Interrupt level setting bit
0
0
0
Interrupt level 0 (highest)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Interrupt level 7 (no interrupt)
EI2OS enable bit
ISE
0
Activates the interrupt sequence when an interrupt occurs
1
Activates EI2OS when an interrupt occurs
EI2OS channel selection bit
ICS3 ICS2 ICS1 ICS0
R/W:
W:
Read/write
Write-only
: Initial value
Channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
000118H
0
0
1
1
3
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
Figure 6.3.1-1 Interrupt control registers (ICR00 to ICR15) during writing
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MB90820 series
Reading
bit7
Address
0000B0H
to
0000BFH
-
bit6
bit5
bit4
bit3
bit2
bit1
bit0
-
S1
S0
ISE
IL2
IL1
IL0
R
R
R/W
R/W
R/W
R/W
Initial value
XX000111B
IL2
IL1
IL0
Interrupt level setting bit
0
0
0
Interrupt level 0 (highest)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
EI2OS enable bit
ISE
R/W: Read/write
R: Write-only
- : Not used
X:
Undefined
: Initial value
Interrupt level 7 (no interrupt)
0
Activates the interrupt sequence when an interrupt occurs
1
Activates EI2OS when an interrupt occurs
S1
S0
EI2OS status
0
0
EI2OS operation in progress or EI2OS not activated
0
1
Stopped status due to count termination
1
0
Reserved
1
1
Stopped status due to a request from the peripheral function
Figure 6.3.1-2 Interrupt control registers (ICR00 to ICR15) during reading
MB90820 series
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6.3
Interrupt Control Registers and Peripheral Functions
6.3.2 Interrupt control register functions
The interrupt control registers (ICR00 to ICR15) consist of the following four functional
bits:
• Interrupt level setting bits (IL2 to IL0)
• Extended intelligent I/O service (EI2OS) enable bit (ISE)
• Extended intelligent I/O service (EI2OS) channel selection bits (ICS3 to ICS0)
• Extended intelligent I/O service (EI2OS) status (S1 to S0)
■ Configuration of interrupt control registers (ICR)
Figure 6.3.2-1 shows the configuration of the interrupt control register (ICR) bits.
Writing to interrupt control register (ICR)
Address
0000B0H
to
0000BFH
Reading of interrupt control register (ICR)
Address
0000B0H
to
0000BFH
Initial value
Initial value
R: Read-only
W: Write-only
- : Not used
Figure 6.3.2-1 Configuration of interrupt control registers (ICR)
[Reference]
•
The ICS3 to ICS0 bits are valid only when the extended intelligent I/O service (EI2OS) has
been activated. To activate EI2OS, set the ISE bit to 1. To not activate EI2OS, set the ISE
bit to 0. When EI2OS is not activated, setting ICS3 to ICS0 is optional.
•
ICS1 and ICS0 are valid only for writing. S1 and S0 are valid only for reading.
■ Interrupt control register functions
● Interrupt level setting bits (IL2 to IL0)
These bits set the interrupt level of the corresponding peripheral function. These bits are
initialized to level 7 (no interrupt) by a reset.
Table 6.3.2-1 shows the correspondence between the interrupt level setting bits and interrupt
levels.
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MB90820 series
Table 6.3.2-1 Correspondence between the interrupt level setting bits and interrupt levels
IL2
IL1
IL0
Interrupt level
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
6 (lowest priority)
1
1
1
7 (no interrupt)
0 (highest priority)
● Extended intelligent I/O service (EI2OS) enable bit (ISE)
If this bit is 1 when an interrupt request is generated, EI2OS is activated. If this bit is 0 at when
an interrupt request is generated, the interrupt sequence is activated. When the EI2OS
termination condition is met (when the S1 and S0 bits are not 00B), the ISE bit is cleared. If the
corresponding peripheral function does not have the EI2OS function, the ISE bit must be set to 0
by software. The ISE bit is initialized to 0 by a reset.
● Extended intelligent I/O service (EI2OS) channel selection bits (ICS3 to ICS0)
These write-only bits specify the EI2OS channel. The EI2OS descriptor address is determined
based on the value set here. The ICS bit is initialized to 0000B by a reset.
Table 6.3.2-2 shows the correspondence between the EI2OS channel selection bits and
descriptor addresses.
Table 6.3.2-2 Correspondence between the EI2OS channel selection bits and
descriptor addresses
MB90820 series
ICS3
ICS2
ICS1
ICS0
Selected channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
127
● Extended intelligent I/O service (EI2OS) status bits (S1, S0)
These are read-only bits. When this value is checked at EI2OS termination, the operating status
and termination status can be distinguished. These bits are initialized to 00B by a reset.
Table 6.3.2-3 shows the relationship between the S0 and S1 bits and the EI2OS status.
Table 6.3.2-3 Relationship between EI2OS status bits and the EI2OS status
128
S1
S0
0
0
EI2OS operation in progress or EI2OS not activated
0
1
Stopped status due to count termination
1
0
Reserved
1
1
Stopped status due to a request from the peripheral function
EI2OS status
MB90820 series
Memo
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129
6.4
Hardware Interrupt
The hardware interrupt function temporarily interrupts the program being executed by
the CPU and transfers control to a user-defined interrupt processing program in
response to an interrupt signal from a peripheral function.
The extended intelligent I/O service (EI2OS) and external interrupt are executed as a
type of hardware interrupt.
■ Hardware interrupt
● Hardware interrupt function
The hardware interrupt function compares the interrupt level of the interrupt request signal output
by a peripheral function with the interrupt level mask register (ILM) in the CPU processor status
(PS). The function then references the contents of the I flag in the processor status (PS)
through the hardware and decides if the interrupt can be accepted.
When the hardware interrupt is accepted, the CPU internal registers are automatically saved on
the system stack. The currently requested interrupt level is stored in the interrupt level mask
register (ILM), and the function branches to the corresponding interrupt vector.
● Multiple interrupts
Multiple hardware interrupts can be activated.
● Extended intelligent I/O service (EI2OS)
EI2OS is an automatic transfer function between memory and I/O. When the specified transfer
count has been completed, a hardware interrupt is activated. Multiple EI2OS activation does not
occur. During EI2OS processing, all other interrupt requests and EI2OS requests are held.
● External interrupt
An external interrupt (including wake-up interrupt) is accepted from a peripheral function
(interrupt request detection circuit) as a hardware interrupt.
● Interrupt vector
Interrupt vector tables referenced during interrupt processing are allocated to memory at
FFFC00H to FFFFFFH. These tables are shared by software interrupts.
See Section 6.2, "Interrupt Causes and Interrupt Vectors", for more information about the
allocation of interrupt numbers and interrupt vectors.
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■ Hardware interrupt structure
Table 6.4-1 lists four mechanisms used for hardware interrupt. These four mechanisms must be
included in the program before hardware interrupt can be used.
Table 6.4-1 Mechanisms used for hardware interrupt
Mechanism
Function
Peripheral function
Interrupt enable bit, interrupt
request bit
Controls interrupt requests from a peripheral
function
Interrupt controller
Interrupt control register (ICR)
Sets the interrupt level and controls EI2OS
Interrupt enable flag (I)
Identifies the interrupt enable status
Interrupt level mask register (ILM)
Compares the request interrupt level and
current interrupt level
Microcode
Executes the interrupt processing routine
Interrupt vector table
Stores the branch destination address for
interrupt processing
CPU
FFFC00H to FFFFFFH
in memory
These four mechanisms must be included in the program before hardware interrupt can be used.
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131
■ Hardware interrupt suppression
Acceptance of hardware interrupt requests is suppressed under the following conditions.
● Hardware interrupt suppression during writing to the peripheral function control register
area
When data is being written to the peripheral function control register area, hardware interrupt
requests are not accepted. This prevents the CPU from making operational mistakes. The
mistakes may be caused if an interrupt request is generated during data is written to the interrupt
control registers for a resource. The peripheral function control register area is not the I/O
addressing area at 000000H to 0000FFH, but the area allocated to the control register of the
peripheral function control register and data register.
Figure 6.4-1 shows hardware interrupt operation during writing to the built-in resource area.
Instruction that writes to the peripheral function control register area
MOV A, #08
MOV io, A
An interrupt request
is generated here
MOV A, 2000H
Interrupt processing
Branches to
the interrupt
Does not branch
to the interrupt
Figure 6.4-1 Hardware interrupt request while writing to the peripheral function
control register area
● Hardware interrupt suppression by interrupt suppression instruction
The ten types of hardware interrupt suppression instructions listed in Table 6.4-2 ignore interrupt
requests without detecting whether a hardware interrupt request exists.
Table 6.4-2 Hardware interrupt suppression instruction
Prefix code
Instructions that do not
accept interrupt and hold
requests
PCB
DTB
ADB
SPB
CMR
NCC
Interrupt/hold suppression
instructions (instructions that delay
the effect of the prefix code)
MOV
OR
AND
POPW
ILM, #imm8
CCR, #imm8
CCR, #imm8
PS
Even if a valid hardware interrupt request is generated during execution of one of these
instructions, the interrupt is not processed until the first time an instruction of a different type is
executed.
● Hardware interrupt suppression during execution of software interrupt
When a software interrupt is activated, the I flag is cleared to 0. In this state, other interrupt
requests cannot be accepted.
132
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Memo
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133
6.4
Hardware Interrupt
6.4.1 Operation of hardware interrupt
This section explains hardware interrupt operation from generation of a hardware
interrupt request to the completion of interrupt processing.
■ Hardware interrupt activation
● Peripheral function operation (generation of an interrupt request)
A peripheral function that has a hardware interrupt request function also has an interrupt request
flag that indicates the presence of interrupt requests and an interrupt enable flag that determines
whether CPU interrupt requests are enabled or disabled. The interrupt request flag is set when
an event specific to the peripheral function occurs.
● Interrupt controller operation (interrupt request control)
The interrupt controller compares the interrupt levels (IL) of interrupt requests received at the
same time. The interrupt controller selects the request with the highest level (with the smallest
IL value) and posts it to the CPU. When multiple requests have the same level, the request with
the smallest interrupt number has the highest priority.
● CPU operation (interrupt request acceptance and interrupt processing)
The CPU compares the received interrupt level (ICR: IL2 ~ IL0) and the interrupt level mask
register (ILM). If IL < ILM and interrupts are enabled (PS: CCR: I = 1), the CPU activates the
interrupt processing microcode after the instruction currently being executed terminates.
At the beginning of the interrupt processing microcode, the CPU references the ISE bit in the
interrupt control register (ICR). If ISE = 0, the CPU continues the execution of interrupt
processing. (If ISE = 1, EI2OS is activated.)
Interrupt processing saves the contents of the dedicated registers (12 bytes including A, DPR,
ADB, DTB, PCB, PC and PS) on the system stack (the system stack space indicated by the SSB
and SSP).
The CPU then loads data into the interrupt vector program counters (PCB and PC), updates the
ILM, and sets the stack flag (S) (sets CCR: S = 1 and activates the system stack).
■ Returning from a hardware interrupt
In an interrupt processing program, when the interrupt request flag of the peripheral function that
generates the interrupt cause is cleared and the RETI instruction is executed, 12-byte data
saved on the system stack is restored to the dedicated registers and the processing that was
being executed before branching for the interrupt is resumed.
When the interrupt request flag is cleared, interrupt requests output by the peripheral function to
the interrupt controller are automatically canceled.
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MB90820 series
■ Hardware interrupt operation
Figure 6.4.1-1 shows hardware interrupt operation from generation of a hardware interrupt to the
completion of interrupt processing.
Internal bus
Microcode
Check
Comparator
X
Other peripheral
functions
Peripheral function that generated
the interrupt request
Enable FF
Level
comparator
Interrupt
level IL
Factor FF
Interrupt controller
IL:
PS:
I:
ILM:
IR:
FF:
Interrupt level setting bit in the interrupt control register (ICR)
Processor status
Interrupt enable flag
Interrupt level mask register
Instruction register
Flip-flop
Figure 6.4.1-1 Hardware interrupt operation
(1) An interrupt cause is generated within the peripheral function.
(2) The interrupt enable bit of the peripheral function is referenced. If the interrupt is enabled,
the interrupt request is output from the peripheral function to the interrupt controller.
(3) The interrupt controller that receives the interrupt request determines the priority of
simultaneous interrupt requests, then transfers the interrupt level (IL) that matches the
corresponding interrupt request to the CPU.
(4) The CPU compares the interrupt level (IL) requested by the interrupt controller with the
interrupt level mask register (ILM).
(5) If the comparison indicates a higher priority than the current interrupt processing level, the
CPU checks the contents of the I flag in the condition code register (CCR).
(6) If in the check in (5) the I flag is interrupt enabled (I = 1), the CPU waits until the execution of
the instruction currently being executed terminates. At termination, the CPU sets the
requested level (IL) in the ILM.
(7) Registers are saved, and processing branches to the interrupt processing routine.
(8) The interrupt cause that was generated in (1) is cleared by software in the interrupt
processing routine. Execution of the RETI instruction terminates the interrupt processing.
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135
6.4
Hardware Interrupt
6.4.2 Processing for interrupt operation
When an interrupt request is generated by the peripheral function, the interrupt
controller transmits the interrupt level to the CPU. If the CPU is able to accept
interrupt, the interrupt controller temporarily interrupts the instruction currently being
executed. The interrupt controller then executes the interrupt processing routine or
activates the extended intelligent I/O service (EI2OS).
If a software interrupt is generated by the INT instruction, the interrupt processing
routine is executed regardless of the CPU status. In this case, hardware interrupt is
not allowed.
■ Processing for interrupt operation
Figure 6.4.2-1 shows the flow of processing for interrupt operation.
START
Main program
YES
String type (*1)
instruction in
progress
I&IF&IF=1
AND
LM>IL
Interrupt activation/return processing
YES
ISE = 1
Fetch the next instruction
and deode
YES
EI2OS
NO
EI2OS processing
Software interrupt/exception
processing
INT
instruction?
NO
Save the dedicated registers
to the system stack
I <- 0 (Disable hardware
interrupts)
Hardware
instruction
YES
Specified
count terminated? Alternatively, is there a termination
request from the peripheral
function?
Save the dedicated
registers to the system stack
NO
ILM <- IL (Transfer the
interrupt level of the accepted
interrupt request to the ILM)
YES
RETI
instruction?
NO
Execute ordinary instruction
(including interrupt processing)
NO
Return
processing
Return the dedicated
registers from the system
stack, call the interrupt
routine, and return to the
previous routine
S <- 1 (Activates the
system stack)
PCB, PC <- interrupt
vector (Branch to the
interrupt processing routine)
Repetition
of string type (*1) instruction
completed?
YES
Move the pointer to the next
instruction by PC update
*1 When a string type instruction is being executed, the interrupt is evaluated in each step.
I:
Interrupt enable flag of the condition code register (CCR)
S:
Stack flag of the condition code register (CCR)
IF:
Interrupt request flag of the peripheral function
PCB: Program bank register
IE:
Interrupt enable flag of the peripheral function
PC: Program counter:
ILM: Interrupt level mask register (in the PS)
ISE: EI²OS enbale flag ofthe interruptor control register (ICR)
IL:
Interrupt level setting bit of the interrupt control register (ICR)
Figure 6.4.2-1 Flow of interrupt processing
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MB90820 series
6.4
Hardware Interrupt
6.4.3 Procedure for using hardware interrupt
Before hardware interrupt can be used, the system stack area, peripheral function, and
interrupt control register (ICR) must be set.
■ Procedure for using hardware interrupt
Figure 6.4.3-1 shows an example of the procedure for using hardware interrupt.
Start
(1)
Set the system stack area
(2)
Initialize the peripheral function
(3)
Set the ICR in the interrupt
controller
Interrupt processing program
Stack processing branches to
the interrupt vector
(8) Processing for interrupt to the
peripheral function (execute the
interrupt processing routine)
(7)
(4)
(5)
Set operation start for the
peripheral function. Set the
interrupt enable bit to enable
Hardware
processing
Set the ILM and I in the PS
(9)
Clear the interrupt cause
(10)
Interrupt return instruction
(RETI)
Main program
(6)
Interrupt request
generated
Main program
Figure 6.4.3-1 Procedure for using hardware interrupt
(1) Set the system stack area.
(2) Initialize a peripheral function that can generate interrupt requests.
(3 Set the interrupt control register (ICR) in the interrupt controller.
(4) Set the peripheral function to the operation start status, and set the interrupt enable bit to
enable.
(5) Set the interrupt level mask register (ILM) and interrupt enable flag (I) to interrupt
acceptable.
(6) An interrupt generated in the peripheral function causes a hardware interrupt request.
(7) The interrupt processing hardware saves the registers and branches to the interrupt
processing program.
(8) The interrupt processing program processes the peripheral function in response to the
generated interrupt.
(9) Clear the peripheral function interrupt request.
(10) Execute the interrupt return instruction, and return to the program before branching.
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6.4
Hardware Interrupt
6.4.4 Multiple interrupts
Multiple hardware interrupts can be implemented by setting different interrupt levels in
the interrupt level setting bits (IL0, IL1, IL2) of the interrupt control register (ICR) in
response to multiple interrupt requests from peripheral functions. Use of multiple
interrupts, however, is not possible with the extended intelligent I/O service.
■ Multiple interrupts
● Operation of multiple interrupts
During execution of an interrupt processing routine, if an interrupt request with a higher-priority
interrupt level is generated, the current interrupt processing is interrupted and the interrupt
request with the higher-priority interrupt level is accepted. When the interrupt request with the
higher-priority interrupt level terminates, the CPU returns to the previous interrupt processing.
0 to 7 can be set as the interrupt level. If level 7 is set, the CPU does not accept interrupt
requests.
During execution of interrupt processing, if an interrupt request with the same or lower-priority
interrupt level is generated, the new interrupt request is held until the current interrupt terminates
unless the I flag or ILM is changed.
Other multiple interrupts to be activated during an interrupt can be temporarily disabled by
setting the I flag in the condition code register (CCR) in the interrupt processing routine to
interrupts not allowed (CCR: I = 0) or the interrupt level mask register (ILM) to interrupts not
allowed (ILM = 000B).
<Check>
The extended intelligent I/O service (EI2OS) cannot be used for the activation of multiple
interrupts. During processing of the extended intelligent I/O service (EI2OS), all other
interrupt requests and extended intelligent I/O service requests are held.
● Example of multiple interrupts
This example of multiple interrupt processing assumes that a timer interrupt is given a higher
priority than an A/D converter interrupt. In this example, the A/D converter interrupt level is set
to 2, and the timer interrupt level is set to 1. If a timer interrupt is generated during processing of
the A/D converter interrupt, the processing shown in Figure 6.4.4-1 is performed.
138
MB90820 series
Main program
A/D interrupt processing
Interrupt level 2
(ILM = 010)
Interrupt level 1
(ILM = 001)
Peripheral initialization
A/D interrupt generated
Interrupted
Timer interrupt processing
Timer interrupt
generated
Timer interrupt processing
Restart
Main processing restarts
A/D interrupt
processing
Timer interrupt return
A/D interrupt return
Figure 6.4.4-1 Example of multiple interrupts
1) A/D interrupt generated
When the A/D converter interrupt processing starts, the interrupt level mask register (ILM)
automatically has the same value (2 in the example) as the A/D converter interrupt level (ICR:
IL2 to IL0). If a level-1 or level-0 interrupt request is generated, this interrupt processing has
priority.
2) Interrupt processing terminated
When the interrupt processing terminates and the return instruction (RETI) is executed, the
values of the dedicated registers (A, DPR, ADB, DTB, PCB, PC and PS) are returned from
the stack, and the interrupt level mask register (ILM) has the value that it had before the
interrupt.
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139
6.4
Hardware Interrupt
6.4.5 Hardware interrupt processing time
From the generation of a hardware interrupt request to the execution of an interrupt
processing routine, the time for the instruction currently being executed to terminate
and the time required to handle an interrupt are necessary.
■ Hardware interrupt processing time
From the generation of a hardware interrupt request to the acceptance of the interrupt and to the
execution of an interrupt processing routine, the time to wait for sampling for an interrupt request
and the time required to handle an interrupt (time to prepare for interrupt processing) are
necessary. Figure 6.4.5-1 shows the interrupt processing time.
CPU operation
Ordinary instruction
execution
Interrupt handling
Interrupt wait time
Interrupt request
sampling wait time
Interrupt handling time
(θ machine cycle) (*)
Interrupt processing
routine
Interrupt request generation
: The final instruction cycle samples the interrupt request here.
: One machine cycle corresponds to one machine clock (φ).
Figure 6.4.5-1 Interrupt processing time
● Interrupt request sampling wait time
The interrupt request sampling wait time is the time from the generation of and interrupt request
to the termination of the instruction currently being executed.
Whether an interrupt request has been generated is determined by sampling the instruction for
an interrupt request in the final cycle of the instruction. Consequently, the CPU cannot identify
an interrupt request during execution of each instruction creating a delay.
The interrupt request sampling wait time is the maximum when an interrupt request is generated
as soon as the POPW RW0, ... RW7 instruction (45 machine cycles), which takes the longest to
execute, starts.
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MB90820 series
● Interrupt handling time (φ machine cycle)
The CPU saves dedicated registers to the system stack and fetches interrupt vectors after it
receives an interrupt request. The required handling time for this processing is φ machine
cycles. The interrupt handling time is calculated with the following formula:
When an interrupt is activated: θ = 24 + 6 + Z machine cycles
When control is returned from an interrupt: θ = 11 + 6 + Z machine cycles (RETI instruction)
The interrupt handling time is different for each address pointed to by the stack pointer.
Table 6.4.5-1 shows the interpolation values (Z) for the interrupt handling time.
Table 6.4.5-1 Interpolation values (Z) for the interrupt handling time
Address pointed to by the stack pointer
Interpolation value (Z)
External 8-bit
+4
External even-numbered address
+1
External odd-numbered address
+4
Internal even-numbered address
0
Internal odd-numbered address
+2
[Reference]
One machine cycle corresponds to one clock cycle of the machine clock (φ).
MB90820 series
141
6.5
Software Interrupt
When the software interrupt instruction (INT instruction) is executed, the software
interrupt function transfers control from the program being executed by the CPU to the
user-defined interrupt processing program. Hardware interrupt is disabled during
execution of a software interrupt.
■ Software interrupt activation
● Software interrupt activation
The INT instruction is used to activate a software interrupt. There is no interrupt request flag or
enable flag for software interrupt requests. When the INT instruction is executed, an interrupt
request is always generated.
● Hardware interrupt suppression
Since the INT instruction does not have interrupt levels, the interrupt level mask register (ILM) is
not updated. During the execution of the INT instruction, the I flag of the condition code register
(CCR) is set to 0, and hardware interrupts are masked.
To enable hardware interrupts during software interrupt processing, set the I flag to 1 in the
software interrupt processing routine.
● Software interrupt operation
When the CPU fetches the INT instruction, the software interrupt processing microcode is
activated. This microcode saves the internal CPU registers on the system stack, masks
hardware interrupts (CCR: I = 0), and branches to the corresponding interrupt vector.
See Section 6.2, "Interrupt Causes and Interrupt Vectors", in Chapter 6 for more information
about the allocation of interrupt numbers and interrupt vectors.
■ Returning from a software interrupt
In the interrupt processing program, when the interrupt return instruction (RETI instruction) is
executed, the 12-byte data saved to the system stack is restored to the dedicated registers and
the processing that was being executed before branching for the interrupt is resumed.
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MB90820 series
■ Software interrupt operation
Figure 6.5-1 shows software interrupt operation from the generation of a software interrupt to the
completion of interrupt processing.
(1)
PS
Register file
(2)
Microcode
I
S
B unit
IR
Queue
Fetch
2
F MC-16LX CPU
(3)
Save
F2MC-16LX bus
Instruction bus
PS :
I
:
ILM :
IR
:
B unit:
RAM
Processor status
Interrupt enable flag
Interrupt level mask register
Instruction register
Bus interface unit
Figure 6.5-1 Software interrupt operation
(1) A software interrupt instruction is executed.
(2) The dedicated registers are saved according to the microcode that corresponds to the
software interrupt instruction, and other necessary processing is performed. Branch
processing is then executed.
(3) The RETI instruction in the user interrupt processing routine terminates the interrupt
processing.
<Check>
When the program bank register (PCB) is FFH, the vector area of the CALLV instruction
overlaps the INT #vct8 instruction table. When creating the software, be careful of the
duplicated address of the CALLV instruction and INT #vct8 instruction.
MB90820 series
143
6.6
Interrupt of Extended Intelligent I/O Service (EI²OS)
The extended intelligent I/O service (EI2OS) automatically transfers data between a
peripheral function (I/O) and memory. When the data transfer terminates, a hardware
interrupt is generated.
■ Extended intelligent I/O service (EI²OS)
The extended intelligent I/O service is a type of hardware interrupt. It automatically transfers
data between a peripheral function (I/O) and a memory. Traditionally, data transfer with a
peripheral function (I/O) has been performed by the interrupt processing program. EI2OS
performs this data transfer in the same way as direct memory access (DMA). At termination,
EI2OS sets the termination condition and automatically branches to the interrupt processing
routine. The user creates programs only for EI2OS activation and termination. Data transfer
programs in between are not required.
● Advantages of extended intelligent I/O service (EI2OS)
Compared to data transfer performed by the interrupt processing routine, EI2OS has the
following advantages.
•
Coding a transfer program is not necessary, reducing program size.
•
Because transfer can be stopped depending on the peripheral function (I/O) status,
unnecessary data transfer can be eliminated.
•
Incrementing or no update can be selected for the buffer address.
•
Incrementing or no update can be selected for the I/O register address.
● Extended intelligent I/O service (EI2OS) termination interrupt
When data transfer by EI2OS terminates, a termination condition is set in the S1 and S0 bits in
the interrupt control register (ICR). Processing then automatically branches to the interrupt
processing routine.
The EI2OS termination factor can be determined by checking the EI2OS status (ICR: S1, S0)
with the interrupt processing program.
Interrupt numbers and interrupt vectors are permanently set for each peripheral. See Section
6.2, "Interrupt Causes and Interrupt Vectors", in Chapter 6 for more information.
● Interrupt control register (ICR)
This register, which is located in the interrupt controller, activates EI2OS, specifies the EI2OS
channel, and displays the EI2OS termination status.
● Extended intelligent I/O service (EI2OS) descriptor (ISD)
This descriptor, which is located in RAM at 000100H to 00017FH, is an eight-byte data that
retains the transfer mode, I/O address, transfer count, and buffer address. The descriptor
handles 16 channels. The channel is specified by the interrupt control register (ICR).
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MB90820 series
<Check>
When the extended intelligent I/O service (EI2OS) is operating, execution of the CPU program
stops.
■ Operation of the extended intelligent I/O service (EI²OS)
Figure 6.6-1 shows EI2OS operation.
Memory space
by IOA
I/O register
2
F MC-16LX
CPU
••• ••• ••• ••• •••
Peripheral
function (I/O)
(5)
Interrupt request (1)
I/O register
(3)
ISD
by ICS
(2)
(3)
Interrupt control register (ICR)
Interrupt controller
by BAP
(4)
Buffer
by
DCT
ISD: EI2OS descriptor
IOA: I/O address pointer
BAP: Buffer address pointer
ICS: EI2OS channel selection bit in ICR
DCT: Data counter
Figure 6.6-1 Extended intelligent I/O service (EI²OS) operation
(1) I/O requests transfer.
(2) The interrupt controller selects the descriptor.
(3) The transfer source and transfer destination are read from the descriptor.
(4) Transfer is performed between I/O and memory.
(5) The interrupt cause is automatically cleared.
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6.6
Interrupt of Extended Intelligent I/O Service (EI²OS)
6.6.1 Extended intelligent I/O service (EI²OS) descriptor (ISD)
The extended intelligent I/O service (EI2OS) descriptor (ISD) resides in internal RAM at
000100H to 00017FH. The ISD consists of 8 bytes x 16 channels.
■ Configuration of the extended intelligent I/O service (EI²OS) descriptor (ISD)
The ISD consists of 8 bytes x 16 channels. Each ISD has the structure shown in Figure 6.6.1-1.
Table 6.6.1-1 shows the correspondence between channel numbers and ISD addresses.
H
High-order 8 bits of data counter (DCTH)
Low-order 8 bits of data counter (DCTL)
High-order 8 bits of I/O address pointer (IOAH)
Low-order 8 bits of I/O address pointer (IOAL)
EI2OS status register (ISCS)
High-order 8 bits of buffer address pointer (BAPH)
000100H + 8 x ICS
Medium-order 8 bits of buffer address pointer (BAPM)
ISD start address
Low-order 8 bits of buffer address pointer (BAPL)
L
Figure 6.6.1-1 Configuration of EI²OS descriptor (ISD)
Table 6.6.1-1 Correspondence between channel numbers and descriptor addresses
Channel
Descriptor address
0
000100H
1
000108H
2
000110H
3
000118H
4
000120H
5
000128H
6
000130H
7
000138H
8
000140H
9
000148H
10
000150H
11
000158H
12
000160H
13
000168H
14
000170H
15
000178H
Registers of the extended intelligent I/O service (EI²OS) descriptor (ISD)
146
MB90820 series
6.6
Interrupt of Extended Intelligent I/O Service (EI²OS)
6.6.2 Registers of EI2OS descriptor (ISD)
• Data counter (DCT)
• I/O register address pointer (IOA)
• EI2OS status register (ISCS)
• Buffer address pointer (BAP)
Note that the initial value of each register is undefined after a reset.
■ Data counter (DCT)
The DCT is a 16-bit register that serves as a counter for the data transfer count. After each data
transfer, the counter is decremented by 1. When the counter reaches zero, EI2OS terminates.
Figure 6.6.2-1 shows the configuration of the DCT.
Upper byte of data counter
Initial value
Lower byte of data counter
Initial value
15
14
13
12
11
10
9
8
Bit number
B15
B14
B13
B12
B11
B10
B09
B08
DCTH
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
3
2
1
0
Bit number
B07
B06
B05
B04
B03
B02
B01
B00
DCTL
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Figure 6.6.2-1 Configuration of DCT
■ I/O register address pointer (IOA)
The IOA is a 16-bit register that indicates the lower address (A15 to A00) of the I/O register used
to transfer data to and from the buffer. The upper address (A23 to A16) is all zeros. Any I/O
from 000000H to 00FFFFH can be specified by address.
Figure 6.6.2-2 shows the configuration of the IOA.
Upper address pointer
Initial value
Lower address pointer
Initial value
15
14
13
12
11
10
9
8
Bit number
A15
A14
A13
A12
A11
A10
A09
A08
IOAH
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
7
6
5
4
3
2
1
0
A07
A06
A05
A04
A03
A02
A01
A00
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Bit number
IOAL
Figure 6.6.2-2 Configuration of I/O register address pointer (IOA)
MB90820 series
147
■ Extended intelligent I/O service (EI²OS) status register (ISCS)
The ISCS is an 8-bit register. The ISCS indicates the update/fixed for the buffer address pointer
and I/O register address pointer, transfer data format (byte or word), and transfer direction.
Figure 6.6.2-3 shows the configuration of the ISCS.
Initial value
EI2OS termination control bit
Not terminated by a request from the peripheral function.
Terminated by a request from the peripheral function
Data transfer direction specification bit
I/O register address pointer → buffer address pointer.
Buffer address pointer → I/O register address pointer
BAP update/fixed selection bit
After data transfer, the buffer address pointer is updated. (*1)
After data transfer, the buffer address pointer is not updated.
Transfer data length specification bit
Byte
Word
IOA update/fixed selection bit
After data transfer, the I/O register address pointer is updated. (*2)
After data transfer, the buffer address pointer is not updated.
Reserved bits
0 must be written to these bits.
R/W: Read-write
X:
Undefined
*1 Only the lower 16 bits of the buffer address pointer change. The buffer address pointer
can only be incremented.
*2 The address pointer can only be incremented.
Figure 6.6.2-3 Configuration of EI²OS status register (ISCS)
■ Buffer address pointer (BAP)
The BAP is a 24-bit register that retains the address used by EI2OS for the next transfer. Since
one independent BAP exists for each EI2OS channel, each EI2OS channel can transfer data
between any address in the 16-megabyte space and the I/O. If the BF bit (BAP update/fixed
selection bit in the EI2OS status register) in the EI2OS status register (ISCS) is set to "update
yes," only the lower 16 bits (BAPH, BAPL) of the BAP change; the upper 8 bits (BAPH) do not
change. Figure 6.6.2-4 shows the configuration of the BAP.
148
MB90820 series
bit23
BAP
~
bit16 bit15
~
BAPH
BAPM
(R/W)
(R/W)
bit8 bit7
~
bit0
BAPL
(R/W)
Initial value
xxxxxxB
R/W: Read-write
x: Undefined
Figure 6.6.2-4 Configuration of buffer address pointer (BAP)
[Reference]
MB90820 series
•
The area that can be specified by the I/O address pointer (IOA) extends from 000000H to
00FFFFH.
•
The area that can be specified with the buffer address pointer (BAP) extends from
000000H to FFFFFFH.
•
The maximum transfer count that can be specified by the data counter (DCT) is 65,536
(64 kilobytes).
149
6.6
Interrupt of Extended Intelligent I/O Service (EI²OS)
6.6.3 Operation of the extended intelligent I/O service (EI²OS)
If an interrupt request is generated by a peripheral function, EI2OS activation is set in
the corresponding interrupt control register (ICR) that the CPU uses EI 2OS to transfer
data. When the specified data transfer count terminates, the hardware interrupt is
automatically processed.
■ Operation flow of the extended intelligent I/O service (EI²OS)
Figure 6.6.3-1 shows the flow of EI2OS operation based on the internal microcode of the CPU.
Interrupt request generated
by peripheral function
NO
ISE = 1
YES
Read ISD/ISCS
Termination
request from peripheral
function
Interrupt sequence
YES
YES
SE = 1
NO
NO
YES
DIR = 1
NO
Data indicated by IOA
(data transfer)
memory indicated by BAP
Data indicated by BAP
(data transfer)
memory indicated by IOA
YES
IF = 0
NO
Updage value
by BW
Update IOA
Updage value
by BW
Update BAP
YES
BF = 0
NO
Decrement DCT
(-1)
YES
DCT = 00
EI2OS termination processing
NO
Set S1 and S0 to 00
Clear interrupt request from
the peripheral function
Return to CPU operation
ISD:
ISCS:
IF:
BW:
BF:
DIR:
SE:
Set S1 and S0 to 11
Set S1 and S0 to 01
EI²OS descriptor
EI²OS status register
IOA update/fixed selection bit inte EI²OS status register (ISCS)
Transfer data length specification bit in the EI²OS status register (ISCS)
BAP update/fixed selection bit in the EI²OS status register (ISCS)
Data transfer direction specification bit in the EI²OS status register (ISCS)
EI²OS termination control bit in the EI²OS status register (ISCS)
Clear ISE to 0
Interrupt sequence
DCT:
IOA:
BAP:
ISE:
Data counter
I/O register address pointer
Buffer address pointer
EI²OS enable bit in the interrupt control
register
S1, S0: EI²OS status in the interrupt control
register (ICR)
Figure 6.6.3-1 Flow of extended intelligent I/O service (EI²OS) operation
150
MB90820 series
6.6
Interrupt of Extended Intelligent I/O Service (EI²OS)
6.6.4 Procedure for using the extended intelligent I/O service (EI²OS)
Before the extended intelligent I/O service (EI2OS) can be used, the system stack area,
extended intelligent I/O service (EI2OS) descriptor, interrupt function, and interrupt
control register (ICR) must be set.
■ Procedure for using the extended intelligent I/O service (EI²OS)
Figure 6.6.4-1 shows the EI2OS software and hardware processing.
Software processing
Hardware processing
Start
Set the system stack area
Set the EI2OS descriptor
Initialization
Initialize the peripheral
function
Set the interrupt control
register (ICR)
Set the built-in resource to
start operation. Set the
interrupt enable bit
Set the ILM and I in the PS
(Interrupt request)
and (ISE = 1)
Execute the user program
S1, S0 = "00"
Transfer data
(Branch to interrupt vector)
Decide whether to end
counting or to branch to an
interrupt requested by the
resource
NO
YES
Set the extended intelligent
I/O service again (switch
channels)
S1, S0 = "01" or
S1, S0 = "11"
Process data in the buffer
RETI
ISE: EI2OS enable bit in the interrupt control register (ICR)
S1, S0: EI2OS status of the interrupt control register (ICR)
Figure 6.6.4-1 Procedure for using the extended intelligent I/O service (EI²OS)
MB90820 series
151
6.6
Interrupt of Extended Intelligent I/O Service (EI²OS)
6.6.5 Processing time of the extended intelligent I/O service (EI²OS)
The time required for processing the extended intelligent I/O service (EI2OS) changes
according to the following factors:
• EI2OS status register (ISCS) setting
• Address (area) pointed to by the I/O register address pointer (IOA)
• Address (area) pointed to by the buffer address pointer (BAP)
• External data bus length for external access
• Transfer data length
Because the hardware interrupt is activated when data transfer by EI2OS terminates,
the interrupt handling time is added.
■ Processing time (one transfer time) of the extended intelligent I/O service (EI²OS)
● When data transfer continues
The EI2OS processing time for data transfer continuation is shown in Table 6.6.5-1 based on the
EI2OS status register (ISCS) setting.
Table 6.6.5-1 Extended intelligent I/O service execution time
Terminates due to Ignores termination
termination request
request from the
from the peripheral
peripheral
EI2OS termination control bit (SE) setting
IOA update/fixed selection bit (IF) setting
BAP address update/fixed selection bit
(BF) setting
Fixed
Update
Fixed
Update
Fixed
32
34
33
35
Update
34
36
35
37
Unit: Machine cycle (One machine cycle corresponds to one clock cycle of the machine clock,
φ).
As shown in Table 6.6.5-2, interpolation is necessary depending on the EI2OS execution
condition.
Table 6.6.5-2 Data transfer interpolation value for EI2OS execution time
Internal access
External access
I/O register address pointer
Internal access
Buffer address
pointer
External access
152
B/Even
Odd
B/Even
8/Odd
B/Even
0
+2
+1
+4
Odd
+2
+4
+3
+6
B/Even
+1
+3
+2
+5
8/Odd
+4
+6
+5
+8
B:
Byte data transfer
8:
External bus using the 8-bit word transfer
Even:
Even-numbered address word transfer
Odd:
Odd-numbered address word transfer
MB90820 series
● When the data counter (DCT) count terminates (final data transfer)
Because the hardware interrupt is activated when data transfer by EI2OS terminates, the
interrupt handling time is added. The EI2OS processing time when counting terminates is
calculated with the following formula:
EI2OS processing time when counting terminates = EI2OS processing time when data is
transferred + (21 + 6 x Z) Machine cycles
Interrupt handling time
The interrupt handling time is different for each address pointed to by the stack pointer. Table
6.6.5-3 shows the interpolation value (Z) for the interrupt handling time.
Table 6.6.5-3 Interpolation value (Z) for the interrupt handling time
Address pointed to by the stack pointer
Interpolation value (Z)
External 8-bit
+4
External even-numbered address
+1
External odd-numbered address
+4
Internal even-numbered address
0
Internal odd-numbered address
+2
● For termination by a termination request from the peripheral function (I/O)
When data transfer by EI2OS is terminated before completion due to a termination request from
the peripheral function (I/O) (ICR: S1, S0 = 11B), the data transfer is not performed and a
hardware interrupt is activated. The EI2OS processing time is calculated with the following
formula. Z in the formula indicates the interpolation value for the interrupt handling time (Table
6.6.5-3).
EI2OS processing time for termination before completion = 36 + 6 x Z Machine cycle
[Reference]
One machine cycle corresponds to one clock cycle of the machine clock (φ).
MB90820 series
153
6.7
Exception Processing Interrupt
In the F2MC-16LX, the execution of an undefined instruction results in exception
processing.
Exception processing is basically the same as an interrupt. When the generation of an
exception processing is detected on the instruction boundary, ordinary processing is
interrupted and exception processing is executed.
Generally, exception processing occurs as the result of an unexpected operation.
Exception processing should be used only to activate recovery software required for
debugging or an emergency.
■ Exception processing
● Exception processing operation
The F2MC-16LX handles all codes that are not defined in the instruction map as undefined
instructions. When an undefined instruction is executed, processing equivalent to the INT #10
software interrupt instruction is executed.
The following processing is executed before exception processing branches to the interrupt
routine:
•
The A, DPR, ADB, DTB, PCB, PC and PS registers are saved to the system stack.
•
The I flag of the condition code register (CCR) is cleared to 0, and hardware interrupts are
masked.
•
The S flag of the condition code register (CCR) is set to 1, and the system stack is activated.
The program counter (PC) value saved to the stack is the exact address where the undefined
instruction is stored. For 2-byte or longer instruction codes, the code identified as undefined is
stored at this address. When the exception factor type must be determined within the exception
processing routine, use this PC value.
● Return from exception processing
When the RETI instruction returns control from exception processing, exception processing
restarts because the PC is pointing to the undefined instruction. Provide a solution such as
resetting the software.
154
MB90820 series
Memo
MB90820 series
155
6.8
Stack Operations for Interrupt Processing
Once an interrupt is accepted, the contents of the dedicated registers are automatically
saved to the system stack before a branch to interrupt processing. When the interrupt
processing terminates, the previous processing is automatically restored from the
stack.
■ Stack operations at the start of interrupt processing
Once an interrupt is accepted, the CPU automatically saves the contents of the current
dedicated registers to the system stack in the order given below:
•
Accumulator (A)
•
Direct page register (DPR)
•
Additional data bank register (ADB)
•
Data bank register (DTB)
•
Program bank register (PCB)
•
Program counter (PC)
•
Processor status (PS)
Figure 6.8-1 shows the stack operations at the start of interrupt processing.
Immediately before interrupt
Immediately after interrupt
Memory
Address
Memory
Address
before update
SP after update
Byte
Byte
Figure 6.8-1 Stack operations at the start of interrupt processing
■ Stack operations on return from interrupt processing
When the interrupt return instruction (RETI) is executed at the termination of interrupt
processing, the PS, PC, PCB, DTB, ADB, DPR and A values are returned from the stack in
reverse order from the order they were placed on the stack. The dedicated registers are
restored to the status they had immediately before the start of interrupt processing.
156
MB90820 series
■ Stack area
● Stack area allocation
The stack area is used for saving and restoring the program counter (PC) when the subroutine
call instruction (CALL) and vector call instruction (CALLV) are executed in addition to interrupt
processing. The stack area is used for temporary saving and restoring of registers by the
PUSHW and POPW instructions.
The stack area is allocated together with the data area in RAM.
Figure 6.8-2 shows the stack area.
Vector table
(interrupt vector call
instruction for a reset)
FFFFFFH
FFFC00H
ROM area
FF0000H*1
001100H*2
Built-in
RAM area
Stack
area 000380H
General-purpose
register bank area
000180H
000100H
0000F0H
Built-in I/O area
000000H
*
1 The internal ROM is different for each model.
2 The internal RAM is different for each model.
*
Figure 6.8-2 Stack area
<Check>
•
Generally set an even-numbered address in the stack pointers (SSP and USP).
•
Allocate the system stack area, user stack area, and data area so that they do not
overlap.
● System stack and user stack
The system stack area is used for interrupt processing. When an interrupt occurs, the user stack
area being used is forcibly switched to the system stack. The system stack area must be set
correctly even in a system that mainly uses the user stack area.
If division of the stack space is not particularly necessary, use only the system stack.
MB90820 series
157
6.9
Sample Programs for Interrupt Processing
This section contains sample programs for interrupt processing.
■ Sample programs for interrupt processing
● Processing specifications
The following is a sample program for an interrupt that uses external interrupt 0 (INT0).
● Sample coding
DDR1
ENIR
EIRR
ELVR
ICR04
STACK
EQU
000011H
; Port 1 direction register
EQU
030H
; Interrupt/DTP enable register
EQU
031H
; Interrupt/DTP flag
EQU
032H
; Request level setting register
EQU
0B4H
; Interrupt control register
SSEG
; Stack
RW
100
STACK_T
RW
1
STACK
ENDS
;---------Main program --------------------------------------------------------------------------------------------------CODE
CSEG
START:
MOV
RP,#0
; General-purpose registers use the first bank
MOV
ILM, #07H
; Sets ILM in PS to level 7
MOV
A, #!STACK_T
; Sets system stack
MOV
SSB, A
MOVW A, #STACK_T
; Sets stack pointer, then
MOVW SP, A
; Sets SSP because S flag = 1
MOV
DDR1, #00000000B ; Sets P10/INT0 pin to input
OR
CCR, #40H
; Sets I flag of CCR in PS, enables interrupts
MOV
I:ICR04, #00H
; Sets interrupt level to 0 (highest priority)
MOV
I:ELVR, #00000001B; Requests that INT0 be made level H
MOV
I:EIRR, #00H
; Clears INT0 interrupt cause
MOV
I:EIRR, #01H
; Enables INT0 input
:
LOOP:
NOP
; Dummy loop
NOP
NOP
NOP
BRA
LOOP
; Unconditional jump
;---------Interrupt program ---------------------------------------------------------------------------------------------ED_INT1:
MOV
I:EIRR, #00H ; Acceptance of new INT0 not allowed
NOP
NOP
NOP
NOP
NOP
NOP
RETI
; Return from interrupt
CODE
ENDS
;--------Vector setting----------------------------------------------------------------------------------------------------VECT
CSEG
ABS=0FFH
158
MB90820 series
VECT
ORG
DSL
ORG
DSL
DB
ENDS
END
0FFACH
ED_INT1
0FFDCH
START
00H
; Sets vector for interrupt #20 (14H)
; Sets reset vector
; Sets single-chip mode
START
■ Processing specifications of sample program for extended intelligent I/O service (EI²OS)
1) This program detects the H level signal input to the INT0 pin and activates the extended
intelligent I/O service (EI2OS).
2) When the H level is input to the INT0 pin, EI2OS is activated. Data is transferred from port 0
to the memory at the 3000H address.
3) The number of transfer data bytes is 100 bytes. After 100 bytes are transferred, an interrupt
is generated because EI2OS transfer has terminated.
● Sample coding
DDR1
ENIR
EIRR
ELVR
ICR04
BAPL
BAPM
BAPH
ISCS
IOAL
IOAH
DCTL
DCTH
ER0
STACK
EQU
000011H
; Port 1-direction register
EQU
000030H
; Interrupt/DTP enable register
EQU
000031H
; Interrupt/DTP factor register
EQU
000032H
; Request level setting register
EQU
0000B4H
; Interrupt control register
EQU
000100H
; Lower buffer address pointer
EQU
000101H
; Middle buffer address pointer
EQU
000102H
; Upper buffer address pointer
EQU
000103H
; EI2OS status
EQU
000104H
; Lower I/O address pointer
EQU
000105H
; Upper I/O address pointer
EQU
000106H
; Low-order data counter
EQU
000107H
; High-order data counter
EQU
EIRR:0
; Definition of external interrupt request flag bit
SSEG
; Stack
RW
100
STACK_T
RW
1
STACK
ENDS
;-------------------Main program-----------------------------------------------------------------------------------------CODE
CSEG
START:
AND
CCR, #0BFH
; Clears the I flag of the CCR in the PS and
prohibits interrupts
MOV
RP, #00
; Sets the register bank pointer
MOV
A, #STACK_T
; Sets the system stack
MOV
SSB, A
MOVW
A, #STACK_T
; Sets the stack pointer, then
MOVW
SP, A
; Sets SSP because the S flag = 1
MOV
I:DDR1, #00000000B; Sets the P10/INT0 pin to input
MOV
BAPL, #00H
; Sets the buffer address (003000H)
MOV
BAPM, #30H
MOV
BAPH, #00H
MOV
ISCS, #00010001B ; No I/O address update, byte transfer,
buffer address updated
MB90820 series
159
; I/O → buffer transfer, terminated by the
peripheral function
; Sets the transfer source address
(port 0: 000000H)
MOV
IOAL, #00H
MOV
MOV
IOAH, #00H
DCTL, #64H
MOV
MOV
DCTH, #00H
I:ICR04, #00001000B; EI2OS channel 0, EI2OS enable,
interrupt level 0 (highest priority)
I:ELVR, #00000001B; Requests that INT0 be made H level
I:EIRR, #00H
; Clears the INT0 interrupt cause
I:ENIR, #01H
; Enables INT0 interrupts
ILM, #07H
; Sets the ILM in the PS to level 7
CCR, #40H
; Sets the I flag of the CCR in the PS
and enables interrupts
MOV
MOV
MOV
MOV
OR
; Sets the number of transfer bytes
(100 bytes)
:
LOOP
BRA
LOOP
; Infinite loop
;---------------Interrupt program----------------------------------------------------------------------------------------WARI
CLRB
ER0
; Clears interrupt/DTP request flag
:
User processing
; Checks EI2OS termination factor,
:
; processes data in buffer, sets EI2OS
again
RETI
CODE
ENDS
;---------------Vector processing---------------------------------------------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFACH
; Sets vector for interrupt #20 (14H)
DSL
WARI
ORG
0FFDCH
; Sets reset vector
DSL
START
DB
00H
; Sets single-chip mode
VECT
ENDS
END
START
160
MB90820 series
CHAPTER 7
MODE SETTING
This chapter describes the operating modes and memory access modes supported by
the MB90820 series.
7.1 Mode Setting
7.2 Mode Pins (MD2 to MD0)
7.3 Mode Data
MB90820 series
161
7.1
Mode Setting
The F2MC-16LX supports the modes for access method, and access areas. A mode is
determined based on the settings by the mode pin at a reset as well as the mode data
fetched.
■ Mode setting
The F2MC-16LX supports the modes for access method, and access areas, classified as shown
in Figure 7.1-1 in this module.
Operating mode
RUN mode
FLASH WRITE mode
Bus mode
Single-chip mode
Figure 7.1-1 Mode classification
■ Operating modes
The operating modes control the operating state of the device, and are specified by the mode
setting pin (MDx) and Mx bit contents in mode data.
<Check>
Because the MB90820 series is only used in single-chip mode, set MD2, 1, 0 to 011B and set
M1, 0 to 00B.
■ Bus mode
The bus mode controls the operation of internal ROM and external access functions, and is
specified by the mode setting pin (MDx) and Mx bit contents in mode data. The mode setting
pin (MDx) specifies bus mode when reset vector and mode data are read. The Mx bit in
mode data specifies bus mode during normal operation.
■ RUN mode
The RUN mode means CPU operating mode. The RUN mode includes main clock mode,
PLL clock mode, and various low power consumption modes. See Chapter 5, "Low Power
Consumption Modes", for details.
<Check>
Because the MB90820 series is only used in single-chip mode, set MD2, 1, 0 to 011B and set
M1, 0 to 00B.
162
MB90820 series
7.2
Mode Pins (MD2 to MD0)
Three external pins, MD2 to MD0, are supported as the mode pins. These are used to
specify how the reset vector and mode data are fetched.
■ Mode pins (MD2 to MD0)
The mode pins are used to select the data bus (external or internal) used for reading the reset
vector and to specify the bus width when the external data bus is selected.
For a built-in FLASH version, the mode pins are also used to specify FLASH programming
mode, which is used to write programs and other data to internal FLASH.
Table 7.2-1 shows the mode pin settings.
Table 7.2-1 Mode pin settings
MD2
MD1
MD0
0
0
0
0
0
1
0
1
0
Mode name
Reset vector
access area
External data
bus width
Remarks
Setting not allowed
Internal vector mode
Internal
Mode data
The reset
sequence and
subsequent
sequences are
controlled by
mode data.
0
1
1
1
0
0
1
0
1
1
1
0
FLASH serial write
mode
-
-
-
1
1
1
FLASH memory
mode
-
-
Mode when the
parallel writer is
used.
Setting not allowed
MD2 to MD0: Connect the pins to Vss for 0 and to Vcc for 1.
*: The flash serial write mode cannot be executed by just setting the mode pins. Other terminal
also need to be set. For details, see Appendix B “Example of F2MC-16LX MB90F822/F823
connection for serial writing”.
<Check>
Because the MB90820 series is only used in single-chip mode, set MD2, 1, 0 to 011B and set
M1, 0 to 00B.
MB90820 series
163
7.3
Mode Data
The mode data is at memory location FFFFDFH, and is used to specify the operation
after a reset sequence. The mode data is automatically fetched to the CPU.
■ Mode data
During a reset sequence, the mode data at address FFFFDFH is fetched to the mode register in
the CPU. The CPU uses the mode data to set the memory access mode.
The contents of the mode register can only be changed during the reset sequence. The settings
in the register take effect after the reset sequence.
Figure 7.3-1 shows the mode data configuration.
Mode data
7
6
5
4
3
2
1
0
M1
M0
0
0
0
0
0
0
Function extension bits (reserved area)
Bus mode setting bits
Figure 7.3-1 Mode data configuration
■ Bus mode setting bits
The bus mode setting bits specify operating mode after a reset sequence. Table 7.3-1 lists the
relationship between the bits and functions.
Table 7.3-1 Bus mode setting bits and functions
M1
M0
Function
0
0
Single-chip mode
0
1
1
0
1
1
(Setting not allowed)
<Check>
Because the MB90820 series is only used in single-chip mode, set MD2, 1, 0 to 011B and set
M1, 0 to 00B.
164
MB90820 series
Figure 7.3-2 shows the correspondence between access areas and physical addresses in
single-chip mode.
FFFFFFH
ROM
Model #1
FF0000H
00FFFFH
ROM
When ROM mirroring function is selected
Model #2
Model #3
RAM
000100H
0000F0H
000000H
: No access
: Internal access
I/O
Note: Model #x becomes the model-dependent address.
Figure 7.3-2 Correspondence between access areas and physical addresses in single-chip mode
■ Relationship between mode pins and mode data
Table 7.3-2 lists the relationship between mode pins and mode data.
Table 7.3-2 Relationship between mode pins and mode data
Mode
MD2
MD1
MD0
M1
M0
Single-chip mode
0
1
1
0
0
<Check>
The MB90820 series is only used in single-chip mode.
MB90820 series
165
166
MB90820 series
CHAPTER 8
I/O PORTS
This chapter describes the functions and operation of the I/O ports.
8.1 Overview of I/O Ports
8.2 Registers of I/O Ports
8.3 Port 0
8.4 Port 1
8.5 Port 2
8.6 Port 3
8.7 Port 4
8.8 Port 5
8.9 Port 6
8.10 Port 7
8.11 Port 8
8.12 Sample Program for the I/O Port
MB90820 series
167
8.1
Overview of I/O Ports
All I/O ports can be used as general-purpose I/O ports (parallel I/O ports). The MB90820
series has 9 ports (66 pins). The ports are also used for resource I/O pins (peripheral
function I/O pins).
■ I/O ports functions
Each I/O port outputs data from CPU to I/O pins or inputs signals from I/O pins to CPU through
port data register (PDR). Direction of the data flow (input or output) for each I/O pin can be
designated in bit unit by port data direction register (DDR). The function of each port and the
resource I/O multiplexed with it are described below:
•
Port 0
: General-purpose I/O port/resource (PWC)
•
Port 1
: General-purpose I/O port/resources (DTP / Multi-functional timer)
•
Port 2
: General-purpose I/O port/resource (16-bit reload timer)
•
Port 3
: General-purpose I/O port/resource (16-bit PPG timer)
•
Port 4
: General-purpose I/O port/resources (16-bit PPG timer / 16-bit reload timer / UART
/ PWC)
•
Port 5
: General-purpose I/O port/resources (16-bit PPG timer / DTP)
•
Port 6
: General-purpose I/O port/resource (8/10-bit AD converter)
•
Port 7
: General-purpose I/O port/resources (8/10-bit AD converter / 8-bit DA converter /
UART / 16-bit free-running timer / 16-bit input capture)
•
Port 8
: General-purpose I/O port/resources (16-bit input capture / Multi-functional timer)
Table 8.1-1 summarizes the functions of individual port.
168
MB90820 series
Table 8.1-1
Port
Pin
Port 0
P00~P07/
PWO0
Input type
Output
type
Functions of individual port
Function
bit
15
bit
14
bit
13
bit
12
bit
11
bit
10
bit9
bit8
General I/O port
–
–
–
–
–
–
–
Resource
–
–
–
–
–
–
–
P16
P15
P14
P13
P12
P11
P10
–
INT0
INT6 INT5 INT4 INT3 INT2 INT1
DTTI
General I/O port P17
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
P10/INT0/
CMOS
DTTI~
(hysteresis) CMOS Resource
P17
pull-up
resistor General I/O port
selectable
P20/TIN1
~P27
P30/
SEG08
~P36/
SEG15
P40/PPG1
~P47/
PWO1
P50/PPG2
~P51/INT7
P60/AN0
~P67/AN7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
–
P07
P06
P05
P04
P03
P02
P01
P00
–
PWO0 PWI0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P21
P20
–
–
–
–
–
–
–
–
P27
P26
P25
P24
P23
P22
–
–
–
–
–
–
–
–
–
–
–
–
–
–
P36
P35
P34
P33
P32
P31
P30
–
–
–
–
–
–
–
–
PPG0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
General I/O port
–
–
–
–
–
–
–
–
P47
P46
P45
P44
P43
P42
P41
P40
Analog output
–
–
–
–
–
–
–
–
PWO1 PWI1 SIN0* SOT0 SCK0 TO0 TIN0 PPG1
General I/O port
–
–
–
–
–
–
P51
P50
–
–
–
–
–
–
–
–
Resource
–
–
–
–
–
–
INT7 PPG2
–
–
–
–
–
–
–
–
General I/O port
–
–
–
–
–
–
–
–
P67
P66
P65
P64
P63
P62
P61
P60
Analog Input
–
–
–
–
–
–
–
–
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
General I/O port P77
P76
P75
P74
P73
P72
P71
P70
–
–
–
–
–
–
–
–
Resource
IN1
IN0
FRCK SCK1 SOT1 SIN1*
–
–
–
–
–
–
–
–
–
–
–
–
DA1
DA0
–
–
–
–
–
–
–
–
AN9
AN8
–
–
–
–
–
–
–
–
P87
P86
P85
P84
P83
P82
P81
P80
IN3
IN2
Resource
General I/O port P37
TO1 TIN1
CMOS
Resource
CMOS
(hysteresis)
CMOS
CMOS
P70/DA0/
AN8
Port 7
~
P77/IN1/
CMOS
AN15 (hysteresis)
Port 8
–
bit7
P80/IN2
~P87/
RTO5
Analog output
Analog input
–
–
–
–
AN15 AN14 AN13 AN12 AN11 AN10
General I/O port
–
–
–
–
–
–
–
–
Resource
–
–
–
–
–
–
–
–
RTO5 RTO4 RTO3 RTO2 RTO1 RTO0
<Check>
Port 6, Port 7 are also used as analog signal input pins. To use the port as a general-purpose port, be sure
to reset the corresponding bit of the analog data input enable register (ADER0, ADER1) to 0. Resetting the
MCU sets the ADER0 / ADER1 register bits to 1.
*: UART0, 1 data input pins SIN0, SIN1 can be selected as CMOS input by user program.
MB90820 series
169
8.2
Registers of I/O Ports
This section provides a list of the registers related to the I/O port settings.
■ Registers for I/O ports
Table 8.2-1 is a list of the registers corresponding to individual port.
Table 8.2-1
Registers and corresponding port
Register
Read/Write
Address
Initial value
Port 0 data register (PDR0)
R/W
000000H
XXXXXXXXB
Port 1 data register (PDR1)
R/W
000001H
XXXXXXXXB
Port 2 data register (PDR2)
R/W
000002H
XXXXXXXXB
Port 3 data register (PDR3)
R/W
000003H
XXXXXXXXB
Port 4 data register (PDR4)
R/W
000004H
XXXXXXXXB
Port 5 data register (PDR5)
R/W
000005H
XXXXXXXXB
Port 6 data register (PDR6)
R/W
000006H
XXXXXXXXB
Port 7 data register (PDR7)
R/W
000007H
XXXXXXXXB
Port 8 data register (PDR8)
R/W
000008H
XXXXXXXXB
Port 0 data direction register (DDR0)
R/W
000010H
00000000B
Port 1 data direction register (DDR1)
R/W
000011H
00000000B
Port 2 data direction register (DDR2)
R/W
000012H
00000000B
Port 3 data direction register (DDR3)
R/W
000013H
00000000B
Port 4 data direction register (DDR4)
R/W
000014H
00000000B
Port 5 data direction register (DDR5)
R/W
000015H
XXXXXX00B
Port 6 data direction register (DDR6)
R/W
000016H
00000000B
Port 7 data direction register (DDR7)
R/W
000017H
00000000B
Port 8 data direction register (DDR8)
R/W
000018H
00000000B
Analog input enable register 0 (ADER0)
R/W
0000C5H
11111111B
Analog input enable register 1 (ADER1)
R/W
0000D0H
11111111B
Port 0 pull-up resistor setting register (RDR0)
R/W
00008CH
00000000B
Port 1 pull-up resistor setting register (RDR1)
R/W
00008DH
00000000B
Port 2 pull-up resistor setting register (RDR0)
R/W
00008EH
00000000B
Port 3 pull-up resistor setting register (RDR0)
R/W
00008FH
00000000B
R/W :Readable and writable
170
R
:Read-only
X
:Undefined
MB90820 series
Memo
MB90820 series
171
8.3
Port 0
Port 0 is a general-purpose I/O port. It can also be used for resource I/O. Individual
port pin can be switched between the I/O port and resource I/O. This section focuses
on the general I/O port function, also provides the configuration of port 0, lists of pins,
shows a block diagram of the pins, and describes the corresponding registers.
■ Port 0 configuration
Port 0 consists of the following:
•
General-purpose I/O pins/resources I/O pins (P00 to P07/PWO0)
•
Port 0 data register (PDR0)
•
Port 0 data direction register (DDR0)
•
Port 0 pull-up resistor setting register (RDR0)
■ Port 0 pins
The port 0 I/O pins are also used as resource I/O pins. Therefore, the pins cannot be used as
general purpose I/O port pins when they are used as resource I/O pins. Table 8.3-1 lists the port
0 pins.
Table 8.3-1
Port
Pin
Port 0 pins
I/O form
Port function
(single-chip mode)
Resource function
P00
P00
–
–
P01
P01
–
–
P02
P02
–
–
P03
P03
–
–
P04
P04
–
–
P05
P05
–
–
P06/PWI0
P06
PWI0
PWC0 input
P07/PWO0
P07
PWO0
PWC0 output
Port 0
Generalpurpose I/O
Input
Output
CMOS
(hysteresis)
CMOS
Circuit
type
C
See Section 1.7, "I/O Circuit Types", for information on the circuit types.
172
MB90820 series
■ Block diagram of port 0 pins
Figure 8.3-1 shows the block diagram of the P00 to P06/PWI0 pins.
RDR
Resource input
Port data register (PDR)
Pull-up resistor
Internal data bus
About 50KΩ
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 8.3-1 Block diagram of P00 to P06/PWI0 pins
Figure 8.3-2 shows the block diagram of the P07/PWO0 pins.
RDR
Resource output
Port data register (PDR)
Resource input
Resource output enable
Pull-up resistor
Internal data bus
About 50KΩ
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 8.3-2 Block diagram of P07/PWO0 pins
When the resource output enable bit is set, the port is forcibly caused to function as resource
output pin regardless of the value in the DDR0 register.
MB90820 series
173
■ Port 0 registers
Port 0 registers are PDR0, DDR0 and RDR0. The bits making up each register correspond to
the port 0 pins on a one-to-one basis. Table 8.3-2 lists the port 0 pins and their corresponding
register bits.
Table 8.3-2
Port 0 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR0, DDR0, RDR0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P07
P06
P05
P04
P03
P02
P01
P00
Port 0
See Section 1.7,"I/O Circuit Types", for information on the circuit types.
174
MB90820 series
8.3
Port 0
Memo
MB90820 series
175
8.3
Port 0
8.3.1 Port 0 Registers (PDR0, DDR0 and RDR0)
This section describes the port 0 registers.
■ Functions of port 0 registers
● Port 0 data register (PDR0)
The PDR0 register indicates the state of each pin of port 0.
● Port 0 data direction register (DDR0)
The DDR0 register specifies the direction of a data flow (input or output) at each pin (bit) of port
0. When a DDR0 register bit is “1”, the corresponding port (pin) is set as an output port. When
the bit is “0”, the port (pin) is set as an input port.
[Check]
•
When a resource having output pins is used, the port functions as resource output pins
regardless of the value in the DDR0 register as long as the resource output enable bit
corresponding to the pins is set.
•
To use a resource having input pins, reset the port direction register bit corresponding to
each resource input pin to “0” to place the port in input mode.
Table 8.3.1-1 lists the functions of the port 0 registers.
<reference>
When the MCU is reset, the DDR0 register is cleared to “0” for general I/O port input.
● Port 0 pull-up resistor setting register (RDR0)
The RDR0 register specifies the selection of a pull-up resistor at each pin (bit) of port 0. When a
RDR0 register bit is “1”, a pull-up resistor is selected for the corresponding port (pin). When the
bit is “0”, the pull-up resistor is deselected.
176
MB90820 series
Table 8.3.1-1 lists the functions of the port 0 registers.
Table 8.3.1-1 Port 0 register functions
Register
Data
During reading
During writing
0
The pin is at the low
level.
The output latch is loaded with 0. When
the pin functions as an output port, the
pin is set to the low level.
1
The pin is at the high
level.
The output latch is loaded with 1. When
the pin functions as an output port, the
pin is set to the high level.
Port 0 data
direction
register
(DDR0)
0
The direction latch is 0.
The output buffer is turned off to place
the port in input mode.
1
The direction latch is 1.
The output buffer is turned on to place
the port in output mode.
Port 0 pull-up
resistor setting
register
(RDR0)
0
The setting latch is 0.
The pull-up resistor is cut and the port is
placed in the Hi-Z state in input mode.
1
The setting latch is 1.
The pull-up resistor is selected and the
port is held at the high level in input
mode.
Port 0 data
register
(PDR0)
R/W
: Readable and writable
X
: Undefined
MB90820 series
Read/
Write
Address
Initial value
R/W
000000H
XXXXXXXXB
R/W
000010H
00000000B
R/W
00008CH
00000000B
177
8.3.2 Operation of Port 0
This section describes the operation of port 0.
■ Operation of port 0
● Port operation in output mode
•
Setting a bit of the DDR0 register to “1” places the corresponding port pin in output mode.
•
Data written to the PDR0 register in output mode is held in the output latch of the PDR0 and
output to the port pins.
•
The PDR0 register can be accessed in read mode to read the value at the port pins (the
same value as in the output latch of the PDR0).
<Check>
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port
data register, the target bits of the register are set to the specified value. The bits that have
been specified for output using the DDR register are not affected, but for the bits that have
been specified for input, a value input from the pins is written to the output latch and output
as is. Before switching the mode for the bits from input to output, therefore, write the output
data to the PDR register, then specify output mode in the DDR register.
● Port operation in input mode
•
Resetting a bit of the DDR0 register to “0” places the corresponding port pin in input mode.
•
In input mode, the output buffer is turned off, and the pin is in high-impedance state.
•
However, when the corresponding bit in RDR0 register is set to “1” to select a pull-up resistor,
the pin is held at the high level.
•
Data written to the PDR0 register in input mode is held in the output latch of the PDR0 but is
not output to the port pins.
•
The PDR0 register can be accessed in read mode to read the level value (“0” or “1”) at the
port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The
state of the resource enable bit takes precedence when specifying a switch between input and
output. Even if a DDR0 register bit is “0”, the corresponding port pin is used for resource output
if the resource has been enabled for output. Because the value at the pins can be read even if
resource output is enabled, the resource output value can be read.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as
resource inputs. To use an external signal for the resource, reset the corresponding bit in DDR0
register to “0” to place the port in input mode.
178
MB90820 series
● Port operation after a reset
•
When the MCU is reset, the DDR0 and RDR0 registers are initialized to “0”. As a result, the
output buffer is turned off (I/O mode changes to input), the pull-up resistor is cut, and the pins
are placed in a high-impedance state.
•
The PDR0 register is not initialized when the MCU is reset. To use the port in output mode,
therefore, output mode must be specified in the DDR0 register after the output data is set in
the PDR0 register.
● Port operation in stop or timebase timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register
(LPMCR) is already “1“ when the port is shifted to stop or timebase timer mode, the port pins are
placed in a high-impedance state. This is because the output buffer is turned off forcibly
regardless of the value in the DDR0 register. Note that the inputs are fixed at “H” level or “L”
level to prevent leakage due to an open circuit. Table 8.3.2-1 lists the states of the port 0 pins.
Table 8.3.2-1 States of port 0 pins
Pin
Normal operation
Sleep mode
Stop mode or
timebase timer
mode (SPL = 0)
P00 ~ P07/
PWO0
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O
port
Stop mode or
timebase timer
mode (SPL = 1,
RDR = 0)
Input disabled/output
in Hi-Z
Stop mode or
timebase timer
mode (SPL = 1,
RDR = 1)
Input disabled/held at
H level
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z : High impedance
MB90820 series
179
8.4
Port 1
Port 1 is a general-purpose I/O port. It can also be used for resource input. Individual
port pin can be switched between the I/O port and resource input. This section
focuses on the general I/O port function. The section also provides the configuration
of port 1, lists its pins, shows a block diagram of the pins, and describes the
corresponding registers.
■ Port 1 configuration
Port 1 consists of the following:
•
General-purpose I/O pins/resources input pins (P10/INT0/DTTI to P17)
•
Port 1 data register (PDR1)
•
Port 1 data direction register (DDR1)
•
Port 1 pull-up resistor setting register (RDR1)
■ Port 1 pins
The port 1 I/O pins are also used as resource input pins. Therefore, the pins cannot be used as
general purpose I/O port pins when they are used as resource input pins. Table 8.4-1 lists the
port 1 pins.
Table 8.4-1
Port 1 pins
I/O form
Port
Port 1
Pin
Port function
Resource function
P10/INT0/DTTI
P10
INT0/
DTTI
External interrupt input
/ waveform generator
input
P11/INT1
P11
INT1
External interrupt input
P12/INT2
P12
INT2
External interrupt input
INT3
External interrupt input
Generalpurpose I/O
P13/INT3
P13
P14/INT4
P14
INT4
External interrupt input
P15/INT5
P15
INT5
External interrupt input
P16/INT6
P16
INT6
External interrupt input
P17
P17
–
Input
Output
CMOS
(hysteresis)
CMOS
Circuit
type
D
–
See Section 1.7, "I/O Circuit Types", for information on the circuit types.
180
MB90820 series
■ Block diagram of port 1 pins
Figure 8.3-1 shows the block diagram of P10/DTTI/INT0 to P16/INT6 pins.
RDR
Resource input
Port data register (PDR)
Pull-up resistor
Internal data bus
About 50KΩ
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
External
interrupt
enable
DDR read
Standby control (SPL=1)
Figure 8.4-1 Block diagram of P10/DTTI/INT0 to P16/INT6 pins
Figure 8.4-2 shows the block diagram of P17 pin.
RDR
Resource input
Port data register (PDR)
Pull-up resistor
Internal data bus
About 50KΩ
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 8.4-2 Block diagram of P17
■ Port 1 registers
Port 1 registers are PDR1, DDR1 and RDR1. The bits making up each register correspond to
the port 1 pins on a one-to-one basis. Table 8.4-2 lists the port 1 pins and their corresponding
register bits.
MB90820 series
181
Table 8.4-2
Port 1 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR1, DDR1, RDR1
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Corresponding pin
P17
P16
P15
P14
P13
P12
P11
P10
Port 1
182
MB90820 series
8.4
Port 1
8.4.1 Port 1 Registers (PDR1, DDR1 and RDR1)
This section describes the port 1 registers.
■ Functions of port 1 registers
● Port 1 data register (PDR1)
The PDR1 register indicates the state of each pin of port 1.
● Port 1 data direction register (DDR1)
The DDR1 register specifies the direction of a data flow (input or output) at each pin (bit) of port
1. When a DDR1 register bit is “1”, the corresponding port (pin) is set as an output port. When
the bit is “0”, the port (pin) is set as an input port.
<check>
•
To use a resource having input pins, reset the port direction register bit corresponding to
each resource input pin to “0” to place the port in input mode.
<reference>
When the MCU is reset, the DDR1 register is cleared to “0” for general I/O port input.
● Port 1 pull-up resistor setting register (RDR1)
The RDR1 register specifies the selection of a pull-up resistor at each pin (bit) of port 1. When a
RDR1 register bit is “1”, a pull-up resistor is selected for the corresponding port (pin). When the
bit is “0”, the pull-up resistor is deselected.
Table 8.4.1-1 lists the functions of the port 1 registers.
Table 8.4.1-1 Port 1 register functions
Register
Data
During
reading
During writing
0
The pin is at
the low level.
The output latch is loaded with “0”. When
the pin functions as an output port, the pin
is set to the low level.
1
The pin is at
the high
level.
The output latch is loaded with “1”. When
the pin functions as an output port, the pin
is set to the high level.
0
The direction
latch is “0”.
The output buffer is turned off to place the
port in input mode.
1
The direction
latch is “1”.
The output buffer is turned on to place the
port in output mode.
0
The setting
latch is “0”.
The pull-up resistor is cut and the port is
placed in the Hi-Z state in input mode.
1
The setting
latch is “1”.
The pull-up resistor is selected and the
port is held at the high level in input mode.
Port 1 data
register (PDR1)
Port 1 data
direction register
(DDR1)
Port 1 pull-up
resistor setting
register (RDR1)
R/W
X
Read/
Write
Address
Initial value
R/W
000001H
XXXXXXXXB
R/W
000011H
00000000B
R/W
00008D H
00000000B
: Readable and writable
: Undefined
MB90820 series
183
8.4
Port 1
8.4.2 Operation of Port 1
This section describes the operation of port 1.
■ Operation of port 1
● Port operation in output mode
•
Setting a bit of the DDR1 register to “1” places the corresponding port pin in output mode.
•
Data written to the PDR1 register in output mode is held in the output latch of the PDR1 and
output to the port pins.
•
The PDR1 register can be accessed in read mode to read the value at the port pins (the
same value as in the output latch of the PDR1).
<Check>
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been
specified for input, a value input from the pins is written to the output latch and output as is.
Before switching the mode for the bits from input to output, therefore, write the output data to the
PDR register, then specify output mode in the DDR register.
● Port operation in input mode
•
Resetting a bit of the DDR1 register to “0” places the corresponding port pin in input mode.
•
In input mode, the output buffer is turned off, and the pin is in high-impedance state.
•
However, when the corresponding bit in RDR1 register is set to “1” to select a pull-up resistor,
the pin is held at the high level.
•
Data written to the PDR1 register in input mode is held in the output latch of the PDR1 but not
output to the port pins.
•
The PDR1 register can be accessed in read mode to read the level value (“0” or “1”) at the
port pins.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as
resource inputs. To use an external signal for the resource, reset the corresponding bit in DDR1
register to “0” to place the port in input mode.
● Port operation after a reset
184
•
When the MCU is reset, the DDR1 registers is initialized to “0”. As a result, the output buffer
is turned off (I/O mode changes to input), and the pins are placed in a high-impedance state.
•
The PDR1 register is not initialized when the MCU is reset. To use the port in output mode,
therefore, output mode must be specified in the DDR1 register after the output data is set in
the PDR1 register.
MB90820 series
● Port operation in stop or timebase timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register
(LPMCR) is already 1 when the port is shifted to stop or timebase timer mode, the port pins are
placed in a high-impedance state. This is because the output buffer is turned off forcibly
regardless of the value in the DDR1 register. Note that the inputs are fixed at “H” level or “L”
level to prevent leakage due to an open circuit. Table 8.4.2-1 lists the states of the port 1 pins.
Table 8.4.2-1 States of port 1 pins
Stop mode or
timebase timer
mode (SPL = 1,
RDR = 0)
Stop mode or
timebase timer
mode (SPL = 1,
RDR = 1)
Pin
Normal operation
Sleep mode
Stop mode or
timebase timer
mode (SPL = 0)
P10/INT0/
DTTI ~
P16/INT6
General-purpose
I/O port
General-purpose
I/O port
General-purpose
I/O port
Input enabled */
output in Hi-Z
Input enabled */
output in Hi-Z
P17
General-purpose
I/O port
General-purpose
I/O port
General-purpose
I/O port
Input disabled/
output in Hi-Z
Input disabled/
held at H level
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z : High impedance
*
: Only when P10/INT0/DTTI ~ P16/INT6 are configured as external interrupt pins, otherwise, input is
disabled.
MB90820 series
185
8.5
8.5
Port 2
Port 2
Port 2 is a general-purpose I/O port. It can also be used for resource I/O. Individual port
pin can be switched between the I/O port and resource I/O. This section focuses on the
general I/O port function. The section provides the configuration of port 2, lists its
pins, shows a block diagram of the pins, and describes the corresponding registers.
■ Port 2 configuration
Port 2 consists of the following:
•
General-purpose I/O pins/resource I/O pins (P20/TIN1 to P27)
•
Port 2 data register (PDR2)
•
Port 2 data direction register (DDR2)
•
Port 2 pull-up resistor setting register (RDR2)
■ Port 2 pins
The port 2 I/O pins are also used as resource I/O pins. Therefore, the pins cannot be used as
general purpose I/O port pins when they are used as resource I/O pins. Table 8.5-1 lists the port
2 pins.
Table 8.5-1
Port 2 pins
I/O form
Port
Pin
Port function
Resource function
P20/TIN1
P20
TIN1
16-bit reload timer 1 input
P21/TO1
P21
TO1
16-bit reload timer 1 output
P22
P22
–
–
P23
P23
–
–
P24
P24
–
–
P25
P25
–
–
P26
P26
–
–
P27
P27
–
–
Port 2
Generalpurpose I/O
Input
Output
CMOS
(hyster
esis)
CMOS
Circuit
type
D
See Section 1.7, "I/O Circuit Types", for information on the circuit types.
186
MB90820 series
■ Block diagram of port 2 pins
Figure 8.5-2 shows the block diagram of port 2 (excluding P21/TO1) pins.
RDR
Resource input
Port data register (PDR)
Pull-up resistor
Internal data bus
About 50KΩ
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 8.5-1 Block diagram of port 2 (excluding P21/TO1) pins
Figure 8.5-2 shows the block diagram of P21/TO1 pin.
RDR
Resource output
Port data register (PDR)
Resource input
Resource output enable
Pull-up resistor
Internal data bus
About 50KΩ
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 8.5-2 Block diagram of P21/TO1 pin
When the resource output enable bit is set, the port is forcibly caused to function as resource
output pin regardless of the value in the DDR2 register.
MB90820 series
187
■ Port 2 registers
Port 2 registers are PDR2, DDR2 and RDR2. The bits making up each register correspond to the
port 2 pins on a one-to-one basis. Table 8.5-2 lists the port 2 pins and their corresponding
register bits.
Table 8.5-2
Port 2 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR2, DDR2, RDR2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P27
P26
P25
P24
P23
P22
P21
P20
Port 2
188
MB90820 series
8.5
Port 2
8.5.1 Port 2 Registers (PDR2, DDR2 and RDR2)
This section describes the port 2 registers.
■ Functions of port 2 registers
● Port 2 data register (PDR2)
The PDR2 register indicates the state of each pin of port 2.
● Port 2 data direction register (DDR2)
The DDR2 register specifies the direction of a data flow (input or output) at each pin (bit) of port
2. When a DDR2 register bit is 1, the corresponding port (pin) is set as an output port. When
the bit is 0, the port (pin) is set as an input port.
<check>
•
When a resource having output pins is used, the port functions as resource output pins
regardless of the value in the DDR2 register as long as the resource output enable bit
corresponding to the pins is set.
•
To use a resource having input pins, reset the port direction register bit corresponding to
each resource input pin to 0 to place the port in input mode.
● Port 2 pull-up resistor setting register (RDR2)
The RDR2 register specifies the selection of a pull-up resistor at each pin (bit) of port 2. When a
RDR2 register bit is “1”, a pull-up resistor is selected for the corresponding port (pin). When the
bit is “0”, the pull-up resistor is deselected.
Table 8.5.1-1 lists the functions of the port 2 registers.
Table 8.5.1-1 Port 2 register functions
Register
Data
During
reading
During writing
0
The pin is at
the low level.
The output latch is loaded with 0. When
the pin functions as an output port, the pin
is set to the low level.
1
The pin is at
the high
level.
The output latch is loaded with 1. When
the pin functions as an output port, the pin
is set to the high level.
0
The direction
latch is 0.
The output buffer is turned off to place the
port in input mode.
1
The direction
latch is 1.
The output buffer is turned on to place the
port in output mode.
0
The setting
latch is “0”.
The pull-up resistor is cut and the port is
placed in the Hi-Z state in input mode.
1
The setting
latch is “1”.
The pull-up resistor is selected and the
port is held at the high level in input mode.
Port 2 data
register (PDR2)
Port 2 data
direction register
(DDR2)
Port 2 pull-up
resistor setting
register (RDR2)
R/W
X
Read/
Write
Address
Initial value
R/W
000002H
XXXXXXXXB
R/W
000012H
00000000B
R/W
00008EH
00000000B
: Readable and writable
: Undefined
MB90820 series
189
8.5
Port 2
8.5.2 Operation of Port 2
This section describes the operation of port 2.
■ Operation of port 2
● Port operation in output mode
•
Setting a bit of the DDR2 register to “1” places the corresponding port pin in output mode.
•
Data written to the PDR2 register in output mode is held in the output latch of the PDR2 and
output to the port pins.
•
The PDR2 register can be accessed in read mode to read the value at the port pins (the
same value as in the output latch of the PDR2).
<Check>
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been
specified for input, a value input from the pins is written to the output latch and output as is.
Before switching the mode for the bits from input to output, therefore, write the output data to the
PDR register, then specify output mode in the DDR register.
● Port operation in input mode
•
Resetting a bit of the DDR2 register to “0” places the corresponding port pin in input mode.
•
In input mode, the output buffer is turned off, and the pin is in high-impedance state.
•
However, when the corresponding bit in RDR2 register is set to “1” to select a pull-up resistor,
the pin is held at the high level.
•
Data written to the PDR2 register in input mode is held in the output latch of the PDR2 but not
output to the port pins.
•
The PDR2 register can be accessed in read mode to read the level value (“0” or “1”) at the
port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The state
of the resource enable bit takes precedence when specifying a switch between input and output.
Even if a DDR2 register bit is “0”, the corresponding port pin is used for resource output if the
resource has been enabled for output. Because the value at the pins can be read even if
resource output is enabled, the resource output value can be read.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as
resource inputs. To use an external signal for the resource, reset the corresponding bit in DDR2
register to “0” to place the port in input mode.
190
MB90820 series
● Port operation after a reset
•
When the MCU is reset, the DDR2 register is initialized to “0”. As a result, the output buffer is
turned off (I/O mode changes to input) and the pins are placed in a high-impedance state.
•
The PDR2 register is not initialized when the MCU is reset. To use the port in output mode,
therefore, output mode must be specified in the DDR2 register after the output data is set in
the PDR2 register.
● Port operation in stop or timebase timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register
(LPMCR) is already “1” when the port is shifted to stop or timebase timer mode, the port pins are
placed in a high-impedance state. This is because the output buffer is turned off forcibly
regardless of the value in the DDR2 register. Note that the inputs are fixed at “H” level or “L”
level to prevent leakage due to an open circuit. Table 8.5.2-1 lists the states of the port 2 pins.
Table 8.5.2-1 States of port 2 pins
Pin
Normal operation
Sleep mode
Stop mode or
timebase timer
mode (SPL = 0)
P20/TIN1 ~
P27
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O
port
Stop mode or
timebase timer
mode (SPL = 1,
RDR = 0)
Input disabled/output
in Hi-Z
Stop mode or
timebase timer
mode (SPL = 1,
RDR = 1)
Input disabled/held at
H level
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z: High impedance
MB90820 series
191
8.6
Port 3
Port 3 is a general-purpose I/O port. It can also be used for resource output. Individual
port pin can be switched between the I/O port and resource output. This section
focuses on the general I/O port function. The section provides the configuration of
port 3, lists its pins, shows a block diagram of the pins, and describes the
corresponding registers.
■ Port 3 configuration
Port 3 consists of the following:
•
General-purpose I/O pins/resources output pin (P30 to P37/PPG0)
•
Port 3 data register (PDR3)
•
Port 3 data direction register (DDR3)
•
Port 3 pull-up resistor setting register (RDR3)
■ Port 3 pins
The port 3 I/O pins are also used as resource output pin. Therefore, the pins cannot be used as
general purpose I/O port pins when they are used as resource output pin. Table 8.6-1 lists the
port 3 pins.
Table 8.6-1
Port 3 pins
I/O form
Port
Pin
Port function
Resource function
P30
P30
–
–
P31
P31
–
–
P32
P32
–
–
P33
P33
–
–
P34
P34
–
–
P35
P35
–
–
P36
P36
–
–
P37/PPG0
P37
Port 3
Generalpurpose I/O
PPG0
Input
Output
CMOS
CMOS
Circuit
type
E
PPG0 output
See Section 1.7, "I/O Circuit Types", for information on the circuit types.
192
MB90820 series
■ Block diagram of port 3 pins
Figure 8.6-2 shows the block diagram of port 3 (excluding P37/PPG0) pins.
RDR
Resource output
Port data register (PDR)
Resource output enable
Pull-up resistor
Internal data bus
About 50KΩ
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 8.6-1 Block diagram of port 3 (excluding P37/PPG0) pins
Figure 8.6-2 shows the block diagram of P37/PPG0 pin.
RDR
Resource output
Port data register (PDR)
Resource output enable
Pull-up resistor
Internal data bus
About 50KΩ
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 8.6-2 Block diagram of P37/PPG0 pin
When the resource output enable bit is set, the port is forcibly caused to function as resource
output pin regardless of the value in the DDR3 register.
MB90820 series
193
■ Port 3 registers
Port 3 registers are PDR3, DDR3 and RDR3. The bits making up each register correspond to
the port 3 pins on a one-to-one basis. Table 8.6-2 lists the port 3 pins and their corresponding
register bits.
Table 8.6-2
Port 3 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR3, DDR3, RDR3
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Corresponding pin
P37
P36
P35
P34
P33
P32
P31
P30
Port 3
194
MB90820 series
8.6
Port 3
8.6.1 Port 3 Registers (PDR3, DDR3 and RDR3)
This section describes the port 3 registers.
■ Functions of port 3 registers
● Port 3 data register (PDR3)
The PDR3 register indicates the state of each pin of port 3.
● Port 3 data direction register (DDR3)
The DDR3 register specifies the direction of a data flow (input or output) at each pin (bit) of port
3. When a DDR3 register bit is “1”, the corresponding port (pin) is set as an output port. When
the bit is “0”, the port (pin) is set as an input port.
<Check>
•
When a resource having output pins is used, the port functions as resource output pins
regardless of the value in the DDR3 register as long as the resource output enable bit
corresponding to the pins is set.
● Port 3 pull-up resistor setting register (RDR3)
The RDR3 register specifies the selection of a pull-up resistor at each pin (bit) of port 3. When a
RDR3 register bit is “1”, a pull-up resistor is selected for the corresponding port (pin). When the
bit is “0”, the pull-up resistor is deselected. Table 8.6.1-1 lists the functions of the port 3
registers.
Table 8.6.1-1 Port 3 register functions
Register
Data
During
reading
During writing
0
The pin is at
the low level.
The output latch is loaded with 0. When
the pin functions as an output port, the pin
is set to the low level.
1
The pin is at
the high
level.
The output latch is loaded with 1. When
the pin functions as an output port, the pin
is set to the high level.
0
The direction
latch is 0.
The output buffer is turned off to place the
port in input mode.
1
The direction
latch is 1.
The output buffer is turned on to place the
port in output mode.
0
The setting
latch is “0”.
The pull-up resistor is cut and the port is
placed in the Hi-Z state in input mode.
1
The setting
latch is “1”.
The pull-up resistor is selected and the
port is held at the high level in input mode.
Port 3 data
register (PDR3)
Port 3 data
direction register
(DDR3)
Port 3 pull-up
resistor setting
register (RDR3)
R/W
X
Read/
Write
Address
Initial value
R/W
000003H
XXXXXXXXB
R/W
000013H
00000000B
R/W
00008FH
00000000B
: Readable and writable
: Undefined
MB90820 series
195
8.6
Port 3
8.6.2 Operation of Port 3
This section describes the operation of port 3.
■ Operation of port 3
● Port operation in output mode
•
Setting a bit of the DDR3 register to “1” places the corresponding port pin in output mode.
•
Data written to the PDR3 register in output mode is held in the output latch of the PDR3 and
output to the port pins.
•
The PDR3 register can be accessed in read mode to read the value at the port pins (the
same value as in the output latch of the PDR3).
<Check>
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port data
register, the target bits of the register are set to the specified value. The bits that have been
specified for output using the DDR register are not affected, but for the bits that have been
specified for input, a value input from the pins is written to the output latch and output as is.
Before switching the mode for the bits from input to output, therefore, write the output data to the
PDR register, then specify output mode in the DDR register.
● Port operation in input mode
•
Resetting a bit of the DDR3 register to “0” places the corresponding port pin in input mode.
•
In input mode, the output buffer is turned off, and the pin is in high-impedance state.
•
However, when the corresponding bit in RDR3 register is set to “1” to select a pull-up resistor,
the pin is held at the high level.
•
Data written to the PDR3 register in input mode is held in the output latch of the PDR3 but not
output to the port pins.
•
The PDR3 register can be accessed in read mode to read the level value (“0” or “1”) at the
port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The state
of the resource enable bit takes precedence when specifying a switch between input and output.
Even if a DDR3 register bit is “0”, the corresponding port pin is used for resource output if the
resource has been enabled for output. Because the value at the pins can be read even if
resource output is enabled, the resource output value can be read.
● Port operation after a reset
196
•
When the MCU is reset, the DDR3 register is initialized to 0. As a result, the output buffer is
turned off (I/O mode changes to input) and the pins are placed in a high-impedance state.
•
The PDR3 register is not initialized when the MCU is reset. To use the port in output mode,
therefore, output mode must be specified in the DDR3 register after the output data is set in
the PDR3 register.
MB90820 series
● Port operation in stop or timebase timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register
(LPMCR) is already 1 when the port is shifted to stop or timebase timer mode, the port pins are
placed in a high-impedance state. This is because the output buffer is turned off forcibly
regardless of the value in the DDR3 register. Note that the inputs are fixed at a certain level to
prevent leakage due to an open circuit. Table 8.6.2-1 lists the states of the port 3 pins.
Table 8.6.2-1 States of port 3 pins
Pin
Normal operation
Sleep mode
Stop mode or
timebase timer
mode (SPL = 0)
P30 ~ P37/
PPG0
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O
port
Stop mode or
timebase timer
mode (SPL = 1,
RDR = 0)
Input disabled/output
in Hi-Z
Stop mode or
timebase timer
mode (SPL = 1,
RDR = 1)
Input disabled/held at
H level
SPL: Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z: High impedance
MB90820 series
197
8.7
Port 4
Port 4 is a general-purpose I/O port. It can also be used for resource I/O. Individual
port pin can be switched between the I/O port and resource I/O. This section focuses
on the general I/O port function, also provides the configuration of port 4, lists of pins,
shows a block diagram of the pins, and describes the corresponding registers.
■ Port 4 configuration
Port 4 consists of the following:
•
General-purpose I/O pins/resources I/O pins (P40/PPG1 to P47/PWO1)
•
Port 4 data register (PDR4)
•
Port 4 data direction register (DDR4)
■ Port 4 pins
The port 4 I/O pins are also used as resource I/O pins. Therefore, the pins cannot be used as
general purpose I/O port pins when they are used as resource I/O pins. Table 8.7-1 lists the port
4 pins.
Table 8.7-1
Port 4 pins
I/O form
Port
Pin
Port function
Resource function
Input
P40/PPG1
P40
PPG1
PPG1 output
P41/TIN0
P41
TIN0
16-bit reload timer 0 input
P42/TO0
P42
TO0
16-bit reload timer 0 output
P43/SCK0
P43
P44/SOT0
P44
P45/SIN0
SCK0
UART 0 serial clock I/O
SOT0
UART 0 data output
P45
SIN0
UART 0 data input
P46/PWI1
P46
PWI1
PWC1 input
P47/PWO1
P47
PWO1
PWC1 output
Port 4
Generalpurpose I/O
Output
Circuit
type
F
CMOS
(hysteresis)
CMOS
G
F
See Section 1.7, "I/O Circuit Types", for information on the circuit types.
198
MB90820 series
■ Block diagram of port 4 pins
Figure 8.7-1 shows the block diagram of port 4 pins (excluding P41/TIN0, P45/SIN0, P46/PWI1).
Resource output
Internal data bus
Port data register (PDR)
Resource input
Resource output enable
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 8.7-1 Block diagram of port 4 (excluding P41/TIN0, P45/SIN0, P46/PWI1) pins
When the resource output enable bit is set, the port is forcibly caused to function as resource
output pin regardless of the value in the DDR4 register.
Figure 8.7-2 shows the block diagram of P41/TIN0 and P46/PWI1 pins.
Resource input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 8.7-2 Block diagram of P41/TIN0 and P46/PWI1 pins
MB90820 series
199
Figure 8.7-3 shows the block diagram of P45/SIN0 pin.
UART0 data input
UART0 data input
level selection bit
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 8.7-3 Block diagram of P45/SIN0 pin
■ Port 4 registers
Port 4 registers are PDR4 and DDR4. The bits making up each register correspond to the port 4
pins on a one-to-one basis. Table 8.7-2 lists the port 4 pins and their corresponding register bits.
Table 8.7-2
Port 4 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR4, DDR4
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P47
P46
P45
P44
P43
P42
P41
P40
Port 4
200
MB90820 series
8.7
Port 4
8.7.1 Port 4 Registers (PDR4 and DDR4)
This section describes the port 4 registers.
■ Functions of port 4 registers
● Port 4 data register (PDR4)
The PDR4 register bit indicates the state of each pin of port 4.
● Port 4 data direction register (DDR4)
The DDR4 register specifies the direction of a data flow (input or output) at each pin (bit) of port
4. When a DDR4 register bit is “1”, the corresponding port (pin) is set as an output port. When
the bit is “0”, the port (pin) is set as an input port.
<Check>
•
When a resource having output pins is used, the port functions as resource output pins
regardless of the value in the DDR4 register as long as the resource output enable bit
corresponding to the pins is set.
•
To use a resource having input pins, reset the port direction register bit corresponding to
each resource input pin to “0” to place the port in input mode.
Table 8.7.1-1 list the functions of the port 4 register.
Table 8.7.1-1 Port 4 register functions
Register
Data
During
reading
During writing
0
The pin is at
the low level.
The output latch is loaded with 0. When
the pin functions as an output port, the pin
is set to the low level.
1
The pin is at
the high
level.
The output latch is loaded with 1. When
the pin functions as an output port, the pin
is set to the high level.
0
The direction
latch is 0.
The output buffer is turned off to place the
port in input mode.
1
The direction
latch is 1.
The output buffer is turned on to place the
port in output mode.
Port 4 data
register (PDR4)
Port 4 data
direction register
(DDR4)
Read/
Write
Address
Initial value
R/W
000004H
XXXXXXXXB
R/W
000014H
00000000B
R/W : Readable and writable
X
: Undefined
MB90820 series
201
8.7
Port 4
8.7.2 Operation of Port 4
This section describes the operation of port 4.
■ Operation of port 4
● Port operation in output mode
•
Setting a bit of the DDR4 register to “1” places the corresponding port pin in output mode.
•
Data written to the PDR4 register in output mode is held in the output latch of the PDR4 and
output to the port pins.
•
The PDR4 register can be accessed in read mode to read the value at the port pins (the
same value as in the output latch of the PDR4).
<Check>
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port
data register, the target bits of the register are set to the specified value. The bits that have
been specified for output using the DDR register are not affected, but for the bits that have
been specified for input, a value input from the pins is written to the output latch and output
as is. Before switching the mode for the bits from input to output, therefore, write output data
to the PDR register, then specify output mode in the DDR register.
● Port operation in input mode
•
Resetting a bit of the DDR4 register to “0” places the corresponding port pin in input mode.
•
In input mode, the output buffer is turned off, and the pins are placed in a high-impedance
state.
•
Data written to the PDR4 register in input mode is held in the output latch of the PDR4 but not
output to the port pins.
•
The PDR4 register can be accessed in read mode to read the level value (“0” or “1”) at the
port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The state
of the resource enable bit takes precedence when specifying a switch between input and output.
Even if a DDR4 register bit is “0”, the corresponding port pin is used for resource output if the
resource has been enabled for output. Because the value at the pins can be read even if
resource output is enabled, the resource output value can be read.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as
resource inputs. To use an external signal for the resource, reset the corresponding bit in DDR4
register to “0” to place the port in input mode.
202
MB90820 series
● Port operation after a reset
•
When the MCU is reset, the DDR4 register bits are initialized to “0”. As a result, the output
buffer is turned off (I/O mode changes to input) and the pins are placed in a high-impedance
state.
•
The PDR4 register is not initialized when the MCU is reset. To use the port in output mode,
therefore, output mode must be specified in the DDR4 register after the output data is set in
the PDR4 register.
● Port operation in stop or timebase timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register
(LPMCR) is already 1 when the port is shifted to stop or timebase timer mode, the port pins are
placed in a high-impedance state. This is because the output buffer is turned off forcibly
regardless of the value in the DDR4 register. Note that the inputs are fixed at “H” level or “L”
level to prevent leakage due to an open circuit.
Table 8.7.2-1 lists the states of the port 4 pins.
Table 8.7.2-1 States of port 4 pins
Pin
P40/PPG1 ~ P47/
PWO1
Normal operation
General-purpose I/O port
Sleep mode
General-purpose I/O port
Stop mode or
timebase timer
mode (SPL = 0)
General-purpose I/O
port
Stop mode or
timebase timer
mode (SPL = 1)
Input disabled/output
in Hi-Z
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z : High impedance
MB90820 series
203
8.8
Port 5
Port 5 is a general-purpose I/O port. It can also be used for resource I/O. Individual
port pin can be switched between the I/O port and resource I/O. This section focuses
on the general I/O port function, also provides the configuration of port 5, lists of pins,
shows a block diagram of the pins, and describes the corresponding registers.
■ Port 5 configuration
Port 5 consists of the following:
•
General-purpose I/O pins/resources I/O pins (P50/PPG2 and P51/INT7)
•
Port 5 data register (PDR5)
•
Port 5 data direction register (DDR5)
■ Port 5 pins
The port 5 I/O pins are also used as resource I/O pins. Therefore, the pins cannot be used as
general purpose I/O port pins when they are used as resource I/O pins. Table 8.8-1 lists the port
5 pins.
Table 8.8-1
Port 5 pins
I/O form
Port
Pin
Port function
P50/PPG2
P50
P51/INT7
P51
Port 5
Generalpurpose I/O
Resource function
PPG2
PPG2 output
INT7
External interrupt input
Input
Output
CMOS
(hysteresis)
CMOS
Circuit
type
F
See Section 1.7, "I/O Circuit Types", for information on the circuit types.
204
MB90820 series
■ Block diagram of port 5 pins
Figure 8.8-1 shows the block diagram of P50/PPG2 pin.
Resource input
Resource output
Internal data bus
Port data register (PDR)
Resource output enable
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 8.8-1 Block diagram of P50/PPG2 pin
Figure 8.8-2 shows the block diagram of P51/INT7 pin.
Resource input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
External
interrupt
enable
DDR read
Standby control (SPL=1)
Figure 8.8-2 Block diagram of P51/INT7 pin
When the resource output enable bit is set, the port is forcibly caused to function as resource
output pin regardless of the value in the DDR5 register.
MB90820 series
205
■ Port 5 registers
Port 5 registers are PDR5 and DDR5. The bits making up each register correspond to the port 5
pins on a one-to-one basis. Table 8.8-2 lists the port 5 pins and their corresponding register bits.
Table 8.8-2
Port 3 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR5, DDR5
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
-
-
-
-
-
-
P51
P50
Port 5
Corresponding pin
206
MB90820 series
8.8
Port 5
8.8.1 Port 5 Registers (PDR5 and DDR5)
This section describes the port 5 registers.
■ Functions of port 5 registers
● Port 5 data register (PDR5)
The PDR5 register indicates the state of each pin of port 5.
● Port 5 data direction register (DDR5)
The DDR5 register specifies the direction of a data flow (input or output) at each pin (bit) of port
5. When a DDR5 register bit is “1”, the corresponding port (pin) is set as an output port. When
the bit is “0”, the port (pin) is set as an input port.
<Check>
•
When a resource having output pins is used, the port functions as resource output pins
regardless of the value in the DDR5 register as long as the resource output enable bit
corresponding to the pins is set.
•
To use a resource having input pins, reset the port direction register bit corresponding to
each resource input pin to “0” to place the port in input mode.
Table 8.8.1-1 lists the functions of the port 5 registers.
Table 8.8.1-1 Port 5 register functions
Register
Data
During
reading
During writing
0
The pin is at
the low level.
The output latch is loaded with 0. When
the pin functions as an output port, the pin
is set to the low level.
1
The pin is at
the high
level.
The output latch is loaded with 1. When
the pin functions as an output port, the pin
is set to the high level.
0
The direction
latch is 0.
The output buffer is turned off to place the
port in input mode.
1
The direction
latch is 1.
The output buffer is turned on to place the
port in output mode.
Port 5 data
register (PDR5)
Port 5 data
direction register
(DDR5)
Read/
Write
Address
Initial value
R/W
000005H
XXXXXXXXB
R/W
000015H
XXXXXX00B
R/W : Readable and writable
X
: Undefined
MB90820 series
207
8.8.2 Operation of Port 5
This section describes the operation of port 5.
■ Operation of port 5
● Port operation in output mode
•
Setting a bit of the DDR5 register to “1” places the corresponding port pin in output mode.
•
Data written to the PDR5 register in output mode is held in the output latch of the PDR5 and
output to the port pins.
•
The PDR5 register can be accessed in read mode to read the value at the port pins (the
same value as in the output latch of the PDR5).
<Check>
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port
data register, the target bits of the register are set to the specified value. The bits that have
been specified for output using the DDR register are not affected, but for the bits that have
been specified for input, a value input from the pins is written to the output latch and output
as is. Before switching the mode for the bits from input to output, therefore, write output data
to the PDR register, then specify output mode in the DDR register.
● Port operation in input mode
•
Resetting a bit of the DDR5 register to “0” places the corresponding port pin in input mode.
•
In input mode, the output buffer is turned off, and the pins are placed in a high-impedance
state.
•
Data written to the PDR5 register in input mode is held in the output latch of the PDR5 but not
output to the port pins.
•
The PDR5 register can be accessed in read mode to read the level value (“0” or “1”) at the
port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The
state of the resource enable bit takes precedence when specifying a switch between input and
output. Even if a DDR5 register bit is “0”, the corresponding port pin is used for resource output
if the resource has been enabled for output. Because the value at the pins can be read even if
resource output is enabled, the resource output value can be read.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as
resource inputs. To use an external signal for the resource, reset the corresponding bit in DDR5
register to “0” to place the port in input mode.
● Port operation after a reset
208
•
When the MCU is reset, the DDR5 register bits are initialized to “0”. As a result, the output
buffer is turned off (I/O mode changes to input), and the pins are placed in a high-impedance
state.
•
The PDR5 register is not initialized when the MCU is reset. To use the port in output mode,
therefore, output mode must be specified in the DDR5 register after the output data is set in
the PDR5 register.
MB90820 series
● Port operation in stop or timebase timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register
(LPMCR) is already “1” when the port is shifted to stop or timebase timer mode, the port pins are
placed in a high-impedance state. This is because the output buffer is turned off forcibly
regardless of the value in the DDR5 register. Note that the inputs are fixed at “H” level or “L”
level to prevent leakage due to an open circuit. Table 8.8.2-1 lists the states of the port 5 pins.
Table 8.8.2-1 States of port 5 pins
Pin
Normal operation
Sleep mode
Stop mode or
timebase timer mode
(SPL = 0)
Stop mode or timebase
timer mode (SPL = 1)
P50/PPG2
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O port
Input disabled/output in Hi-Z
P51/INT7
General-purpose I/O
port
General-purpose I/O
port
General-purpose I/O port
Input enabled*/output in Hi-Z
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z : High impedance
*
: Only when P51/INT7 are configured as external interrupt pins, otherwise,
input is disabled.
MB90820 series
209
8.9
Port 6
Port 6 is a general-purpose I/O port. It can also be used for A/D converter input.
Individual port pin can be switched between the I/O port and A/D converter input. This
section focuses on the general I/O port function. It provides the configuration of port
6, lists its pins, shows a block diagram of the pins, and describes the corresponding
registers.
■ Port 6 configuration
Port 6 consists of the following:
•
General-purpose I/O pins/analog input pins (P60/AN0 to P67/AN7)
•
Port 6 data register (PDR6)
•
Port 6 data direction register (DDR6)
•
A/D input enable register 0 (ADER0)
■ Port 6 pins
The port 6 I/O pins are also used as A/D converter input pins. Therefore, the pins cannot be
used as general purpose I/O port pins when they are used as A/D converter input pins. Table
8.9-1 lists the port 6 pins.
Table 8.9-1
Port 6 pins
I/O form
Port
Pin
Port function
Resource function
P60/AN0
P60
AN0
A/D converter channel 0 input
P61/AN1
P61
AN1
A/D converter channel 1 input
P62/AN2
P62
AN2
A/D converter channel 2 input
P63/AN3
P63
AN3
A/D converter channel 3 input
P64/AN4
P64
AN4
A/D converter channel 4 input
P65/AN5
P65
AN5
A/D converter channel 5 input
P66/AN6
P66
AN6
A/D converter channel 6 input
P67/AN7
P67
AN7
A/D converter channel 7 input
Port 6
Generalpurpose
I/O
Input
Output
CMOS/
Analog
CMOS
Circuit
type
H
See Section 1.7, "I/O Circuit Types", for information on the circuit types.
210
MB90820 series
■ Block diagram of port 6 pins
Figure 8.9-1 shows the block diagram of P60/AN0 to P67/AN7.
AD converter input
AD converter channel selection bit
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
Figure 8.9-1 Block diagram of P60/AN0 to P67/AN7
When the A/D input enable bit is set, the port is forcibly caused to function as A/D converter
input pin regardless of the value in the DDR6 register.
■ Port 6 registers
Port 6 registers are PDR6, DDR6 and ADER0. The bits making up PDR6, DDR6 and ADER0
registers correspond to the Port 6 pin on one-to-one basis. Table 8.9-2 lists the port 6 pins and
their corresponding register bits.
Table 8.9-2
Port 6 pins and their corresponding register bits
Port
Register bits and corresponding port pins
PDR6, DDR6, ADER0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P67
P66
P65
P64
P63
P62
P61
P60
Port 6
MB90820 series
211
8.9
Port 6
8.9.1 Port 6 Registers (PDR6, DDR6 and ADER0)
This section describes the port 6 registers.
■ Functions of port 6 registers
● Port 6 data register (PDR6)
The PDR6 register indicates the state of each pin of port 6.
● Port 6 data direction register (DDR6)
The DDR6 register specifies the direction of a data flow (input or output) at each pin (bit) of
port 6. When a DDR6 register bit is “1”, the corresponding port (pin) is set as an output port.
When the bit is 0, the port (pin) is set as an input port.
<Check>
•
When A/D input enable bit is set, the corresponding port functions as A/D converter input pins
regardless of the value in the DDR6 register.
•
To use as general-purpose I/O port, reset the corresponding A/D converter input enable
register bit to “0” to place the port in general-purpose I/O mode.
● A/D input enable register 0 (ADER0)
Each bit of the ADER0 register specifies whether the corresponding port 6 pin is to be used as a
general-purpose I/O port or an A/D converter input pin. Setting an ADER0 bit to “1” enables the
corresponding pin for A/D converter input. Setting the bit to 0 enables the pin for generalpurpose I/O.
<check>
If a signal at an intermediate level is input in port I/O mode, input leak current flows.
Therefore, for a pin used for analog input, be sure to set the corresponding ADER0 bits to “1”
for A/D converter input.
[Reference]
When the MCU is reset, the DDR6 register is cleared to “0” and the ADER0 register is set to
“1” for A/D converter input.
212
MB90820 series
Table 8.9.1-1 lists the functions of the port 6 registers.
Table 8.9.1-1 Port 6 register functions
Data
During
reading
During writing
0
The pin is at
the low level.
The output latch is loaded with 0. When
the pin functions as an output port, the pin
is set to the low level.
1
The pin is at
the high
level.
The output latch is loaded with 1. When
the pin functions as an output port, the pin
is set to the high level.
Port 6 data
direction register
(DDR6)
0
The direction
latch is 0.
The output buffer is turned off to place the
port in input mode.
1
The direction
latch is 1.
The output buffer is turned on to place the
port in output mode.
A/D input enable
register 0
(ADER0)
0
Port I/O mode
1
Analog input mode
Register
Port 6 data
register (PDR6)
Read/
Write
Address
Initial value
R/W
000006H
XXXXXXXXB
R/W
000016H
00000000B
R/W
0000C5H
11111111B
R/W : Readable and writable
X
: Undefined
MB90820 series
213
8.9
Port 6
8.9.2 Operation of Port 6
This section describes the operation of port 6.
■ Operation of Port 6
● Port operation in output mode
•
Setting a bit of the ADER0 register to “0” places the corresponding port pin in Port I/O mode.
•
Setting a bit of the DDR6 register to “1” places the corresponding port pin in output mode.
•
Data written to the PDR6 register in output mode is held in the output latch of the PDR6 and
output to the port pins.
•
The PDR6 register can be accessed in read mode to read the value at the port pins (the
same value as in the output latch of the PDR6).
<Check>
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port
data register, the target bits of the register are set to the specified value. The bits that have
been specified for output using the DDR register are not affected, but for the bits that have
been specified for input, a value input from the pins is written to the output latch and output
as is. Before switching the mode for the bits from input to output, therefore, write output data
to the PDR register, then specify output mode in the DDR register.
● Port operation in input mode
•
Setting a bit of the ADER0 register to “0” places the corresponding port pin in Port I/O mode.
•
Resetting a bit of the DDR6 register to “0” to place the corresponding port pin in input mode.
•
In input mode, the output buffer is turned off, and the pins are placed in a high-impedance
state.
•
Data written to the PDR6 register in input mode is held in the output latch of the PDR6 but not
output to the port pins.
•
The PDR6 register can be accessed in read mode to read the level value (0 or 1) at the port
pins.
● Port operation for A/D converter input
To use a port pin for A/D converter input, write “1” to the corresponding ADER0 bit. Doing so
disables the port from operating as a general-purpose port pin and enables it to function as an A/
D converter input pin. When PDR6 is accessed in read mode in this situation, a value of “0” is
read.
214
MB90820 series
● Port operation after a reset
•
When the MCU is reset, the DDR6 register is initialized to “0” and the ADER0 register is
initialized to “1” to place the port in A/D converter input mode. To use the port as a generalpurpose port, write “0” to the ADER0 register in advance to place the port in port I/O mode.
•
When the MCU is reset, the DDR6 register bits are initialized to “0”. As a result, the output
buffer is turned off (I/O mode changes to input), and the pins are placed in a high-impedance
state.
•
The PDR6 register is not initialized when the MCU is reset. To use the port in output mode,
therefore, output mode must be specified in the DDR6 register after the output data is set in
the PDR6 register.
● Port operation in stop or timebase timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register
(LPMCR) is already “1” when the port is shifted to stop or timebase timer mode, the port pins are
placed in a high-impedance state. This is because the output buffer is turned off forcibly
regardless of the value in the DDR6 register. Note that the inputs are fixed at “H” level or “L”
level to prevent leakage due to an open circuit.
Table 8.9.2-1 lists the states of the port 6 pins.
Table 8.9.2-1 States of port 6 pins
Pin
P60/AN0 ~
P67/AN7
Normal operation
General-purpose I/O
port
Sleep mode
General-purpose I/O
port
Stop mode or timebase
timer mode (SPL = 0)
General-purpose I/O port
Stop mode or timebase
timer mode (SPL = 1)
Input disabled/output in Hi-Z
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z : High impedance
MB90820 series
215
8.10 Port 7
Port 7 is a general-purpose I/O port. It can also be used for resource I/O. Individual
port pin can be switched between the I/O port and resource I/O. This section focuses
on the general I/O port function. It provides the configuration of port 7, lists its pins,
shows a block diagram of the pins, and describes the corresponding registers.
■ Port 7 configuration
Port 7 consists of the following:
•
General-purpose I/O pins/resource I/O pins (P70/DA0/AN8 to P77/IN1/AN15)
•
Port 7 data register (PDR7)
•
Port 7 data direction register (DDR7)
•
A/D converter input enable register 1 (ADER1)
■ Port 7 pins
The port 7 I/O pins are also used as resource I/O pins. Therefore, the pins cannot be used as
general purpose I/O port pins when they are used as resource I/O pins. Table 8.10-1 lists the
port 7 pins.
Table 8.10-1 Port 7 pins
I/O form
Port
Pin
Port function
Resource function
Input
P70/DA0/
AN8
P70
DA0/
AN8
D/A converter output 0 /
A/D converter channel 8 input
P71/DA1/
AN9
P71
DA1/
AN9
D/A converter output 1 /
A/D converter channel 9 input
P72/SIN1/
AN10
P72
SIN1/
AN10
UART 0 data input /
A/D converter channel 10 input
P73/SOT1/
AN11
P73
SOT1/
AN11
UART 0 data output /
A/D converter channel 11 input
UART 0 serial clock I/O /
A/D converter channel 12 input
Output
Circuit
type
I
Generalpurpose I/O
Port 7
P74/SCK1/
AN12
P74
SCK1/
AN12
P75/FRCK/
AN13
P75
FRCK/
AN13
Free-run timer clock input /
A/D converter channel 13 input
P76/IN0/
AN14
P76
IN0/
AN14
Input capture channel 0 input /
A/D converter channel 14 input
P77/IN1/
AN15
P77
IN1/
AN15
Input capture channel 1 input /
A/D converter channel 15 input
J
CMOS
(hysteresis)
/ Analog
CMOS
K
See Section 1.7, "I/O Circuit Types", for information on the circuit types.
216
MB90820 series
■ Block diagram of port 7 pins
Figure 8.10-1 shows the block diagram of P70/DA0/AN8 and P71/DA1/AN9) pins.
AD converter channel selection bit
AD converter input
Internal data bus
Port data register (PDR)
DA converter output
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
DA converter output enable bit
Figure 8.10-1 Block diagram of P70/DA0/AN8 and P71/DA1/AN9 pins
When the D/A converter output enable bit or A/D input enable bit is set, the port is forcibly
caused to function as D/A converter output pin or A/D converter input pin regardless of the value
in the DDR7 register.
MB90820 series
217
Figure 8.10-2 shows the block diagram of P72/SIN1/AN10 pin.
AD converter channel selection bit
AD converter input
UART1 data input
UART1 data input
level selection bit
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
Figure 8.10-2 Block diagram of P72/SIN1/AN10 pin
When A/D input enable bit is set, the port is forcibly caused to function as A/D converter input pin
regardless of the value in the DDR7 register.
218
MB90820 series
Figure 8.10-3 shows the block diagram of port 7 (P73/SOT1/AN11 to P74/SCK1/AN12) pins.
AD converter input
AD converter channel selection bit
Resource input
Resource output
Internal data bus
Port data register (PDR)
Resource output enable
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
Figure 8.10-3 Block diagram of P73/SOT1/AN11 to P74/SCK1/AN12 pins
When the resource output enable bit is set, the port is forcibly caused to function as resource
output pin regardless of the value in the DDR7 register.
MB90820 series
219
Figure 8.10-4 shows the block diagram of P75/FRCK/AN13 to P77/IN1/AN15 pins.
AD converter input
AD converter channel selection bit
Resource input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
Figure 8.10-4 Block diagram of P73/SOT1/AN11 to P77/IN1/AN15 pins
■ Port 7 registers
Port 7 registers are PDR7, DDR7 and ADER1. The bits making up each register correspond to
the port 7 pins on a one-to-one basis. Table 8.10-2 lists the port 7 pins and their corresponding
register bits.
Table 8.10-2 Port 7 pins and their corresponding register bits
Port
Port 7
220
Register bits and corresponding port pins
PDR7, DDR7
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ADER1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P77
P76
P75
P74
P73
P72
P71
P70
MB90820 series
Memo
MB90820 series
221
8.10
Port 7
8.10.1 Port 7 Registers (PDR7, DDR7 and ADER1)
This section describes the port 7 registers.
■ Functions of port 7 registers
● Port 7 data register (PDR7)
The PDR7 register indicates the state of each pin of port 7.
● Port 7 data direction register (DDR7)
The DDR7 register specifies the direction of a data flow (input or output) at each pin (bit) of port
7. When a DDR7 register bit is “1”, the corresponding port (pin) is set as an output port. When
the bit is 0, the port (pin) is set as an input port.
<Check>
•
When D/A converter output enable bit or A/D input enable bit is set, the corresponding port
functions as D/A converter output pin or A/D converter input pin regardless of the value in the
DDR7 register.
•
To use as general-purpose I/O port, reset the corresponding D/A output enable bit and A/D
converter input enable register bit to “0” to place the port in general-purpose I/O mode.
● A/D input enable register 1 (ADER1)
Each bit of the ADER1 register specifies whether the corresponding port 7 pin is to be used as a
general-purpose I/O port or an A/D converter input pin. Setting an ADER1 bit to “1” enables the
corresponding pin for A/D converter input. Setting the bit to 0 enables the pin for generalpurpose I/O.
<check>
If a signal at an intermediate level is input in port I/O mode, input leak current flows.
Therefore, for a pin used for analog input, be sure to set the corresponding ADER1 bits to “1”
for A/D converter input.
[Reference]
When the MCU is reset, the DDR7 register is cleared to “0” and the ADER1 register is set to
“1” for A/D converter input.
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MB90820 series
Table 8.10.1-1 lists the functions of the port 7 registers.
Table 8.10.1-1 Port 7 register functions
Data
During
reading
During writing
0
The pin is at
the low level.
The output latch is loaded with 0. When
the pin functions as an output port, the pin
is set to the low level.
1
The pin is at
the high
level.
The output latch is loaded with 1. When
the pin functions as an output port, the pin
is set to the high level.
Port 7 data
direction register
(DDR7)
0
The direction
latch is 0.
The output buffer is turned off to place the
port in input mode.
1
The direction
latch is 1.
The output buffer is turned on to place the
port in output mode.
A/D converter
input enable
register 1
(ADER1)
0
Port I/O mode
1
A/D converter input mode
Register
Port 7 data
register (PDR7)
Read/
Write
Address
Initial value
R/W
000007H
XXXXXXXXB
R/W
000017H
00000000B
R/W
0000D0H
11111111B
R/W : Readable and writable
X
: Undefined
MB90820 series
223
8.10.2 Operation of Port 7
This section describes the operation of port 7.
■ Operation of port 7
● Port operation in output mode
•
Setting a bit of the ADER1 register to “0” places the corresponding port pin in Port I/O mode.
•
Setting a bit of the DDR7 register to “1” places the corresponding port pin in output mode.
•
Data written to the PDR7 register in output mode is held in the output latch of the PDR7 and
output to the port pins.
•
The PDR7 register can be accessed in read mode to read the value at the port pins (the
same value as in the output latch of the PDR7).
<Check>
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port
data register, the target bits of the register are set to the specified value. The bits that have
been specified for output using the DDR register are not affected, but for the bits that have
been specified for input, a value input from the pins is written to the output latch and output
as is. Before switching the mode for the bits from input to output, therefore, write output data
to the PDR register, then specify output mode in the DDR register.
● Port operation in input mode
•
Setting a bit of the ADER1 register to “0” places the corresponding port pin in Port I/O mode.
•
Resetting a bit of the DDR7 register to “0” places the corresponding port pin in input mode.
•
In input mode, the output buffer is turned off, and the pins are placed in a high-impedance
state.
•
Data written to the PDR7 register in input mode is held in the output latch of the PDR7 but not
output to the port pins.
•
The PDR7 register can be accessed in read mode to read the level value (“0” or “1”) at the
port pins.
● Port operation for A/D converter input
To use a port pin for A/D converter input, write “1” to the corresponding ADER1 bit. Doing so
disables the port from operating as a general-purpose port pin and enables it to function as an A/
D converter input pin. When PDR7 is accessed in read mode in this situation, a value of “0” is
read.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The
state of the resource enable bit takes precedence when specifying a switch between input and
output. Even if a DDR7 register bit is “0”, the corresponding port pin is used for resource output
if the resource has been enabled for output. Because the value at the pins can be read even if
resource output is enabled, the resource output value can be read.
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MB90820 series
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as
resource inputs. To use an external signal for the resource, reset the DDR7 register to 0 to
place the port in input mode.
● Port operation after a reset
•
When the MCU is reset, the DDR7 register is initialized to “0” and the ADER1 register is
initialized to “1” to place the port in A/D converter input mode. To use the port as a generalpurpose port, write “0” to the ADER1 register in advance to place the port in port I/O mode.
•
When the MCU is reset, the DDR7 register bits are initialized to “0”. As a result, the output
buffer is turned off (I/O mode changes to input), and the pins are placed in a high-impedance
state.
•
The PDR7 register is not initialized when the MCU is reset. To use the port in output mode,
therefore, output mode must be specified in the DDR7 register after the output data is set in
the PDR7 register.
● Port operation in stop or timebase timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register
(LPMCR) is already “1” when the port is shifted to stop or timebase timer mode, the port pins are
placed in a high-impedance state. This is because the output buffer is turned off forcibly
regardless of the value in the DDR7 register. Note that the inputs are fixed at “H” level or “L”
level to prevent leakage due to an open circuit. Table 8.10.2-1 lists the states of the port 7 pins.
Table 8.10.2-1 States of port 7 pins
Pin
P70/DA0/AN8 ~ P77/
IN1/AN15
Normal operation
General-purpose I/O
port
Sleep mode
Stop mode or
timebase timer mode
(SPL = 0)
General-purpose I/O
port
General-purpose I/O port
Stop mode or timebase
timer mode (SPL = 1)
Input disabled/output in Hi-Z
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z : High impedance
MB90820 series
225
8.11
Port 8
8.11 Port 8
Port 8 is a general-purpose I/O port. It can also be used for resource I/O. Individual
port pin can be switched between the I/O port and resource I/O. This section focuses
on the general I/O port function. This section also provides the configuration of port 8,
lists its pins, shows a block diagram of the pins, and describes the corresponding
registers.
■ Port 8 configuration
Port 8 consists of the following:
•
General-purpose I/O pins/resource I/O pins (P80/IN2 to P87/RTO5)
•
Port 8 data register (PDR8)
•
Port 8 data direction register (DDR8)
■ Port 8 pins
The port 8 I/O pins are also used as resource I/O pins. Therefore, the pins cannot be used as
general purpose I/O port pins when they are used as resource I/O pins. Table 8.11-1 lists the
port 8 pins.
Table 8.11-1 Port 8 pins
I/O form
Port
Pin
Port function
Resource function
Input
P80/IN2
P80
IN2
Input capture channel 2 input
P81/IN3
P81
IN3
Input capture channel 3 input
P82/RTO0
P82
RTO0
Waveform generator output 0
P83/RTO1
P83
RTO1
Waveform generator output 1
P84/RTO2
P84
RTO2
Waveform generator output 2
P85/RTO3
P85
RTO3
Waveform generator output 3
P86/RTO4
P86
RTO4
Waveform generator output 4
P87/RTO5
P87
RTO5
Waveform generator output 5
Output
Circuit
type
F
Port 8
Generalpurpose I/O
CMOS
(hysteresis)
CMOS
L
See Section 1.7, "I/O Circuit Types", for information on the circuit types.
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MB90820 series
■ Block diagram of port 8 pins
Figure 8.11-2 shows the block diagram of P80/IN2 and P81/IN3.
Resource input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 8.11-1 Block diagram of P80/IN2 to P81/IN3
Figure 8.11-2 shows the block diagram of P82/RTO0 to P87/RTO5.
Resource output
Internal data bus
Port data register (PDR)
Resource input
Resource output enable
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 8.11-2 Block diagram of P82/RTO0 to P87/RTO5
When the resource output enable bit is set, the port is forcibly caused to function as resource
output pin regardless of the value in the DDR8 register.
MB90820 series
227
■ Port 8 registers
Port 8 registers are PDR8 and DDR8. The bits making up each register correspond to the port 8
pins on a one-to-one basis. Table 8.11-2 lists the port 8 pins and their corresponding register
bits.
Table 8.11-2 Port 8 pins and their corresponding register bits
Port
Port 8
228
Register bits and corresponding port pins
PDR8, DDR8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P87
P86
P85
P84
P83
P82
P81
P80
MB90820 series
8.11.1 Port 8 Registers (PDR8 and DDR8)
This section describes the port 8 registers.
■ Functions of port 8 registers
● Port 8 data register (PDR8)
The PDR8 register indicates the state of each pin of port 8.
● Port 8 data direction register (DDR8)
The DDR8 register specifies the direction of a data flow (input or output) at each pin (bit) of port
8. When a DDR8 register bit is “1”, the corresponding port (pin) is set as an output port. When
the bit is “0“, the port (pin) is set as an input port.
<Check>
•
When a resource having output pins is used, the port functions as resource output pins
regardless of the value in the DDR8 register as long as the resource output enable bit
corresponding to the pins is set.
•
To use a resource having input pins, reset the port direction register bit corresponding to
each resource input pin to “0” to place the port in input mode.
Table 8.11.1-1 lists the functions of the port 8 registers.
Table 8.11.1-1 Port 8 register functions
Register
Data
During
reading
During writing
0
The pin is at
the low level.
The output latch is loaded with 0. When
the pin functions as an output port, the pin
is set to the “L” level.
1
The pin is at
the high
impedance.
The output buffer is turned off to place the
port in input mode.
0
The direction
latch is 0.
The output buffer is turned off to place the
port in input mode.
1
The direction
latch is 1.
The output buffer is turned off to place the
port in input mode.
Port 8 data
register (PDR8)
Port 8 data
direction register
(DDR8)
Read/
Write
Address
Initial value
R/W
000008H
XXXXXXXXB
R/W
000018H
00000000B
R/W : Readable and writable
X
: Undefined
MB90820 series
229
8.11.2 Operation of Port 8
This section describes the operation of port 8.
■ Operation of port 8
● Port operation in output mode
•
Setting a bit of the DDR8 register to “1” places the corresponding port pin in output mode.
•
Data written to the PDR8 register in output mode is held in the output latch of the PDR8 and
output to the port pins.
•
The PDR8 register can be accessed in read mode to read the value at the port pins (the
same value as in the output latch of the PDR8).
<Check>
If a read-modify-write instruction (such as an instruction that sets bits) is used with the port
data register, the target bits of the register are set to the specified value. The bits that have
been specified for output using the DDR register are not affected, but for the bits that have
been specified for input, a value input from the pins is written to the output latch and output
as is. Before switching the mode for the bits from input to output, therefore, write the output
data to the PDR register, then specify output mode in the DDR register.
● Port operation in input mode
•
Resetting a bit of the DDR8 register to “0” places the corresponding port pin in input mode.
•
In input mode, the output buffer is turned off, and the pins are placed in a high-impedance
state.
•
Data written to the PDR8 register in input mode is held in the output latch of the PDR8 but not
output to the port pins.
•
The PDR8 register can be accessed in read mode to read the level value (“0” or “1”) at the
port pins.
● Port operation for resource output
The resource output enable bit is set to enable the port to be used for resource output. The
state of the resource enable bit takes precedence when specifying a switch between input and
output. Even if a DDR8 register bit is “1”, the corresponding port pin is used for resource output
if the resource has been enabled for output. Because the value at the pins can be read even if
resource output is enabled, the resource output value can be read.
● Port operation for resource input
When the port is also used for resource input, the value at the pins is always supplied as
resource inputs. To use an external signal for the resource, reset the PDR8 register to 1 to
place the port in input mode.
230
MB90820 series
● Port operation after a reset
•
When the MCU is reset, the DDR8 register bits are initialized to “0”. As a result, the output
buffer is turned off (I/O mode changes to input), and the pins are placed in a high-impedance
state.
•
The PDR8 register is not initialized when the MCU is reset. To use the port in output mode,
therefore, output mode must be specified in the DDR8 register after the output data is set in
the PDR8 register.
● Port operation in stop or timebase timer mode
If the pin state specification bit (SPL) in the low-power consumption mode control register
(LPMCR) is already 1 when the port is shifted to stop or timebase timer mode, the port pins are
placed in a high-impedance state. This is because the output buffer is turned off forcibly
regardless of the value in the PDR8 register. Note that the inputs are fixed at “H” level or “L”
level to prevent leakage due to an open circuit. Table 8.11.2-1 lists the states of the port 8 pins.
Table 8.11.2-1 States of port 8 pins
Pin
P80/IN2 ~ P87/
RTO5
Normal operation
General-purpose I/O port
Sleep mode
General-purpose I/O port
Stop mode or
timebase timer
mode (SPL = 0)
General-purpose I/O
port
Stop mode or
timebase timer
mode (SPL = 1)
Input disabled/output
in Hi-Z
SPL : Pin state specification bit of low-power consumption mode control register (LPMCR)
Hi-Z : High impedance
MB90820 series
231
8.12 Sample Program for the I/O Port
This section contains a sample program using I/O port pins.
■ Sample program for the I/O port
●
Processing specification
• Ports 0 and 1 are used to turn on all segments of a seven-segment (eight-segment if the
decimal point is included) LED.
• Pin P00 corresponds to the anode common pin of the LED and pins P10 to P17
correspond to the segment pins.
Figure 8.12-1 shows an example of connecting the eight-segment LED to the MB90820
series ports.
MB90820 series
P00
P17
P16
P15
P14
P13
P12
P11
P10
Figure 8.12-1 Example of eight-segment LED connection
●
Coding example
void main(void)
{
IO_DDR0.byte=0x0ff;
IO_DDR1.byte=0x0ff;
IO_PDR0.byte=0x00;
IO_PDR1.byte=0x0ff;
.
.
/*Put all port 0 bit in output mode*/
/*Put all port 1 bit in output mode*/
/*Put P00 at a low level (#xxxxxxx0b)*/
/*Set all port 1 bits to 1*/
/*User set bit patterns of Port 1 to turn*/
/*on/off accordingly*/
.
}
232
MB90820 series
CHAPTER 9
TIMEBASE TIMER
This chapter describes the functions and operation of the timebase timer.
9.1 Overview of the Timebase Timer
9.2 Configuration of the Timebase Timer
9.3 Timebase Timer Control Register (TBTC)
9.4 Timebase Timer Interrupts
9.5 Operation of the Timebase Timer
9.6 Usage Notes on the Timebase Timer
9.7 Sample Program for the Timebase Timer Program
MB90820 series
233
9.1
Overview of the Timebase Timer
The timebase timer is an 18-bit free-running counter (timebase counter) that counts up
in synchronization with the internal count clock (one-half of the source oscillation).
The timer has an interval timer function that can select four intervals.
The timebase timer also has functions for timer output of the oscillation stabilzation
time and for supplying the clocks for the watchdog timer.
■ Interval timer function
The interval timer function repeatedly generates an interrupt request at a given interval.
•
An interrupt request is generated when the interval timer bit for the timebase counter
overflows.
•
The interval timer bit (interval) can be selected from four types. Table 9.1-1 lists the intervals
for the timebase timer.
Table 9.1-1 Intervals for the timebase timer
Internal count clock cycle
Interval cycle
212 / HCLK (Approx. 1.0 ms)
214 / HCLK (Approx. 4.1 ms)
2 / HCLK (0.5 µs)
216 / HCLK (Approx. 16.4 ms)
219 / HCLK (Approx. 131.1 ms)
HCLK: Oscillation clock
Values in parentheses are for a 4 MHz oscillation clock.
234
MB90820 series
■ Clock supply function
The clock supply function supplies clocks to the oscillation stabilization time timer and to some
peripheral functions.
Table 9.1-2 lists the cycle times of clocks supplied from the timebase timer to each peripheral.
Table 9.1-2 Clock cycle time supplied from the timebase timer
Clock destination
Clock cycle time
213 / HCLK (Approx. 2.0 ms)
Oscillation
stabilzation time
Remarks
Oscillation stabilzation time for ceramic vibrator
215 / HCLK (Approx. 8.2 ms)
Oscillation stabilzation time for crystal vibrator
218 / HCLK (Approx. 65.4 ms)
212 / HCLK (Approx. 1.0 ms)
214 / HCLK (Approx. 4.1 ms)
Watchdog timer
Count-up clock for watchdog timer
216 / HCLK (Approx. 16.4 ms)
219 / HCLK (Approx. 131.1 ms)
HCLK: Oscillation clock
Values in parentheses occurs during operation of the 4 MHz oscillation clock.
[Reference]
The oscillation stablization time is the yardstick because the oscillation cycle time is unstable
as soon as oscillation starts.
MB90820 series
235
9.2
Configuration of the Timebase Timer
The timebase timer consists of the following four blocks:
• Timebase timer counter
• Counter clear circuit
• Interval timer selector
• Timebase timer control register (TBTC)
■ Block diagram of the timebase timer
Figure 9.2-1 shows the block diagram of the timebase timer.
To watchdog timer
Timebase
timer counter
Divide-by
-two HCLK
×21 ×22
×23
...
...
×28
×29
×210 ×211 ×212 ×213 ×214 ×215 ×216 ×217 ×218
OF
OF
OF
OF
Counter clear
OF
To the oscillation
setting time selector in the clock control section
Power-on reset
Stop mode start
CKSCR: MCS = 1 to 0(*1)
Counter
clear circuit
TBOF clear
Interval
timer selector
TBOF set
Timebase timer
interrupt signal
#36 (24H)(*2)
—
—
—
TBIE TBOF
OF:Overflow
HCLK: Oscillation clock
*1 Switching of the machine clock from the oscillation clock to the PLL clock
*2 Interrupt number
TBR TBC1 TBC0
Timebase timer interrpt register (TBTC)
Figure 9.2-1 Block diagram of the timebase timer
● Timebase timer counter
This 18-bit up counter uses the divide-by-two clock of the oscillation clock (HCLK) as the count
clock.
● Counter clear circuit
Used to clear the counter by writing 0 to the TBTC:TBR bit, by a power-on reset or by transition
to stop mode (LPMCR: STP = 1).
● Interval timer selector
Selects one of four outputs of the timebase timer counter. An overflow of the selected bit
becomes an interrupt cause.
● Timebase timer control register (TBTC)
236
Selects the interval, clears the counter, controls an interrupt request, and checks the status.
MB90820 series
Memo
MB90820 series
237
9.3
Timebase Timer Control Register (TBTC)
The timebase timer control register (TBTC) selects the interval, clears the counter,
controls interrupts, and checks the status.
■ Timebase timer control register (TBTC)
bit15 bit14 bit13 bit12 bit11 bit10 bit9
Address
0000A9H
RESV
R/W
-
-
bit8
bit7
TBIE TBOF TBR TBC1 TBC0
R/W
R/W
W
R/W
bit0
Initial value
(WDTC)
1XX00100B
R/W
TBC1 TBC0
Interval selection bit
0
0
212/HCLK (Approx. 1.0 ms)
0
1
214/HCLK (Approx. 4.1 ms)
1
0
216/HCLK (Approx. 16.4 ms)
1
1
219/HCLK (Approx. 131 ms)
Values in parentheses are for a 4 MHz oscillation clock.
Timebase timer initialization bit
TBR
During reading
During writing
Clearing of the timebase timer
counter and TBOF bit
0
-
1
The read value is always 1.
TBOF
No change, no effect on other bits.
Interrupt request flag bit
During reading
0
No overflow from the
specified bit
Clearing of this bit
1
Overflow from the specified
bit
No change, no effect on other bits.
TBIE
Interrupt request enable bit
0
Interrupt request output disabled
1
Interrupt request output enabled
RESV
R/W:
W:
-:
x:
Read/write
Write only
Not used
Undefined
Initial value
During writing
Reserved bit
Always write 1 to this bit.
Figure 9.3-1 Timebase timer control register (TBTC)
238
MB90820 series
Table 9.3-1 Function description of each bit in the timebase timer control register (TBTC)
Bit name
Function
bit15
RESV:
Reserved bit
bit14
bit13
Not used
• When read, the value is undefined.
• Writing has no effect on operation.
bit12
TBIE:
Interrupt request
enable bit
• Used to enable or disable the output of an interrupt request
to the CPU.
• When this bit and the interrupt request flag bit (TBOF) are
1, an interrupt request is output.
bit11
TBOF:
Interrupt request
flag bit
bit10
TBR:
Timebase timer
initialization bit
<Caution>
Always write 1 to this bit.
• This bit is set to 1 when the bit specifying the timebase
timer counter overflows.
• When this bit and the interrupt request enable bit (TBIE) are
1, an interrupt request is output.
• During writing, this bit is cleared with 0. If 1 is written, the
bit does not change and there is no effect.
<Caution>
• To clear the TBOF bit, disable the timebase timer
interrupt by specifying the TBIE bit or processor status
(PS) ILM bit.
• The TBOF bit is cleared by writing 0, by a transition to
stop mode, by clearing of the timebase timer with the
TBR bit or by a reset.
• Used to clear the timebase timer counter.
• When 0 is written to this bit, the counter is cleared and the
TBOF bit is cleared. If 1 is written, the bit does not change
and there is no effect.
[Reference]
The read value is always 1.
bit9
bit8
MB90820 series
TBC1, TBC0:
Interval selection
bit
• Used to select an interval timer cycle.
• The bit for the interval timer of the timebase timer counter is
specified.
• Four types of interval can be selected.
239
9.4
Timebase Timer Interrupts
The timebase timer can generate an interrupt request when the bit specifying the
timebase timer counter overflows.
■ Timebase timer interrupts
The interrupt request flag bit (TBTC: TBOF) is set to 1 when the timebase timer counter counts
up with the internal count clock and when the bit for the selected interval timer bit overflows. If
the interrupt request enable bit has been enabled (TBTC: TBIE = 1), an interrupt request (#36) is
generated in the CPU. Write 0 to the TBOF bit in the interrupt handling routine to clear the
interrupt request. When the specified bit overflows, the TBOF bit is set regardless of the TBIE
bit value.
<Check>
Clear the interrupt request flag bit (TBTC: TBOF) while a timebase timer interrupt is disabled
by setting the TBIE bit or the processor status (PS) ILM bit.
[Reference]
•
When the TBOF bit is 1, if the TBIE bit status is switched from disable to enable (0 → 1),
an interrupt request occurs immediately.
■ Timebase timer interrupts and EI²OS
Table 9.4-1 lists the timebase timer interrupt and EI2OS.
Table 9.4-1 Timebase interrupts and EI2OS
Interrupt
number
#36 (24 H)
Interrupt level setting
register
Vector table address
EI2OS
Register name
Address
Lower
Upper
Bank
ICR12
0000BC H
FFFF6CH
FFFF6DH
FFFF6EH
∆
∆: Usable when an interrupt cause that shares the ICR is not used.
<Check>
ICR12 is common to the timebase timer interrupt and input capture channels 2/3 interrupt.
Interrupts can be used for two applications, but the interrupt level is the same.
240
MB90820 series
9.5
Operation of the Timebase Timer
The timebase timer provides the interval timer function and the clock supply function
that supplies clocks to some peripheral functions.
■ Operation of the interval timer function (timebase timer)
The interval timer function generates an interrupt request for each interval
The setting in Figure 9.5-1 is required to all the timer to operate as an interval timer.
bit15 bit14 bit13 bit12 bit11 bit10
TBTC
RESV
-
-
1
bit9
bit8 bit7
TBIE TBOF TBR TBC1 TBC0
0
bit0
WDTC
0
: Used
0 : Set 0
1 : Set 1
Figure 9.5-1 Setting of the timebase timer
•
The timebase timer counter continues counting up in synchronization with the internal count
clock (one-half of the oscillation clock) as long as the clock is being oscillated.
•
When the counter is cleared (TBR = 0), it counts up from 0. When the interval timer bit
overflows, the interrupt request flag bit (TBOF) is set to 1. If interrupt request output has
been enabled (TBIE = 1), an interrupt is generated for each selected interval based on the
cleared time.
•
The interval may become longer than the time set because of timebase timer clearing.
■ Oscillation stablizationi time timer function
The timebase timer is also used as the oscillation stabilzation time timer for oscillation and the
PLL clocks.
The oscillation stabilzation time is set for the interval from the time the counter counts up from 0
(count clear) until the oscillation stabilzation time bit overflows. When control returns from
timebase timer mode to PLL clock mode, the oscillation stablization time starts from the middle
of counting because the timebase timer counter has been not cleared. Table 9.5-1 shows the
clearing of the timebase counter and the oscillation stablization times.
MB90820 series
241
Table 9.5-1 Timebase timer counter clearing and oscillation settling times
Operation
Counter
clear
TBOF
clear
TBTC: Writing of 0 to TBR
O
O
O
O
Oscillation clock oscillation stablization time
Releasing of stop mode
O
O
Oscillation clock oscillation stablization time (at
return to main clock mode)
Transition from oscillation
clock mode to PLL clock
mode (MCS = 1 → 0)
O
O
PLL clock oscillation stablization time
Releasing of timebase timer
mode
X
X
PLL clock oscillation stablization time (at return to
PLL clock mode)
Releasing of sleep mode
X
X
Oscillation settling time
Power-on reset
Watchdog reset
O: Available
X: Not available
■ Clock supply function
The timebase timer supplies clocks to the watchdog timer. Clearing of the timebase counter
affects operation of the watchdog timer.
242
MB90820 series
9.6
Usage Notes on the Timebase Timer
Notes about the effects on peripheral functions of clearing interrupt requests and the
timebase timer are given below.
■ Timebase timer usage notes
● Clearing interrupt requests
The TBOF bit of the timebase timer control register must be cleared while a timebase timer
interrupt is masked by the TBIE bit or the interrupt level mask register (ILM) of the processor
status (PS).
● Effects of timebase timer clearing
Clearing of the timebase timer counter affects the following operations:
•
When the timebase timer is using the interval timer function (interval interrupt)
•
When the watchdog timer is being used
● Use of the timebase timer as the oscillation stablization time timer
At power-on, the source oscillation of the main clock stops in main stop mode. After oscillator
operation starts, the operating clock supplied by the timebase timer is used to take the oscillation
stabilization wait time of the main clock. An appropriate oscillation stabilization wait time must
be selected based on the type of oscillating element connected to the main clock oscillator (clock
generation section). See Section 4.5, "Oscillation Stabilization Wait Time", for details.
● Notes on peripheral functions to which clocks are supplied from the timebase timer
In the mode in which the main clock source oscillation stops, the counter is cleared and
timebase timer operation stops. When the timebase timer counter is cleared, the clock supplied
from the timebase timer is supplied from its initial state. As a result, the H level is shortened and
the L level lengthened 1/2 cycle. Although the clock for the watchdog timer is also supplied from
its initial state; the watchdog timer operates in normal cycles because the watchdog timer
counter is cleared at the same time.
■ Operation of the timebase timer
The following operations are shown in Figure 9.6-1:
•
A power-on reset occurs.
•
Sleep mode is entered during operation of the interval timer function.
•
A counter clear request is issued.
When stop mode is entered, the timebase timer is cleared and its operation stops. On return
from stop mode, the timebase timer counts the oscillation stablization time.
MB90820 series
243
Counter value
3FFFFH
Cleared by transition to
stop mode.
Oscillation stabilization
delay overflow
0000H
CPU operation starts
Power-on reset
(optional)
Counter clear
(TBTC: TBR = “0”)
Interval cycle
(TBTC: TBC1, TBC0 = “11 B”)
Cleared by the interrupt
handling routine.
TBOF bit
Sleep mode
TBIE bit
SLP bit
(STBC register)
STP bit
(STBC register)
Stop
Releasing of interval interrupt sleep
Releasing of Stop by an external interrupt
When 11B has been set in the interval selection bit
(TBTC:TBC1,TBC0) of the timebase timer control register
: Indicates the oscillation stabilization time.
Figure 9.6-1 Timebase timer operations
244
MB90820 series
9.7
Sample Program for the Timebase Timer Program
This section contains a sample program for the timebase timer.
■ Sample program for the timebase timer
● Processing
An interval interrupt of 212 / HCLK (HCLK: oscillation clock) is repeatedly generated. The interval
becomes approx. 1.0 ms (during 4 MHz operation).
● Coding example
ICR12
EQU
0000BCH
; Timebase timer interrupt control register
TBTC
EQU
0000A9H
; Timebase timer control register
TBOF
EQU
TBTC:3
; Interrupt request flag bit
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
; Assumes that stack pointer (SP) has already been
initialized
AND
CCR,#0BFH
; Disables interrupts
MOV
I:ICR12 #00H
; Interrupt level 0 (highest)
MOV
I:TBTC,#10010000B ; Fixes upper 3 bits
; Enables interrupts and clears TBOF
; Clears counter
;
;
;
;
Selects interval 212/HCLK
Sets PS ILM to level 7
Enables interrupts
Endless loop
MOV
ILM,#07H
OR
CCR,#40H
LOOP:
MOV
A,#00H
MOV
A,#01H
BRA
LOOP
;-------Interrupt program--------------------------------------------------------------------------------------------WARI:
CLRB I:TBOF
; Clears interrupt request flag
;
:
;
User handling
;
:
RETI
; Returns from interrupt
CODE
ENDS
;-------Vector setting-------------------------------------------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG
0FF6CH
; Sets vector for interrupt #36 (24H)
DSL
WARI
ORG
0FFDCH
; Sets reset vector
DSL
START
MB90820 series
245
VECT
246
DB
ENDS
END
00H
; Sets single-chip mode
START
MB90820 series
CHAPTER 10
WATCHDOG TIMER
This chapter describes the functions and operation of the watchdog timer.
10.1 Overview of the Watchdog Timer
10.2 Configuration of the Watchdog Timer
10.3 Watchdog Timer Control Register (WDTC)
10.4 Operation of the Watchdog Timer
10.5 Usage Notes on the Watchdog Timer
10.6 Sample Program for the Watchdog Timer
MB90820 series
247
10.1 Overview of the Watchdog Timer
The watchdog timer is a 2-bit counter that uses the timebase timer supply clock as the
count clock. After activation, if the watchdog timer is not cleared within a given time,
the CPU is reset.
■ Watchdog timer function
The watchdog timer is a counter for handling program crashes. Once the watchdog timer is
activated, it must be regularly cleared within a given time. If the program results in an endless
loop and the watchdog timer is not cleared over a given time, a watchdog reset is generated for
the CPU.
Table 10.1-1 lists the watchdog timer intervals. If the watchdog timer is not cleared, a watchdog
reset is generated between the minimum time and maximum time. Clear the counter within the
minimum time listed in this table.
Table 10.1-1 Intervals for the watchdog timer
Interval
Minimum*
Maximum*
Oscillation clock cycle count
Approx. 3.58 ms
Approx. 4.61 ms
214 ±211 cycle
Approx. 14.33 ms
Approx. 18.3 ms
216 ±213 cycle
Approx. 57.23 ms
Approx. 73.73 ms
218 ±215 cycle
Approx. 458.75 ms
Approx. 589.82 ms
221 ±218 cycle
* Value during operation of the 4 MHz oscillation clock
The maximum and minimum watchdog timer intervals and the oscillation clock cycle count
depend on the clear timing.
The interval is 3.5 to 4.5 times longer than the cycle of the count clock (timebase timer supply
clock).
See Section 10.4, "Operation of the Watchdog Timer".
<Check>
The watchdog counter consists of a 2-bit counter that uses the carry signals of the timebase
timer as count clocks. Therefore, if the timebase timer is cleared, the watchdog reset
generation time may become longer than the time set.
[Reference]
At activation, the watchdog timer is initialized by a power-on or watchdog reset, and is placed
in stopped status. The watchdog timer is cleared by an external pin reset, software reset,
writing to the WTE bit (watchdog timer control register), sleep mode or transition to stop
mode. However, It is not stopped.
248
MB90820 series
10.2 Configuration of the Watchdog Timer
The watchdog timer consists of the following five blocks:
• Count clock selector
• Watchdog counter (2-bit counter)
• Watchdog reset generator
• Counter clear control circuit
• Watchdog timer control register (WDTC)
■ Block diagram of the watchdog timer
Figure 10.2-1 shows the block diagram of the watchdog timer.
Watchdog timer control register (WDTC)
Watchdog timer
Activation
with CLR
Start of sleep mode
Start of hold status mode
Start of stop mode
Counter
clear control
circuit
Count
clock
selector
2-bit
counter
OverWatchdog
flow
reset generator
To the internal
reset generator
Clear
(Timebase timer counter)
One-half of HCLK
HCLK: Oscillation clock
Figure 10.2-1 Block diagram of the watchdog timer
● Count clock selector
This circuit is used to select the count clock of the watchdog timer from four types of timebase
timer outputs. This determines the watchdog reset generation time.
● Watchdog counter (2-bit counter)
This 2-bit up counter uses the timebase timer output as the count clock.
● Watchdog reset generator
Used to generate the reset signal by an overflow of the watchdog counter.
● Counter clear circuit
Used to clear the watchdog counter and to control the operation or stopping of the counter.
● Watchdog timer control register (WDTC)
Used to activate or clear the watchdog timer; holds the reset generation cause.
MB90820 series
249
10.3 Watchdog Timer Control Register (WDTC)
The watchdog timer control register (WDTC) activates and clears the watchdog timer,
and displays the reset cause.
■ Watchdog timer control register (WDTC)
Figure 10.3-1 shows the watchdog timer control register (WDTC). Table 10.3-1 describes the
function of each bit of the watchdog timer control register (WDTC).
bit15
Address
0000A8H
bit8 bit7
(TBTC)
bit6
PONR
-*
R
-
bit5
bit4
bit3
bit2
WRST ERST SRST WTE
R
R
R
WT1
WT0
W
bit1
bit0
WT1
WT0
W
W
Initial value
XXXXX111B
Interval selection bit (for 4 MHz HCLK)
Interval
Minimum
Maximum
Oscillation clock
cycle count
0
0
Approx. 3.58 ms
Approx. 4.61 ms
214 ±211 cycle
0
1
Approx. 14.33 ms
Approx. 18.3 ms
216 ±213 cycle
1
0
Approx. 57.23 ms
Approx. 73.73 ms
218 ±215 cycle
1
1
Approx. 458.75 ms Approx. 589.82 ms
221 ±218 cycle
HCLK: Oscillation clock
Watchdog control bit
WTE
0
- Activation of the watchdog timer
(At first write after reset)
- Clearing of the watchdog timer
(At second or subsequent write after reset)
1
No operation
Reset cause bit
Reset cause
PONR WRST ERST SRST
R: Read only
W: Write only
X: Undefined
*: Retains the previous status.
: Initial value
1
X
X
X
Power-on
*
1
*
*
Watchdog timer
*
*
1
*
External pin (RSTX input)
*
*
*
1
RST bit (software reset)
Figure 10.3-1 Watchdog timer control register (WDTC)
The interval becomes 3.5 to 4.5 times longer than the count clock (timebase timer output
value) cycle. For details, see Section 10.4, "Operation of the Watchdog Timer".
250
MB90820 series
Table 10.3-1 Function description of each bit of the watchdog timer control register
(WDTC)
Bit name
Function
• Read-only bits for indicating the reset cause. If more than one
bit7
bit5
bit4
bit3
PONR, WRST,
ERST, SRST:
Reset cause bits
bit6
unused
bit2
WTE:
Watchdog timer
control bit
bit1
bit0
MB90820 series
WT1, WT0:
Interval selection bit
•
•
reset cause occurs, the bit for each reset cause occurring is set to
1.
These bits are all cleared to 0 after the watchdog timer control
register (WDTC) is read.
At power-on, the contents of the bits other than the PONR bit are
not guaranteed. Therefore, when the PONR bit is 1, ignore the
contents of the bits other than the PONR bit.
• When read, the value is undefined. Writing has no effect on
operation.
• When 0 is written to this bit, the watchdog timer is activated (first
•
write after reset) or the 2-bit counter is cleared (second or
subsequent write after reset).
Writing 1 does not affect operation.
• Used to select the watchdog timer interval.
• Only data at watchdog timer activation is valid.
Data written after watchdog timer activation is ignored.
• These bits are write-only.
251
10.4 Operation of the Watchdog Timer
The watchdog timer generates a watchdog reset by an overflow of the watchdog
counter.
■ Watchdog timer operation
Operation of the watchdog timer requires the setting in Figure 10.4-1.
bit8
bit15
WDTC
TBTC
bit7
PONR
bit6
-
bit5
bit4
bit3
bit2
WRST ERST SRST WTE
bit1
bit0
WT1 WT0
0
: Used
0 : Set 0
1 : Set 1
Figure 10.4-1 Setting of the watchdog timer
● Activating the watchdog timer
•
The watchdog timer is activated when the first 0 after reset is written to the WTE bit of the
watchdog timer control register (WDTC). Specify the interval by specifying the WT1 and WT0
bits of the watchdog timer control register at the same time.
•
When watchdog timer activation starts, it can be stopped only by a power-on or its own reset.
● Clearing the watchdog timer
•
When a second or subsequent 0 is written to the WTE bit, the 2-bit counter of the watchdog
timer is cleared. If the counter is not cleared within the time interval, it overflows and a
watchdog reset occurs.
•
The watchdog counter is cleared by reset generation, sleep mode or stop mode, transition to
clock mode.
● Intervals for the watchdog timer
Figure 10.4-2 shows the relationship between the clear timing of the watchdog timer and
intervals. The interval changes according to the clear timing of the watchdog timer and requires
3.5 to 4.5 times longer than the count clock cycle.
● Checking a reset cause
A reset cause can be determined by checking the PONR, WRST, ERST and SRST bits of the
watchdog timer control register (WDTC) after a reset.
252
MB90820 series
[WDG timer block diagram]
2-bit counter
Clock
selector
Divide-bytwo circuit
Divide-bytwo circuit
Reset
circuit
Reset signal
Count enabling and clearing
WTE bit
Count enable
output circuit
[Minimum interval] When the WTE bit is cleared immediately before the count clock rises:
Counter clearing
Count start
Count clock a
Divide-by-two
value b
Divide-by-two
value c
Count enabling
Reset signal d
7 x (count clock cycle/2)
WTE bit clearing
Watchdog reset generation
[Maximum interval] When the WTE bit is cleared immediately after the count clock rises:
Counter clearing
Count start
Count clock a
Divide-by-two
value b
Divide-by-two
value c
Count enabling
Reset signal d
9 x (count clock cycle/2)
WTE bit clearing
Watchdog reset generation
Figure 10.4-2 Clear timing and watchdog timer intervals
MB90820 series
253
10.5 Usage Notes on the Watchdog Timer
Notes on using the watchdog timer are given below.
■ Usage notes on the watchdog timer
● Stopping the watchdog timer
Once the watchdog timer is activated, it cannot stop until a power-on or watchdog reset occurs.
The watchdog timer counter is cleared by an external reset or software reset; however, the
watchdog timer does not stop.
● Intervals
Since a carry signal of the timebase timer is used as the count clock for the interval, the
watchdog timer interval may become longer than the setting time when the timebase timer is
cleared.
● Selecting the interval
The interval can be set when the watchdog timer is activated. Data written during operations
other than activation is ignored.
● Notes on program creation
When a program that repeatedly clears the watchdog timer in the main loop is created, the
processing time of the main loop including the interrupt processing must be equal to or less than
the minimum watchdog timer interval.
● Watchdog timer operation in timebase timer mode
The timebase timer operates while the timebase timer mode is set. The watchdog timer,
however, is temporarily stopped.
254
MB90820 series
10.6 Sample Program for the Watchdog Timer
This section contains a sample program for the watchdog timer.
■ Sample program for the watchdog timer
● Processing
•
The watchdog timer is cleared every time in the main program loop.
•
The main loop must make one iteration within the minimum watchdog timer interval.
● Coding example
WDTC
EQU
0000A8H
; Watchdog timer control register
WTE
EQU
WDTC:2
; Watchdog control bit
;-------Main program-----------------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
; Assumes that stack pointer (SP) has already been
initialized
WDG_START:
MOV
WDTC,#00000011B ; Activates watchdog timer
; Selects the interval 221 ± 218 cycle
;--------Main loop---------------------------------------------------------------------------------------------------------MAIN:
CLRB I:WTE
; Clears watchdog timer
;
:
Clears this bit regularly
;
User processing
;
:
JMP
MAIN
; Loops in less time than the watchdog timer interval
CODE
ENDS
;--------Vector setting----------------------------------------------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG
0FFDCH
; Sets reset vector
DSL
START
DB
00H
; Sets single-chip mode
VECT
ENDS
END
START
MB90820 series
255
256
MB90820 series
CHAPTER 11 16-BIT RELOAD TIMER
This chapter describes the functions and operations of the 16-bit reload timer.
11.1 Overview of 16-Bit Reload Timer
11.2 Configuration of 16-Bit Reload Timer
11.3 Pins of 16-Bit Reload Timer
11.4 Registers of 16-Bit Reload Timer
11.5 Interrupts of 16-Bit Reload Timer
11.6 Operation of 16-Bit Reload Timer
11.7 Notes on Using the 16-Bit Reload Timer
11.8 Sample Programs for the 16-Bit Reload Timer
257
11.1 Overview of 16-Bit Reload Timer
The 16-bit reload timer has two modes: Internal clock mode (with countdown
performed in synchronization with three types of internal clock), and event count mode
(with countdown performed by detecting any pulse edge input to the external pin).
Either mode may be selected. The timer defines an underflow when the counter value
is in the range from 0000H to FFFFH. In other words, an underflow occurs at a count of
[reload register’s setting value +1].
The counter can be used to select either reload mode, in which an underflow causes
the count set value to be reloaded for repeated counting, or one-shot mode, in which
counting is stopped when an underflow occurs. Counter underflow may generate an
interrupt and supports the extended intelligent I/O service (EI2OS).
■ Operation Mode of 16-bit Reload Timer
Table 11.1-1 "Operation Modes of 16-bit Reload Timer" lists the operation modes of the 16-bit
reload timer.
Table 11.1-1 Operation Modes of 16-bit Reload Timer
Clock mode
Counting
Reload mode
Internal clock mode
One-Shot mode
Event count mode
(External clock mode)
16-bit reload timer operation
Software trigger operation
External trigger operation
External gate input operation
Reload mode
Software trigger operation
One-Shot mode
■ Internal Clock Mode
One type of count clock is selected among three types of internal clocks to operate as follows:
● Software trigger operation
Sets the Timer control status register (TMCSR0/1): TRG bit to "1" to start count operation.
Trigger input by using the TRG bit is also enabled for external trigger input and external gate
input.
● External trigger operation
Starts counting when the edge selected (leading, trailing, or both) is input to the TIN0/1 pins.
● External gate input operation
Continues counting when the signal level selected ("L" or "H") is input to the TIN0/1.
258
MB90820 series
■ Event Count Mode (External Clock Mode)
Event count mode provides a function for starting countdown when a valid edge selected
(leading, trailing, or both) is input to the TIN0/1 pins. It is also used as an interval timer when
using an external clock with a constant interval.
■ Counter Operation
● Reload mode
If the countdown causes an underflow, and a transfer of the type 0000H --> FFFFH occurs, the
setting value for counting is reloaded so that counting can continue. An underflow can trigger an
interrupt request, which may be used for providing an interval timer. A toggled waveform, which
reverses itself at every underflow, is output from the TO0/1 pins. If the countdown causes an
underflow, and a transfer of the type 0000H --> FFFFH occurs, the setting value for counting is
reloaded so that counting can continue. An underflow can trigger an interrupt request, which
may be used for providing an interval timer. A toggled waveform, which reverses itself at every
underflow, is output from the TO0/1 pins. “Interval Time of 16-bit Reload Timer” lists the interval
time for the 16-bit reload timer. “Interval Time of 16-bit Reload Timer” lists the interval time for
the 16-bit reload timer.
Table 11.1-2 Interval Time of 16-bit Reload Timer
Count clock
Count clock interval
Internal clock
External clock
Interval time
21/Φ (0.125 µs)
0.125 µs to 8.192 ms
23/Φ (0.5 µs)
0.5 µs to 32.768 ms
25/Φ (2.0 µs)
2.0 µs to 131.1 ms
23/Φ or more (0.5 µs)
0.5 µs or more
Φ: Machine clock. The parenthesized value indicates the clock interval applied when the machine clock
frequency is 16 MHz and the FSEL bit is "1".
Table 11.1-3
Count clock
Internal clock
Interval Time of 16-bit Reload Timer
Count clock interval
21/Φ (0.167 µs)
0.167 µs to 10.923 ms
23/Φ (0.667 µs)
0.667 µs to 43.690 ms
2 /Φ (2.667 µs)
2.667 µs to 174.760 ms
23/Φ or more (0.667 µs)
0.667 µs or more
5
External clock
Interval time
Φ: Machine clock. The parenthesized value indicates the clock interval applied when the machine clock
frequency is 24 MHz and the FSEL bit is "0".
● One-shot mode
If countdown leads to an underflow (0000H --> FFFFH), count operation will stop. Underflow may
also trigger an interrupt. During counter operation, the square wave that indicates counting is
output from the TO0/1 pins.
MB90820 series
259
References:
•
The 16-bit reload timer is used to generate the UART baud rate.
• The 16-bit reload timer is used to trigger A/D converter operation.
260
MB90820 series
11.2 Configuration of 16-Bit Reload Timer
The 16-bit reload timer consists of the following seven blocks:
• Count clock generation circuit
• Reload control circuit
• Output control circuit
• Operation control circuit
• 16-bit timer registers (TMRL0/1, TMR0/1H)
• 16-bit reload registers (TMRD0/1L, TMRD0/1H)
• Timer control status registers (TMCSR0/1L, TMCSR0/1H)
■ Block Diagram of 16-bit Reload Timer
Figure 11.2-1 "Block Diagram of 16-bit Reload Timer" shows a block diagram of the 16-bit reload timer.
Figure 11.2-1
Block Diagram of 16-bit Reload Timer
Internal data bus
TMRD0*1
<TMRD1>
16-bit reload register
Reload signal
TMR0*1
<TMR1>
16-bit timer register (down-counter)
CLK
Clock
selector
1
Reload
control
circuit
UF
1-bit
down-counter
0
FSEL: Initial value "1"
Machine
clock
Gate
input
Prescaler
3
Clock
judgement
circuit
Clear
Input
control
circuit
P41/TIN0*1
<P20/TIN1>
Output control circuit
Clock
selector
Output signal
generation
Rever- circuit
sed
External clock
Count clock generation circuit
3
Function select
_
UART0*1
<UART1, A/D converter>
CLK
Internal
clock
Pin
Wait signal
_
_
2
Timer control status register (TMCSR0) *1
<TMCSR1>
MB90820 series
P42/TO0*1
<P21/TO1>
EN
Select
signal
FSEL CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE
*1: Used for channel 0/1. <> indicates channel 1.
*2: Interrupt number
Pin
Operation
control
circuit
UF CNTE TRG
Interrupt request signal
#30*2
<#18>
261
● Count clock generation circuit
The count clock generation circuit generates the count clock for the 16-bit reload timer from the
machine clock or external input clock.
● Reload control circuit
Controls reload operation when the timer starts and when underflow occurs.
● Output control circuit
Controls the reversal of TO pin output due to 16-bit timer register underflow and the enable or
disable states of TO pin output.
● Operation control circuit
Controls starting and stopping of the16-bit reload timer.
16-bit timer registers (TMRL0/1, TMRH0/1)
These registers are used to read the current counter value for the 16-bit down counter.
● 16-bit reload registers (TMRDL0/1, TMRDH0/1)
These registers are used to set the interval time of the 16-bit reload timer, which is loaded into
the 16-bit timer registers for countdown.
● Timer control status registers (TMCSRL0/1, TMCSRH0/1)
These registers are used to select the count clock and operation mode of the 16-bit reload timer,
set operating conditions, activating a trigger by software, enabling/disabling count operation,
select reload or one-shot mode, select the pin output level, enable or disable timer output, couto
clock division control , interrupt control, and check the state of operation.
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11.3 Pins of 16-Bit Reload Timer
This section describes the pins of the 16-bit reload timer.
■ Pins of 16-bit Reload Timer
The pins of the 16-bit reload timer can also be used for general-purpose ports. Table 11.3-1
"Pins of the 16-bit Reload Timer" lists the pin functions, type of I/O, and settings for using the 16bit reload timer.
Table 11.3-1
Pin name
Pin function
P41/TIN0
I/O and timer
input of port 4
P42/TO0
I/O and timer output of port 4
Pins of the 16-bit Reload Timer
Type of I/O
Pull-up
selection
Standby
control
Set to input port.
(DDR4:bit1=0)
Not used
P20/TIN1
I/O and timer
input of port 2
P21/TO1
I/O and timer output of port 2
Setting to use pin
CMOS output
and CMOS
hysteresis
input
Setting to timer output enabled
(TMCSRL0:OUTE=1)
Sound generator output disabled
Provided
Set to input port
(DDR2:bit0=0)
PPG1 output disabled
Selectable
Setting to timer output enabled
(TMCSRL1:OUTE=1)
PPG4 output disabled
Reference:
For pin block diagrams, refer to CHAPTER 8 "I/O PORTS".
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11.4 Registers of 16-Bit Reload Timer
This section lists the registers of the 16-bit reload timer.
■ List of Registers of 16-bit Reload Timer
Figure 11.4-1 "Registers of 16-bit Reload Timer" lists the registers of the 16-bit reload timer.
Figure 11.4-1 Registers of 16-bit Reload Timer
Address
16-Bit Reload Timer 0
16-Bit Reload Timer 1
bit15
bit8
bit7
000082 83H
TMCSR0 (Timer control status register)
000084 85H
TMR0 TMRD0
000086 87H
TMCSR1 (Timer control status register)
000088 89H
TMR1 TMRD1
bit0
(16-bit timer register/16-bit reload register)
(16-bit timer register/16-bit reload register)
1
1
*1: Functions as a 16-bit timer register (TMR) for reading and as a 16-bit reload register (TMRLR) for writing.
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265
11.4.1
Upper Bits of Timer Control Status Registers
(TMCSRH0/1)
Upper bits 12-8 and lower bit 7 in the timer control status registers (TMCSR0/1) are
used to select the 16-bit reload timer operation mode and set the operating conditions.
Use of the last lower bit 7 (MOD0 bit) is also described here.
■ Upper Bits and Bit 7 of Timer Control Status Registers (TMCSRH0/1)
Figure 11.4.1-1
Upper Bits and Bit 7 of Timer Control Status Registers (TMCSRH0/1)
Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6
bit0
Initial value
TMCSRH0
(TMCSRL)
XXX100000B
FSEL CSL1 CSL0 MOD2 MOD1 MOD0
000083H
TMCSRH1 R/W R/W R/W R/W R/W R/W
000087H
MOD2 MOD1 MOD0
0
0
0
0
0
1
0
1
0
0
1
1
1
X
0
1
X
1
Input pin function
Trigger prohibited
0
0
X
0
1
X
1
0
X
1
1
CSL1 CSL0
0
0
0
1
1
0
1
1
Valid edge, level
Leading edge
Trailing edge
Both edges
L level
H level
Trigger input
Gate input
MOD2 MOD1 MOD0
X
Operation mode selection bit
(in internal clock mode)
Operation mode selection bit
(in event count mode)
Input pin function
Valid edge
Leading edge
Trailing edge
Both edges
Trigger input
Count clock selection bit
Function
Count clock
21/ (0.125 s)
Internal clock mode
23/
(0.5 s)
25/ (2.0 s)
Event count mode
External event input
Count clock division control bit
Division by two
R/W : Reading and writing permitted
: Undefined
Division by one
x : Unspecified value
: Initial value
: Machine clock. The parenthesized value indicates the count clock applied when the machine
clock frequency is 16 MHz and the count clock division ratio is 1 (FSEL bit is "1").
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Table 11.4.1-1
Function of the Upper Bits and Bit 7 of Timer Control Status Registers:
(TMCSRH0, TMCSRH1)
Bit name
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
Function
Bit undefined
•
•
FSEL:
Count clock division
control
Specifies the count clock division ratio.
• If the FSEL bit is set to "0", the count clock specified by the count clock
selection bits (CSL1 and CSL0) is divided by two.
CSL1, CSL0:
Count clock selection
bit
MOD2, MOD1,
MOD0:
Operation mode
selection bit
•
•
•
Value at reading is not specified.
If read, the bit value is always "1".
Selects the count clock.
Internal clock mode to count the internal clock is selected if the CSL1 and
CSL0 bits are other than "11B".
Event count mode to count external clock edges is selected if the CSL1 and
CSL0 bits are "11B".
Internal clock mode
• The MOD2 bit is used to select the function of the input pin.
• When the MOD2 bit is set to "0", the input pin is used as a trigger input pin.
When a valid edge is input, reload register data is loaded into the counter to
continue with count operation. Valid edge types are selected by using the
MOD1/0 bits.
• With the MOD2 bit set to "1", the input pin is used for gate input for counting
only when a valid level is being input. The MOD0 bit enables selection of a
valid level.
• Because the value of the MOD1 bit has no effect on operation, either value
(0 or 1) can be set.
Event Count mode
• Because the value of the MOD2 bit has no effect on operation, either value
(0 or 1) can be set.
• The input pin is used as a trigger input pin for event input. A valid edge is
selected by using the MOD1/0 bits.
Note:
The Operation mode selection must be counter operation stop mode
(TMCSRL0/1: CNTE=0).
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11.4.2
Lower Bits of Timer Control Status Registers
(TMCSRL0/1)
Bit 7 of the timer control status registers (TMCSR0/1), which is part of the lower bits, is
used to set the operating conditions of the 16-bit reload timer, enable or disable
operation, control interrupts, and check the state of operation.
■ Lower Bits of Timer Control Status Registers (TMCSRL0/1)
Figure 11.4.2-1 Lower Bits of Timer Control Status Registers (TMCSRL0/1)
*1
Address
bit15
TMCSRL0
000082H
bit8 bit7
(TMCSRH)
TMCSRL1
bit6
bit5
bit4
bit3
MOD0 OUTE OUTL RELD INTE
R/W
R/W
R/W
R/W
R/W
bit2
bit1
bit0
UF CNTE TRG
R/W
R/W
Initial value
00000000B
R/W
000086H
TRG
0
1
CNTE
0
1
UF
Software trigger bit
Does not change and has no effect
Starts counting after reload
Count enable bit
Count stop
Count enabled (waiting for start trigger)
Underflow flag bit for interrupt request
Reading
Writing
0
No counter underflow
Bit cleared
1
Counter underflow generated
Does not change and has
no effect
INTE
0
1
RELD
0
1
Enable bit for interrupt requests
Interrupt request output disabled
Interrupt request output enabled
Reload selection bit
One-shot mode
Reload mode
Selection bit for pin output level
OUTL
0
1
OUTE
One-shot mode
(RELD=0)
Reload mode
(RELD=1)
Rectangle wave at H level
during counting
Rectangle wave at L level
during counting
Toggle output at L level when
counting starts
Toggle output at H level when
counting starts
Timer output enable bit
Register and pin for each channel
Pin function
TMCSRL0
R/W : Reading and writing permitted
: Initial value
TMCSRL1
0
General-purpose
port
P42
P21
1
Timer output
TO0
TO1
*1 : For details about the M0D0 (bit 7), see Section 12.4.1, "Upper Bits of Timer Control Status Registers (TMCSRL0,
TMCSRL1)."
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Table 11.4.2-1
Function of the Lower Bits of the Timer Control Status Registers (TMCSRL0/1)
Bit name
bit6
OUTE:
Timer output enable bit
Function
•
•
•
Enables or disables output via the timer output pin.
When this bit is "0", the pin is used as a general-purpose port; when this
bit is "1", the pin is used as a timer output pin.
The waveform output from the timer output pin becomes toggle output in
reload mode. In one-shot mode, a rectangular wave is output, which indicates that counting is in progress.
bit5
OUTL:
Selection bit for pin output level
•
•
Bit used to select the output level of the timer output pin.
Toggle this bit to "0" or "1" to reverse the pin level.
bit4
RELD:
Reload selection bit
•
•
Enables reload operation.
Reload mode is entered when this bit is set to "1". If underflow occurs,
reload register data is loaded into the counter to continue count operation.
One-Shot mode is entered when this bit is se to "0". If underflow occurs,
count operation will stop.
•
bit3
INTE:
Enable bit for interrupt
requests
•
•
Enables or disables interrupt requests to the CPU.
When this bit and the flag bit for interrupt request (UF) are set to "1", an
interrupt request is output.
bit2
UF:
Underflow flag bit for
interrupt request
•
•
•
Set to "1" if counter underflow occurs.
Cleared by writing "0". Writing "1" has no effect.
Also cleared at EI2OS startup.
bit1
CNTE:
Count enable bit
•
•
Enables or disables count operation.
When this bit is set to "1", start trigger wait state is entered. As soon as the
start trigger occurs, the actual counting will begin.
bit0
TRG:
Software trigger bit
•
•
Used to start the interval timer function or counter function by software.
Set this bit to "1" to activate the software trigger and load the reload register value into the counter to start counting. Writing "0" has no effect.
When CNTE=1, trigger input is always enabled by this but regardless of
the mode.
•
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11.4.3
16-Bit Timer Registers (TMR0/1)
The 16-bit timer registers (TMR0/1) are used to continuously read the current count
value of the 16-bit down counter.
■ 16-Bit Timer Registers (TMR0/1)
Figure 11.4.3-1 "Bit Configuration of 16-bit Timer Registers (TMR0/1)" shows the bit
configuration of the 16-bit timer registers (TMR0/1).
Figure 11.4.3-1 Bit Configuration of 16-bit Timer Registers (TMR0/1)
Address
TMR0:
TMR1:
000053 H
000057 H
D15 D14
R
Address
TMR0:
TMR1:
000052 H
000056 H
bit8
Initial value
D9
D8
XXXXXXXX B
R
R
bit15 bit14 bit13 bit12 bit11 bit10 bit9
D13
R
D12 D11 D10
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
R
R
R
R
R
R
R
R
R: Read only
X: Not specified
These registers are used to read the current counter value of the 16-bit down counter. When
counter operation is allowed (TMCSR0/1: CNTE=1) to start counting, the value written to the 16bit reload register is loaded into these registers to start the countdown. In counter stop mode
(CNTE=0 for TMCSR0/1), the register value is retained.
Note:
These registers may be read in counter operation mode by using a word transfer instruction.
The 16-Bit Timer Registers (TMR0/1) are read-only registers, and assigned the same address as
the 16-bit write-only reload registers (TMRDL0/1,TMRDH0/1). Therefore, writing does not affect
TMR values, though writing is performed to TMRDL0/1 and TMRDH0/1.
Be sure to perform word-access to the TMR0/1 registers.
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11.4.4 16-Bit Reload Registers (TMRDL0/1, TMRDH0/1)
The 16-bit reload registers (TMRDL0/1, TMRDH0/1) are used to set the 16-bit down
counter to a reload value. The value written to these registers is loaded into the down
counter for countdown.
■ 16-Bit Reload Registers (TMRDL0/1, TMRDH0/1)
Figure 11.4.4-1 "Bit Configuration of 16-bit Reload Registers (TMRDL0/1, TMRDH0/1)" shows
the bit configuration of the 16-bit reload registers (TMRDL0/1,TMRDH0/1).
Figure 11.4.4-1 Bit Configuration of 16-bit Reload Registers (TMRDL0/1, TMRDH0/1)
Address
TMRDH0: 000085H
TMRDH1: 000089H
bit15 bit14 bit13 bit12 bit11 bit10 bit9
D15 D14
W
Address
TMRDL0:
TMRDL1:
000084H
000088H
D13
W
D12 D11 D10
W
W
W
W
bit8
D9
D8
W
W
Initial value
XXXXXXXXB
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXXB
W
W
W
W
W
W
W
W
W: Write-only
X: Not specified
Regardless of the 16-bit reload timer operation mode, if counter operation is prohibited
(TMCSR0/1: CNTE=0), these registers are set to the initial value of the counter. When counter
operation is allowed (TMCSR0/1: CNTE=1) to start the counter, the countdown starts from the
value written to these registers.
The value set in the 16-bit reload registers (TMRDL0/1, TMRDH0/1) is reloaded into the counter
in reload mode if underflow occurs, then the countdown continues. In one-shot mode, the
counter stops at FFFFH if underflow occurs.
Writing to the registers is always performed in counter stop mode (TMCSR0/1: CNTE=0). Write
operations always use a word transfer instruction.
The 16-bit reload registers (TMRDL0/1, TMRDH0/1) are functionally write-only registers that are
allocated under the same address as the read-only 16-bit timer registers (TMR0/1). Therefore,
the value read is the value of TMR0/1. Consequently, an instruction such as INC/DEC for readmodify-write (RMW) operation cannot be used.
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11.5 Interrupts of 16-Bit Reload Timer
The16-bit reload timer may generate an interrupt due to counter underflow. The timer
also supports the extended intelligent I/O service (EI2OS).
■ Interrupts Generated by 16-bit Reload Timer
Table 11.5-1 "Interrupt Control Bits and Interrupt Sources of 16-bit Reload Timer" lists the
interrupt control bits and interrupt sources of the 16-bit reload timer.
Table 11.5-1 Interrupt Control Bits and Interrupt Sources of 16-bit Reload Timer
Lower bits of timer control status register (TMCSRL0/1)
Interrupt source
Interrupt flag bit
Interrupt enable bit
UF
INTE
Underflow of 16-bit down counter
(TMR0/1)
(0000H --> FFFFH)
Clearance of interrupt flag
•
•
•
Writing "0" to the UF bit
Resetting
Starting EI2OS
If the interrupt source listed in Table 11.5-1 "Interrupt Control Bits and Interrupt Sources of 16-bit
Reload Timer" is generated, the interrupt flag bit of the 16-bit reload timer is set to "1". If the
interrupt enable bit of the 16-bit reload timer is "1" when the interrupt flag bit is set to "1", the 16bit reload timer outputs an interrupt request to the interrupt controller.
■ Interrupts of 16-bit Reload Timer and EI2OS
Table 11.5-2 "Interrupts of 16-bit Reload Timer and EI2OS" lists the interrupts of the 16-bit reload
timer and their relationship to EI2OS.
Table 11.5-2
Channel
Interrupt
number
Interrupts of 16-bit Reload Timer and EI2OS
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower
bits
Upper
bits
Bank
16-Bit Reload
Timer 0
#30(1EH)
ICR09
0000B9H
FFFF94H
FFFF95H
FFFF96H
*
16-Bit Reload
Timer 1
#18(12H)
ICR03
0000B3H
FFFFB4H
FFFFB5H
FFFFB6H
*
*: Available when not using interrupt sources sharing ICR03, ICR09, or the interrupt vector.
■ EI2OS Function of 16-bit Reload Timer
The 16-bit reload timer has a circuit supporting EI2OS. Therefore, a counter underflow will start EI2OS. Note
that EI2OS is only available when no other peripheral function that shares the interrupt control register (ICR)
uses an interrupt. To use EI2OS by 16-bit reload timer 0, interrupts of waveform generator must be
prohibited. To use EI2OS by 16-bit reload timer 1, interrupts of output compare 2 must be prohibited.
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11.6 Operation of 16-Bit Reload Timer
This section describes how to set the 16-Bit Reload Timer and counter operation state.
■ 16-Bit Reload Timer Settings
● Setting internal clock mode
To operate the interval timer, the settings listed in Figure 11.6-1 "Internal Clock Mode Settings"
are required.
Figure 11.6-1
Internal Clock Mode Settings
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
TMCSR
FSEL CSL1 CSL0 MOD2 MOD1 MOD0 OUTEOUTL RELD INTE UF CNTE TRG
1
Other than "11"
TMRD
Setting of the initial counter value (reload value)
: Bit used
1 : Set to 1.
● Setting event count mode
To operate the event counter, the settings listed in Figure 11.6-2 "Event Count Mode Settings"
are required.
Figure 11.6-2
Event Count Mode Settings
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
TMCSR
bit4 bit3 bit2
bit1 bit0
FSEL CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
1
TMRD
bit7 bit6 bit5
1
1
Setting of the initial counter value (reload value)
DDR5
DDR0
: Bit used
1 : Set to 1.
: Set the bit corresponding to the pin used to "0".
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■ States of Counter Operation
The counter’s operation state is determined by the CNTE bit of the timer control status registers
(TMCSRL0/1,TMCSRH0/1) and the internal WAIT signal. States that can be set include the stop
state (STOP state), start trigger wait state (WAIT state), and operation state (RUN state). Figure
11.6-3 "State Transition Diagram of Counter States" shows a state transition diagram for the
counter.
Figure 11.6-3
State Transition Diagram of Counter States
STOP state CNTE=0, WAIT=1
TIN pin: Input disabled
TO pin: General-purpose port
Counter: Retains the value at stop.
Not specified immediately
after reset
Reset
CNTE=0
CNTE=0
CNTE=1
TRG=0
WAIT state CNTE=1, WAIT=1
TIN pin: Valid for trigger input only
TO pin: Initial value output
Counter: Retains the value at stop.
Not specified until loading
after reset
TRG=1
(Software trigger)
External trigger from TIN
CNTE=1
TRG=1
UF=1 &
RELD=0
(One-shot mode)
RUN state CNTE=1, WAIT=0
TIN pin: Functions as TIN pin.
TO pin: Functions as TO pin.
Counter: operating
UF=1 &
RELD=1
TRG=1
(Reload mode)
(Software trigger)
LOAD
CNTE=1, WAIT=0
Loads the reload register value into
Load end
the counter.
: State transition by hardware
: State transition by register access
WAIT : WAIT signal (internal signal)
TRG : Software trigger bit of timer control status register (TMCSR)
CNTE : Count enable bit of timer control status register (TMCSR)
: Underflow flag bit for interrupt request of timer control status register (TMCSR)
UF
RELD : Reload selection bit of timer control status register (TMCSR)
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11.6.1 Internal Clock Mode (Reload Mode)
The counter operates in sync with the internal count clock to count down the 16-bit
counter and generate an interrupt request in case of counter underflow. The counter
also outputs a toggle waveform from the timer output pin.
■ Operation in Internal Clock Mode (Reload Mode)
When count operation is allowed (TMCSR0/1: CNTE=1) and the timer is started by the software
trigger bit (TMCSR: TRG) or external trigger, counter operation will start by loading the data of
the 16-bit reload registers (TMRDL0/1, TMRDH0/1) into the counter. When both the count
enable bit and software trigger bit are set to "1", counting will begin as soon as the counter is
enabled.
If the counter value causes an underflow (0000H --> FFFFH), the value of the16-bit reload
registers (TMRDL0/1, TMRDH0/1) is loaded into the counter to continue counting. Note that if
the underflow flag bit for interrupt request (UF) and enable bit for interrupt request (INTE) are set
to "1", an interrupt request is generated.
The TO pin outputs a toggle waveform that is reversed at every underflow.
● Software trigger operation
When the TRG bit of the timer control status registers (TMCSRL0/1, TMCSRH0/1) is set to "1",
the counter starts operation. Figure 11.6.1-1 "Count Operation (Software Trigger Operation) in
Reload Mode" shows the software trigger operation in reload mode.
Figure 11.6.1-1
Count Operation (Software Trigger Operation) in Reload Mode
Count clock
Counter
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
Data load signal
UF bit
CNTE bit
TRG bit
TO pin
T : Machine cycle
*1 : It takes 1T from trigger input to loading reload data.
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● External trigger operation
When a valid edge (leading, trailing, or both can be selected) is input to the TIN pin, the counter
will start operation. Figure 11.6.1-2 "Count Operation in Reload Mode (External Trigger
Operation)" shows the external trigger operation in reload mode.
Figure 11.6.1-2
Count Operation in Reload Mode (External Trigger Operation)
Count clock
Counter
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
Data load signal
UF bit
CNTE bit
TIN pin
2T to 2.5T
TO pin
T: Machine cycle
*1: It takes 2T to 2.5T from trigger input to loading reload data.
Note:
The pulse width of trigger pulses input to the TIN pin must be 2/F or more.
● Gate input operation
As soon as a valid level ("H" level or "L" level can be selected) is input to the TIN pin, the counter
will start operation. Figure 11.6.1-3 "Count Operation in Reload Mode (Software Trigger, Gate
Input Operation)" shows the gate input operation in reload mode.
Figure 11.6.1-3
Count Operation in Reload Mode (Software Trigger, Gate Input Operation)
Count clock
Counter
Reload data
-1
-1
-1
0000H
Reload
data
-1
-1
Data load signal
UF bit
CNTE bit
TRG bit
TIN pin
TO pin
T : Machine cycle
*1: It takes 1T from trigger input to loading reload data.
Note:
The pulse width of pulses input to TIN pin must be 2/Φ or more.
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11.6.2 Internal Clock Mode (One-Shot Mode)
The counter is in synchronization with the internal count clock in this mode to count
down the 16-bit counter and generate an interrupt request to the CPU at counter
underflow. It also outputs a square wave from the TO0/1 pin to indicate that counting is
in progress.
■ Operation of Internal Clock Mode (One-shot Mode)
When count operation is allowed (TMCSR0/1: CNTE=1) and the timer is started by the software
trigger bit (TMCSR0/1: TRG) or external trigger, count operation will start. When both the count
enable bit and software trigger bit are set to "1", counting will start at the same time counting
becomes enabled. If the counter value causes an underflow (0000H --> FFFFH), the counter
stops at FFFFH, and the underflow flag bit for interrupt requests (UF) is set to "1". If the enable
bit for interrupt request (INTE) is set to "1", an interrupt request is generated.
The TO pin outputs a square wave to indicate that counting is in progress.
● Software trigger operation
The counter will start as soon as the TRG bit of the timer control status registers (TMCSRL0/
1,TMCSRH0/1) is set to "1". Figure 11.6.2-1 "Count Operation in One-shot Mode (Software
Trigger Operation)" shows the software trigger operation in one-shot mode.
Figure 11.6.2-1
Count Operation in One-shot Mode (Software Trigger Operation)
Count clock
Counter
Reload
data
-1
0000H FFFFH
-1
Reload
data
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
TO pin
Waiting for start trigger input
T : Machine cycle
*1: It takes 1T from trigger input to loading reload data.
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MB90820 series
● External trigger operation
When a valid edge (leading, trailing, or both can be selected) is input to the TIN0/1 pins, the
counter will start operation. Figure 11.6.2-2 Count Operation in One-shot Mode (External
Trigger Operation)"Count Operation in One-shot Mode (External Trigger Operation)" shows the
external trigger operation in one-shot mode.
Figure 11.6.2-2
Count Operation in One-shot Mode (External Trigger Operation)
Count clock
Counter
Reload
data
-1
0000H FFFFH
Reload
data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TIN bit
2T to 2.5T
TO pin
Waiting for start trigger input
T: Machine cycle
*1: It takes 2T to 2.5T from trigger input to loading reload data.
Note:
The pulse width of trigger pulses input to the TIN pin must be 2/Φ or more.
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279
● Gate input operation
When a valid level ("H" and "L" level can be selected) is input to the TIN pin, the counter starts
operation. Figure 11.6.2-3 "Count Operation in One-shot Mode (Software Trigger, Gate Input
Operation)" shows the gate input operation in one-shot mode.
Figure 11.6.2-3
Count Operation in One-shot Mode (Software Trigger, Gate Input Operation)
Count clock
Counter
Reload
data
-1
0000H FFFFH
Reload
data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
TO pin
Waiting for start trigger input
T : Machine cycle
*1: It takes 1T from trigger input to loading reload data.
Note:
The pulse width for gate input to the TIN pin must be 2/Φ or more.
280
MB90820 series
Memo
MB90820 series
281
11.6.3
Event Count Mode
In this mode, the counter counts input edges from the TIN pin to count down the 16-bit
counter and generate an interrupt request to the CPU when a counter underflow
occurs. The TO0/1 pin can output either a toggle waveform or a square wave.
■ Event Count Mode
When count operation is allowed (TMCSR0/1: CNTE=1) to start the counter (TMCSR0/1:
TRG=1), data from the 16-bit reload registers (TMRDL0/1, TMRDH0/1) is loaded into the counter
for a countdown whenever a valid edge (leading or trailing can be selected) of pulses (external
count clock) input to the TIN0/1 pin is detected. When both the count enable bit and software
trigger bit are set to "1", counting will start as soon as counting becomes enabled.
Operation in reload mode
If the counter value has an underflow (0000H --> FFFFH), data from the 16-bit reload registers
(TMRDL0/1, TMRDH0/1) is loaded into the counter to continue counting. In this case, an
interrupt request is issued when the underflow flag bit for interrupt requests (UF) and enable bit
for interrupt requests (TMCSR0/1: INTE) are both set to "1". The TO0/1 pin outputs a toggle
waveform, which is reversed at every occurrence of underflow. Figure 11.6.3-1 "Count Operation
in Reload Mode (Event Count Mode)" shows the counting operation in reload mode.
Figure 11.6.3-1
Count Operation in Reload Mode (Event Count Mode)
TIN pin
Reload
data
Counter
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
Data load signal
UF bit
CNTE bit
TRG bit
*1
T
TO pin
T: Machine cycle
*1: It takes 1T from trigger input to loading reload data.
Note:
Both the "H" width and "L" width of clock input to TIN pin must be 4/Φ or more.
282
MB90820 series
● Operation in one-shot mode
If the counter value causes an underflow (0000H --> FFFFH), the counter stops at FFFFH. In this
case, the underflow request flag bit (UF) is set to "1". If the interrupt request output enable bit
(INTE) is also set to "1", an interrupt request is generated. The TO0/1 pin outputs a square wave
that indicates counting in progress. Figure 11.6.3-2 "Counter Operation in One-shot Mode (Event
Count Mode)" shows the counter operation in one-shot mode.
Figure 11.6.3-2
Counter Operation in One-shot Mode (Event Count Mode)
TIN pin
Reload
data
Counter
-1
0000H FFFFH
-1
Reload
data
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
{1
T
TO pin
Waiting for start trigger input
T : Machine cycle
*1: It takes 1T from trigger input to loading reload data.
Note:
Both the "H" width and "L" width for the input clock to TIN pin must be 4/F or more.
MB90820 series
283
11.7 Notes on Using the 16-Bit Reload Timer
This section provides notes on using the 16-bit reload timer.
■ Notes on Using the 16-bit Reload Timer
● Notes on setup by program
Writing to the 16-bit reload registers (TMRDL0/1, TMRDH0/1) must be performed in counter
operation stop (TMCSR0/1: CNTE=0) mode. Reading of the 16-bit timer registers (TMR0/1) may
be performed while the counter is in operation, but a word transfer instruction must be used in
this case.
The contents of the FSEL/CSL1/CSL0/MOD2/MOD1/MOD0 bits of the timer control status
registers (TMCSRL0/1, TMCSRH0/1) can only be changed in counter operation stop mode
(TMCSRL0/1: CNTE=0).
● Notes on interrupts
If the UF bit of the timer control status registers (TMCSRL0/1, TMCSRH0/1) is set to "1" in
interrupt enabled state (TMCSRL0/1:INTE=1), return from interrupt handling cannot be
performed. Ensure that the UF bit is always cleared.
Since the 16-bit reload timer, waveform generator and output compare 2 share the same
interrupt vector, interrupt sources must be checked in the interrupt-handling routine to enable
using interrupts.
If the 16-Bit Reload Timer uses EI2OS, “shared resource interrupts must be disabled”.
284
MB90820 series
11.8 Sample Programs for the 16-Bit Reload Timer
The sample programs listed below uses the 16-bit reload timer in internal clock mode
and event count mode.
■ Sample Program for Internal Clock Mode
Process specifications
Uses the 16-bit reload timer to generate a 25 ms interval timer interrupt.
Uses reload mode to generate interrupts repeatedly.
Uses no external trigger input, but uses a software trigger to start the timer.
Does not use EI2OS.
Uses a 16-MHz machine clock with a count clock of 2 µs.
MB90820 series
285
[Coding example]
ICR07 EQU
0000B7H
;Interrupt Control Register for reload time
TMCSR EQU
000050H
;Timer control status register
TMR
EQU
000052H
;16-bit timer register
TMRLR EQU
000052H
;16-bit reload register
UF
EQU
TMCSR:2
;Flag bit for interrupt requests
CNTE
EQU
TMCSR:1
;Counter operation enable bit
TRG
EQU
TMCSR:0
;Software trigger bit
;----------Main program--------------------------------------------------CODE
CSEG
START:
;
:
;Stack pointer (SP) already
;initialized
AND
CCR, #0BFH
;Interrupt disabled
MOV
I:ICR07, #00H
;Interrupt level 0 (highest)
CLRB
I:CNTE
;Counter temporary stopped
MOVW
I:TMRLR, #30D4H ;Setting the data for the 25-ms timer
MOVW
I:TMCSR, #181BH ;Interval timer operation, clock 2ms
;External trigger disabled, external
;output disabled
;Reload mode selection, enabling interrupts
;Interrupt flag cleared, counter started
;Count clock divided by one
MOV
ILM, #07H
;ILM in PS set to level 7
OR
CCR, #40H
;Interrupts enabled
;Interrupt flag clear, counter start
LOOP: MOV
A, #00H
;Infinite loop
MOV
A, #01H
;
BRA
LOOP
;
;----------Interrupt program---------------------------------------------WARI:
CLRB
I:UF
;Interrupt request flag cleared
;
:
;
User processing;
:
RETI
;Return from interrupt
CODE
ENDS
;----------Vector settings--------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FF94H
;Set the vector to interrupt #26 (1AH)
DSL
WARI
ORG
0FFDCH
;Reset the vector setting
DSL
START
DB
00H
;Set Single-Chip mode
VECT
ENDS
END
START
286
MB90820 series
■ Sample Program for Event Count Mode
Specification of processing
The 10,000th time the 16-bit reload timer/counter counts a leading edge in the pulses input to
the external event input pin, an interrupt is generated.
The device operates in one-shot mode.
In case of external trigger input, the leading edge is selected.
This program does not use EI2OS.
[Coding example]
ICR07
;Interrupt control register for 16-bit
;reload timer
TMCSR EQU
000050H
;Timer control status register
TMR
EQU
000052H
;16-bit timer register
TMRLR EQU
000052H
;16-bit reload register
DDR1
EQU
000011H
;Port data register
UF
EQU
TMCSR:2
;Flag bit for interrupt request
CNTE
EQU
TMCSR:1
;Counter operation enable bit
TRG
EQU
TMCSR:0
;Software trigger bit
;----------Main program-----------------------------------------------------CODE
CSEG
START:
;
:
;Stack pointer (SP) already initialized
AND
CCR, #0BFH
;Interrupt disabled
MOV
I:ICR09, #00H
;Interrupt level 0 (highest)
MOV
I:DDR5, #00H
;P50/TIN0 pin set to input
CLRB
I:CNTE
;Counter temporarily stopped
MOVW
I:TMRLR, #2710H ;Reload value set to 10000
MOVW
I:TMCSR, #0001110010001011B
;Counter operation, external trigger,
;leading edge, External output disabled
;Selection of one-shot mode,
;interrupts enabled, Interrupt flag cleared,
;counter start
;Counter clock divided by one
MOV
ILM, #07H
;ILM in PS set to level 7
OR
CCR, #40H
;Interrupts enabled
LOOP: MOV
A, #00H
;Infinite loop
MOV
A, #01H
;
BRA
LOOP
;
MB90820 series
EQU
0000B7H
287
;----------Interrupt program------------------------------------------------WARI:
CLRB
I:UF
;Interrupt request flag cleared
;
:
;
User processing
;
:
RETI
;Return from interrupt
CODE
ENDS
;----------Vector settings--------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FF94H
;Set the vector to interrupt #26 (1AH)
DSL
WARI
ORG
0FFDCH
;Reset vector settings
DSL
START
DB
00H
;Set Single-Chip mode
VECT
ENDS
END
START
288
MB90820 series
CHAPTER 12
PWC Timer
This chapter explains the functions and operations of the PWC timer.
12.1 Overview of the PWC Timer
12.2 Block Diagram of the PWC Timer
12.3 PWC Timer Pins
12.4 PWC Timer Registers
12.5 PWC Timer Interrupts
12.6 Operation of the PWC Timer
12.7 Usage Notes on the PWC Timer
12.8 Sample Programs for the PWC Timer
MB90820 series
289
12.1 Overview of the PWC Timer
The PWC timer (pulse-width measurement) is the multi-functional 16-bit up counter
with the reload function and also has a function that calculates the pulse width of the
input signal.
The PWC timer consists of a 16-bit counter, an input pulse divider, a division rate
control register, a count input pin, a pulse output pin, and a 16-bit control register.
■ PWC timer
The MB90820 series contain two PWC timer channels. The PWC timer has the following
characteristics:
● Timer function
•
Generates an interrupt request at the specified time interval.
•
Outputs the pulse signal that is synchronized with the timer period.
•
Selects the counter clock from three internal clocks.
● Pulse-width measurement function
•
Measures the time between external pulse input events.
•
Selects the counter clock from three internal clocks.
•
Count mode
•
H pulse width (rising edge to falling edge) / L pulse width (falling edge to rising edge)
•
Rising edge period (rising edge to falling edge) / falling edge period (falling edge to rising
edge)
•
Intermediate edge count (rising or falling edge to falling or rising edge)
•
Uses the 16-bit input divider to divide the input pulse by 22, 24, 26, and 28 to enable period
measurement.
•
Generates an interrupt request at completion of count.
•
Selects single count or continuous count.
■ PWC timer operation
This block is a multi-functional timer that is based on the 16-bit up-count timer and contains a count input pin
and an 8-bit input divider. The block has two main functions, a timer function and a pulse-with measurement
function, both of which enable the selection of two types of count clocks.
290
MB90820 series
12.2 Block Diagram of the PWC Timer
Figure 12.2-1 PWC timer block diagram.
■ PWC timer block diagram
PWC read
Error
detection
ERR
16
PWC
16
Write enabled
16
Overflow
Reload
P07/PWO0
P47/PWO1
F.F.
Data transfer
16
Clock
Overflow
22
16-bit up-count timer
23
Timer clear
F2MC-16LX bus
Count
enabled
CKS1, CKS0,
Divider clear
Count bit
output
Flag setting
Control circuit
Start edge
selection
Count end
edge
Count start edge
End edge
selection
Overflow interrupt request
15
Internal clock
(machine clock / 4)
Divider ON/OFF
P06/PWI0
P46/PWI1
Edge
detection
Count end interrupt request
PWCS
Clock
Clock
divider
8-bit
divider
CKS1
ERR CKS0
Division
rate
selection
2
DIVR
Figure 12.2-1 PWC timer block diagram
MB90820 series
291
12.3 PWC Timer Pins
This section describes the pins of the PWC timer and provides a pin block diagram.
■ PWC timer pins
The pins of the PWC timer are shared with the general-purpose ports. Table 12.3-1 lists the
functions of the pins, I/O format, and settings required to use the 16-bit reload timer.
Table 12.3-1 16-bit PWC timer pins
Pin name
Pin function
P06/PWI0
Port 0 input-output / timer input
P07/PWO0
Port 0 input-output / timer output
P46/PWI1
Port 4 input-output / timer input
I/O format
CMOS
output /
CMOS
input
Pull-up
option
Standby
control
Settings required for
pins
Setting for the input port
(DDR0: bit 6 = 0)
Selectable
Setting for timer enable
(PWCSL0: MOD2~0 not
equal 0)
Available
P47/PWO1
Port 4 input-output / timer output
CMOS
output /
CMOS
hysteresis
input
Setting for the input port
(DDR4: bit 6 = 0)
Not
provided
Setting for timer enable
(PWCSL1: MOD2~0 not
equal 0)
■ Block diagram of the PWC timer pins
Figure 12.3-1 shows the block diagram of the PWC timer 0 input pin.
RDR
Resource input
Port data register (PDR)
Pull-up resistor
Internal data bus
About 50KΩ
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 12.3-1 Block diagram of the PWC timer 0 input pin
292
MB90820 series
Figure 12.3-2 shows the block diagram of the PWC timer 0 output pin.
RDR
Resource output
Port data register (PDR)
Resource input
Resource output enable
Pull-up resistor
Internal data bus
About 50KΩ
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 12.3-2 Block diagram of the PWC timer 0 output pin
Figure 12.3-3 shows the block diagram of the PWC timer 1 input pin.
Resource input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 12.3-3 Block diagram of the PWC timer 1 input pin
MB90820 series
293
Figure 12.3-4 shows the block diagram of the PWC timer 1 output pin.
Resource output
Internal data bus
Port data register (PDR)
Resource input
Resource output enable
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 12.3-4
294
Block diagram of the PWC timer 1 output pin
MB90820 series
12.4 PWC Timer Registers
Following are the PWC timer registers.
■ PWC timer registers
PWC control status register (Upper)
Address: ch0 0000C1H
ch1 000029H
Read/write
Initial value
15
14
13
12
11
10
9
STRT
STOP
EDIR
EDIE
OVIR
OVIE
ERR
POUT
R/W
0
R
0
R/W
0
R/W
0
R/W
0
R
0
R/W
0
5
4
3
2
R/W
0
8
Bit number
PWCSH0~1
PWC control status register (Lower)
Address: ch0 0000C0H
ch1 000028H
Read/write
Initial value
7
6
MOD2
0
CKS1
CKS0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
10
PW15
PW14
PW13
PW12
PW11
PW10
PW09
PW08
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
4
3
2
1
0
PW01
PW00
R/W
X
R/W
X
Reserved Reserved
S/C
1
MOD1 MOD0
R/W
0
Bit number
PWCSL0~1
R/W
0
PWC data buffer register (Upper)
Address: ch0 0000C3H
ch1 00002BH
Read/write
Initial value
R/W
X
9
8
Bit number
PWC0~1
PWC data buffer register (Lower)
Address: ch0 0000C2H
ch1 00002AH
Read/write
Initial value
7
6
5
PW07
PW06
PW05
PW04
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
6
5
4
3
2
—
—
—
—
—
—
DIV1
X
X
X
X
X
X
R/W
0
PW03 PW02
R/W
X
Bit number
PWC0~1
Division rate control register
7
Address: ch0 0000C4H
ch1 00002CH
Read/write
Initial value
1
0
DIV0
Bit number
DIV0~1
R/W
0
Figure 12.4-1 PWC timer registers
MB90820 series
295
12.4.1 PWC control status register (PWCSH0/1, PWCSL0/1)
The PWC control status register (PWCSH0/1, PWCSL0/1) controls the PWC timer
operation and reads the PWC timer state.
■ PWC control status register, upper byte (PWCSH0/1)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
ch0: 0000C1H STRT STOP EDIR
ch1: 000029H R/W
R/W
R
EDIE
OVIR
OVIE
ERR
POUT
00000000B
R/W
R/W
R/W
R
R/W
POUT
Pulse output bit
0
When previous value is 1 and timer overflows
1
When previous value is 0 and timer overflows
ERR
Error flag bit
0
Count result is not overwritten
1
Count result is overwritten before previous value is read
OVIE
Overflow interrupt request enable bit
0
Disables overflow interrupt request
1
Enables overflow interrupt request
Overflow interrupt request bit
OVIR
Read
Write
0
No timer overflow
Clear this bit
1
Timer overflows
No effect
EDIE
End interrupt enable bit
0
Disables end interrupt request
1
Enables end interrupt request
EDIR
End interrupt request flag bit
0
Pulse-width measurement is operating
1
Pulse-width measurement is terminated
Operation status indication
STRT STOP
X
: Indeterminate
R/W : Read and write
: Initial value
—
: Not used
Read
Write
0
0
Timer stops (the timer is not
started or count ends)
No function. Operation is not
affected
0
1
No meaning
Starts or restarts the timer
(enables count)
1
0
No meaning
Stops the timer operation
(disables count)
1
1
Timer count operation in
progress (counting)
No function. The operation is not
affected
Figure 12.4.1-1 PWC control status register (PWCSH0/1)
296
MB90820 series
Table 12.4.1-1 PWC control status register (PWCSH0/1)
Bit name
Function
STRT, STOP:
Start and Stop
bits
• These bits are used to start, restart, and stop the 16-bit up-count timer.
• When these bits are read, the timer operation status is returned.
• These bits can be read and written. The meaning of bits depend on
whether they are read or written.
• In read-modify-write operation, “11B” is always read.
• When the STRT and STOP bits are written to start and stop the timer,
a bit manipulation instruction (such as bit clear instruction) can be
used. However, when the operation status (which always indicates
that the timer is operating, for example) is read, a bit manipulation
instruction cannot be used.
EDIR:
End interrupt
request flag bit
• This bit indicates that measurement terminated in pulse-width
measurement mode.
• When pulse-width measurement terminates, the bit is set (PWC0/1
contains the measurement result).
• This bit is cleared automatically when the meaurement result in PWC
data buffer register, PWC0/1, is read.
• In timer mode, this bit is meaningless.
• This bit is read-only, writing this bit is meaningless.
EDIE:
End interrupt
enable bit
• This bit is used to control a measurement termination interrupt request
in pulse-width count mode.
• When this bit is “1” and EDIR is set to “1”, the end interrupt request
will be generated to CPU.
• Always set “0” in timer mode.
bit11
OVIR:
Overflow
interrupt request
bit
• This bit is used to specify when the 16-bit up-count timer overflows.
The operation affects all modes.
• When timer overflow occurs (FFFFH to 0000H), the bit is set.
• Writing “0” will clear the bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
Note:In H/L pulse-width count mode, do not use this bit for pulsewidth time measurement.
bit10
OVIE:
Overflow
interrupt request
enable bit
• This bit is used to enable timer overflow interrupt request.
• When this bit is “1” and OVIR is set to “1”, the overflow interrupt
request will be generated to CPU.
Note:In the H/L pulse-width count mode, set this bit to “0”.
ERR:
Error flag bit
• This bit is used to execute a continuous count in the pulse-width count
mode. This flag indicates that the next count has been completed
before the previous count result is read from PWC0/1. If this state
occurs, PWC0/1 is overwritten by new count result and the previous
result is lost. The count operation continues regardless of the value of
this bit.
• The bit is read-only. Writing to this bit is meaningless.
• When the count result that has not been read is overwritten by the
next result, the bit is set.
• This bit is cleared automatically when the measurement result in PWC
data buffer register, PWC0/1, is read.
bit15
bit14
bit13
bit12
bit9
MB90820 series
297
Table 12.4.1-1 PWC control status register (PWCSH0/1)
Bit name
bit8
298
POUT:
Pulse output bit
Function
• When the 16-bit up-count timer overflows in timer mode, this bit is
reversed.
• In the pulse-width count mode, this bit is meaningless.
• The bit can be read and written. However, the bit can be written only if
the timer stops (both bit 15: STRT and bit 14: STOP are set to “0”). If
the bit is written during timer operation (both bit 15: STRT and bit 14:
STOP are set to “1”), the bit value remains unchanged.
• When the POUT value is “0” and the timer overflows in the range from
FFFFH to 0000H or the timer stops and 1 is written, the bit is set.
• When the POUT value is “1” and the timer overflows in the range from
FFFFH to 0000H or the timer stops and “0” is written, the bit is cleared.
The bit is also cleared by reset.
MB90820 series
Memo
MB90820 series
299
12.4
PWC Timer Registers
■ PWC control status register, lower byte (PWCSL0/1)
Address
ch0: 0000C0H
ch1: 000028H
bit7
bit6
bit5
bit4
CKS1 CKS0 Reserved Reserved
R/W
R/W
R/W
bit3
S/C
R/W
bit2
bit1
bit0 Initial value
MOD2 MOD1 MOD0 00000000B
R/W
R/W
R/W
MOD2 MOD1 MOD0
0
0
Timer mode and no pulse output
0
0
1
Timer mode and pulse output (PWO pin valid):
reload mode only
0
1
0
All edge-to-edge pulse-width measurement
mode (rising edge or falling edge to falling edge
or rising edge)
0
1
1
Division period measurement mode (when the
input divider is used)
1
0
0
Rising edge-to-rising edge period
measurement mode (rising edge to rising edge)
1
0
1
H pulse-width measurement mode (rising edge
to falling edge)
1
1
0
L pulse-width measurement mode (falling edge
to rising edge)
1
1
1
Falling edge-to-falling edge period
measurement mode (falling edge to falling
edge)
Count mode
selection
Single
measurement mode No reload (one shot)
1
Continuous
measurement mode
—
Reload (reload
timer)
Buffer register is
valid
Pulse-width count
mode
Stop after one
measurement
Continuous
measurement:
Buffer register is
valid
Count clock selection
0
0
Machine clock divided by 4 (0.17µs for machine cycle at
24 MHz)
0
1
Machine clock divided by 16 (0.67 µs for machine cycle
at 24 MHz)
1
0
Machine clock divided by 32 (1.33 µs for machine cycle
at 24 MHz)
1
1
Setting prohibited (undefined)
R/W : Read and write
: Initial value
Timer mode
0
CKS1 CKS0
: Indeterminate
Operation mode / count edge selection
0
S/C
X
R/W
: Not used
Figure 12.4.1-2 PWC control status register (PWCSL0/1)
300
MB90820 series
Table 12.4.1-2 PWC control status register (PWCSL0/1)
Bit name
bit7
bit6
CLK1,CLK0:
Clock select bits
Function
• CKS1 and CKS0 bits are used to select the internal count clock.
These bits are used to select the internal count clock.
• After reset, the bits are initialized to “00B”. The bits can be read and
written. However, “11B“ cannot be set.
Note: After the timer is started, changing the setting is prohibited.
Write these bits before the timer is started or after the timer is
stopped.
bit5
bit4
Reserved bits
bit3
• The S/C bit is used to select the count mode.
S/C:
• After reset, the bit is initialized to “0”. The bit can be read and written.
Singe/continuous
Note: After the timer is started, changing the setting is prohibited.
bit
Write this bit before the timer is started or after the timer is stopped.
• There bits are reserved. Always write “00B” to these bits.
• Setting these bits enables selection of the operating mode and the
pulse edge that fits the pulse-width count.
• After reset, these bits are initialized to “000B”. These bits can be read
and written.
bit2
bit1
bit0
MB90820 series
MOD2,MOD1,
MOD0:
Operation mode
bits
Note: After the timer is started, changing the setting is prohibited.
Write these bits before the timer is started or after the timer is
stopped.
If the continuous measurement mode is set for the setting marked *,
the number of edges are totaled and the divider for the internal
count clock is not cleared at the end of count. In all other modes,
the divider for the internal count clock is cleared at the end of the
count.
301
12.4
PWC Timer Registers
12.4.2 PWC data buffer register (PWC0/1)
The PWC data buffer register (PWC0/1) has functions that depend on the operation
mode of the PWC timer.
■ PWC data buffer register (PWC0/1)
PWC data buffer register (Upper)
Address: ch0 0000C3H
ch1 00002BH
Read/write
Initial value
15
14
13
12
11
10
9
8
PW15
PW14
PW13
PW12
PW11
PW10
PW09
PW08
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
4
3
2
1
0
Bit number
PWC0~1
PWC data buffer register (Lower)
Address: ch0 0000C2H
ch1 00002AH
Read/write
Initial value
7
6
5
PW07
PW06
PW05
PW04
PW03
PW02
PW01
PW00
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Bit number
PWC0~1
Figure 12.4.2-1 PWC data buffer register (PWC0/1)
● Timer mode
In the reload timer operation mode (PWCSL0/1:S/C = 1), this register contains the reload value.
The register can be read or written.
In the single timer operation mode (PWCSL0/1:S/C = 0), direct access to this register accesses
the up-count timer. In this mode, this register can be read or written. However, the register is
written only when the timer stops. The register can always be read and the current timer value is
read.
● Pulse-width measurement mode (read-only)
In the continuous measurement mode (PWCSL0/1:S/C = 1), this register functions as the buffer
register and contains the previous count result. This register is read-only. Writing to this register
has no effect.
In the single measurement mode (PWCSL0/1:S/C = 0), direct access to this register accesses
the up-count timer. In this mode, the register is also read-only. Writing to this register has no
effect. The register can always be read and the current timer value is read. After the count, the
register contains the count results.
Notes:To access this register, always use the word transfer instruction.
After reset, this register is initialized to “0000H”.
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MB90820 series
12.4.3 Division rate control register (DIV0/1)
The division rate control register (DIV0/1) is used in the division period measurement
mode (PWCSL:MOD2, 1, and 0 = 011B). This register has no meaning in other modes.
■ Division rate control register (DIV0/1)
Address
ch0: 0000C4 H
ch1: 00002C H
X
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
—
—
—
—
—
—
DIV1
DIV0 XXXXXX00B
—
—
—
—
—
—
R/W
R/W
DIV1
DIV0
0
0
22 = divided by 4
0
1
24 = divided by 16
1
0
26 = divided by 64
1
1
28 = divided by 256
: Indeterminate
R/W : Read and write
Initial value
Division rate selection bits
: Initial value
—
: Not used
Figure 12.4.3-1 Division rate control register (DIV0/1)
Table 12.4.3-1 Division rate control register (DIV0/1)
Bit name
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
MB90820 series
Unused bit
DIV1,DIV0:
Division rate
selection bits
Function
• The read value is indeterminate.
• Writing to these bits has no effect on the operation.
• In the division range measurement mode, this register is used to
divide the pulse input from the measurement pin and measure the
one-period width after division.
• After reset, these bits are initialized to “00B”. These bits can be read
and written.
Note: After the timer starts, the setting cannot be changed. Write
these bits before the timer has started or after the timer has
stopped.
303
12.5
PWC Timer Interrupts
12.5 PWC Timer Interrupts
The PWC timer is enabled to generate an interrupt request in an overflow of the
counter or measurement terminated in pulse-width measurement mode. It is also
coordinated with the extended intelligent I/O service (EI2OS).
■ PWC timer interrupts
Table 12.5-1 lists the interrupt control bits and interrupt causes of the PWC timer.
Table 12.5-1 Interrupt control bits and interrupt causes of the PWC timer
PWC timer 0
PWC timer 1
Interrupt request flag
bit
PWCSL0: OVIR
PWCSL0: EDIR
PWCSL1: OVIR
PWCSL1: EDIR
Interrupt request
enable bit
PWCSL0: OVIE
PWCSL0: EDIE
PWCSL1: OVIE
PWCSL1: EDIE
Overflow of the
16-bit up
counter
Measurement
terminated in
pulse-width
measurement
mode
Overflow of
the 16-bit up
counter
Measurement
terminated in
pulse-width
measurement
mode
Interrupt cause
In the PWC timer, the OVIR bit of the PWC control status register (PWCSL) is set to 1 by an
overflow (from FFFFH to 0000H) of the up counter. If an interrupt request is enabled
(PWCSL:OVIE = 1) in this operation, the interrupt request is output to the interrupt controller.
The EDIR bit of the PWC control status register (PWCSL) is set to 1 by measurement terminated
in pulse-width measurement mode. If an interrupt request is enabled (PWCSL:EDIE = 1) in this
operation, the interrupt request is output to the interrupt controller.
■ PWC timer interrupts and EI²OS
Table 12.5-2 lists the PWC timer interrupts and EI²OS.
Table 12.5-2 16-bit PWC timer interrupts and EI²OS
Channel
Interrupt
number
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
PWC timer 0*1
#13 (0DH)
ICR01
0000B1H
FFFFC8H
FFFFC9H
FFFFCAH
PWC timer 1*2
#24 (18H)
ICR06
0000B6H
FFFF9CH
FFFF9D H
FFFF9EH
O
*1: The same interrupt number as that for 16-bit PPG timer 0 is assigned to PWC timer 0.
*2: The same interrupt number as that for output compare channel 5 match is assigned to PWC
timer 1.
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MB90820 series
■ EI²OS function of the PWC timer
Since the PWC timer has a circuit that coordinates with EI2OS, the counter can start EI2OS when
an overflow or measurement termination occurs.
However, EI2OS is available only when other peripheral functions sharing the interrupt control
register (ICR) do not use interrupts. For example, when PWC timer 0 uses EI²OS, interrupts of
the 16-bit PPG timer 0 must be disabled.
MB90820 series
305
12.6
Operation of the PWC Timer
12.6 Operation of the PWC Timer
The PWC timer is the multi-functional timer based on the 16-bit up-count timer and
contains the count input pin and 8-bit input divider. The block has two main functions:
timer function and pulse-width count function. Both the timer function and the pulsewidth count function enable the selection of two types of count clocks.
■ Timer function
The timer function is the up-count timer that enables selection of the operation in single mode or
reload mode.
When the timer is started, a timer count is performed at each count clock.
When an overflow occurs in the range from FFFFH to 0000H, an interrupt request is issued.
If an overflow occurs, the following occurs:
During single mode, count is discontinued (see Figure 12.6-1).
During reload mode, the reload register contents are reloaded to the timer and the count is
restarted (see Figure 12.6-2).
Timer count value
Overflow
Overflow
FFFFH
Write to
PWC
(Restart is invalid)
0000H
Timer starts
Timer starts
OVIR flag setting, Timer stops
OVIR flag setting, Timer stops
Time
Figure 12.6-1 Timer operation (single mode)
306
MB90820 series
Overflow
Overflow
Timer count value
Overflow
Overflow
Overflow
FFFFH
(Restart is invalid)
PWC write value
Reload
Reload
Reload
Reload
Reload
Reload
0000H
Write to PWC
Timer starts
Reload
Restart
Timer stop
OVIR flag setting
Time
POUT bit
If the timer is started at L level, the level is not toggled when the timer is restarted
(except when an overflow occurs simultaneously)
Figure 12.6-2 Timer operation (reload mode)
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307
■ Pulse-width measurement function
The pulse-width measurement function calculates the time between the specified events related
to the input pulse.
When this function is activated, a count is started after the specified count start edge is input. If
the counter is cleared to 0000H, a count is started when the start edge is detected, then the stop
edge is detected. The count value during this period is held in the register as the pulse width.
When the measurement terminates or an overflow occurs, an interrupt request can be
generated. When the measurement is completed, the following occurs:
•
Single measurement mode
The operation is discontinued (see Figure 12.6-3).
•
Continuous measurement mode
The timer value is transferred to the buffer register and the timer is in free-running state until
the next edge is input (see Figure 12.6-4).
PWC input
measured pulse
(The solid line indicates the timer count value)
Timer count value
FFFFH
Timer
clears
0000H
Start of
Timer
measurement starts
Timer
stops
EDIR flag setting (termination of measurement)
Time
Figure 12.6-3 Pulse-width measurement operation (single measurement mode, H width measurement
mode)
308
MB90820 series
PWC input
measured pulse
(The solid line indicates the timer count value)
Timer count value
Data transfer
to PWC
FFFFH
Timer
clears
Data transfer
to PWC
Timer clear
0000H
Start of
Timer
measurement starts
OVIR flag Timer
setting
starts
EDIR flag setting
(termination of measurement)
OVIR flag
setting
EDIR flag setting
Time
*
*: The timer value during this period is not guaranteed (a timer overflow may result in OVIR being set)
Figure 12.6-4 Pulse-width measurement operation (continuous measurement mode, H-width measurement mode)
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12.6.1 Operation mode selection
Operation modes and count modes are selected according to the setting of PWCS.
■ Operation mode selection
The following registers are used to set the selection of operation modes and count modes:
● Operation mode setting: PWCSL:MOD2, MOD1, and MOD0 bits
Select the timer mode or pulse-width measurement mode to specify control of the count
operation.
● Count mode setting: PWCSL:S/C bit
Select single measurement or continuous measurement or reload operation or one-shot
operation.
Table 12.6.1-1 lists the operation modes selected using the mode setting bits.
Table 12.6.1-1 Operation mode selection
Operation mode
Timer
Pulse-width
measurement
S/C
MOD2
MOD1
MOD0
One-shot timer
0
0
0
0
Reload timer
1
0
0
0/1
Setting prohibited
0
0
0
1
Rising edge or falling
edge to falling edge or
rising edge:
All edge-to-edge
measurement
Single measurement: Buffer invalid
0
0
1
0
Continuous measurement: Buffer valid
1
0
1
0
Division count:
Divide by 4 to 256
Single measurement: Buffer invalid
0
0
1
1
Continuous measurement: Buffer valid
1
0
1
1
Rising edge to rising
edge:
Rising edge to rising
edge period
measurement
Single measurement: Buffer invalid
0
1
0
0
Continuous measurement: Buffer valid
1
1
0
0
Rising edge to falling
edge:
H pulse-width
measurement
Single measurement: Buffer invalid
0
1
0
1
Continuous measurement: Buffer valid
1
1
0
1
Falling edge to rising
edge:
L pulse-width
measurement
Single measurement: Buffer invalid
0
1
1
0
Continuous measurement: Buffer valid
1
1
1
0
Falling edge to falling
edge:
Falling edge-to-falling
edge period
measurement
Single measurement: Buffer invalid
0
1
1
1
Continuous measurement: Buffer valid
1
1
1
1
After reset, the one-shot timer is selected as an initial value.
Note: Before the timer starts, always selects the operation mode.
310
MB90820 series
12.6
Operation of the PWC Timer
12.6.2 Starting and stopping the timer and pulse-width
measurement and clearing the timer
To start, restart, and forcibly stop the timer and pulse-width measurement, use the
PWCSH0/1:STRT and PWCSH0/1:STOP.
The 16-bit up-count timer is cleared to 0000H at reset and when the measurement start
edge is detected and the count is started in the pulse-width measurement mode.
■ Starting and stopping timer and pulse-width measurement
Writing 0 to the PWCSH0/1:STRT bit starts or restarts the operation, and writing 0 to the
PWCSH0/1:STOP bit stops the operation. However, unless the value is written to these two bits
are different, none of the bits executes operations. If an instruction (byte or word instruction)
other than the bit manipulation instruction is being used, a value is written to the following bit
combinations only.
Table 12.6.2-1
Pulse-width measurement operation (single measurement mode, H width
measurement mode)
Function
STRT
STOP
Starts and restarts the timer or pulse-width measurement
0
1
Stops the timer or pulse-width measurement
1
0
If a bit manipulation instruction (clear bit instruction) is being used, the hardware automatically
writes the above combination of values. The user need not know which value is to be written.
● Operation after start
Timer mode: The count operation is started immediately.
Pulse-width measurement mode: Measurement is started after the measurement start edge is
input. After the measurement start edge is detected, the 16-bit up-count timer is cleared to
0000H and the count is started.
● Restarting the timer
While the timer operation continues after the timer is started in the timer mode or pulse-width
measurement mode, starting the start (writing 0 to the PWCSH0/1:STRT bit) is called timer
restart. The operations to be executed during restart are dependent on the following modes:
One-shot mode: The operation is not affected.
Reload timer mode: Reload is executed and the operation is continued. If the timer is restarted
when an overflow occurs, the overflow flag (PWCSH0/1:OVIR) is set and the POUT bit is
reversed.
Pulse-width measurement mode: In the measurement start edge wait state, the operation is not
affected. During measurement, the count stops and the timer state returns to the "measurement
start edge wait" state. When the timer is restarted on termination of measurement, the
measurement termination flag (PWCSH0/1:EDIR) is set and the measurement results are
transferred to PWC0/1 in continuous measurement mode.
MB90820 series
311
12.6
Operation of the PWC Timer
● Stopping the timer
In one-shot timer mode or single measurement mode, measurement is automatically
discontinued when the timer overflows or at the end of a count. The user need not know if the
timer has stopped. However, in other modes, the timer must be stopped. This is also true when
the timer is to be stopped before the timer automatically stops.
● Checking operation state
The previously described STRT and STOP bits function as bits that indicate the operation state
of the timer during a read operation. Table 12.6.2-2 lists the contents of the indicated values.
Table 12.6.2-2
Functions of operation state indication bits
STRT
STOP
Operation state
0
0
Timer is stopping (except measurement start edge wait state).
The bits indicate that the timer has not started or a measurement has terminated.
1
1
Measurement start edge wait state or timer count operation
During a read operation, both the STRT bit and the STOP bit have the same value. However,
during a read operation using the read modify write instruction (such as bit manipulation
instruction), the values of the bits are always 11 B. Do not use this instruction to read the values
of the bits.
■ Clearing the timer
In the following cases, the 16-bit up-count timer is cleared to 0000H:
312
•
During reset
•
When a count has started after the count start edge is detected in the pulse-width
measurement mode
MB90820 series
12.6
Operation of the PWC Timer
12.6.3 Timer Mode Operation
The timer mode includes the one-shot operation mode and reload operation mode.
■ One-shot operation mode
When the timer is started in this mode, a count is incremented at each count clock. The timer
automatically stops when an overflow occurs from FFFFH to 0000H.
If PWC0/1 is set before the timer has started, the count is started from this set value. After
overflow, the set value is deleted and the current count value remains in PWC0/1.
PWCSH0/1:POUT is reversed if an overflow occurs.
■ Reload operation mode
When the timer is started in this mode, the reload value in PWC0/1 is set in the timer and the
count is incremented at each count clock. If an overflow occurs when the timer counts FFFFH to
0000H, the reload value in PWC0/1 is set in the timer again, the PWCSH0/1:POUT bit is
reversed, and the count operation is repeated. The timer does not stop until a value is written to
the PWCSH0/1:STOP to stop the timer or it is reset. The port bit will output to pin PWO0/1 if
pulse output mode is specified.
The reload value (set in PWC0/1 before the timer is started) is stored during a count. When the
timer is started or restarted and an overflow occurs, the reload value is always set in the timer. If
the value that is set during a count is to be changed, a new reload value becomes valid when
the next overflow occurs or the timer is restarted.
■ Timer value and reload value
In one-shot operation mode, direct access to PWC0/1 accesses the up-count timer. When a
value is written to PWC0/1, the value is written directly to the timer. When PWC0/1 is read
during a count operation, the current timer value is read. If the value is set in PWC0/1 before the
timer is started, the timer starts a count from the specified value.
In reload operation mode, the up-count timer cannot be accessed and PWC0/1 functions as a
reload register (stores the reload value). When the timer is started or restarted and an overflow
occurs, the value written to PWC0/1 is always set in the timer. When PWC0/1 is read, the stored
reload value is read.
The PWC0/1 value and timer value are undefined if the timer is set in one-shot mode after the
operation is discontinued in reload mode. Therefore, always set the values before the timer is
used.
The PWC0/1 value is undefined if the timer is set in reload mode after the operation is forcibly
discontinued in one-shot mode. Therefore, always set the value before the timer is used.
■ Interrupt request generation
During operation in timer mode, an overflow enables the generation of an interrupt request. If
the increment of a timer count causes an overflow, the overflow flag is set, an overflow interrupt
request is enabled, and an interrupt request is generated.
MB90820 series
313
■ Timer period
If the timer is started in one-shot mode after 0000H is set in PWC0/1, a timer overflow occurs
and the count is discontinued if the count exceeds 65536. The following formula is used to
calculate the time from start to stop of the timer.
T1 = (65536-n 1) x t
{
T1 ...... Time from start to stop (µs)
n1 ...... Timer value set in PWC0/1 when the timer is started
t ...... Count clock period (µs)
If the timer is started after 0000H is set in PWC0/1, a timer overflow occurs every time the count
exceeds 65536. The following formula is used to calculate the reload period and the PWO pin
output pulse period.
TR ...... Reload period (overflow period) (µs)
TR = (65536-NR) x t
{
TPOUT ...... PWO0/1 pin output pulse period (µs)
NR ...... Reload value stored in PWC0/1
t ...... Time from start to stop (µs)
■ Count clock and maximum period
In timer mode, when 0000H is set in PWC0/1, the maximum period results.
Table 12.6.3-1 lists the count clock period and maximum timer period corresponding to the
machine cycle (indicated by φ in the table) at 24 MHz.
Table 12.6.3-1
Count clock and period
Count clock selection
Count clock period
Maximum timer period
314
When CKS1, 0=00B
(φ/4)
When CKS1, 0=01B
(φ/16)
When CKS1, 0=10B
(φ/32)
0.17 µs
0.67 µs
1.33 µs
10.92 ms
43.69 ms
87.38 ms
MB90820 series
12.6
Operation of the PWC Timer
■ Flowchart of timer mode operation
Setting
-Select count clock
-Select operation mode and timer mode
-Clear interrupt flag
-Enable interrupt
-Set pulse output initial value
Set value in PWC
Restart
Start by STRT bit
Reload operation mode
Single operation mode
Reload PWC value to timer
Start count
Start count
Addition
Addition
Overflow occurs
Set OVIR flag
Reverse POUT
bit value
Overflow occurs
Set OVIR flag
Reverse POUT
bit value
Discontinue count
Discontinue operation
Figure 12.6.3-1 Flowchart of timer mode operation
MB90820 series
315
Memo
316
MB90820 series
12.6.4 Pulse Width Measurement Mode Operation
The signal for pulse-width measurement is input from the PWI pin.
The pulse-width measurement mode includes the single measurement mode in which
the count is performed only once and continuous measurement mode in which the
pulse width is continuously measured.
■ Single measurement mode and continuous measurement mode
The differences between the single measurement mode and continuous measurement mode are as follows:
● Single measurement mode
When the first count end edge is input, the timer discontinues the count, the count end flag
(EDIR) of PWCSH0/1 is set, and the subsequent measurement is not performed. However, if a
timer restart is also specified, the timer state changes to measurement start edge wait state.
● Continuous measurement mode [H/L pulse-width measurement mode]
When the count end edge is input, the count end flag (EDIR) of PWCSH0/1 is set, the timer
count result is transferred to PWC0/1, and the timer may continue incrementing the count in a
free-run state. When the next count start edge is input, the timer is cleared to 0000H and the
pulse-width count is started.
Notes:
When the count end edge is input and the timer enters a free-running state, the timer may
overflow and the OVIR flag may be set. In the H/L pulse-width measurement mode, do not
use the OVIR flag to measure the pulse-width time.
[All edge-to-edge pulse-width measurement mode, division period measurement mode, rising
edge-to-rising edge measurement mode, and falling edge-to-falling edge measurement
mode]
When the count end edge (count start edge) is input, the count end flag (EDIR) of PWCSH0/1
is set, the timer count result is transferred to PWC0/1, the timer is cleared to 0000H, and the
count is restarted.
■ Measurement result data
Handling of the measurement result, timer value, and PWC0/1 function varies with the single measurement
mode and continuous measurement mode as follows:
● Single measurement mode
When PWC0/1 is read during timer operation, the current timer value is read.
When PWC0/1 is read after termination of measurement, the measurement results are read.
● Continuous measurement mode
At termination of measurement, the timer measurement results are transferred to PWC0/1.
When PWC0/1 is read, the previous measurement results are read. While measurement is in
progress, the previous measurement results are stored in PWC0/1. During measurement, the
timer value cannot be read.
In continuous measurement mode, unless the previous measurement results are read before
MB90820 series
317
completion of the next measurement, a new measurement result overwrites the existing value.
The error flag (ERR) of PWCSH0/1 is set. When PWC0/1 is read, the error flag (ERR) is cleared
automatically.
318
MB90820 series
12.6
Operation of the PWC Timer
■ Minimum input pulse width
The pulse must be input to the pulse-width count input pin (PWI0/1) longer than the following
minimum input pulse width.
Pulse width: 2 machine cycles (0.833 ηs or more for the machine clock at 24 MHz)
However, the input pulse that is shorter than the above specification may also be recognized as
a valid pulse.
■ Calculating pulse width/period
The pulse width or pulse period of the measurement object is calculated based on the count
result read from PWC0/1 at the end of a count as follows.
TW...... Measured pulse width or pulse period (µs)
TW = n x t / Div (µs)
{
n ...... Measurement result contained in PWC0/1
t ...... Count clock period (µs)
Div ...... Division rate set in the division rate register (DIV0/1)
(a value of 1 is used in a mode other than the division count mode)
n Pulse width/period measurement range
The range of the pulse width/period that can be measured depends on the count clock and
division rate of an input divider.
Table 12.6.4-1 lists the measurement range for the machine cycle (indicated by φ) at 24 MHz.
Table 12.6.4-1
Division rate
DIV1, 0
No division
-
Divide-by 4
Pulse width measurement range
CKS1, 0=00B (φ/4)
CKS1, 0=01B (φ/16)
CKS1, 0=10B (φ/32)
0.833 ηs to 10.92 ms [0.17 µs] 0.833 ηs to 43.7 ms [0.67 µs]
0.833 ηs to 87.38 ms [1.33 µs]
00B
0.833 ηs to 2.73 ms [41.7 ηs]
0.833 ηs to 21.85 ms [333 ηs ]
Divide-by 16
01B
0.833 ηs to 682.7 µs [10.4 ηs] 0.833 ηs to 2.73 ms [41.7 ηs]
0.833 ηs to 5.46 ms [83.3 ηs]
Divide-by 64
00B
0.833 ηs to 170.7 µs [2.60 ηs] 0.833 ηs to 682.7 µs [10.4 ηs]
0.833 ηs to 1.37 ms [20.83 ηs]
Divide-by 256
11B
0.833 ηs to 42.7 µs [0.65 ηs]
0.833 ηs to 0.34 ms [5.21 ηs]
0.833 ηs to 10.92 ms [0.17 µs]
0.833 ηs to 170.7 µs [2.60 ηs]
Note: The number in [ ] indicates the resolution per bit.
n Interrupt request generation
In the pulse-width measurement mode, the following two interrupt requests can be generated:
● Timer overflow interrupt request
If an overflow occurs during a count, the overflow flag is set.
request is enabled, an interrupt request is generated.
When the overflow interrupt
● Measurement termination interrupt request
When the measurement termination edge is detected, the count end flag (EDIR) of PWCSH0/1
is set. If the measurement termination interrupt is enabled, an interrupt request is generated.
The measurement termination flag (EDIR) is automatically cleared when PWC0/1 is read.
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319
■ Measurement mode and measurement operation
Table 12.6.4-2 lists measurement mode operations.
Table 12.6.4-2
Measurement mode
MOD2
Measurement mode operation
MOD1
MOD0
Measurement operation
w
H pulse-width
measurement
1
0
1
Start of
measurement
w
Termination of
measurement
Termination of
measurement
Start
The H period width is measured.
Start of measurement:
Termination of measurement:
When the rising edge is detected
When the falling edge is detected
w
L pulse-width
measurement
1
1
0
Start of
measurement
w
Termination of
measurement
Termination of
measurement
Start
The L period width is measured.
Start of measurement:
End of measurement:
w
Rising edge-to-rising
edge period
measurement
Start of
measurement
1
0
When the falling edge is detected
When the rising edge is detected
w
Termination of
measurement
Start
0
w
Termination
Termination
Start
The rising edge-to-rising edge time is measured.
Start of measurement:
Termination of measurement:
w
Start of
measurement
Falling edge-to-falling edge period
measurement
1
1
When the rising edge is detected
When the rising edge is detected
w
Termination of
measurement
Start
1
w
Termination
Termination
Start
The falling edge-to-falling edge time is measured.
Start of measurement:
Termination of measurement:
w
Start of
measurement
All edge pulse-width
measurement
0
1
0
When the falling edge is detected
When the falling edge is detected
w
Termination of
measurement
Start
w
Termination
Start
Termination
The width between continuous input edges is measured.
Start of measurement:
Termination of measurement:
320
When the edge is detected
When the edge is detected
MB90820 series
12.6
Operation of the PWC Timer
Table 12.6.4-2
Measurement mode
MOD2
Measurement mode operation(Continued)
MOD1
MOD0
Measurement operation
φ
w
Start of
measurement
Division
measurement
0
1
1
w
Termination of
measurement
Start
w
Termination
(Divided by 4 in the above example.)
The input pulse is divided by the division rate set in the division rate
register (DIVR), and the measurement period is obtained as a result.
Start of measurement:
Termination of measurement:
The falling edge is detected after
the operation is started.
One period of division signal
ends.
W: Pulse width being measured
In all modes, the timer does not start count during the period from the start of measurement to
input of measurement start edge. After the measurement start edge is input, the timer is cleared
to 0000H, and the count is incremented at each count clock until the measurement termination
edge is input.
When the measurement termination edge is input, the following operations are executed:
(1)
The count end flag (EDIR) of PWCSH0/1 is set.
(2)
The timer stops count operation (except if the timer is restarted at the same time or continuous
measurement mode of the H/L pulse-width measurement is used).
(3)
Continuous measurement mode: The timer value (measurement result) is transferred to PWC0/1.
(4)
Single measurement mode: Measurement is terminated (except if the timer is restarted at the
same time).
If all edge-to-edge pulse-width measurement, period measurement, falling edge-to-falling edge
period measurement, or rising edge-to-rising edge period measurement is done in continuous
measurement mode, the termination edge becomes the next measurement start edge.
MB90820 series
321
■ Flowchart of pulse-width measurement operation
Setting
-Select count clock
-Select operation mode and timer mode
-Clear interrupt flag
-Enable interrupt
Restart
Start by STRT bit
Continuous measurement mode
Detect count start page
Single operation mode
Detect count start page
Clear timer
Clear timer
Start count
Start count
Addition
Addition
Overflow occurs
Set OVIR flag
Overflow occurs
Set OVIR flag
Detect count end edge
Set EDIR flag
Detect count end edge
Set EDIR flag
Discountinue count*
Discountinue count*
Transfer timer value to PWC
Discontinue operation
*: Except continuous measurement mode of H/L pulse-width measurement
Figure 12.6.4-1 Flowchart of pulse-width measurement mode operation
322
MB90820 series
Memo
MB90820 series
323
12.7 Usage Notes on the PWC Timer
Notes on using the PWC timer are given below.
■ Usage notes on the PWC timer
● Notes about using a program for setting
•
Changing the following PWCS0/1 bit values is prohibited during timer operation. The bit
values are changed only before the timer is started or after the operation is discontinued.
[Bits 7 and 6] CKS1 and CKS0: Clock selection bits
[Bit 3] S/C: Measurement mode (single or continuous) selection bit
[Bits 2, 1, and 0] MOD2, MOD1, and MOD0: Operation mode and measurement edge
selection bits
Note that the value of pulse output level indication bit (POUT: bit 8) remains unchanged even
if the bit is written during timer operation.
•
Changing the DIV0/1 value is prohibited during timer operation. Change the DIV0/1 value
before the timer is started or after the operation has stopped.
•
Setting the clock selection bits CKS1 and CKS0 of PWC control status register (PWCSL0/1)
to 11B is prohibited.
•
The PWC0/1 and timer values are determined when the timer is set in the one-shot mode or
after the operation is terminated in reload timer mode. Therefore, always set the values after
the timer is used.
•
The PWC0/1 value is undefined if the timer is set in reload timer mode after the operation is
discontinued in the one-shot mode. Therefore, always set the value before the timer is used.
•
To change the mode from pulse-width measurement mode to timer mode, always set the
value in PWC0/1 before the timer has started.
•
When division period measurement mode is used in pulse-width measurement mode, the
input pulse is divided. Note that the pulse width calculated from the count result becomes a
mean.
•
During continuous measurement in pulse-width measurement mode, the division circuit for an
internal count clock is not cleared, and the number of edges smaller than the count clock is
added to the count result.
● Notes about using a program for status checking
324
•
In timer mode, the value of the measurement termination interrupt request flag (EDIR) of
PWCSH0/1 is insignificant. Therefore, always set 0 in the count end interrupt request (EDIE)
enable bit of PWCSH0/1.
•
The STRT and STOP bits of PWC control status register (PWCSH0/1) are dependent on
whether they are read or written (see the details of registers). Read modify write instruction
always reads the bits as 11 B. So bit manipulation instruction cannot be used to read the
MB90820 series
12.7
Usage Notes on the PWC Timer
operation state.
However, a bit manipulation instruction (bit clear instruction) can be used to start or stop the
timer by writing the STRT or STOP bit.
•
In the pulse-width measurement mode, the measurement start edge causes the timer to be
cleared, and the previous timer data is insignificant.
● Notes about pulse input to the pulse width measurement input pin
•
Minimum pulse width is divide-by 2 of machine cycle (83.33 ηs or more for the machine cycle
at 24 MHz)
•
Maximum input frequency is divide-by 4 of machine cycle (4 MHz or less for the machine
cycle at 24 MHz)
If a pulse width smaller than the above or a frequency larger than the above is input, the timer
operation is not guaranteed. A noise violating the above constraint and appearing in the
input signal must be reduced.
•
If a pulse width smaller than the above or a frequency larger than the above is input, the timer
operation is not guaranteed. A noise violating the above constraint and appearing in the
input signal must be reduced.
● Notes about restart the timer during operation
•
If the timer is restarted when an overflow occurs in reload timer mode, the timer is restarted
but the overflow flag (OVIR) is set and the POUT bit is reversed (that is, the same operation
as the normal overflow is executed).
•
If the timer is restarted when the measurement termination edge is detected in one-shot
pulse-width measurement mode, the timer is restarted and enters measurement start edge
wait state but the measurement termination flag (EDIR) is also set.
•
If the timer is restarted when the measurement termination edge is detected in continuous
pulse-width measurement mode, the timer is restarted and enters the measurement start
edge wait state, the count termination flag (EDIR) is set, and the measurement results are
transferred to PWC0/1.
•
To restart the timer during operation, note the flag (OVIR, EDIR) operations to generate
interrupts and exercise other controls.
● Notes about interrupts
•
When the OVIR bit of the PWC control status register (PWCSH0/1) is set to 1 and an
interrupt request is enabled (PWCSH0/1:OVIE = 1), control cannot be returned from interrupt
processing. Always clear the OVIR bit.
•
When the EDIR bit of the PWC control status register (PWCSH0/1) is set to 1 and an
interrupt request is enabled (PWCSH0/1:EDIE = 1), control cannot be returned from interrupt
processing. Always clear the OVIR bit.
•
Since the PWC timer shares an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the PWC timer, shared resource interrupts must be disabled.
MB90820 series
325
12.8 Sample Programs for the PWC Timer
This section contains sample programs for the PWC timer.
■ Sample program for the PWC timer
● Processing
•
An output PWO0 of 30.6 Hz is generated with PWC timer 0.
•
The PWC is used in reload timer mode to repeatedly generate an overflow interrupt.
•
EI2OS is not used.
•
24 MHz is used for the machine clock, and 0.17 µs is used for the count clock.
● Coding example
ICR01
EQU
0000B1H
; Interrupt control register for the PWC timer
PWCS0 EQU
000008H
; PWC control status register
PWC0
EQU
00000AH
; PWC data buffer register
OVIR
EQU
PWCS0:11
; Interrupt request flag bit
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
; Assumes that stack pointer (SP) has already been
initialized
AND
CCR,#0BFH
; Interrupt disable
MOV
I:ICR01,#00H
; Interrupt level 0 (strongest)
MOVW I:PSC0,#0FF00H
; Sets the reload value
MOVW I:PWCS0,#4409H
; Sets reload timer mode, 0.17 µs clock
; Enable PWC output
; Sets overflow interrupt
; Clears interrupt flag and starts PWC timer
MOV
ILM,#07H
; Sets ILM in PS to level 7
OR
CCR,#40H
; Interrupt enable
LOOP:
MOV
A,#00H
; Endless loop
MOV
A,#01H
;
BRA
LOOP
;
;-------Interrupt program-------------------------------------------------------------------------------------------WARI:
CLRB I:OVIR
; Clears interrupt request flag
;
:
;
User processing
;
:
RETI
; Returns from interrupt
326
MB90820 series
CODE
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG
0FFC8H
; Sets vector for interrupt #13 (0DH)
DSL
WARI
ORG
0FFDCH
; Sets reset vector
DSL
START
DB
00H
; Sets single-chip mode
VECT
ENDS
END
START
MB90820 series
327
328
MB90820 series
CHAPTER 13
16-BIT PPG TIMER
This chapter describes the functions and operation of the 16-bit PPG Timer.
13.1 Overview of 16-bit PPG Timer
13.2 Block Diagram of 16-bit PPG Timer
13.3 16-bit PPG Timer Pins
13.4 16-bit PPG Timer Registers
13.5 16-bit PPG Timer Interrupts
13.6 Operation of 16-bit PPG Timer
13.7 Usage Notes on the 16-bit PPG Timer
13.8 Sample Programs for the 16-bit PPG Timer
MB90820 series
329
13.1 Overview of 16-bit PPG Timer
The 16-bit PPG timer consists of a 16-bit down counter, prescaler, 16-bit period setting
register, 16-bit duty setting register, 16-bit control register and a PPG output pin.
■ 16-bit PPG timer (x 3)
The 16-bit PPG timer consists of a 16-bit down counter, prescaler, 16-bit period setting register,
16-bit duty setting register, 16-bit control register and a PPG output pin. This module can be
used to output pulses synchronized by software trigger or GATE signal from Multi-functional
timer, refer to “Multi-functional Timer” in chapter 14.
•
•
•
330
8 types of counter operation clock (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128) can be selected
(φ is the machine clock).
An interrupt is generated when there is a trigger or an counter borrow or when PPG rising
(normal polarity) / PPG falling (inverted polarity).
PPG output operation
The 16-bit PPG timer can output pulse waveforms with variable period and duty ratio. Also, it
can be used as D/A converter in conjunction with an external circuit.
MB90820 series
13.2 Block Diagram of 16-bit PPG Timer
This section shows the block diagram of 16-bit PPG timer.
Period Setting Buffer Register 0/1/2
Duty Setting Buffer Register 0/1/2
Prescaler
CKS2
CKS1
CKS0
Period Setting Register 0/1/2
F2MC-16LX bus
1/1
1/2
1/4
1/8
1/16
1/32
1/64
1/128
Duty Setting Register 0/1/2
Comparator
CLK
LOAD
16-bit down counter
MDSE PGMS OSEL POEN
STOP
START
BORROW
P37/PPG0
or
P40/PPG1
or
P50/PPG2
Machine clock φ
Pin
Down Counter Register 0/1/2
S
Q
PPG0 (multi-functional timer)
or
PPG1 (multi-pulse generator)
or
PPG2
R
Interrupt
selection
Interrupt
#14/#16/#32
GATE - from multi-functional
timer (for PPG ch. 0 only)
IRS1
Edge detection
IRS0
IRQF
IREN
(for PPG ch. 1 & 2)
STGR CNTE RTRG
Figure 13.2-1 Block diagram of 16-bit PPG Timer
MB90820 series
331
13.3 16-bit PPG Timer Pins
This section describes the pins of the 16-bit PPG timer and provides a pin block
diagram.
■ 16-bit PPG timer pins
The pins of the 16-bit PPG timer are shared with the general-purpose ports. Table 13.3-1 lists
the functions of the pins, I/O format, and settings required to use the 16-bit PPG timer.
Table 13.3-1 16-bit PPG timer pins
Pin name
Pin function
I/O format
Pull-up option
P37/PPG0
Port 3 input-output /
PPG0 output
CMOS output /
CMOS input
Selectable
P40/PPG1
Port 4 input-output /
PPG1 output
P50/PPG2
Port 5 input-output /
PPG2 output
CMOS output /
CMOS hysteresis
input
Standby control
Settings required for pins
Setting for the PPG timer 0 output
(PNCTL0:POEN=1)
Available
Not provided
Setting for PPG timer 1 output
enable (PNCTL1:POEN=1)
Setting for PPG timer 2 output
enable (PNCTL2:POEN=1)
■ Block diagram of the 16-bit PPG timer pins
Resource output
Internal data bus
Port data register (PDR)
Resource input
Resource output enable
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 13.3-1 Block diagram of the 16-bit PPG timer 1 & 2 output pins
332
MB90820 series
RDR
Resource output
Port data register (PDR)
Resource output enable
Pull-up resistor
Internal data bus
About 50KΩ
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 13.3-2 Block diagram of the 16-bit PPG timer 0 pin
MB90820 series
333
13.4 16-bit PPG Timer Registers
PPG Down Counter Register (Upper)
Address: ch0 000039H
ch1 000041H
ch2 000049H
Read/write
Initial value
15
14
12
11
10
9
8
Bit number
PDCR0 ~ 2
DC15 DC14 DC13 DC12 DC11 DC10 DC09 DC08
R
1
R
1
R
1
R
1
R
1
R
1
R
1
R
1
7
6
5
4
3
2
1
PPG Down Counter Register (Lower)
Address: ch0 000038H
ch1 000040H
ch2 000048H
13
0
PDCR0 ~ 2
DC07 DC06 DC05 DC04 DC03 DC02 DC01 DC00
Read/write
Initial value
R
1
R
1
R
1
R
1
R
1
R
1
R
1
R
1
PPG Period Setting Buffer Register (Upper)
15
14
13
12
11
10
9
8
Address: ch0 00003BH
ch1 000043H
ch2 00004BH CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08
Read/write
Initial value
W
X
W
X
PPG Period Setting Buffer Register (Lower)
Address: ch0 00003AH
ch1 000042H
ch2 00004AH
7
W
X
W
X
W
X
W
X
W
X
W
X
6
5
4
3
2
1
Bit number
PCSR0 ~ 2
0
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
PPG Duty Setting Buffer Register (Upper)
15
14
13
12
11
10
9
8
Address: ch0 00003DH
ch1 000045H
ch2 00004DH DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08
Read/write
Initial value
W
X
PPG Duty Setting Buffer Register (Lower)
Address: ch0 00003C H
ch1 000044H
ch2 00004C H
Read/write
Initial value
334
Bit number
PCSR0 ~ 2
CS07 CS06 CS05 CS04 CS03 CS02 CS01 CS00
Read/write
Initial value
Bit number
W
X
W
X
W
X
W
X
W
X
W
X
W
X
7
6
5
4
3
2
1
Bit number
PDUT0 ~ 2
0
Bit number
PDUT0 ~ 2
DU07 DU06 DU05 DU04 DU03 DU02 DU01 DU00
W
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
MB90820 series
PPG Control Status Register (Upper)
15
Address: ch0 00003FH
ch1 000047H
ch2 00004FH
14
13
12
11
10
9
8
CKS1
CKS0 PGMS
Bit number
PCNTH0 ~ 2
CNTE STGR MDSE RTRG CKS2
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
3
2
IREN
IRQF
IRS1
IRS0
POEN OSEL
R/W
0
R/W
0
R/W
0
R/W
0
PPG Control Status Register (Lower)
7
Address: ch0 00003EH
ch1 000046H
ch2 00004EH
Read/write
Initial value
X
X
1
R/W
0
0
Bit number
PCNTL0 ~ 2
R/W
0
Figure 13.4-1 Registers of 16-bit PPG timer
MB90820 series
335
13.4 Registers of 16-bit PPG Timer
13.4.1 PPG Down Counter Register (PDCR0 ~ 2)
PPG down counter registers (PDCR0 ~ 2) are 16-bit registers, which are used to read
the count value of the 16-bit PPG down counter.
■ PPG down counter register (PDCR0 ~ 2)
PPG Down Counter Register (Upper)
Address: ch0 000039H
ch1 000041H
ch3 000049H
Read/write
Initial value
15
DC15
14
DC14
R
1
13
12
DC13 DC12
R
1
R
1
11
10
9
8
DC11
DC10
DC09
DC08
R
1
R
1
R
1
R
1
R
1
Bit number
PDCR0 ~ 2
PPG Down Counter Register (Lower)
Address: ch0 000038H
ch1 000040H
ch3 000048H
Read/write
Initial value
7
6
5
DC07
DC06
DC05 DC04
R
1
R
1
4
3
2
1
0
DC03
DC02
DC01
DC00
Bit number
PDCR0 ~ 2
R
1
R
1
R
1
R
1
R
1
R
1
Figure 13.4.1-1 PPG down counter register (PDCR0 ~ 2)
These are 16-bit registers that are used to store the values of the 16-bit down counter. The initial value
of them are all 1. Word access to these register are recommended. These registers are read-only.
336
MB90820 series
13.4 Registers of 16-bit PPG Timer
13.4.2 PPG Period Setting Buffer Register (PCSR0 ~ 2)
PPG period setting buffer register is used to set the period of the output pulses
generated by PPG.
PPG Period Setting Buffer Register (Upper)
Address: ch0 00003BH
ch1 000043H
ch3 00004BH
Read/write
Initial value
15
CS15
14
CS14
W
X
13
12
CS13 CS12
W
X
W
X
11
10
9
8
CS11
CS10
CS09
CS08
W
X
W
X
W
X
W
X
W
X
Bit number
PCSR0 ~ 2
PPG Period Setting Buffer Register (Lower)
Address: ch0 00003AH
ch1 000042H
ch3 00004AH
Read/write
Initial value
7
6
5
CS07
CS06
CS05 CS04
W
X
W
X
4
3
2
1
0
CS03
CS02
CS01
CS00
W
X
W
X
W
X
Bit number
PCSR0 ~ 2
W
X
W
X
W
X
Figure 13.4.2-1 PPG period setting buffer register (PCSR0 ~ 2)
These are 16-bit registers that are used to set the period of the output pulses generated by PPG. The
initial value of them are undetermined, so that these registers must be written before starting an
operation. Word access to these registers are recommended. These registers are write-only.
Data transfer from period setting buffer register to period setting register will be at counter borrow or
trigger or retrigger if enabled.
[Check]
In case of updating period setting buffer register, duty setting buffer register must be written after
writing to period setting buffer register. Only updating period setting buffer register is prohibited.
MB90820 series
337
13.4 Registers of 16-bit PPG Timer
13.4.3 PPG Duty Setting Buffer Register (PDUT0 ~ 2)
PPG duty setting buffer register is used to control the duty ratio of the output pulses
generated by PPG.
PPG Duty Setting Buffer Register (Upper)
Address: ch0 00003D H
ch1 000045H
ch3 00004D H
Read/write
Initial value
15
DU15
14
DU14
W
X
13
12
DU13 DU12
W
X
11
10
9
8
DU11
DU10
DU09
DU08
W
X
W
X
W
X
W
X
4
3
2
1
DU11
DU10
DU09
DU08
W
X
W
X
W
X
W
X
W
X
7
6
5
DU14
DU13 DU12
Bit number
PDUT0 ~ 2
PPG Duty Setting Buffer Register (Lower)
Address: ch0 00003CH
ch1 000044H
ch3 00004CH
Read/write
Initial value
0
Bit number
PDUT0 ~ 2
DU15
W
X
W
X
W
X
W
X
W
X
Figure 13.4.3-1 PPG duty setting buffer register (PDUT0 ~ 2)
These are 16-bit registers that are used to control the duty ratio of the output pulses generated by
PPG. The initial value of them are undetermined, so that these registers must be set a value before
starting an operation. Word access instruction to these registers are recommended. These registers
are write-only.
Data transfer from duty setting buffer register to duty setting register is at counter borrow or trigger or
retrigger if enabled.
Setting the same value in both the period setting register and duty setting register outputs all “H”s for
normal polarity and all “L”s for inverted polarity.
The output of the PPG is indeterminate if PCSR < PDUT.
[Check]
Duty setting buffer register can be written in the case of not updating period setting buffer register.
338
MB90820 series
Memo
MB90820 series
339
13.4 Registers of 16-bit PPG Timer
13.4.4 PPG Control Status Register (PCNTL0 ~ 2, PCNTH0 ~ 2)
PPG control status register is used to set operating conditions for 16-bit PPG timer
enable or disable operation, software trigger, retrigger control interrupt, output polarity
and check the status
■ PPG control status register, upper byte (PCNTH0 ~ 2)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
ch0: 00003FH
ch1: 000047H
ch2: 00004FH
CNTE
STGR
MDSE
RTRG
CKS2
CKS1
CKS0
PGMS
00000000 B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PGMS
PPG output mask enable bit
0
PPG output masking disabled
1
PPG output masking enabled
CKS2 CKS1 CKS0
Counter clock selection bits
0
0
0
φ (41.7 ns, φ = 24 MHz)
0
0
1
φ/2 (83.3 ns, φ = 24 MHz)
0
1
0
φ/4 (167 ns, φ = 24 MHz)
0
1
1
φ/8 (333 ns, φ = 24 MHz)
1
0
0
φ/16 (0.67 µs, φ = 24 MHz)
1
0
1
φ/32 (1.33 µs, φ = 24 MHz)
1
1
0
φ/64 (2.67 µs, φ = 24 MHz)
1
1
1
φ/128 (5.33 µs, φ = 24 MHz)
φ: Machine clock
RTRG
Retrigger enable bit
0
Retriggering disabled
1
Retriggering enabled
MDSE
Mode selection bit
0
PWM mode
1
Single-shot mode
Software trigger bit
STGR
write
0
No software trigger
1
Trigger the PPG by software
read
Always read “0”
CNTE
R/W : Read and Write
: Initial value
Timer enable bit
0
Stop the PPG timer
1
Enable the PPG timer
Figure 13.4.4-1 PPG0 ~ 2 control register (PCNTH0 ~ 2)
340
MB90820 series
Table 13.4.4-1 PPG control register (PCNTH0 ~ 2) bit
Bit name
bit15
CNTE:
Timer enable
bit
• This bit is used to enable the PPG timer operation.
• Writing “1” will enable the PPG operation and wait for trigger to
start PPG operation.
• Writing “0” will stop the operation.
bit14
STGR:
Software trigger
bit
• This bit is the software trigger bit for PPG.
• Writing “1” to this bit triggers the PPG by software.
• This bit is always read as “0”.
bit13
MDSE:
• When this bit is “0”, PPG operates in PWM mode.
Mode selection bit • When this bit is “1”, PPG operates in single-shot mode.
bit12
RTRG:
Retrigger enable
bit
• This bit is used to enable retriggering function of PPG during
operation.
• When this bit is “0”, retriggering function is disabled.
• When this bit is “1”, retriggering function is enabled.
CKS2,CKS1,
CKS0:
Counter clock
selection bits
• This bit are used to select the operation clock for 16-bit PPG
timer.
PGMS: PPG
output mask
enable bit
• This bit is used to mask the PPG output to specific level
regardless of the mode setting (PCNTH:MDSE), period setting
(PCSR) or duty setting (PDUT).
• Write “0” will disable PPG output masking function.
• Writing “1” to this bit masks the PPG output to always “L” when
polarity setting is “Normal” (PCNTL:OSEL=0).
• Writing “1” to this bit masks the PPG output to always “H”
when polarity setting is “Inverted” (PCNTL:OSEL=1).
Note: By setting period setting register (PCSR) and duty
setting register (PDUT) with same value, all “H” in
normal polarity or all “L” in inverted polarity can be
outputted when this bit is “1”.
bit11
bit10
bit9
bit8
MB90820 series
Function
341
■ PPG control status register, lower byte (PCNTL0 ~ 2)
Address
bit7
ch0: 00003EH
ch1: 000046H
ch2: 00004EH
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
IREN
IRQF
IRS1
IRS0
POEN
OSEL
XX000000B
R/W
R/W
R/W
R/W
R/W
R/W
OSEL
Output inversion bit
0
Normal polarity
1
Inverted polarity
POEN
Output enable bit
0
General-purpose I/O pin (P37/P40/P50)
1
PPG output pin (PPG0/PPG1/PPG2)
IRS1
IRS0
Interrupt type
0
0
Gate trigger (channel 0 only) / Software trigger /
Retigger
0
1
Counter borrow
1
0
PPG output rising in normal polarity or PPG output
falling in inverted polarity (duty match)
1
1
Counter borrow or PPG output rising in normal
polarity or PPG output falling in inverted polarity
PPG interrupt request flag
IRQF
R/W : Read and Write
-
: Not used
: Initial value
Read
Write
0
No PPG interrupt generated
Clear this bit
1
PPG interrupt generated
No effect
IREN
PPG interrupt request enable bit
0
Interrupt request disabled
1
Interrupt request enabled
Figure 13.4.4-2 PPG control register (PCNTL0 ~ 2)
342
MB90820 series
Table 13.4.4-2 PPG control register (PCNTL0 ~ 2)
Bit name
MB90820 series
Function
bit7
bit6
Unused bit
• This read value is indeterminate.
• Writing to this bit has no effect on the operation.
bit5
IREN:
PPG interrupt
request enable
bit
• This bit enable or disables PPG interrupt request to the CPU.
• When this bit and the interrupt flag (IRQF) bit are “1”, PPG
outputs an interrupt request.
bit4
IRQF:
PPG interrupt
flag bit
•
•
•
•
•
bit3
bit2
IRS1, IRS0:
Interrupt
selection bit
• These bits are used to select interrupt condition of the PPG
timer.
bit1
POEN:
Output
enable bit
• This bit enables or disables output from the PPG output pin.
• When this bit is “0”, the pin functions as a general purpose port.
• When this bit is “1”, the pin functions as a PPG timer output pin.
bit0
OSEL:
Output
inversion bit
• This bit selects the polarity of PPG output pin.
• When this bit is “0”, normal polarity is selected. PPG outputs “L”
when 16-bit down count vlaue is greater than PDUT, and
outputs “H” when smaller than or equals to PDUT.
• When this bit is “1”, the PPG output is inverted.
This bit is set to 1 when PPG interrupt occurs.
Writing 0 will clear this bit.
Writing 1 has no effect.
In read-modify-write operation, “1” is always read.
This bit is also cleared when EI2OS is activated.
343
13.5 16-bit PPG Timer Interrupts
The 16-bit PPG timer is enabled to generate an interrupt request when trigger or
counter borrow or PPG rising in normal polarity or PPG falling in inverted polarity
depanding on PCNTL=IRS1, IRS0 setting. It is also coordinated with the extended
intelligent I/O service (EI2OS).
■ 16-bit PPG timer interrupts
Table 13.5-1 list the interrupt control bits and interrupt causes of the 16-bit PPG timer.
Table 13.5-1 Interrupt control bits and interrupt causes of the 16-bit PPG timer
Interrupt flag bit
Interrupt request
enable bit
Interrupt type
selection bit
Interrupt cause
16-bit PPG timer 0
PCNTL0:IRQF
16-bit PPG timer 1
PCNTL1:IRQF
16-bit PPG timer 2
PCNTL2:IRQF
PCNTL0:IREN
PCNTL1:IREN
PCNTL2:IREN
PCNTL0:IRS1,0
PCNTL1:IRS1,0
PCNTL2:IRS1,0
PCNTL0:IRS1,0=”00”
gate trigger/software
trigger/retrigger of 16bit down counter (ch0)
PCNTL0:IRS1,0=”01”
counter borrow of 16bit down counter (ch0)
PCNTL0:IRS1,0=”10”
PPG0 output rising in
normal polarity or
PPG0 output falling in
inverted polarity
PCNTL0:IRS1,0=”11”
Counter borrow of 16bit down counter (ch0)
or PPG0 output rising
in normal polarity or
PPG0 output falling in
inverted polarity
PCNTL1:IRS1,0=”00”
software trigger/
retrigger of 16-bit
down counter (ch1)
PCNTL1:IRS1,0=”01”
counter borrow of 16bit down counter (ch1)
PCNTL1:IRS1,0=”10”
PPG1 output rising in
normal polarity or
PPG1 output falling in
inverted polarity
PCNTL0:IRS1,0=”11”
Counter borrow of 16bit down counter (ch1)
or PPG1 output rising
in normal polarity or
PPG1 output falling in
inverted polarity
PCNTL2:IRS1,0=”00”
software trigger/
retrigger of 16-bit
down counter (ch2)
PCNTL2:IRS1,0=”01”
counter borrow of 16bit down counter (ch2)
PCNTL2:IRS1,0=”10”
PPG2 output rising in
normal polarity or
PPG2 output falling in
inverted polarity
PCNTL0:IRS1,0=”11”
Counter borrow of 16bit down counter (ch2)
or PPG2 output rising
in normal polarity or
PPG2 output falling in
inverted polarity
In the 16-bit PPG timer, the IRQF bit of the PPG control status register (PCNTL) is set to 1 and an
interrupt request is enabled (PCNTL: IREN=1), the interrupt request is outputted to the interrupt
controller.
344
MB90820 series
■ 16-bit PPG timer interrupts and EI2OS
Table 13.5-2 lists the 16-bit PPG timer interrupts and EI2OS.
Table 13.5-2 16-bit PPG timer interrupts and EI2OS
Interrupt control register
Channel
16-bit PPG
timer 0*1
16-bit PPG
timer 1*2
16-bit PPG
timer 2*3
Interrupt
number
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
#14 (0EH)
ICR01
0000B1H
FFFFC4H
FFFFC5H
FFFFC6H
#16 (10H )
ICR02
0000B2H
FFFFBCH
FFFFBDH
FFFFBE H
#32 (20H )
ICR10
0000BAH
FFFF7CH
FFFF7DH
FFFF7EH
O
*1: The same interrupt control register as that for 16-bit PPG timer 0 is assigned to PWC timer 0.
*2: The same interrupt control register as that for 16-bit PPG timer 1 is assigned to 16-bit output compare channel 1 match.
*3: The same interrupt control register as that for 16-bit PPG timer 2 is assigned to 16-bit free-running timer zero detect.
■ EI2OS function of the 16-bit PPG timer
Since the 16-bit PPG timer has a circuit that coordinates with EI2OS, the counter can start EI2OS when
PPG interrupt occurs.
However, EI2OS is available only when other peripheral functions sharing the interrupt control register
(ICR) do not use interrupts . For example, when 16-bit PPG timer 0 uses EI2OS, interrupts of the output
compare channel 0 match must be disabled.
MB90820 series
345
13.6 Operation of 16-bit PPG Timer
The 16-bit PPG Timer operates in either PWM mode or single shot mode. And
Retriggering can be enabled.
■ PWM mode (PCNTL: MDSE = 0)
For PWM opertion, the 16-bit down counter will be loaded with PCSR value, starts counting after
a valid trigger is detected. And once the 16-bit down counter reached zero, it is reloaded with
PCSR value and repeat counting again. PPG output is toggled when 16-bit down counter is
reloaded. The period of the output pulses can be controlled by setting PCSR and the duty ratio
controlled by setting PDUT.
a) Retriggering is disabled (PCNTH: RTRG = 0)
Counter value
m
n
0
Time
Rising edge detected
Trigger is ignored
Software trigger
PPG
(normal polarity)
(inverted polarity)
(1)
(2)
T: Count clock period
m: PCSR value
n: PDUT value
Figure 13.6-1 Retriggering is disabled in PWM mode
(1) = (n+1)*T ns
(2) = (m+1)*T ns
346
MB90820 series
b) Retriggering is enabled (PCNTH: RTRG = 1)
Counter value
m
n
Time
0
Rising edge detected
Restarted by trigger
Software trigger
PPG
(normal polarity)
PPG
(inverted polarity)
(1)
(2)
T: Count clock period
m: PCSR value
n: PDUT value
(1) = (n+1)*T ns
(2) = (m+1)*T ns
Figure 13.6-2 Retriggering is enabled in PWM mode
■ Single-shot mode (PCNTL: MDSE = 1)
For single-shot opertion, a single pulse of specified width can be output by a valid trigger. When
retriggering is enabled, the counter is reloaded if an edge is detected during operation.
a) Retriggering is disabled (PCNTH: RTRG = 0)
Counter value
m
n
Time
0
Rising edge detected
Trigger is ignored
Software trigger
PPG
(normal polarity)
PPG
(inverted polarity)
(1)
(2)
T: Count clock period
m: PCSR value
n: PDUT value
Figure 13.6-3 Retriggering is disabled in single-shot mode
(1) = (n+1)*T ns
(2) = (m+1)*T ns
MB90820 series
347
b) Retriggering is enabled (PCNTH: RTRG = 1)
Counter value
m
n
Time
0
Software trigger
Rising edge detected
Restarted by trigger
PPG
(normal polarity)
PPG
(inverted polarity)
(1)
(2)
(1) = (n+1)*T ns
(2) = (m+1)*T ns
T: Count clock period
m: PCSR value
n: PDUT value
Figure 13.6-4 Retriggering is enabled in single-shot mode
■ Gate trigger (PPG channel 0 only)
When gate trigger is used, PPG starts operation when rising edge of gate trigger is detected and stops
when falling is detected. In next rising edge, PPG restarts operation again.
Counter value
m
n
0
Time
Rising edge detected
Falling edge detected
Gate trigger
PPG
(normal polarity)
(inverted polarity)
(1)
(2)
(1) = (n+1)*T ns
(2) = (m+1)*T ns
T: Count clock period
m: PCSR value
n: PDUT value
Figure 13.6-5 Gate trigger in PWM mode when retriggering is enable
■ PPG interrupts
There are four types of interrupts sharing one interrupt flag (PCNTL:IRQF) selected by interrupt type
bits (PCNTL:IRS1~0).
348
•
Gate trigger (for PPG channel 0 only) or software trigger or retrigger
•
•
Counter borrow
Duty match occurs when PPG output rising in normal polarity or PPG output falling in inverted
MB90820 series
•
polarity
Counter borrow or duty match
Software trigger
Load
Count clock
Counter value
0002H
0001H
0000H
0002H
PPG output
(normal polarity)
Interrupt
(by software trigger)
Interrupt
(by duty match)
Interrupt
(by counter borrow)
Figure 13.6-6 PPG interrupt timing
MB90820 series
349
13.7 Usage Notes on the 16-bit PPG Timer
Notes on using the 16-bit PPG timer are given below.
■ Usage notes on the 16-bit PPG timer
● Notes on using a program for setting
•
•
•
Write a value to the period setting buffer register (PCSR), duty setting buffer register (PDUT)
must be written after writing to PCSR. Only updating PCSR is prohibited. Be sure to use a
word transfer instruction (MOVW A, dir, etc.) to access PCSR and PDUT.
Always set the value of duty setting buffer register (PDUT) not greater than period setting
buffer register (PCSR), otherwise the output of PPG is indeterminate.
Change the CKS2, CKS1 and CKS0 bits of the control status register (PCNTH) when the
PPG is stopped (PCNTH: CNTE=0).
● Notes about interrupts
•
When the IRQF bit of the PPG control status register (PCNTL) is set to 1 and an interrupt
request is enabled (PCNTL: IREN = 1), control cannot be returned from interrupt processing.
Always clear the IRQF bit.
•
Since the 16-bit PPG timer shares an interrupt vector with other resource, interrupt causes
must be checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the 16-bit PPG timer, shared resource interrupts must be
disabled.
350
MB90820 series
Memo
MB90820 series
351
13.8 Sample Programs for the 16-bit PPG Timer
This section contains sample programs for the 16-bit PPG timer.
■ Sample program for the 16-bit PPG timer
● Processing
•
An output in 160 KHz with 60% duty is generated with 16-bit PPG timer 0.
•
The timer is used in PWM mode to repeatedly generate an interrupt.
•
The timer is started with a software trigger.
•
EI2OS is not used.
•
24 MHz is used for the machine clock, and 41.7 ns is used for the count clock.
● Coding example
ICR01
EQU
0000B1H
; Interrupt control register for the 16-bit PPG timer
PCSR0 EQU
00003AH
; PPG period setting register
PDUT0 EQU
00003CH
; PPG duty setting register
PCNT0 EQU
00003EH
; PPG control status register
IRQF
EQU
PCNT0:4
; Interrupt request flag bit
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
; Assumes that stack pointer (SP) has already been
initialized
AND
CCR,#0BFH
; Interrupt disable
MOV
I:ICR01,#00H
; Interrupt level 0 (strongest)
MOVW I:PCSR0,#0063H
; Sets the period of the PPG output
MOVW I:PDUT0,#003BH
; Sets the duty ratio of the PPG output
MOVW I:PCNT0,#01100000000100110B
; Enables PPG output in normal polarity
; Enables 16-bit PPG timer, and 41.7 ns clock
; Software triggers PPG
; Select PWM mode and enable interrupt
; Clears interrupt flag, and starts counter
MOV
ILM,#07H
; Sets ILM in PS to level 7
OR
CCR,#40H
; Interrupt enable
LOOP:
MOV
A,#00H
; Endless loop
MOV
A,#01H
;
BRA
LOOP
;
;-------Interrupt program-------------------------------------------------------------------------------------------WARI:
CLRB I:IRQF
; Clears interrupt request flag
;
:
;
User processing
;
:
352
MB90820 series
RETI
; Returns from interrupt
CODE
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG
0FFC4H
; Sets vector for interrupt #14 (0EH)
DSL
WARI
ORG
0FFDCH
; Sets reset vector
DSL
START
DB
00H
; Sets single-chip mode
VECT
ENDS
END
START
MB90820 series
353
354
MB90820 series
CHAPTER 14
MULTI-FUNCTIONAL TIMER
This chapter describes the functions and operation of the multi-functional timer.
14.1 Overview of Multi-functional Timer
14.2 Block Diagram of Multi-functional Timer
14.3 Multi-functional Timer Pins
14.4 Registers of Multi-functional Timer
14.5 Multi-functional Timer Interrupts
14.6 Operation of Multi-functional Timer
14.7 Usage Notes on the Multi-functional Timer
14.8 Sample Programs for the Multi-functional Timer
MB90820 series
355
14.1 Overview of Multi-functional Timer
The multi-functional timer consists of a 16-bit free-running timer, six 16-bit output
compare, four 16-bit input capture, 1 channel of 16-bit PPG timer and a waveform
generator. By using this waveform generator, 12 independent waveform can be
outputted through 16-bit free-running timer. Furthermore input pulse width
measurement and external clock cycle measurement can be done.
■ 16-bit free-running timer (x 1)
•
•
•
•
•
•
■ 16-bit output
The 16-bit free-running timer consists of a 16-bit up/up-down counter, control register, 16-bit
compare clear register (with buffer register) and a prescaler.
8 types of counter operation clock (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128) can be selected (φ
is the machine clock).
Compare clear interrupt is generated when there is a compare match with compare clear
register and 16-bit free-running timer. Zero detection interrupt is generated while 16-bit freerunning timer is detected as zero in count value.
The compare clear register has a selectable buffer register, into which data is written for
transfer to the compare clear register. When the timer is stopped, transfer occurs immediately
when the data is written to the buffer. When the timer is operation, data transfer from the
buffer occurs when the timer value is detected to be zero.
Reset, software clear, compare match with compare clear register in up-count mode will reset
the counter value to “0000H”.
The output value of this counter can be used as the count clock of the output compares and
input captures in multi-functional timer.
compare (x 6)
•
The output compare consists of six 16-bit compare registers (with selectable buffer register),
compare output latch and compare control registers. An interrupt is generated and output
level is inverted when the value of 16-bit free-running timer and compare register are
matched.
• 6 compare registers can be operated independently.
Output pins and interrupt flag are corresponding to each compare register.
• 2 compare registers can be paired to control the output pins.
Inverts output pins by using 2 compare registers together.
• Setting the initial value for each output pin is possible.
• An interrupt is generated when output compare register is matched with 16-bit free-running
timer.
■ 16-bit input capture (x 4)
Input capture consists of 4 independent external input pins, the corresponding capture register
and capture control register. By detecting any edge of the input signal from the external pin, the
value of the 16-bit free-running timer can be stored in the capture register and an interrupt is
generated simultaneously.
•
•
•
•
•
356
3 types of trigger edge (rising edge, falling edge and both edge) of the external input signal
can be selected and there is indication bit to show the trigger edge is rising or falling.
4 input captures can be operated independently.
An interrupt is generated by detecting a valid edge from external input.
Channel 0 and 1 share interrupt #33.
Channel 2 and 3 share interrupt #35.
MB90820 series
■ 16-bit PPG timer (x 1)
The 16-bit PPG timer 0 is used to provide a PPG signal for waveform generator. The detail of
16-bit PPG timer 0 is described in Chapter 13.
■ Waveform generator
The waveform generator consists of three 16-bit timer registers, three timer control registers and
16-bit waveform control register.
With waveform generator, it is possible to generate realtime output, 16-bit PPG waveform output,
non-overlap 3-phase waveform output for inverter control and DC chopper waveform output.
•
•
It is possible to generate a non-overlap waveform output based on dead-time of 16-bit timer.
(Dead-time timer function)
It is possible to generate a non-overlap waveform output when realtime output is operated in
2-channel mode. (Dead-time timer function)
By detecting realtime output compare match, GATE signal of the PPG timer operation will be
generated to start or stop PPG timer operation. (GATE function)
When a match is detected by realtime output compare, the 16-bit timer is activated. The PPG
timer can be started or stopped easily by generating a GATE signal for PPG operation until
the 16-bit timer stops. (GATE function)
Forced stop control using DTTI pin input
MB90820 series
357
•
•
•
14.2 Block Diagram of Multi-functional Timer
The block diagram of the multi-functional timer will be described in the following
sections.
■ Block diagram of multi-functional timer
Real time I/O
16-bit output
compare
Interrupt #12
Interrupt #15
Interrupt #17
Interrupt #19
Interrupt #21
Interrupt #23
Output compare 0
Output compare 1
Output compare 2
Output compare 3
Output compare 4
Output compare 5
RT0 ~ 5
F2MC-16LX bus
P82/RTO0 (U)
RTO1
Pin
P83/RTO1 (X)
RTO2
Pin
P84/RTO2 (V)
RTO3
Pin
P85/RTO3 (Y)
RTO4
Pin
P86/RTO4 (W)
RTO5
Pin
P87/RTO5 (Z)
DTTI
Pin
P10/INT0/DTTI
Counter value
Interrupt #31
Interrupt #34
16-bit freerunning
timer
A/D trigger
Zero detect
Compare clear
Interrupt #29
16-bit timer 0/1/2
underflow
Interrupt #20
DTTI falling edge detect
A/D trigger
EXCK
Counter value
Pin
RT0 ~5
Waveform
generator
Buffer transfer
RTO0
PPG0
GATE
GATE
Pin
P75/FRCK/AN13
IN0
Pin
P76/IN0/AN14
IN1
Pin
P77/IN1/AN15
IN2
Pin
P80/IN2
IN3
Pin
P81/IN3
Interrupt #33
Interrupt #35
16-bit input
capture
PPG0
Input capture 0/1
Input capture 2/3
Figure 14.2-1 Block diagram of multi-functional timer
358
MB90820 series
■ Block diagram of 16-bit free-running timer
φ
STOP
STOP
MODE
SCLR
UP/UP-DOWN
CLK2
CLK1
CLK0
Prescaler
CLR
Zero detect
circuit
16-bit free-running
timer
Zero detect (to output compare)
CK
To input capture &
output compare
transfer
F2MC-16LX bus
16-bit compare
clear register
Compare circuit
Compare clear match (to output compare)
16-bit compare clear
buffer register
I0
I1
O
Interrupt #31 (1FH)
I1
O
Selector
I0
Selector
I0
I1
O
Interrupt #34 (22H)
Selector
Mask circuit
A/D trigger
MSI2
MSI1
MSI0
ICLR
ICRE
IRQZF
IRQZE
I0
I1
O
Selector
Figure 14.2-2 Block diagram of 16-bit free-running timer
MB90820 series
359
■ Block diagram of 16-bit output compare
Count value from free-running timer
BTS0
BUF0
Compare buffer register 0/2/4
O
Compare register 0/2/4
F2MC-16LX bus
Zero detect from
free-running timer
Compare clear match from
free-running timer
I0
transfer
I1
Selector
BUF1
BTS1
Compare circuit
I0
O
Compare buffer register 1/3/5
Selector
transfer
Compare register 1/3/5
I1
CMOD
Compare circuit
IOP1
IOP0
IOE1
T
Q
RT0/2/4
(Waveform
generator)
T
Q
RT1/3/5
(Waveform
generator)
IOE0
Interrupt
#12, #17, #21
#15, #19, #23
Figure 14.2-3 Block diagram of 16-bit output compare
■ Block diagram of 16-bit input capture
Count value from free-running timer
F2MC-16LX bus
IN0/2
Edge detect
Capture register 0/2
EG11
EG10 EG01 EG00
Edge detect
Capture register 1/3
ICP0
ICP1
ICE0
IEI1
IEI0
IN1/3
ICE1
Interrupt
#33, #35
#33, #35
Figure 14.2-4 Block diagram of 16-bit input capture
360
MB90820 series
■ Block diagram of waveform generator
DCK2 DCK1 DCK0 NRSL DTIF DTIE NWS1 NWS0
φ
DTTI control circuit
Divider
PICSH01
DTCR0 TMD2
TMD1
TMD0
SIGCR
Noise cancellation
DTTI
PGEN1 PGEN0
GTEN1 GTEN0
GATE 0/1
GATE
(to PPG0)
TO0
Waveform control
RT0
Selector
16-bit timer 0
Compare circuit
Selector
Output control
TO1
RT1
RTO1 (X)
U
16-bit timer register 0
RTO0 (U)
Dead time generator
X
DTCR1 TMD2
TMD1
TMD0
F2MC-16LX bus
PICSH01
GTEN1 GTEN0
GATE 2/3
PGEN3 PGEN2
TO2
Waveform control
RT2
Selector
16-bit timer 1
Compare circuit
Selector
Output control
TO3
RT3
RTO3 (Y)
V
16-bit timer register 1
RTO2 (V)
Dead time generator
Y
DTCR2 TMD2
TMD1
TMD0
GTEN1 GTEN0
GATE 4/5
PICSH01 PGEN5 PGEN4
TO4
Waveform control
RT4
Selector
16-bit timer 2
Compare circuit
Selector
W
16-bit timer register 2
Output control
TO5
RT5
RTO4 (W)
RTO5 (Z)
Dead time generator
PPG0
Z
Figure 14.2-5 Waveform generator block diagram
MB90820 series
361
14.3 Multi-functional Timer Pins
This section describes the pins of the multi-functional timer and provides a pin block
diagram.
■ Multi-functional timer pins
Table 14.3-1 Multi-functional timer pins
362
Pin Name
Pin function
I/O format
Pull-up option
Standby control
P10/INT0/
DTTI
Port 1 input-output/
external interrupt
input/DTTI
P75/FRCK/
AN13
Port 7 input-output/
external clock
Set the pin as an input port
(DDR7:bit 13 = 0)
P76/IN0/AN14
Port 7 input-output/
input capture 0
Set the pin as an input port
(DDR7:bit 14 = 0)
P77/IN1/AN15
Port 7 input-output/
input capture 1
Set the pin as an input port
(DDR7:bit 15 = 0)
P80/IN2
Port 8 input-output/
input capture 2
Set the pin as an input port
(DDR8:bit 0 = 0)
P81/IN3
Port 8 input-output/
input capture 3
Set the pin as an input port
(DDR1:bit 8 = 0)
Selectable
CMOS output/
CMOS
hysteresis
input
Setting required for pins
Provided
Set the pin as an input port
(DDR8:bit 1 = 0)
P82/RTO0 (U)
Port 8 input-output/
RTO0
P83/RTO1 (X)
Port 8 input-output/
RTO1
Set RTO1 output
(OCS1:OTE1 = 1)
P84/RTO2 (V)
Port 8 input-output/
RTO2
Set RTO2 output
(OCS3:OTE0 = 1)
P85/RTO3 (Y)
Port 8 input-output/
RTO3
Set RTO3 output
(OCS3:OTE1 = 1)
P86/RTO4 (W)
Port 8 input-output/
RTO4
Set RTO4 output
(OCS5:OTE0 = 1)
P87/RTO5 (Z)
Port 8 input-output/
RTO5
Set RTO5 output
(OCS5:OTE1 = 1)
Not provided
Set RTO0 output
(OCS1:OTE0 = 1)
MB90820 series
■ Block diagram of multi-functional timer pins
RDR
Resource input
Port data register (PDR)
Pull-up resistor
Internal data bus
About 50KΩ
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
External
interrupt
enable
DDR read
Standby control (SPL=1)
Figure 14.3-1 Block diagram of P10/INT0/DTTI
AD converter input
AD converter channel selection bit
Resource input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
Figure 14.3-2 Block diagram of P75/FRCK/AN13 ~ P77/IN1/AN15
MB90820 series
363
Resource input
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 14.3-3 Block diagram of P80/IN2 ~ P81/IN3
Resource output
Internal data bus
Port data register (PDR)
Resource input
Resource output enable
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 14.3-4 Block diagram of P82/RTO0 ~ P87/RTO5
364
MB90820 series
14.4 Registers of Multi-functional Timer
This section describes registers of multi-functional timer.
■ 16-bit free-running timer registers
Compare Clear Buffer Register / Compare Clear Register (Upper)
Address: 00005BH
Read/write
Initial value
15
14
13
12
11
10
9
8
Bit number
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
1
0
CPCLRB/CPCLR
Compare Clear Buffer Register / Compare Clear Register (Lower)
7
6
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
11
10
9
8
Address: 00005DH
T15
T14
T13
T12
T11
T10
T09
T08
Read/write
Initial value
R/W
0
R/W
0
Address: 00005AH
Read/write
Initial value
5
4
3
2
Bit number
CPCLRB/CPCLR
Timer Data Register (Upper)
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
T01
T00
Bit number
TCDT
Timer Data Register (Lower)
7
6
5
4
Address: 00005C H
T07
T06
T05
T04
T03
T02
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
12
11
10
MSI2
MSI1
MSI0
R/W
0
R/W
0
R/W
0
6
5
4
3
BFE
STOP
R/W
0
R/W
1
R/W
0
R/W
0
Bit number
TCDT
R/W
0
Timer Control Status Register (Upper)
15
Address: 00005FH
Read/write
Initial value
14
13
ECKE IRQZF IRQZE
R/W
0
R/W
0
9
8
Bit number
ICLR
ICRE
TCCSH
R/W
0
R/W
0
R/W
0
2
1
0
CLK2
CLK1
CLK0
R/W
0
R/W
0
R/W
0
Timer Control Status Register (Lower)
7
Address: 00005E H
Read/write
Initial value
X
MODE SCLR
R/W
0
R/W
0
Bit number
TCCSL
Figure 14.4-1 Registers of 16-bit free-running timer
MB90820 series
365
■ 16-bit output compare registers
Output Compare Buffer Register / Output Compare Register (Upper)
Address: ch0 000071H
ch1 000073H
ch2 000075H
ch3 000077H
ch4 000079H
ch5 00007BH
Read/write
Initial value
15
OP15
R/W
X
14
13
12
11
10
9
8
OP14
OP13
OP12
OP11
OP10
OP09
OP08
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Bit number
OCCPB0 ~ 5/
OCCP0 ~ 5
Output Compare Buffer Register / Output Compare Register (Lower)
Address: ch0 000070H
ch1 000072H
ch2 000074H
ch3 000076H
ch4 000078H
ch5 00007AH
Read/write
Initial value
7
6
5
4
3
OP07
OP06
OP05
OP04
OP03 OP02
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
2
1
OP01
OP00
R/W
X
0
R/W
X
R/W
X
9
8
Bit number
OCCPB0 ~ 5/
OCCP0 ~ 5
Compare Control Register (Upper)
15
Address: ch1 00007DH
ch3 00007FH
ch5 000081H
Read/write
Initial value
14
13
12
11
10
BTS1 BTS0 CMOD OTE1 OTE0
R/W
1
X
R/W
1
R/W
0
Bit number
OCS1/3/5
OTD1 OTD0
R/W
0
R/W
0
R/W
0
2
R/W
0
Compare Control Register (Lower)
Address: ch0 00007C H
ch2 00007EH
ch4 000080H
Read/write
Initial value
7
6
5
4
3
1
IOP0
IOE1
IOE0
BUF1
BUF0 CST1
0
Bit number
OCS0/2/4
IOP1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
0
CST0
R/W
0
Figure 14.4-2 Registers of output compare
366
MB90820 series
■ Input capture registers
Input Capture Data Register (Upper)
Address: ch0 000061H
ch1 000063H
ch2 000065H
ch3 000067H
Read/write
Initial value
15
CP15
14
CP14
12
11
10
9
Bit number
8
CP13
CP12
CP11
CP10
CP09
CP08
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
13
IPCP0 ~ 3
Input Capture Data Register (Lower)
Address: ch0 000060H
ch1 000062H
ch2 000064H
ch3 000066H
7
6
5
4
3
2
1
0
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
R
X
R
X
R
X
Bit number
IPCP0 ~ 3
Read/write
Initial value
R
X
R
X
R
X
12
11
10
R
X
R
X
Input Capture Control Status Register (2/3) (Upper)
15
14
13
Address: 00006BH
Read/write
Initial value
8
IEI3
IEI2
Bit number
ICSH23
X
X
X
R
0
R
0
5
4
3
2
1
0
ICP2
ICE3
ICE2
EG31
EG30
EG21
EG20
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
9
8
Bit number
IEI1
IEI0
PICSH01
X
X
9
X
Input Capture Control Status Register (2/3) (Lower)
7
Address: 00006AH
Read/write
Initial value
ICP3
R/W
0
6
PPG output control/ Input Capture Control Status Register (0/1) (Upper)
15
14
13
12
11
10
Address: 000069H
Read/write
Initial value
PGEN5 PGEN4 PGEN3 PGEN2 PGEN1 PGEN0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
R
0
5
4
3
2
1
0
Bit number
ICSL23
Input Capture Control Register (0/1)
Address: 000068H
Read/write
Initial value
7
6
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
PICSL01
Figure 14.4-3 Registers of 16-bit input capture
MB90820 series
367
■ Waveform generator registers
16-bit Timer Register (Upper)
Address: ch0 000051H
ch1 000053H
ch2 000055H
15
14
13
12
11
10
9
8
TR15
TR14
TR13
TR12
TR11
TR10
TR09
TR08
R/W
X
R/W
X
Bit number
TMRR0/1/2
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
16-bit Timer Register (Lower)
Address: ch0 000050H
ch1 000052H
ch2 000054H
7
6
5
4
3
2
1
0
TR07
TR06
TR05
TR04
TR03
TR02
TR01
TR00
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
14
13
12
11
10
Bit number
TMRR0/1/2
Read/write
Initial value
R/W
X
R/W
X
16-bit Timer Control Register
15
Address: ch1 000057H
Read/write
Initial value
9
8
Bit number
DTCR1
DMOD GTEN1 GTEN0 TMIF
R/W
0
R/W
0
R/W
0
TMIE
R/W
0
TMD2 TMD1 TMD0
R/W
0
R/W
0
R/W
0
R/W
0
16-bit Timer Control Register
7
Address: ch0 000056H
ch2 000058H
Read/write
Initial value
6
5
4
DMOD GTEN1 GTEN0 TMIF
3
TMIE
2
1
0
TMD2 TMD1 TMD0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
DTIE
DTIF
NRSL
DCK2
DCK1
DCK0 NWS1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
DTCR0/2
R/W
0
Waveform Control Register
Address: 000059H
Read/write
Initial value
10
9
R/W
0
8
NWS0
Bit number
SIGCR
R/W
0
Figure 14.4-4 Registers of waveform generator
368
MB90820 series
14.4
Registers of Multi-functional Timer
14.4.1 Compare Clear Buffer Register (CPCLRB) and Compare
Clear Register (CPCLR)
Compare clear buffer register (CPCLRB) is a 16-bit buffer register of compare clear
register (CPCLR). Both CPCLRB and CPCLR registers are located in the same address.
■ Compare clear buffer register (CPCLRB)
Compare Clear Buffer Register (Upper)
15
14
Address: 00005B H
Read/write
Initial value
13
12
11
10
9
8
Bit number
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
W
1
W
1
W
1
W
1
W
1
W
1
W
1
W
1
5
4
3
2
1
0
CPCLRB
Compare Clear Buffer Register (Lower)
Address: 00005AH
7
6
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
W
1
W
1
W
1
W
1
W
1
W
1
W
1
W
1
Read/write
Initial value
Bit number
CPCLRB
Figure 14.4.1-1 Compare clear buffer register (CPCLRB)
Compare Clear Buffer Register is the buffer register for Compare Clear Register. When buffer function
is disabled (TCCSL:BFE=0) or when free-running timer is stopped, value in Compare clear buffer
register is transferred to Compare clear register immediately. When buffer function is enabled, value is
transferred when the count value of 16-bit free-running timer is detected as zero.
Word access to this register is recommended.
■ Compare clear register (CPCLR)
Compare Clear Register (Upper)
Address: 00005BH
Read/write
Initial value
15
14
13
12
11
10
9
8
Bit number
CL15
CL14
CL13
CL12
CL11
CL10
CL09
CL08
R
1
R
1
R
1
R
1
R
1
R
1
R
1
R
1
4
3
CPCLR
Compare Clear Register (Lower)
Address: 00005AH
Read/write
Initial value
7
6
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
R
1
R
1
R
1
R
1
R
1
R
1
R
1
R
1
5
2
1
0
Bit number
CPCLR
Figure 14.4.1-2 Compare clear register (CPCLR)
The Compare Clear Register is used to compare with the count value of the 16-bit free-running timer.
In up-count mode, when this register is matched with the count value of 16-bit free-running timer, timer
will be reset to “0000H”. In up-down count mode, when this register is matched with the count value of
the 16-bit free-running timer, the timer changes from up-count to down-count and changes from downcount to up-count at zero detect.
Word access to this register is recommended.
MB90820 series
369
14.4
Registers of Multi-functional Timer
14.4.2 Timer Data Register (TCDT)
The timer data register (TCDT) is used to read the count value of 16-bit free-running
timer.
■ Timer data register (TCDT)
Timer Data Register (Upper)
15
14
13
12
11
10
Address: 00005DH
T15
T14
T13
T12
T11
T10
Read/write
Initial value
R/W
0
R/W
0
9
8
T09
T08
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
T01
T00
Bit number
TCDT
Timer Data Register (Lower)
7
6
5
4
Address: 00005CH
T07
T06
T05
T04
T03
T02
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
TCDT
R/W
0
Figure 14.4.2-1 Timer data register
The timer data register is used to read the count value of the 16-bit free-running timer. The
counter value is cleared to “0000H” upon a reset. The timer value can be set by writing a value to
this register. However, ensure that the value is written while the operation is stopped (STOP =
1). Word access instruction to the timer data register is recommended.
The 16-bit free-running timer is initialized upon the following factors:
•
•
•
370
Reset
Clear bit (SCLR) of control status register
A match between compare clear register and the timer counter value in up-count mode
(TCCSL:MODE=0)
MB90820 series
Memo
MB90820 series
371
14.4
Registers of Multi-functional Timer
14.4.3 Timer Control Status Register (TCCSH, TCCSL)
The timer control status register (TCCS) is a 16-bit register and used to control the
operation of 16-bit free-running timer.
■ Timer control status register, upper byte (TCCSH)
Address bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8 Initial value
00005FH ECKE IRQZFIRQZE MSI2 MSI1 MSI0 ICLR ICRE 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ICRE
Compare clear interrupt request enable bit
0
Disable interrupt request
1
Enable interrupt request
Compare clear interrupt flag bit
ICLR
Read
Write
0
No compare-clear match
Clear this bit
1
Compare-clear match
No effect
MSI2 MSI1 MSI0
Interrupt masking selection bits
0
0
0
Interrupt is generated when 1st match
0
0
1
Interrupt is generated when 2nd match
0
1
0
Interrupt is generated when 3rd match
0
1
1
Interrupt is generated when 4th match
1
0
0
Interrupt is generated when 5th match
1
0
1
Interrupt is generated when 6th match
1
1
0
Interrupt is generated when 7th match
1
1
1
Interrupt is generated when 8th match
IRQZE
Zero detect interrupt request enable bit
0
Disable interrupt request
1
Enable interrupt request
Zero detect interrupt flag bit
IRQZF
Read
Write
0
No zero detect
Clear this bit
1
Zero detect
No effect
ECKE
Clock selection bit
0
Internal clock
1
External clock
R/W : Read and Write
: Initial value
Figure 14.4.3-1 Timer control status register (TCCSH)
372
MB90820 series
Table 14.4.3-1 Timer control status register (TCCSH)
Bit name
ECKE:
Clock selection
bit
• This bit is used to select internal or external clock as count clock for
16-bit free-running timer.
• Writing “0” selects internal clock. The clock frequency selection bits
(CK2~0) should also be set to select the count clock frequency.
• Writing “1” selects external clock. External clock is input from pin “P75/
FRCK/AN13”, so DDR1:7 should be set as “0” to enable external clock
input.
Note: The count clock is changed immediately after this bit is set.
So change this bit while the output compare and input
capture units are stopped.
bit 14
IRQZF:
Zero detect
interrupt flag bit
• This bit is an interrupt flag for zero detect.
• When the count value of 16-bit free-running timer is 0000H, this bit is
set to “1”.
• Writing “0” will clear this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
Note: In software clear, (writing TCCSL:SCLR “1”) will not set this
bit.
Note: In up-down count mode (MODE=1) and interrupt mask
function is selected (MSI2~0 not equals 000B), this bit will
only be set after the number of zero detect is masked.
Note: In up-count mode (MODE=0), this bit is set at every zero
detect disregarding the value of MSI2~0.
bit 13
IRQZE:
Zero detect
interrupt request
enable bit
• This is the interrupt request enable bit for the zero detect.
• When this bit is “1” and the interrupt flag (bit 14: IRQZF) is set to “1”, an
interrupt request will be generated to CPU.
MSI2 ~ 0:
Interrupt mask
selection bits
• These bits are used to set the number of times of masking the
compare clear interrupt in up-count mode (MODE=0) or zero detect
interrupt in up-down count mode (MODE=1).
• No interrupt cause is masked when MSI2~0 equals zero.
Note: To mask the interrupt cause twice and perform interrupt
processing at the third time, MSI2~0 should be set as 010B.
bit9
ICLR:
Compare clear
interrupt flag bit
• This bit is an interrupt flag for compare clear.
• When the compare clear value and 16-bit free-running timer value are
matched, this bit is set to “1”.
• Writing “0” will clear this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
Note: In up-count mode (MODE=0) and interrupt mask function is
selected (MSI2~0 not equals 000B), this bit will only be set
after the number of compare clear is masked.
Note: In up-down count mode (MODE=1), this bit is set at every
compare clear disregarding the value of MSI2~0.
bit8
ICRE:
Compare clear
interrupt request
enable bit
• This is the interrupt request enable bit for the compare clear.
• When this bit is “1” and the interrupt flag (bit 9: ICLR) is set to “1”, an
interrupt request will be generated to CPU.
bit15
bit12
bit11
bit10
MB90820 series
Function
373
■ TImer control status register, lower byte (TCCSL)
Address bit7
bit6
00005EH
BFE STOP MODE SCLR CLK2 CLK1 CLK0 X0100000B
R/W
R/W
bit5
R/W
bit4
R/W
bit3
R/W
bit2
bit1
R/W
R/W
bit0 Initial value
R/W
Clock frequency selection bit
CLK2 CLK1
CLK0
φ=
24MHz
Count
clock
φ=
8MHz
φ=
16MHz
φ=
4MHz
φ=
1MHz
0
0
0
φ
41.7 ns 62.5 ns 125 ns 0.25 µs
1 µs
0
0
1
φ/2
83.3 ns 125 ns 0.25 µs 0.5 µs
2 µs
0
1
0
φ/4
0.17 µs 0.25 µs 0.5 µs
1 µs
4 µs
0
1
1
φ/8
0.33 µs 0.5 µs
1 µs
2 µs
8 µs
1
0
0
φ/16
0.67 µs
1 µs
2 µs
4 µs
16 µs
1
0
1
φ/32
1.33 µs
2 µs
4 µs
8 µs
32 µs
1
1
0
φ/64
2.67 µs
4 µs
8 µs
16 µs
64 µs
1
1
1
φ/128
5.33 µs
8 µs
16 µs
32 µs
128
µs
φ: Machine cycle
Timer clear bit
SCLR
Write
Read
0
Clear SCLR bit
1
Initialize counter to “0000H”
Always read as ”0”
R/W : Read and write
: Initial value
—
: Not used
MODE
Timer counting mode
0
up-count mode
1
up-down count mode
STOP
Timer enable bit
0
Counting is enabled (operation)
1
Counting is disabled (stop)
BFE
Compare clear buffer enable bit
0
Disable compare clear buffer
1
Enable compare clear buffer
Figure 14.4.3-2 Timer control status register (TCCSL)
374
MB90820 series
Table 14.4.3-2 Timer control status register (TCCSL)
Bit name
bit7
• The read value is indeterminate.
• Writing to this bit has no effect on the operation.
BFE:
Compare clear
buffer enable bit
• This bit is used to enable compare clear buffer.
• Writing “0” disables compare clear buffer. Directly write in compare
clear register is possible.
• Writing “1” enables compare clear buffer. Data written in compare clear
buffer register will be held and transfer to compare clear register when
the count value of 16-bit free-running timer is detected as zero.
STOP:
Timer enable bit
• This bit is used to stop/start the counting of the 16-bit free-running
timer.
• Writing “1” stops the counting of the 16-bit free-running timer.
• Writing “0” starts the counting of the 16-bit free-running timer.
Note: When the 16-bit free-running timer is stopped, the output
compare operation will also be stopped.
MODE:
Timer counting
mode bit
• This bit is used to select the count mode of the 16-bit free-running
timer.
• Writing “0” selects up-count mode. Timer counts up until counter value
matches with compare clear register and reset to “0000H” and then
counts up again.
• Writing “1” selects up-down count mode.
In up-down count mode, whenever zero in the timer data register is
detected, the timer counting direction will always be reseted to upcounting.
The timer will reverse its counting direction whenever the timer value
matches with compare clear register.
• This bit can be written at any time whether the timer is operating or
stopped. The value written to this bit is buffered and the count mode
will be changed when timer value is “0000H”.
Note: Becasue the timer will reverse its counting direction when
compare-match is detected in up-down count mode ( MODE
= “1” ), it should be careful to set the compare clear register
and timer data register when the timer is being counted down.
bit3
SCLR:
Timer clear bit
• This bit is used to initialize the 16-bit free-running timer to “0000H”.
• Writing “1” initializes 16-bit free-running timer to “0000H” at the next
count clock.
• Writing “0” will clear the bit SCLR if it is “1”.
• Read value is always “0”.
Note: This bit cannot be used to initialize the timer when timer stops
(STOP=1). Writing “0000H” to timer data register (TCDT) can
initialize the timer.
Note: Writng “1” will not generate zero detect interrupt.
Note: This bit will be cleared by hardware after the timer is
initialized to “0000”. If “0” is written to the bit before timer
initialization, the bit is cleared and the timer did not initialized.
bit2
bit1
bit0
CLK2 ~ 0:
Clock frequency
selection bit
• This bit is used to select count clock for the 16-bit free-running timer.
• The count clock is changed immediately after these bits are set. So
change them while the output compare and input capture units are
stopped.
bit6
bit5
bit4
MB90820 series
Unused bit
Function
375
14.4
Registers of Multi-functional Timer
14.4.4 Output Compare Buffer Registers (OCCPB0 ~ 5) / Output
Compare Registers (OCCP0 ~ 5)
Output compare buffer register (OCCPB) is a 16-bit buffer register of output compare
register (OCCP). Both OCCPB and OCCP registers are located in the same address.
■ Output compare buffer registers (OCCPB0 ~ 5)
Output Compare Buffer Register (Upper)
Address: ch0
ch1
ch2
ch3
ch4
ch5
000071H
000073H
000075H
000077H
000079H
00007BH
Read/write
Initial value
15
OP15
14
OP14
W
X
13
12
11
10
9
8
OP13
OP12
OP11
OP10
OP09
OP08
W
X
W
X
W
X
W
X
W
X
W
X
3
2
1
OP01
OP00
W
X
Bit number
OCCPB0 ~ 5
Output Compare Buffer Register (Lower)
Address: ch0
ch1
ch2
ch3
ch4
ch5
000070H
000072H
000074H
000076H
000078H
00007AH
Read/write
Initial value
7
6
5
4
OP07
OP06
OP05
OP04
OP03 OP02
W
X
W
X
W
X
W
X
0
Bit number
OCCPB0 ~ 5
W
X
W
X
W
X
W
X
Figure 14.4.4-1 Output compare buffer registers (OCCPB0 ~ 5)
Output compare buffer register is the buffer register of output compare register (OCCP). When buffer
function is disabled (OCS0/2/4:BUF0/1=1) or when free-running timer is stopped, value in output
compare buffer register is transferred to output compare register immediately. When buffer function is
enabled (OCS0/2/4:BUF0/1=0), value is transferred at compare clear match or zero detection
depending on transfer selection bit BTS in compare control register (OCS1/3/5).
Word access to this register is recommended.
376
MB90820 series
■ Output compare registers (OCCP0 ~ 5)
Output Compare Register (Upper)
Address: ch0
ch1
ch2
ch3
ch4
ch5
000071H
000073H
000075H
000077H
000079H
00007BH
15
OP15
Read/write
Initial value
14
OP14
R
X
13
12
11
10
9
8
OP13
OP12
OP11
OP10
OP09
OP08
R
X
R
X
R
X
R
X
R
X
R
X
2
1
OP01
OP00
R
X
R
X
R
X
Bit number
OCCP0 ~ 5
Output Compare Register (Lower)
Address: ch0
ch1
ch2
ch3
ch4
ch5
000070H
000072H
000074H
000076H
000078H
00007AH
7
6
5
4
3
OP07
OP06
OP05
OP04
OP03 OP02
R
X
R
X
R
X
R
X
0
Bit number
OCCP0 ~ 5
Read/write
Initial value
R
X
R
X
Figure 14.4.4-2 Output compare registers (OCCP0 ~ 5)
The output compare register is a 16-bit register which is used to compare the count value of 16-bit freerunning timer. The initial value of the output compare register is undetermined, so output compare
buffer register (OCCPB) must be set with a value before enabling the operation.
When the value of the output compare register matches the count value of 16-bit free-running timer, a
compare signal is generated to set the output compare interrupt flag (OCS0/2/4:IOP0/1). If output level
is set (OCS1/3/5:OTD0/1), the output level of RT0 ~ 5 corresponding to the output compare register
(OCCP0 ~ 5) can be reversed.
Word access to this register is recommended.
MB90820 series
377
14.4
Registers of Multi-functional Timer
14.4.5 Compare Control Registers (OCS0/1/2/3/4/5)
Compare control register is used to control the output level, output enable, output
reverse mode, compare operation enable, compare match interrupt enable and
compare match interrupt flag for RTO0 ~ 5.
■ Compare control register, upper byte (OCS1/3/5)
Address
bit15 bit14 bit13 bit12 bit11 bit10
ch1: 00007DH
ch3: 00007FH
ch5: 000081H
—
—
bit9
bit8 Initial value
BTS1 BTS0 CMOD OTE1 OTE0 OTD1 OTD0 X1100000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output level bit
OTD0
Write
Read
0
Output “0” for RT0/RT2/RT4
1
Output “1” for RT0/RT2/RT4
Current output value of RT0/
RT2/RT4
Output level bit
OTD1
Write
Read
0
Output “0” for RT1/RT3/RT5
1
Output “1” for RT1/RT3/RT5
Current output value of RT1/
RT3/RT5
OTE0
Output enable bit
0
General-purpose port (P82/P84/P86)
1
Output compare output pin (RTO0/RTO2/RTO4)
OTE1
Output enable bit
0
General-purpose port (P83/P85/P87)
1
Output compare output pin (RTO1/RTO3/RTO5)
CMOD
Output level reverse mode bit
0
RT0/2/4: The level is reversed upon a match with compare register 0/2/4
RT1/3/5: The level is reversed upon a match with compare register 1/3/5 respectively
1
RT0/2/4: The level is reversed upon a match with compare register 0/2/4
RT1/3/5: The level is reversed upon a match with compare register (0or1)/(2or3)/(4or5)
BTS0
R/W : Read and write
: Initial value
—
: Not used
Buffer transfer select bit
0
Transfer at zero detect ( channel 0/2/4)
1
Transfer at compare clear match (channel 0/2/4)
BTS1
Buffer transfer select bit
0
Transfer at zero detect (channel 1/3/5)
1
Transfer at compare clear match (channel 1/3/5)
Figure 14.4.5-1 Compare control register (OCS1/3/5)
378
MB90820 series
Table 14.4.5-1 Compare control register (OCS1/3/5) bit
Bit name
Unused bit
• The read value is indeterminate.
• Writing to this bit has no effect on the operation.
BTS1
• This bit is used to select when data transfer from output compare buffer
register (OCCPB1/3/5) to output compare register (OCCP1/3/5).
• When BTS1=0, buffer transfer is occurred when count value of 16-bit freerunning timer is detected as zero.
• When BTS1=1, buffer transfer is occurred when compare clear match is
occurred in 16-bit free-running timer.
BTS0
• This bit is used to select when data transfer from output compare buffer
register (OCCPB0/2/4) to output compare register (OCCP0/2/4).
• When BTS0=0, buffer transfer is occurred when count value of 16-bit freerunning timer is detected as zero.
• When BTS0=1, buffer transfer is occurred when compare clear match is
occurred in 16-bit free-running timer.
bit12
CMOD:
Output
level
reverse
mode bit
• CMOD is used to switch the pin output level reverse mode upon a match while
pin output is enabled (OTE1 = 1 or OTE0 = 1).
• When CMOD = 0, the output level of the pin is reversed upon a match with
corresponding compare register.
RT0/2/4: The level is reversed upon a match between the 16-bit free-running timer and compare register 0/2/4.
RT1/3/5: The level is reversed upon a match between the 16-bit free-running timer and compare register 1/3/5.
• When CMOD = 1, the output level of the pin RT0/2/4 corresponding to
compare register is reversed as same as when CMOD = 0. However, the
output level of the pin (RT1/3/5) corresponding to compare register 1/3/5 is
reversed when a match is detected in compare register 0/2/4 or 1/3/5. If
compare registers 0/2/4 and 1/3/5 have the same value, the same operation as
when only one compare register is used.
RT0/2/4: The level is reversed upon a match between the 16-bit free-running timer and compare register 0/2/4.
RT1/3/5: The level is reversed upon a match between the 16-bit free-running timer and compare register (0 or 1)/(2 or 3)/(4 or 5).
bit11
OTE1:
Output
enable bit
• This bit is used to enable waveform generator output RTO1/3/5 to P83/P85/
P87.
• The initial value for these bits is “0”.
Note: If waveform generator is disabled (DTCR:TMD2~0=000B) RTO1/3/5
output the same value in output compare RT1/3/5.
bit10
OTE0:
Output
enable bit
• This bit is used to enable waveform generator output RTO0/2/4 to P82/P84/
P86.
• The initial value for these bits is “0”.
Note: If waveform generator is disabled (DTCR:TMD2~0=000B) RTO0/2/4
output the same value in output compare RT0/2/4.
bit9
OTD1:
Output
level bit
• This bit is used to change the output level for output compare 1/3/5 (RT1/3/5).
• The initial value of the compare output is “0”.
• Ensure that the compare operation is stopped before a value is written. When
reading this bit, this bit indicate the output compare value in RT1/3/5.
bit8
OTD0:
Output
level bit
• This bit is used to change the output level for output compare 0/2/4 (RT0/2/4).
• The initial value of the compare output is “0”.
• Ensure that the compare operation is stopped before a value is written. When
reading this bit, this bit indicates the output compare value in RT0/2/4.
bit15
bit14
bit13
MB90820 series
Function
379
■ Compare control register , lower byte (OCS0/2/4)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0 Initial value
ch0: 00007CH IOP1 IOP0 IOE1 IOE0 BUF1 BUF0 CST1 CST0 00001100B
ch2: 00007EH R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ch4: 000080H
CST0
Compare operation enable bit
0
Disable compare operation for compare register 0/2/4
1
Enable compare operation for compare register 0/2/4
CST1
Compare operation enable bit
0
Disable compare operation for compare register 1/3/5
1
Enable compare operation for compare register 1/3/5
BUF0
Compare buffer disable bit
0
Enable compare buffer for compare register 0/2/4
1
Disable compare buffer for compare register 0/2/4
BUF1
Compare buffer disable bit
0
Enable compare buffer for compare register 1/3/5
1
Disable compare buffer for compare register 1/3/5
IOE0
Compare match interrupt enable bit
0
Disable compare match interrupt for compare register 0/2/4
1
Enable compare match interrupt for compare register 0/2/4
IOE1
Compare match interrupt enable bit
0
Disable compare match interrupt for compare register 1/3/5
1
Enable compare match interrupt for compare register 1/3/5
Compare match interrupt flag bit
IOP0
Read
Write
0
No compare match interrupt for
compare register 0/2/4
Clear this bit
1
Compare match interrupt for
compare register 0/2/4
No effect
Compare match interrupt flag bit
IOP1
R/W : Read and Write
Read
Write
0
No compare match interrupt for
compare register 1/3/5
Clear this bit
1
Compare match interrupt for
compare register 1/3/5
No effect
: Initial value
—
380
: Not used
MB90820 series
Figure 14.4.5-2 Compare control register (OCS0/2/4)
Table 14.4.5-2 Compare control register (OCS0/2/4)
Bit name
bit7
• This bit is an interrupt flag for when compare register 1/3/5 is matched
with the value of 16-bit free-running timer.
• “1” is set to this bit when the compare register value matches the 16-bit
IOP1:
free-running timer value.
Compare match • While the interrupt request bits (IOE1) is enabled, an output compare
interrupt flag bit interrupt occurs when the IOP1 bit is set.
• Writing “0” will clear this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
bit6
• This bit is an interrupt flag for when compare register 0/2/4 is matched
with the value of 16-bit free-running timer.
• “1” is set to this bit when the compare register value matches the 16-bit
IOP0:
free-running timer value.
Compare match • While the interrupt request bits (IOE0) is enabled, an output compare
interrupt flag bit interrupt occurs when the IOP0 bit is set.
• Writing “0” will clear this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
bit5
IOE1:
• This bit is used to enable output compare interrupt for compare register
Compare match
1/3/5.
• While the “1” is written to this bit, an output compare interrupt occurs
interrupt
when an interrupt flag (IOP1) is set.
enable bit
bit4
IOE0:
• This bit is used to enable output compare interrupt for compare register
Compare match
0/2/4.
interrupt enable • While the “1” is written to this bit, an output compare interrupt occurs
when an interrupt flag (IOP0) is set.
bit
bit3
BUF1:
• This bit is used to disable buffer function for output compare register 1/
3/5.
Compare buffer
• Writing “0” will enable the buffer function.
disable bit
bit2
BUF0:
• This bit is used to disable buffer function for output compare register 0/
2/4.
Compare buffer
• Writing “0” will enable the buffer function.
disable bit
bit1
MB90820 series
Function
CST1:
Compare
operation
enable bit
• This bit is used to enable the compare operation between 16-bit freerunning timer and compare register 1/3/5.
• Ensure that a value is written into the compare register and timer data
register before the compare operation is enabled.
Note: Since output compare is synchronized with the 16-bit
free-running timer clock, stopping the 16-bit freerunning timer stops compare operation.
381
Table 14.4.5-2 Compare control register (OCS0/2/4)
Bit name
bit0
382
CST0:
Compare
operation
enable bit
Function
• This bit is used to enable the compare operation between 16-bit freerunning timer and compare register 0/2/4.
• Ensure that a value is written into the compare register and timer data
register before the compare operation is enabled.
Note: Since output compare is synchronized with the 16-bit
free-running timer clock, stopping the 16-bit freerunning timer stops compare operation.
MB90820 series
14.4
Registers of Multi-functional Timer
14.4.6 Input Capture Register (IPCP0 ~ 3)
Input capture registers are used to hold the count value of 16-bit timer when a valid
edge of the input waveform is detected.
■ Input capture register (IPCP0 ~ 3)
Input Capture Data Register (Upper)
Address: ch0
ch1
ch2
ch3
000061H
000063H
000065H
000067H
15
CP15
Read/write
Initial value
14
CP14
12
11
10
9
8
CP13
CP12
CP11
CP10
CP09
CP08
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
13
Bit number
IPCP0 ~ 3
Input Capture Data Register (Lower)
Address: ch0
ch1
ch2
ch3
000060H
000062H
000064H
000066H
Read/write
Initial value
7
6
5
4
3
2
1
0
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
R
X
R
X
R
X
R
X
Bit number
IPCP0 ~ 3
R
X
R
X
R
X
R
X
Figure 14.4.6-1 Input capture data registers (IPCP0 ~ 3)
This register is used to store the value of the 16-bit timer when a valid edge of the corresponding
external pin input waveform is detected. (Word access instruction to this register is
recommended. No data can be written to this register.)
MB90820 series
383
14.4.7 Input Capture Control Status Registers (ICS23, PICS01)
Input capture control status registers (ICS23, PICS01) are used to control edge
selection, interrupt request enable, interrupt request flag and to indicate valid edge
detected for input capture 0 ~ 3.
■ Input capture control status register, upper byte (ICSH23)
Address bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8 Initial value
00006BH
IEI3
IEI2 XXXXXX00B
R
R
: Read-only
-
: Not used
: Initial value
R
IEI2
Valid edge indication bit (input capture 2)
0
Falling edge detected
1
Rising edge detected
IEI3
Valid edge indication bit (input capture 3)
0
Falling edge detected
1
Rising edge detected
Figure 14.4.7-1 Input capture control status register (ICSH23)
Table 14.4.7-1 Input capture control status register (ICSH23)
Bit name
bit15
bit14
bit13
bit12
bit11
bit10
bit9
Unused bit
IEI3:
Valid edge
indication bit
Function
• The read value is indeterminate.
• Writing to this bit has no effect on the operation.
• This bit is an valid edge indication bit for capture register 3, to indicate
a rising or falling edge is detected.
• “0” is written to this bit when falling edge is detected.
• “1” is written to this bit when rising edge is detected.
• This bit is read-only.
Note: The read value is meaningless when EG31, EG30 = “00”.
bit8
IEI2:
Valid edge
indication bit
• This bit is an valid edge indication bit for capture register 2, to indicate
a rising or falling edge is detected.
• “0” is written to this bit when falling edge is detected.
• “1” is written to this bit when rising edge is detected.
• This bit is read-only.
Note: The read value is meaningless when EG21, EG20 = “00”.
384
MB90820 series
Memo
MB90820 series
385
■ Input capture control status register, lower byte (ICSL23)
Address bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0 Initial value
00006AH ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EG21
EG20
Edge selection bit (input capture 2)
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
EG31
EG30
Edge selection bit (input capture 3)
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
ICE2
Interrupt request enable bit (input capture 2)
0
Disable interrupt request
1
Enable interrupt request
ICE3
Interrupt request enable bit (input capture 3)
0
Disable interrupt request
1
Enable interrupt request
Interrupt request flag bit (input capture 2)
ICP2
Read
Write
0
No valid edge detected
Clear this bit
1
Valid edge detected
No effect
Interrupt request flag bit (input capture 3)
ICP3
R/W : Read and Write
Read
Write
0
No valid edge detected
Clear this bit
1
Valid edge detected
No effect
: Initial value
Figure 14.4.7-2 Input capture control status register (ICSL23)
386
MB90820 series
Table 14.4.7-2 Input capture control status register (ICSL23)
Bit name
MB90820 series
Function
bit7
• This bit is used as interrupt request flag for input capture 3.
• “1” is set to this bit upon detection of a valid edge in an external input
ICP3:
pin.
Interrupt request • While the interrupt enable bit (ICE3) is set, an interrupt can be
generated upon detection of a valid edge.
flag bit
(Input capture 3) • Writing “0” will clear this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
bit6
• This bit is used as interrupt request flag for input capture 2.
• “1” is set to this bit upon detection of a valid edge in an external input
ICP2:
pin.
Interrupt request • While the interrupt enable bit (ICE2) is set, an interrupt can be
generated upon detection of a valid edge.
flag
(Input capture 2) • Writing “0” will clear this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
bit5
ICE3:
• This bit is used to enable input capture interrupt request for input
Interrupt request
capture 3.
• While “1” is written to this bit, an input capture interrupt is generated
enable bit
when the interrupt flag (ICP3) is set.
(Input capture 3)
bit4
ICE2:
• This bit is used to enable input capture interrupt request for input
Interrupt request
capture 2.
• While “1” is written to this bit, an input capture interrupt is generated
enable bit
when the interrupt flag (ICP2) is set.
(Input capture 2)
bit3
bit2
EG31, EG30:
• These bits are used to specify the valid edge polarity of an external
Edge selection
input for input capture 3.
bit
• These bits are also used to enable input capture operation.
(Input capture 3)
bit1
bit0
EG21, EG20:
• These bits are used to specify the valid edge polarity of an external
Edge selection
input for input capture 2.
bit
• These bits are also used to enable input capture operation.
(Input capture 2)
387
■ PPG output control / Input capture control status register, upper byte (PICSH01)
Address bit15
bit14
bit13
bit12
bit11
bit10
bit9
000069H PGEN5 PGEN4PGEN3 PGEN2 PGEN1 PGEN0 IEI1
R/W
R
R/W
: Read-only
R/W : Read and Write
R/W
R/W
R/W
R/W
R
bit8 Initial value
IEI0
00000000B
R
IEI0
Valid edge indication bit (input capture 0)
0
Falling edge detected
1
Rising edge detected
IEI1
Valid edge indication bit (input capture 1)
0
Falling edge detected
1
Rising edge detected
PGEN0
PPG output enable bit
0
Disable PPG0 output to RTO0
1
Enable PPG0 output to RTO0
PGEN1
PPG output enable bit
0
Disable PPG0 output to RTO1
1
Enable PPG0 output to RTO1
PGEN2
PPG output enable bit
0
Disable PPG0 output to RTO2
1
Enable PPG0 output to RTO2
PGEN3
PPG output enable bit
0
Disable PPG0 output to RTO3
1
Enable PPG0 output to RTO3
PGEN4
PPG output enable bit
0
Disable PPG0 output to RTO4
1
Enable PPG0 output to RTO4
PGEN5
PPG output enable bit
0
Disable PPG0 output to RTO5
1
Enable PPG0 output to RTO5
: Initial value
Figure 14.4.7-3 PPG output control/input capture control status register (PICSH01)
388
MB90820 series
Table 14.4.7-3 PPG output control/input capture control status register (PICSH01)
Bit name
bit15
bit14
bit13
bit12
bit11
bit10
bit9
PGEN5~0:
PPG output
enable bits
IEI1:
Valid edge
indication bit
Function
• This bit is used to select PPG0 output to RTO0/1/2/3/4/5.
• This bit is an valid edge indication bit for capture register 1, to indicate
a rising or falling edge is detected.
• “0” is written to this bit when falling edge is detected.
• “1” is written to this bit when rising edge is detected.
• This bit is read-only.
Note: The read value is meaningless when EG11, EG10 =
“00B”.
bit8
IEI0:
Valid edge
indication bit
• This bit is an value edge indication bit for capture register 0, to indicate
a rising or falling edge is detected.
• “0” is written to this bit when falling edge is detected.
• “1” is written to this bit when rising edge is detected.
• This bit is read-only.
Note: The read value is meaningless when EG01, EG00 =
“00B”.
MB90820 series
389
■ Input capture control status register, lower byte (PICSL01)
Address bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0 Initial value
000068H ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EG01
EG00
Edge selection bit (input capture 0)
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
EG11
EG10
Edge selection bit (input capture 1)
0
0
No edge detection (stop)
0
1
Rising edge detection
1
0
Falling edge detection
1
1
Both edges detection
ICE0
Interrupt request enable bit (input capture 0)
0
Disable interrupt request
1
Enable interrupt request
ICE1
Interrupt request enable bit (input capture 1)
0
Disable interrupt request
1
Enable interrupt request
Interrupt request flag bit (input capture 0)
ICP0
Read
Write
0
No valid detected
Clear this bit
1
Valid detected
No effect
Interrupt request flag bit (input capture 1)
ICP1
R/W : Read and Write
Read
Write
0
No valid edge detected
Clear this bit
1
Valid edge detected
No effect
: Initial value
Figure 14.4.7-4 Input capture control status register (PICSL01)
390
MB90820 series
14.4
Registers of Multi-functional Timer
Table 14.4.7-4 Input capture control status register (PICSL01)
Bit name
MB90820 series
Function
• This bit is used as interrupt request flag for input capture 1.
• “1” is set to this bit upon detection of a valid edge of an external input
pin.
• While the interrupt enable bit (ICE1) is set, an interrupt can be
generated upon detection of a valid edge.
• Writing “0” will clear this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
bit7
ICP1:
Interrupt
request
flag bit
(Input capture 1)
bit6
• This bit is used as interrupt request flag for input capture 0.
• “1” is set to this bit upon detection of a valid edge of an external input
ICP0:
pin.
Interrupt
• While the interrupt enable bit (ICE0) is set, an interrupt can be
request
generated upon detection of a valid edge.
flag bit
• Writing “0” will clear this bit.
(Input capture 0) • Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
bit5
ICE1:
• This bit is used to enable input capture interrupt request for input
Interrupt
capture 1.
request
• While “1” is written to this bit, an input capture interrupt is generated
enable bit
when the interrupt flag (ICP1) is set.
(Input capture 1)
bit4
ICE0:
• This bit is used to enable input capture interrupt request for input
Interrupt
capture 0.
request
• While “1” is written to this bit, an input capture interrupt is generated
enable bit
when the interrupt flag (ICP0) is set.
(Input capture 0)
bit3
bit2
EG11, EG10:
• These bits are used to specify the valid edge polarity of an external
Edge selection
input for input capture 1.
bit
• These bits are also used to enable input capture operation.
(Input capture 1)
bit1
bit0
EG01, EG00:
• These bits are used to specify the valid edge polarity of an external
Edge selection
input for input capture 0.
bit
• These bits are also used to enable input capture operation.
(Input capture 0)
391
14.4.8 16-bit Timer Register (TMRR0/1/2)
16-bit timer registers hold the compare value of 16-bit timers.
■ 16-bit timer registers (TMRR0/1/2)
16-bit Timer Register (Upper)
Address: ch0 000051H
ch1 000053H
ch2 000055H
15
14
13
12
11
10
9
TR14
TR13
TR12
TR11
TR10
TR09
TR08
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
7
6
5
4
3
2
1
TR07
TR06
TR05
TR03
TR02
TR01
TR00
R/W
X
R/W
X
Bit number
8
TMRR0/1/2
TR15
Read/write
Initial value
R/W
X
R/W
X
16-bit Timer Register (Lower)
Address: ch0 000050H
ch1 000052H
ch2 000054H
Bit number
0
TMRR0/1/2
Read/write
Initial value
R/W
X
TR04
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Figure 14.4.8-1 16-bit timer registers (TMRR0/1/2)
These registers are used to store the comparison value of 16-bit timers. The value in these registers
will be reloaded when the 16-bit timer is started to operate. Therefore, if the value is re-written into
these registers during timer operation, this value will be valid at the next timer initiation/operation.
In dead-time timer mode, these registers are used to set the non-overlap time.
•
Non-overlap time = (set value + 1) x selected clock.
Note: The value of “0000H” cannot be set.
Note: The maximum offset of non-overlap time is -1 selected clock.
In timer mode, these registers are used to set the GATE time for PPG timer 0 operation.
•
GATE time = (set value + 1) x selected clock.
Note: The value of “0000H” cannot be set and maximum offset is -1 selected clock
Note: The maximum offset of GATE time is -1 selected clock.
392
MB90820 series
Memo
MB90820 series
393
14.4
Registers of Multi-functional Timer
14.4.9 16-bit Timer Control Register (DTCR0/1/2)
16-bit timer control registers (DTCR0/1/2) are used to control the operation mode,
interrupt request enable, interrupt request flag, GATE signal enable and output level
polarity for the waveform generator.
■ 16-bit timer control register (DTCR0/2)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0 Initial value
ch0: 000056H DMOD GTEN1 GTEN0 TMIF TMIE TMD2 TMD1 TMD0 00000000B
ch2: 000058H R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TMD2 TMD1 TMD0
Operation mode bit
0
0
0
Waveform generator is stopped.
0
0
1
PPG timer 0 output pulse while RT signal is “H”.
0
1
0
The rising edge of each RT signal will trigger
16-bit timer to start. PPG timer 0 output pulse
until the 16-bit timer stopped. (Timer mode)
1
0
0
Generate non-overlap signal by RT signal.
(Dead-time timer mode)
1
1
1
Generate non-overlap signal by PPG timer 0.
(Dead-time timer mode)
Others
Prohibited
TMIE
Interrupt request enable bit
0
Disable an interrupt when the 16-bit timer underflow
1
Enable an interrupt when the 16-bit timer underflow
Interrupt request flag bit
TMIF
R/W : Read and Write
: Initial value
Read
Write
0
No counter underflow detected
Clear this bit
1
Counter underflow detected
No effect
GTEN0
GATE signal control bit 0
0
GATE signal is not controlled by RT0/4 (asynchronous mode)
1
GATE signal is controlled by RT0/4 (synchronous mode)
GTEN1
GATE signal control bit 1
0
GATE signal is not controlled by RT1/5 (asynchronous mode)
1
GATE signal is controlled by RT1/5 (synchronous mode)
DMOD
Output polarity control bit
0
Normal polarity output
1
Inverted polarity output
Figure 14.4.9-1 16-bit timer control register (DTCR1)
394
MB90820 series
Table 14.4.9-1 16-bit timer control registers (DTCR0/2) bit
Bit name
bit7
DMOD:
Output polarity
control bit
Function
• This bit is used to set the output polarity of U/V/W in dead-time timer
mode.
• By setting this bit, the output polarity of U/V/W is inverted.
Note: This bit is meaningless when dead-time timer mode is
not selected (bit 2: TMD2 = 0).
bit6
GTEN1:
GATE signal
control bit 1
• This bit is used to control the GATE signal output for PPG timer 0 by
RT1/5.
bit5
GTEN0:
GATE signal
control bit 0
• This bit is used to control the GATE signal output of PPG timer 0 by
RT0/4.
bit4
bit3
TMIF:
Interrupt request
flag bit
TMIE:
Interrupt request
enable / software
trigger bit
•
•
•
•
•
This bit is used as an interrupt request flag for 16-bit timers.
This bit will be set to “1” when 16-bit timer 0/2 is underflow.
Writing “0” will clear this bit.
Writing “1” has no effect.
In read-modify-write operation, “1” is always read.
Note: This bit functions only in mode TMD2~0=000B or 001B.
In other modes, this bit is always “0”.
Note: If both software clear (writing “0”) and hardware set
(16-bit timer 0/2 underflow) occurs simultaneously,
software clear takes the higher priority to clear this bit.
• This bit is used as the software trigger bit and interrupt enable bit for
the 16-bit timer 0/2.
• When TMD2~0=000B or 001B, this bit is used as software trigger for
16-bit timer. Setting this bit from “0” to “1” trigger the 16-bit timer to
reload and starts down-counting.
• When this bit is “1” and the interrupt flag bit (bit 4: TIMF) is “1”, an
interrupt request is sent to CPU.
Note: To retrigger the 16-bit timer, be sure to write “0” before
write “1” to this bit.
bit2
bit1
bit0
MB90820 series
TMD2 ~ 0:
Operation mode
bits
• These bits are used to select the operation mode of the waveform
generator.
• When TMD2~0=000B, output compare RT0/4 and RT1/5 outputs to
RTO0/4 and RTO1/5 respectively. And 16-bit timer can be used as
reload timer.
• When TMD2~0=001B, output compare RT0/4 and RT1/5 outputs to
RTO0/4 and RTO1/5 respectively if PPG0 output is disabled
(PICSH01:PGEN0/4=0, PGEN1/5=0). And 16-bit timer can be used
as reload timer.
Note: To operate the waveform generator in dead-time timer
mode, be sure to select 2-channel mode for RT1/5
(OCS1/5:CMOD=1)
Note: When TMD2~0=111B is selected, RTO0/4 and RTO1/5
output are independent of setting in PICSH01:PGEN0/
4,PGEN1/5.
395
■ 16-bit timer control register (DTCR1)
Address
ch1: 000057H
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9
bit 8 Initial value
DMOD GTEN1 GTEN0 TMIF TMIE TMD2 TMD1 TMD0 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TMD2 TMD1 TMD0
Operation mode bit
0
0
0
Waveform generator is stopped.
0
0
1
PPG timer 0 output pulse while RT signal is “H”.
0
1
0
The rising edge of each RT signal will trigger
16-bit timer to start. PPG timer 0 output pulse
until the 16-bit timer stopped. (Timer mode)
1
0
0
Generate non-overlap signal by RT signal.
(Dead-time timer mode)
1
1
1
Generate non-overlap signal by PPG timer 0.
(Dead-time timer mode)
Others
Prohibited
TMIE
Interrupt request enable bit
0
Disable an interrupt when the 16-bit timer underflow
1
Enable an interrupt when the 16-bit timer underflow
Interrupt request flag bit
TMIF
R/W : Read and Write
Read
Write
0
No counter underflow detected
Clear this bit
1
Counter underflow detected
No effect
GTEN0
GATE signal control bit 0
0
GATE signal is not controlled by RT2 (asynchronous mode)
1
GATE signal is controlled by RT2 (synchronous mode)
GTEN1
GATE signal control bit 1
0
GATE signal is not controlled by RT3 (asynchronous mode)
1
GATE signal is controlled by RT3 (synchronous mode)
DMOD
Output polarity control bit
0
Normal polarity output
1
Inverted polarity output
: Initial value
Figure 14.4.9-2 16-bit timer control register (DTCR1)
396
MB90820 series
14.4
Registers of Multi-functional Timer
Table 14.4.9-2 16-bit timer control registers (DTCR1) bit
Bit name
bit15
DMOD:
Output polarity
control bit
Function
• This bit is used to set the output polarity of U/V/W in dead-time timer
mode.
• By setting this bit, the output polarity of U/V/W is inverted.
Note: This bit is meaningless when dead-time timer mode is
not selected (bit10: TMD2 = 0).
bit14
GTEN1:
GATE signal
control bit 1
• This bit is used to control the GATE signal output for PPG timer 0 by
RT3.
bit13
GTEN0:
GATE signal
control bit 0
• This bit is used to control the GATE signal output of PPG timer 0 by
RT2.
bit12
bit11
TMIF:
Interrupt request
flag bit
TMIE:
Interrupt request
enable bit
•
•
•
•
•
This bit is used as an interrupt request flag for 16-bit timers.
This bit will be set to “1” when 16-bit timer 1 is underflow.
Writing “0” will clear this bit.
Writing “1” has no effect.
In read-modify-write operation, “1” is always read.
Note: This bit functions only in mode TMD2~0=000B or 001B.
In other modes, this bit is always “0”.
Note: If both software clear (writing “0”) and hardware set
(16-bit timer 1 underflow) occurs simultaneously,
software clear takes the higher priority to clear this bit.
• This bit is used as the software trigger bit and interrupt enable bit for
the 16-bit timer.
• When TMD2~0=000B or 001B, this bit is used as software trigger for
16-bit timer. Setting this bit from “0” to “1” trigger the 16-bit timer to
reload and starts down-counting.
• When this bit is “1” and the interrupt flag bit (bit12: TIMF) is “1”, an
interrupt request is sent to CPU.
Note: To retrigger the 16-bit timer, be sure to write “0” before
write “1” to this bit.
bit10
bit9
bit8
MB90820 series
TMD2 ~ 0:
Operation mode
bit
• These bits are used to select the operation mode of the waveform
generator.
• When TMD2~0=000B, output compare RT2 and RT3 outputs to RTO2
and RTO3 respectively. And 16-bit timer can be used as reload timer.
• When TMD2~0=001B, output compare RT2 and RT3 outputs to RTO2
and
RTO3
respectively
if
PPG0
output
is
disabled
(PICSH01:PGEN2=0, PGEN3=0). And 16-bit timer can be used as
reload timer.
Note: To operate the waveform generator in dead-time timer
mode, be sure to select 2-channel mode for RT3
(OCS3:CMOD=1)
Note: When TMD2~0=111B is selected, RTO2 and RTO3
output
are
independent
of
setting
in
PICSH01:PGEN2,3.
397
14.4.10 Waveform Control Register (SIGCR)
Waveform control register is used to control how the operating clock frequencies,
noise cancellation function enable, DTTI input enable and DTTI interrupt.
■ Waveform control register (SIGCR)
Address bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8 Initial value
000059H DTIE DTIF NRSL DCK2 DCK1 DCK0 NWS1 NWS0 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NWS1
NWS0
DTTI Noise width selection bits
0
0
Cancel 4-cycle noise.
0
1
Cancel 8-cycle noise.
1
0
Cancel 16-cycle noise.
1
1
Cancel 32-cycle noise.
DCK2 DCK1 DCK0
Operating clock selection bit
0
0
0
φ (41.7 ns, φ = 24 MHz)
0
0
1
φ/2 (83.3 ns, φ = 24 MHz)
0
1
0
φ/4 (167 ns, φ = 24 MHz)
0
1
1
φ/8 (333 ns, φ = 24 MHz)
1
0
0
φ/16 (0.67 µs, φ = 24 MHz)
1
0
1
φ/32 (1.33 µs, φ = 24 MHz)
1
1
0
φ/64 (2.67 µs, φ = 24 MHz)
1
1
1
Prohibited
φ: Machine clock
NRSL
Noise cancellation function enable bit
0
DTTI input does not go thru the noise cancellation circuit.
1
DTTI input goes thru the noise cancellation circuit.
DTTI interrupt flag bit
DTIF
R/W : Read and Write
Read
Write
0
No interrupt request
Clear this bit
1
Has interrupt request
No effect
DTIE
DTTI input enable bit
0
Disable DTTI input
1
Enable DTTI input
: Initial value
Figure 14.4.10-1 Waveform control register (SIGCR)
398
MB90820 series
Table 14.4.10-1Waveform control register (SIGCR)
Bit name
bit15
bit14
MB90820 series
DTIE:
DTTI input
enable bit
DTIF:
DTTI interrupt
flag bit
Function
• This bit is used to enable the DTTI pin to control the output level of
RTO0 ~ 5 pin.
• This bit is an interrupt flag for DTTI.
• When DTTI input is enabled (DTIE=1) and low level of DTTI is
detected, this bit will be set and interrupt request will send to CPU.
• Writing “0” will clear this bit.
• Writing “1” has no effect.
• In read-modify-write operation, “1” is always read.
Note: If noise cancellation function is enabled (NRSL=1), this
bit will be set to “1” when noise pulse width is passed.
Note: If both software clear (writing “0”) and hardware set
(low level of DTTI is detected) occurs simultaneously,
software clear takes the higher priority to clear this bit.
• This bit is used to enable the noise cancellation function.
• Noise cancellation circuit will receive DTTI input signal when the low
level is held until the counter overflows. The counter is n-bit counter
which is operated by the low level input. The value of n can be 2, 3, 4
and 5 which depends on the setting of NWS1 and NWS0.
bit13
NRSL:
Noise
cancellation
function
enable bit
bit12
bit11
bit10
DCK2 ~ 0:
Operating clock
selection bit
• These bits are used to select the operating clock for the 16-bit timer.
bit9
bit8
NWS1 ~ 0:
DTTI Noise
width selection
bits
• These bits are used to select the noise pulse width to be removed for
DTTI pin.
Note: To cancel the noise pulse width, it takes approximately
2n machine cycles.
Note: When the noise cancellation circuit is selected, the
input will become invalid in a mode such as STOP
mode in which the internal clock is stopped.
399
14.5 Multi-functional Timer Interrupts
The multi-functional timer is enabled to generate interrupts in 16-bit free-running timer,
16-bit output compare, 16-bit input capture and waveform generator.
■ 16-bit free-running timer interrupts
Table 14.5-1 lists the interrupt control bits and interrupt causes of the 16-bit free-running timer.
Table 14.5-1 Interrupt control bits and interrupt causes of the 16-bit free-running timer
16-bit free-running timer
Compare Clear
Zero Detect
Interrupt request flag bit
TCCSH:ICLR
TCCSH:IRQZF
Interrupt request enable bit
TCCSH:ICRE
TCCSH:IRQZE
Interrupt cause
16-bit free-running timer value
matches with compare clear
register (CPCLR)
16-bit free-running timer value
equals zero
In the 16-bit free-running timer, the ICLR bit of the timer control status register (TCCSH) is set to
1 when timer value matches compare clear register (CPCLR). If an interrupt request is enabled
(TCCSH:ICRE = 1) in this operation, the interrupt request is output to the interrupt controller.
The IRQZF bit of the timer control status register (TCCSH) is set to 1 when timer value equals
0000H. If an interrupt request is enabled (TCCSH:IRQZE = 1) in this operation, the interrupt
request is output to the interrupt controller.
■ 16-bit free-running timer interrupts and EI²OS
Table 14.5-2 lists the 16-bit free-running timer interrupts and EI²OS.
Table 14.5-2 16-bit free-running timer interrupts and EI²OS
Channel
Interrupt
number
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
Compare clear *1
#34 (22H)
ICR11
0000BBH
FFFF74H
FFFF75H
FFFF76H
Zero detect *2
#31 (1FH)
ICR10
0000BAH
FFFF80H
FFFF81H
FFFF82H
∆
*1: The same interrupt control register as that for 16-bit free-running timer compare clear is
assigned to 16-bit input capture channels 0/1.
*2:
400
The same interrupt control register as that for 16-bit free-running timer zero detect is
assigned to 16-bit PPG timer 2.
MB90820 series
■ 16-bit output compare interrupts
Table 14.5-3 lists the interrupt control bits and interrupt causes of the 16-bit output compare.
Table 14.5-3 Interrupt control bits and interrupt causes of the 16-bit output compare 0~5
16-bit output compare
0/1
16-bit output compare
2/3
16-bit output compare
4/5
Interrupt request flag
bit
OCS0:IOP0/1
OCS2:IOP0/1
OCS4:IOP0/1
Interrupt request
enable bit
OCS0:IOE0/1
OCS2:IOE0/1
OCS4:IOE0/1
Interrupt cause
16-bit free-running
timer value matches
with output compare
register (OCCP0/1)
16-bit free-running
timer value matches
with output compare
register (OCCP2/3)
16-bit free-running
timer value matches
with output compare
register (OCCP4/5)
In the 16-bit output compare, the IOP0/1 bit of the compare control register (OCS0/2/4) is set to
1 when 16-bit free-running timer value matches output compare register (OCCP0~5). If an
interrupt request is enabled (OCS0/2/4:IOE0/1 = 1) in this operation, the interrupt request is
output to the interrupt controller.
■ 16-bit output compare interrupts and EI²OS
Table 14.5-4 lists the 16-bit output compare interrupts and EI²OS
Table 14.5-4 16-bit output compare interrupts and EI²OS
Interrupt
number
Channel
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
Output compare 0 match
*1
#12 (0CH)
ICR00
0000B0H
FFFFCCH
FFFFCDH
FFFFCEH
Output compare 1 match
*2
#15 (0FH)
ICR02
0000B2H
FFFFC0H
FFFFC1H
FFFFC2H
Output compare 2 match
*3
#17 (11H)
ICR03
0000B3H
FFFFB8H
FFFFB9H
FFFFBAH
Output compare 3 match
*4
#19 (13H)
ICR04
0000B4H
FFFFB0H
FFFFB1H
FFFFB2H
Output compare 4 match
*5
#21 (15H)
ICR05
0000B5H
FFFFA8H
FFFFA9H
FFFFAAH
Output compare 5 match
*6
#23 (17H)
ICR06
0000B6H
FFFFA0H
FFFFA1H
FFFFA2H
O
*1: The same interrupt control register as that for 16-bit output compare 0 is assigned to A/D conversion
termination.
*2: The same interrupt control register as that for 16-bit output compare 1 is assigned to 16-bit PPG timer
1.
*3: The same interrupt control register as that for 16-bit output compare 2 is assigned to 16-bit reload timer
1 underflow.
*4: The same interrupt control register as that for 16-bit output compare 3 is assigned to DTP/external
interrupt channels 0/1 detection / DTTI.
*5: The same interrupt control register as that for 16-bit output compare 4 is assigned to DTP/external
interrupt channels 2/3 detection.
*6: The same interrupt control register as that for 16-bit output compare 5 is assigned to PWC timer 1.
MB90820 series
401
■ 16-bit input capture interrupts
Table 14.5-5 lists the interrupt control bits and interrupt causes of the 16-bit input capture.
Table 14.5-5 Interrupt control bits and interrupt causes of the 16-bit input capture 0~3
16-bit input capture 0/1
16-bit input capture 2/3
Interrupt request flag bit
PICSL01:ICP0/1
ICSL23:ICP2/3
Interrupt request enable bit
PICSL01:ICE0/1
ICSL23:ICE2/3
Interrupt cause
Valid edge is detected in IN0/1
Valid edge is detected in IN2/3
In the 16-bit input capture, the ICP0/1/2/3 bit of the input capture control register (PICSL01/
ICSL23) is set to 1 when valid edge is detected in IN0/1/2/3. If an interrupt request is enabled
(PICSL01/ICSL23:ICE0/1 = 1) in this operation, the interrupt request is output to the interrupt
controller.
■ 16-bit input capture interrupts and EI²OS
Table 14.5-6 lists the 16-bit input capture interrupts and EI²OS.
Table 14.5-6 16-bit input capture interrupts and EI²OS
Channel
Interrupt
number
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
Input capture 0/1 *1
#33 (21H)
ICR11
0000BB H
FFFF78H
FFFF79H
FFFF7AH
Input capture 2/3 *2
#35 (23H)
ICR12
0000BC H
FFFF70H
FFFF71H
FFFF72H
O
*1: The same interrupt control register as that for 16-bit input capture 0/1 is assigned to 16-bit
free-running timer compare clear.
*2:
The same interrupt control register as that for 16-bit input capture 2/3 is assigned to
Timebase timer.
■ Waveform generator interrupts
Table 14.5-7 lists the interrupt control bits and interrupt causes of the waveform generator.
Table 14.5-7 Interrupt control bits and interrupt causes of the waveform generator
Waveform generator
16-bit timer 0/1/2
DTTI
Interrupt request flag bit
DTCR0/1/2:TMIF
SIGCR:DTIF
Interrupt request enable bit
DTCR0/1/2:TMIE
--
Interrupt cause
16-bit timer 0/1/2 underflow
Low level is detected in DTTI
In the waveform generator, the TMIF bit of the 16-bit timer control register (DTCR0/1/2) is set to
1 when 16-bit timer underflow and DTCR0/1/2:TMD2~0=000B or 001B. If an interrupt request is
enabled (DTCR0/1/2:TMIE = 1) in this operation, the interrupt request is output to the interrupt
controller.
402
MB90820 series
■ Waveform generator interrupts and EI²OS
Table 14.5-8 lists the waveform generator interrupts and EI²OS.
Table 14.5-8 Waveform generator interrupts and EI²OS
Channel
Interrupt
number
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
16-bit timer 0/1/2
underflow *1
#29 (1DH)
ICR09
0000B9H
FFFF88H
FFFF89H
FFFF8A H
DTTI *2
#20 (14H)
ICR04
0000B4H
FFFFACH
FFFFADH
FFFFAE H
∆
*1: The same interrupt control register as that for 16-bit timer 0/1/2 underflow is assigned to 16bit reload timer 0 underflow.
*2: The same interrupt control register as that for DTTI is assigned to DTP/external interrupt
channels 0/1 detection and 16-bit output compare 3.
■ EI²OS function of the multi-functional timer
Since the multi-functional timer has a circuit that coordinates with EI2OS, the interrupt generated
can start EI2OS.
However, EI2OS is available only when other peripheral functions sharing the interrupt control
register (ICR) do not use interrupts. For example, when 16-bit free-running timer compare clear
uses EI²OS, interrupts of 16-bit input capture channels 0/1 must be disabled.
MB90820 series
403
14.6 Operation of Multi-functional Timer
This section describes the operation of the multi-functional timer.
■ Operation of multi-functional timer
● 16-bit free-running timer
The 16-bit free-running timer starts counting up from value set in timer data register (TCDT) after
a reset has been completed. The counter value is used as the reference time for 16-bit output
compare and 16-bit input capture.
● 16-bit output compare
The 16-bit output compare is used to compare the value set in the specified output compare
register with the value of the 16-bit free-running timer. If a match is detected, the interrupt flag is
set and the output level is inverted.
● 16-bit input capture
The 16-bit input capture is used to detect a specified valid edge. If a valid edge is detected, the
interrupt flag is set and the value of 16-bit free-running timer is fetched and stored into the input
capture data register.
● Waveform generator
Waveform generator can produce various waveform such as dead-time, by using the realtime
outputs (RT0 ~ 5), 16-bit PPG timer 0 and 16-bit timers.
404
MB90820 series
14.6.1 Operation of 16-bit free-running timer
The 16-bit free-running timer starts counting up from counter value specified in timer
data register (TCDT) after a reset has been completed. The counter value is used as the
reference time for 16-bit output compare and 16-bit input capture.
■ Timer clear
The counter value of 16-bit free-running timer is cleared in the following conditions:
•
•
•
•
When a match with compare clear register is detected in up-count mode (TCCSL:MODE=0)
When “1” is written to the SCLR bit of the TCCSL register during operation. The timer will be
cleared at the valid edge of count clock.
Note : If writing “0” to the SCLR bit before a valid edge of count clock, the SCLR bit is cleared
and the timer would not be cleared to “0000”
When “0000H” is written to the TCDT register during stop.
Reset
By a reset, the counter is immediately cleared. By a software clear or a match with compare clear
register, the counter is cleared in synchronization with the count timing. If the
Compare
register value
N
Compare match
cleared by hardward
writing “1”
writing “1”
writing “0”
TCCS : SCLR
Counter value
N -1
N
0000
0001
0000
0001
0002
Figure 14.6.1-1 16-bit free-running timer clear timing
■ Timer mode
Two count modes can be selected in 16-bit free-running timer
•
up-count mode (TCCSL:MODE=0)
•
up-down count mode (TCCSL:MODE=1)
In up-count mode, counter starts counting from pre-set timer data register (TCDT), counts up until
counter value matches value of compare clear register (CPCLR), then counter is cleared to 0000H and
then counts up again.
In up-down count mode, counter starts counting from pre-set timer data register (TCDT), counts up
until counter value matches value of compare clear register (CPCLR), then counter changes from upcount to down-count, counts down until counter value reaches “0000 H” and then counts up again.
MB90820 series
405
There is a buffer in mode bit, TCCSL:MODE, it can be written at any time no matter the timer is
operating or stopped. While the timer is operating, value written to this bit is buffered and the count
mode will be changed when timer value is “0000H”.
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000 H
Reset
Timer starts
Change to up-down mode
Compare clear
buffer register
Change to up mode
BFFFH
TCCSL:MODE
Figure 14.6.1-2 Change timer mode while timer is operating
■ Compare clear buffer
There is a selected buffer function on compare clear register (CPCLR). In buffer enable
(TCCSL:BFE=1), data written in compare clear buffer register (CPCLRB) will transfer to CPCLR at zero
detection of the 16-bit free-running timer. In buffer disable (TCCSL:BFE=0), CPCLRB is transparent,
data can directly be written into CPCLR.
Counter value
FFFF H
BFFF H
7FFF H
3FFF H
0000H
Time
Timer starts
Reset
Compare clear
buffer register
value
Compare clear
register value
Zero detect
Zero detect
BFFFH
BFFFH
7FFFH
7FFFH
FFFFH
FFFFH
Figure 14.6.1-3 Operation in up-count mode with compare clear buffer is disabled (TCCSL:BFE=0)
406
MB90820 series
Counter value
FFFF H
BFFF H
7FFF H
3FFF H
0000 H
Time
Timer starts
Zero detect
Reset
Compare clear
buffer register
value
Compare clear
register value
Zero detect
FFFFH
7FFFH
BFFFH
7FFFH
BFFFH
FFFFH
Figure 14.6.1-4 Operation in up-count mode with compare clear buffer is enabled (TCCSL:BFE=1)
Counter value
FFFFH
Compare clear match
BFFFH
7FFFH
3FFFH
Time
0000 H
Timer starts
Zero detect
Reset
Compare clear
buffer register
value
Compare clear
register value
BFFFH
7FFFH
BFFFH
FFFFH
7FFFH
FFFFH
Figure 14.6.1-5 Operation in up-down count mode with compare clear buffer enabled (TCCSL:BFE=1)
■ Timer interrupts
Two interrupts can be generated from 16-bit free-running timer:
•
Compare clear interrupt
•
Zero detect interrupt
Compare clear interrupt is generated when the timer value matches compare clear register (CPCLR).
Zero detect interrupt is generated when the timer value reaches “0000 H”.
Note:
MB90820 series
Software clear (TCCSL:SCLR=1) will not generate zero detect interrupt.
407
Counter value
N-1
N
0
1
Compare clear interrupt
Zero detect interrupt
Figure 14.6.1-6 Interrupts generated in up-count mode (TCCSL:MODE=0)
Counter value
N-1
N
N-1
0
Compare clear interrupt
Zero detect interrupt
Figure 14.6.1-7 Interrupts generated in up-down count mode (TCCSL:MODE=1)
■ Interrupt mask function
The number of times of Interrupt source can be masked by setting TCCSH:MSI2~0. MSI2~0 configure
a 3-bit reload down counter, which reloads when its count value reaches “000B”. Count value can also
be loaded by writing directly to MSI2~0. The mask count equals the value set in MSI2~0 and there is
no interrupt source will be masked when MSI2~0 equals “000 B”
The interrupt source depends on the count mode (TCCSL:MODE). In up-count mode, only compare
clear interrupt can be masked, zero detect interrupt is generated in every zero detection. In up-down
count mode, only zero detect interrupt can be masked, compare clear interrupt is generated in every
compare clear.
Note:
408
Software clear (TCCSL:SCLR=1) will not generate zero detection.
MB90820 series
Counter value
2nd
1st
FFFFH
Compare clear match
3rd
4th
6th
5th
BFFFH
7FFFH
3FFFH
Time
0000 H
Timer starts
Reset
Zero detect interrupt
Software
clear
Compare
clear
interrupt
TCCSH:MSI2:0=000B
TCCSH:MSI2:0=001B
TCCSH:MSI2:0=010B
* Both zero detect interrupt and compare clear interrupt are software cleared
Figure 14.6.1-8 Compare clear interrupt masked in up-count mode
Counter value
2nd
1st
FFFFH
Compare clear match
3rd
4th
6th
5th
BFFFH
7FFFH
3FFFH
Time
0000 H
Timer starts
1st
Reset
2nd
Zero detect
3rd
4th
5th
6th
Compare clear interrupt
Zero
detect
interrupt
Software
clear
TCCSH:MSI2:0=000B
TCCSH:MSI2:0=001 B
TCCSH:MSI2:0=010B
* Both zero detect interrupt and compare clear interrupt are software cleared
Figure 14.6.1-9 Zero detect interupt masked in up-down count mode
MB90820 series
409
14.6
Operation of Multi-functional Timer
■ External count clock selected
The 16-bit free-running timer is incremented based on the input clock (internal or external clock). When
external clock is selected, the 16-bit free-running timer counts up at a rising edge when the initial value
of external input is “1” or at a falling edge when initial value of external clock input is “0” after external
clock mode is selected (TCCSH:ECKE=1).
External clock
input
TCCSH:ECKE
Count clock
Counter value
N
N+1
Figure 14.6.1-10 16-bit free-running timer count timing
410
MB90820 series
14.6.2 Operation of 16-bit Output Compare
The output compare unit is used to compare the value set in the specified compare
register with the value of the 16-bit free-running timer. If a match is detected, the
interrupt flag is set and the output level is inverted.
■ 16-bit output compare operation
a) Compare operation can be performed for individual channel (OCS1/3/5:CMOD = “0”)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
RT1
Compare 0
interrupt
Compare 1
interrupt
Figure 14.6.2-1 Sample output waveform when compare registers 0 and 1 are used individually when
the initial output value is “0” (free-running timer in up-count mode).
MB90820 series
411
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
RT1
Compare 0
interrupt
Compare 1
interrupt
Figure 14.6.2-2 Sample output waveform when compare registers 0 and 1 are used individually when
the initial output value is “0” (free-running timer in up-down count mode).
b) Output level can be changed by using a pair of compare registers (OCS1/3/5:CMOD = ”1”)
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
Time
0000H
Reset
Compare register 0
value
Compare register 1
value
RT0
RT1
BFFFH
7FFFH
associated with compare 0
associated with compare 0 & 1
Compare 0
interrupt
Compare 1
interrupt
Figure 14.6.2-3 Sample output waveform when compare registers 0 and 1 are used in a pair when the
initial output value is “0” (free-running timer in up-count mode).
412
MB90820 series
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Reset
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
associated with compare 0
associated with compare 0 &1
RT1
Compare 0
interrupt
Compare 1
interrupt
Figure 14.6.2-4 Sample output waveform when compare register 0 and 1 are used in a pair when the
initial output value is “0” (free-running timer in up-down count mode).
c) Output level when compare buffer is disabled
Counter value
FFFF H
BFFF H
7FFF H
3FFF H
0000 H
Time
Timer starts
Reset
Compare clear match
Compare clear match
Compare buffer
register 0 value
BFFFH
3FFFH
BFFFH
Compare
register 0 value
BFFFH
3FFFH
BFFFH
RT0
Interrupt
Figure 14.6.2-5 Sample output waveform when compare buffer is disabled (free-running timer in upcount mode).
MB90820 series
413
d) Output level when compare buffer is selected at compare clear match
Counter value
FFFFH
BFFFH
7FFFH
3FFFH
0000H
Time
Zero detection
Timer starts
Reset
Compare buffer
register 0 value
Compare
register 0 value
Compare clear match
BFFFH
BFFFH
BFFFH
3FFFH
3FFFH
3FFFH
BFFFH
RT0
Interrupt
Figure 14.6.2-6 Sample output waveform when compare buffer is enable (free-running timer in updown count mode).
414
MB90820 series
■ 16-bit output compare timing
When the free-running timer matches the value set in the compare register, the output compare
unit generates a compare match signal to invert the output and generate an interrupt. When a
compare match occurs, the output is inverted in synchronization with the count timing of the
counter.
Note:When the compare register is updated, comparison with the counter value is not
performed.
Counter value
N
N+1
N+2
N+3
No match signal is generated.
Compare
register 0 value
Compare
register 0 write
Compare
register 1 value
Compare
register 1 write
N+1
M
N+3
L
Compare 0 stop
Compare 1 stop
Figure 14.6.2-7 Compare operation upon update of compare registers
Counter value
N
N+1
Compare
register
value
N
Compare
match
Interrupt
Figure 14.6.2-8 Compare interrupt timing
Counter value
Compare
register
value
N
N+1
N
N+1
N
Compare
match
signal
Pin output
Figure 14.6.2-9 Output pin change timing
MB90820 series
415
14.6.3 Operation of 16-bit Input Capture
The input capture unit is used to detect a specified valid edge. If a valid edge is
detected, the interrupt flag is set and the value of 16-bit free-running timer is loaded
into the capture register.
■ 16-bit input capture operation
Counter value
FFFF H
BFFF H
7FFF H
3FFF H
0000H
Time
Reset
IN0
IN1
IN example
Capture register 0
Undefined
Capture register 1
Capture register
example
Capture 0 interrupt
Undefined
Undefined
3FFFH
7FFFH
BFFFH
3FFF H
Capture 1 interrupt
Capture example
interrupt
Interrupt is generated
with another valid edge
Note: Capture 0: Rising edge
Capture 1: Falling edge
Capture example: Both edges
Interrupt is cleared
by software
Figure 14.6.3-1 Sample input capture timing
416
MB90820 series
14.6
Operation of Multi-functional Timer
■ 16-bit input capture input timing
Machine clock
Counter value
Input capture
input
N
N+1
Valid edge
Capture signal
Capture register
N+1
Interrupt
Figure 14.6.3-2 16-bit input capture timing for input signals
MB90820 series
417
14.6.4 Operation of Waveform Generator
Waveform generator can produce various waveform such as dead-time, by using the
realtime outputs (RT0 ~ 5), 16-bit PPG timer 0 and 16-bit timers 0/1/2.
■ Output condition of RTO0~5 and GATE
Table 14.6.4-1 Output condition of RTO0~5, GATE and register bit setting
TMD2 TMD1 TMD0 GTENx PGENx
RTOx
GATE
0
0
0
X
X
Realtime output, RTx
Always “0”
0
0
1
X
0
Realtime output, RTx
OR(RTx & GTENx)
0
0
1
0
1
PPG0 output pulse when RTx is high
Always “0”
0
0
1
1
1
Gate triggered PPG0 output pulse when RTx is high OR(RTx)
Output “H” from rising edge of RTx to 16-bit timer 0
underflow (x=0,1)
0
1
0
X
0
Output “H” from rising edge of RTx to 16-bit timer 1
underflow (x=2,3)
OR(RTOx & GTENx)
Output “H” from rising edge of RTx to 16-bit timer 2
underflow (x=4,5)
PPG0 output pulse from rising edge of RTx to 16-bit
timer 0 underflow (x=0,1)
0
1
0
0
1
PPG0 output pulse from rising edge of RTx to 16-bit
timer 1 underflow (x=2,3)
Always “0”
PPG0 output pulse from rising edge of RTx to 16-bit
timer 2 underflow (x=4,5)
0
1
0
1
1
Gate triggered PPG0 output pulse from rising edge of OR(output “H” from
RTx to 16-bit timer 0 underflow (x=0,1)
RTx/y/z rising edge
to timer 0/1/2
Gate triggered PPG0 output pulse from rising edge of
underflow)
RTx to 16-bit timer 1 underflow (x=2,3)
x=0,1
Gate triggered PPG0 output pulse from rising edge of y=2,3
z=4,5
RTx to 16-bit timer 2 underflow (x=4,5)
Generate non-overlap signal by RT1 (x=0,1) *1
1
0
0
X
X
Generate non-overlap signal by RT3 (x=2,3) *1
Always “0”
Generate non-overlap signal by RT5 (x=4,5) *1
1
1
1
0
X
Generate non-overlap signal by PPG0
1
1
1
1
X
Generate non-overlap signal by gate triggered PPG0 OR(RTx)
Others
Always “0”
Always “0”
Always “0”
*1 In order to generate non-overlap signal, be sure to select 2-channel mode for RT1/3/5 (OCS1/3/
5:CMOD=1)
*2 RTO0/1 is controlled by DTCR0:TMD2~0, RTO2/3 is controlled by DTCR1:TMD2~0 and RTO4/5 is
418
MB90820 series
controlled by DTCR2:TMD2~0.
MB90820 series
419
■ PPG0 output control
PPG0 output to RTO0~5 can be enabled by PGEN0~5 in PPG ouptut control/input capture control
status register (PICSH01).
■ Gate triggered PPG0 output
In waveform generator, a GATE signal can be generated by using realtime outputs RT0~5 or cope with
16-bit timers 0/1/2 to trigger PPG0 counting. When 16-bit timer is used, two real-time outputs RT0/2/4
and RT1/3/5 is operated with one 16-bit timer 0/1/2 to generate six individual gate signal. And these six
gate signals are logically OR to generate a GATE signal to trigger PPG0 counting.
If PGEN0~5 signal is also used, six different waveforms can be output to RTO0~5 by using one PPG0
only.
■ Generating GATE signal during each RTx is at “H” level when GTENx is active
(DTCR0/1/2:TMD2~0=001B or 111B)
16-bit free-running timer
FFFFH
BFFF H
Count value
7FFF H
3FFF H
Time
0000H
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
RT1
GATE0
GATE1
GATE
Figure 14.6.4-1 Generating GATE signal during RTx is at “H” level
420
MB90820 series
14.6
Operation of Multi-functional Timer
■ Generating GATE signal from rising edge of each RTx until 16-bit timer 0/1/2 underflow when GTENx is
active (DTCR0/1/2:TMD2~0=010B)
16-bit free-running timer
FFFFH
BFFF H
Count value
7FFF H
3FFF H
Time
0000H
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
RT1
GATE0
GATE1
Time of
16-bit timer 0
Time of
16-bit timer 0
GATE
Figure 14.6.4-2 Generating GATE signal from rising edge of RTx until 16-bit timer underflow
Note: Each 16-bit timer is used for two RTs. i.e. 16-bit timer 0 is used for RT0 and RT1; 16-bit timer 1 is used
for RT2 and RT3; 16-bit timer 2 is used for RT4 and RT5. Therefore, do not use an RT and attempt to
start the corresponding timer that is already operating. Doing so may cause that the outputting GATE
signal will be extended and malfunction will be occurred.
MB90820 series
421
14.6.4
Operation of Waveform Generator
14.6.4.1 Operation in Timer Mode
With RT0~5 rising edge, the 16-bit timer is reloaded, starts down-counting and the PPG
timer 0 keeps outputting to RTO0~5 until the 16-bit timer is underflow.
■ PPG0 output pulse from rising edge of RT to 16-bit timer underflow (DTCR0/1/2:TMD2~0=010B)
Setting up registers:
• PCSR
: XXXXH
• TCDT
: 0000H
• PDUT
: XXXXH
• TCCS
: XXXXXXXXXX0X0XXX B
• CPCLR
: XXXXH (Cycle setting)
• PCNT
: XXXXH
• OCCP0 ~ 5 : XXXXH (Compare value)
• PICS01
: XXH (PPG0 output selection)
• OCS0 ~ 5 : -XX0XXXXXXXXXX11B
• DTCR0 ~ 2 : 011XX010B
• TMRR0 ~ 2 : XXXXH (Non-overlap timing setting)
• SIGCR
: XXXXXX00 B (DTTI input and 16-bit timer count clock setting)
Note: “X” must be set according to the operation.
16-bit free-running timer
FFFF H
Count
value
BFFFH
7FFF H
3FFF H
0000H
Time
PPG0
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT0
RT1
GATE
RTO0
RTO1
Time of
16-bit timer 0
Time of
16-bit timer 0
Figure 14.6.4.1-1 Waveform generated when TMD2~0=010B
Note: Each 16-bit timer is used for two RTs. i.e. 16-bit timer 0 is used for RT0 and RT1; 16-bit timer 1 is used for RT2
and RT3; 16-bit timer 2 is used for RT4 and RT5. Therefore, do not use an RT and attempt to start PPG0 which is
under operation. Doing so may cause that the outputting GATE signal will be extended and malfunction will be
occurred.
422
MB90820 series
Memo
MB90820 series
423
14.6.4.2 Operation in Dead-time Timer Mode
The dead-time generator will input the realtime output (RT1/3/5), select PPG timer 0
pulse output, and output non-overlap signals (inverted signals) to external pins
(RTO0~5).
■ Making non-overlap signals by using RT1/3/5 in normal polarity (DTCR0/1/2:TMD2~0=100B)
When selecting non-overlap signal for an active level “0” (normal polarity) in DTCR0/1/2:DMOD, a
delay corresponding to the non-overlap time set in the TMRR0/1/2 register (16-bit timer register) is
applied. The delay is applied at a rising edge of RT1/3/5 or its falling edge. If RT1/3/5 pulse width is
smaller than the set non-overlap time, the 16-bit timer will restart down-counting from TMRR0/1/2 value
at the next RT’s edge.
Setting up registers:
• CPCLR
: XXXXH (Cycle setting)
• TCDT
: 0000H
• OCS0 ~ 5 : -XX1XXXXXXXXXX11B
• TCCS
: X--XXXXXX0X0XXXB
• DTCR0 ~ 2 : 0XXXX100B
• OCCP0 ~ 5 : XXXXH (Compare value)
• TMRR0 ~ 2 : XXXXH (Non-overlap timing setting)
• SIGCR
: XXXXXXXXB (DTTI input and 16-bit timer count clock setting)
Note: “X” must be set according to the operation.
16-bit timer 0
TMRR0 set value
Count
value
RT1
RTO0 (U)
RTO1 (X)
1 machine cycle
Pin name
1.5 machine cycle
Output signal
RTO0 (U)
Signal with delay is applied at RT1 rising edge
RTO2 (V)
Signal with delay is applied at RT3 rising edge
RTO4 (W)
Signal with delay is applied at RT5 rising edge
RTO1 (X)
Inverted signal with delay is applied at RT1 falling edge
RTO3 (Y)
Inverted signal with delay is applied at RT3 falling edge
RTO5 (Z)
Inverted signal with delay is applied at RT5 falling edge
Figure 14.6.4.2-1 Non-overlap signal generation by RT1/3/5 in normal polarity
424
MB90820 series
■ Making non-overlap signals by using RT1/3/5 in inverted polarity (DTCR0/1/2:TMD2~0=100B)
When selecting non-overlap signal for an active level “1” (inverted polarity) in DTCR0/1/2:DMOD, a
delay corresponding to the non-overlap time set in the TMRR0/1/2 register (16-bit timer register) is
applied. The delay is applied at a rising edge of RT1/3/5 or its falling edge. If RT1/3/5 pulse width is
smaller than the set non-overlap time, the 16-bit timer will restart down-counting from TMRR0/1/2 value
at the next RT’s edge.
Setting up registers:
• TCDT
: 0000 H
• CPCLR
: XXXX H (Cycle setting)
• TCCS
: XXXXXXXXXX0X0XXXB
• OCS0 ~ 5 : -XX1XXXXXXXXXX11 B
• OCCP0 ~ 5 : XXXXH (Compare value)
• DTCR0 ~ 2 : 1XXXX100B
• TMRR0 ~ 2 : XXXXH (Non-overlap timing setting)
• SIGCR
: XXXXXXXXB (DTTI input and 16-bit timer count clock setting)
Note: “X” must be set according to the operation.
16-bit timer 0
TMRR0 set value
Count
value
RT1
RTO0 (U)
RTO1 (X)
1 machine cycle
Pin name
1.5 machine cycle
Output signal
RTO0 (U)
Inverted signal with delay is applied at RT1 rising edge
RTO2 (V)
Inverted signal with delay is applied at RT3 rising edge
RTO4 (W)
Inverted signal with delay is applied at RT5 rising edge
RTO1 (X)
Signal with delay is applied at RT1 falling edge
RTO3 (Y)
Signal with delay is applied at RT3 falling edge
RTO5 (Z)
Signal with delay is applied at RT5 falling edge
Figure 14.6.4.2-2 Non-overlap signal generation by RT1/3/5 in inverted polarity
MB90820 series
425
14.6.4
Operation of Waveform Generator
■ Making non-overlap signals by using PPG in normal polarity (DTCR0/1/2:TMD2~0=111 B)
When selecting non-overlap signal for an active level “0” (normal polarity) in DTCR0/1/2:DMOD, a
delay corresponding to the non-overlap time set in the TMRR0/1/2 register (16-bit timer register) is
applied. The delay is applied at a rising edge of PPG timer 0 pulse signal or its inverted signal. If PPG
timer pulse width is smaller than the set non-overlap time, the 16-bit timer will start down-counting from
TMMR0/1/2 value at the next edge of PPG0 pulse.
Setting up registers:
• PCSR
: XXXXH
• TCDT
: 0000H
•
PDUT
: XXXXH
• TCCS
: XXXXXXXXXX0X0XXXB
• PCNT
: XXXXH
• CPCLR
: XXXXH (Cycle setting)
• OCCP0 ~ 5 : XXXXH (Compare value)
• OCS0 ~ 5 : -XX1XXXXXXXXXX11B
• DTCR0 ~ 2 : 0XXXX111B
• TMRR0 ~ 2 : XXXXH (Non-overlap timing setting)
• SIGCR
: XXXXXXXXB (DTTI input and 16-bit timer count clock setting)
Note: “X” must be set according to the operation.
16-bit timer 0
TMRR0 set value
Count
value
PPG0
RTO0 (U)
RTO1 (X)
1 machine cycle
Pin name
1.5 machine cycle
Output signal
RTO0 (U)
Signal with delay is applied at PPG0 rising edge
RTO2 (V)
Signal with delay is applied at PPG0 rising edge
RTO4 (W)
Signal with delay is applied at PPG0 rising edge
RTO1 (X)
Inverted signal with delay is applied at PPG0 falling edge
RTO3 (Y)
Inverted signal with delay is applied at PPG0 falling edge
RTO5 (Z)
Inverted signal with delay is applied at PPG0 falling edge
Figure 14.6.4.2-3 Non-overlap signal generation by PPG0 in normal polarity
426
MB90820 series
■ Making non-overlap signals by using PPG in inverted polarity (DTCR0/1/2:TMD2~0=111B)
When selecting non-overlap signal for an active level “1” (inverted polarity) in DTCR0/1/2:DMOD, a
delay corresponding to the non-overlap time set in the TMRR0/1/2 register (16-bit timer register) is
applied. The delay is applied at a rising edge of PPG timer 0 pulse signal or its inverted signal. If PPG
timer 0 pulse width is smaller than the set non-overlap time, the 16-bit timer will start down-counting
from TMMR0/1/2 value at the next edge of PPG0 pulse.
Setting up registers:
• PCSR
: XXXXH
• TCDT
: 0000H
• PDUT
: XXXXH
• TCCS
: XXXXXXXXXX0X0XXXB
• PCNT
: XXXXH
• CPCLR
: XXXXH (Cycle setting)
• OCCP0 ~ 5 : XXXXH (Compare value)
• OCS0 ~ 5 : -XX1XXXXXXXXXX11B
• DTCR0 ~ 2 : 1XXXX111B
• TMRR0 ~ 2 : XXXXH (Non-overlap timing setting)
• SIGCR
: XXXXXXXXB (DTTI input and 16-bit timer count clock setting)
Note: “X” must be set according to the operation.
16-bit timer 0
TMRR0 set value
Count
value
PPG0
RTO0 (U)
RTO1 (X)
1 machine cycle
Pin name
1.5 machine cycle
Output signal
RTO0 (U)
Inverted signal with delay is applied at PPG0 rising edge
RTO2 (V)
Inverted signal with delay is applied at PPG0 rising edge
RTO4 (W)
Inverted signal with delay is applied at PPG0 rising edge
RTO1 (X)
Signal with delay is applied at PPG0 falling edge
RTO3 (Y)
Signal with delay is applied at PPG0 falling edge
RTO5 (Z)
Signal with delay is applied at PPG0 falling edge
Figure 14.6.4.2-4 Non-overlap signal generation by PPG0 in inverted polarity
MB90820 series
427
14.6.4.3 Operation of DTTI Pin Control
By setting “1” to waveform control register, SIGCR: bit 7 (DTIE), the output of RTO0 ~ 5
can be controlled by the DTTI pin. When “L” level in DTTI is detected, the output of
RTO0 ~ 5 will be fixed to an inactive level until the interrupt flag, SIGCR: bit 6 (DTIF) is
cleared. The inactive level of RTO0 ~ 5 can be set by PDR8 in port 8 by software.
■ DTTI pin input operation
Even when the “L” level of DTTI pin input is detected, the timer will keep running for the waveform
generator operation, but no waveform will outputted to external pins P82/RTO0~P87/RTO5.
Setting up registers:
• TCDT
: 0000H
• CPCLR
: XXXX H (Cycle setting)
• TCCS
: XXXXXXXXXX0X0XXX B
• OCS0 ~ 5 : -XX1XXXXXXXXXX11 B
• OCCP0 ~ 5 : XXXXH (Compare value)
• DTCR0 ~ 2 : 0XXXX100B
• PDR3
: XXXXXX00 B (Inactive level setting)
• TMRR0 ~ 2 : XXXXH (Non-overlap timing setting)
• SIGCR
: 1XXXXXXX B (DTTI input and 16-bit timer count clock setting)
Note: “X” must be set according to the operation.
16-bit free-running timer
FFFFH
Count value
BFFF H
7FFF H
3FFF H
Time
0000H
Compare register 0
value
BFFFH
Compare register 1
value
7FFFH
RT1
RTO0
RTO1
DTTI
DTIF
Output inactive
Software Clear
Figure 14.6.4.3-1 Operation when DTTI input is enabled
428
MB90820 series
■ DTTI pin noise cancellation function
By setting bit 5 (NRSL) of the waveform control register (SIGCR) to “1”, the noise cancellation function
for DTTI pin input is enabled. When noise cancellation function is enabled, the time for fixing an output
pin RTO0~5 to inactive level is delayed for about 4, 8, 16 or 32 machine cycles (selected by
SIGCR:NWS1,NWS0). Since the noise cancellation circuit uses a peripheral clock, input is invalidated
even if the DTTI input is enabled in a mode such as STOP mode in which the oscillation stops.
■ DTTI interrupt
When low level of DTTI is detected, DTTI interrupt flag (SIGCR:DTIF) is set to “1” after noise
cancellation time is passed and an interrupt request is sent to interrupt controller.
DTTI
SIGCR: DTIF
Noise cancellation time controlled
by SIGCR:NWS1,NWS0
Software write “0” in SIGCR: DTIF
Figure 14.6.4.3-2 DTTI interrupt timing
Note: If SIGCR:NWS1,NWS0 is changed within noise cancellation time, the larger value of NWS1, NWS0 will
take effect.
Note: SIGCR:DTIF can only be software clear.
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429
14.7 Usage Notes on the Multi-functional Timer
Notes on using the multi-functional timer are given below.
■ Usage notes on the 16-bit free-running timer
● Notes about using a program for setting
•
•
•
After reset, the timer value is 0000H, zero detect interrupt flag will be set to “1” in next count
clock after timer enable (TCCSL:STOP=0).
Since the timer mode bit (TCCSL:MODE) has a buffer, changing timer mode will take effect in
next count cycle. Zero detect interrupt is always generated when timer mode is changed from
up-count to up-down count mode.
Software clear timer (TCCSL:SCLR=1) will initialize the timer but not generate zero detect
interrupt.
● Notes about interrupts
•
•
•
When the IRQZF bit of the timer control status register (TCCSH) is set to 1 and an interrupt
request is enabled (TCCSH:IRQZE=1), control cannot be returned from interrupt processing.
Always clear the IRQZF bit.
When the ICLR bit of the timer control status register (TCCSH) is set to 1 and an interrupt
request is enabled (TCCSH:ICRE=1), control cannot be returned from interrupt processing.
Always clear the ICLR bit.
Since the 16-bit free-running timer shares an interrupt vector with other resource, interrupt
causes must be checked carefully by the interrupt processing routine when interrupts are
used.
Also, when EI2OS is used by the 16-bit free-running timer, shared resource interrupts must be
disabled.
■ Usage notes on the 16-bit output compare
● Notes about interrupts
•
•
When the IOP bit of the compare control register (OCS0/2/4) is set to 1 and an interrupt
request is enabled (OCS0/2/4:IOE=1), control cannot be returned from interrupt processing.
Always clear the IOP bit.
Since the 16-bit output compare shares an interrupt vector with other resource, interrupt
causes must be checked carefully by the interrupt processing routine when interrupts are
used.
Also, when EI2OS is used by the 16-bit output compare, shared resource interrupts must be
disabled.
■ Usage notes on the 16-bit input capture
● Notes about interrupts
•
•
•
430
When the ICP bit of the input capture control status register (PICSL01/ICSL23) is set to 1 and
an interrupt request is enabled (PICSL01/ICSL23:ICE=1), control cannot be returned from
interrupt processing. Always clear the ICP bit.
If input capture pins IN is toggled after ICP bit is set but before interrupt routine is processed,
the edge indication bit (ICSH23:IEI3,2 or PICSH01:IEI1,0) will show the latest edge detected.
Since the 16-bit input capture shares an interrupt vector with other resource, interrupt causes
must be checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI2OS is used by the 16-bit input capture, shared resource interrupts must be
disabled.
MB90820 series
■ Usage notes on the waveform generator
● Notes on using a program for setting
•
Change the TMD2, TMD1 and TMD0 bits of the 16-bit timer control register (DTCR0/1/2)
when the waveform generator is under operation (TMD2~0=001B, 010B, 100B or 111B),
always be sure no trigger source and timer is not counting. Otherwise unexpected waveform
in RTO will be occurred due to prescheduled output by previous trigger. But RTO output
becomes normal once after timer is underflow or retriggered by new trigger source in new
mode setting.
Trigger source is H level of RT when TMD2~0=001B, rising edge of RT when TMD2~0=010B,
rising/falling edge of RT when TMD2~0=100B or rising/falling edge of PPG0 when
TMD2~0=111B.
For example, changing TMD2~0 from 100B to 111B, you can set in following procedures
1) set TMRR0/1/2 to a very small value like 0001H
2) set RT1/3/5 to output “L”/”H” and wait until timer 0/1/2 underflow
3) change mode bits TMD2, TMD1 and TMD0 and corresponding setting
4) corrected output waveform will appear in RTO pins one machine cycle later
•
Writing a value in 16-bit timer register (TMRR0/1/2) during timer counting, new value will be
valid at the next timer trigger. And always be sure to use a word transfer instruction (MOVW
A, dir, etc.) to access timer register.
Change the DCK2, DCK1 and DCK0 bits of the waveform control register (SIGCR) when the
timer is not counting.
Change the NWS1 and NWS0 bits of waveform control register (SIGCR) when the noise
cancellation function is disabled (SIGCR: NRSL=0).
•
•
● Notes about interrupts
•
•
•
MB90820 series
When the TMIF bit of the timer control register (DTCR) is set to 1 and an interrupt request is
enabled (DTCR:TMIE=1), control cannot be returned from interrupt processing. Always clear
the TMIF bit.
When the DTIF bit of the waveform control register (SIGCR) is set to 1, control cannot be
returned from interrupt processing. Always clear the DTIF bit.
Since the waveform generator shares an interrupt vector with other resource, interrupt
causes must be checked carefully by the interrupt processing routine when interrupts are
used.
Also, when EI2OS is used by the waveform generator, shared resource interrupts must be
disabled.
431
14.8 Sample Programs for the Multi-functional Timer
This section contains sample programs for the multi-functional timer.
■ Sample program for 16-bit free-running timer
● Processing
•
A 4 ms compare clear interrupt is generated with 16-bit free-running timer 0.
•
The timer is used in up-down mode to repeatedly generate a compare clear interrupt.
•
EI2OS is not used.
•
24 MHz is used for the machine clock, and 41.7 ns is used for the count clock.
● Coding example
ICR11
; Interrupt control register for the
16-bit free-running timer
TCCS
EQU
00005EH
; Timer control status register
CPCLRB EQU
000058H
; Compare clear buffer register
ICLR
EQU
TCCS:9
; Interrupt request flag bit
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
; Assumes that stack pointer (SP) has already been
initialized
AND
CCR,#0BFH
; Interrupt disable
MOV
I:ICR11,#00H
; Interrupt level 0 (strongest)
MOVW I:CPCLRB,#0FFFFH ; Set compare clear value to change
16-bit free-running timer from up-count to
down-count
MOVW I:TCCS,#0110H
; Sets up-down mode, 41.7 ns count clock
; Enables compare clear interrupt
; Disables interrupt mask
; Clears interrupt flag and enable timer
MOV
ILM,#07H
; Sets ILM in PS to level 7
OR
CCR,#40H
; Interrupt enable
LOOP:
MOV
A,#00H
; Endless loop
MOV
A,#01H
;
BRA
LOOP
;
;-------Interrupt program-------------------------------------------------------------------------------------------WARI:
CLRB I:ICLR
; Clears interrupt request flag
;
:
;
User processing
;
:
RETI
; Returns from interrupt
432
EQU
0000BBH
MB90820 series
CODE
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG
0FF74H
; Sets vector for interrupt #34 (22H)
DSL
WARI
ORG
0FFDCH
; Sets reset vector
DSL
START
DB
00H
; Sets single-chip mode
VECT
ENDS
END
START
■ Sample program for 16-bit output compare
● Processing
•
A output compare match interrupt is generated when the count value of 16-bit free-running
timer is matched with output compare 0.
•
The 16-bit free-running timer is used in up-count mode.
•
EI2OS is not used.
•
24 MHz is used for the machine clock, and 41.7 ns is used for the count clock of 16-bit freerunning timer.
● Coding example
ICR00
EQU
0000B0H
; Interrupt control register for the output compare 0
TCCS
EQU
00005EH
; Timer control status register
CPCLRB EQU
000058H
; Compare clear buffer register
OCCP0 EQU
000070H
; Output compare register 0
OCCP1 EQU
000072H
; Output compare register 1
OCS01 EQU
00007CH
; Compare control register
IOP
EQU
OCS01:6
; Interrupt request flag bit
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
; Assumes that stack pointer (SP) has already been
initialized
AND
CCR,#0BFH
; Interrupt disable
MOV
I:ICR00,#00H
; Interrupt level 0 (strongest)
MOVW I:TCCS,#0000H
; Enables 16-bit free-running timer
; Sets up-count mode
MOVW I:OCCP0,#0BFFFH ; Set output compare register 0
MOVW I:OCCP1,#07FFFH ; Set output compare register 1
MOVW I:OCS01,#0C1FH
; Enables output compare output
; Enables compare match interrupt 0
; Clears interrupt flag and enable output compare
MOV
ILM,#07H
; Sets ILM in PS to level 7
OR
CCR,#40H
; Interrupt enable
LOOP:
MOV
A,#00H
; Endless loop
MOV
A,#01H
;
BRA
LOOP
;
;-------Interrupt program-------------------------------------------------------------------------------------------MB90820 series
433
WARI:
;
;
;
CLRB I:IOP
:
User processing
:
RETI
; Clears interrupt request flag
; Returns from interrupt
CODE
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG
0FFCCH
; Sets vector for interrupt #12 (0CH)
DSL
WARI
ORG
0FFDCH
; Sets reset vector
DSL
START
DB
00H
; Sets single-chip mode
VECT
ENDS
END
START
434
MB90820 series
CHAPTER 15
DELAYED INTERRUPT GENERATOR
MODULE
This chapter describes the functions and operation of the delayed interrupt generator
module.
15.1 Overview of the Delayed Interrupt Generator Module
15.2 Delayed Interrupt Generator Module Register
15.3 Operation of the Delayed Interrupt Generator Module
15.4 Usage Notes on the Delayed Interrupt Generator Module
MB90820 series
435
15.1 Overview of the Delayed Interrupt Generator Module
The delayed interrupt generator module generates interrupts for task switching. By
using this module, software can issue and cancel interrupt requests for the F²MC-16LX
CPU.
■ Block diagram of the delayed interrupt generator module
F2MC-16LX bus
Figure15.1-1 shows the block diagram of the delayed interrupt generator module.
Delayed interrupt cause issuance/cancellation decoder
Interrupt cause latch
Figure 15.1-1 Block diagram of the delayed interrupt generator module
436
MB90820 series
15.2 Delayed Interrupt Generator Module Register
This section lists the delayed interrupt generator module register.
■ Delayed interrupt generator module register (DIRR)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
—
—
—
—
—
—
—
R0
XXXXXXX0B
—
—
—
—
—
—
—
R/W
00009FH
X
: Indeterminate
R0
Delayed interrupt request
0
Clears delayed interrupt request
1
Generates delayed interrupt request
R/W : Read and write
: Initial value
—
: Not used
Figure 15.2-1 Delayed interrupt generator module register (DIRR)
Table 15.2-1 Delayed interrupt generator module register (DIRR)
Bit name
MB90820 series
Function
bit15
bit14
bit13
bit12
bit11
bit10
bit9
Reserved bits
bit8
• This bit is used to controls the generation or clearing of a
delayed interrupt request.
•
Writing 1 to this register generates a delayed interrupt request.
R0:
•
Writing 0 to this register clears the delayed interrupt request.
Delayed interrupt
•
The register is cleared at reset.
request bit
• Both 0 and 1 may be written to the reserved bit area. However,
the set bit and clear bit instructions should be used to access
this register to prepare for future expansion.
• Both “0” and “1” may be written to the reserved bits, writing to
these bits has no effect on the operation.
437
15.3 Operation of the Delayed Interrupt Generator Module
When software causes the CPU to write 1 to the relevant bit of DIRR, the request latch
in the delayed interrupt generator module is set and an interrupt request is generated
to the interrupt controller.
■ Operation of the delayed interrupt generator module
When software causes the CPU to write 1 to the relevant bit of DIRR, the request latch in the
delayed interrupt generator module is set and an interrupt request is generated to the interrupt
controller. If the priority of other interrupt requests is lower than that of this interrupt or no other
interrupt request is generated, the interrupt controller generates an interrupt request to the
F²MC-16LX CPU. The F²MC-16LX CPU compares the ILM bit of the internal CCR register and
the interrupt request. When the request level is higher than that of the ILM bit, the CPU starts
the hardware interrupt processing microprogram immediately after execution of the current
instruction ends. As a result, the interrupt processing routine for this interrupt is executed. This
interrupt cause is cleared and task switching is done by writing 0 to the relevant bit of DIRR in
the interrupt processing routine. Figure 15.3-1Operation of the delayed interrupt generator
module shows the operation of the delayed interrupt generator module.
Delayed interrupt generation module
Delayed interrupt controller
WRITE
F2MC-16LX CPU
Other requests
ICR yy
IL
CMP
CMP
DIRR
ICR xx
ILM
NTA
Figure 15.3-1 Operation of the delayed interrupt generator module
438
MB90820 series
15.4 Usage Notes on the Delayed Interrupt Generator Module
Notes on using the delayed interrupt generator module are given below.
■ Usage notes on the delayed interrupt request latch
•
MB90820 series
This latch is set by writing 1 to the relevant bit of DIRR and cleared by writing 0 to the same
bit. Note that interrupt processing is restarted at the moment control returns from interrupt
processing unless software is created to clear the cause in the interrupt processing routine.
439
440
MB90820 series
CHAPTER 16
DTP/EXTERNAL INTERRUPT CIRCUIT
This chapter describes the functions and operation of the DTP/external interrupt
circuit.
16.1 Overview of the DTP/External Interrupt Circuit
16.2 Block Diagram of the DTP/External Interrupt Circuit
16.3 DTP/External Interrupt Circuit Pins
16.4 DTP/External Interrupt Circuit Registers
16.5 Operation of the DTP/External Interrupt Circuit
16.6 Usage Notes on the DTP/External Interrupt Circuit
16.7 Sample Programs for the DTP/External Interrupt Circuit
MB90820 series
441
16.1 Overview of the DTP/External Interrupt Circuit
The data transfer peripheral (DTP)/external interrupt circuit is located between external
peripherals and the F2MC-16LX CPU. It receives interrupt requests and data transfer
requests from peripherals and passes them to the CPU to generate external interrupt
requests or activate the extended intelligent I/O service (EI2OS).
■ DTP/external interrupt functions
The DTP/external interrupt circuit is activated by the signal supplied to a DTP/external interrupt
pin. The CPU accepts the signal using the same procedure it uses for normal hardware
interrupts and generates external interrupts or activates the extended intelligent I/O service
(EI2OS).
If the extended intelligent I/O service (EI2OS) is disabled when an interrupt request is accepted
by the CPU, the circuit executes its external interrupt function and branches to an interrupt
routine. If EI2OS is enabled, the circuit executes its DTP function, which performs automatic
data transfer using EI2OS and branches to an interrupt processing routine after the data transfer
has been performed a specified number of times.
Table 16.1-1 provides an overview of the DTP/external interrupt circuit.
Table 16.1-1 Overview of the DTP/external interrupt circuit
External interrupt function
Input pins
DTP function
Eight (P10/INT0/DTTI ~ P16/INT6, P51/INT7)
By using the request level setting register (ELVR), the level or edge to be
detected can be selected for each pin
Interrupt cause
Input of H level or L level or rising
edge or falling edge
Input of H level or L level
Interrupt number
#20 (14H), #22 (16H), #25 (19H), #26 (1A H), #27 (1BH), #28 (1CH)
Interrupt control
The output of interrupt requests is enabled and disabled using the DTP/
interrupt enable register (ENIR)
Interrupt flag
Interrupt causes are stored in the DTP/interrupt cause register (EIRR)
Processing selection
EI2OS is disabled (ICR: ISE = 0)
EI2OS is enabled (ICR: ISE = 1)
Processing
The circuit branches to an external
interrupt processing routine
The circuit performs automatic data
transfer using EI2OS for a specified
number of times and then branches
to an interrupt routine
ICR: Interrupt control register
442
MB90820 series
■ Interrupt of the DTP/external interrupt circuit and EI²OS
Table 16.1-2 Interrupt of the DTP/external interrupt circuit and EI²OS
Channel
Interrupt
number
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower
Middle
Upper
INT0/INT1
#20 (14H)
ICR04
0000B4H
FFFFACH
FFFFADH
FFFFAEH
INT2/INT3
#22 (16H)
ICR05
0000B5H
FFFFA4H
FFFFA5H
FFFFA6H
INT4
#25 (19H)
FFFF98H
FFFF99H
FFFF9AH
ICR07
0000B7H
FFFF94H
FFFF95H
FFFF96H
FFFF90H
FFFF91H
FFFF92H
FFFF8CH
FFFF8DH
FFFF8EH
INT5
#26 (1AH)
INT6
#27 (1BH)
ICR08
INT7
#28 (1CH)
Ο
0000B8H
Ο: Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal.
MB90820 series
443
16.2 Block Diagram of the DTP/External Interrupt Circuit
The DTP/external interrupt circuit consists of four blocks, the block diagram is shown
in Figure 16.2-1.
■ Block diagram of the DTP/external interrupt circuit
Request level setting register (ELVR)
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
2
Pin
2
2
2
2
2
2
Selector
2
Selector
P51/INT7
Pin
P10/INT0/DTTI
Selector
Pin
Selector
P16/INT6
Pin
P11/INT1
Pin
Pin
Selector
Selector
Internal data bus
P15/INT5
P12/INT2
Pin
Selector
Selector
Pin
P14/INT4
P13/INT3
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
Interrupt request number
#20(14H)
#22(16H)
#25(19H)
#26(1AH)
#27(1BH)
#28(1CH)
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
Figure 16.2-1 Block diagram of the DTP/external interrupt circuit
444
MB90820 series
● DTP/external interrupt input detection circuit
Upon detecting the level or edge selected for each pin by the interrupt request level setting
register (ELVR), this circuit sets to 1 the IR bit of the DTP/external interrupt cause register
(EIRR) that corresponds to the pin.
● Request level setting register (ELVR)
This register selects the effective level or edge for each pin.
● DTP/interrupt cause register (EIRR)
This register stores DTP/external interrupt causes. It contains an external interrupt request flag
bit for each pin. The bit is set to 1 if a valid signal is input to the corresponding pin.
● DTP/interrupt enable register (ENIR)
This register enables and disables external interrupts for each pin.
MB90820 series
445
16.3 DTP/External Interrupt Circuit Pins
This section describes the DTP/external interrupt circuit pins and provides a pin block
diagram.
■ DTP/external interrupt circuit pins
The DTP/external interrupt circuit pins are also used as general ports. Table 16.3-1 lists the pin
functions, I/O formats, and settings required to use the DTP/external interrupt circuit.
Table 16.3-1 DTP/external interrupt circuit pins
Pin name
Function
I/O format
Pull-up
resistor
Standby
control
Setting required
to use pins
Set the pin as
an input port
P10/INT0/
DTTI
(DDR1: bit8 = 0)
Set the pin as
an input port
P11/INT1
(DDR1: bit9 = 0)
Set the pin as
an input port
P12/INT2
P13/INT3
(DDR1: bit10 = 0)
Port 1 inputoutput/external
interrupt input/
resource inputoutput
Set the pin as
an input port
Selectable
CMOS output /
CMOS hysteresis
input
(DDR1: bit11 = 0)
Provided
Set the pin as
an input port
P14/INT4
(DDR1: bit12 = 0)
Set the pin as
an input port
P15/INT5
(DDR1: bit13 = 0)
Set the pin as
an input port
P16/INT6
(DDR1: bit14 = 0)
P51/INT7
446
Port 5 inputoutput/external
interrupt input
Not
provided
Set the pin as
an input port
(DDR5: bit9 = 0)
MB90820 series
■ Block diagram of the DTP/external interrupt circuit pins
RDR
Resource input
Port data register (PDR)
Pull-up resistor
About 50KΩ
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
External
interrupt
enable
DDR read
Standby control (SPL=1)
Figure 16.3-1 Block diagram of the DTP/external interrupt circuit pins (INT0 ~ INT6)
Resource input
Port data register (PDR)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
External
interrupt
enable
DDR read
Standby control (SPL=1)
Figure 16.3-2 Block diagram of the DTP/external interrupt circuit pins (INT7)
MB90820 series
447
16.4 DTP/External Interrupt Circuit Registers
This section describes DTP/external interrupt circuit registers.
DTP / Interrupt Cause Register
15
14
13
12
11
10
9
8
ER5
ER4
ER3
ER2
ER1
ER0
R/W
X
R/W
X
R/W
X
R/W
X
4
3
Address: 000031H
ER7
ER6
Read/write
Initial value
R/W
X
R/W
X
Bit number
R/W
X
R/W
X
2
1
0
EN1
EN0
EIRR
DTP / Interrupt Enable Register
Address: 000030 H
Read/write
Initial value
7
6
5
EN7
EN6
EN5
R/W
0
R/W
0
EN4
EN3
EN2
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit number
ENIR
R/W
0
Request Level Setting Register (Upper)
15
14
13
12
11
10
9
8
Address: 000033H
LB7
LA7
LB6
LA6
LB5
LA5
LB4
LA4
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
LA1
LB0
LA0
Bit number
ELVRH
Request Level Setting Register (Lower)
Address: 000032H
Read/write
Initial value
7
6
5
4
LB3
LA3
LB2
LA2
R/W
0
R/W
0
R/W
0
R/W
0
LB1
R/W
0
R/W
0
R/W
0
Bit number
ELVRL
R/W
0
Figure 16.4-1 DTP/external interrupt circuit registers
448
MB90820 series
16.4
DTP/External Interrupt Circuit Registers
16.4.1 DTP/interrupt cause register (EIRR)
The DTP/interrupt cause register (EIRR) stores and clears interrupt causes.
■ DTP/interrupt cause register (EIRR)
Address
bit15 bit14 bit13 bit12 bit11 bit10 bit9
000031 H
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0
R/W R/W
R/W R/W R/W R/W
ER0
0
: Read/write
1
bit0
(ENIR)
Initial value
XXXXXXXX B
R/W R/W
ER7
R/W
bit8 bit7
External interrupt request flag bit
Read
Write
No DTP/external interrupt is input
This bit is cleared
No effect
A DTP/external interrupt is input
Figure 16.4.1-1 DTP/interrupt cause register (EIRR)
Table 16.4.1-1 Function description of each bit of the DTP/interrupt cause register (EIRR)
Bit name
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
ER7 ~ ER0:
External interrupt
request flag bits
Function
• Each of these bits is set to 1 if a signal with the edge or
level selected by bits LB7, LA7 ~ LB0, LA0 of the request
level setting register (ELVR) is input to the DTP/external
interrupt pin (stores an interrupt cause).
• If these bits and corresponding bits EN7 ~ EN0 of the DTP/
interrupt enable register (ENIR) are 1, an interrupt request
is output to the CPU.
• Writing 0 to this bit clears the bit. Writing 1 to this bit does
not change the bit value and has no effect on other bits.
<Caution>
If more than one external interrupt request output is
enabled (ENIR: EN7 ~ EN0 = 1), clear only the bit that
caused the CPU to accept an interrupt (bits ER7 ~ ER0 set
to 1). Do not clear the other bits without a reason.
[Reference]
When the extended intelligent I/O service (EI²OS) is activated, the corresponding external interrupt request flag bit
is automatically cleared when the transfer of one data ends.
MB90820 series
449
16.4
DTP/External Interrupt Circuit Registers
16.4.2 DTP/interrupt enable register (ENIR)
The DTP/interrupt enable register (ENIR) enables and disables the output of interrupt
requests to the CPU.
■ DTP/interrupt enable register (ENIR)
bit15
Address
000030H
bit8 bit7
(EIRR)
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 0 0 0 0 0 0 0 0 B
R/W R/W R/W R/W R/W R/W R/W R/W
EN7
External interrupt request enable bits
R/W
: Read/write enabled
: Initial value
EN0
0
An external interrupt request is disabled.
1
An external interrupt request is enabled.
Figure 16.4.2-1 DTP/interrupt enable register (ENIR)
Table 16.4.2-1
Function description of each bit of the DTP/interrupt enable register (ENIR)
Bit name
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
450
EN7 ~ EN0:
External interrupt
request enable
bits
Function
Each of these bits enables and disables the output of interrupt requests to the CPU. If these bits and corresponding bits
ER7 ~ ER0 of the DTP/interrupt cause register (EIRR) are 1,
an interrupt request is output to the CPU.
[Reference]
• To use a DTP/external interrupt pin, write 0 to the corresponding bit of the port direction register to set the pin as
an input port.
• The states of the DTP/external interrupt pins can be read
directly using the port data register regardless of the states
of external interrupt request enable bits.
• Bits ER7 ~ ER0 of the DTP/interrupt cause register (EIRR)
are set to 1 if an interrupt cause is detected regardless of
the values of external interrupt request enable bits.
MB90820 series
Table 16.4.2-2 Correspondence between the DTP/interrupt control registers (EIRR, ENIR) and
each channel
DTP/external interrupt
pin
Interrupt number
External interrupt
request flag bit
External interrupt
request enable bit
P51/INT7
#28 (1CH)
ER7
EN7
P16/INT6
#27 (1BH)
ER6
EN6
P15/INT5
#26 (1AH)
ER5
EN5
P14/INT4
#25 (19H)
ER4
EN4
ER3
EN3
ER2
EN2
ER1
EN1
ER0
EN0
P13/INT3
#22 (16H)
P12/INT2
P11/INT1
#20 (14H)
P10/INT0/DTTI
MB90820 series
451
16.4
DTP/External Interrupt Circuit Registers
16.4.3 Request level setting register (ELVR)
The request level setting register (ELVR) selects the level or edge of the signal input to
each DTP/external interrupt pin that is to be detected as a DTP/external interrupt cause.
■ Request level setting register (ELVR)
Address Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Initial value
000033H LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00000000B
R/W:Read/write enabled
:Initial value
LB 7
LB 0
LA 7
LA 0
0
0
0
1
1
0
1
1
External interrupt request detection selection bits
L level is to be detected.
H level is to be detected.
Rising edge is to be detected.
Falling edge is to be detected.
Figure 16.4.3-1 Request level setting register (ELVR)
Table 16.4.3-1 Function description of each bit of the request level setting register (ELVR)
Bit name
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
452
LB7, LB0 ~ LA7,
LA0:
Request detection
selection bits
Function
• Each of these bits selects the level or edge of the signal
input to the DTP/external interrupt pin to be detected as a
DTP/external interrupt cause.
• Two bits are assigned to each pin.
[Reference]
If the selected detection signal is input to a DTP/external
interrupt pin, the external interrupt request flag bit is set to 1
regardless of the settings of the DTP/interrupt enable register (ENIR).
MB90820 series
Table 16.4.3-2 Correspondence between request level setting register (ELVR) and each
channel
DTP/external interrupt pin
Interrupt number
Bit name
P51/INT7
#28 (1C H)
LB7, LA7
P16/INT6
#27 (1B H)
LB6, LA6
P15/INT5
#26 (1A H)
LB5, LA5
P14/INT4
#25 (19H)
LB4, LA4
P13/INT3
LB3, LA3
#22 (16H)
P12/INT2
LB2, LA2
P11/INT1
LB1, LA1
#20 (14H)
P10/INT0/DTTI
MB90820 series
LB0, LA0
453
16.5 Operation of the DTP/External Interrupt Circuit
The DTP/external interrupt circuit provides the external interrupt function and the DTP
function. This section describes the settings required for each function and the
operation of the circuit.
■ Setting the DTP/external interrupt circuit
Figure 16.5-1 shows the settings required to operate the DTP/external interrupt circuit.
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ICR08/ICR07
or
ICS3 ICS2 ICS1 ICS0 ISE
ICR05/ICR04
IL2
IL1
IL0
ICS3 ICS2 ICS1 ICS0 ISE
IL2
IL1
IL0
For the external interrupt function
For the DTP function
EIRR
/ ENIR
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
ELVR
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
DDR1
P16 P15 P14 P13 P12 P11 P10
DDR6
P63
: Used
: Set the bit corresponding to the bit used to 1
: Set the bit corresponding to the bit used to 0
0 : Specifies 0
1 : Specifies 1
Figure 16.5-1 DTP/external interrupt circuit
Set the DTP/external interrupt circuit registers with the following procedure:
1. Set the target bit of the DTP/interrupt enable register (ENIR) to disable interrupts.
2. Set the target bit of the request level setting register (ELVR).
3. Clear the target bit of the DTP/interrupt cause register (EIRR).
4. Set the target bit of the DTP/interrupt enable register (ENIR) to enable interrupts.
The procedure for setting the DTP/external interrupt circuit registers must start with disabling the
output of external interrupt requests (ENIR:EN7 ~ EN0 = 0). Before the output of external
interrupt requests can be enabled (ENIR:EN7 ~ EN0 = 1), the corresponding interrupt request
flag bits must be cleared (ENIR:EN7 ~ EN0 = 0).
This is in order to avoid interrupt requests from being generated accidentally while the registers
are being set.
454
MB90820 series
● Switching between the external interrupt function and the DTP function
Switching between the external interrupt function and the DTP function is accomplished by the
ISE bit of the corresponding interrupt control register (ICR). If the ISE bit is 1, the extended
intelligent I/O service (EI2OS) is enabled and the circuit executes its DTP function. If it is 0,
EI2OS is disabled and the circuit executes the its external interrupt function.
<Check>
If multiple interrupt requests are assigned to a single ICR register, the interrupt level (IL2 ~
IL0) is common to all of the interrupt requests. As a rule, when one interrupt request uses
EI2OS, the other interrupt requests cannot use it.
■ Operation of the DTP/external interrupt circuit
Table 16.5-1 shows the control bits and interrupt causes of the DTP/external interrupt circuit.
Table 16.5-1 Control bit and interrupt cause of the DTP/external interrupt circuit
DTP/external interrupt circuit
Interrupt request flag bit
EIRR: ER7 ~ ER0
Interrupt request enable bit
ENIR: EN7 ~ EN0
Interrupt cause
Input of an effective edge or level to pin INT7 ~ INT0
When DTP/external input requests are set, the resource will generate an interrupt request signal
to the interrupt controller whenever an interrupt cause indicated in the request level setting
register (ELVR) is received at the corresponding pin. If the ISE bit is 0, the interrupt processing
microprogram is executed. If it is 1, the extended intelligent I/O service handling (DTP handling)
microprogram is executed.
MB90820 series
455
Figure 16.5-2 shows the operation of the DTP/external interrupt circuit.
DTP/external interrupt circuit
Another request
Interrupt controller
CPU
ELVR
ICRYY
ELVR
IL
CMP
ICRXX
ELVR
CMP
ILM
Interrupt processing
microprogram
Cause
DTP handling routine
(EI2OS is started)
Generation of DTP/
external interrupt request
Transfer data between memory
and peripheral
Accepted by
interrupt controller?
Update descriptor
Descriptor
data counter
0
Interrupt processing routine
Accepted by CPU?
≠0
Return from DTP handling routine
Start interrupt processing
microprogram
ICR: ISE
Set again or stop
Return to CPU processing
1
0
Start external interrupt flag.
Processing. Clear interrupt flag.
Return from external interrupt
Figure 16.5-2 Operation of the DTP/external interrupt circuit
456
MB90820 series
Memo
MB90820 series
457
16.5
Operation of the DTP/External Interrupt Circuit
16.5.1
External interrupt function
The DTP/external interrupt circuit has an external interrupt function that generates an
interrupt request when a selected signal level is input to a DTP/external interrupt pin.
■ External interrupt function
If the edge or level selected for a DTP/external interrupt pin by the request level setting register
(ELVR) is detected at that pin, the corresponding ER7 ~ ER0 bit of the DTP/interrupt cause
register (EIRR) is set to 1. If, in this state, the corresponding interrupt request enable bit of the
DTP/interrupt enable register is set to 1 to enable interrupts (ENIR:EN7 ~ EN0 = 1), the interrupt
cause is reported to the interrupt controller. The interrupt controller checks the magnitude of the
interrupt level (ICR:IL2 ~ IL0) in relation to those of the interrupt requests from other peripheral
functions, the interrupt priority, etc. The CPU checks the magnitudes of the interrupt level mask
register (PS:ILM2 ~ ILM0) and the interrupt level, the interrupt enable bit (PS:CCR: 1), etc.
When the interrupt request is accepted by the CPU, the CPU executes an internal interrupt
processing routine (microprogram) and branches to the interrupt processing routine. In the
interrupt processing routine, 0 must be written to the corresponding interrupt request flag bit to
clear the interrupt request.
<Check>
458
•
An ER bit is set to 1 if a DTP/external interrupt cause is generated, regardless of the state
of the corresponding EN bit.
•
When the interrupt routine is activated, the ER bit that caused the routine to be activated
must be cleared. If the ER bit is kept at 1, control cannot return from the interrupt. Only
clear the flag bit that caused the interrupt; do not clear the other bits without reason.
MB90820 series
16.5
Operation of the DTP/External Interrupt Circuit
16.5.2 DTP function
The DTP/external interrupt circuit has a DTP function that detects a signal supplied to a
DTP/external interrupt pin from an external peripheral and activates the extended
intelligent I/O service.
■ Operation of the DTP function
The DTP function detects a data transfer request signal from an external peripheral to
automatically transfer data between memory and the peripheral.
The extended intelligent I/O service (EI2OS) is activated by the external interrupt function using
level detection. The operation of the DTP function is the same as that of the external interrupt
function up to the point that the CPU accepts an interrupt request. If the operation of EI2OS is
enabled (ICR:ISE = 1), EI2OS is activated to start data transfer when an interrupt request is
accepted. When the transfer of one data unit ends, the descriptor is updated and the interrupt
request flag bit is cleared to wait for the next request from the pin. When the entire transfer
using EI2OS is completed, control is transferred to the interrupt processing routine.
The external peripheral must remove only the level of the data transfer request signal (DTP
external interrupt cause) within three cycles of the first transfer.
Rising edge request, or H level request (ELVR: LB0, LA0 = 01B)
Input to the INTO pin
(DTP/external interrupt cause)
*Intelligent I/O service data transfer
Internal operation of
the CPU (microprogram)
Descriptor selection
and reading
from i/o register to memory.
Descriptor updating
Write address
Read address
Address bus pin
Data bus pin
Read data
Write data
Read signal
Write signal
*1
Internal bus
Register
External peripheral
Data, address bus
IRQ
Data
transfer
request
Read operation *1
DTP/external
interrupt cause*2
INT DTP/external
interrupt circuit
Interrupt
request
Write
opration*3
CPU
(EI2OS)
Internal
Memory
MB90820 series
*1, *2 : Must be removed within three machine cycles of transfer.
*3
: If the extended intelligent I/O service is in peripheral -> memory transfer mode.
Figure 16.5.2-1 Example of interfacing to the external peripheral
MB90820 series
459
16.6 Usage Notes on the DTP/External Interrupt Circuit
Notes on the signal to be input to the DTP/external interrupt circuit, release from
standby mode, and interrupts are given below.
■ Usage notes on the DTP/external interrupt circuit
● Conditions for external peripherals using the DTP function
To support the DTP function, external peripherals must be able to clear data transfer requests
automatically in response to transfer operations. If a transfer request is not removed within three
machine cycles of the start of transfer, the DTP/external interrupt circuit interprets the request as
another transfer request.
● Input polarities of external interrupts
•
If the request level setting register (ELVR) is set so that an edge is detected, the pulse width
must be at least three machine cycles for the edge to be detected.
•
If the register is set for level detection, and the level to be detected as an interrupt cause is
input, cause F/F in the DTP/interrupt cause register (EIRR) is set to 1 to store the cause, as
shown in Figure 16.6-1. Even if the cause is removed, the request to the interrupt controller
remains active provided the output of interrupt requests is enabled. Thus, to cancel the
request to the interrupt controller, clear the external interrupt request flag bit and cause F/F,
as shown in Figure 16.6-2.
DTP/external
interrupt cause
DTP/interrupt input
detection circuit
Cause flip-flop
(in the EIRR register)
To interrupt
controller
(interrupt
request)
Enable gate
The cause is stored until the register is cleared
Figure 16.6-1 Clearing the cause retention circuit when a level is specified
DTP/external interrupt
cause (when the H level
is detected)
H level
Removal of the interrupt cause
Interrupt request to the
interrupt controller
Request becomes inactive when
cause flip-flop is cleared
Figure 16.6-2 DTP/external interrupt cause and interrupt request when the output
of interrupt requests is enabled
460
MB90820 series
● Notes about interrupts
When the external interrupt function is used, control cannot return from the interrupt processing
routine if the external interrupt request flag bit is 1 and the output of interrupt requests is
enabled. In the interrupt processing routine, the external interrupt request flag bit must be
cleared. (When the DTP function is used,EI2OS automatically clears the bit.) For level
detection, the external interrupt request flag bit is set again as soon as it is cleared if the level
assumed as an interrupt cause continues to be input. Either disable the output of interrupt
requests or remove the interrupt cause, if required.
MB90820 series
461
16.7 Sample Programs for the DTP/External Interrupt Circuit
This section contains sample programs for the external interrupt function and the DTP
function.
■ Sample program for the external interrupt function
● Processing
•
The rising edge of the pulse input to the INT0 pin is detected, and an external interrupt is
generated.
● Coding example
ICR04
462
EQU
0000B4H
; Interrupt control register for the DTP/external
interrupt circuit
DDR6
EQU
000016H
;
DDR1
EQU
000011H
; Port 1 direction register
ENIR
EQU
000030H
; DTP/interrupt enable register
EIRR
EQU
000031H
; DTP/interrupt cause register
ELVRL EQU
000032H
; Request level setting register
ELVRH EQU
000033H
; Request level setting register
ER0
EQU
EIRR:0
; INT0 interrupt flag bit
EN0
EQU
ENIR:0
; INT0 interrupt enable bit
;-------Main program-----------------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
; Assumes that stack pointer (SP) has already been
initialized
MOV
I:DDR1,#00000000B ; Sets DDR1 as an input port
AND
CCR,#0BFH
; Disables interrupts
MOV
I:ICR04,#00H
; Interrupt level: 0 (highest). Disables EI2OS
CLRB I:EN0
; Disables INT0, using ENIR
MOV
I:ELVRL,#00000010B; Selects the rising edge for INT0
CLRB I:ER0
; Clears the cause for INT0 using EIRR
SETB I:EN0
; Enables INT0 using ENIR
MOV
ILM,#07H
; Sets ILM in PS to level 7
OR
CCR,#40H
; Enables interrupts
LOOP:
MOV
A,#00H
; Endless loop
MOV
A,#01H
BRA
LOOP
;-------Interrupt program------------------------------------------------------------------------------------------------WARI
CLRB I:ER0
; Clears the interrupt request flag
;
:
;
User processing
;
:
RETI
; Returns from interrupt
CODE
ENDS
MB90820 series
;-------Vector setting-----------------------------------------------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG
0FFACH
; Sets vector for interrupt #20 (14H)
DSL
WARI
ORG
0FFDCH
; Sets reset vector
DSL
START
DB
00H
; Sets single-chip mode
VECT
ENDS
END
START
■ Sample program for the DTP function
● Processing
•
The H level of the signal input to the INT0 pin is detected, and channel 0 of the extended
intelligent I/O service (EI2OS) is activated.
•
Data is output from RAM to port 0 by DTP processing (EI2OS).
● Coding example
ICR04
; Interrupt control register for the DTP/external
interrupt circuit
DDR0
EQU
000010H
; Port 0 direction register
DDR1
EQU
000011H
; Port 1 direction register
ENIR
EQU
000030H
; DTP/interrupt enable register
EIRR
EQU
000031H
; DTP/interrupt cause register
ELVRL EQU
000032H
; Request level setting register
ELVRH EQU
000033H
; Request level setting register
ER0
EQU
EIRR:0
; INT0 interrupt flag bit
EN0
EQU
ENIR:0
; INT0 interrupt enable bit
BAPL
EQU
000100H
; Buffer address pointer, lower
BAPM
EQU
000101H
; Buffer address pointer, middle
BAPH
EQU
000102H
; Buffer address pointer, upper
ISCS
EQU
000103H
; EI2OS status register
IOAL
EQU
000104H
; I/O address register, lower
IOAH
EQU
000105H
; I/O address register, upper
DCTL
EQU
000106H
; Data counter, lower
DCTH
EQU
000107H
; Data counter, upper
;-------Main program-----------------------------------------------------------------------------------------------------CODE
CSEG
START:
;
:
; Assumes that stack pointer (SP) has already been
initialized
MOV
I:DDR0,#11111111B ; Sets DDR0 as an output port
MOV
I:DDR1,#00000000B ; Sets DDR1 as an input port
AND
CCR,#0BFH
; Disables interrupts
MOV
I:ICR04,#08H
; Interrupt level: 0 (highest)
; Enables EI2OS. Channel 0
MOV
BAPL,#00H
; Sets the address of the output data
MB90820 series
EQU
0000B4H
463
MOV
MOV
MOV
;
;
; Byte transfer. I/O address fixed. Buffer address
+ 1. Transfer from memory to I/O
MOV
IOAL,#00H
; Specifies port 0 (PDR0) as the transfer destination
MOV
IOAH,#00H
; address pointer
MOV
DCTL,#0AH
; Number of transfers: 10
MOV
DCTH,#00H
;
CLRB I:EN0
; Disables INT0 using ENIR
MOV
I:ELVRL,#00000001B; Selects H level for INT0
CLRB I:ER0
; Clears the cause of INT0 using EIRR
SETB I:EN0
; Enables INT0 using ENIR
MOV
ILM,#07H
; Sets ILM in PS to level 7
OR
CCR,#40H
; Enables interrupts
LOOP:
MOV
A,#00H
; Endless loop
MOV
A,#01H
;
BRA
LOOP
;
;-------Interrupt program------------------------------------------------------------------------------------------------WARI:
CLRB I:ER0
; Clears the interrupt request flag
;
:
;
; Switches the channel and changes the transfer
address, if required
;
User processing
; Specifies processing again, such as the termination
of EI2OS. To terminate the processing, interrupts
must be disabled
;
:
RETI
; Returns from the interrupt
CODE
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------------VECT
CSEG ABS=0FFH
ORG
0FFACH
; Sets vector for interrupt #20 (14H)
DSL
WARI
ORG
0FFDCH
; Sets reset vector
DSL
START
DB
00H
; Sets single-chip mode
VECT
ENDS
END
STAR
464
BAPM,#06H
BAPH,#00H
ISCS,#12H
MB90820 series
CHAPTER 17
A/D CONVERTER
This chapter explains the function and operation of the A/D converter.
17.1 Features of A/D Converter
17.2 Block Diagram of A/D Converter
17.3 Registers for A/D Converter
17.4 Operation of A/D Converter
17.5 Conversion Using EI2OS
17.6 Converted-data Protection Function
465
17.1 Features of A/D Converter
The A/D converter converts analog input voltages to digital values.
■ Features of A/D converter
● Conversion time: 3 µs min. per channel (with 24-MHz machine clock)
● RC sequential compare conversion with sample and hold circuit
● Resolution: 10 bits or 8 bits
● Analog input pin selected from up to 16 channels by program
•
Single-channel conversion:1 channel is selected and converted.
•
Scan conversion:Sequential channels (up to 16 channels) are converted.
● Mode setting
•
Single mode:
Converts the specified channel once. Up to 16 channels can be specified.
•
Continuous mode: Converts the specified channel repeatedly. Up to 16 channels can be
specified.
•
Stop mode: Converts one channel ,then the system stops and stands by for the next
activation. (starting of conversion can be synchronized)
● Interrupt requests
At the A/D conversion end, the interrupt request for an A/D conversion end can be generated to
the CPU. This interrupt can start EI2OS, which can transfer A/D conversion result data to the
memory. Therefore, interrupt requests are suitable for continuous processing.
● Selectable activation cause
The activation can be done by activation cause software, reload timer 1, or free running timer
zero detect.
466
MB90820 series
■ Analog input pins
Table 17.1-1 shows analog input pins of the A/D converter.
Table 17.1-1 Analog input pins
Port
Analog input
channel name
corresponding
ADE register
AN0
ADE0
AN1
ADE1
AN2
ADE2
AN3
Port6
ADE3
ADER0
AN4
ADE4
AN5
ADE5
AN6
ADE6
AN7
ADE7
AN8
ADE8
AN9
ADE9
AN10
ADE10
AN11
Port7
MB90820 series
corresponding
ADE bit
ADE11
ADER1
AN12
ADE12
AN13
ADE13
AN14
ADE14
AN15
ADE15
467
■ Input impedance
The sampling circuit of the A/D converter is represented as the following equivalent circuit:
When the sampling time is set to 0.5 µs (16-MHz machine clock; ST2 = 0, ST1 = 1, ST0 = 0), the
driving impedance for the analog input pin must be 1.5 kΩ or less.
When the driving impedance exceeds 1.5 kΩ, set a longer sampling time or add an external
capacitor compensate the driving impedance.
When the above conditions are not met, the A/D conversion precision is not assured.
For details, see the sampling time setting bit of ADSR1 in Section 17.3.4.
468
MB90820 series
17.2 Block Diagram of A/D Converter
Figure 17.2-1 shows the block diagram of A/D converter.
■ Block diagram of A/D converter
Figure 17.2-1 Block diagram of A/D converter
AVCC
AVR
AVSS
D/A converter
MPX
AN0
Input circuit
AN1
Port 6
AN2
AN3
AN4
AN5
Sequential compare register
Comparator
AN6
AN7
Sample and hold circuit
AN11
AN12
AN13
AN14
Decoder
Port 7
AN9
AN10
Input circuit
AN8
Data register
ADCR0/1
AN15
A/D setting register 0
A/D setting register 1
Operation clock
Prescaler
A/D input enable register 0
A/D input enable register 1
ADER0/1
A/D control register 0
A/D control register 1
ADCS0/1
16-bit reload timer 1
16-bit free-running timer zero detection
: Machine clock
MB90820 series
469
17.3 Registers for A/D Converter
The A/D converter has the following three registers:
• Control status register : ADCS0/1
• Data register : ADCR0/1
• Setting register : ADSR0/1
■ Registers for A/D converter
Figure 17.3-1 Registers for A/D Converter
A/D control status register ( Upper)
Address: 0000C7H
Read/write
Initial value
15
14
13
12
11
10
9
8
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
-
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(0)
(-)
(X)
Bit No.
ADCS1
A/D control status register (Lower)
6
5
0
Bit No.
MD1
MD0
S10
-
-
-
-
reserved
ADCS0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(0)
15
14
13
12
11
10
9
8
Bit No.
-
-
-
-
-
D9
D8
ADCR1
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(X)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
Bit No.
D7
D6
D5
D4
D3
D2
D1
D0
ADCR0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
7
Address: 0000C6H
Read/write
Initial value
4
3
2
1
Data register ( Upper)
Address: 0000C9 H
Read/write
Initial value
-
Data register ( Lower)
Address: 0000C8 H
Read/write
Initial value
A/D setting register ( Upper)
Address: 0000CBH
Read/write
Initial value
15
14
13
12
11
10
9
8
Bit No.
ST2
ST1
ST0
CT2
CT1
CT0
Reserved
ANS3
ADSR1
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
6
5
4
2
1
0
Bit No.
ANS2
ANS1
ANS0
Reserved
ANE3
ANE2
ANE1
ANE0
ADSR0
(R/W)
(0)
(R/W)
(0)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(R/W)
(0)
(0)
(0)
A/D setting register ( Lower)
Address: 0000CAH
Read/write
Initial value
470
3
MB90820 series
Memo
MB90820 series
471
17.3.1 Control status register (ADCS0)
The control status register (ADCS0) controls the A/D converter and indicates its
status. Do not rewrite ADCS0 during A/D conversion.
■ Control Status Register (ADCS0)
Figure 17.3.1-1 A/D control status register (ADCS0)
A/D control status register (Lower)
Address: 0000C6H
Read/write
Initial value
7
6
5
4
3
2
1
0
Bit No.
MD1
MD0
S10
-
-
-
-
reserved
ADCS0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(0)
[bit 7 and bit 6] MD1 and MD0 (A/D converter mode set)
Table 17.3.1-1 Operation Mode Settings
MD1
MD0
Operation mode
0
0
Single mode 1 ( Reactivation during A/D conversion is allowed.)
0
1
Single mode 2 ( Reactivation during A/D conversion is not allowed.)
1
0
Continuous mode ( Reactivation during A/D conversion is not allowed.)
1
1
Stop mode ( Reactivation during A/D conversion is not allowed.)
● Single mode
A/D conversion is continuously performed from the channel specified with ANS3 to ANS0
to the channel specified with ANE3 to ANE0. The conversion stops once it has been done
for all these channels.
● Continuous mode
A/D conversion is repeatedly performed from the channel specified with ANS3 to ANS0 to
the channel specified with ANE3 to ANE0 in a row.
● Stop mode
A/D conversion is performed from the channel specified with ANS3 to ANS0 to the
channel specified with ANE3 to ANE0, pausing for each channel. The A/D conversion is
resumed upon an activation.
Note:
• The A/D conversion in the continuous or stop mode continues until it is stopped by the BUSY bit.
• Write 0 to the BUSY bit to stop the A/D conversion.
• Reactivation disabled in single mode2, continuous mode, and stop mode applies to all kinds of activation by
software, an external trigger, and a timer.
472
MB90820 series
[bit 5] SIO
This bit specifies the resolution of conversion. When "0" is written to this bit, 10-bit A/D conversion is
performed. When "1" is written to this bit, 8-bit A/D conversion is performed and the conversion result is
stored in D7 to D0.
[bits 4 to bit 1] Unused bits
Writing to these bits has no effect. Reading these bits always returns "1".
[bit 0] reserved (reserved bit)
This bit is a reserved bit. Always write "0" to this bit.
Reading this bit always returns "0".
MB90820 series
473
17.3.2 Control status register (ADCS1)
The control status register (ADCS1) controls the A/D converter and indicates its
status.
■ Control Status Register (ADCS1)
Figure 17.3.2-1 A/D control status register (ADCS1)
A/D control status register (Upper)
Address: 0000C7H
Read/write
Initial value
15
14
13
12
11
10
9
8
Bit No.
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
-
ADCS1
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(W)
(0)
(-)
(X)
[bit 15] BUSY (busy flag and stop)
● At read:
•
This bit indicates an operation of the A/D converter.
•
The bit is set by starting of A/D conversion, and cleared by end of A/D conversion.
● At write:
•
When "0" is written to this bit during the A/D conversion, the conversion stops forcibly.
•
This bit is used in the continuous or stop mode.
•
"1" cannot be written to the bit used to indicate the A/D converter operation.
Note:
474
•
"1" is read from this bit when an RMW instruction is used.
•
In the single mode, this bit is cleared when A/D conversion ends.
•
In the continuous or stop mode, this bit is not cleared until writing "0" to this bit to stop the A/
D conversion.
•
This bit is initialized to 0 at reset.
•
Do not perform the forced stop and the starting concurrently (using software (BUSY = 0,
STRT = 1), external trigger, or timer).
MB90820 series
[bit 14] INT (interrupt)
This bit is set when converted data is written to ADCR. When this bit is set with bit5 (INTE) set to
"1", an interrupt request is generated. In addition, the EI2OS is activated if it is enabled. Writing
"1" to this bit does not affect it. This bit is cleared by writing "0" to it or by using the EI2OS
interrupt clear signal.
Note:
● To clear this bit by writing "0", ensure that A/D conversion is not in progress.
● This bit is initialized to "0" at reset.
● Using an RMW instruction, "1" is read from this bit.
[bit 13] INTE (Interrupt enable)
This bit sets enabling/disabling of interrupts due to the end of conversion.
● 0: Interrupt disabled
● 1: Interrupt enabled
When using EI2OS, set this bit (EI2OS is started by an interrupt request).
This bit is initialized to 0 at reset.
[bit 12] PAUS (A/D converter pause)
This bit is set when A/D conversion pauses.
Only one register is available for storing the A/D conversion result. Therefore, in the case that
EI2OS is used, unless the conversion results are transferred by the EI2OS, the result data would
be continuously updated and destroyed in continuous conversion.
To prevent the above condition, the system is so designed as not to store the next converteddata when a conversion result is not transferred yet (INT = "1"), with INTE = "1". A/D conversion
pauses during that period. When transferred by EI2OS ends or when "0" is set to INT bit , A/D
conversion is resumed. At this point, this bit is not cleared; to clear it, write "0" to it.
This bit is valid only when EI2OS is used.
Note:
● Regarding the converted-data protection function, see Section 17.6.
● This bit is initialized to "0" at reset.
[bit 11 and bit 10] STS1 and STS0 (Start source select)
These bits are initialized to "00B" at reset.
Select an A/D conversion activation cause by setting these bits.
Table 17.3.2-1
Function Settings
STS1
STS0
0
0
Activation A/D conversion by software
0
1
Activation A/D conversion by free-running timer zero detection and by software
1
0
Activation A/D conversion by timer and by software
1
1
Activation A/D conversion by free-running timer zero detection, timer, and by software
MB90820 series
Function
475
In a mode allowing two or more activation factors, A/D conversion is activated by the source that
occurs first. When rewriting the setting of these bits during A/D conversion, note that the result is
immediately reflected when it is rewritten.
Note:
● When the timer is selected, the 16-bit reload timer 1 is selected.
[bit 9] STRT (Start)
A/D conversion is started by writing "1" to this bit.
To reactivate A/D conversion, write "1" to this bit again.
At reset, this bit is initialized to "0".
Reading this bit always returns "1". Using an RMW instruction, "0" is read from this bit.
Reactivation during the operation is only available in the single mode 1, but not supported in the
single mode2, continuous mode and the stop mode. Check the BUSY bit before writing "1" to
this bit, in the latter three mode.
Do not forcibly stop A/D conversion concurrently with start of A/D conversion by software
(BUSY=0, STRT=1).
[bit 8] Unused bit
Writing to this bit has no effect.
Reading this bit always returns "1".
476
MB90820 series
17.3.3 Data Register (ADCR0, ADCR1)
The data register (ADCR0, ADCR1) is used to store digital values generated as a result
of conversion. ADCR0 stores lower 8 bits; ADCR1 stores most significant 2 bits of the
conversion result. These register's values are rewritten every time conversion ends.
Normally, the last converted value is stored in these register's bits.
■ Data register (ADCR0, ADCR1)
Figure 17.3.3-1 Data register (IBCR)
Data register (Upper)
Address: 0000C9 H
Read/write
Initial value
13
12
11
10
9
8
Bit No.
-
-
-
-
-
D9
D8
ADCR1
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(X)
(R)
(0)
(R)
(0)
7
6
5
4
3
2
1
0
Bit No.
D7
D6
D5
D4
D3
D2
D1
D0
ADCR0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
15
14
-
Data register (Lower)
Address: 0000C8 H
Read/write
Initial value
(R)
(0)
(R)
(0)
(R)
(0)
Reading bit 10 to bit 15 of ADCR1 always returns "1".
When S10 bit of ADCS0 is "1", the 8-bit mode is established, storing converted data in bit7 to
bit0. In this case, Reading bit9 to bit8 always returns "1".
For the use of the converted-data protection function, see Section 17.4. Do not write to this
register.
MB90820 series
477
17.3.4 Setting Register (ADSR0, ADSR1)
The setting register (ADSR) is used to set the A/D conversion time and the sampling
channels and to indicate the current sampling channel.
■ Setting Register (ADSR)
Figure 17.3.4-1 Setting register (ADSR)
15
14
13
12
11
10
9
Bit No.
8
ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8
Address: 0000C5 H
Read/write
Initial value
Address: 0000D0 H
Read/write
Initial value
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
7
6
5
4
3
2
1
0
Bit No.
ADE7 ADE6 ADE5
ADE4 ADE3 ADE2 ADE1 ADE0
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
ADER0
ADER1
(R/W)
(1)
[bit 15 to bit 13] ST2, ST1, ST0 (Sampling time)
Table 17.3.4-1
Function Settings
ST2
ST1
ST0
Function
0
0
0
4-machine cycle (8 MHz, 0.5 µs)
0
0
1
6-machine cycle (8 MHz, 0.8 µs)
0
1
0
8-machine cycle (16 MHz, 0.5 µs)
0
1
1
12-machine cycle (24 MHz, 0.5 µs)
1
0
0
24-machine cycle (8 MHz, 3 µs)
1
0
1
36-machine cycle (16 MHz, 2.25 µs)
1
1
0
48-machine cycle (16 MHz, 3.0 µs)
1
1
1
128-machine cycle (24 MHz, 5.3 µs)
These bits are used to determine a duration of the voltage sampling period at the input time. The
sampling time (the sampling period) needs to be set according to the driving impedance for the
analog input pin. When the following condition is not met, the A/D conversion precision is not
assured:
● When the driving impedance Rext is 1.5 kΩ or less, set the sampling time so as to be 0.5
478
MB90820 series
µs or more.
● When the driving impedance Rext is more than 1.5 kΩ , set the sampling time Tsamp to the
value obtained using the following expression or more:
Tsamp = (3.4 kΩ + Rext) × 12.4 pF × 8
[bit 12 and bit 10] CT2, CT1, CT0 (Compare time)
Table 17.3.4-2
Function Settings
CT2
CT1
CT0
Function
0
0
0
22-machine cycle (8 MHz, 2.8 µs)
0
0
1
33-machine cycle (16 MHz, 2.1 µs)
0
1
0
44-machine cycle (20 MHz, 2.2 µs)
0
1
1
66-machine cycle (24 MHz, 2.8 µs)
1
0
0
88-machine cycle (8 MHz, 11.0 µs)
1
0
1
132-machine cycle (16 MHz, 8.3 µs)
1
1
0
176-machine cycle (20 MHz, 8.8 µs)
1
1
1
264-machine cycle (24 MHz, 11.0 µs)
These bits are used to determine a duration of the comparison operation time.
● When 4.5 V
AVCC < 5.5 V
Set the comparison operation time so as to be 1.76 µs or more. When it is less than 1.76 µs, the
A/D conversion precision is not assured.
● When 4.0 V
VCC < 4.5 V
Set the comparison operation time so as to be 4 µs or more. When it is less than 4 µs, the A/D
conversion precision is not assured.
[bit 9] Reserved
This bit is reserved and is always written to “0”.
[bit 8 to bit 5] ANS3, ANS2, ANS1, ANS0 (Analog start channel set)
These bits are used to set the starting channel for A/D conversion , and to indicate the current
analog input channel.
When the A/D converter is activated, A/D conversion is started from the channel selected by
these bits.
MB90820 series
479
17.3
Registers for A/D Converter
17.3.5 Analog Input Enable Register
This register controls the analog input of port 6 and 7.
■
Analog input enable registers
Figure 17.3.5-1 Analog Input Enable register (ADER)
15
Address: 0000C5 H
Read/write
Initial value
Address: 0000D0 H
Read/write
Initial value
14
13
12
11
10
9
Bit No.
8
ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
7
6
5
4
3
2
1
0
Bit No.
ADE7 ADE6 ADE5
ADE4 ADE3 ADE2 ADE1 ADE0
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
ADER0
ADER1
(R/W)
(1)
This register controls the analog input of port 6 (AN0-7) and port 7 (AN8-15) as described below:
0: Port input / output mode
1: Analog input mode
If an external pin is used as an analog input for the A/D converter, the corresponding bit sould be
set to “1”.
Upon reset, both port 6 and 7 are set as analog input mode.
480
MB90820 series
Table 17.3.4-3 Starting Channel Settings
ANS3
ANS2
ANS1
ANS0
Starting channel
0
0
0
0
AN0
0
0
0
1
AN1
•
•
•
1
1
1
1
AN15
• At read: During A/D conversion, the channel being converted currently is read from these bits. If the system stops in the
stop mode or after the A/D conversion ends, the last converted channel is read.
● At reset: These bits are initialized to "0000B".
[bit 4] Reserved
This bit is reserved and is always written to “0”.
[bit 3 to bit 0] ANE3, ANE2, ANE1, ANE0 (Analog end channel set)
These bits are used to set the ending channel for A/D conversion.
Table 17.3.4-4
Ending Channel Settings
ANE3
ANE2
ANE1
ANE0
Ending channel
0
0
0
0
AN0
0
0
0
1
AN1
0
0
1
0
AN2
1
AN15
•
•
•
1
1
1
● At reset, these bits are initialized to "0000B".
Note:
● When writing to this register, always use word access. When byte write or bit
manipulation is performed for this register, A/D conversion may be started from an
unintended channel.
● When the same channel is written to the ANE3 to ANE0 bits and to the ANS3 to ANS0 bits,
conversion is performed for only 1 channel (single channel conversion).
● When conversion of the Analog end channel set by ANE3 to ANE0 is ended, with the
continuous mode or the stop mode set, control returns to the Analog start channel set by
the ANS3 to ANS0 bits.
● If ANS is larger than ANE, conversion does not return to AN0 after AN15. Therefore, do
not set ANS larger than ANE.
MB90820 series
481
17.4 Operation of A/D Converter
The A/D converter operates using the sequential-comparison converter system; and 10
bits or 8 bits can be selected for the A/D converter's resolution.
Since this A/D converter has only one register (10 bits; conversion result data register
ADCR0 and ADCR1) for storing conversion results, this register is rewritten every time
conversion is ended. So, this A/D converter alone is not suitable for continuous
conversion; and therefore conversion be performed with transferring converted data to
the memory using the extended intelligent I/O function (EI2OS) is recommended.
■ Single mode 1 / 2
In the single mode, analog inputs from the starting channel set by the ANS bits to the ending
channel set by the ANE bits are sequentially converted; and when conversion for up to the
ending channel is ended, A/D conversion is stopped. When the starting channel and the ending
channel are the same (ANS = ANE), conversion is performed for only the channel set by the
ANS bits.
Example:
ANS = 0000B, ANE = 0011 B :
Start --> AN0 --> AN1 --> AN2 --> AN3 --> End
ANS = 0010 B, ANE = 0010 B:
Start --> AN2 --> End
■ Continuous mode
In the continuous mode, analog inputs from the starting channel set by the ANS bits to the
ending channel set by the ANE bits are sequentially converted; and when conversion for up to
the ending channel is ended, control returns to the starting channel to continue A/D conversion.
When the starting channel and the ending channel are the same (ANS = ANE), conversion is
continued for only the channel set by the ANS bits.
Example:
ANS = 0000B, ANE = 0011 B :
Start --> AN0 --> AN1 --> AN2 --> AN3 --> AN0 -->-->--> Repetition of sequence
ANS = 0010 B, ANE = 0010 B:
Start --> AN2 --> AN2 --> AN2 -->-->--> Repetition of sequence
In the continuous mode, A/D conversion is repeated until "0" is written to the BUSY bit (when "0"
is written to the BUSY bit, operation of the A/D converter stops forcibly).
Note that when operation of the A/D converter stops forcibly, A/D conversion stops halfway. In
this case, the conversion result register contains the previous data for which conversion
completed.
■ Stop mode
In the stop mode, analog inputs from the starting channel set by the ANS bits to the ending
channel set by the ANE bits are sequentially converted, but every time one channel is converted,
conversion stops.
482
MB90820 series
When conversion for up to the ending channel is ended, control returns to the starting channel to
continue A/D conversion. When the starting channel and the ending channel are the same (ANS
= ANE), conversion is performed for only one channel.
Example:
ANS = 0000B, ANE = 0011 B :
Start --> AN0 --> Stop --> Start --> AN1 --> Stop --> Start --> AN2 --> Stop --> Start --> AN3 -->
Stop --> Start --> AN0 -->-->--> Repetition of sequence
ANS = 0010 B, ANE = 0010 B:
Start --> AN2 --> Stop --> Start --> AN2 --> Stop --> Start --> AN2 -->-->--> Repetition of
sequence
In the above sequences, only A/D activation causes set using the STS1 and STS0 bits are valid.
The start of conversion can be synchronized by this mode.
MB90820 series
483
17.5 Conversion Using EI2OS
Figure 17.5-1 gives an example of flow (continuous mode) from the activation of A/D
conversion to the transfer of converted data.
■ Conversion using EI2OS
Figure 17.5-1 Example of flow (continuous mode) from activation of A/D conversion
to transfer of converted data
EI2OS controller
A/D conveter
A/D converter activated
Sample & Hold
Data transfer
2
EI OS
request
Conversion
*
Interrupt
processing
Conversion ended
ADCS:INT=0?
N
Y
Store conversion data
to ADCR0/1
interrupt cleared
INT clear
request
*: The operation count depends
2
on the setting of the EI OS.
Interrupt
generated
484
MB90820 series
Memo
MB90820 series
485
17.5.1 Example of activating of EI2OS in single mode
In the single mode, EI2OS is activated in the following procedure:
• Convert analog inputs AN1 to AN3 and then end the conversion.
• Transfer sequentially converted data to the 200H to 205H addresses.
• Activate conversion using software.
• Use the highest interrupt level.
■ Example of starting of EI2OS in single mode
Table 17.5.1-1
Setting item
Operation Description
Sample program
Operation description
MOV ICR03, #08H
Set the highest interrupt level, start EI2OS at the interrupt, and set the
descriptor address.
MOV BAPL, #00H
MOV BAPM, #02H
Transfer destination address for converted data
MOV BAPH, #00H
Setting of
EI2OS
MOV ISCS, #18H
Transfer word data, and then increment the transfer destination address.
Transfer converted data from I/O to the memory. Don't terminate transfer
due to a request from the resource.
MOV IOAL, #6A H
Set the A/D converter result regitster
MOV IOAH, #00H
MOV DCTL, #03H
Performs EI2OS transfer three times (the number of conversion times)
MOV DCTH, #00H
Setting of A/D
converter
MOV ADCS0, #00H
Single mode1
MOVW ADSR0, #6823H
The sampling time is 0.6 µs; the comparison operation time is 2.2 µs (as
machine CLK is 20 MHz); the starting channel is AN1; the ending channel
is AN3.
MOV ADCS1, #A2H
Interrupt
sequence
Start A/D conversion using software.
MOV ADCS1, #80H
RETI
Return from the interrupt.
ICR03: Interrupt control register
BAPL: Buffer address pointer (lower)
BAPM: Buffer address pointer (middle)
BAPH: Buffer address pointer (upper)
ISCS: EI2OS status register
IOAL: I/O address counter (lower)
IOAH: I/O address counter (upper)
486
DCTL: Data counter (lower)
DCTH: Data counter (upper)
MB90820 series
Figure 17.5.1-1 Example of starting of EI2OS in single mode
START
AN1
Interrupt
Transfer by EI2OS
AN2
Interrupt
Transfer by EI2OS
AN3
Interrupt
Transfer by EI2OS
END
Interrupt sequence
Parallel processing
MB90820 series
487
17.5.2 Example of activating of EI2OS in continuous mode
An example of the activating of EI2OS in the continuous mode is given below.
• Convert analog inputs AN3 to AN5 and obtain two converted data for each channel.
• Transfer sequentially converted data to the 600H to 60BH addresses.
• Start conversion using a free-running timer zero detect.
• Use the highest interrupt level.
■ Example of starting of EI2OS in continuous mode
Table 17.5.2-1
Setting item
Operation Description
Sample program
Operation description
MOV ICR03, #08H
Set the highest interrupt level, start EI2OS at the interrupt, and set the
descriptor address.
MOV BAPL, #00H
MOV BAPM, #06H
Transfer destination address for converted data
MOV BAPH, #00H
Setting of
EI2OS
MOV ISCS, #18H
Transfer word data, and then increment the transfer destination address.
Transfer converted data from I/O to the memory. Don't terminate transfer
due to a request from the resource.
MOV IOAL, #6A H
Transfer source address
MOV IOAH, #00H
MOV DCTL, #06H
Transfer converted data by EI2OS six times data for '3 channels × 2'.
MOV DCTH, #00H
Setting of A/D
converter
MOV ADCS0, #80H
Continuous mode
MOVW ADSR0, #6865H
The sampling time is 0.6 µs; the comparison operation time is 2.2 µs (with
machine CLK is 20 MHz); the starting channel is AN3; the ending channel
is AN5.
MOV ADCS1, #A4H
EI2OS end
interrupt
sequence
Start A/D conversion using free-running timer zero detect.
MOV ADCS1, #84H
RETI
Return from the interrupt.
ICR03: Interrupt control register
BAPL: Buffer address pointer (lower)
BAPM: Buffer address pointer (middle)
BAPH: Buffer address pointer (upper)
ISCS: EI2OS status register
IOAL: I/O address counter (lower)
IOAH: I/O address counter (upper)
488
DCTL: Data counter (lower)
DCTH: Data counter (upper)
MB90820 series
Figure 17.5.2-1 Example of starting of EI2OS in continuous mode
START
AN3
Interrupt
EI2OS
AN4
Interrupt
EI2OS
AN5
Interrupt
EI2OS
After transfer 6 times in total:
Interrupt sequence
END
MB90820 series
489
17.5.3 Example of activating of EI2OS in stop mode
An example of the activating of EI2OS in the stop mode is given below.
• Convert the analog input AN3 12 times at regular intervals.
• Transfer sequentially converted data to the 600H to 617H addresses.
• Start conversion using a free-running timer zero detect.
• Use the highest interrupt level.
■ Example of starting of EI2OS in stop mode
Table 17.5.3-1 Operation Description
Setting item
Sample program
Operation description
MOV ICR03, #08H
Set the highest interrupt level, start EI2OS at the interrupt time, and set the
descriptor address.
MOV BAPL, #00H
MOV BAPM, #06H
Transfer destination address for converted data
MOV BAPH, #00H
Setting of
EI2OS
MOV ISCS, #18H
Transfer word data, and then increment the transfer destination address.
Transfer converted data from I/O to the memory. Don't terminate transfer
due to a request from the resource.
MOV IOAL, #6A H
Transfer source address
MOV IOAH, #00H
MOV DCTL, #0CH
Transfer converted data by EI2OS 12 times.
MOV DCTH, #00H
Setting of A/D
converter
MOV ADCS0, #C0H
Stop mode
MOVW ADSR0, #6863H
The sampling time is 0.6 µs; the comparison operation time is 2.2 µs (with
machine CLK is 20 MHz); the starting channel is AN3; the ending channel
is AN3 (1 channel is converted).
MOV ADCS1, #A4H
EI2OS end
interrupt
sequence
Start A/D conversion using the free-running timer zero detect.
MOV ADCS1, #84H
RETI
Return from the interrupt.
ICR03: Interrupt control register
BAPL: Buffer address pointer (lower)
BAPM: Buffer address pointer (middle)
BAPH: Buffer address pointer (upper)
ISCS: EI2OS status register
IOAL: I/O address counter (lower)
IOAH: I/O address counter (upper)
490
DCTL: Data counter (lower)
DCTH: Data counter (upper)
MB90820 series
Figure 17.5.3-1 Example of starting of EI2OS in stop mode
START
AN3
Interrupt
Transfer by EI2OS
After transfer 12 times:
STOP
External edge start
Interrupt sequence
END
MB90820 series
491
17.6 Converted-data Protection Function
The A/D converter has the converted-data protection function, is featured by
continuous conversion and securing two or more data using EI2OS.
Only one converted-data register (ADCR0/1:conversion result data register) is
provided, so when A/D conversion is continuously performed, converted data is stored
every time one conversion is ended, destroying the previous data. To prevent this, the
A/D converter has a function that a converted-data is not stored in the register and the
A/D conversion pauses even when conversion is ended unless the previous data is
transferred to the memory using EI2OS.
■ Converted-data protection function
The pause is cancelled after converted data is transferred to the memory via EI2OS.
When the previous data is already transferred to the memory, A/D conversion is continuously
performed without a pause.
Note:
This function is related to the INT and INTE bits of ADCS1 register.
The data protection function operates only in the interrupt enabled state (INTE = 1).
In the interrupt disabled state (INTE = 0), this function does not operate. In this state when A/D
conversion is continuously performed, converted data is successively stored in the register,
destroying old data.
When EI2OS is not used in the interrupt enabled state (INTE = 1), the INT bit is not cleared
automatically, so the data protection functions works, placing A/D conversion in a pause. In this
case, when the INT bit is cleared(by writing "0" to the bit) in an interrupt sequence, the pause is
cancelled.
When interrupts are disabled(by writing "0" to INTE bit), with EI2OS operating and with the A/D
converter pausing , A/D converter resume conversion and the contents of the converted-data
register may change before it is transferred to memory.
When A/D conversion is reactivated during a pause(by writing "1" to STRT bit in the single
mode1), queued data is destroyed.
When the data protection function works to cause a pause, the PAUS bit is set.
The PAUS bit is not cleared by canceling the pause; to clear it, write "0" to it.
492
MB90820 series
■ Example of flow of data protection function (when EI2OS is used)
Figure 17.6-1 Example of flow of data protection function (when EI2OS is used)
2
Set El OS
Start continuous A/D conversion
First conversion end
Store in data register
2
Second conversion end
Start EI OS
NO
A/D conversion pauses
2
EI OS end
YES
Stored in data register
YES
2
EI OS end
NO
Third conversion end
Continues
2
All conversions end
Start EI OS
Interrupt routine
End
A/D converter stopp
When the A/D converter is reactivated during a pause, queued, converted data is destroyed.
■ Cautions
To select the free-running timer zero detect or the internal timer as the activation causes of A/D
converted, the A/D start source select bits (STS1 and STS0 bits) of ADCS1 register are used.
In this case, ensure that the input value of a free-running timer zero detect or of the internal
timer are "inactive". If the values are "active", A/D conversion may start operating immediately.
When setting the STS1 bit and STS0 bit, always set the free-running timer zero detect to "1"
(input) and set the internal timer (reload timer 1) to "0" (output).
MB90820 series
493
494
MB90820 series
CHAPTER 18
D/A CONVERTER
This chapter explains the functions and operation of the Digital/Analog (D/A) converter.
18.1 Overview of D/A Converter
18.2 Block Diagram of D/A Converter
18.3 D/A Converter Pins
18.4 D/A Converter Registers
18.5 Sample Programs for the D/A Converter
MB90820 series
495
18.1 Overview of D/A Converter
The Digital/Analog (D/A) Converter converts an 8-bit digital input into an analog output
by using R-2R method. The D/A converter has two channels. Output control can be
executed individually for each channel by using its D/A control register .
■ Function and operation of the D/A converter
This circuit is used to generate an analog output from an 8-bit digital input. By setting the enable
bit in the D/A control register (DACR) to 1, it will enable the corresponding D/A output channel.
Hence, setting this bit to 0 will disable that channel.
If D/A output is disabled, the analog switch inserted to the output of each D/A converter channel
in series is turned off. In the D/A converter, the bit is cleared to 0 and the direct-current path is
shut off. The above is also true in the stop mode.
The output voltage of the D/A converter ranges from 0 V to 255/256 x AVCC. To change the
output voltage range, adjust the AVCC voltage externally.
The D/A converter output does not have the internal buffer amplifier. The analog switch (= 100
Ω) is inserted to the output in series. To apply load to the output externally, estimate a sufficient
stabilising time.
Table 18.1-1 lists the theoretical values of output voltage of the D/A converter.
Table 18.1-1 Theoretical values of output voltage of the D/A converter
496
Value written to DA07 to DA00
and DA17 to DA10
Theoretical value of output voltage
00H
0/256 × AVCC (=0 V)
01H
1/256 × AVCC
02H
2/256 × AVCC
:
:
FDH
253/256 × AVCC
FEH
254/256 × AVCC
FFH
255/256 × AVCC
MB90820 series
18.2 Block Diagram of D/A Converter
This section shows the block diagram of D/A converter
■ D/A converter block diagram
F 2 M2C16LX-BUS
DA DA DA DA DA DA DA DA
17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA
07 06 05 04 03 02 01 00
AVCC
AVCC
DA17
DA07
2R
2R
R
DA16
R
DA06
2R
2R
R
R
DA15
DA05
DA11
DA01
2R
2R
R
DA10
R
DA00
2R
2R
2R
2R
DAE1
DAE0
Standby control
Standby control
DA output ch.1
DA output ch.0
Figure 18.2-1 Block diagram of D/A converter
MB90820 series
497
18.3 D/A Converter Pins
This section describes the pins of the D/A converter and provides a pin block diagram.
■ D/A converter pins
The pins of the D/A converter are shared with the general-purpose ports. Table 18.3-1 lists the
functions of the pins, I/O format, and settings required to use the D/A converter.
Table 18.3-1 D/A converter pins
Pin name
Pin function
I/O format
Pull-up option
Standby
P70/DA0/AN8
Port 7 inputoutput / Analog
D/A converter
pins
Analog/CMOS
output / CMOS
hysteresis input
Not provided
Provided
P71/DA1/AN9
Settings required for pins
DACR0:DAE0=”1”
DACR1:DAE1=”1”
■ Block diagram of the D/A converter pins
AD converter channel selection bit
AD converter input
Internal data bus
Port data register (PDR)
DA converter output
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
DA converter output enable bit
Figure 18.3-1 Shows the block diagram of the D/A converter pins.
498
MB90820 series
18.4 D/A Converter Registers
The D/A converter has the following two types of registers :
• D/A converter registers (DAT0 and DAT1)
• D/A control registers (DACR0 and DACR1)
■ D/A converter registers
D/A converter register 1
Bit
Address:0000CDH
Read/write
Initial value
15
14
13
12
DA17 DA16 DA15 DA14
11
10
DA13
DA12
9
8
DA11 DA10 DAT1
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
7
6
5
4
3
2
1
0
DA03
DA02
D/A converter register 0
Bit
Address:0000CCH
DA07
Read/write
Initial value
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
DAE1 DACR1
X
X
X
X
X
X
X
R/W
0
7
6
5
4
3
2
1
0
-
-
-
-
-
-
DAE0 DACR0
X
X
X
X
X
X
X
R/W
0
DA06 DA05 DA04
DA01 DA00 DAT0
D/A control register 1
Bit
Address:0000CFH
Read/write
Initial value
D/A control register 0
Bit
Address:0000CE H
Read/write
Initial value
Figure 18.4-1 D/A converter registers
MB90820 series
499
18.4
D/A Converter Registers
18.4.1 D/A converter register 1 (DAT1)
The D/A Converter Register 1 is used to set the digital input data for channel 1, which
will be converted into an analog output.
■ D/A converter register 1 (DAT1)
D/A converter register 1
15
Bit
Address:0000CDH
Read/write
Initial value
R/W
X
14
13
12
DA17 DA16 DA15 DA14
R/W
X
R/W
X
R/W
X
R/W
X
11
10
DA13
DA12
R/W
X
R/W
X
9
8
DA11 DA10 DAT1
R/W
X
R/W
X
: Read and write
: Unknown
Figure 18.4.1-1 D/A converter register 1 (DAT1)
The D/A converter register 1 (DAT1) is used to set the digital input data for channel 1, which will be
converted into an analog output.
500
MB90820 series
18.4
D/A Converter Registers
18.4.2 D/A Converter Register 0 (DAT0)
The D/A Converter Register 0 is used to set the digital input data for channel 0, which
will be converted into an analog output.
■ D/A converter register 0 (DAT0)
D/A converter register 0
Bit
7
Address:0000CC H
DA07
Read/write
Initial value
R/W
X
R/W
X
6
5
4
3
DA06 DA05 DA04 DA03
R/W
X
R/W
X
R/W
X
R/W
X
2
DA02
R/W
X
1
0
DA01 DA00 DAT0
R/W
X
R/W
X
: Read and write
: Unknown
Figure 18.4.2-1 D/A converter register 0 (DAT0)
The D/A converter register 0 (DAT0) is used to set the digital input data for channel 0, which will be
converted into an analog output.
MB90820 series
501
18.4
D/A Converter Registers
18.4.3 D/A Control Register 1 (DACR1)
The D/A Control Register 1 is used to keep the output enable signal for channel 1.
■ D/A control register 1 (DACR1)
bit15
Address 0000CFH
Read/write
Initial value
-
bit14 bit13 bit12 bit11 bit10
-
-
-
-
-
bit9
-
bit8
Initial value
DAE1 XXXXXXX0B
-
-
-
-
-
-
-
R/W
X
X
X
X
X
X
X
0
R/W : Read and write
-
: Unused
X
: Unknown
DAE1
D/A output enable bit for channel 1
0
Disable
1
Enable
: Initial value
Figure 18.4.3-1 D/A control register 1 (DACR1)
Table 18.4.3-1 D/A control register 1 (DACR1)
Bit name
502
Function
bit15
bit14
bit13
bit12
bit11
bit10
bit 9
Unused bit
• The read value is indeterminate.
• Writing to this bit has no effect on the operation.
bit 8
DAE1 :
D/A output
enable bit for
channel 1
• This bit is used to determine if D/A converter output is enabled or disabled.
DAE1 is responsible for channel 1.
• Writing “1” to this bit enables D/A output; similarly “0” disables D/A output.
• This bit is initialized to “0” at reset.
• This bit can be read and written.
MB90820 series
18.4
D/A Converter Registers
18.4.4 D/A Control Register 0 (DACR0)
The D/A Control Register 0 is used to keep the output enable signal for channel 0.
■ D/A control register 0 (DACR0)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
X
X
X
X
X
X
X
0
Address 0000CEH
Read/write
Initial value
bit0
Initial value
DAE0 XXXXXXX0B
R/W : Read and write
-
: Unused
X
: Unknown
: Initial value
DAE0
D/A output enable bit for channel 0
0
Disable
1
Enable
Figure 18.4.4-1 D/A control register 0 (DACR0)
Table 18.4.4-1 D/A control register 0 (DACR0)
Bit name
bit
bit
bit
bit
bit
bit
bit
7
6
5
4
3
2
1
bit 0
MB90820 series
Function
Unused bit
• The read value is indeterminate.
• Writing to this bit has no effect on the operation.
DAE0 :
D/A output
enable bit for
channel 0
• This bit is used to determine if D/A converter output is enabled or disabled.
DAE0 is responsible for channel 0.
• Writing “1” to this bit enables D/A output; similarly “0” disables D/A output.
• This bit is initialized to “0” at reset.
• This bit can be read and written.
503
18.5 Sample Programs for the D/A Converter
This section contains sample programs for the D/A converter.
■ Sample program for the D/A converter
● Processing specification
•
Convert a byte to analog and output to Port 7 bit 0.
● Coding example
/* Insert below initialization routines for :
User/System stacks,
Direct page register,
Register bank,
Interrupt level mask register,
main() routine start address - reset vector starting address */
/* Insert below definition of registers in structure :
structure of DACR0 */
/* Insert below definition of register location for :
DAT0, DACR0 */
void main(void)
{
IO_DACR0.byte = 1;
IO_DAT0 = 0;
__asm("nop");
__asm("nop");
__asm("nop");
IO_DAT0 = 0x80;
__asm("nop");
__asm("nop");
__asm("nop");
IO_DAT0 = 0xff;
__asm("nop");
__asm("nop");
__asm("nop");
/*enable DAC channel 0*/
/*output 0V for a while*/
/*short delay*/
/*output 1/2 AVCC for a while*/
/*short delay*/
/*output AVCC for a while*/
/*short delay*/
}
504
MB90820 series
CHAPTER 19
UART
This chapter explains the functions and operation of UART.
19.1 Overview of UART
19.2 Block Diagram of UART
19.3 UART Pins
19.4 UART Registers
19.5 UART Interrupts
19.6 UART Baud Rates
19.7 Operation of UART
19.8 Usage Notes on UART
19.9 Sample Program for UART
MB90820 series
505
19.1 Overview of UART
UART is a general-purpose serial data communication interface for performing
synchronous or asynchronous (start-stop synchronization) communication with
external devices. The UART has a normal bidirectional communication function
(normal mode), additionally the master-slave communication function (multiprocessor
mode) is only available for the master system.
■ UART functions (x 2)
● UART functions
UART is a general-purpose serial data communication interface for transmitting serial data to
and receiving data from another CPU and peripheral devices. It has the functions listed in
Table 19.1-1.
Table 19.1-1 UART functions
Function
Data buffer
Full-duplex, double buffering
Transfer mode
• Clock synchronous
• Clock asynchronous (start-stop synchronization)
Baud rate
• A dedicated baud rate generator is provided. Eight settings can be
selected
• An external clock can be input
• Internal clock (internal clocks supplied from 16-bit reload timer 0
can be used)
Data length
• 7 bits (in asynchronous normal mode only)
• 8 bits
Signal mode
Non-return to zero (NRZ)
Reception error
detection
• Framing error
• Overrun error
• Parity error (cannot be detected in multiprocessor mode)
Interrupt request
• Reception interrupt (reception completion and reception error
detection)
• Transmission interrupt (transmission completion)
• Extended intelligent I/O service (EI2OS) is available for both
transmission and reception interrupts
Master-slave
communication function
(multiprocessor mode)
One-to-n communication (one master to n slaves) can be performed
(this function is supported only for the master system)
<Check>
During clock synchronous transfer, start and stop bits are not added so only data is
transferred in UART.
506
MB90820 series
Table 19.1-2 UART operation mode
Data length
Operation mode
When parity is
disabled
Synchronizati
on mode
When parity is
enabled
0
Normal mode
7 or 8 bits
1
Multiprocessor
8+1*1
–
Asynchronous
2
Normal mode
8
–
Synchronous
Stop bit length
Asynchronous
1 or 2 bits *2
None
: Setting not possible.
*1: "+1" indicates the address/data selection bit (A/D) for communication control.
*2: During reception, only one stop bit can be detected.
■ UART interrupt and EI²OS
Table 19.1-3 UART interrupt and EI²OS
Interrupt cause
Interrupt
number
Interrupt control register
Vector table address
EI²OS
Register name
Address
Lower
Upper
Bank
UART1
reception
interrupt
#37(25H)
ICR13
0000BDH
FFFF68H
FFFF69H
FFFF6AH
UART1
transmission
interrupt
#38(26H)
ICR13
0000BDH
FFFF64H
FFFF65H
FFFF66H
∆
UART0
reception
interrupt
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
UART0
transmission
interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
∆
: Provided with a function that detects a UART reception error and stops EI²OS
∆: Usable when ICR13 and ICR14 or interrupt causes that share an interrupt vector are not
used
MB90820 series
507
19.2 Block Diagram of UART
UART consists of the following 11 blocks, the block diagram is shown in Figure 19.2-1.
■ Block diagram of UART
From
communication
prescaler
Reception interrupt
#39 (27H)*
<#37 (25H)*>
Baud rate
generator
Reception clock
External clock
Reception control
circuit
Transmission control
circuit
Start bit detect
circuit
Transmission
start circuit
P45/SIN0
<P72/SIN1>
Reception status
judgment circuit
Reception bit
counter
Transmission bit
counter
Reception parity
counter
Transmission
parity counter
Reception shifter
Start of transmission
Control bus
P43/SCK0
<P74/SCK1>
Transmission
interrupt
#40 (28H)*
<#38 (26H)*>
Transmission clock
End of reception
16-bit reload timer
Clock
selection
circuit
P44/SOT0
<P73/SOT1>
Transmission shifter
SIDR0/1
SODR0/1
EI2OS reception error
signal (to CPU)
F2MC-16LX bus
SMR0/1
register
MD1
MD0
CS2
CS1
CS0
RST
SCKE
SOE
SCR0/1
register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR0/1
register
*: Interrupt number
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
Control signal
Figure 19.2-1 Block diagram of UART
508
MB90820 series
● Clock selector
The clock selector selects the dedicated baud rate generator, external input clock, or internal
clock (clock supplied from the 16-bit reload timer) as the transmitting and receiving clocks.
● Reception control circuit
The reception control circuit consists of a received bit counter, start bit detection circuit, and
received parity counter. The received bit counter counts receive data bits. When reception of
one data item for the specified data length is complete, the received bit counter generates a
reception interrupt request. The start bit detection circuit detects start bits from the serial input
signal. When the circuit detects a start bit, it writes data in the SIDR1 register by shifting at the
specified transfer rate. The received parity counter calculates the parity of the receive data.
● Transmission control circuit
The transmission control circuit consists of a transmission bit counter, transmission start circuit,
and transmission parity counter. The transmission bit counter counts transmission data bits.
When transmission of one data item of the specified data length is complete, the transmission bit
counter generates a transmission interrupt request. The transmission start circuit starts
transmission when data is written to SODR0/1. The transmission parity counter generates a
parity bit for data to be transmitted when parity is enabled.
● Reception shift register
The reception shift register fetches receive data input from the SIN pin, shifting the data bit by
bit. When reception is complete, the reception shift register transfers receive data to the SIDR0/
1 register.
● Transmission shift register
The transmission shift register transfers data written to the SODR0/1 register to itself and
outputs the data to the SOT pin, shifting the data bit by bit.
● Mode control register 1 (SMC0/1)
This register performs the following operations:
•
Selecting a UART operation mode
•
Selecting a clock input source
•
Setting up the dedicated baud rate generator
•
Selecting a clock rate (clock division value) when using the dedicated baud rate generator
•
Specifying whether to enable serial data output to the corresponding pin
•
Specifying whether to enable clock output to the corresponding pin
MB90820 series
509
● Control register 1 (SCR0/1)
This register performs the following operations:
•
Specifying whether to provide parity bits
•
Selecting parity bits
•
Specifying a stop bit length
•
Specifying a data length
•
Selecting a frame data format in mode 1
•
Clearing a flag
•
Specifying whether to enable transmission
•
Specifying whether to enable reception
● Status register 1 (SSR0/1)
This register checks the transmission and reception status and error status, and enables and
disables transmission and reception interrupt requests.
● Input data register 1 (SIDR0/1)
This register retains receive data. Serial input data is converted and stored in this register.
● Output data register 1 (SODR0/1)
This register sets transmission data. Data written to this register is converted to serial data and
output.
510
MB90820 series
Memo
MB90820 series
511
19.3 UART Pins
This section describes the UART pins and provides a pin block diagram.
■ UART pins
The UART pins also serve as general ports. Table 19.3-1 lists the pin functions, I/O formats and
settings required to use UART.
Table 19.3-1 UART pins
Pin name
Pin function
I/O format
Pull-up
Standby
control
Setting required to use pin
P45/SIN0
Port 4 I/O or serial
data input
Set as an input port
(DDR4: bit 5 = 0)
P44/SOT0
Port 4 I/O or serial
data output
Set to output enable mode
(SMR0: SOE = 1)
CMOS output and
CMOS hysteresis
input
P43/SCK0
Not provided
Provided
Port 4 I/O or serial
clock input/output
Set as an input port when a
clock is input
(DDR4: bit 3 = 0 )
Set to output enable mode
when a clock is output
(SMR0: SCKE = 1)
P72/SIN1
Port 7 I/O or serial
data input
Set as an input port
(DDR7: bit 10 = 0)
P73/SOT1
Port 7 I/O or serial
data output
Set to output enable mode
(SMR1: SOE = 1)
CMOS output and
CMOS hysteresis
input
P74/SCK1
512
Port 7 I/O or serial
clock input/output
Not provided
Provided
Set as an input port when a
clock is input
(DDR7: bit 12 = 0)
Set to output enable mode
when a clock is output
(SMR1:SCKE = 1)
MB90820 series
■ Block diagram of UART pins
UART0 data input
UART0 data input
level selection bit
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 19.3-1 Block diagram of UART serial data input pin(P45)
Resource output
Internal data bus
Port data register (PDR)
Resource input
Resource output enable
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Figure 19.3-2 Block diagram of UART serial clock input/output pin(P43) & serial data output pin(P44)
MB90820 series
513
AD converter channel selection bit
AD converter input
UART1 data input
UART1 data input
level selection bit
Internal data bus
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
Figure 19.3-3 Block diagram of UART serial data input pin(P72)
AD converter input
AD converter channel selection bit
Resource input
Resource output
Internal data bus
Port data register (PDR)
Resource output enable
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL=1)
ADER
Figure 19.3-4 Block diagram of UART serial clock input/output pin(P74) & serial data output pin(P73)
514
MB90820 series
19.4 UART Registers
The following figure shows the UART registers.
■ UART registers
Serial Control Register
15
Address: ch0 000021H
ch1 000025H
14
13
12
11
10
9
8
Bit number
SCR0/1
PEN
P
R/W
0
R/W
0
Read/write
Initial value
SBL
CL
R/W
0
A/D
R/W
0
REC
RXE
TXE
W
1
R/W
0
R/W
0
R/W
0
Serial Mode Register
7
6
5
4
3
2
1
0
MD0
CS2
CS1
CS0
RST
SCKE SOE
Bit number
SMR0/1
Address: ch0 000020H
ch1 000024H
MD1
Read/write
Initial value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
14
13
12
11
10
R/W
0
R/W
0
UART Status Register
15
Address: ch0 000023H
ch1 000027H
Read/write
Initial value
9
8
Bit number
SSR0/1
PE
ORE
R
0
R
0
FRE
RDRF TDRE
R
0
R
0
R
1
BDS
RIE
TIE
R/W
0
R/W
0
R/W
0
3
2
UART Input Data Register / Output Data Register
7
Address: ch0 000022H
ch1 000026H
Read/write
Initial value
6
5
4
1
0
Bit number
SIDR0~1 /
SODR0~1
D7
D6
D5
D4
D3
D2
D1
D0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Clock Division Control Register
15
14
Address: ch0 000035H
ch1 000037H
MD
ILS
Read/write
Initial value
R/W
0
R/W
0
13
12
11
10
9
8
Bit number
CDCR0/1
X
X
X
DIV2
DIV1
DIV0
R/W
0
R/W
0
R/W
0
Figure 19.4-1 UART registers
MB90820 series
515
19.4
UART Registers
19.4.1 Serial Control Register (SCR0/1)
This register specifies parity bits, selects the stop bit and data lengths, selects a frame
data format in mode 1, clears the reception error flag, and specifies whether to enable
transmission and reception.
■ Serial control register (SCR0/1)
Address
bit15 bit14 bit13 bit12 bit11 bit10 bit9
ch0:000021 H
c h 1 : 0 0 0 0 2 5 H PEN
P
SBL
CL
A/D
R/W R/W R/W R/W R/W
bit8 bit7
Initial value
0 0 0 0 0 1 0 0B
R/W R/W
TXE
Transmission enable bit
0
Disables transmission
1
Enables transmission
RXE
Reception enable bit
0
Disables reception
1
Enables reception
REC
Reception error flag clear bit
0
Clears the FRE, ORE, and PE flags
1
Has no effect on the others
A/D
Address/data selection bit
0
Data frame
1
Address frame
CL
Data length selection bit
0
7 bits
1
8 bits
SBL
Stop bit length selection bit
0
1-bit length
1
2-bit length
P
Parity selection bit
Enabled only when parity is provided (PEN=1)
0
Even parity
1
Odd parity
PEN
R/W : Read/Write
W : Write only
y : Initial value
(SMR)
REC RXE TXE
W
bit0
Parity enable bit
0
Provides no parity bit
1
Provides a parity bit
Figure 19.4.1-1 Serial control register (SCR0/1)
516
MB90820 series
Table 19.4.1-1 Serial control register (SCR0/1)
Bit name
Function
• This bit selects whether to add a parity bit during transmission in
bit15
PEN:
Parity enable bit
serial data input-output mode or to detect it during reception.
<Caution>
No parity can be used in operation modes 1 and 2. Therefore, fix
this bit to 0.
bit14
P:
Parity selection bit
• When parity is provided (PEN = 1), this bit selects an even or odd
bit13
SBL:
Stop bit length
selection bit
bit12
CL:
Data length
selection bit
bit11
A/D:
Address/data
selection bit
parity.
• This bit selects the length of the stop bits or the frame end mark of
send data in asynchronous transfer mode.
<Caution>
During reception, only the first bit of the stop bits is detected.
• This bit specifies the length of send and receive data.
<Caution>
Seven bits can be selected in operation mode 0 (asynchronous)
only. Be sure to select eight bits (CL = 1) in operation mode 1
(multiprocessor mode) and operation mode 2 (synchronous).
• Specify the data format of a frame to be sent or received in
multiprocessor mode (mode 1).
• Select usual data when this bit is 0, and select address data when
the bit is 1.
• This bit clears the FRE, ORE and PE flags of the status register
(SSR).
bit10
REC:
Reception error flag
clear bit
• Write 0 to this bit to clear the FRE, ORE and PE flag. Writing 1 to
this bit has no effect on the others.
<Caution>
If UART is active and a reception interrupt is enabled, clear the
REC bit only when the FRE, DRE or PE flag indicates 1.
• This bit controls UART reception.
• When this bit is 0, reception is disabled. When it is 1, reception is
bit9
bit8
MB90820 series
RXE:
Reception
enable bit
TXE:
Transmission
enable bit
enabled.
<Caution>
If this bit is cleared during reception, reception can only be disabled
until the reception of current frame is completed and the reception
data is stored in the reception data is stored in the input data register SIDR0/1.
• This bit controls UART transmission.
• When this bit is 0, transmission is disabled. When the bit is 1,
transmission is enabled.
<Caution>
If this bit is cleared during transmission, transmission can only be
disabled until all data in the output data register SOR0/1 has been
transmitted.
517
19.4
UART Registers
19.4.2 Serial Mode Register (SMR0/1)
This register selects an operation mode and baud rate clock and specifies whether to
enable output of serial data and clocks to the corresponding pin.
■ Serial mode register (SMR0/1)
Address
ch0:000020H
ch1:000024H
bit15
bit8 bit7
(SCR)
bit6
bit5
bit4
bit3
bit1
bit0
Initial value
MD1 MD0 CS2 CS1 CS0 RST SCKE SOE 0 0 0 0 0 0 0 0 B
R/W R/W R/W R/W R/W
SOE
R/W R/W R/W
0
Serial data output enable bit
Uses the pin as a general I/O port
1
Uses the pin as the serial data output pin of UART
SCKE
Serial clock output enable bit
0
Uses the pin as a general I/O port or clock input pin of UART
1
Uses the pin as the clock output pin of UART
RST
UART reset bit
0
No effect
1
resets UART
CS2~0
Clock selection bit
"000B"~"100B"
Baud rate by dedicated baud rate generator
"101B"
Disables setting.
"110B"
Baud rate by internal timer
( 16 bit reload timer )
"111B"
Baud rate by external clock
Operation mode selection bit
MD1 MD0
R/W : Enables read and write.
: Initial value
bit2
Operation mode
0
0
0
Asynchronous (normal mode)
0
1
1
1
0
2
Asynchronous (multiprocessor mode)
Synchronous (normal mode)
1
1
-
Disables setting.
Figure 19.4.2-1 Serial mode register (SMR0/1)
518
MB90820 series
Table 19.4.2-1 Serial mode register (SMR0/1)
Bit name
Function
• These bits select an operation mode.
bit7
bit6
MD1, MD0:
Operation mode
selection bits
<Caution>
Operation mode 1 (multiprocessor mode) can be used only from the
master system during master-slave communication. UART cannot
be used from the slave system because it has no address/data
detection function during reception.
• These bits select the baud rate clock source. When the dedicated
bit5
bit4
bit3
CS2 ~ CS0:
Clock selection bits
•
•
bit2
RST:
UART reset bit
baud rate generator is selected, the baud rate is determined by the
value of these bits.
When the dedicated baud rate generator is selected, six baud rates
can be selected for asynchronous/synchronous transfer mode. With
the baud rate generated by internal and external timer, there are
totally eight baud rate selections.
Input clocks can be selected from external clocks (SCK0/1 pin),
16-bit reload timer 0, and the dedicated baud rate generator.
• Writing 0 to this bit has no effect.
• Writing 1 to this bit resets the UART.
• Always read as 0.
• This bit controls the serial clock input-output ports.
• When this bit is 0, the P43/SCK0 and P74/SCK1 pins operate as
bit1
SCKE:
Serial clock output
enable bit
general input-output ports (P43 and P74) or serial clock input pins.
When this bit is 1, the pins operate as serial clock output pins.
<Caution>
•When using the P43/SCK0 and P74/SCK1 pins as serial clock
input (SCKE = 0) pins, set the P43 and P74 as input ports. Also,
select external clocks (SMR0/1: CS2 ~ CS0 = 111B) using the
clock selection bits.
•When using the pins as serial clock output (SCKE = 1) pins, select
clocks other than external clocks (other than SMR0/1: CS2 ~ CS0
= 111B).
[Reference]
When the SCK0/1 pin is assigned to serial clock output (SCKE = 1),
it functions as the serial clock output pin regardless of the status of
the general input-output ports.
• This bit enables or disables the output of serial data.
• When this bit is 0, the P44/SOT0 and P73/SOT1 pins operate as
bit0
MB90820 series
SOE:
Serial data output
enable bit
general input-output ports (P44 and P73). When this bit is 1, the
P44/SOT0 and P73/SOT1 pins operate as serial data output pins
(SOT0/1).
[Reference]
When serial data is output (SOE = 1), the enabled, the P44/SOT0
and P73/SOT1pins function as SOT0/1 pins regardless of the status of general input-output ports (P44 and P73).
519
19.4
UART Registers
19.4.3 Serial Status Register (SSR0/1)
This register checks the transmission and reception status and error status, and
enables and disables the transmission and reception interrupts.
■ Serial status register (SSR0/1)
Address
ch0:000023 H
ch1:000027 H
bit15 bit14 bit13 bit12 bit11 bit10 bit9
PE
R
ORE FRE RDRF TDRE BDS RIE
R
R
R
R
bit8 bit7
TIE
bit0
(SIDR/SODR)
Initial value
00001000B
R/W R/W R/W
TIE
Transmission interrupt request enable bit
0
Disables output of transmission interrupt request
1
Enables output of transmission interrupt request
RIE
Reception enable bit
0
Disables output of reception interrupt request
1
Enables output of reception interrupt request
BDS
Transfer direction selection bit
0
LSB first (transfer from the least significant bit)
1
MSB first (transfer from the most significant bit)
TDRE
Transmission data empty flag bit
0
Transmission data exists
(Writing transmission data is not allowed)
1
Transmission data does not exist.
(Writing transmission data is allowed)
RDRF
Receive data full flag bit
0
No receive data exists
1
Receive data exists
Framing error flag bit
FRE
0
No framing error occurred
1
ORE
-
: Not used
X : Indefinite
y : Initial value
Overrun error flag bit
0
No overrun error occurred
1
An overrun error occurred
PE
R/W : Read/Write
R : Read only
A framing error occurred
Parity error flag bit
0
No parity error occurred
1
A parity error occurred
Figure 19.4.3-1 Serial status register (SSR0/1)
520
MB90820 series
Table 19.4.3-1 Functions of each bit of status register (SSR0/1)
Bit name
bit15
PE:
Parity error flag bit
bit14
ORE:
Overrun error flag
bit
bit13
FRE:
Framing error flag
bit
bit12
RDRF:
Receive data full
flag bit
bit11
TDRE:
Transmission data
empty flag bit
Function
• This bit is set to 1 when a parity error occurs during reception and is cleared when
0 is written to the RFC bit of the mode control register (SMR0/1).
• A reception interrupt request is output when this bit and the RIE bit are 1.
• Data in input data register (SIDR0/1) is invalid when this flag is set.
• This bit is set to 1 when an overrun error occurs during reception and is cleared
when 0 is written to the RFC bit of the mode control register (SMR0/1).
• A reception interrupt request is output when this bit and the RIE bit are 1.
• Data in the input data register (SIDR0/1) is invalid when this flag is set.
• This bit is set to 1 when a framing error occurs during reception and is cleared
when 0 is written to the RFC bit of the mode control register (SMR0/1).
• A reception interrupt request is output when this bit and the RIE bit are 1.
• Data in the input data register (SIDR0/1) is invalid when this flag is set.
• This flag indicates the status of the input data register (SIDR0/1).
• This bit is set to 1 when receive data is loaded into SIDR0/1 and is cleared to 0
when input data register SIDR0/1 is read.
• A reception interrupt request is output when this bit and the RIE bit are 1.
• This flag indicates the status of output data register (SODR0/1).
• This bit is cleared to 0 when transmission data is written to SODR0/1 and is set to
1 when data is loaded into the transmission shift register and transmission starts.
• A transmission interrupt request is output when this bit and the RIE bit are 1.
<Caution>
This bit is set to 1 (SODR0/1 empty) as its initial value.
• This bit selects whether to transfer serial data from the least significant bit (LSB
bit10
BDS:
Transfer direction
selection bit
bit9
RIE:
Reception interrupt
request enable bit
bit8
TIE:
Transmission
interrupt request
enable bit
MB90820 series
first, BDS = 0) or the most significant bit (MSB first, BDS = 1).
<Caution>
The high-order and low-order sides of serial data are interchanged with each
other during reading from or writing to the serial data register. If this bit is set to
another value after the data is written to the SDR register, the data becomes
invalid.
• This bit enables or disables input of a request for transmission interrupt to the
CPU.
• A reception interrupt request is output when this bit and the receive data flag bit
(DRRF) are 1 or this bit and one or more error flag bits (PE, ORE and FRE) are 1.
• This bit enables or disables output of a request for transmission interrupt to the
CPU.
• A transmission interrupt request is output when this bit and the TDRE bit are 1.
521
19.4
UART Registers
19.4.4 Input Data Register (SIDR0/1) and Output Data Register (SOR0/1)
The input data register (SIDR0/1) is a serial data reception register. The output data
register (SODR0/1) is a serial data transmission register. Both SIDR0/1 and SODR0/1
registers are located in the same address.
■ Input data register (SIDR0/1)
Figure 19.4.4-1 shows the bit configuration of input data register 1.
Serial input data register
Address : 000022H
000026H
Read/write
Initial value
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
(R)
(X)
Bit number
SIDR0
SIDR1
Figure 19.4.4-1 Input data register (SIDR0/1)
SIDR0/1 is a register that contains receive data. The serial data signal transmitted to the SIN0/1
pin is converted in the shift register and stored there. When the data length is 7 bits, the
uppermost bit (D7) contains invalid data. When receive data is stored in this register, the receive
data full flag bit (SSR0/1: RDRF) is set to 1. If a reception interrupt request is enabled at this
point, a reception interrupt occurs.
Read SIDR0/1 when the RDRF bit of the status register (SSR0/1) is 1. The RDRF bit is cleared
automatically to 0 when SIDR01/1 is read.
Data in SIDR0/1 is invalid when a reception error occurs (SSR0/1: PE, ORE or FRE = 1).
■ Output data register (SODR0/1)
Figure 19.4.4-2 shows the bit configuration of the output data register.
Serial output data register
Address : 000022H
000026H
Read/write
Initial value
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
(W)
(X)
Bit number
SODR0
SODR1
Figure 19.4.4-2 Output data register (SODR0/1)
When data to be transmitted is written to this register in transmission enable state, it is
transferred to the transmission shift register, then converted to serial data, and transmitted from
the serial data output terminal (SOT0/1 pin). When the data length is 7 bits, the uppermost bit
(D7) contains invalid data.
When transmission data is written to this register, the transmission data empty flag bit (SS0/1:
522
MB90820 series
TDRE) is cleared to 0. When transfer to the transmission shift register is complete, the bit is set
to 1. When the TDRE bit is 1, the next piece of transmission data can be written. If output
transmission interrupt requests have been enabled, a transmission interrupt is generated. Write
the next piece of transmission data when a transmission interrupt is generated or the TDRE bit is
1.
<Check>
SODR0/1 is a write-only register and SIDR0/1 is a read-only register. These registers are
located in the same address, so the read value is different from the write value. Therefore,
instructions that perform a read-modify-write (RMW) operation, such as the INC/DEC
instruction, cannot be used.
MB90820 series
523
19.4
UART Registers
19.4.5 Communication Prescaler Control Register (CDCR)
This register controls the division of machine clocks.
■ Communication prescaler control register (CDCR)
The operation clocks of UART can be obtained by dividing machine clocks. UART is designed to
obtain certain baud rates for various machine cycles. Output from the communication prescaler
is used for the operation clocks of I/O extended serial interfaces. The CDCR bit configuration is
shown below.
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
000035H
000037H
MD
ILS
—
—
—
DIV2
DIV1
DIV0
0XXXX000B
R/W
R/W
—
—
—
R/W
R/W
R/W
MD
DIV2
DIV1
DIV0
div
0
—
—
—
Setting not allowed
1
0
0
0
1
1
0
0
1
2
1
0
1
0
3
1
0
1
1
4
1
1
0
0
5
1
1
0
1
6
1
1
1
0
7
1
1
1
1
8
ILS
0
Select data input (SIN) as hysteresis level
1
Select data input (SIN) as CMOS level
MD
X
: Indeterminate
R/W : Read and write
SIN input level select
Machine clock divide mode select
0
Stops the communication prescaler.
1
Operates the communication prescaler.
: Initial value
—
: Not used
Figure 19.4.5-1 Communication prescaler control register
524
MB90820 series
Table 19.4.5-1 Communication prescaler control register
Bit name
MB90820 series
Function
bit15
MD:
Machine clock
divide mode
select bit
• This bit is the operation enable bit of the communication
prescaler.
• When 0 is set, the communication prescaler stops.
• When 1 is set, the communication prescaler operates.
bit 14
ILS:
SIN input level
select bit
• This bit select input level of UART data input pin (SIN)
• Write “0” selects hysteresis input level.
• Write “1” selects CMOS input level.
bit13
bit12
Reserved bits
• Always read as 0.
bit10
bit9
bit8
DIV2 ~ 0:
Machine clock
division bits
• These bits determines the machine clock division ratios.
• Division ratios can only be set when MD is 1.
Note: If division ratio is changed, wait 2 cycles as stabilization
time before starting communication.
525
19.5 UART Interrupts
UART uses both reception and transmission interrupts. An interrupt request can be
generated for either of the receive data is set in the input register (SIDR0/1), or a
reception error occurs and transmission data is transferred from output data register 1
(SODR0/1) to the transmission shift register.
The extended intelligent I-O service (EI²OS) is available for these interrupts.
■ UART interrupts
Table 19.5-1 lists the interrupt control bits and causes of UART.
Table 19.5-1 Interrupt control bits and interrupt causes of UART
Reception/
transmission
Interrupt
request flag bit
Reception
Transmission
Operation mode
Interrupt cause
0
1
2
RDRF
O
O
O
Loading receive
data into buffers
(SIDR0/1)
ORE
O
O
O
Overrun error
FRE
O
O
X
Framing error
PE
O
X
X
Parity error
TDRE
O
O
O
Empty transmission
buffer (SODR0/1)
Interrupt cause
enable bit
When interrupt
request flag is
cleared
Receive data is
read
SSR0/1:RIE
0 is written to the
reception error
flag clear bit
(SSR0/1: REC)
SSR0/1:TIE
Transmission data
is written
O: Used
X: Not used
● Reception interrupt
If one of the following events occurs in reception mode, the corresponding flag bit of the status
register is set to 1:
•
Data reception is complete (SSR0/1: RDRF)
•
Overrun error (SSR0/1: ORE)
•
Framing error (SSR0/1: FRE)
•
Parity error (SSR0/1: PE)
When at least one of the flag bits is 1 and the reception interrupts are enabled (SSR0/1: RIE =
1), a reception interrupt request is output to the interrupt controller.
When the input data register (SIDR0/1) is read, the receive data full flag (SSR0/1: RDRF) is
automatically cleared to 0. When 0 is written to the REC bit of the control register (SCR0/1), all
the reception error flags (SSR0/1: PE, ORE and FRE) are cleared to 0.
526
MB90820 series
● Transmission interrupt
When transmission data is transferred from the output data register (SODR0/1) to the transfer
shift register, the TDRE bit of the status register (SSR0/1) is set to 1. When the transmission
interrupts have been enabled (SSR0/1: TIE = 1), a transmission interrupt request is output to the
interrupt controller.
■ UART interrupts and EI²OS
Table 19.5-2 UART interrupts and EI²OS
Interrupt cause
Interrupt
number
Interrupt control register
Vector table address
EI²OS
Register name
Address
Lower
Upper
Bank
UART1
reception
interrupt
#37(25H)
ICR13
0000BDH
FFFF68H
FFFF69H
FFFF6AH
UART1
transmission
interrupt
#38(26H)
ICR13
0000BDH
FFFF64H
FFFF65H
FFFF66H
∆
UART0
reception
interrupt
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
UART0
transmission
interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
∆
:
Provided with a function that detects a UART reception error and stops EI²OS
∆: Usable when interrupt causes that share the ICR13 and ICR14 or the interrupt vectors are
not used
■ UART EI²OS functions
UART has a circuit for operating EI²OS, which can be started up for either reception or
transmission interrupts.
● For reception
EI²OS can be used regardless of the status of other resources.
● For transmission
UART shares the interrupt registers (ICR13 and ICR14) with the UART reception interrupts.
Therefore, EI²OS can be started up only when no UART reception interrupts are used.
MB90820 series
527
19.5
UART Interrupts
19.5.1 Reception Interrupt Generation and Flag Set Timing
The following are the reception interrupt causes: completion of reception (SSR0/1:
RDRF) and occurrence of a reception error (SSR0/1: PE, ORE, or FRE).
■ Reception interrupt generation and flag set timing
Receive data is stored in input data register 1 (SIDR0/1) if a stop bit is detected (in operation
mode 0 or 1) or the last bit of data is detected (in operation mode 2) during reception. If a
reception error is detected, the error flags (SSR0/1: PE, ORE and FRE) are set, then the receive
data flag (SSR0/1: RDRF) is set to 1. If one of the error flags is 1 in each mode, the SIDR0/1
register contains invalid data.
● Operation mode 0 (asynchronous, normal mode)
The RDRF bit is set to 1 when a stop bit is detected. If a reception error is detected, the error
flags (PE, ORE and FRE) are set.
● Operation mode 1 (asynchronous, multiprocessor mode)
The RDRF bit is set to 1 when a stop bit is detected. If a reception error is detected, the error
flags (ORE and FRE) are set. Parity errors cannot be detected.
● Operation mode 2 (synchronous, normal mode)
The RDRF bit is set when the last bit of receive data (D7) is detected. If a reception error is
detected, the error flag (ORE) is set. Parity and framing errors cannot be detected. Figure
19.5.1-1 below shows the reception operation and flag set timing.
Receive data
(operation mode 0)
ST
D0
D1
D5
D6
D7/P
SP
Receive data
(operation mode 1)
ST
D0
D1
D6
D7
A/D
SP
D0
D1
D4
D5
D6
D7
Receive data
(operation mode 2)
PE, ORE, FRE*
RDRF
A reception interrupt occurs.
*
: The PE flag cannot be used in mode 1
The PE and PRE flags cannot be used in mode 2
ST : Start bit
SP : Stop bit
A/D : Mode 2 (multiprocessor mode) address/data selection bit
Figure 19.5.1-1 Reception operation and flag set timing
● Reception interrupt generation timing
When the RDRF, PE, ORE or FRE flag is set to 1 in the reception interrupt enable state (SSR0/
1: RIE = 1), reception interrupt requests (#37 and #39) are generated.
528
MB90820 series
19.5
UART Interrupts
19.5.2 Transmission Interrupt Generation and Flag Set Timing
A transmission interrupt is generated when the next piece of data is ready to be written
to the output data register (SODR0/1).
■ Transmission interrupt generation and flag set timing
The transmission data empty flag bit (SSR0/1: TDRE) is set to 1 when data written to the output
data register (SODR0/1) is transferred to the transmission shift register, and the next piece of
data is ready to be written. TDRE is cleared to 0 when transmission data is written to SODR0/1.
Figure 19.5.2-1 shows the transmission operation and flag set timing.
[Operation modes 0 and 1]
SODR write
TDRE
An interrupt request is issued to the CPU.
SOT interrupt
SOT output
ST D0
D1 D2
D3
D4 D5
D6 D7
SP SP ST D0
A/D
D1 D2
D3
[Operation mode 2]
SODR write
TDRE
An interrupt request is issued to the CPU.
SOT interrupt
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
SOT output
ST: Start bit
D0 ~ D7: Data bits
SP: Stop bit
A/D: Address/data multiplexer
Figure 19.5.2-1 Transmission operation and flag set timing
● Transmission interrupt request generation timing
If the TDRE flag is set to 1 when a transmission interrupt is enabled (SSR0/1: TIE = 1),
transmission interrupt requests (#38 and #40) are generated.
<Check>
A transmission completion interrupt is generated immediately after the transmission interrupts
are enabled (TIE = 1) because the TDRE bit is set to 1 as its initial value. TDRE is a readonly bit that can be cleared only by writing new data to the output data register (SODR0/1).
Carefully specify the transmission interrupt enable timing.
MB90820 series
529
19.6 UART Baud Rates
One of the following can be selected as the UART transmitting/receiving block, the
block diagram show as below.
■ UART baud rate selection
The baud rate selection circuit is designed as shown below. One of the following three types of
baud rates can be selected:
● Baud rates determined using the dedicated baud rate generator
UART has an internal dedicated baud rate generator. One of eight baud rates can be selected
using the mode control register (SMR0/1).
An asynchronous or synchronous baud rate is selected using the machine clock frequency by
setting the CS2 ~ CS0 bits of the mode control register (SMR0/1) .
● Baud rates determined using the internal timer
The internal clock supplied from 16-bit reload timer 0 is used as it is (synchronous) or by dividing
it by 16 (asynchronous) for the baud rate. Any baud rate can be set by setting the reload value.
● Baud rates determined using the external clock
The clock input from the UART clock pulse input pins (P43/SCK0 and P74/SCK1) is used as it is
(synchronous) or by dividing it by 16 (asynchronous) for the baud rate. Any baud rate can be set
externally.
530
MB90820 series
SMR0/1 : CS2 ~ 0
(Clock selection bits)
[Dedicated baud rate generator]
3
Clock selector
CDCR0/1 : MD, DIV2 ~ 0
(Prescaler enable and selection bits)
When the bits
are 000B ~ 101B
4
φ
Frequency divider
(synchronous)
Frequency divider
(asynchronous)
Selects the internal fixed
division ratios
Machine clock prescaler
[Internal timer]
TMCSR0/1 : CSL1, CSL0
2
When the bits
are 110B
Clock selector
φ
Down
counter
UF
1/1 (synchronous)
1/16 (asynchronous)
Baud rate
SCKI
φ/21
φ/23 φ/25
Prescaler
16-bit reload timer 0
When the bits
are 111B
[External clock]
P43/SCK0, P74/SCK1
Pin
1/1 (synchronous)
1/16 (asynchronous)
SMR0/1 : MD1
(Synchronous or asynchronous clock selection)
φ : Machine clock frequency
Figure 19.6-1 Baud rate selection circuit
MB90820 series
531
19.6
UART Baud Rates
19.6.1 Baud Rates Determined Using the Dedicated Baud Rate Generator
This section describes the baud rates that can be set when the clock from the
dedicated baud rate generator is selected as the UART transfer clock.
■ Baud rates determined using the dedicated baud rate generator
When the transfer clock is generated using the dedicated baud rate generator, the machine
clock is divided with the machine clock prescaler. The divided machine clock is then divided by
the transfer clock division ratio selected with the clock selector again.The machine clock division
ratios are common to the asynchronous and synchronous baud rates, but different values set
internally are selected as the transfer clock division ratio for the asynchronous and synchronous
baud rates.
The actual transfer rate can be calculated using the following formulas:
asynchronous baud rate = φ x (prescaler division ratio) x (asynchronous transfer clock
division ratio)
synchronous baud rate = φ x (prescaler division ratio) x (synchronous transfer clock division
ratio)
φ : Machine clock frequency
● Division ratios for the prescaler (common to asynchronous and synchronous baud rates)
Each machine clock division ratio is selected using the DIV2 ~ DIV0 bits of the CDCR register as
listed in Table 19.6.1-1.
Table 19.6.1-1 Selection of each division ratio for the machine clock prescaler
532
MD
DIV2
DIV1
DIV0
div
0
–
–
–
Setting not allowed
1
0
0
0
1
1
0
0
1
2
1
0
1
0
3
1
0
1
1
4
1
1
0
0
5
1
1
0
1
6
1
1
1
0
7
1
1
1
1
8
MB90820 series
● Synchronous transfer clock division ratios
A division ratio for synchronous baud rates is selected using the CS2 ~ CS0 bits of the mode
control register (SMR0/1) as listed in Table 19.6.1-2
Table 19.6.1-2 Selection of synchronous baud rate division ratios
CS2
CS1
CS0
CLK synchronization
Calculation formula
0
0
0
2 MHz
( φ ÷ div) / 1
0
0
1
1 MHz
( φ ÷ div) / 2
0
1
0
500 KHz
( φ ÷ div) / 4
0
1
1
250 KHz
( φ ÷ div) / 8
1
0
0
125 KHz
( φ ÷ div) / 16
1
0
1
62.5 KHz
( φ ÷ div) / 32
Note that the calculation is supposing that φ (machine cycle) = 16 MHz and div (machine clock
division ratio) = 8. The maximum baud rate is 1/8 machine clock.
● Asynchronous transfer clock division ratios
A division ratio for asynchronous baud rates is selected using the CS2 ~ CS0 bits of the mode
control register (SMR0/1) as listed in Table 19.6.1-3
Table 19.6.1-3 Selection of asynchronous baud rate division ratios
CS2
CS1
CS0
Asynchronus
(start-stop synchronization)
Calculation formula
0
0
0
76923 Hz
( φ ÷ div) / (8 x 13 x 2)
0
0
1
38461 Hz
( φ ÷ div) / (8 x 13 x 4)
0
1
0
19230 Hz
( φ ÷ div) / (8 x 13 x 8)
0
1
1
9615 Hz
( φ ÷ div) / (8 x 13 x 16)
1
0
0
500 KHz
( φ ÷ div) / (8 x 2 x 2)
1
0
1
250 KHz
( φ ÷ div) / (8 x 2 x 4)
Note that the calculation is supposing that φ (machine clock) = 16 MHz, div (machine clock
division ratio) = 1.
MB90820 series
533
● Internal timer
When CS2 ~ CS0 are set to 110B and the internal timer is selected, the formulas for calculating
baud rates (when using the reload timer) are as follows:
Asynchronous (start-stop synchronization): ( φ ÷ N) / (16 x 2 x (n + 1))
CLK synchronization: ( φ ÷ N) / (2 x (n + 1))
N: Division ratio for the prescaler of 16-bit re-load timer count clock
n: reload value of the 16-bit reload timer
<Check>
In mode 2 (CLK synchronization mode), SCK0/SCK1 is up to three clocks later than SCKI. A
logically attainable transfer rate is 1/3 of the system clock frequency. However, 1/4 of the
system clock frequency is recommended as taken from the actual specifications.
● External clock
When CS2 ~ CS0 are set to 111B and the external clock is selected, note the following:
If the external clock frequency is specified as f, the following baud rates are assumed:
Asynchronous (start-stop synchronization): f/16
CLK synchronization: f
Note that the maximum external clock frequency f is 2 MHz.
534
MB90820 series
Memo
MB90820 series
535
19.6
UART Baud Rates
19.6.2 Baud Rates Determined Using the Internal Timer (16-bit
Reload Timer 0)
This section describes the settings used when the internal clock supplied from 16-bit
reload timer 0 is selected as the UART transfer clock. It also shows the baud rate
calculation formulas.
■ Baud rates determined using the internal timer (16-bit reload timer 0)
Writing 110B to the CS2 ~ CS0 bits of the mode control register (SMR0/1) selects the baud rate
determined using the internal timer. Any baud rate can be set by specifying a prescaler division
ratio and reload value for 16-bit reload timer 0. Figure 19.6.2-1 shows the baud rate selection
circuit for the internal timer.
SMR0/1 : CS2 ~ 0 = “110B”
(Selects the internal timer)
Clock selector
16-bit reload timer output
(the frequency is specified with
a prescaler division ratio and
reload value)
1/1 (synchronous)
1/16 (asynchronous)
Baud rate
SCKI
SMR0/1 : MD1
(Synchronous or asynchronous clock selection)
Figure 19.6.2-1 Baud rate selection circuit for the internal timer (16-bit reload timer 0)
● Baud rate calculation formulas
φ bps
Asynchronous baud rate =
X (n + 1) x 2 x 16
φ bps
Synchronous baud rate =
X (n + 1) x 2
φ: Machine clock frequency
X: Division ratio for the prescaler of 16-bit reload timer 0 (21, 23, 25)
n: Reload value for 16-bit reload timer 0 (0 ~ 65535)
536
MB90820 series
● Examples of setting reload values (machine clock: 7.3728 MHz)
Table 19.6.2-1 Baud rates and reload values
Reload value
Baud rate
Clock asynchronous
(start-stop synchronization)
Clock synchronous
X=21(machine cycle
divided by 2)
X=23 (machine
cycle divided by 8)
X=21(machine cycle
divided by 2)
X=23 (machine
cycle divided by 8)
38400
2
–
47
11
19200
5
–
95
23
9600
11
2
191
47
4800
23
5
383
95
2400
47
11
767
191
1200
95
23
1535
383
600
191
47
9071
767
300
383
95
6143
1535
X: Division ratio for the prescaler of 16-bit reload timer 0
–: Setting not allowed
MB90820 series
537
19.6
UART Baud Rates
19.6.3 Baud Rates Determined Using the External Clock
This section describes the settings used when the external clock is selected as the
UART transfer clock. It also shows the baud rate calculation formulas.
■ Baud rates determined using the external clock
The following three settings are required to select the baud rate determined by using the
external clock:
•
Write 111B to the CS2 to CS0 bits of the mode control register (SMR0/1) to select the baud
rate determined by using the external clock input.
•
Set the P43/SCK0 and P74/SCK1 pins as input ports (DDR4: bit 3 = 0 and DDR7: bit 12 = 0).
•
Write 0 to the SCKE bit of the mode control register (SMR0/1) to set the pin as an external
clock input pin.
As shown in Figure 19.6.3-1 , a baud rate is selected using the external clock input from the
SCK1 pin. To change the baud rate, the external input clock cycle must be changed because
the internal division ratio is fixed.
SMR0/1 : CS2 ~ 0 = “111B”
(Selects the external clock)
Clock selector
P43/SCK0
P74/SCK1
1/1 (synchronous)
1/16 (asynchronous)
Pin
Baud rate
SCKI
SMR0/1 : MD1
(Synchronous or asynchronous clock selection)
Figure 19.6.3-1 Baud rate selection circuit for the external clock
● Baud rate calculation formulas
Asynchronous baud rate = f/16
Synchronous baud rate = f
f: External clock frequency (up to 2 MHz)
538
MB90820 series
Memo
MB90820 series
539
19.7 Operation of UART
UART operates in operation modes 0 and 2 for normal bidirectional serial
communication and in operation mode 1 for master-slave communication.
■ Operation of UART
● Operation modes
There are three UART operation modes: modes 0 to 2. As listed in Table 19.7-1, an operation
mode can be selected according to the inter-CPU connection method and data transfer mode.
Table 19.7-1 UART operation mode
Data length
Operation mode
When parity is
disabled
0
Normal mode
1
Multiprocessor
8+1*
2
Normal mode
8
When parity is
enabled
7 or 8 bits
1
Synchronization
mode
Stop bit length
Asynchronous
–
Asynchronous
–
Synchronous
1 or 2 bits *2
None
–: Setting not possible.
*1: "+1" indicates the address/data selection bit (A/D) for communication control.
*2: During reception, only one stop bit can be detected.
<Check>
Operation mode 1 of UART is used only from the master system during master-slave
connection.
● Inter-CPU connection method
One-to-one connection (normal mode) and master-slave connection (multiprocessor mode) can
be selected. For either connection method, the data length, whether to enable parity, and the
synchronization method must be common to all CPUs. Select an operation mode as follows:
•
In the one-to-one connection method, operation mode 0 or 2 must be used in the two CPUs.
Select operation mode 0 for asynchronous transfer mode and operation mode 2 for
synchronous transfer mode.
•
Select operation mode 1 for the master-slave connection method and use it from the master
system. Select "When parity is disabled" for this connection method.
● Synchronization method
Asynchronous mode (start-stop synchronization) or clock synchronous mode can be selected in
different operation modes.
● Signal mode
UART can treat data only in NRZ (Non-return to Zero) format.
540
MB90820 series
● Operation enable bit
UART controls both transmission and reception using the operation enable bit for TXE
(transmission) and that for RXE (reception). If each of the operations is disabled, stop it as
follows:
•
If reception operation is disabled during reception (data is input to the reception shift register),
finish frame reception and store the received data in the input data register (SIDRI). Then
stop the reception operation.
•
If the transmission operation is disabled during transmission (data is output from the
transmission shift register), wait until there is no data in the output data register (SODR0/1)
before stopping the transmission operation.
MB90820 series
541
19.7
Operation of UART
19.7.1 Operation in Asynchronous Mode (Operation Modes 0 and 1)
When UART is used in operation mode 0 (normal mode) or operation mode 1
(multiprocessor mode), the asynchronous transfer mode is selected.
■ Operation in asynchronous mode
● Transfer data format
Transfer data begins with the start bit (L level) and ends with the stop bit (H level). The data of
the specified data bit length is transferred in LSB first mode.
•
In operation mode 0, the length of data with no parity is fixed to 7 bits, and that of data with
parity is fixed to 8 bits.
•
In operation mode 1, the length of data is fixed to 8 bits with an address/data (A/D) selection
bit added instead of parity.
Figure 19.7.1-1 shows the data format in asynchronous mode.
[Operation mode 0]
ST
D0
D1
D2
D3
D4
D5
D6
*
D7/P
SP
[Operation mode 1]
ST
D0
D1
D2
D3
D4
D5
D6
D7
A/D
SP
* : D7 (bit 7) when parity is not provided
P (parity) when parity is provided
ST : Start bit
SP : Stop bit
A/D : Address/data selection bit in operation mode 1 (multiprocessor mode)
Figure 19.7.1-1 Transfer data format (operation modes 0 and 1)
● Transmission operation
Transmission data is written to the output data register (SODR0/1) when the transmission data
empty flag bit (SSR0/1: TDRE) is 1. This data is transmitted if the transmission operation is
enabled (SCR0/1: TXE = 1).
The TDRE flag is again set to 1 when the transmission data is transferred to the transmission
shift register and its transmission starts. Then, the next piece of transmission data gets ready to
be set. At this point, a transmission interrupt request is output requesting that the next piece of
transmission data be set in the SODR0/1 register if that request is enabled (SSR0/1: TIE = 1).
The TDRE flag is cleared to 0 when the transmission data is written to SODR0/1.
● Reception operation
Reception operation is performed every time it is enabled (SCR0/1: RXE = 1). When a start bit is
detected, a frame of data is received according to the data format specified by the control
register (SCR0/1). After the frame has been received, the error flag is set if an error occurs, then
the receive data full flag bit (SSR0/1: RDRF) is set to 1. At this point, a reception interrupt
request is output if it is enabled (SSR0/1: TIE = 1).
Check each flag of the input data register (SIDR0/1). If the reception is normal, read the input
data register (SIDR0/1). If an error is found, proceed to error handling. The RDRF flag is cleared
to 0 every time receive data is read from SIDR0/1.
542
MB90820 series
● Stop bit
For transmission, 1 or 2 bits can be selected. During reception however, the first bit is the only
one that is always checked.
● Error detection
•
In mode 0, parity, overrun and framing errors can be detected.
•
In mode 1, overrun and framing errors can be detected but parity errors cannot be detected.
● Parity 0
Parity can only be used in operation mode 0 (asynchronous, normal mode). Whether to provide
parity can be specified using the PEN bit of the control register (SCR0/1). Even or odd parity
can also be specified using the P bit of the control register (SDR0/1). In operation mode 1
(asynchronous, multiprocessor mode) and operation mode 2 (synchronous, normal mode), parity
cannot be used. Figure 19.7.1-2 shows both transmission and receive data when parity is
enabled.
SIN0/1
ST
SP
A parity error occurs
during reception with even parity
(SCR0/1: P=0)
SP
Transmission with even parity
(SCR0/1: P=0)
1 0 1 1 0 0 0
SOT0/1
ST
1 0 1 1 0 0 1
SOT0/1
ST
SP
Transmission with odd parity
(SCR0/1: P=1)
1 0 1 1 0 0 0
Data
ST : Start bit
SP : Stop bit
Note : Parity is disabled in operation modes 1 and 2
Parity
Figure 19.7.1-2 Transmission data when parity is enabled
MB90820 series
543
19.7
Operation of UART
19.7.2 Operation in Synchronous Mode (Operation Mode 2)
The clock synchronous transfer method is used for UART operation mode 2 (normal
mode).
■ Operation in synchronous mode (operation mode 2)
● Transfer data format
In synchronous mode, 8-bit data is transferred using the LSB first method, in which start and
stop bits are not added. Figure 19.7.2-1 shows the data format in clock synchronous mode.
Transmission data writing
Mark level
Transmitting and reception
clock
RXE, TXE
Transmission and reception
data
1
0
1
1
0
0
LSB
1
0
MSB
(Mode 2)
01001101B is transferred.
Figure 19.7.2-1 Transfer data format (operation mode 2)
● Clock supply
In clock synchronous mode (I/O extended serial), as many clocks as the number of transmission
and reception bits must be supplied.
•
When the internal clock (dedicated baud rate generator or internal timer) is selected, the data
receiving synchronous clocks is generated automatically if data is transmitted.
•
When the external clock is selected, confirm that the transmission side UART output data
register (SODR0/1) contains data (SSR0/1: TDRE = 0). Then, clocks for just 1 byte must be
supplied from outside.
The mark level (H) must be retained before transmission starts and after it is complete.
● Error detection
Only overrun errors can be detected; parity and framing errors cannot be detected.
● Initialization
The following shows the set values of each control register using the synchronous mode:
[Mode control register (SMR0/1)]
MD1,MD0:"10B"
CS2,CS1,CS0:Specify clock input using the clock selector.
SCKE:1 for dedicated baud rate generator or internal timer
0 for clock output and external clock (clock input)
544
MB90820 series
SOE:1 for transmission; 0 for reception only
[Control register (SCR0/1)]
PEN:"0"
P,SBL,A/D:These bits make no sense.
CL:1 (8-bit data)
REC:0 (the error flag is cleared for initialization.)
RXE,TXE:At least one of the two bits is set to 1.
[Status register (SSR0/1)]
RIE:1 when using interrupts; 0 when using no interrupts.
TIE:1 when using interrupts; 0 when using no interrupts.
● Starting communication
Write data to the output data register (SODR0/1) to start communication. Temporary data must
be written to SODR0/1 to start communication for reception.
● Ending communication
The RDRF flag of the status register (SSR0/1) is set to 1 when transmission or reception of a
data frame is complete. During reception, check the overrun error flag bit (SSR0/1) to see if
communication is performing normally.
MB90820 series
545
19.7
Operation of UART
19.7.3 Bidirectional Communication Function (Normal Mode)
In operation mode 0 or 2, normal serial bidirectional communication (one-to-one
connection) is available. Select operation mode 0 for asynchronous communication
and operation mode 2 for synchronous communication.
■ Bidirectional communication function
The settings shown in Figure 19.7.3-1 are required to operate UART in normal mode (operation
mode 0 or 2).
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1 CS0 RST SCKE SOE
×
×
0
0 0
×
0 × ×
1 ×
0
1 0
SCR0/1, SMR0/1
Mode 0
Mode 2
SSR0/1,
SIDR0/1 / SODR0/1 PE ORE FRE RDRF TDRE BDS RIE TIE
Mode 0
Mode 2
×
Set conversion data (during writing).
Retain receive data (during reading).
×
DDR4 (UART0)
DDR6 (UART1)
: Bit used
x : Bit not used
1 : Set 1
0 : Set 0
: Set 0 to use an input pin
Figure 19.7.3-1 Settings for UART operation mode 0
● Inter-CPU connection
As shown in Figure 19.7.3-2 , interconnect two CPU’s.
SOT
SOT
SIN
SCK
CPU-1
Ouput
Input
SIN
SCK
CPU-2
Figure 19.7.3-2 Connection example of UART bidirectional communication
546
MB90820 series
● Communication procedure
Communication starts from the transmitting system at an optional timing when transmission data
has been prepared. An ANS is returned periodically (byte by byte in this example) when the
receiving system receives transmission data. Figure 19.7.3-3 shows an example of a
bidirectional communication flowchart.
(Transmitting system)
(Receiving system)
Start
Start
Set operation mode
(0 or 2)
Set operation mode(same mode
as that for the transmitting side)
Set 1-byte data in UODR
and perform communication
Data transmission
Any received data?
NO
YES
Any received data?
NO
Read and process received data.
YES
Data transmission
Read and process received data.
(ANS)
Transmit 1-byte data
Figure 19.7.3-3 Example of bidirectional communication flowchart
MB90820 series
547
19.7
Operation of UART
19.7.4 Master-slave Communication Function (Multiprocessor Mode)
With UART, communication with multiple CPUs connected in master-slave mode is
available in operation mode 1. However, UART can be used only from the master
system.
■ Master-slave communication function
The settings shown in Figure 19.7.4-1 are required to operate UART in multiprocessor mode
(operation mode 1).
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1 CS0 RST SCKE SOE
SCR0/1, SMR0/1
-
0
×
1
0
0
×
1
0
transmission data (during writing).
SSR0/1,
PE ORE FRE RDRF TDRE BDS RIE TIE Set
Retain receive data (during reading).
SIDR0/1 / SODR0/1
×
DDR4 (UART0)
DDR6 (UART1)
: Bit used
x : Bit not used
1 : Set 1
0 : Set 0
: Set 0 to use an input pin
Figure 19.7.4-1 Settings for UART operation mode 1
● Inter-CPU connection
As shown in Figure 19.7.4-2 , a communication system consists of one master CPU and
multiple slave CPUs connected to two communication lines. UART can be used only from the
master CPU.
SOT0/1
SIN0/1
Master CPU
SOT
SIN
Slave CPU #0
SOT
SIN
Slave CPU #1
Figure 19.7.4-2 Connection example of UART master-slave communication
548
MB90820 series
● Function selection
Select the operation mode and data transfer mode for master-slave communication as shown in
Table .
Table 19.7.4-1 Selection of the master-slave communication function
Operation mode
Data
Master CPU
Synchronization
method
Stop bit
None
Asynchronous
1 or 2 bits
Slave CPU
Address
transmission
and reception
Data
transmission
and reception
Parity
A/D = "1"
+
8-bit address
Mode 1
–
A/D = "0"
+
8-bit data
● Communication procedure
When the master CPU transmits address data, communication starts. The A/D bit in the address
data is set to 1, and the communication destination slave CPU is selected. Each slave CPU
checks the address data using a program. When the address data indicates the address
assigned to a slave CPU, the slave CPU communicates with the master CPU (ordinary data).
Figure 19.7.4-3 shows a flowchart of master-slave communication (multiprocessor mode).
MB90820 series
549
(Master CPU)
Start
Select transfer mode 1
Set the data for selecting the slave
CPUs in D0 to D7 and set “1” in A/D
to transfer one byte
Set “0” in A/D
Reception is enabled
Communication with the slave CPU
No
End communication?
Yes
Communicate with
other slave CPU?
No
Yes
Reception is disabled
End
Figure 19.7.4-3 Master-slave communication flowchart
550
MB90820 series
Memo
MB90820 series
551
19.8 Usage Notes on UART
Notes on using UART are given below.
■ Notes on using UART
● Enabling operations
In UART, the control register (SCR0/1) has both TXE (transmission) and RXE (reception)
operation enable bits. Both transmission and reception operations must be enabled before the
transfer starts because they have been disabled as the default value (initial value). The transfer
can also be canceled by disabling its operation as required.
● Communication mode setting
Set the communication mode while the system is not operating. If the mode is set during
transmission or reception, the transmission or reception data is not guaranteed.
● Synchronous mode
UART clock synchronous mode (operation mode 2) uses clock control (I/O extended serial)
mode, in which start and stop bits are not added to the data.
● Transmission interrupt enabling timing
The default (initial value) of the transmission data empty flag bit (SSR0/1: TRE) is 1 (no
transmission data and transmission data write enable state). A transmission interrupt request is
generated as soon as the transmission interrupt requests are enabled (SSR0/1: TIE = 1). Be
sure to set the TIE flag to 1 after setting the transmission data.
552
MB90820 series
Memo
MB90820 series
553
19.9 Sample Program for UART
This section contains a sample program for UART.
■ Sample program for UART
● Processing specifications
The UART1 bidirectional communication function (normal mode) is used to perform serial
transmission and reception.
•
Operation mode 0, asynchronous mode, eight data bits, two stop bits and no parity are set.
•
The P72/SIN1 and P73/SOT1 pins are used for communication.
•
The dedicated baud rate generator is used and the baud rate is set to about 9600 bps.
•
Character 13H is transmitted from the SOT1 pin and is received using an interrupt.
•
The machine clock (φ) is assumed to be 16 MHz.
● Coding example
ICR13
EQU
0000BDH
;UART1 transmission and reception interrupt control register
DDR7
EQU
000017H
;Port-7 data direction register
CDCR1 EQU
000037H
;Communication prescaler register 1
SMR1
EQU
000024H
;Mode control register 1
SCR1
EQU
000025H
;Control register 1
SIDR1
EQU
000026H
;Input data register 1
SODR1 EQU
000026H
;Output data register 1
SSR1
EQU
000027H
;Status register 1
REC
EQU
SCR1:2
;Reception error flag clear bit
;-------Main program-----------------------------------------------------------------------------------------------CODE
CSEG ABS = 0FFH
START:
;
:
;Assumes that stack pointer (SP) has already been
AND
CCR,#0BFH
; initialized
;Disables interrupts
MOV
I:ICR13,#00H
;Interrupt level 0 (highest)
MOV
I:DDR7,#00000000B ;Sets SIN1 pin as input pin
MOV
I:CDCR1,#080H
MOV
I:SMR1,#00010001B ;Operation mode 0 (asynchronous)
;Enables communication prescaler
;Uses dedicated baud rate generator (9615 bps)
;Disables clock pulse output and enables data output
MOV
I:SCR1,#00010011B ;No parity and two stop bits
;Clears eight data bits and reception error flag
554
MB90820 series
;Enables transmission and reception operations
MOV
I:SSR1,#00000010B ; Disables transmission interrupts and enables reception
; interrupts
MOV
I:SODR1,#13H
;Writes transmission data
MOV
ILM,#07H
;Sets ILM in PS to level 7
OR
CCR,#40H
;Enables interrupts
LOOP: MOV
A,#00H
;Endless loop
MOV
A,#01H
BRA
LOOP
;-------Interrupt program------------------------------------------------------------------------------------------WARI:
MOV
A,SIDR1
CLRB I:REC
;
:
;
User processing
;
:
RETI
CODE
;Reads receive data
;Clears reception interrupt request flag
;Returns from the interrupt
ENDS
;-------Vector setting-----------------------------------------------------------------------------------------------VECT
VECT
MB90820 series
CSEG ABS=0FFH
ORG
0FF68H
DSL
WARI
ORG
0FFDCH
DSL
START
DB
00H
;Sets vector for interrupt #37 (25H)
;Sets reset vector
;Sets single-chip mode
ENDS
555
556
MB90820 series
CHAPTER 20
ROM CORRECTION FUNCTION
This chapter describes the functions and operation of the ROM correction function.
20.1 Overview of the ROM Correction Function
20.2 Block Diagram of ROM Correction Function
20.3 ROM Correction Function Registers
20.4 Operation of the ROM Correction Function
20.5 Example of Using ROM Correction Function
MB90820 series
557
20.1 Overview of the ROM Correction Function
An instruction code to be read by the CPU is replaced forcibly with an INT9 instruction
code (01H) when the corresponding address is equal to the value set in a program
address detect register. A program patch application function can be implemented by
processing with the INT #9 interrupt routine.
■ Program address detection registers (x 2)
There are two program address detection registers (PADR0/1), each is provided with an interrupt
enable bit and interrupt flag.
■ ROM correction interrupts
When the interrupt enable bit is “1”, the value set in the program address detection register is
compared with the address. If the value matches the addresss, “1” is set in the interrupt flag bit
and the instruction code to be read to the CPU, is forcibly replaced with an INT9 instruction
code.
The interrupt flag bit is cleared to “0” by writing “0” to it using an instruction.
558
MB90820 series
20.2 Block Diagram of ROM Correction Function
The block diagram of ROM correction function is shown as below.
■ Block diagram of ROM correction function
Address latch
Comparator
INT9
command
F2MC-16LX bus
Address detection register 0/1
F2MC-16LX
AD0E/AD1E AD0D/AD1D
PACSR
CPU
Figure 20.2-1 Block diagram of ROM correction function
MB90820 series
559
20.3
ROM Correction Function Registers
20.3 ROM Correction Function Registers
The section lists the ROM correction function registers.
■ ROM correction function registers
Program Address Detection Register 0/1
Upper byte
Middle byte
Lower byte
Address : 1FF2 H/1FF1H/1FF0H
PADRH0
PADRM0
PADRL0
PADR0
Address : 1FF5 H/1FF4H/1FF3H
PADRH1
PADRM1
PADRL1
PADR1
Read/write
Initial value
(R/W)
(XXXXXXXXB)
(R/W)
(XXXXXXXX B)
(R/W)
(XXXXXXXXB)
Program Address Detection Control Status Register
Address : 00009E H
Read/write
Initial value
7
6
5
4
3
2
1
0
—
—
—
—
AD1E
AD1D
AD0E
AD0D
(-)
(X)
(-)
(X)
(-)
(X)
(-)
(X)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Bit number
PACSR
Figure 20.3-1 Registers of ROM Correction Function
560
MB90820 series
20.3
ROM Correction Function Registers
20.3.1 Program address detection register (PADR0/PADR1)
The program address detection register (PADR0/1) is a 24-bit register and used to store
the address to be compared with internal address bus.
■ Program address detection register 0/1 (PADR0/PADR1)
Program Address Detection Register 0/1
Upper byte
Middle byte
Lower byte
Address : 1FF2H/1FF1H/1FF0H
PADRH0
PADRM0
PADRL0
PADR0
Address : 1FF5H/1FF4H/1FF3H
PADRH1
PADRM1
PADRL1
PADR1
Read/write
Initial value
(R/W)
(XXXXXXXXB)
Figure 20.3.1-1
(R/W)
(XXXXXXXX B)
(R/W)
(XXXXXXXXB)
Program address detection register
The value written to this register is compared with a target address. If the value matches the
address, and the corresponding interrupt enable bit of the PACSR register is “1”, the
corresponding interrupt bit is set to “1” to request the CPU to generate an INT9 instruction. If the
corresponding interrupt enable bit is “0”, no operation is performed.
Table 20.3.1-1lists the correspondence between the program address detection register and
PACSR.
Table 20.3.1-1 Correspondence between program address detection register and PACSR
MB90820 series
Program address detection register
Interrupt enable bit
Interrupt bit
PADR0
AD0E
AD0D
PADR1
AD1E
AD1D
561
20.3
ROM Correction Function Registers
20.3.2 Program address detection control status register (PACSR)
The program address detection control status register (PACSR) is an 8-bit register and
used to control the operation of ROM correction function.
■ Program address detection control status register (PACSR)
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
00009EH
—
—
—
—
AD1E
AD1D
AD0E
AD0D
XXXX0000B
—
—
—
—
R/W
R/W
R/W
R/W
Address detection flag 0 bit
AD0D
Read
Write
0
No address compare match
Clear this bit
1
Address compare match
No effect
AD0E
Address detection register 0 enable bit
0
Disable interrupt request
1
Enable interrupt request
Address detection flag 1 bit
AD1D
Read
Write
0
No address compare match
Clear this bit
1
Address compare match
No effect
Address detection register 1 enable bit
AD1E
X
: Indeterminate
Read
Write
0
No address compare match
Clear this bit
1
Address compare match
No effect
R/W : Readable and writable
: Initial value
—
: Not used
Figure 20.3.2-1
562
Program address detection control status register
MB90820 series
Table 20.3.2-1 Program address detection control status register
Bit name
MB90820 series
Function
bit7
bit6
bit5
bit4
Reserved bits
bit3
AD1E:
• ADR1 operation enable bit.
Address detection • When this bit is “1”, the value set in the PADR1 register is
register 1 enable
compared with the address. If the two values are equal, an
bit
INT9 instruction is generated and the AD1D bit is set to “1”.
bit2
• ADR1 address match detection bit.
AD1D:
• This bit is set to “1” to indicate that the value set in the PADR1
Address detection
register matches the address. It is cleared to “0” by writing “0”
flag 1 bit
to it. It is left unchanged by writing “1” to it.
bit1
AD0E:
• ADR0 operation enable bit.
Address detection • When this bit is “1”, the value set in the PADR0 register is
register 0 enable
compared to the address. If the two values are equal, an INT9
bit
instruction is generated and the AD0D bit is set to “1”.
bit0
• ADR0 address match detection bit.
AD0D:
• This bit is set to “1” to indicate that the value set in the PADR0
Address detection
register is equal to the address. It is cleared to “0” by writing “0”
flag 0 bit
to it. It is left unchanged by writing “1” to it.
• Always write “0” to these bits.
563
20.4 Operation of the ROM Correction Function
If the program counter specifies the same address as that in program address
detection register (PADR), the INT9 instruction is executed. The ROM correction
function can be done by processing the INT9 instruction routine.
An instruction code to be read by the CPU is replaced forcibly with an INT9 instruction code
(01H) when the corresponding address is equal to the value set in an address detection register.
Therefore, the CPU executes the INT9 instruction when executing the set instruction.
A program patch application function can be implemented by processing with the INT #9
interrupt routine.
There are two address detection registers, of which each is provided with an interrupt enable bit
and interrupt flag. When the address is equal to the value set in the address detection register,
and the interrupt enable bit is “1”, assume the following: the interrupt flag is set to “1”, and the
instruction code to be read by the CPU is replaced forcibly with the INT9 instruction code. The
interrupt flag is cleared to “0” by writing “0” to it using an instruction.
Note:
The address match detection function fails if an address later than the first byte of the instruction
is set in the address detection register. The value in the set address is replaced with “01H”so a
wrong instruction is executed or an invalid address is accessed. Before changing the value set
in the address detection register, set the interrupt enable bit to “0”. If data is written while the
interrupt enable bit is “1”, the address may be wrongly detected during writing, causing a
malfunction.
564
MB90820 series
20.5 Example of Using ROM Correction Function
This section contains example of Using the Address Match Detection Function.
■ System configuration
E2PROM
MCU
F2MC-16LX
Pull-up resistor
Connector (UART)
SIN
Figure 20.5-1 System configuration example
■ E2PROM memory map
Table 20.5-1 E2PROM memory map
Address
Meaning
0000H
Number of bytes of patch program No. 0
(0 for no program error)
0001H
Bit 7 to bit 0 of program address No. 0
0002H
Bit 15 to bit 8 of program address No. 0
0003H
Bit 24 to bit 26 of program address No. 0
0004H
Number of bytes of patch program No. 1
(0 for no program error)
0005H
Bit 7 to bit 0 of program address No. 1
0006H
Bit 15 to bit 8 of program address No. 1
0007H
Bit 24 to bit 16 of program address No. 1
~ 0010H+
Number of bytes of patch program No. 0
Original of patch program No. 0
■ Initial state
The contents of E2PROM are all 0’s.
■ If a program error occurs
The original of a patch program and its address is transferred to the MCU via the connector
(UART). The MCU writes the information to E2PROM.
MB90820 series
565
■ Reset sequence
After the reset sequence is completed, the MCU reads the value of E2PROM. If the number of
bytes of the patch program is not 0, the MCU reads the original patch program and writes it to
RAM. Then, the MCU sets the program address to PADR0 or PADR1 and enables the program
to run. The first address of the program written to RAM is saved in RAM as specified for each
address detection register.
■ INT9 interrupt
During execution of an interrupt routine, control checks the interrupt flag for an address in which
an interrupt was enabled, and branches to the corresponding program. The information stacked
by the interrupt is deleted. The interrupt flag is also cleared.
MB90820 series
FFFFFFH
(3)
Adnormal program
(1)
PC = Trigger address
ROM
External E2PROM
O Number of program byte
Register setting
for ROM correction
O Interrupt trigger address
O Corrected program
Data sent via UART
RAM
Corrected program
(2)
000000H
Figure 20.5-2 System configuration example
566
MB90820 series
Reset
Read the 00H of E2PROM
INT9
Yes
2
0000H (E PROM) = 0
No
Clear interrupt program
Read the address
0001H ~ 0003H (E2PROM)
MOV
PADR0 (MCU)
To patch program
JMP 000400H
Read the patch program
0010 H ~ 0090H (E2PROM)
MOV
Patch program execution
000400H ~ 000480H
000400H ~ 000480H (MCU)
Enable compare
End of patch program
MOV PACSR, #02H
JMP FF0050H
Normal program execution
MB90820
FFFFFFH
PC = PADR0
No
Yes
FF0050H
2
E PROM
ROM
Abnormal program
FFFFH
FF0000H
0090H
FE0000H
INT9
Patch program
0010H
001100H
Stack area
Lower program address: 00
RAM area
0003H
Middle program address: 00
0002H
Upper program address: 00
0001H
0000H
Size of patch
program in byte: 80
000480H
RAM
Patch program
000400H
RAM / Register area
000100H
I/O area
000000H
Figure 20.5-3 Flowchart of program patch processing
MB90820 series
567
568
MB90820 series
CHAPTER 21
ROM MIRRORING FUNCTION SELECTION
MODULE
This chapter explains the function and operation of the MB90820 series ROM mirroring
function selection module.
21.1 Overview of the ROM Mirroring Function Selection Module
21.2 ROM Mirroring Function Selection Register (ROMM)
MB90820 series
569
21.1 Overview of the ROM Mirroring Function Selection Module
The ROM mirroring function selection module can access bank FF located in ROM from
bank 00 by setting the register.
■ ROM mirroring function selection module register
ROM Mirror Function Selection Register
Address : 00006FH
Read/write
Initial value
15
14
13
12
11
10
9
8
Bit number
—
—
—
—
—
—
—
MI
ROMM
(–)
(X)
(–)
(X)
(–)
(X)
(–)
(X)
(–)
(X)
(–)
(X)
(–)
(X)
(W)
(1)
■ ROM mirroring function selection module block diagram
F2MC-16LX bus
ROM mirroring register
Address area
FF bank
00 bank
ROM
Figure 21.1-1 ROM mirroring function selection module block diagram
570
MB90820 series
21.2 ROM Mirroring Function Selection Register (ROMM)
The ROM mirroring function selection register (ROMM) is used to enable mirroring
function.
■ ROM mirroring function selection register (ROMM)
Address
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Initial value
—
—
—
—
—
—
—
MI
XXXXXXX1B
—
—
—
—
—
—
—
W
00006FH
MI
X
: Indeterminate
R/W : Readable and writable
Mirroring enable bit
0
Disable mirroring function
1
Enable mirroring function
: Initial value
—
: Not used
Figure 21.2-1 ROM mirroring function selection register
Table 21.2-1 ROM mirroring function selection register
Bit name
MB90820 series
Function
bit15
bit14
bit13
bit12
bit11
bit10
bit9
Unused bits
• The read value is indeterminate.
• Always write 0 to these bits.
bit8
MI:
Mirroring enable
bit
• When 1 has been written to this bit, the ROM data in bank FF
can be read from bank 00.
• When 0 has been written to this bit, the function is disabled in
bank 00. This bit is write only.
571
<Check>
Bank 00 accesses FF8000H ~ FFFFFFH from 008000H ~ 00FFFFH. Therefore, FFF000H ~
FF7FFFH cannot be accessed even by selecting the ROM mirroring function.
MB90822
MB90F822
MB90F823
MB90V820
Address 1
FF0000H
FF0000H
FE0000H
FE0000H
Address 2
001100H
001100H
001100H
004100H
Address
FFFFFF H
Address 1
ROM area
ROM area
010000H
ROM area
008000H
002000H
Address 2
RAM area
RAM area
IO area
IO area
000100H
0000F0H
000000H
When MI = 1
Internal
area
When MI = 0
Figure 21.2-2 Memory space
572
MB90820 series
CHAPTER 22 512K / 1024K BIT FLASH MEMORY
The following explains the functions and operations of the 512K / 1024K bit flash
memory.
Three methods of data writing/deleting to the flash memory are provided:
1. Parallel writer (MODEL1890A made by Minato Electronics)
2. Serial dedicated writer (AF-200 made by Yokogawa Digital Computer)
3. Write/delete operation by program execution
This chapter provides an explanation for the above item "3. Write/delete operation by
program execution."
22.1 Overview of the 512K / 1024K Bit Flash Memory
22.2 512K / 1024K Bit Flash Memory Sector Configuration
22.3 Flash Memory Control Status Register (FMCS)
22.4 Method of Starting the Automatic Algorithm in Flash Memory
22.5 Verifying Automatic Algorithm Execution Status
22.6 Detailed Explanation on the Flash Memory Write/Delete
22.7 Flash Security Feature
22.8 Programming Example of 512K Bit Flash Memory
MB90820 series
573
22.1 Overview of the 512K / 1024K Bit Flash Memory
The 512K bit flash memory is allocated in the FF bank on the CPU memory map while
1024K bit flash memory is allocated in FE and FF bank. The function of the flash
memory interface circuit enables the read/access or program access from the CPU to
the flash memory, same as the mask ROM. The write/delete operation to the flash
memory can be executed through the flash memory interface circuit by executing an
instruction issued from the CPU. Therefore, the flash memory mounted can be
rewritten under the control of the internal CPU, so that the program or data can be
upgraded or updated more efficiently. However, no selector operation such as the
enable sector protect can be used.
■ Characteristics of the 512K / 1024K Bit Flash Memory
•
512K Bit: 64K words x 8 bits/32K words x 16 bits (16K+8K+8K+32K) sector configuration
•
1024K Bit: 128K words x 8 bits/64K words x 16 bits (64K+16K+8K+8K+32K) sector
configuration
•
Automatic program algorithm (same as the Embedded Algorithm : MBM29F400TA)
•
Installation of the deletion temporary stop/delete restart function
•
Write/delete completion detected by the data polling or toggle bit
•
Write/delete completion detected by the CPU interrupt
•
Compatibility with the JEDEC standard-type command
•
Each sector deletion can be executed (Sectors can be freely combined)
•
Number of write/delete operations 10,000 times guaranteed
•
Flash security feature
"Embedded Algorithm" is the trademark of Advanced Micro Device
■ Procedure for Writing/Deleting the data to the Flash Memory
The write/delete operation of the flash memory cannot be executed simultaneously. In executing
the data write/delete operation in the flash memory, only the write operation can be executed
without a program access from the flash memory, by copying a program on the flash memory to
RAM and executing the program.
■ Register on the Flash Memory
•
Flash memory control status register (FMCS)
7
Bit No.
Address:0000AEH
Read/Write
Initial value
574
INTE
(R/W)
(0)
6
5
4
3
2
RDYINT
WE
RDY
Reserved
Reserved
(R/W)
(0)
(R/W)
(0)
(R)
(1)
(0)
(0)
1
Reserved
(0)
0
Reserved
(0)
MB90820 series
22.2 512K / 1024K Bit Flash Memory Sector Configuration
Figure 22.2-1 and figure 22.2-2 and shows the sector configuration in the 512K bit flash
memory. The address indicated in figure 22.2-1 and figure 22.2-2 is classified into the
upper address and lower address of each sector.
■ Sector Configuration
When accessing the 512Kbit flash memory from the CPU, four sector addresses, SA0 to SA3,
are allocated in the FF bank register.
Flash memory
SA3 (16 Kbytes)
SA2 (8 Kbytes)
SA1 (8 Kbytes)
SA0 (32 Kbytes)
CPU address
*Writer address
FFFFFFH
7FFFFH
FFC000H
FFBFFFH
7C000H
7BFFFH
FFA000H
7A000H
FF9FFFH
79FFFH
FF8000H
FF7FFFH
78000H
77FFFH
FF0000H
70000H
Figure 22.2-1 512K Bit Flash Memory Sector Configuration
When accessing the 1024Kbit flash memory from the CPU, five sector addresses, SA0 to SA4,
are allocated in the FE and FF bank register.
Flash memory
SA4 (16 Kbytes)
SA3 (8 Kbytes)
SA2 (8 Kbytes)
SA1 (32 Kbytes)
CPU address
FFFFFFH
7FFFFH
FFC000H
FFBFFFH
7C000H
7BFFFH
FFA000H
7A000H
FF9FFFH
79FFFH
FF8000H
78000H
77FFFH
FF7FFFH
FF0000H
SA0 (64 Kbytes)
*Writer address
FEFFFFH
70000H
6FFFFH
FE0000H
60000H
Figure 22.2-2 1024K Bit Flash Memory Sector Configuration
* Writer address
The writer address is equivalent to the CPU address when writing the data to the flash memory
using the parallel writer. If the write/delete operation is executed using the general-purpose
writer, the write/delete operation is executed using this address.
MB90820 series
575
22.3 Flash Memory Control Status Register (FMCS)
The FMCS, which exists in the flash memory interface circuit, is used when data is
written to or erased from flash memory.
■ Control Status Register (FMCS)
7
Bit No.
Address:0000AEH
Read/Write
Initial value
INTE
(R/W)
(0)
6
5
4
3
2
RDYINT
WE
RDY
Reserved
Reserved
(R/W)
(0)
(R/W)
(0)
(R)
(1)
(0)
(0)
1
Reserved
(0)
0
Reserved
(0)
● Contents of the bits
[Bit 7] INTE (Interrupt Enable)
This bit generates an interrupt to the CPU when the write/delete operation to the flash
memory is terminated.
When the INTE bit is "1" and the RDYINT bit is "1" an interrupt generated and sent to the
CPU. If the INTE bit is "0", no interrupt is generated:
0: Interrupt disabled when the write/delete operation is terminated.
1: Interrupt enabled when the write/delete operation is terminated.
[Bit 6] RDYINT (Ready Interrupt)
This bit indicates the flash memory operating status.
After the write/delete to the flash memory is terminated, this bit is set to "1". While this bit is
"0" after the end of write/delete operation to the flash memory, the flash memory cannot be
written or deleted. After the write/delete operation is terminated and this bit is set to "1", the
flash memory can be written or deleted. This bit is cleared to "0" by writing "0" and the writing
of "1" is ignored. At the termination time of the automatic algorithm in the flash memory (see
Section 22.4, "Method of Starting the Automatic Algorithm in Flash Memory"), this bit is set to
"1". While using the read modify write (RMW) instruction, "1" can be read at any time.
0: During the write/delete operation
1: Write/delete operation terminated (An interrupt request is generated)
[Bit 5] WE (Write Enable)
This bit is the write enable bit for the flash memory area.
When this bit is "1", the write instruction after issuing command sequence to FF bank (see
Section 22.4, "Method of Starting the Automatic Algorithm in Flash Memory") is equivalent to
writing to the flash memory area. When this bit is "0", no write/delete signal is generated.
This bit is used when the flash memory write/delete command is started.
0: Flash memory write/delete disabled
1: Flash memory write/delete enabled
576
MB90820 series
[Bit 4] RDY (Ready)
This bit is the flash memory write/delete permission bit.
While this bit is "0", the write/delete cannot be executed to the flash memory. Even in this
state, however, suspend commands such as the read/reset command and the sector deletion
temporary stop can be accepted.
0: During the write/delete operation
1: Write/delete operation terminated (Next data write/delete operation permitted)
[Bit 3~0] Reserved bits
These bits are the reserved bits. Always write "0" to these bits.
[Bit 2,0] LPM1, LPM0 (Low-power Mode)
[Check]
The RDYINT bit and RDY bit are not changed simultaneously. Create a program using one
of the RDYINT bit or RDY bit for determination.
Automatic algorithm
Termination time
RDYINT bit
RDY bit
1 machine cycle
MB90820 series
577
22.4 Method of Starting the Automatic Algorithm in Flash
Memory
There are four types of commands for starting the automatic algorithm in the flash
memory, i.e., the read/reset command, write command, and chip deletion command. In
addition, the sector deletion command can be temporarily stopped and restarted.
■ Command Sequence Table
Table 22.4-1 lists the commands to be used for writing/deleting the data to the flash memory. All
the data is written to the command register in units of bytes, though it should be accessed and
written in units of words.
In this case, the data in the upper bytes is ignored.
Table 22.4-1
Command
sequence
Bus
write
cycle
Command Sequence Table
1st bus write
cycle
2nd bus write
cycle
Address
Data
Address
3rd bus write
cycle
Address
Data
4th bus write
cycle
Address
Data
Data
5th bus write
cycle
6th bus write
cycle
Address
Address
Data
Data
Read/reset
1
FFXXXX
XXF0
-
-
-
-
-
-
-
-
-
-
Read/reset
4
FFAAAA
XXAA
FF5554
XX55
FFAAAA
XXF0
RA
RD
-
-
-
-
Write program
4
FFAAAA
XXAA
FF5554
XX55
FFAAAA
XXA0
PA
(even)
PD
(word)
-
-
-
-
Chip deletion
6
FFAAAA
XXAA
FF5554
XX55
FFAAAA
XX80
FFAAAA
XXAA
FF5554
XX55
FFAAAA
XX10
Sector deletion
6
FFAAAA
XXAA
FF5554
XX55
FFAAAA
XX80
FFAAAA
XXAA
FF5554
XX55
SA
(even)
XX30
Sector deletion temporary stop
Temporarily stops the sector deletion command when inputting Address "FFXXXX" Data(xxB0H).
Sector deletion restart
Restarts the sector deletion command when inputting Address "FFXXXX" Data(xx30H).
* : Two types of read/reset commands can reset the flash memory to the read mode.
[Check]
The addresses in the above table are the values on the CPU memory map. All the
addresses and data are represented in hexadecimal. However, "X" is an optional value.
RA : Read address
PA : Write address. Only the even address can be specified.
SA : Sector address. For details, see Section 22.2, "512K / 1024K Bit Flash Memory
Sector Configuration"
RD : Read data
PD : Write data. Only the word data can be specified
578
MB90820 series
Memo
MB90820 series
579
22.5 Verifying Automatic Algorithm Execution Status
The flash memory contains the hardware for posting the internal flash memory
operating status or the flash memory operation completion, because the automatic
algorithm executes the sequence of data writing/deleting procedures. This automatic
algorithm can verify the internal flash memory operating status, depending on the
following hardware sequence.
■ Hardware Sequence Flag
The hardware sequence flag consists of the four flag bits, DQ7, DQ6, DQ5, and DQ3. These
flag bits have the data polling flag (DQ7) function, toggle bit flag (DQ6) function, time limit
exceeded flag (DQ5) function, and sector deletion timer flag (DQ3) function, respectively. These
functions can verify whether the write/chip sector deletion is terminated or whether the deletion
code write is valid.
The hardware sequence flag can be referenced by accessing/reading the address of the target
sector in the flash memory, after setting the command sequence (see Section 22.4, "Method of
Starting the Automatic Algorithm in Flash Memory"). Table 22.5-1 indicates the hardware
sequence flag bit allocation.
Table 22.5-1
Bit no.
Hardware
sequence flag
Hardware Sequence Flag Bit Allocation
7
6
5
4
3
2
1
0
DQ7
DQ6
DQ5
-
DQ3
-
-
-
It can be determined whether automatic write/chip sector deletion is being performed, depending
on the end of write processing, by checking the hardware sequence flag or the RDY bit in the
flash memory control register (FMCS). After the write/delete operation is terminated, the flash
memory is returned to the read/reset status. To actually create a program, it should be verified
whether automatic write/delete operation is terminated, depending on any flag, and the next
operation such as the data reading should be executed. Also, it can be verified whether the
second sector deletion code write command or later commands are valid, depending on the
hardware sequence flag. The following explains the hardware sequence flags. Table 22.5-2
lists the hardware sequence flag functions.
580
MB90820 series
Table 22.5-2
Hardware Sequence Flag Function List
State
Status
transition
during
normal
operation
Abnormal
operation
MB90820 series
DQ7
DQ6
DQ5
DQ3
Write operation -->
Write completion (when
the write address is
specified)
DQ7 -->
DATA:7
Toggle -->
DATA:6
0 --> DATA:5
0 -->
DATA:3
Chip/sector deletion
operation --> Deletion
completion
0 --> 1
Toggle -->
Stop
0 --> 1
1
Sector deletion wait -->
Deletion start
0
Toggle
0
0 --> 1
Deletion processing -->
Sector deletion
temporary stop (sector
being deleted)
0 --> 1
Toggle --> 1
0
1 --> 0
Sector deletion
temporary stop -->
Deletion restart (sector
being deleted)
1 --> 0
1 --> Toggle
0
0 --> 1
While the sector
deletion is being
temporarily stopped -->
(sector not being
deleted)
DATA:7
DATA:6
DAATA:5
DATA:3
Write operation
DQ7
Toggle
1
0
Chip/sector deletion
operation
0
Toggle
1
1
581
22.5.1
Data Polling Flag (DQ7)
The data polling flag (DQ7) indicates whether the automatic algorithm is being
executed or has been terminated, using the data polling function. Table 22.5.1-1 shows
the data polling flag status transition.
■ When the Write Operation is Executed.
When the read/access is executed during automatic write algorithm execution, the flash memory
outputs the reverse data of bit 7 in the last-written data, irrespective of the specified address.
When the read/access is executed at the end of the automatic write algorithm, the flash memory
outputs the data of bit 7 in the specified read address. When the read/access is executed at the
end of the automatic write algorithm, the flash memory outputs the data of bit 7 in the specified
read address.
■ When the Chip/Sector Deletion Operation is Executed.
When the read/access is executed during the chip/sector deletion algorithm execution, the flash
memory outputs "0" from the sector being deleted by the sector deletion, or irrespective of the
specified address during the chip deletion. Similarly, the flash memory outputs "1" at the end of
chip/sector deletion algorithm.
■ When the Sector Deletion Temporary Stop is Executed.
When the access/read is executed while executing the sector deletion temporary stop, the flash
memory outputs "1" if the specified address is the sector being deleted. However, the flash
memory outputs the data of bit 7 (DATA:7) of the specified read address, if the specified address
is not the sector being deleted. By referencing this together with the toggle bit flag (DQ6), it can
be determined whether the current sector is in the temporary stop state or which sector is being
deleted.
[Check]
When the automatic algorithm is started, the read/access to the specified address is ignored. As
for the data reading, the end of data polling flag (DQ7) is posted, and then other data bit can be
output. Therefore, the data read operation after the end of the automatic algorithm should be
executed next to the read/access after verifying the end of data polling flag.
582
MB90820 series
Table 22.5.1-1 Data Polling Flag Station Transition
- Status transition during normal operation
Sector deletion
Sector deletion -->Deletion
Operating Write operation Chip/sector
wait-->Start
status
--> Completion deletion
temporary stop
-->Completion
(Sector being
deleted)
DQ7
DQ7-->DATA:7
0-->1
0
0-->1
Sector deletion
temporary stop
-->Restart
(Sector being
deleted)
1-->0
During the sector
deletion temporary
stop (Sector not
being deleted)
DATA:7
- Status transition during abnormal operation
Operating Write operation
status
DQ7
MB90820 series
DQ7
Chip/sector
deletion
operation
0
583
22.5.2
Toggle Bit Flag (DQ6)
The toggle bit flag specifies whether the automatic algorithm is being executed or has
been terminated, using the toggle bit function, the same as the data polling flag.
Table 22.5.2-1 shows the toggle bit flag status transition.
■ When the Write Operation or Chip/Sector Deletion Operation is Executed.
When the continuous read/access is executed during the automatic write algorithm or chip/sector
deletion algorithm execution, the flash memory outputs the toggle status, in which "1" and "0" are
alternately output for each read operation, irrespective of the specified address. If the
continuous read/access is executed at the end of the automatic write algorithm or chip/sector
deletion algorithm, the flash memory stops the toggle operation in bit 6 and outputs the data of
bit 6 (DATA:6) in the specified read address.
■ When the Sector Deletion Temporary Stop is Executed.
When the read/access is executed while executing the sector deletion temporary stop, the flash
memory outputs "1" if the specified address belongs to the sector being deleted. The flash
memory outputs the data of bit 6 (DATA:6) in the specified read address unless the specified
address belongs to the sector being deleted.
<Reference>
When executing the write operation, the toggle bit executes the toggle operation for about 2 µs,
then terminates it without rewriting the data, if the sector to be written is write-protected.
When executing the deletion operation, the toggle bit executes the toggle operation for about
100 µs, then returns to the read/reset status without rewriting the data, if all the selected sectors
are protected from rewriting.
Table 22.5.2-1 Toggle Bit Flag Status Transition
- Status transition during normal operation
Sector deletion
Sector deletion -->Deletion
Operating Write operation Chip/sector
wait-->Start
status
--> Completion deletion
temporary stop
-->Completion
(Sector being
deleted)
DQ6
Toggle
-->DATA:6
Toggle-->Stop
Toggle
Toggle-->1
Sector deletion
temporary stop
-->Restart
(Sector being
deleted)
1-->Toggle
During the sector
deletion temporary
stop (Sector not
being deleted)
DATA:6
- Status transition during abnormal operation
Operating
status
DQ6
584
Write operation
Toggle
Chip/sector
deletion
operation
Toggle
MB90820 series
22.5.3 Time limit Exceeded Flag (DQ5)
The time limit exceeded flag indicates that the automatic algorithm execution time has
exceeded the time defined within the flash memory (i.e., internal pulse count).
Table 22.5.3-1 shows the transition of the time limit exceeded flag status.
■ When the Write Operation or Chip/Sector Deletion Operation is Executed.
When the read/access is executed after starting the write or chip/sector deletion automatic
algorithm, this flag is set to "0" if the execution time is within the defined time (required for
writing/deletion), or it outputs "1" if this execution time exceeds the defined time. This is not
related to the state in which the automatic algorithm is being executed or has been terminated,
so it can be determined whether the write/delete has succeeded or failed. Thus, when this flag
is set to "1", it indicates that the write operation has failed if the automatic algorithm is being
performed by the data polling function or toggle bit function.
For example, a fail occurs if an attempt is made to write "1" to the flash memory with "0" written.
In this case, the flash memory is locked and the automatic algorithm is not terminated.
Therefore, no valid data is set in data polling flag (DQ7). The toggle bit flag (DQ6) does not stop
the toggle operation, so the execution time exceeds the time limit. Then, the time limit exceeded
flag (DQ5) outputs "1". This event indicates that the flash memory has not been correctly used,
but does not indicate that the flash memory is not good. If this event occurs, the reset command
should be executed.
Table 22.5.3-1 Transition of the Time Limit Exceeded Flag Status
- Status transition during normal operation
Sector deletion
Sector deletion -->Deletion
Operating Write operation Chip/sector
wait-->Start
status
--> Completion deletion
temporary stop
-->Completion
(Sector being
deleted)
DQ5
0-->DATA:5
0-->1
0
0
Sector deletion
temporary stop
-->Restart
(Sector being
deleted)
0
During the sector
deletion temporary
stop (Sector not
being deleted)
DATA:5
- Status transition during abnormal operation
Operating
status
DQ5
MB90820 series
Write operation
1
Chip/sector
deletion
operation
1
585
22.5.4 Sector Deletion Timer Flag (DQ3)
After starting the sector deletion command, the sector deletion timer flag indicates
whether it is "during the sector deletion waiting period". Table 22.5.4-1 shows the
sector deletion timer flag status transition.
■ When the Sector Deletion Operation is Executed.
When the read/access is executed after starting the sector deletion command, the flash memory
outputs "0" if this flag indicates "during the sector deletion waiting period" irrespective of the
address specified by the address signal from the sector having issued the command. However,
the flash memory outputs "1" if this flag exceeds the defined sector deletion waiting period.
When the deletion algorithm is being executed by the data polling function or toggle bit function,
the internally-controlled deletion operation is started if this flag is "1". The succeeding sector
deletion code to be written and other commands except the sector deletion temporary stop
command are ignored until deletion is terminated.
If this flag is "0", the flash memory accepts the additional sector deletion code to be written. To
verify this event, it is recommended that this flag status be checked before writing the
succeeding sector deletion code. If this flag is "1" when the second time the status is checked,
the additional sector deletion code may not be accepted.
■ When the Sector Deletion Operation is Executed.
When the read/access is executed while executing the sector deletion temporary stop, the flash
memory outputs "1" if the specified address belongs to the sector being deleted. However,
unless the specified address belongs to the sector being deleted, the flash memory outputs the
data of bit 3 (DATA:3) of the specified read address.
Table 22.5.4-1 Sector Deletion Timer Flag Status Transition
- Status transition during normal operation
Sector deletion
Sector deletion -->Deletion
Operating Write operation Chip/sector
wait-->Start
status
--> Completion deletion
temporary stop
-->Completion
(Sector being
deleted)
DQ3
0-->DATA:3
1
0-->1
1-->0
Sector deletion
temporary stop
-->Restart
(Sector being
deleted)
0-->1
During the sector
deletion temporary
stop (Sector not
being deleted)
DATA:3
- Status transition during abnormal operation
Operating
status
DQ3
586
Write operation
0
Chip/sector
deletion
operation
1
MB90820 series
22.6 Detailed Explanation on the Flash Memory Write/Delete
This section explains the procedures for issuing the command to start the automatic
algorithm, reading/resetting the flash memory, writing the data to the flash memory,
deleting the chip, deleting the sector, temporarily stopping the sector deletion, and
restarting the sector deletion.
■ Detailed Explanation on the Flash Memory Write/Delete
The read/reset, write, chip deletion, sector deletion, sector deletion temporary stop, or deletion
start operation can be performed by the automatic algorithm which can be started by setting the
command sequence (see Section 22.4, "Method of Starting the Automatic Algorithm in Flash
Memory") to each bus write cycle. The write cycles to the respective buses must be executed
continuously. The ending time of the automatic algorithm can be notified by the data polling
function and so on. After the normal end of the automatic algorithm, the flash memory returns to
the read/reset status.
22.6.1 Setting the Read/Reset Status
22.6.2 Writing the Data
22.6.3 Deleting the Data (Chip Deletion)
22.6.4 Deleting the Data (Sector Deletion)
22.6.5 Temporarily Stopping the Sector Deletion
22.6.6 Restarting the Sector Deletion
MB90820 series
587
22.6.1 Setting the Read/Reset Status
This section explains the procedure of issuing the read/reset command and setting the
flash memory to the read/reset status.
■ Setting the Read/Reset Status
When the flash memory is set to the read/reset status, the read/reset command can be executed
by continuously sending the read/reset command, listed in the command sequence table (see
Section 22.4, "Method of Starting the Automatic Algorithm in Flash Memory"), to the target sector
in the flash memory.
There are two types of read/reset command sequences, one is that the bus operation is
executed once and the other is that the bus operations are executed three times. However,
these command sequences have no essential difference.
The read/reset status is the initial status of the flash memory. When the power supply is turned
on, or when the command is normally terminated, the flash memory is always set to the read/
reset status. The read/reset status means the status of the flash memory that is waiting for
another command to be input.
In the read/reset status, data can be read from the flash memory by executing a usual read/
access command. The data can be program-accessed from CPU same as the mask ROM. This
command is not required for usual data reading. This command should be mainly used for
initializing the automatic algorithm if the command has not been normally terminated for any
reason.
588
MB90820 series
Memo
MB90820 series
589
22.6.2 Writing the Data
This section explains the procedure of issuing the write command and writing the data
to the flash memory. Figure 22.6.2-1 shows an example of procedure of writing data to
the flash memory.
■ Writing the Data
The automatic algorithm for writing the data to the flash memory can be performed by
continuously sending the write command, listed in the command sequence table (see
Section 22.4, "Method of Starting the Automatic Algorithm in Flash Memory"), to the target sector
in the flash memory. When the data write operation to the target address in the 4th cycle has
been terminated, the automatic algorithm is started for automatic writing.
■ How to Specify the Address
Only even addresses can be specified as the write address in the write data cycle. If an odd
address is specified, data cannot be correctly written. That is, it is necessary to write the data in
units of words to even addresses.
Data can be written to the flash memory, and any address sequence may be specified, even if
data has been written across the sector boundary. However, only one-word data can be written
by executing the write command once.
■ Notes on Writing the Data
By writing the data, data "0" cannot be returned to data "1". If data "1" is written to data "0", the
data polling algorithm (DQ7) or toggle operation (DQ6) is not terminated and the flash memory
element is determined to be bad. Then, the time limit exceeded flag (DQ5) error may be
determined by the excess of the write defined time, or data "1" may be apparently written but is
not actually done. However, if data is read from the flash memory in the read/reset status, data
remains "0". Only the deletion operation enables data "0" to be changed to data "1".
All commands are ignored while automatic writing is being performed. Note that the data at the
address for writing is not assured if the hardware is reset during automatic writing.
■ Procedure of Writing the Data to the Flash Memory
Figure 22.6.2-1 shows an example of procedure of writing the data to the flash memory. Using
the hardware sequence flag (see Section 22.5, "Verifying Automatic Algorithm Execution
Status"), the status of the automatic algorithm within the flash memory can be determined.
Here, the data polling flag (DQ7) is used for verifying the end of writing.
The data reading for checking the flag is started from the last-written address. The data polling
flag (DQ7) is changed at the same time when the time limit exceeded flag (DQ5) is changed, so
the data polling flag (DQ7) must be rechecked even if the time limit exceeded flag (DQ5) is "1".
Similarly, the toggle bit flag (DQ6) stops the toggle operation at the same time when the time
limit exceeded flag (DQ5) is changed to "1", so the toggle bit flag (DQ6) must be rechecked.
590
MB90820 series
Start the write
FMCS:WE (bit5)
Flash memory write
enabled
Write command sequence
1.FxAAAA
XXAA
2.Fx5554
XX55
3.FxAAAA
XXA0
4.Write address
Write data
Next address
Internal address read
Data
Data polling (DQ7)
Data
0
Time limit (DQ5)
1
Internal address read
Data
Data polling (DQ7)
Data
Write error
Last address
FMCS:WE(bit5)
Flash memory write disabled
Verification using
the hardware sequence flag
Write completion
Figure 22.6.2-1 Example of Procedure of Writing the Data to the Flash Memory
MB90820 series
591
22.6.3 Deleting the Data (Chip Deletion)
This section explains the procedure of issuing the chip deletion command and deleting
all the data in the flash memory.
■ Deleting the data (Chip deletion)
All the data can be deleted from the flash memory by continuously sending the chip deletion
command, listed in the command sequence table (see Section 22.4, "Method of Starting the
Automatic Algorithm in Flash Memory"), to the target sector in the flash memory.
The chip deletion command is executed by executing the bus operation six times. When the 6thcycle write operation has been completed, the chip deletion operation is started. The user need
not write the data to the flash memory before chip deletion operation. During the automatic
deletion algorithm execution, the flash memory writes data "0" to all the cells and verifies them
before they are automatically deleted.
592
MB90820 series
Memo
MB90820 series
593
22.6.4 Deleting the Data (Sector Deletion)
This section explains the procedure of issuing the sector deletion command and
deleting any sector from the flash memory. This command enables each sector to be
deleted, and two or more sectors to be specified at the same time.
■ Deleting the data (Sector deletion)
Any sector can be deleted from the flash memory by continuously sending the sector deletion
command, listed in the command sequence table (see Section 22.4, "Method of Starting the
Automatic Algorithm in Flash Memory"), to the target sector in the flash memory.
Method of Specifying a Sector
The sector deletion command is executed by executing the bus operation six times. The sector
deletion wait of 50 µs is started by writing the sector deletion code (30H) to any accessible even
address in the target sector in the 6th-cycle bus operation. To delete two or more sectors, the
deletion code (30H) should be written to the address in the target sector just after the above
operation.
■ Notes on Specifying Two or More Sectors
The deletion operation is started after the last sector deletion code is written and the sector
deletion wait period of 50 µs is terminated. Thus, the next deletion sector address and deletion
code (i.e. in the 6th cycle of the command sequence) must be input each within 50 µs to delete
two or more sectors simultaneously, which may not be accepted later than 50 µs. It can be
checked whether the succeeding sector deletion code write operation is valid, using the sector
deletion timer flag (DQ3). In this case, the address from which the sector deletion timer flag
(DQ3) is read must indicate the sector to be deleted.
■ Procedure of Deleting a Sector
Using the hardware sequence flag (see Section 22.5 "Verifying Automatic Algorithm Execution
Status"), the status of the automatic algorithm within the flash memory can be determined.
Figure 22.6.4-1 shows an example of procedure of deleting the sector from the flash memory.
Here, the toggle bit flag (DQ6) is used for verifying the end of writing. Note that data to be used
for checking the flag is read from the sector to be deleted.
The toggle bit flag (DQ6) stops the toggle operation at the same time when the time limit
exceeded flag (DQ5) is changed to "1", so the toggle bit flag (DQ6) must be rechecked even if
the time limit exceeded flag (DQ5) is "1".
Similarly, the data polling flag (DQ7) is changed at the same time when the time limit exceeded
flag (DQ5) is changed, so the data polling flag (DQ7) must be rechecked.
594
MB90820 series
Start the deletion.
FMCS:WE(bit5)
Flash memory deletion enabled
Deletion command sequence
1. FxAAAA
XXAA
2. Fx5554
XX55
3. FxAAAA
XX80
4. FxAAAA
XXAA
5. Fx5554
XX55
1
Sector deletion timer (DQ3)
0
Input the code to the sector to be
deleted. (30H)
Y
Internal address read
Is there another sector
to be deleted?
N
Internal adress read 1
Internal adress read 2
Toggle (DQ6)
Data 1 (DQ6) = Data 2 (DQ6)
Next sector
Y
N
O
Time limit (DQ5)
1
Internal adress read 1
Internal adress read 2
N
Toggle bit (DQ6)
Data 1 (DQ6) = Data 2 (DQ6)
Y
Delete error
N
Last sector
Y
FMCS:WE(bit15)
Flash memory deletion disabled
Deletion completion
Verification using
the hardware sequence flag
Figure 22.6.4-1 Example of Procedure of Deleting the Sector from the Flash Memory
MB90820 series
595
22.6.5 Temporarily Stopping the Sector Deletion
This section explains the procedure of issuing the sector deletion temporary stop
command and temporarily stopping the deletion of a sector from the flash memory.
This command can read the data from the sector not being deleted.
■ Temporarily stopping the sector deletion
The sector deletion from the flash memory can be temporarily stopped by continuously sending
the sector deletion temporary stop command, listed in the command sequence table (see
Section 22.4, "Method of Starting the Automatic Algorithm in Flash Memory"), to the target sector
in the flash memory.
The sector deletion temporary stop command stops the sector deletion operation temporarily,
and enables the data reading from the sector not being deleted. In this case, only the read
operation can be executed, but the write operation cannot be done. This command is valid only
during the sector deletion operation including the deletion waiting time, but it is ignored during
the chip deletion operation or the write operation.
This command is executed by writing the deletion temporary stop code (B0 H). In this case, the
address must indicate an address within the flash memory. During the deletion temporary stop
operation, the reissued deletion temporary stop command is ignored.
If the sector deletion temporary stop command is input during the sector deletion waiting period,
the sector deletion wait is immediately terminated to stop the deletion operation, and the flash
memory enters the deletion stop status. If the sector deletion temporary stop command is input
during the sector deletion operation after the sector deletion waiting period, the flash memory
enters the deletion temporary stop status after a lapse of up to 15 µs.
596
MB90820 series
22.6.6 Restarting the Sector Deletion
This section explains the procedure of issuing the sector deletion restart command
and restarting the operation of deleting a sector from the flash memory, which has
been temporarily stopped.
■ Restarting the sector deletion
The sector deletion operation which has been temporarily stopped can be restarted by
continuously sending the sector deletion restart command, listed in the command sequence
table (see Section 22.4, "Method of Starting the Automatic Algorithm in Flash Memory"), to the
target sector in the flash memory.
The sector deletion restart command is used to restart the sector deletion operation when the
flash memory is in the sector deletion temporary stop status caused by the sector deletion
temporary stop command. This command is executed by writing the deletion restart code (30H).
In this case, the address must indicate an address within the flash memory area.
However, the sector deletion restart command issued during the sector deletion operation is
ignored.
MB90820 series
597
22.7 Flash Security Feature
The Flash Security Controller provides possibilities to protect the content of the flash
memory from being read from external pins.
One predefined address of the flash memory is assigned to the Flash Security Controller
(MB90F822: FF0001H; MB90F823: FE0001H). If the protection code of “01H” is written in this
address, access to the flash memory is restricted. Once the flash memory is protected,
preforming the chip erase operation only can unlock the function otherwise read/write access to
the flash memory from any external pins is not generally possible.
This function is suitable for applications requiring security of self-containing program and data
stored in the flash memory. If the target application requires any part of the program to locate
outside the microcontroller, the Flash Security Controller can not offer the intended features. For
this reason, the External Vector Fetch mode should not be used when the protection code is set.
Programming of the flash microcontroller by standard parallel programmer may require unique
set-up. For example, with the programmer from Minato Electronics the device checking should
be turned off. Writing the protection code is generally recommended to take place at the end of
the flash programming. This is to avoid unnecessary protection during the programming.
In order to re-program the once protected flash memory, the chip erase operation should be
preformed.
For further information, please contact Fujitsu.
598
MB90820 series
22.8 Programming Example of 512K Bit Flash Memory
This section presents a programming example for the use of 512K bit flash memory.
■ Programming Example Using 512K Bit Flash Memory
NAME FLASHWE
TITLE FLASHWE
;--------------------------------------------------------------------------;512k-FLASH Sample program for 512-Kb FLASH
;
;1: Transfer the program from the flash memory (address: FFBC00H sector: SA2) to RAM (address: 000700H).
;2: Run the transferred program in RAM.
;3: Write the value of PDR1 to the flash memory (address: FF0000H sector: SA0).
;4: Read the written value (address: FF0000H sector: SA0), and output the value to PDR2.
;5: Erase the sector (SA0) to which the value was written.
;6: Output a confirmation that the data was erased.
; Requirements:
;
- Number of bytes transferred to RAM: 100 H (256 B)
;
- Determination that writing or erasing has ended
;
Determined via DQ5 (timing limit exceeded flag)
;
Determined via DQ6 (toggle bit flag)
;
Determined via RDY (FMCS)
;
- Error handling
;
Output Hi to P00 to P07.
;
Issue a reset command.
;--------------------------------------------------------------------------;
ABS=00
;"RESOUS" I/O segment definition
RESOUS IOSEG
ORG
0000H
PDR0
RB
1
PDR1
RB
1
PDR2
RB
1
PDR3
RB
1
ORG
0010H
DDR0
RB
1
DDR1
RB
1
DDR2
RB
1
DDR3
RB
1
ORG
00A1H
CKSCR
RB
1
ORG
00AEH
FMCS
RB
1
ORG
006FH
ROMM
RB
1
RESOUS ENDS
;
SSEG
SSTA
RW
0127H
STA_T
RW
1
SSTA
ENDS
;
DSEG
ABS=0FFH
;Flash command address
DATA
ORG
5554H
COMADR2 RW
1
ORG
0AAAAH
COMADR1 RW
1
MB90820 series
599
DATA ENDS
;///////////////////////////////////////////////////////////////
;Main program (SA1)
;///////////////////////////////////////////////////////////////
CODE CSEG
START:
;//////////////////////////////////////////////////////
;Initialization
;//////////////////////////////////////////////////////
MOV
CKSCR,#0BAH
;Set a frequency multiplier of three.
MOV
RP,#0
MOV
A,#!STA_T
MOV
SSB,A
MOVW
A,#STA_T
MOVW
SP,A
MOV
ROMM,#00H
;Mirror OFF
MOV
PDR0,#00H
;For error check
MOV
DDR0,#0FFH
MOV
PDR1,#00H
;Data input port
MOV
DDR1,#00H
MOV
PDR2,#00H
;Data output port
MOV
DDR2,#0FFH
;////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
;The flash memory write/erase program (FFBC00H) is transferred to RAM (1500H address).
;////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
MOVW
A,#0700H
;Destination RAM area
MOVW
A,#0BC00H
;Source address (location of program)
MOVW
RW0,#100H
;Number of bytes of data transferred to RAM
MOVS
ADB,PCB
;Transfer 100H from FFBC00H to 000700H.
CALLP
000700H
;Jump to the address where the transferred program
exists.
;/////////////////////////////////////////////////////
;Data output
;/////////////////////////////////////////////////////
OUT
MOV
A,#0FEH
MOV
ADB,A
MOVW
RW2,#0000H
MOVW
A,@RW2+00
MOV
PDR2,A
END
JMP
*
CODE
ENDS
;///////////////////////////////////////////////////////////////////
; Flash program write/erase program (SA2)
;///////////////////////////////////////////////////////////////////
RAMPRG CSEG
ABS=0FFH
ORG
0BC00H
;
////////////////////////////////////////////
;
Initialization
;
////////////////////////////////////////////
MOVW
RW0,#0500H
;RW0: Reserve RAM space for input area
00:0500 to
MOVW
RW2,#0000H
;RW2: Flash memory write address
FF:0000 to
MOV
A,#00H
;DTB modification
MOV
DTB,A
;Bank specification for @RW0
MOV
A,#0FFH
;ADB modification 1
MOV
ADB,A
;Bank specification for write mode specification
address
600
MB90820 series
MOV
MOV
PDR3,#00H
DDR3,#00H
;Switch initialization
;
WAIT1
BBC
PDR3:0,WAIT1
;Writing starts if PDR3:0 Hi.
;
;/////////////////////////////////////////////////
; Write (SA0)
;/////////////////////////////////////////////////
MOV
A,PDR1
MOVW
@RW0+00,A
;PDR1 data is stored in RAM.
MOV
FMCS,#20H
;Write mode setting
MOVW ADB:COMADR1,#00AAH
;Flash write command 1
MOVW ADB:COMADR2,#0055H
;Flash write command 2
MOVW ADB:COMADR1,#00A0H
;Flash write command 3
;
MOVW
A,@RW0+00
; Input data (RW0) is written to flash memory (RW2).
MOVW
@RW2+00,A
WRITE ; Wait time check
;
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
;
If the "time-limit-exceeded" check flag is set while toggling is on, branches to ERROR.
;
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOW
;Time limit exceeded
MOVW
A,@RW2+00
;AH
MOVW
A,@RW2+00
;AL
XORW
A
;XOR of AH and AL (1 when the values
are different.)
AND
A,#40H
;Checks whether the DQ6 toggle bit is
different.
BNZ
ERROR
;If it is different, branches to ERROR
;
///////////////////////////////////////////////
;
Write-end check (FMCS-RDY)
;
////////////////////////////////////////////////
NTOW
MOVW
A,FMCS
AND
A,#10H
;FMCS RDY bit (4 bit) is extracted.
BZ
WRITE
;Verifies that writing has ended.
MOV
FMCS,#00H
;Write mode is released.
;/////////////////////////////////////////////////////
; Write data output
;/////////////////////////////////////////////////////
MOVW
RW2,#0000H
;Write data output
MOVW
A,@RW2+00
MOV
PDR2,A
;
BBC
PDR3:1,WAIT2
;If PDR3:1 Hi, erasing of the sector starts.
WAIT2
;
;/////////////////////////////////////////////
; Erasing sectors (SA0)
;/////////////////////////////////////////////
MOVW
@RW2+00,#0000H
;Address initialization
MOV
FMCS,#20H
;Erase mode setting
MOVW
ADB:COMADR1,#00AAH
;Flash memory erase command 1
MOVW
ADB:COMADR2,#0055H
;Flash memory erase command 2
MOVW
ADB:COMADR1,#0080H
;Flash memory erase command 3
MOVW
ADB:COMADR1,#00AAH
;Flash memory erase command 4
MOVW
ADB:COMADR2,#0055H
;Flash memory erase command 5
MB90820 series
601
MOVW
@RW2+00,#0030H
;Issuing the erase command to the sector to be erased. 6
; Wait-time check
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
When the "time-limit-exceeded" check flag is set and toggling is on, branches to ERROR.
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
MOVW
A,@RW2+00
AND
A,#20H
;DQ5 time limit check
BZ
NTOE
;Time limit exceeded
MOVW
A,@RW2+00
;AH From DQ6 during writing
MOVW
A,@RW2+00
;AL Hi and Low are output alternately by each read.
XORW
A
;XOR of AH and AL (If the DQ6 value is toggled,
XOR is 1, indicating that writing is in progress.)
AND
A,#40H
;Checks whether the DQ6 toggle bit is Hi.
BNZ
ERROR
;If the bit is Hi, branches to ERROR
;
////////////////////////////////////////////////
;
Erase-end check (FMCS-RDY)
;
////////////////////////////////////////////////
NTOE
MOVW
A,FMCS
;
AND
A,#10H
;FMCS RDY bit (4 bit) is extracted.
BZ ELS
;Verifies that erasing of the sector has ended.
MOV
FMCS,#00H
;Flash memory erase mode is released.
RETP
;Returns to the main program.
;//////////////////////////////////////////////
; Error
;//////////////////////////////////////////////
ERROR
MOV
ADB:COMADR1,#0F0H
;Reset command (enabling data reading)
MOV
FMCS,#00H
;Flash command mode is released.
MOV
PDR0,#0FFH
;Confirmation of error processing.
RETP
;Returns to the main program.
RAMPRG ENDS
;/////////////////////////////////////////////
VECT
CSEG
ABS=0FFH
ORG
0FFDCH
DSL
START
DB
00H
VECT
ENDS
;
END START
ELS
;
;
;
602
MB90820 series
APPENDIX A
I/O MAP
Table A-1 lists the addresses assigned to the registers for peripheral functions in the
MB90820 series.
■ I/O map
Table A-1 I/O map
Byte
Word
access access
Resource name
Initial
value
R/W
Port 0
XXXXXXXXB
R/W
R/W
Port 1
XXXXXXXXB
R/W
R/W
Port 2
XXXXXXXXB
Port 3 data register
R/W
R/W
Port 3
XXXXXXXXB
Port 4 data register
R/W
R/W
Port 4
XXXXXXXXB
PDR5
Port 5 data register
R/W
R/W
Port 5
XXXXXXXXB
PDR6
Port 6 data register
R/W
R/W
Port 6
XXXXXXXXB
000007H
PDR7
Port 7 data register
R/W
R/W
Port 7
XXXXXXXXB
000008H
PDR8
Port 8 data register
R/W
R/W
Port 8
XXXXXXXXB
Address
Abbreviation
Register
000000H
PDR0
Port 0 data register
R/W
000001H
PDR1
Port 1 data register
000002H
PDR2
Port 2 data register
000003H
PDR3
000004H
PDR4
000005H
000006H
000009H
~ 0FH
Prohibited area
000010H
DDR0
Port 0 direction register
R/W
R/W
Port 0
00000000B
000011H
DDR1
Port 1 direction register
R/W
R/W
Port 1
00000000B
000012H
DDR2
Port 2 direction register
R/W
R/W
Port 2
00000000B
000013H
DDR3
Port 3 direction register
R/W
R/W
Port 3
00000000B
000014H
DDR4
Port 4 direction register
R/W
R/W
Port 4
00000000B
000015H
DDR5
Port 5 direction register
R/W
R/W
Port 5
XXXXXX00B
000016H
DDR6
Port 6 direction register
R/W
R/W
Port 6
00000000B
000017H
DDR7
Port 7 direction register
R/W
R/W
Port 7
00000000B
000018H
DDR8
Port 8 direction register
R/W
R/W
Port 8
00000000B
000019H
~ 1FH
000020H
000021H
000022H
Prohibited area
SMR0
Serial mode register 0
R/W
R/W
SCR0
Serial control register 0
R/W
R/W
SIDR0 / SODR0 Input data register 0 / Output data register 0
R/W
R/W
00000000B
UART0
00000100B
XXXXXXXXB
000023H
SSR0
Serial status register 0
R/W
R/W
00001000B
000024H
SMR1
Serial mode register 1
R/W
R/W
00000000B
SCR1
Serial control register 1
R/W
R/W
SIDR1 / SODR1 Input data register 1 / Output data register 1
R/W
R/W
R/W
R/W
00001000B
R/W
R/W
00000000B
R/W
R/W
000025H
000026H
000027H
SSR1
000028H
PWCSL1
000029H
PWCSH1
00002AH
00002BH
00002CH
PWC1
DIV1
00002DH
~ 2EH
MB90820 series
Status register 1
PWC control status register CH1
PWC data buffer register CH1
Divide ratio control register CH1
-
R/W
R/W
R/W
UART1
00000100B
XXXXXXXXB
00000000B
PWC timer (CH1)
XXXXXXXXB
XXXXXXXXB
XXXXXX00B
Prohibited area
603
Address
Abbreviation
00002FH
PCKCR
000030H
ENIR
000031H
EIRR
000032H
000033H
PLL clock control register
000038H
000039H
00003AH
00003BH
00003CH
00003DH
R/W
R/W
00000000B
R/W
R/W
XXXXXXXXB
ELVRL
Request level setting register (lower byte)
R/W
R/W
ELVRH
Request level setting register (higher byte)
R/W
R/W
CDCR0
Clock division control register 0
CDCR1
Clock division control register 1
PDCR0
PCSR0
000044H
000045H
PDUT0
R/W
Communication prescaler 0
00XXX000B
R/W
R/W
Communication prescaler 1
00XXX000B
PPG0 down counter register
-
R
PPG0 period setting register
-
W
00004CH
00004DH
11111111B
XXXXXXXXB
PPG0 control status register
R/W
XX000000B
R/W
R/W
00000000B
PPG1 period setting register
-
W
XXXXXXXXB
11111111B
11111111B
XXXXXXXXB
16-bit PPG timer (CH1)
PPG1 duty setting register
PPG1 control status register
R/W
R/W
XX000000B
R/W
R/W
00000000B
-
R
PCSR2
PPG2 period setting register
-
W
XXXXXXXXB
11111111B
11111111B
XXXXXXXXB
16-bit PPG timer (CH2)
PCNTL2
00004FH
PCNTH2
PPG2 control status register
XXXXXXXXB
W
PPG2 down counter register
PPG2 duty setting register
XXXXXXXXB
-
PDCR2
PDUT2
XXXXXXXXB
R/W
PCSR1
PDUT1
XXXXXXXXB
W
R
00004EH
000050H
11111111B
-
-
PCNTL1
00004BH
PPG0 duty setting register
PPG1 down counter register
PCNTH1
00004AH
R/W
PDCR1
000047H
000049H
00000000B
16-bit PPG timer (CH0)
000046H
000048H
00000000B
Prohibited area
PCNTL0
000043H
DTP/external interrupt
Prohibited area
PCNTH0
000042H
XXXX0000B
Interrupt / DTP cause register
00003FH
000041H
PLL
Interrupt / DTP enable register
00003EH
000040H
Initial
value
W
000036H
000037H
Resource name
W
000034H
000035H
Byte
Word
access access
Register
XXXXXXXXB
XXXXXXXXB
-
W
R/W
R/W
XX000000B
R/W
R/W
00000000B
XXXXXXXXB
XXXXXXXXB
TMRR0
16-bit timer register 0
-
R/W
TMRR1
16-bit timer register 1
-
R/W
TMRR2
16-bit timer register 2
-
R/W
000056H
DTCR0
16-bit timer control register 0
R/W
R/W
00000000B
000057H
DTCR1
16-bit timer control register 1
R/W
R/W
00000000B
000058H
DTCR2
16-bit timer control register 2
R/W
R/W
00000000B
000059H
SIGCR
Waveform control register
R/W
R/W
00000000B
000051H
000052H
000053H
000054H
000055H
604
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Waveform generator
XXXXXXXXB
XXXXXXXXB
MB90820 series
Address
Abbreviation
00005AH
CPCLRB /
CPCLR
00005BH
00005CH
00005DH
Byte
Word
access access
Register
Compare clear buffer register /
Compare clear register (lower)
-
16-bit free-running timer
TCDT
Timer data register (lower)
-
R/W
TCCSL
Timer control status register (lower)
R/W
R/W
00005FH
TCCSH
Timer control status register (upper)
R/W
R/W
000061H
000062H
000063H
000064H
000065H
000066H
000067H
Initial
value
11111111B
R/W
00005EH
000060H
Resource name
11111111B
00000000B
00000000B
16-bit free-running timer
00000000B
X0000000B
XXXXXXXXB
IPCP0
Input capture data register CH0
-
R
IPCP1
Input capture data register CH1
-
R
IPCP2
Input capture data register CH2
-
R
IPCP3
Input capture data register CH3
-
R
R/W
R/W
00000000B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
16-bit input capture
(CH0 ~ CH3)
XXXXXXXXB
000068H
PICSL01
PPG output control / Input capture control
status register 01 (lower)
000069H
PICSH01
PPG output control / Input capture control
status register 01 (upper)
R/W
R/W
00000000B
00006AH
ICSL23
Input capture control status register 23
(lower)
R/W
R/W
00000000B
00006BH
ICSH23
Input capture control status register 23
(upper)
R
R
XXXXXX00B
00006CH
~ 6EH
Prohibited area
00006FH
ROMM
000070H
W
W
OCCPB0 /
OCCP0
Output compare buffer register / Output
compare register 0
-
R/W
OCCPB1 /
OCCP1
Output compare buffer register / Output
compare register 1
-
R/W
OCCPB2 /
OCCP2
Output compare buffer register / Output
compare register 2
-
R/W
OCCPB3 /
OCCP3
Output compare buffer register / Output
compare register 3
-
R/W
OCCPB4 /
OCCP4
Output compare buffer register / Output
compare register 4
-
R/W
00007BH
OCCPB5 /
OCCP5
Output compare buffer register / Output
compare register 5
-
R/W
00007CH
OCS0
Compare control register 0
R/W
R/W
00000000B
00007DH
OCS1
Compare control register 1
R/W
R/W
X0000000B
00007EH
OCS2
Compare control register 2
R/W
R/W
00000000B
00007FH
OCS3
Compare control register 3
R/W
R/W
X0000000B
000080H
OCS4
Compare control register 4
R/W
R/W
00000000B
000081H
OCS5
Compare control register 5
R/W
R/W
X0000000B
000071H
000072H
000073H
000074H
000075H
000076H
000077H
000078H
000079H
00007AH
ROM mirroring function selection register
ROM mirroring function
XXXXXXX1B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
Output compare
(CH0 ~ CH5)
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
000082H
TMCSRL0
Timer control status register CH0 (lower)
R/W
R/W
00000000B
000083H
TMCSRH0
Timer control status register CH0 (upper)
R/W
R/W
XXXX0000B
-
R/W
000084H
000085H
TMR0 / TMRD0
MB90820 series
16 bit timer register CH0 / 16-bit reload
register CH0
16-bit reload timer (CH0)
XXXXXXXXB
XXXXXXXXB
605
Byte
Word
access access
Address
Abbreviation
000086H
TMCSRL1
Timer control status register CH1 (lower)
R/W
R/W
000087H
TMCSRH1
Timer control status register CH1 (upper)
R/W
R/W
000088H
000089H
TMR1 / TMRD1
Register
16 bit timer register CH1 / 16-bit reload
register CH1
00008AH
~ 8BH
-
Resource name
Initial
value
00000000B
16-bit reload timer (CH1)
R/W
XXXX0000B
XXXXXXXXB
XXXXXXXXB
Prohibited area
00008CH
RDR0
Port 0 pull-up resistor setting register
R/W
R/W
Port 0
00000000B
00008DH
RDR1
Port 1 pull-up resistor setting register
R/W
R/W
Port 1
00000000B
00008EH
RDR2
Port 2 pull-up resistor setting register
R/W
R/W
Port 2
00000000B
00008FH
RDR3
Port 3 pull-up resistor setting register
R/W
R/W
Port 3
00000000B
000090H
~ 9D H
Prohibited area
00009EH
PACSR
Program address detect control status
register
R/W
R/W
Address match detection
00000000B
00009FH
DIRR
Delayed interrupt cause / clear register
R/W
R/W
Delayed interrupt
XXXXXXX0B
0000A0H
LPMCR
Low-power consumption mode register
R/W
R/W
CKSCR
Clock selection register
R/W
R/W
Low-power consumption
control register
00011000B
0000A1H
0000A2H
~ A7H
11111100B
Prohibited area
0000A8H
WDTC
Watchdog control register
R/W
R/W
Watchdog timer
XXXXX111B
0000A9H
TBTC
Timebase timer control register
R/W
R/W
Timebase timer
1XX00100B
R/W
Flash memory interface
circuit
00010000B
0000AAH
~ ADH
0000AEH
Prohibited area
FMCS
Flash memory control status register
0000B0H
ICR00
Interrupt control register 00
R/W
R/W
00000111B
0000B1H
ICR01
Interrupt control register 01
R/W
R/W
00000111B
0000B2H
ICR02
Interrupt control register 02
R/W
R/W
00000111B
0000B3H
ICR03
Interrupt control register 03
R/W
R/W
00000111B
0000B4H
ICR04
Interrupt control register 04
R/W
R/W
00000111B
0000B5H
ICR05
Interrupt control register 05
R/W
R/W
00000111B
0000B6H
ICR06
Interrupt control register 06
R/W
R/W
00000111B
0000B7H
ICR07
Interrupt control register 07
R/W
R/W
0000B8H
ICR08
Interrupt control register 08
R/W
R/W
0000AFH
R/W
Prohibited area
Interrupt controller
00000111B
00000111B
0000B9H
ICR09
Interrupt control register 09
R/W
R/W
00000111B
0000BAH
ICR10
Interrupt control register 10
R/W
R/W
00000111B
0000BBH
ICR11
Interrupt control register 11
R/W
R/W
00000111B
0000BC H
ICR12
Interrupt control register 12
R/W
R/W
00000111B
0000BD H
ICR13
Interrupt control register 13
R/W
R/W
00000111B
0000BEH
ICR14
Interrupt control register 14
R/W
R/W
00000111B
0000BFH
ICR15
Interrupt control register 15
R/W
R/W
00000111B
0000C0H
PWCSL0
R/W
R/W
00000000B
0000C1H
PWCSH0
R/W
R/W
0000C2H
0000C3H
0000C4H
606
PWC0
DIV0
PWC control status register CH0
PWC data buffer register CH0
Divide ratio control register CH0
-
R/W
R/W
R/W
00000000B
PWC timer (CH0)
XXXXXXXXB
XXXXXXXXB
XXXXXX00B
MB90820 series
Byte
Word
access access
Register
Resource name
Initial
value
Port 6, A/D
11111111B
Address
Abbreviation
0000C5H
ADER0
A/D input enable register 0
R/W
R/W
0000C6H
ADCS0
A/D control status register 0
R/W
R/W
000XXXX0B
0000C7H
ADCS1
A/D control status register 1
R/W
R/W
0000000XB
0000C8H
ADCR0
A/D data register 0
R
R
0000C9H
ADCR1
A/D data register 1
R/W
R/W
0000CAH
ADSR0
A/D setting register 0
R/W
R/W
00000000B
0000CBH
ADSR1
A/D setting register 1
R/W
R/W
00000000B
0000CC H
DAT0
D/A data register 0
R/W
R/W
XXXXXXXXB
0000CD H
DAT1
D/A data register 1
R/W
R/W
0000CEH
DACR0
D/A control register 0
R/W
R/W
0000CFH
DACR1
D/A control register 1
R/W
R/W
0000D0H
ADER1
A/D input enable register 1
R/W
R/W
0000D1H
~ EFH
Prohibited area
0000F0H
~ FFH
External area
8/10-bit A/D converter
8-bit D/A converter
00000000B
XXXXXX00B
XXXXXXXXB
XXXXXXX0B
XXXXXXX0B
Port 7, A/D
11111111B
001FF0H
PADRL0
Program address detection register 0
(lower byte)
R/W
R/W
XXXXXXXXB
001FF1H
PADRM0
Program address detection register 0
(middle byte)
R/W
R/W
XXXXXXXXB
001FF2H
PADRH0
Program address detection register 0
(higher byte)
R/W
R/W
XXXXXXXXB
Address match detection
001FF3H
PADRL1
Program address detection register 1
(lower byte)
R/W
R/W
XXXXXXXXB
001FF4H
PADRM1
Program address detection register 1
(middle byte)
R/W
R/W
XXXXXXXXB
001FF5H
PADRH1
Program address detection register 1
(higher byte)
R/W
R/W
XXXXXXXXB
MB90820 series
607
● Meaning of abbreviations used for reading and writing
R/W: Read and write enabled
R:
Read-only
W:
Write-only
● Explanation of initial values
0: The bit is initialized to 0.
1: The bit is initialized to 1.
X: The initial value of the bit is undefined.
608
MB90820 series
APPENDIX B
EXAMPLE OF F²MC-16LX MB90F822/F823
CONNECTION FOR SERIAL WRITING
This chapter describes examples of F2MC-16LX MB90F822/F823 connections for serial
writing.
B.1 Standard Configuration for Serial On-board Writing (Fujitsu Standard)
B.2 Example of Connection for Serial Writing (When Power Supplied by User)
B.3 Example of Connection for Serial Writing (When Power Supplied from
Writer)
B.4 Example of Minimum Connection with Flash Microcomputer Programmer
(When Power Supplied by User)
B.5 Example of Minimum Connection with Flash Microcomputer Programmer
(When Power Supplied from Writer)
MB90820 series
609
B.1
Standard Configuration for Serial On-board Writing (Fujitsu
Standard)
MB90F822/F823 supports serial on-board writing (Fujitsu standard) to flash ROM. This
describes the specifications for serial on-board writing.
■ Standard configuration for Fujitsu standard serial on-board writing
The AF200 flash microcomputer programmer of Yokogawa Digital Computer Co., Ltd. is used for
Fujitsu standard serial on-board writing.
Host interface cable (AZ201)
RS232C
AF200
flash
microcomputer
programmer
+
memory card
General-purpose common cable (AZ210)
Clock
synchronous
serial
MB90F462/F462A/F463A
user system
Operable in stand-alone mode
[Check]
Contact Yokogawa Digital Computer Co., Ltd. for the functionality and operation of the AF200
flash microcomputer programmer and information on the general-purpose common cable
(AZ210) and connectors.
Table B.1-1 Pins used for Fujitsu standard serial on-board writing
Pin
Function
Description
MD2, MD1,
MD0
Mode pin
Used to enable write mode for the flash microcomputer programmer.
X0, X1
Oscillator pin
In write mode, since the operation clock is one times the CPU clock, the
oscillation clock frequency is the internal operation clock.
The resonator used for serial rewriting is therefore 1 MHz ~ 16 MHz.
P00, P01
Write program start
pin
–
RSTX
Reset pin
–
SIN0
Serial data input pin
SOT0
Serial data output pin
SCK0
Serial clock input pin
C
C pin
Capacitance pin for power stabilization. Connect a ceramic capacitor of
about 0.1 µF to the outside.
VCC
Power supply pin
If write voltage (5 V ± 10%) is supplied from the user system, this pin need
not be connected to the flash microcomputer programmer. If the pin is
connected to the flash microcomputer programmer, do not connect it to the
power of the user system.
VSS
Ground pin
Used also as the ground pin for the flash microcomputer programmer.
UART0 is used in CLK synchronous mode.
Note: When the P00, P01, SIN0, SOT0, SCK0 pins are also used by the user system, the
610
MB90820 series
control circuit shown below is required. (The /TICS signal of the flash microcomputer
programmer can separate the user circuit during serial writing. See the connection
example shown later.)
AF200
write control pin
MB90F822/F823
write control pin
10KΩ
AF200
/TICS pin
User
Figure B.1-1 Control circuit
Refer to the following four serial writing examples in Appendix B.2 ~ B.5.
•
Example of serial write connection when power supplied by user
•
Example of serial write connection when power supplied from writer
•
Example of minimum connection to flash microcomputer programmer when power supplied
by user
•
Example of minimum connection to flash microcomputer programmer when power supplied
from writer
Table B.1-2 System configuration of AF200 flash microcomputer programmer
(Yokogawa Digital Computer Co., Ltd.)
Type
Function
AF200 ACP
Flash microcomputer programmer/100 V power supply adapter
AF200 AC2P
Flash microcomputer programmer/power supply adapter with overseas specification
AZ201
RS232C cable for PC/AT
AZ210
Standard target probe (a) Length: 1 m
FF001
Control module for Fujitsu F2 MC-16LX flash microcomputer
FF001 P2
2 MB PC Card (Option)
FF001 P4
4 MB PC Card (Option)
For more information, contact the Sales Department, Equipment Business Division, Yokogawa
Digital Computer Co., Ltd. (Telephone: 042-333-6224).
MB90820 series
611
B.2
Example of Connection for Serial Writing (When Power
Supplied by User)
Figure B.2-1 is an example of serial write connection when power is supplied by the
user.
MD2=1 and MD0=0 are input from TAUX3 and TMODE respectively in AF200 flash
microcomputer programmer. Serial write mode: MD2, MD1, MD0 = 110B
■ Example of connection for serial writing (when power supplied by user)
AF200 flash
microcomputer
programmer
User system
Connector
DX10-28S
MB90F822/F823
(19)
TAUX3
MD2
10kΩ
10kΩ
MD1
10kΩ
TMODE
MD0
(12)
X0
1MHz-16MHz
X1
(23)
TAUX
P00
10KΩ
(10)
/TICS
User
10kΩ
/TRES
(5)
10kΩ
User
P01
C
0.1µF
TTXD
TVcc
GND
SIN0
SOT0
SCK0
(13)
(27)
(6)
TRXD
TCK
(2)
(7,8,
14,15,
21,22,
1,28)
Vcc
User power
supply
Pin 14
Pins 3, 4, 9, 11, 16,
17, 18,20, 24, 25,
and 26 are open.
DX10-28S, right-angle type
Vss
Pin 1
DX10-28S
Pin 28
Pin 15
Connector (made by Hirose Electric) pin layout
Figure B.2-1 Example of connection for serial writing in MB90F822/F823 internal vector mode (when
power supplied by user)
612
MB90820 series
•
When the user system also uses pins SIN0, SOT0 and SCK0, the control circuit shown below
is necessary, just as it is for P00. (During serial writing, the user circuit can be disconnected
by the flash microcomputer programmer /TICS signal.)
•
Before connecting the AF200, turn off the power supplied by the user.
AF200
write control pin
MB90F822/F823
write control pin
10KΩ
AF200
/TICS pin
User
MB90820 series
613
B.3
Example of Connection for Serial Writing (When Power
Supplied from Writer)
Figure B.3-1 is an example of serial write connection when power is supplied from the
writer.
MD2=1 and MD0 are input from TAUX3 and TMODE respectively in AF200 flash
microcomputer programmer. Serial write mode: MD2, MD1, MD0 = 110B
■ Example of connection for serial writing (when power supplied from writer)
AF200 flash
microcomputer
programmer
User system
Connector
DX10-28S
MB90F822/F823
(19)
TAUX3
MD2
10kΩ
10kΩ
MD1
10kΩ
TMODE
MD0
(12)
X0
1MHz-16MHz
X1
(23)
TAUX
P00
10KΩ
(10)
/TICS
User
10kΩ
/TRES
(5)
10kΩ
User
P01
C
0.1µF
TTXD
TRXD
TCK
TVcc
GND
SIN0
SOT0
SCK0
(13)
(27)
(6)
(2)
(7,8,
14,15,
21,22,
1,28)
Vcc
User power
supply
Pin 14
Pins 3, 4, 9, 11, 16,
17, 18,20, 24, 25,
and 26 are open.
DX10-28S, right-angle type
Vss
Pin 1
DX10-28S
Pin 28
Pin 15
Connector (made by Hirose Electric) pin layout
Figure B.3-1 Example of connection for serial writing in MB90F822/F823 internal vector mode
(when power supplied from writer)
614
MB90820 series
•
When the SIN0, SOT0 and SCK0 pins are also used by the user system, the control circuit
shown below is necessary, just as it is for P00. (During serial writing, the user circuit can be
disconnected by the flash microcomputer /TICS signal.)
•
Before connecting the AF200, turn off the power supplied by the user.
•
When supplying write power from the AF200, do not create a short with the power supplied
by the user.
AF200
write control pin
MB90F822/F823
write control pin
10KΩ
AF200
/TICS pin
User
MB90820 series
615
B.4
Example of Minimum Connection with Flash Microcomputer
Programmer (When Power Supplied by User)
Figure B.4-1 is an example of the minimum connection with the flash microcomputer
programmer when power is supplied by the user.
Serial write mode: MD2, MD1, MD0 = 110B
■ Example of minimum connection with flash microcomputer programmer (when power supplied by
user)
If the pins are set as shown in Figure B.4-1 during writing to flash memory, MD2, MD1, MD0,
P00 and flash microcomputer programmer connection is unnecessary.
AF200 flash
microcomputer
programmer
User system
Serial write 1
10kΩ
MB90F822/F823
MD2
Serial
rewriting
10kΩ
10kΩ
10kΩ
10kΩ
MD1
MD0
10kΩ
X0
1MHz-16M Hz
X1
Serial
write 0
P00
10kΩ
User circuit
P01
Serial write 1
User circuit
Connector
DX10-28S
/TRES
TTXD
TRXD
TCK
TVcc
(27)
GND
(7,8,
14,15,
21,22,
1,28)
10kΩ
(5)
RSTX
(6)
SIN0
SOT0
SCK0
(2)
Vcc
(13)
Pins 3, 4, 9, 10, 11,
12, 16, 17, 18, 19,
20, 23, 24, 25, and
26 are open.
DX10-28S, right-angle type
C
0.1µF
User power supply Vss
Pin 14
Pin 1
DX10-28S
Pin 15
Pin 28
Connector (made by Hirose Electric) pin layout
Figure B.4-1 Example of minimum connection with flash microcomputer programmer
(when power supplied by user)
616
MB90820 series
•
When the user system also uses the SIN0, SOT0 and SCK0 pins, the control circuit shown
below is necessary. (During serial writing, the user circuit can be disconnected by the flash
microcomputer programmer /TICS signal.)
•
Before connecting the AF200, turn off the power supplied by the user.
AF200
write control pin
MB90F822/F823
write control pin
10KΩ
AF200
/TICS pin
User
MB90820 series
617
B.5
Example of Minimum Connection with Flash Microcomputer
Programmer (When Power Supplied from Writer)
Figure B.5-1 is an example of the minimum connection with the flash microcomputer
programmer when power is supplied from the writer.
■ Example of minimum connection with flash microcomputer programmer (when power supplied from
writer)
If the pins are set as shown in Figure B.5-1 during writing to flash memory, MD2, MD1, MD0,
P00 and flash microcomputer programmer connection is unnecessary.
AF200 flash
microcomputer
programmer
User system
10kΩ
Serial write1
MB90F822/F823
MD2
10kΩ
10kΩ
MD1
Serial
write1
10kΩ
10kΩ
MD0
Serial write0
10kΩ
X0
1MHz-16MHz
X1
P00
10kΩ
Serial
write0
User circuit
Serial write1
10kΩ
User
circuit
P01
C
0.1µF
Connector
DX10-28S
/TRES
TTXD
TRXD
TCK
TVcc
Vcc
TVPP1
GND
(5)
(13)
(27)
(6)
(2)
(3)
(16)
(7,8,
14,15,
21,22,
1,28)
Pins 4, 9, 10, 11, 12,
17, 18, 19, 20, 23, 24,
25, and 26 are open.
DX10-28S, right-angle type
10kΩ
User power
supply
Pin 14
RSTX
SIN0
SOT0
SCK0
Vcc
Vss
Pin 1
DX10-28S
Pin 28
Pin 15
Connector (made by Hirose Electric) pin layout
Figure B.5-1 Example of minimum connection with flash microcomputer programmer
(when power supplied from writer)
618
MB90820 series
•
When the user system also uses the SIN0, SOT0, SCK0 pins, the control circuit shown below
is necessary. (During serial writing, the user circuit can be disconnected by the flash
microcomputer programmer /TICS signal.)
•
Before connecting the AF200, turn off the power supplied by the user.
•
When write power is supplied from the AF200, do not create a short with the power supplied
by user.
AF200
write control pin
MB90F822/F823
write control pin
10KΩ
AF200
/TICS pin
User
MB90820 series
619
620
MB90820 series
APPENDIX C
INSTRUCTIONS
This appendix describes the instructions used by the F2MC-16LX.
C.1 Instructions
C.2 Addressing
C.3 Direct Addressing
C.4 Indirect Addressing
C.5 Number of Execution Cycles
C.6 Effective-address Field
C.7 Reading the Instruction List
C.8 List of F²MC-16LX Instructions
C.9 Instruction Maps
MB90820 series
621
C.1
Instructions
The F²MC-16LX uses the 351 instructions listed below. Addresses must be specified in
the effective address field of an instruction or by an instruction code.
■ Overview of instructions
The F2MC-16LX uses the 351 instructions listed below.
622
•
Transfer (byte):
41 instructions
•
Transfer (word, long-word):
38 instructions
•
Addition/subtraction (byte, word, long-word):
42 instructions
•
Increment/decrement (byte, word, long-word):
12 instructions
•
Comparison (byte, word, long-word):
11 instructions
•
Unsigned multiplication/division (word, long-word)
11 instructions
•
Signed multiplication/division (word, long-word)
11 instructions
•
Logical operation (byte, word):
39 instructions
•
Logical operation (long-word):
6 instructions
•
Sign inversion (byte, word):
6 instructions
•
Normalization (long-word):
1 instruction
•
Shift (byte, word, long-word,):
18 instructions
•
Branching:
50 instructions
•
Accumulator operation (byte, word):
6 instructions
•
Other types of control (byte, word, long-word):
28 instructions
•
Bit operation:
21 instructions
•
String:
10 instructions
MB90820 series
C.2
Addressing
The F2MC-16LX determines the address format according to the instruction's effectiveaddress field or from the instruction code (the address format is implied). When the
address format is determined from the instruction code, the address format that
matches the instruction code is used. More than one type of address format can be
specified for some instructions.
■ Addressing
The F2MC-16LX uses the following 23 types of addressing:
•
Immediate (#imm)
•
Register direct
•
Direct branch (addr16)
•
Physical direct branch (addr24)
•
I/O direct (io)
•
Condensed direct (dir)
•
Direct (addr16)
•
I/O direct bit (io:bp)
•
Condensed direct bit (dir:bp)
•
Direct bit (addr16:bp)
•
Vector (#vct)
•
Register indirect (@RWj j = 0 to 3)
•
Register indirect with post-incrementing
•
(@RWj+ j = 0 to 3)
•
Register indirect with displacement (@RWi+disp8 i = 0 to 7, @RWj+disp16 j = 0 to 3)
•
Long-word register indirect with displacement (@RLi+disp8 i = 0 to 3)
•
Program counter indirect with displacement (@PC+disp16)
•
Register indirect with base index (@RW0+RW7, @RW1+RW7)
•
Program counter relative branch (rel)
•
Register list (rlst)
•
Accumulator indirect (@A)
•
Accumulator indirect branch (@A)
•
Indirect designation branch (@ear)
•
Indirect designation branch (@eam)
MB90820 series
623
■ Effective-address field
Table C.2-1 lists the address formats specified by the effective-address field.
Table C.2-1 Effective-address field
Code
00
01
02
03
04
05
06
07
624
Notation
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Address format
RL0
(RL0)
RL1
(RLL1)
RL2
(RL2)
RL3
(RL3)
Default bank
Register direct
ea corresponds to
byte,
word,
and long-word
formats in order from the left.
None
Register indirect
DTB
DTB
ADB
SPB
Register indirect with post-incrementing
DTB
DTB
ADB
SPB
Register indirect with 8-bit displacement
DTB
DTB
ADB
SPB
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
0C
0D
0E
0F
@RW0+
@RW1+
@RW2+
@RW3+
10
11
12
13
@RW0+disp8
@RW1+disp8
@RW2+disp8
@RW3+disp8
14
15
16
17
@RW4+disp8
@RW5+disp8
@RW6+disp8
@RW7+disp8
Register indirect with 8-bit displacement
DTB
DTB
ADB
SPB
18
19
1A
1B
@RW0+disp16
@RW1+disp16
@RW2+disp16
@RW3+disp16
Register indirect with 16-bit displacement
DTB
DTB
ADB
SPB
1C
1D
1E
1F
WRW0+RW7
@RW1+RW7
@PC+disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
DTB
DTB
SPB
ADB
MB90820 series
C.3
Direct Addressing
In direct addressing, operand values, registers and addresses are specified directly.
■ Direct addressing
● Immediate addressing (#imm)
Operand values are specified directly (#imm4/#imm8/#imm16/#imm32). Figure C.3-1 shows an
example.
MOVW A, #01212H (Instruction that stores the operand value in A)
Before execution
(Some instructions transfer data from AL to AH.)
After execution
Figure C.3-1 Example of immediate addressing (#imm)
● Register direct addressing
Operand values specify registers directly. The following registers can be specified:
General-purpose register
Dedicated registers
*
Byte
R0, R1, R2, R3, R4, R5, R6, R7
Word
RW0, RW1, RW2, RW3, RW4, RW5,
RW6, RW7
Long-word
RL0, RL1, RL2, RL3
Accumulator
A, AL
Pointer
SP*
Bank
PCB, DTB, USB, SSB, ADB
Page
DPR
Control
PS, CCR, RP, ILM
The SP register functions as a user stack pointer (USP) or system stack pointer (SSP)
depending on the S flag bit value indicated in the condition code register (CCR). For
branching instructions, the program counter (PC) is not specified as an operand, but is
implicitly specified.
Figure C.3-2 shows an example.
MB90820 series
625
MOV R0, A (Instruction that transfers lower 8 bits of A to general-purpose register R0)
Before execution
Memory space
After execution
Memory space
Figure C.3-2 Example of register direct addressing
● Direct branch addressing (addr16)
Branch destination addresses are specified directly by displacement. The displacement is 16
bits and is used to specify a branch destination within the logical space. This method is used for
unconditional branching instructions, subroutine call instructions, and software interrupt
instructions. Address bits 16 to 23 are specified by the program bank register (PCB). Figure
C.3-3 shows an example of direct branch addressing (addr16).
JMP 3B20H (Unconditional branch instruction with direct branch address
specified in the bank)
Before execution
Memory space
After execution
Next instruction
Figure C.3-3 Example of direct branch addressing (addr16)
● Physical direct branch addressing (addr24)
Branch destination addresses are specified directly by displacement. The displacement is 24
bits. This method is used for unconditional branching instructions, subroutine call instructions,
and software interrupt instructions. Figure C.3-4 shows an example of physical direct branch
addressing (addr24).
626
MB90820 series
JMPP 333B20H (Unconditional branch instruction with 24-bit direct branch
address specified)
Before execution
Memory space
After execution
Next instruction
Figure C.3-4 Example of physical direct branch addressing (addr24)
● I/O direct addressing (io)
This method specifies memory addresses of the operand directly using an 8-bit displacement.
Regardless of the values of the data bank register (DTB) and direct page register (DPR), the I/O
space at physical addresses 000000H to 0000FFH is accessed. Prefix instructions designating
banks specified before instructions using this addressing method are invalid.
Figure C.3-5 shows an example of I/O direct addressing (io).
MOVW A, i:0C0H (Instruction that reads data by I/O direct addressing
and stores it in A)
Before execution
Memory space
After execution
Figure C.3-5 Example of I/O direct addressing (io)
● Condensed direct addressing (dir)
This method uses the operand to specify the lower eight bits of a memory address directly.
Address bits 8 to 15 are specified by the DPR register. Address bits 16 to 23 are specified by
the DTB register. Figure C.3-6 shows an example of condensed direct addressing (dir).
MOV S:20H, A (Instruction that writes the lower eight bits of A by
condensed direct addressing)
Before execution
Memory space
Memory space
After execution
Figure C.3-6 Example of condensed direct addressing (dir)
MB90820 series
627
● Direct addressing (addr16)
Operand values specify lower 16 bits of an memory address directly. Address bits 16 to 23 are
specified by the DTB register.
Prefixed instructions that specify the access space are invalid for this type of addressing.
Figure C.3-7 shows an example of direct addressing (addr16).
MOVW A, 3B20H (This instruction reads data by direct addressing and stores it in A.)
Before execution
A
Memory space
2 0 2 0 A A B B DTB 5 5
553B21H
553B20H
After execution
A
01
23
A A B B 0 1 2 3 DTB 5 5
Figure C.3-7 Example of direct addressing (addr16)
● I/O direct bit addressing (io:bp)
This method directly specifies bits within the physical address range from 000000H to 0000FFH.
The bit location is expressed as :bp, with higher values representing a more significant bit (MSB)
and lower values representing a less significant bit (LSB). Figure C.3-8 shows an example of I/O
direct bit addressing (io:bp).
SETB i:0C1H:0 (Instruction that sets a bit using I/O direct bit
addressing)
Memory space
Before execution
Memory space
After execution
Figure C.3-8 Example of I/O direct bit addressing (io:bp)
● Condensed direct bit addressing (dir:bp)
This method uses the operand to specify the lower eight bits of the memory address. Address
bits 8 to 15 are specified by the DPR register and address bits 16 to 23 are specified by the DTB
register.
The bit location is expressed as :bp, with a higher value representing an MSB and a lower value
representing an LSB. Figure C.3-9 shows an example of condensed direct bit addressing
(dir:bd).
628
MB90820 series
SETB S:10H:0 (Instruction that sets a bit using condensed direct bit
addressing)
Memory space
Before execution
Memory space
After execution
Figure C.3-9 Example of condensed direct bit addressing (dir:bp)
● Direct bit addressing (addr16:bp)
This method directly specifies any bit within the 64-kilobyte area. Address bits 16 to 23 are
specified by the DTB register.
The bit location is expressed as :bp, with a higher value representing an MSB and a lower value
representing an LSB. Figure C.3-10 shows an example of direct bit addressing (addr16:bp).
SETB 2222H:0 (Instruction sets a bit using direct bit addressing)
Memory space
Before execution
Memory space
After execution
Figure C.3-10 Example of direct bit addressing (addr16:bp)
● Vector addressing (#vct)
In this method, the contents of the specified vector indicates the branch destination address.
The data length of the vector number may be either four bits or eight bits. This method is used
for subroutine call instructions and software interrupt instructions. Figure C.3-11 shows an
example of vector addressing (#vct).
CALLV #15 (Instruction that branches to the address specified by the interrupt
vector specified by the operand)
Before execution
Memory space
After execution
Figure C.3-11 Example of vector addressing (#vct)
MB90820 series
629
Table C.3-1 CALLV vectors
Instruction
Vector address (low)
Vector address (high)
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
<Caution> XX indicates a PCB register value.
<Check>
Note that the vector area is shared with INT #vct8 (#0 to #7) when the PCB register value is
FFH (see Table C.3-1 ).
630
MB90820 series
C.4
Indirect Addressing
In indirect addressing, the operand specifies indirectly the address of the data.
■ Indirect addressing
● Register indirect addressing (@RWj j = 0 to 3)
This type of addressing accesses memory at the address indicated by the contents of generalpurpose register RWj. Address bits 16 to 23 are specified by the DTB register if RW0 or RW1 is
used, by the system stack bank register (SSB) or user stack bank register (USB) if RW3 is used,
and by the additional data bank register (ADB) if RW2 is used. Figure C.4-1 shows an example
of register indirect addressing (@RWj, j= 0 to 3).
MOVW A, @RW1 (Instruction that reads data using register indirect
addressing and stores it in A)
Before execution
Memory space
After execution
Figure C.4-1 Example of register indirect addressing (@RWj j = 0 to 3)
● Register indirect addressing with post-incrementing (@RWj+ j = 0 to 3)
This type of addressing accesses memory at the address indicated by the contents of generalpurpose register RWj. After the operand has been operated on, register RWj is incremented by
the length of the operand data (one for byte length, two for word length, four for long-word
length). Address bits 16 to 23 are specified by the DTB register if RW0 or RW1 is used, by the
SSB or USB register if RW3 is used, and by the ADB register if RW2 is used.
Note that if the results of post-incrementing are the address of the same register that specified
the increment, the value to be referenced after incrementing will be the incremented value. Also,
if a write instruction is used, the write operation will have priority, so that the register that is
supposed to be incremented receives the write data. Figure C.4-2 shows an example of register
indirect addressing with post-incrementing (@RWj+, j = 0 to 3).
MOVW A, @RW1+ (Instruction that reads data by register indirect
addressing with post-incrementing and stores it in A)
Before execution
Memory space
After execution
Figure C.4-2 Example of register indirect addressing with post-incrementing (@RWj+ j = 0 to 3)
MB90820 series
631
● Register indirect addressing with displacement (@RWi+disp8 i = 0 to 7, @RWj+disp16 j =
0 to 3)
This type of addressing accesses memory at an address derived from the contents of the
general-purpose register RWj with a displacement added. Displacements may be either byte or
word length, and are added as signed numerical values. Address bits 16 to 23 are specified by
the DTB register if RW0, RW1, RW4, or RW5 is used, by the SSB or USB register if RW3 or
RW7 is used, and by the ADB register if RW2 or RW6 is used. Figure C.4-3 shows an example
of register indirect addressing with displacement (@RWi+disp8, i = 0 to 7; @RWj+disp16, j = 0
to 3).
MOVW A, @RW1+10H (Instruction that reads data by register indirect
addressing with displacement and stores it in A)
Before execution
Memory space
After execution
Figure C.4-3 Example of register indirect addressing with displacement (@RWi+disp8 i = 0 to 7,
@RWj+disp16 j = 0 to 3)
● Long-register indirect addressing with displacement (@RLi+disp8 i = 0 to 3)
This type of addressing accesses memory at an address derived by using the lower 24 bits of
the sum of the contents of general-purpose register RLi plus a displacement. The displacement
is 8 bits, and is added as a signed numerical value to the RLi contents. Figure C.4-4 shows an
example of long-register indirect addressing with displacement (@RLi+disp8, i = 0 to 3).
MOVW A, @RL2+25H (Instruction that reads data by long-word register indirect
addressing with displacement and stores it in a)
Before execution
Memory space
After execution
Figure C.4-4 Example of long-word register indirect addressing with displacement(@RLi+disp8 i = 0 to 3)
632
MB90820 series
● Program counter indirect addressing with displacement (@PC+disp16)
This type of addressing accesses memory at an address determined by the formula (instruction
address+4+disp16). The displacement is word-length data. Address bits 16 to 23 are specified
by the PCB register.
Note that the operand addresses of the following instructions are not considered to be (next
instruction address+disp16):
•
DBNZ eam,rel
•
DWBNZ eam,rel
•
CBNE eam,#imm8,rel
•
CWBNE eam,#imm16,rel
•
MOV
•
MOVW eam,#imm16
eam,#imm8
Figure C.4-5 shows an example of program counter indirect addressing with displacement
(@PC+disp16).
MOVW A, @PC+20H (Instruction that reads data with PC indirect addressing
with displacement and stores it in A)
Memory space
Before execution
After execution
Figure C.4-5 Example of program counter indirect addressing with displacement (@PC+disp16)
MB90820 series
633
● Register indirect addressing with base index (@RW0+RW7, @RW1+RW7)
This type of addressing accesses memory at an address determined by adding the contents of
general-purpose register RW7 to RW0 or RW1. Address bits 16 to 23 are specified by the DTB
register. Figure C.4-6 shows an example of register indirect addressing with a base index
(@RW0+RW7, @RW1+RW7).
MOVW A, @RW1+RW7 (Instruction that reads data by register indirect
addressing with base index and stores it in A)
Before execution
Memory space
After execution
Figure C.4-6 Example of register indirect addressing with base index (@RW0+RW7, @RW1+RW7)
● Program counter relative branch addressing (rel)
A branch destination address is represented as the program counter (PC) value plus an 8-bit
displacement. Because the bank register is not incremented or decremented and overflow is
ignored if the result is over 16 bits, the result is an address within the 64-kilobyte bank.
This addressing method is used for unconditional and conditional branch instructions. Address
bits 16 to 23 are specified by the PCB register. Figure C.4-7 shows an example of program
counter relative branch addressing (rel).
BRA 10H
(This instruction causes an unconditional relative branch.)
Before execution PC
After execution
PC
3C20
3C32
Memory space
PCB 4 F
PCB 4 F
4F3C32H
Next instruction
4F3C21H
4F3C20H
10
60
BRA 10H
Figure C.4-7 Example of program counter relative branch addressing (rel)
634
MB90820 series
● Register list (rlst)
This addressing method specifies registers that are used by push/pop instructions for stack
operations. Figure C.4-8 shows the register list configuration. Figure C.4-9 shows an example
of the register list (list).
Selected when the corresponding bit is set to 1 and not selected when it is set to 0.
Figure C.4-8 Register list configuration
POPW RW0, RW4 (Instruction that transfers data at the memory locations specified
by the SP to the word registers in the register list)
Memory space
Before execution
Memory space
After execution
Figure C.4-9 Example of register list (rlst)
● Accumulator indirect addressing (@A)
This addressing method accesses memory at the address indicated by the contents (16 bits) of
the lower bytes of the accumulator (AL). Address bits 16 to 23 are specified by the DTB register
as mnemonics. Figure C.4-10 shows an example of accumulator indirect addressing (@A).
MOVW A, @A (Instruction that reads data by accumulator indirect
addressing and stores it in A)
Before execution
Memory space
After execution
Figure C.4-10 Example of accumulator indirect addressing (@A)
MB90820 series
635
● Accumulator indirect branch addressing (@A)
The 16-bit contents of the lower bytes of the accumulator (AL) indicate the branch destination
address, which specifies a branch destination within the bank space. Address bits 16 to 23 are
specified by the PCB register. If the Jump Context (JCTX) instruction is used, address bits 16 to
23 are specified by the DTB register.
This addressing method is used for unconditional branching instructions. Figure C.4-11 shows
an example of accumulator indirect branch addressing (@A).
JMP @A (Unconditional branch instruction that uses accumulator indirect branch
addressing)
Before execution
After execution
Memory space
Next instruction
Figure C.4-11 Example of accumulator indirect branch addressing (@A)
● Indirect designation branch addressing (@ear)
In this type of addressing, the branch destination address is the word data at the address
specified by the ear parameter. Figure C.4-12 shows an example of indirect designation branch
addressing (@ear).
JMP @RW0 (Unconditional branch instruction that uses register indirect addressing)
Before execution
After execution
Figure C.4-12 Example of indirect designation branch addressing (@ear)
636
MB90820 series
● Indirect designation branch addressing (@eam)
In this type of addressing, the branch destination address is the word data at the address
specified by the eam parameter. Figure C.4-13 shows an example of indirect designation
branch addressing (@eam).
JMP @@RW0 (Unconditional branch instruction that uses register indirect addressing)
Before execution
After execution
Figure C.4-13 Example of indirect designation branch addressing (@eam)
MB90820 series
637
C.5
Number of Execution Cycles
The number of cycles required to execute an instruction is obtained by adding the
number of cycles for the instruction, the compensation value determined by
conditions, and the number of cycles for program fetch.
■ Number of execution cycles
The number of cycles required to execute an instruction is obtained by adding the number of
cycles for the instruction, the compensation value determined by conditions, and the number of
cycles for program fetch.
Because a program in memory connected to the 16-bit bus to the built-in ROM is fetched each
time an executing instruction exceeds the word boundary, the number of execution cycles
increases if data access is interfered with.
Because a program in memory connected to the 8-bit external data bus is fetched for each byte
of the instruction being executed, the number of execution cycles increases if data access is
interfered with.
If general-purpose registers, built-in ROM, built-in RAM, built-in I/O, and external data buses are
accessed during intermittent operation of the CPU, clocks supplied to the CPU stop for the
number of cycles specified by the CG0 and CG1 bits of the low-power consumption mode
control register. To calculate the number of cycles needed to execute an instruction during
intermittent operation of the CPU, add as a compensation value to the normal number of
execution cycles the product of the number of accesses and the number of cycles for the
temporary stop.
■ Calculation of the number of execution cycles
Table C.5-1 ~ Table C.5-3 list the number of execution cycles for each instruction and
compensation values.
Table C.5-1 Number of execution cycles for each type of addressing
(a) (*1)
Code
638
Operand
00
|
07
Ri
RWi
RLi
08
|
0B
Number of execution cycles for
type of addressing
Number of register
accesses for type of
addressing
Shown in instruction list.
Shown in instruction list.
@RWj
2
1
0C
|
0F
@RWj+
4
2
10
|
17
@RWj+disp8
2
1
MB90820 series
Table C.5-2 Number of execution cycles for each type of addressing (continued)
(a) (*1)
Number of register
accesses for type of
addressing
Code
Operand
18
|
1B
@RWi+disp16
2
1
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
Number of execution cycles for
type of addressing
*1 (a) is used for ~ (number of cycles) and B (compensation value) in Section C.7, "Reading the
Instruction List."
Table C.5-3 Compensation values for calculating the number of execution cycles
(b) byte (*1)
Operand
(c) word (*1)
(d) long-word (*1)
Number
of cycles
Number of
accesses
Number
of cycles
Number of
accesses
Number
of cycles
Number of
accesses
Internal register
+0
1
+0
1
+0
2
Internal memory,
even address
+0
1
+0
1
+0
2
Internal memory,
odd address
+0
1
+2
2
+4
4
External data bus
16-bit even address
+1
1
+1
1
+2
2
External data bus
16-bit odd address
+1
1
+4
2
+8
4
External data bus
(*2) 8 bits
+1
1
+4
2
+8
4
*1 (b), (c), and (d) are used for ~ (number of cycles) and B (compensation value) in Section
C.7, "Reading the Instruction List."
*2 When the external data bus is used, the number of cycles for waiting due to ready input and
automatic ready should be added.
Table C.5-4 Compensation values for calculating number of cycles for program fetch
Instruction
MB90820 series
Byte boundary
Word boundary
Internal memory
-
+2
External data bus 16 bits
-
+3
External data bus 8 bits
+3
-
639
<Cautions>
1. When the external data bus is used, the number of cycles for waiting due to ready input and
automatic ready should be added.
2
640
Not all program fetches delay instruction execution during actual operation. Use the
compensation values for calculating values for worst-case situations.
MB90820 series
C.6
Effective-address Field
Table C.6-1 lists the effective-address field for each code.
■ Effective-address field
Table C.6-1 Effective-address field
Code
00
01
02
03
04
05
06
07
Notation
R0
R1
R2
R3
R4
R5
R6
R7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
Address format
RL0
(RL0)
RL1
(RLL1)
RL2
(RL2)
RL3
(RL3)
Number of bytes in
address expansion
part (*1)
Register direct
ea corresponds to
byte,
word,
and long-word
formats in order from the left.
-
08
09
0A
0B
@RW0
@RW1
@RW2
@RW3
Register indirect
0
0C
0D
0E
0F
@RW0+
@RW1+
@RW2+
@RW3+
Register indirect with post-incrementing
0
10
11
12
13
14
15
16
17
@RW0+disp8
@RW1+disp8
@RW2+disp8
@RW3+disp8
@RW4+disp8
@RW5+disp8
@RW6+disp8
@RW7+disp8
Register indirect with 8-bit displacement
1
18
19
1A
1B
@RW0+disp16
@RW1+disp16
@RW2+disp16
@RW3+disp16
Register indirect with 16-bit displacement
2
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
0
0
2
2
*1 The number of bytes in the address expansion part is used for "+" in the # (number of bytes)
column in Section C.7, "Reading the Instruction List."
MB90820 series
641
C.7
Reading the Instruction List
This section explains the items (Table C.7-1 ) and codes (Table C.7-2 ) that appear in
Section C.7, "List of F2MC-16LX Instructions."
■ Explanation of items covered and instruction codes
Table C.7-1 Items covered in instruction list
Item
Mnemonic
Description
Uppercase alphabetic characters, symbols: Shown as they appear in assembler.
Lowercase alphabetic characters: Placeholders for assembler.
Numerics following lowercase alphabetic characters: Indicates the bit length of instructions.
#
Indicates the number of bytes.
~
Indicates the number of cycles.
For alphabetic characters in the items, see Table C.3-1 .
RG
B
Operation
Indicates the number of register accesses during instruction execution.
Used for calculating compensation values during intermittent operation of the CPU.
Indicates compensation values for calculating the actual number of cycles during instruction execution.
The actual number of cycles is the sum of the values in the → column.
Describes how the instruction operates.
LH
Indicates special operations with respect to accumulator bits 08 to 15.
Z: Transfers zero.
X: Transfers using sign extension.
-: No transfer
AH
Indicates special operations with respect to the upper 16 bits of the accumulator.
*: Transfers from AL to AH.
-: No transfer
Z: Transfers 00 H to AH.
X: Using AL sign extension, transfers 00H or FFH to AH.
I
S
T
N
Z
Indicates status of flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z
(zero), V (overflow), C (carry).
*: Changed as a result of instruction execution.
-: Not changed.
Z: Set by instruction execution.
X: Reset by instruction execution.
V
C
RMW
642
Indicates a read-modify-write instruction (one which reads data from memory and writes
the result in memory with the I instruction).
*: Read-modify-write instruction
-: Not a read-modify-write instruction
<Caution>
This type of instruction cannot be used with addresses with a different read/write
meaning.
MB90820 series
Table C.7-2 Symbols used in the instruction list (continued)
Symbol
A
32-bit accumulator
Length in bits varies with the instruction.
Byte: Lower 8 bits of AL
Word: 16 bits of AL
Long-word: 32 bits of AL and AH.
AH
AL
Upper 16 bits of A
Lower 16 bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
Ri
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
addr16
addr24
ad24 0-15
ad24 16-23
Condensed direct addressing
Direct addressing
Physical direct addressing
addr24 bits 0 to 15
addr24 bits 16 to 23
io
I/O area (000000H to 0000FFH)
#imm4
#imm8
#imm16
#imm32
ext (imm8)
4-bit immediate data
8-bit immediate data
16-bit immediate data
32-bit immediate data
16-bit immediate data extended to signed 8-bit data
disp8
disp16
bp
MB90820 series
Meaning
8-bit displacement
16-bit displacement
Bit offset value
643
Table C.7-3 Symbols used in the instruction list (continued)
Symbol
644
Meaning
vct4
vct8
Vector number (0 to 15)
Vector number (0 to 255)
( )b
Bit address
rel
ear
eam
PC relative branch addressing
Effective address designation (codes 00 to 07)
Effective address designation (codes 08 to 1F)
rist
Register list
MB90820 series
C.8
List of F²MC-16LX Instructions
Table C.8-1 to Table 14list instructions used by F2MC-16LX.
Table C.8-1 Transfer instructions (byte): 41 instructions
Mnemonic
#
~
RG
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVN
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,
dir
addr16
Ri
ear
eam
io
#imm8
@A
@RLi+disp8
#imm4
2
3
3
4
1
2
2
2
2+ 3+ (a)
2
3
2
2
2
3
3
10
1
1
0
0
1
1
0
0
0
0
2
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ← ((RLi)+disp8)
byte (A) ← imm4
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– *
– *
– *
– *
– *
– *
– *
– *
– *
– R
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
MOVX
A, dir
A, addr16
A, Ri
A, ear
A, eam
A, io
A, #imm8
A, @A
A,@RWi+disp8
A, @RLi+disp8
2
3
3
4
2
2
2
2
2+ 3+ (a)
2
3
2
2
2
3
2
5
3
10
0
0
1
1
0
0
0
0
1
2
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
byte (A) ← (dir)
byte (A) ← (addr16)
byte (A) ← (Ri)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← (io)
byte (A) ← imm8
byte (A) ← ((A))
byte (A) ←
((RWi)+disp8)
byte (A) ← ((RLi)+disp8)
X
X
X
X
X
X
X
X
X
X
*
*
*
*
*
*
*
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
/MOV
dir, A
addr16, A
Ri, A
ear, A
eam, A
io, A
@RLi+disp8, A
Ri, ear
Ri, eam
ear, Ri
eam, Ri
Ri, #imm8
io, #imm8
dir, #imm8
ear, #imm8
eam, #imm8
@AL, AH
@A, T
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
3
4
2
2
3+ (a)
3
10
3
4+ (a)
4
5+ (a)
2
5
5
2
4+ (a)
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
–
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2
3
0
(b)
–
–
–
–
–
*
*
–
–
–
XCH
XCH
XCH
XCH
A, ear
A, eam
Ri, ear
Ri, eam
2
4
2+ 5+ (a)
2
7
2+ 9+ (a)
byte (dir) ← (A)
byte (addr16) ← (A)
byte (Ri) ← (A)
byte (ear) ← (A)
byte (eam) ← (A)
byte (io) ← (A)
byte ((RLi) +disp8) ← (A)
byte (Ri) ← (ear)
byte (Ri) ← (eam)
byte (ear) ← (Ri)
byte (eam) ← (Ri)
byte (Ri) ← imm8
byte (io) ← imm8
byte (dir) ← imm8
byte (ear) ← imm8
byte (eam) ← imm8
byte ((A)) ← (AH)
0
Z – – – – – – – –
–
2× (b) byte (A) ↔ (ear)
Z – – – – – – – –
–
0
byte (A) ↔ (eam)
– – – – – – – – –
–
2× (b) byte (Ri) ↔ (ear)
– – – – – – – – –
–
byte (Ri) ↔ (eam)
<Caution>See Table C.5-1 , "Number of execution cycles for each type of addressing," and
Table C.5-2 , "Compensation values for calculating the number of execution cycles,"
for (a) to (d) in the above table.
MB90820 series
2
0
4
2
645
Table C.8-2 Transfer instructions (word, long-word): 38 instructions
Mnemonic
#
~
RG
B
A, dir
A, addr16
A, SP
A, RWi
A, ear
A, eam
A, io
A, @A
A, #imm16
A, @RWi+disp8
A, @RLi+disp8
2
3
1
1
2
2+
2
2
3
2
3
3
4
1
2
2
3+ (a)
3
3
2
5
10
0
0
0
1
1
0
0
0
0
1
2
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
word
word
word
word
word
word
word
word
word
(A) ← (dir)
(A) ← (addr16)
(A) ← (SP)
(A) ← (RWi)
(A) ← (ear)
(A) ← (eam)
(A) ← (io)
(A) ← ((A))
(A) ← imm16
–
–
–
–
–
–
–
–
–
word (A) ← ((RWi) +disp8) –
word (A) ← ((RLi) +disp8) –
MOVW dir, A
MOVW addr16, A
MOVW SP, A
MOVW RWi, A
MOVW ear, A
MOVW eam, A
MOVW io, A
MOVW @RWi+disp8, A
MOVW @RLi+disp8, A
MOVW RWi, ear
MOVW RWi, eam
MOVW ear, RWi
MOVW eam, RWi
MOVW RWi, #imm16
MOVW io, #imm16
MOVW ear, #imm16
MOVW eam, #imm16
MOVW @AL, AH
/MOVW@A, T
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
3
4
1
2
2
3+ (a)
3
5
10
3
4+ (a)
4
5+ (a)
2
5
2
4+ (a)
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
(0)
(c)
0
(c)
0
(c)
0
(c)
word (dir) ← (A)
word (addr16) ← (A)
word (SP) ← (A)
word (RWi) ← (A)
word (ear) ← (A)
word (eam) ← (A)
word (io) ← (A)
2
3
0
(c)
XCHW
XCHW
XCHW
XCHW
2
2+
2
2+
4
5+ (a)
7
9+ (a)
2
0
4
2
0
2× (c)
0
2× (c)
MOVL A, ear
MOVL A, eam
MOVL A, #imm32
2
2+
5
4
5+ (a)
3
2
0
0
0
(d)
0
MOVL ear, A
MOVL eam, A
2
2+
4
5+ (a)
2
0
0
(d)
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
A, ear
A, eam
RWi, ear
RWi, eam
Operation
I
S
T
N
Z
V
C
RMW
*
*
*
*
*
*
*
–
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word ((RWi) +disp8) ← (A) –
word ((RLi) +disp8) ← (A) –
word (RWi) ← (ear)
–
word (RWi) ← (eam)
–
word (ear) ← (RWi)
–
word (eam) ← (RWi)
–
word (RWi) ← imm16
–
word (io) ← imm16
–
word (ear) ← imm16
–
word (eam) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word ((A)) ← (AH)
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
long (A) ← (ear)
long (A) ← (eam)
long (A) ← imm32
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
long (ear) ← (A)
long (eam) ← (A)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
–
–
–
–
–
–
word
word
word
word
(A) ↔ (ear)
(A) ↔ (eam)
(RWi) ↔ (ear)
(RWi) ↔ (eam)
LH AH
<Caution> See Table C.5-1 , "Number of execution cycles for each type of addressing," and Table C.5-2 ,
"Compensation values for calculating the number of execution cycles," for (a) to (d) in the above
table.
646
MB90820 series
Table C.8-3 Addition/subtraction (byte, word, long-word): 42 instructions
Mnemonic
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
A, #imm8
A, dir
A, ear
A, eam
ear, A
eam, A
A
A, ear
A, eam
A
ADDW A
ADDW A, ear
ADDW A, eam
ADDW A, #imm16
ADDW ear, A
ADDW eam, A
ADDCW A, ear
ADDCW A, eam
SUBW A
SUBW A, ear
SUBW A, eam
SUBW A, #imm16
SUBW ear, A
SUBW eam, A
SUBCW A, ear
SUBCW A, eam
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
2
2
2
2+
2
2+
1
2
2+
1
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
2
5
3
4+ (a)
3
5+ (a)
2
3
4+ (a)
3
0
0
1
0
2
0
0
1
0
0
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2× (b)
0
0
(b)
0
0
(b)
0
(b)
0
2× (b)
0
0
(b)
0
byte (A) ← (A) +imm8
byte (A) ← (A) +(dir)
byte (A) ← (A) +(ear)
byte (A) ← (A) +(eam)
byte (ear) ← (ear) + (A)
byte (eam) ← (eam) + (A)
byte (A) ← (AH) + (AL) + (C)
byte (A) ← (A) + (ear) + (C)
byte (A) ← (A) + (eam) + (C)
Z
Z
Z
Z
–
Z
Z
Z
Z
Z
Z
Z
Z
Z
–
–
Z
Z
Z
Z
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
–
–
*
–
–
–
–
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
2
3
4+ (a)
2
3
5+ (a)
3
4+ (a)
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
0
0
(c)
0
0
2× (c)
0
(c)
0
0
(c)
0
0
2× (c)
0
(c)
word (A) ← (AH) + (AL)
word (A) ← (A) +(ear)
word (A) ← (A) +(eam)
word (A) ← (A) +imm16
word (ear) ← (ear) + (A)
word (eam) ← (eam) + (A)
word (A) ← (A) + (ear) + (C)
word (A) ← (A) + (eam) +
(C)
word (A) ← (AH) – (AL)
word (A) ← (A) – (ear)
word (A) ← (A) – (eam)
word (A) ← (A) –imm16
word (ear) ← (ear) – (A)
word (eam) ← (eam) – (A)
word (A) ← (A) – (ear) – (C)
word (A) ← (A) – (eam) – (C)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
*
–
–
–
–
–
–
–
*
–
–
byte (A) ← (AH) + (AL) + (C) (decimal)
byte (A) ← (A) –imm8
byte (A) ← (A) – (dir)
byte (A) ← (A) – (ear)
byte (A) ← (A) – (eam)
byte (ear) ← (ear) – (A)
byte (eam) ← (eam) – (A)
byte (A) ← (AH) – (AL) – (C)
byte (A) ← (A) – (ear) – (C)
byte (A) ← (A) – (eam) – (C)
byte (A) ← (AH) – (AL) – (C) (decimal)
A, ear
2
6
2
0
long (A) ← (A) + (ear)
– – – – – * * * *
–
A, eam
2+ 7+ (a) 0
(d) long (A) ← (A) + (eam)
– – – – – * * * *
–
A, #imm32 5
4
0
0
long (A) ← (A) +imm32
– – – – – * * * *
–
A, ear
2
6
2
0
long (A) ← (A) – (ear)
– – – – – * * * *
–
A, eam
2+ 7+ (a) 0
(d) long (A) ← (A) – (eam)
– – – – – * * * *
–
A, #imm32 5
4
0
0
long (A) ← (A) –imm32
– – – – – * * * *
–
<Caution>See Table C.5-1 , "Number of execution cycles for each type of addressing," and
Table C.5-2 , "Compensation values for calculating the number of execution cycles,"
for (a) to (d) in the above table.
MB90820 series
647
Table C.8-4 Increment/decrement (byte, word, long-word): 12 instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
INC
INC
ear
eam
2
2+
2
5+ (a)
2
0
0
byte (ear) ← (ear) +1
2× (b) byte (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DEC
DEC
ear
eam
2
2+
3
5+ (a)
2
0
0
byte (ear) ← (ear) –1
2× (b) byte (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCW
INCW
ear
eam
2
2+
3
5+ (a)
2
0
0
word (ear) ← (ear) +1
2× (c) word (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECW ear
DECW eam
2
2+
3
5+ (a)
2
0
0
word (ear) ← (ear) –1
2× (c) word (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
INCL
INCL
ear
eam
2
2+
7
9+ (a)
4
0
0
long (ear) ← (ear) +1
2× (d) long (eam) ← (eam) +1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
DECL
DECL
ear
eam
2
2+
7
9+ (a)
4
0
0
long (ear) ← (ear) –1
2× (d) long (eam) ← (eam) –1
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
*
<Caution> See Table C.5-1 , "Number of execution cycles for each type of addressing," and Table C.5-2 ,
"Compensation values for calculating the number of execution cycles," for (a) to (d) in the above
table.
Table C.8-5 Comparison (byte, word, long-word): 11 instructions]
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
CMP
CMP
CMP
CMP
A
A, ear
A, eam
A, #imm8
1
2
2+
2
1
2
3+ (a)
2
0
1
0
0
0
0
(b)
0
byte (AH) – (AL)
byte (A) ← (ear)
byte (A) ← (eam)
byte (A) ← imm8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPW
CMPW
CMPW
CMPW
A
A, ear
A, eam
A, #imm16
1
2
2+
3
1
2
3+ (a)
2
0
1
0
0
0
0
(c)
0
word (AH) – (AL)
word (A) ← (ear)
word (A) ← (eam)
word (A) ← imm16
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
CMPL
CMPL
CMPL
A, ear
2
6
2
0
word (A) ← (ear)
– – – – – * * * *
–
A, eam
2+ 7+ (a) 0
(d) word (A) ← (eam)
– – – – – * * * *
–
A, #imm32 5
3
0
0
word (A) ← imm32
– – – – – * * * *
–
<Caution>See Table C.5-1 , "Number of execution cycles for each type of addressing," and
Table C.5-2 , "Compensation values for calculating the number of execution cycles,"
for (a) to (d) in the above table.
648
MB90820 series
Table C.8-6 Unsigned multiplication/division (word, long-word): 11 instructions]
Mnemonic
#
~ RG B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
DIVU
A
1
*1
0
0 word (AH) /byte (AL)
–
–
–
–
–
–
–
*
*
–
DIVU
A, ear
2
*2
1
0 word (A)/byte (ear)
–
–
–
–
–
–
–
*
*
–
DIVU
A, eam 2+ *3
0
*6 word (A)/byte (eam)
–
–
–
–
–
–
–
*
*
–
*4
1
0 long (A)/word (ear)
–
–
–
–
–
–
–
*
*
–
DIVUW A, eam 2+ *5
0
*7 long (A)/word (eam)
–
–
–
–
–
–
–
*
*
–
MULU
MULU
MULU
0 0 byte (AH) *byte (AL) → word (A)
1 0 byte (A) *byte (ear) → word (A)
0 (b) byte (A) *byte (eam) → word (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
MULUW A
1 *11 0 0 word (AH) *word (AL) → long (A)
MULUW A, ear
2 *12 1 0 word (A) *word (ear) → long (A)
MULUW A, eam 2+ *13 0 (c) word (A) *word (eam) → long (A)
*13 for division by zero, 7 for overflow, normally 15
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DIVUW A, ear
2
A
1 *8
A, ear
2 *9
A, eam 2+ *10
Quotient → byte (AL) Remainder → byte (AH)
Quotient → byte (A) Remainder → byte (ear)
Quotient → byte (A) Remainder → byte (eam)
Quotient → word (A) Remainder → word (ear)
Quotient → word (A) Remainder → word (ear)
*2
4 for division by zero, 8 for overflow, normally 16
*3
6 + (a) for division by zero, 9 + (a) for overflow, normally 19 + (a)
*4
4 for division by zero, 7 for overflow, normally 22
*5
6 + (a) for division by zero, 8 + (a) for overflow, normally 26 + (a)
*6
(b) for division by zero or overflow, normally 2 x (b)
*7
(c) for division by zero or overflow, normally 2 x (c)
*8
3 when byte(AH) is zero, 7 otherwise
*9
4 when byte(ear) is zero, 8 otherwise
*10
5 + (a) when byte(eam) is zero, 9 + (a) otherwise
*11
3 when word(AH) is zero, 11 otherwise
*12
4 when word(ear) is zero, 12 otherwise
*13
5 + (a) when word(eam) is zero, 13 + (a) otherwise
<Caution>
MB90820 series
See Table C.5-1 , "Number of execution cycles for each type of addressing," and Table C.52 , "Compensation values for calculating the number of execution cycles," for (a) to (d) in the
above table.
649
Table C.8-7 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11
Instructions]
LH AH
I
S
T
N
Z
V
C RMW
Mnemonic
#
~ RG B
Operation
DIV
A
2
*1
0
DIV
A, ear
2
*2
1
DIV
A, eam 2 +
*3
0
DIVW
A, ear
2
*4
1
DIVW
A, eam
2+
*5
0
MULU
MULU
MULU
MULUW
MULUW
MULUW
A
2
A, ear
2
A, eam 2 +
A
2
A, ear
2
A, eam 2 +
*8
*9
*10
*11
*12
*13
0
1
0
0
1
0
0
word (AH) /byte (AL)
Quotient → byte (AL)
Remainder → byte (AH)
0 word (A)/byte (ear)
Quotient → byte (A)
Remainder → byte (ear)
*6 word (A)/byte (eam)
Quotient → byte (A)
Remainder → byte (eam)
0 long (A)/word (ear)
Quotient → word (A)
Remainder → word (ear)
*7 long (A)/word (eam)
Quotient → word (A)
Remainder → word (eam)
0
0
(b)
0
0
(c)
byte (AH) *byte (AL) → word (A)
byte (A) *byte (ear) → word (A)
byte (A) *byte (eam) → word (A)
word (AH) *word (AL) → long (A)
word (A) *word (ear) → long (A)
word (A) *word (eam) → long (A)
Z
–
–
–
–
–
–
*
*
–
Z
–
–
–
–
–
–
*
*
–
Z
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*1:
*2:
*3:
*4:
Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation.
Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation.
Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation.
Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation.
Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation.
*5: Positive dividend:Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for
normal operation.
Negative dividend: Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for
normal operation.
*6: When the division-by-0, (b) for an overflow, and 2 × (b) for normal operation.
*7: When the division-by-0, (c) for an overflow, and 2 × (c) for normal operation.
*8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative.
*10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is
negative.
*11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative.
*12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative.
*13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is
negative.
Notes: • When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes
two values because of detection before and after an operation.
• When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed.
• For (a) to (d), refer to “Table 4 Number of Execution Cycles for Effective Address in Addressing Modes”
and “Table 6 Correction Values for Number of Cycles for Calculating Actual Number of Cycles.”
650
MB90820 series
Table C.8-8 Logical 1 (byte, word): 39 instructions]
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
AND
AND
AND
AND
AND
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
1
0
2
0
0
0
(b)
0
2× (b)
byte (A) ← (A) and imm8
byte (A) ← (A) and (ear)
byte (A) ← (A) and (eam)
byte (ear) ← (ear) and (A)
byte (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
OR
OR
OR
OR
OR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
1
0
2
0
0
0
(b)
0
2× (b)
byte (A) ← (A) or imm8
byte (A) ← (A) or (ear)
byte (A) ← (A) or (eam)
byte (ear) ← (ear) or (A)
byte (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
XOR
XOR
XOR
XOR
XOR
A, #imm8
A, ear
A, eam
ear, A
eam, A
2
2
2
3
2+ 4+ (a)
2
3
2+ 5+ (a)
0
1
0
2
0
0
0
(b)
0
2× (b)
byte (A) ← (A) xor imm8
byte (A) ← (A) xor (ear)
byte (A) ← (A) xor (eam)
byte (ear) ← (ear) xor (A)
byte (eam) ← (eam) xor (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
–
–
–
–
–
–
–
–
–
*
NOT
NOT
NOT
A
ear
eam
1
2
2
3
2+ 5+ (a)
0
2
0
0
byte (A) ← not (A)
0
byte (ear) ← not (ear)
2× (b) byte (eam) ← not (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
R
R
R
–
–
–
–
–
*
ANDW
ANDW
ANDW
ANDW
ANDW
ANDW
A
1
2
A, #imm16 3
2
A, ear
2
3
A, eam
2+ 4+ (a)
ear, A
2
3
eam, A
2+ 5+ (a)
0
0
1
0
2
0
0
0
0
(c)
0
2× (c)
word (A) ← (AH) and (A)
word (A) ← (A) and imm16
word (A) ← (A) and (ear)
word (A) ← (A) and (eam)
word (ear) ← (ear) and (A)
word (eam) ← (eam) and (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
ORW
ORW
ORW
ORW
ORW
ORW
A
1
2
A, #imm16 3
2
A, ear
2
3
A, eam
2+ 4+ (a)
ear, A
2
3
eam, A
2+ 5+ (a)
0
0
1
0
2
0
0
0
0
(c)
0
2× (c)
word (A) ← (AH) or (A)
word (A) ← (A) or imm16
word (A) ← (A) or (ear)
word (A) ← (A) or (eam)
word (ear) ← (ear) or (A)
word (eam) ← (eam) or (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
XORW
XORW
XORW
XORW
XORW
XORW
A
1
2
A, #imm16 3
2
A, ear
2
3
A, eam
2+ 4+ (a)
ear, A
2
3
eam, A
2+ 5+ (a)
0
0
1
0
2
0
0
0
0
(c)
0
2× (c)
word (A) ← (AH) xor (A)
word (A) ← (A) xor imm16
word (A) ← (A) xor (ear)
word (A) ← (A) xor (eam)
word (ear) ← (ear) xor (A)
word (eam) ← (eam) xor (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
R
R
R
R
R
R
–
–
–
–
–
–
–
–
–
–
–
*
NOTW A
NOTW ear
NOTW eam
1
2
0
0
word (A) ← not (A)
– – – – – * * R – –
2
3
2
0
word (ear) ← not (ear)
– – – – – * * R – –
2+ 5+ (a) 0 2× (c) word (eam) ← not (eam)
– – – – – * * R –
*
<Caution>See Table C.5-1 , "Number of execution cycles for each type of addressing," and
Table C.5-2 , "Compensation values for calculating the number of execution cycles,"
for (a) to (d) in the above table.
MB90820 series
651
Table C.8-9 Logical 2 (long-word): 6 instructions]
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
ANDL A, ear
ANDL A, eam
2
2+
6
7+ (a)
2
0
0
(d)
long (A) ← (A) and (ear)
long (A) ← (A) and (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
ORL
ORL
2
2+
6
7+ (a)
2
0
0
(d)
long (A) ← (A) or (ear)
long (A) ← (A) or (eam)
–
–
–
–
–
–
–
–
–
–
*
*
*
*
R
R
–
–
–
–
A, ear
A, eam
XORL A, ea
2
6
2
0
long (A) ← (A) xor (ear)
– – – – – * * R –
–
XORL A, eam
2+ 7+ (a) 0
(d) long (A) ← (A) xor (eam) – – – – – * * R –
–
<Caution>See Table C.5-1 , "Number of execution cycles for each type of addressing," and
Table C.5-2 , "Compensation values for calculating the number of execution cycles,"
for (a) to (d) in the above table.
Table C.8-10 Sign inversion (byte, word): 6 instructions
Mnemonic
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
2
0
0
byte (A) ← 0 – (A)
X
–
–
–
–
*
*
*
*
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
*
–
–
–
–
–
*
*
*
*
–
NEG
A
1
NEG
NEG
ear
eam
2
3
2+ 5+ (a)
2
0
1
0
NEGW A
NEGW ear
NEGW eam
2
0
byte (ear) ← 0 – (ear)
2× (b) byte (eam) ← 0 – (eam)
0
word (A) ← 0 – (A)
2
3
2
0
word (ear) ← 0 – (ear)
– – – – – * * * *
–
2+ 5+ (a) 0 2× (c) word (eam) ← 0 – (eam) – – – – – * * * *
*
<Caution>See Table C.5-1 , "Number of execution cycles for each type of addressing," and
Table C.5-2 , "Compensation values for calculating the number of execution cycles,"
for (a) to (d) in the above table.
Table C.8-11 Normalization (long-word): 1 instruction]
Mnemonic
NRML A, R0
#
~
*
<Caution>
652
RG
B
Operation
LH
long (A) ← Shift until first digit is “1” –
byte (R0) ← Current shift count
*1 4 when all accumulators indicate 0, 6 + (R0) otherwise
2
1
1
0
AH
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
*
–
–
–
See Table C.5-1 , "Number of execution cycles for each type of addressing," and Table C.52 , "Compensation values for calculating the number of execution cycles," for (a) to (d) in the
above table.
MB90820 series
Table C.8-12 Shift instructions (byte, word, long-word): 18 instructions]
Mnemonic
RORC A
ROLC A
RORC ear
RORC eam
ROLC ear
ROLC eam
#
~
RG
B
2
2
2
2
0
0
0
0
2
3
2+ 5+ (a)
2
3
2+ 5+ (a)
Operation
LH AH
I
S
T
N
Z
V
C
RMW
byte (A) ← Right rotation with carry
byte (A) ← Left rotation with carry
–
–
–
–
– –
– –
–
–
*
*
*
*
–
–
*
*
–
–
2
0
0 2× (b)
2
0
0 2× (b)
byte (ear) ← Right rotation with carry
byte (eam) ← Right rotation with carry
byte (ear) ← Left rotation with carry
byte (eam) ← Left rotation with carry
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
–
–
*
*
*
*
–
*
–
*
2
2
2
*1
*1
*1
1
1
1
0
0
0
byte (A) ← Arithmetic right barrel shift (A, R0)
byte (A) ← Logical right barrel shift (A, R0)
byte (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
– –
– –
– –
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRW A
LSRW A/SHRW A
LSLW A/SHLW A
1
1
1
2
2
2
0
0
0
0
0
0
word (A) ← Arithmetic right shift (A, 1 bit)
–
–
–
–
–
–
– –
– –
– –
* *
* R
– *
*
*
*
–
–
–
*
*
*
–
–
–
ASRW A, R0
LSRW A, R0
LSLW A, R0
2
2
2
*1
*1
*1
1
1
1
0
0
0
word (A) ← Arithmetic right barrel shift (A,
R0)
word (A) ← Logical right barrel shift (A, R0)
word (A) ← Logical left barrel shift (A, R0)
–
–
–
–
–
–
– –
– –
– –
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASRL A, R0
LSRL A, R0
LSLL A, R0
2
2
2
*2
*2
*2
1
1
1
0
0
0
long (A) ← Arithmetic right shift (A, R0) –
–
–
–
– –
– –
– –
*
*
–
*
*
*
*
*
*
–
–
–
*
*
*
–
–
–
ASR
LSR
LSL
A, R0
A, R0
A, R0
word (A) ← Logical right shift (A, 1 bit)
word (A) ← Logical left shift (A, 1 bit)
long (A) ← Logical right barrel shift (A, R0)
long (A) ← Logical left barrel shift (A, R0)
–
–
*1 6 when R0 is zero, 5 + (R0) otherwise
*2 6 when R0 is zero, 6 + (R0) otherwise
<Caution>
MB90820 series
See Table C.5-1 , "Number of execution cycles for each type of addressing," and Table C.52 , "Compensation values for calculating the number of execution cycles," for (a) to (d) in the
above table.
653
Table C.8-13 Branching instructions (1): 31 instructions
Mnemonic
BZ/BEQ
BNZ/BNE
BC/BLO
BNC/BHS
BN
rel
BP
rel
BV
rel
BNV
rel
BT
rel
BNT
rel
BLT
rel
BGE
rel
BLE
rel
BGT
rel
BLS
rel
BHI
rel
BRA
rel
JMP
JMP
JMP
JMP
JMPP
JMPP
JMPP
rel
rel
rel
rel
@A
addr16
@ear
@eam
@ear *3
@eam *3
addr24
#
~
RG
B
Operation
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Branch when (Z) = 1
Branch when (Z) = 0
Branch when (C) = 1
Branch when (C) = 0
Branch when (N) = 1
Branch when (N) = 0
Branch when (V) = 1
Branch when (V) = 0
Branch when (T) = 1
Branch when (T) = 0
Branch when (V) xor (N) = 1
Branch when (V) xor (N) = 0
1
3
2
2+
2
2+
4
2
3
3
4+ (a)
5
6+ (a)
4
0
0
1
0
2
0
0
0
0
0
(c)
0
(d)
0
AH
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
–
–
–
–
–
–
Branch when ((V) xor (N)) or (Z) = 1 –
Branch when ((V) xor (N)) or (Z) = 0 –
Branch when (C) or (Z) = 1
–
Branch when (C) or (Z) = 0
–
Branch unconditionally
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
← (A)
← addr16
← (ear)
← (eam)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (PC)
word (PC)
word (PC)
word (PC)
LH
–
–
–
–
word (PC) ← (ear), (PCB) ← (ear +2) –
word (PC) ← (eam), (PCB) ← (eam +2) –
word (PC) ← ad24 0 to 15,
–
(PCB) ← ad24 16 to 23
2
6
1
(c) word (PC) ← (ear)
–
CALL @ear *4
–
CALL @eam *4 2+ 7+ (a) 0 2× (c) word (PC) ← (eam)
6
0
(c) word (PC) ← addr16
–
CALL addr16 *5 3
1
7
0 2× (c) Vector call instruction
–
CALLV #vct4 *5
2
10
2 2× (c) word (PC) ← (ear) 0 to 15,
–
CALLP @ear *6
(PCB) ← (ear) 16 to 23
word (PC) ← (eam) 0 to 15, –
*2
CALLP @eam *6 2+ 11+ (a) 0
(PCB) ← (eam) 16 to 23
10
0 2× (c) word (PC) ← addr0 to 15,
–
CALLP addr24 *7 4
(PCB) ← addr16 to 23
*1 4 when branching occurs, 3 otherwise
*2 3 x (c) + (b)
*3 Reads a branch destination address (word).
*4 Write: Saves to stack (word), Read: Reads a branch destination address (word).
*5 Saves to stack (word).
*6 Write: Saves to stack (long-word), Read: Reads a branch destination address (long-word).
*7 Saves to stack (long-word).
<Caution> See Table C.5-1 , "Number of execution cycles for each type of addressing," and
Table C.5-2 , "Compensation values for calculating the number of execution cycles,"
for (a) to (d) in the above table.
654
MB90820 series
Table C.8-14 Branch instructions (2): 19 instructions
Mnemonic
CBNE A, #imm8, rel
CWBNE A, #imm16, rel
CBNE
CBNE
ear, #imm8, rel
eam, #imm8, rel*
10
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel*10
#
~
RG
B
Operation
3
4
*1
*1
0
0
0
0
Branch when byte (A) ≠ imm8
Branch when word (A) ≠ imm16
4
4+
5
5+
*2
*3
*4
*3
1
0
1
0
0
(b)
0
(c)
Branch when byte (ear) ≠ imm8
Branch when byte (eam) ≠ imm8
Branch when word (ear) ≠ imm16
Branch when word (eam) ≠ imm16
0
N
Z
V
C
RMW
–
–
– – – – *
– – – – *
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
–
–
–
– – – – *
*
* –
–
–
– – – – *
*
* –
*
Branch when word (ear) =
(ear) – 1, and (ear) ≠ 0
2× (c) Branch when word (eam) =
(eam) – 1, and (eam) ≠ 0
–
– – – – *
*
* –
–
–
– – – – *
*
* –
*
Software interrupt
Software interrupt
Software interrupt
Software interrupt
Return from interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
–
–
–
–
*
–
–
–
–
*
–
–
–
–
–
At constant entry, save old
frame pointer to stack, set
new frame pointer, and
allocate local pointer area
At constant entry, retrieve old
frame pointer from stack.
–
– – – – – – – –
–
–
– – – – – – – –
–
Return from subroutine
Return from subroutine
–
–
– – – – – – – –
– – – – – – – –
–
–
DBNZ
ear, rel
3
*5
2
DBNZ
eam, rel
3+
*6
2
DWBNZ ear, rel
3
*5
2
DWBNZ eam, rel
3+
*6
2
INT
INT
INTP
INT9
RETI
#vct8
addr16
addr24
2
3
4
1
1
20
16
17
20
15
0
0
0
0
0
8× (c)
6× (c)
6× (c)
8× (c)
*7
LINK
#local8
2
6
0
(c)
UNLINK
1
5
0
(c)
RET *8
RETP *9
1
1
4
6
0
0
(c)
(d)
Branch when byte (ear) =
(ear) – 1, and (ear) ≠ 0
2× (b) Branch when byte (eam) =
(eam) – 1, and (eam) ≠ 0
0
LH AH
I
–
–
–
–
R
R
R
R
*
S
–
–
–
–
S
S
S
S
*
T
–
–
–
–
–
–
–
–
*
–
–
–
–
*
*1 5 when branching occurs, 4 otherwise
*2 13 when branching occurs, 12 otherwise
*3 7 + (a) when branching occurs, 6 + (a) otherwise
*4 8 when branching occurs, 7 otherwise
*5 7 when branching occurs, 6 otherwise
*6 8 + (a) when branching occurs, 7 + (a) otherwise
*7 Returns from stack (word)
*8 Returns from stack (long-word)
*9 Do not use the RWj + addressing mode for a CBNE/CWBNE instruction.
<Caution>
MB90820 series
See Table C.5-1 , "Number of execution cycles for each type of addressing," and Table C.52 , "Compensation values for calculating the number of execution cycles," for (a) to (d) in the
above table.
655
Table C.8-15 Other control instructions (byte, word, long-word): 28 instructions
Mnemonic
#
~
RG
B
Operation
PUSHW A
PUSHW AH
PUSHW PS
PUSHW rlst
1
1
1
2
4
4
4
*3
0
0
0
*5
(c)
(c)
(c)
*4
POPW
POPW
POPW
POPW
A
AH
PS
rlst
1
1
1
2
3
3
4
*2
0
0
0
*5
(c)
(c)
(c)
*4
JCTX
@A
1
14
0
AND CCR, #imm8
OR CCR, #imm8
2
2
3
3
0
0
MOV RP, #imm8
MOV ILM, #imm8
2
2
2
2
LH AH
I
S
T
N
Z
V
C
RMW
word (SP) ← (SP) –2, ((SP)) ← (A)
word (SP) ← (SP) –2, ((SP)) ← (AH)
word (SP) ← (SP) –2, ((SP)) ← (PS)
(SP) ← (SP) –2n, ((SP)) ← (rlst)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
word (A) ← ((SP)), (SP) ← (SP) +2
word (AH) ← ((SP)), (SP) ← (SP) +2
word (PS) ← ((SP)), (SP) ← (SP) +2
(rlst) ← ((SP)), (SP) ← (SP) +2n
–
–
–
–
*
–
–
–
– – – – – – –
– – – – – – –
* * * * * * *
– – – – – – –
–
–
–
–
–
–
*
*
*
*
*
*
*
–
0
0
byte (CCR) ← (CCR) and imm8 –
byte (CCR) ← (CCR) or imm8
–
–
–
*
*
*
*
*
*
*
*
*
*
*
*
*
*
–
–
0
0
0
0
byte (RP) ←imm8
byte (ILM) ←imm8
–
–
–
–
– – – – – – –
– – – – – – –
–
–
MOVEA RWi, ear
2
3
MOVEA RWi, eam 2+ 2+ (a)
MOVEA A, ear
2
1
MOVEA A, eam
2+ 1+ (a)
1
1
0
0
0
0
0
0
word (RWi) ←ear
word (RWi) ←eam
word(A) ←ear
word (A) ←eam
–
–
–
–
–
–
*
*
–
–
–
–
–
–
–
–
–
–
–
–
ADDSP #imm8
ADDSP #imm16
2
3
3
3
0
0
0
0
word (SP) ← (SP) +ext (imm8)
word (SP) ← (SP) +imm16
–
–
–
–
– – – – – – –
– – – – – – –
–
–
MOV
MOV
2
2
*1
1
0
0
0
0
byte (A) ← (brgl)
byte (brg2) ← (A)
Z
–
*
–
– – –
– – –
*
*
*
*
– –
– –
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
NOP
ADB
DTB
PCB
SPB
NCC
CMR
A, brgl
brg2, A
6× (c) Context switch instruction
1
1
1
1
1
1
1
No operation
0
0
1
Prefix code for accessing AD space
0
0
1
Prefix code for accessing DT space
0
0
1
Prefix code for accessing PC space
0
0
1
Prefix code for accessing SP space
0
0
1
Prefix code for no flag change
0
0
1
Prefix code for common register bank
0
0
1
*1PCB,ADB,SSB,USB ------------1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DTB,DPR --------------------------2
*2 7 + 3 x (pop count) + 2 x (last register number popped), 7 when RLST = 0 (no transfer
register)
*3 29 + 3 x (push count) - 3 x (last register number pushed), 8 when RLST = 0 (no transfer
register)
*4 (Pop count) x (c) or (push count) x (c)
<Caution> See Table C.5-1 , "Number of execution cycles for each type of addressing," and
Table C.5-2 , "Compensation values for calculating the number of execution cycles,"
for (a) to (d) in the above table.
656
MB90820 series
Table C.8-16 Bit operation instructions: 21 instructions
Mnemonic
#
~
RG
B
MOVB A, dir:bp
MOVB A, addr16:bp
MOVB A, io:bp
3
4
3
5
5
4
0
0
0
(b)
(b)
(b)
MOVB dir:bp, A
MOVB addr16:bp, A
MOVB io:bp, A
3
4
3
7
7
6
0
0
0
SETB dir:bp
SETB addr16:bp
SETB io:bp
3
4
3
7
7
7
CLRB dir:bp
CLRB addr16:bp
CLRB io:bp
3
4
3
BBC
BBC
BBC
dir:bp, rel
addr16:bp, rel
io:bp, rel
BBS
BBS
BBS
Operation
LH AH
I
S
T
N
Z
V
C
RMW
Z
Z
Z
*
*
*
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
–
–
–
2× (b) bit (dir:bp) b ← (A)
2× (b) bit (addr16:bp) b ← (A)
2× (b) bit (io:bp) b ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
–
–
–
–
–
–
*
*
*
0
0
0
2× (b) bit (dir:bp) b ← 1
2× (b) bit (addr16:bp) b ← 1
2× (b) bit (io:bp) b ← 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
7
7
7
0
0
0
2× (b) bit (dir:bp) b ← 0
2× (b) bit (addr16:bp) b ← 0
2× (b) bit (io:bp) b ← 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 0
Branch when (addr16:bp) b = 0
Branch when (io:bp) b = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
dir:bp, rel
addr16:bp, rel
io:bp, rel
4
5
4
*1
*1
*2
0
0
0
(b)
(b)
(b)
Branch when (dir:bp) b = 1
Branch when (addr16:bp) b = 1
Branch when (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
–
–
–
–
–
–
–
–
–
SBBS addr16:bp, rel
5
*3
0
2× (b) Branch when (addr16:bp) b = 1, bit = 1 –
–
–
–
–
–
*
–
–
*
WBTS io:bp
3
*4
0
WBTC io:bp
3
*4
0
byte (A) ← (dir:bp) b
byte (A) ← (addr16:bp) b
byte (A) ← (io:bp) b
Wait until (io:bp) b = 1
–
–
–
–
–
–
–
–
–
–
Wait until (io:bp) b = 0
*5
*1 8 when branching occurs, 7 otherwise
–
–
–
–
–
–
–
–
–
–
V
C
RMW
*5
*2 7 when branching occurs, 6 otherwise
*3 10 when conditions are met, 9 otherwise
*4 Undefined number of cycles
*5 Until conditions are met
Table C.8-17 Accumulator operation instructions (byte, word): 6 instructions]
Mnemonic
SWAP
SWAPW
EXT
EXTW
ZEXT
ZEXTW
#
~
RG
B
Operation
LH
AH
I
S
T
N
Z
1 3 0 0 byte (A) 0 to 7 ↔ (A) 8 to 15 – – – – – – – – –
–
1 2 0 0 word (AH) ↔ (AL)
– * – – – – – – –
–
1 1 0 0 byte sign extension
X – – – – * * – –
–
1 2 0 0 word sign extension
– X – – – * * – –
–
1 1 0 0 byte zero extension
Z – – – – R * – –
–
1 1 0 0 word zero extension
– Z – – – R * – –
–
<Caution>See Table C.5-1 , "Number of execution cycles for each type of addressing," and
Table C.5-2 , "Compensation values for calculating the number of execution cycles,"
for (a) to (d) in the above table.
MB90820 series
657
Table 14
String instructions: 10 instructions
Mnemonic
#
~
MOVS/MOVSI
MOVSD
2
2
2
*
*2
*
*5
* Byte transfer @AH+ ← @AL+, counter = RW0 –
*3 Byte transfer @AH– ← @AL–, counter = RW0 –
SCEQ/SCEQI
SCEQD
2
2
*1
*1
*5
*5
*4 Byte retrieval (@AH+) – AL, counter = RW0
*4 Byte retrieval (@AH–) – AL, counter = RW0
FISL/FILSI
2 6m +6 *5
RG
5
B
Operation
LH AH
I
S
T
N
Z
V
C
RMW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
*3 Byte filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
3
MOVSW/MOVSWI 2
MOVSWD
2
2
*
*2
*
*8
* Word transfer @AH+ ← @AL+, counter = RW0
*6 Word transfer @AH– ← @AL–, counter = RW0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SCWEQ/SCWEQI
SCWEQD
2
2
*1
*1
*8
*8
*7 Word retrieval (@AH+) – AL, counter = RW0
*7 Word retrieval (@AH–) – AL, counter = RW0
–
–
–
–
–
–
–
–
–
–
*
*
*
*
*
*
*
*
–
–
FILSW/FILSWI
2 6m +6 *8
*6 Word filling @AH+ ← AL, counter = RW0
–
–
–
–
–
*
*
–
–
–
8
6
*15 when RW0 is zero, 4 + 7 x (RW0) when counter limit reached, 7n + 5 for a match
*2 5 when RW0 is zero, 4 + 8 x (RW0) otherwise
*3 (b) x (RW0) + (b) x (RW0). When source and destination access different areas, calculate item (b)
separately.
*4 (b) x n
*5 2 x (RW0)
*6 (c) x (RW0) + (c) x (RW0). When source and destination access different areas, calculate item (c)
separately.
*7 (c) x n
*8 2 x (RW0)
Note:
m: RW0 value (counter value)
n:
Loop count
<Caution>
658
See Table C.5-1 , "Number of execution cycles for each type of addressing," and Table C.52 , "Compensation values for calculating the number of execution cycles," for (a) to (d) in the
above table.
MB90820 series
C.9
Instruction Maps
An F2MC-16LX instruction code consists of one or two bytes. Accordingly an
instruction map consists of several one-byte or two-byte pages.
Table C.9-2 to Table C.9-20 show F2MC-16LX instruction maps.
■ Configuration of instruction maps
: 1st byte
Basic page map
Bit operation instructions
Character string operation instructions
2-byte instructions
ea instructions x 9
: 2nd byte
Figure C.9-1 Configuration of instruction maps
When the instruction code is a 1-byte instruction (NOP instruction, etc.), the instruction code is
described on the basic page map. When the instruction code is a 2-byte instruction (MOVS,
etc.), see the basic page map and check the name of the map where the second byte of the
instruction code to be referenced next is described.
MB90820 series
659
Figure C.9-2 shows the relationship between the actual instruction code and instruction maps.
Instruction
code
Not present in some
instructions.
Length varies with the
instruction.
1st byte
2nd byte Operand
Operand
[Basic page map]
[Extended page map] (*1)
*1 The extended page map is a generic term used for bit operation instructions, character string
operation instructions, 2-byte instructions, and ea instructions. Actually, more than one extended page
map exists for each type of instruction.
Figure C.9-2 Relationship between actual instruction codes and instruction maps
Table C.9-1 lists instruction code examples.
Table C.9-1 Example instruction codes
660
Instruction
1st byte (from the basic page
map)
2nd byte (from the extended
page map)
NOP
00 + 0 = 00
AND A,#8
30 + 4 = 34
MOV A,ADB
60 + F = 6F
00 + 0 = 00
@RW2+d8,#8,rel
70 + 0 = 70
F0 + 2 = F2
MB90820 series
MB90820 series
Character
string operation instructions
2-byte
instructions
Bit operation
instructions
ea instructions (9)
ea instructions (8)
ea instructions (7)
ea instructions (6)
ea instructions (5)
ea instructions (4)
ea instructions (3)
ea instructions (2)
ea instructions (1)
Table C.9-2 Basic page map
661
Table C.9-3 Bit operation instruction map (1st byte = 6C H)
662
MB90820 series
Table C.9-4 Character string operation instruction map (1st byte = 6EH)
MB90820 series
663
Table C.9-5 2-byte instruction map (1st byte = 6FH)
664
MB90820 series
MB90820 series
Use
prohibited
Use
prohibited
Use
prohibited
Use
prohibited
Use
prohibited
Use
prohibited
Use
prohibited
Use
prohibited
Table C.9-6 ea instruction map (1) (1st byte = 70H)
665
Table C.9-7 ea instruction map (2) (1st byte = 71 H)
666
MB90820 series
Table C.9-8 ea instruction map (3) (1st byte = 72H)
MB90820 series
667
Table C.9-9 ea instruction map (4) (1st byte = 73 H)
668
MB90820 series
Table C.9-10 ea instruction map (5) (1st byte = 74H)
MB90820 series
669
Table C.9-11 ea instruction map (6) (1st byte = 75 H)
670
MB90820 series
Table C.9-12 ea instruction map (7) (1st byte = 76H)
MB90820 series
671
Table C.9-13 ea instruction map (8) (1st byte = 77 H)
672
MB90820 series
Table C.9-14 ea instruction map (9) (1st byte = 78H)
MB90820 series
673
Table C.9-15 MOVEA RWi,ea instruction map (1st byte = 79H)
674
MB90820 series
Table C.9-16 MOV Ri,ea instruction map (1st byte = 7AH)
MB90820 series
675
Table C.9-17 MOVW RWi,ea instruction map (1st byte = 7BH)
676
MB90820 series
Table C.9-18 MOV ea,Ri instruction map (1st byte = 7CH)
MB90820 series
677
Table C.9-19 MOVW ea,Rwi instruction map (1st byte = 7D H)
678
MB90820 series
Table C.9-20 XCH Ri,ea instruction map (1st byte = 7EH)
MB90820 series
679
Table C.9-21 XCHW RWi,ea instruction map (1st byte = 7FH)
680
MB90820 series
Numerics
16-bit reload register (TMRLR0/1L, TMRLR0/1H) 271
16-bit reload timer ................................................ 403
16-bit reload timer 0 ............................................. 536
16-bit reload timer interrupt .......... 304, 400, 401, 402
16-bit reload timer setting .................................... 274
16-bit reload timer, block diagram of.................... 261
16-bit reload timer, EI2OS function of.................. 272
16-bit reload timer, interrupt generated by ........... 272
16-bit reload timer, interrupt of ............................. 272
16-bit reload timer, list of register of..................... 264
16-bit reload timer, note on using ........................ 284
16-bit reload timer, operation mode of ................. 258
16-bit reload timer, pin of ..................................... 263
16-bit timer register (TMR0/1) .............................. 270
24-bit operand specification, linear addressing by . 32
A
A............................................................................. 42
access space ......................................................... 33
accumulator (A)...................................................... 42
ADB.................................................................. 55, 60
address match detection function ................ 558, 564
addressing ........................................................... 623
Analog input enable register ................................ 467
asynchronous mode............................................. 542
B
bank addressing............................................... 31, 34
bank register .......................................................... 33
bank register (PCB, DTB, USB, SSB, ADB) .......... 55
bank select prefix (PCB, DTB, ADB, SPB) ............ 60
basic configuration ............................................... 610
baud rate determined using external clock .......... 538
baud rate determined using internal timer ........... 536
baud rates determined using dedicated baud rate generator ................................................................. 532
bidirectional communication function ................... 546
block diagram of 16-bit reload timer pin ............... 292
Block diagram of A/D converter ........................... 469
block diagram of clock generation block ................ 80
block diagram of delayed interrupt generator module
436
block diagram of DTP/external interrupt circuit .... 444
block diagram of DTP/external interrupt circuit pin447
block diagram of external reset pin ........................ 71
block diagram of low power consumption control circuit
96
block diagram of port 0 pin................................... 173
MB90820 series
block diagram of port 1 pin ...................181, 187, 193
block diagram of port 4 pin ...................................211
block diagram of timebase timer...........................236
block diagram of UART ........................................508
block diagram of UART pin...................................513
block diagram of watchdog timer ..........................249
bus mode ......................................................162, 164
C
calculating pulse width/period...............................319
Cautions ...............................................................493
CCR ........................................................................49
CDCR ...................................................................524
change diagram ....................................................110
characteristic of 512k / 1024k bit flash memory ...574
characteristic of PWC timer ..................................290
chip/sector deletion operation execution ..............582
CKSCR .............................................................84, 86
clearing the timer ..................................................312
clock .......................................................................78
clock generation block ............................................80
clock mode .............................................................95
clock mode transition ..............................................88
clock selection bit .................................................325
clock selection register (CKSCR) .....................84, 86
clock supply function ....................................235, 242
clock supply map ....................................................79
CMR .......................................................................62
command sequence table ....................................578
common register bank prefix (CMR).......................62
communication prescaler control register (CDCR)524
condition code register (CCR) ................................49
configuration of interrupt control register (ICR) ....126
consecutive prefix code ..........................................65
continuous measurement mode ...........................317
Continuous mode .................................................482
control register (SCR0/1) ......................................516
Control Status Register (ADCS0) .........................472
Control Status Register (ADCS1) .........................474
control status register (FMCS)..............................576
Conversion using EI2OS ......................................484
Converted-data protection function ......................492
count clock and maximum period .........................314
counter operation..................................................259
counter operation, states of ..................................275
CPU ........................................................................26
CPU intermittent operation mode ...................95, 101
CPU operating mode ..............................................94
current consumption ...............................................94
681
D
D/A control register (DACR0 and DACR1)........... 501
D/A converter register (DAT0 and DAT1)............. 500
DACR0 and DACR1 ............................................. 501
DAT0 and DAT1 ................................................... 500
data counter (DCT) .............................................. 147
Data register (ADCR0, ADCR1) ........................... 477
DCT ...................................................................... 147
dedicated baud rate generator ............................. 532
dedicated register............................................. 38, 40
default space .......................................................... 34
delayed interrupt generator module ..... 436, 438, 439
delayed interrupt generator module register 437, 438
diagram ................................................................ 110
direct addressing .................................................. 625
direct page register (DPR)...................................... 54
division rate control register (DIVR) ..................... 303
DIVR..................................................................... 303
DPR........................................................................ 54
DTB .................................................................. 55, 60
DTP ...................................................................... 443
DTP function ................................................ 459, 463
DTP/external interrupt circuit........ 444, 454, 455, 460
DTP/external interrupt circuit pin .................. 446, 447
DTP/external interrupt function ............................ 442
DTP/interrupt cause register (EIRR) .................... 449
DTP/interrupt enable register (ENIR) ................... 450
E
EEPROM memory map........................................ 565
effective-address field .................................. 624, 641
EI²OS ..144, 145, 146, 148, 150, 151, 152, 159, 240,
304, 400, 401, 402, 403, 443, 507, 527
EI²OS function of the 16-bit reload timer ...... 305, 403
EI2OS................................................................... 272
EIRR..................................................................... 449
ELVR .................................................................... 452
ENIR..................................................................... 450
error...................................................................... 565
event count mode................................................. 282
event count mode (external clock mode) ............. 259
event count mode, sample program for................ 287
Example of flow of data protection function (when
EI2OS is used)................................................... 493
Example of starting of EI2OS in continuous mode488
Example of starting of EI2OS in single mode....... 486
Example of starting of EI2OS in stop mode ......... 490
exception processing ........................................... 154
execution cycle..................................................... 638
682
extended intelligent I/O service... 146, 148, 150, 151,
152, 159
extended intelligent I/O service (EI²OS)....... 144, 145
external clock ................................................. 91, 538
external clock mode ............................................. 259
external interrupt circuit........................................ 443
external interrupt function ............................ 458, 462
external reset pin ................................................... 71
F
Features of A/D converter.................................... 466
flag change suppression prefix (NCC) ................... 63
flag set timing............................................... 528, 529
flowchart of pulse-width measurement operation 322
flowchart of timer mode operation........................ 315
G
general-purpose register.................................. 38, 56
general-purpose register area................................ 51
H
handling device, note on ........................................ 22
hardware interrupt................................ 130, 134, 137
hardware interrupt activation................................ 134
hardware interrupt operation................................ 135
hardware interrupt processing time...................... 140
hardware interrupt structure................................. 131
hardware interrupt suppression ........................... 132
hardware sequence flag....................................... 580
how to specify address ........................................ 590
I
I/O area .................................................................. 29
I/O map ................................................................ 603
I/O port ................................................................. 170
I/O port function ................................................... 168
I/O port program................................................... 232
I/O register address pointer (IOA)........................ 147
I/O service descriptor ........................................... 146
I/O service status register .................................... 148
ICR....................................................................... 126
ICR00 to ICR15.................................................... 124
ILM ......................................................................... 52
indirect addressing............................................... 631
indirect specification with 32-bit register, addressing by
32
initial state ............................................................ 565
input data register (SIDR0/1) ............................... 522
MB90820 series
Input impedance .................................................. 468
instruction............................................................. 622
instruction code.................................................... 642
instruction map..................................................... 659
INT9 interrupt ....................................................... 566
internal clock mode .............................................. 258
internal clock mode (one-shot mode), operation of278
internal clock mode (reload mode), operation in .. 276
internal clock mode, sample program for ............. 285
internal timer (16-bit reload timer 0) ..................... 536
interrupt cause ..................................................... 121
interrupt control register ....................................... 123
interrupt control register (ICR00 to ICR15) .......... 124
interrupt control register function ................. 123, 126
interrupt level mask register (ILM) ......................... 52
interrupt operation ........................................ 119, 136
interrupt processing ..................................... 156, 158
interrupt request generation ......................... 313, 319
interrupt type and function ................................... 118
interrupt vector ..................................................... 120
interrupt vector/interrupt control register .............. 121
interrupt/hold suppression instruction .................... 64
interval timer function ................................... 234, 241
IOA....................................................................... 147
ISCS..................................................................... 148
ISD ....................................................................... 146
L
linear addressing.................................................... 31
low power consumption control circuit ................... 96
low power consumption mode control register98, 100
low power consumption mode operating state..... 111
lower bit of timer control status register (TMCSR0/1L)
268
LPMCR .................................................................. 98
M
machine clock ........................................................ 88
main clock mode .................................................... 88
master-slave communication function.................. 548
MD2 to MD0 ......................................................... 163
measurement mode and measurement operation320
measurement result data ..................................... 317
measurement termination flag in timer mode....... 324
memory map .......................................................... 30
memory space ....................................................... 28
method of specifying sector ................................. 594
minimum input pulse width................................... 319
mode control register (SMR0/1) ........................... 518
MB90820 series
mode data...............................................76, 164, 165
mode data reading, pin after...................................76
mode fetch ..............................................................73
mode pin .........................................................72, 165
mode pin (MD2 to MD0) .......................................163
mode setting .........................................................162
multibyte ...........................................................36, 37
multibyte data access .............................................37
multiple interrupt ...................................................138
N
NCC ........................................................................63
note.......................................................................564
note on delayed interrupt generator module.........439
note on DTP/external interrupt circuit ...................460
note on reset cause bit ...........................................75
note on specifying two or more sectors ................594
note on standby mode ..........................................114
note on UART .......................................................552
note on watchdog timer ........................................254
note on writing data ..............................................590
O
one-shot operation mode......................................313
operand, storage of multibyte .................................36
operating mode.....................................................162
operation mode 2..................................................544
operation mode selection .....................................310
oscillation settling time timer function ...................241
oscillation stabilization wait.....................................70
oscillation stabilization wait interval ..........70, 90, 115
oscillator .................................................................91
output data register (SODR0/1) ............................522
P
PC...........................................................................53
PCB ..................................................................55, 60
pin during reset .......................................................76
pin in single-chip mode .........................................113
PLL clock mode ......................................................88
PLL clock multiplier.................................................88
port 0 ....................................................................178
port 0 configuration ...............................................172
port 0 pin.......................................................172, 173
port 0 register ...............................................174, 176
port 1 ....................................................184, 190, 196
port 1 configuration ...............................180, 186, 192
port 1 pin...............................................180, 186, 192
683
port 1 register ............................... 183, 188, 189, 194
port 2 ............................................................ 202, 230
port 2 configuration ......................................198, 226
port 2 pin ...................................... 198, 199, 226, 227
port 2 register ............................... 200, 201, 228, 229
port 3 ............................................................ 208, 224
port 3 configuration ......................................204, 216
port 3 pin ...................................... 204, 205, 216, 217
port 3 register ............................... 206, 207, 220, 222
port 4 .................................................................... 214
port 4 configuration .............................................. 210
port 4 pin ...................................................... 210, 211
port 4 register ............................................... 211, 212
prefix code........................................................58, 64
procedure for writing/deleting initiadata to flash memory........................................................................ 574
procedure of deleting sector................................. 594
procedure of writing data to flash memory ........... 590
processor status (PS)............................................. 48
program counter (PC) ............................................ 53
PS ..........................................................................48
pull-up resistor...................................................... 113
pulse width/period measurement range ............... 319
pulse-width measurement and starting and stopping
timer................................................................... 311
pulse-width measurement function....................... 308
pulse-width measurement operation, flowchart of 322
PWC control status register (PWCSR)......... 296, 300
PWC data buffer register (PWCR) ....................... 302
PWC timer block diagram..................................... 291
PWC timer operation ............................................ 290
PWC timer register ............................................... 295
PWC timer, characteristic of................................. 290
PWCR .................................................................. 302
PWCSR ........................................................ 296, 300
R
RAM ....................................................................... 36
RAM area ............................................................... 29
reception interrupt generation .............................. 528
register bank .......................................................... 57
register bank pointer .............................................. 51
register bank pointer (RP) ...................................... 51
register on flash memory...................................... 574
register value change ........................................... 324
Registers for A/D converter .................................. 470
reload mode ......................................................... 276
reload operation mode ......................................... 313
request level setting register (ELVR).................... 452
684
reset ....................................................................... 76
reset cause ................................................ 68, 70, 75
reset cause bit.................................................. 74, 75
reset operation ....................................................... 72
reset sequence .................................................... 566
reset state .............................................................. 70
restart during operation........................................ 325
ROM area .............................................................. 29
ROM mirroring function selection register............ 571
ROMM (ROM mirroring function selection register)571
RP .......................................................................... 51
RUN mode ........................................................... 162
S
SCR0/1 ................................................................ 516
sector configuration.............................................. 575
sector deletion operation execution ..................... 586
sector deletion temporary stop execution .... 582, 584
Setting Register (ADSR) .............................. 478, 480
SIDR0/1 ............................................................... 522
single measurement mode................................... 317
single measurement mode and continuous measurement mode ........................................................ 317
Single mode 1 / 2 ................................................. 482
single-chip mode.................................................. 113
sleep mode .......................................................... 103
SMR0/1 ................................................................ 518
SODR0/1.............................................................. 522
software interrupt ................................................. 142
software interrupt activation ................................. 142
software interrupt operation ................................. 143
software pull-up resistor....................................... 113
SPB........................................................................ 60
SSB........................................................................ 55
SSP........................................................................ 47
SSR0/1................................................................. 520
stack area ............................................................ 157
stack operation..................................................... 156
stack selection ....................................................... 46
stack, storage of multibyte data in ......................... 37
standby mode ........................................ 95, 102, 114
starting and stopping timer and pulse-width measurement .................................................................. 311
status register (SSR0/1)....................................... 520
Stop mode............................................................ 482
stop mode .................................................... 108, 115
storage of multibyte data in RAM........................... 36
synchronous mode (operation mode 2), operation in
544
MB90820 series
system configuration ............................................ 565
system stack pointer (SSP).................................... 47
T
TBTC.................................................................... 238
timebase timer ............................. 236, 241, 243, 245
timebase timer control register (TBTC) ................ 238
timebase timer interrupt ....................................... 240
timebase timer mode ................................... 106, 115
timebase timer usage note................................... 243
timer clear ............................................................ 325
timer function ....................................................... 306
timer mode operation, flowchart of....................... 315
timer mode, measurement termination flag in...... 324
timer period .......................................................... 314
timer value and reload value ................................ 313
TMCSR0/1H......................................................... 266
TMCSR0/1L ......................................................... 268
TMR0/1 ................................................................ 270
TMRLR0/1H ......................................................... 271
TMRLR0/1L.......................................................... 271
transmission interrupt generation......................... 529
U
UART ........................................... 508, 540, 552, 554
UART baud rate selection .................................... 530
UART EI²OS function ........................................... 527
UART function...................................................... 506
UART interrupt ..................................... 507, 526, 527
UART pin ..................................................... 512, 513
UART register ...................................................... 515
upper bit and bit 7 of timer control status register
(TMCSR0/1H).................................................... 266
USB........................................................................ 55
user stack pointer (USP)........................................ 47
USP........................................................................ 47
W
watchdog timer..................................... 249, 254, 255
watchdog timer control register (WDTC).............. 250
watchdog timer function ....................................... 248
watchdog timer operation..................................... 252
WDTC .................................................................. 250
write operation execution ..................................... 582
write operation or chip/sector deletion operation execution............................................................. 584, 585
MB90820 series
685
686
MB90820 series