A3918 Datasheet

A3918
Low Voltage DC Motor Driver
Features and Benefits
Description
▪ 2.5 to 9 V operation
▪ Internal PWM current control
▪ Synchronous rectification for reduced power dissipation
▪ Peak current output flag
▪ Undervoltage lockout
▪ Low RDS(on) outputs
▪ Small package
▪ Brake mode for DC motor
▪ Sleep function
▪ Crossover-current protection
▪ Thermal shutdown
Designed for pulse width modulated (PWM) control of a low
voltage DC motor, the A3918 is capable of output currents up
to 1.5 A and operating voltages from 2.5 to 9 V.
The A3918 has an internal fixed off-time PWM timer that
sets a peak current based on the selection of a current sense
resistor. An overcurrent output flag is provided that notifies
the user when the current in the motor winding reaches the
peak current determined by the sense resistor. The fault output
does not affect driver operation.
The A3918 is provided in a 16-contact, 3 mm × 3 mm, 0.75 mm
nominal overall height QFN, with exposed pad for enhanced
thermal dissipation. It is lead (Pb) free, with 100% matte tin
leadframe plating.
Package: 16-contact QFN (suffix ES)
Applications include the following:
▪ Digital still cameras (DSC)
▪ Cell phone cameras
▪ USB powered devices
▪ Battery powered devices
3 × 3 mm
0.75 mm overall height
Approximate size
Functional Block Diagram
0.1 μF
0.1 μF
CP4
CP3
CP2
CP1
VCP
0.1 μF
VBB
VCP
Charge
Pump
VBB
+5 V
PWM Latch
and
Blanking
Comparator
Bridge
Regulator
SLEEP
Sense
FL
OUTA
OUTB
10 μF
10 V
IN1
Control Logic
IN2
Sense
SENSE
RSENSE
GND
A3918-DS
PAD
GND
GND
A3918
Low Voltage DC Motor Driver
Selection Guide
Part Number
Packing
A3918SESTR-T
Package
1500 pieces per 7-in. reel
16-pin QFN with exposed thermal pad
Absolute Maximum Ratings
Characteristic
Symbol
Load Supply Voltage
VBB
Logic Input Voltage Range
VIN
Sense Voltage
VSENSE
Output Current
Pulsed, tw < 1 μs
Continuous
Peak, DC < 30%
Range S
TA
Junction Temperature
Continuous
May be limited by duty cycle, ambient
temperature, and heat sinking. Under
any set of conditions, do not exceed
the specified current rating or a junction
temperature of 150°C.
IOUT
Operating Temperature Range
Notes
Rating
Units
9.6
V
–0.3 to 7
V
0.5
V
1
V
1
A
1.5
A
–20 to 85
°C
TJ(max)
150
°C
Tstg
–40 to 150
°C
Storage Temperature Range
Thermal Characteristics may require derating at maximum conditions, see application information
Characteristic
Symbol
RθJA
Package Thermal Resistance
Test Conditions*
Value Units
4-layer PCB based on JEDEC standard
42
ºC/W
*Additional thermal information available on the Allegro website.
Terminal List Table
Current limit flag
GND
2, 6, 8
IN1
4
VCP
Charge pump capacitor terminal 4
7
CP3
16
13
CP4
14
Charge pump capacitor terminal 2
Charge pump capacitor terminal 3
CP1
VBB
Ground
Control input 1
IN2
5
Control input 2
OUTA
12
DMOS full-bridge output A
OUTB
10
DMOS full-bridge output B
8
7
9
FL
SENSE
10 OUTB
GND
4
GND
3
IN1
1
14
CP4
SLEEP
11
PAD
Function
Charge pump capacitor terminal 1
CP2
15
2
12 OUTA
6
GND
CP1
15
FL
5
1
Number
CP3
IN2
CP2
Name
16
Pin-out Diagram
PAD
–
Exposed thermal pad
SENSE
11
Current sense resistor terminal
¯P̄¯
S̄¯L̄¯Ē¯Ē
3
Sleep logic input, active low
VBB
9
Supply Voltage
VCP
13
Reservoir capacitor terminal
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3918
Low Voltage DC Motor Driver
ELECTRICAL CHARACTERISTICS1,2 valid at TA = 25°C and VBB = 2.5 to 9 V, unless otherwise noted
Characteristics
Symbol
Operating Voltage Range
VBB
VBB Supply Current
IBB
Output Resistance
RDS(on)
Current Trip Sense Voltage
VSENSE
Test Conditions
Output Leakage Current
Vf
IDSS
Typ.
Max.
Units
2.5
–
9
V
IOUT = 0 mA, PWM = 50 kHz, Duty Cycle = 50%
–
5
–
mA
IOUT = 0 mA, outputs disabled, VBB = 9.6 V
–
3
–
mA
Sleep mode, VIN < 0.4 V
–
150
500
nA
Source driver, IOUT = 400 mA , VBB = 3 V, TJ = 25°C
–
0.52
0.60
Ω
Source driver, IOUT = 400 mA , VBB = 3 V, TJ = 85°C
–
0.78
–
Ω
Sink driver, IOUT = 400 mA, VBB = 3 V, TJ= 25°C
–
0.62
0.74
Ω
Sink driver, IOUT = 400 mA, VBB = 3 V, TJ= 85°C
Clamp Diode Voltage
Min.
FL falling edge
I = 400 mA
Outputs, VOUT = 9 V
–
0.93
–
Ω
160
200
240
mV
–
–
1
V
–20
–
20
μA
Control Logic
Logic Input Voltage
Logic Input Current
Input Hysteresis
S̄¯L̄¯Ē¯Ē¯P̄¯ Input
VIN(1)
2.0
–
5.5
V
VIN(0)
–
–
0.8
V
IIN(1)
VIN = 5.5 V
–
<100
500
nA
IIN(0)
VIN = 0.8 V
–
<–100
–500
nA
VINhys
–
150
–
mV
VSLEEP(0)
–
–
0.4
V
VSLEEP(1)
2
–
–
V
Fault Output
VFL
Flag asserted, IFL = 1 mA
–
–
200
mV
Fault Output Leakage Current
IFL
VFL = 5 V
–
–
1
μA
tFL
Reset of PWM latch
–
300
–
μs
2.1
3
3.9
μs
Fault Output Timer
Blank Time
Fixed Off-Time
Propagation Delay Time
tBLANK
–
30
–
μs
tpd(on)
tOFF
Input high to source on, input low to source off
100
235
350
ns
tpd(off)
Input low to sink off, input high to sink on
50
100
200
ns
Protection Circuitry
Crossover Delay
tCOD
200
425
650
ns
2.2
2.31
2.45
V
VBBUVHYS
200
300
400
mV
TJTSD
–
165
–
°C
TJTSDHYS
–
15
–
°C
VBB Undervoltage Lockout Threshold
VBBUVLO
VBB Undervoltage Lockout Hysteresis
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
VBB rising
1For
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2Specifications over the operating temperature range are assured by design and characterization.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3918
Low Voltage DC Motor Driver
Fault Timing Diagram
ITRIP
ILOAD
FL
tFL
Fault Asserted
tFL
Fault Asserted
Fault Asserted
NOTE: Timer resets after each reset of the PWM latch.
Control Logic
DC Motor Operation
IN1
IN2
OUTA
OUTB
Function
0
0
Off
Off
Disabled
1
0
High
Low
Forward
0
1
Low
High
Reverse
1
1
Low
Low
Brake
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3918
Low Voltage DC Motor Driver
Functional Description
Device Operation The A3918 is a full-bridge low voltage
motor driver capable of operating one high current DC motor.
MOSFET output stages substantially reduce the voltage drop and
the power dissipation of the outputs of the A3918, compared to
typical drivers with bipolar transistors.
the source-side DMOS gates. For pumping purposes, a 0.1 μF
ceramic capacitor should be connected between CP1 and CP2,
and between CP3 and CP4. A 0.1 uF ceramic capacitor is required
between VCP and VBB, to act as a reservoir to operate the highside DMOS devices.
Output current can be regulated by pulse width modulating
(PWM) the inputs. In addition supporting external PWM of the
driver, the A3918 limits the peak current by internally PWMing
the source driver when the current in the winding exceeds the
peak current, which is determined by a sense resistor. A fault
output notifies the user that peak current was reached. If internal
current limiting is not needed, the sense pin should be shorted to
ground.
Thermal Shutdown The A3918 will disable the outputs if the
junction temperature reaches 165°C. When the junction temperature drops 15°C, the outputs will be enabled.
Internal circuit protection includes thermal shutdown with hysteresis, undervoltage lockout, internal clamp diodes, and crossover
current protection.
The A3918 is designed for portable applications, providing a
power-off low current sleep mode and an operating voltage of
2.5 to 9 V.
External PWM Output current regulation can be achieved by
pulse width modulating the inputs. Slow decay mode is selected
by holding one input high while PWMing the other input. Holding one input low and PWMing the other input results in fast
decay. Refer to the Applications Information section for further
information.
Blanking This function blanks the output of the current sense
comparator when the outputs are switched. The comparator
output is blanked to prevent false overcurrent detections due to
reverse recovery currents of the clamp diodes or to switching
transients related to the capacitance of the load. The blank time,
tBLANK , is approximately 3 μs.
Sleep Mode An active-low control input used to minimize
power consumption when the A3918 is not in use. This disables much of the internal circuitry including the output drivers,
internal regulator, and charge pump. A logic high allows normal
operation. When coming out of sleep mode, wait 1.5 ms before
issuing a command, to allow the internal regulator and charge
pump to stabilize.
Enable When all logic inputs are pulled to logic low, the outputs
of the bridges are disabled. The charge pump and internal circuitry continue to run when the outputs are disabled.
Charge Pump (CP1, CP2, CP3, and CP4) When supply voltages are lower than 3.5 V, the two-stage charge pump triples the
input voltage to a maximum of 7 V above the supply. The charge
pump is used to create a supply voltage greater than VBB , to drive
Brake Mode When driving DC motors, the A3918 goes into
brake mode (turns on both sink drivers) when both of its inputs
are high (IN1 and IN2). There is no protection during braking, so
care must be taken to ensure that the peak current during braking
does not exceed the absolute maximum current.
Internal PWM Current Control The bridge is controlled
by a fixed off-time PWM current control circuit that limits the
load current to a desired value, ITRIP . Initially, a diagonal pair
of source and sink DMOS outputs are enabled and current flows
through the motor winding and the current sense resistor, RSENSE .
When the voltage across RSENSE equals the internal reference
voltage, the current sense comparator resets the PWM latch,
which turns off the source driver.
The maximum value of current limiting, ITRIP(max) , is set by the
selection of the sense resistor, RSENSE , and is approximated by a
transconductance function:
ITRIP(max) = 0.2 / RSENSE .
It is critical to ensure the maximum rating on the SENSE pin
(0.5 V) is not exceeded.
Synchronous Rectification When a PWM off-cycle is triggered by an internal fixed off-time cycle, load current recirculates
in slow decay SR mode. During slow decay, current recirculates
through the sink-side FET and the sink-side body diode. The SR
feature enables the sink-side FET, effectively shorting out the
body diode. The sink driver is not enabled until the source driver
is turned off and the crossover delay has expired. This feature
helps lower the voltage drop during current recirculation, lowering power dissipation in the bridge.
Overcurrent Output Flag When the peak current (set by the
external resistor) is reached, the fault pin, FL, is pulled low.
When a reset of the PWM latch occurs, the fault timer begins. At
each PWM latch reset, the timer is reset to zero. After approximately 300 μs, if no peak current event was triggered, the timer
expires and the fault is released. This ensures that during PWM
current limiting, the fault pin remains in a fault state.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A3918
Low Voltage DC Motor Driver
Applications Information
External PWM If external PWM is used, the internal current
control can either be disabled by shorting the SENSE pin to
ground, or it can be used to limit the peak current to a value under
the stall current to prevent motor heating. External PWM of
IN1/IN2 control is shown in the figure below.
VIN(1)
IN1
GND
VIN(1)
PWM current control in fast and
slow decay modes
IN2
GND
+IREG
IOUT(x)
0A
-IREG
Forward/
Fast Decay
Reverse/
Fast Decay
Forward/
Slow Decay
Reverse/
Slow Decay
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A3918
Low Voltage DC Motor Driver
Layout The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the
A3918 must be soldered directly onto the board. On the underside of the A3918 package is an exposed pad, which provides a
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
are used to transfer heat to other layers of the PCB.
Grounding In order to minimize the effects of ground bounce
and offset issues, it is important to have a low impedance singlepoint ground, known as a star ground, located very close to the
device. By making the connection between the exposed thermal
pad and the ground plane directly under the A3918, that area
becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current
operation and ensure that the supply voltage remains stable at
the input terminal. The recommended PCB layout shown in the
diagram below, illustrates how to create a star ground under the
device, to serve both as low impedance ground point and
thermal path.
The two input capacitors should be placed in parallel, and as
close to the device supply pin as possible. The ceramic capacitor should be closer to the pin than the bulk capacitor. This is
necessary because the ceramic capacitor will be responsible for
delivering the high frequency current components.
Sense Pin The sense resistor, RSENSE, should have a very low
impedance path to ground, because it must carry a large current
while supporting very accurate voltage measurements by the current sense comparator. Long ground traces will cause additional
voltage drops, adversely affecting the ability of the comparator to
accurately measure the current in the winding. As shown in the
layout below, the SENSE pin has very short traces to the RSENSE
resistor and very thick, low impedance traces directly to the star
ground underneath the device. If possible, there should be no
other components on the sense circuit.
Note: When selecting a value for the sense resistor, be sure not to
exceed the maximum voltage on the SENSE pin of ±500 mV.
Solder
A3918
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
C1
C2
CP4
C1
C3
C3
VCP
C2
Thermal Vias
CP3
Thermal (2 oz.)
CP1
PCB
OUTA
A3918
CP2
GND
SLEEP
SLEEP
R1
OUTB
VCCIO
VBB
C4
IN2
C4
GND
R1
R6
R2
VBB
IN1
IN2
OUTB
IN1
FL
OUTA
R6
OUTB
GND
R4
U1
IN2
R3
R4
SENSE
R3
SLEEP
IN1
PAD
OUTA
C5
C6
R2
VCCIO
R5
FL
GND
C5
VBB
C6
FL
R5
GND
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A3918
Low Voltage DC Motor Driver
ES Package, 16-Contact QFN with Exposed Thermal Pad
0.30
3.00 ±0.15
0.90
16
1
2
A
0.50
16
1
3.00 ±0.15
1.70
3.10
1.70
17X
D
SEATING
PLANE
0.08 C
+0.05
0.25 –0.07
C
3.10
C
PCB Layout Reference View
0.75 ±0.05
0.50
For reference only, not for tooling use (reference JEDEC MO-220WEED)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
0.40±0.10
A Terminal #1 mark area
B
1.70
2
1
16
1.70
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P300X300X80-17W4M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
Copyright ©2011-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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