A3949 Datasheet

A3949
DMOS Full-Bridge Motor Driver
Features and Benefits
Description
▪ Single supply operation
▪ Very small outline package
▪ Low RDS(ON) outputs
▪ Sleep function
▪ Internal UVLO
▪ Crossover current protection
▪ Thermal shutdown protection
Designed for PWM (pulse width modulated) control of DC
motors, the A3949 is capable of peak output currents to ±2.8 A
and operating voltages to 36 V.
PHASE and ENABLE input terminals are provided for use
in controlling the speed and direction of a DC motor with
externally applied PWM control signals. Internal synchronous
rectification control circuitry is provided to reduce power
dissipation during PWM operation.
Packages:
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of VBB and VCP , and
crossover current protection.
The A3949 is supplied in a power package, a 16-pin plastic SOIC
with a copper batwing tab (part number suffix LB). The packages
are lead (Pb) free, with 100% matte tin leadframes.
Package LB, 16-pin SOIC
with internally fused pins
Not to scale
Functional Block Diagram
.22 μF
25 V
0.1 μF
VREG
Low Side
Gate Supply
CP1
OSC
Charge
Pump
CP2
VCP
0.1 μF
VBB
Load
Supply
MODE
0.1 μF
PHASE
OUTA
Control
Logic
OUTB
ENABLE
SENSE
SLEEP
DMOS Full Bridge
GND
GND
29319.47i
100 μF
A3949
DMOS Full-Bridge Motor Driver
Selection Guide
Part Number
A3949SLBTR-T
Package
Packing
16-pin, SOIC
1000 per reel
Absolute Maximum Ratings
Characteristic
Symbol
Load Supply Voltage
VBB
Logic Input Voltage
VIN
Sense Voltage
Notes
Peak < 2 μs
IOUT
V
38
V
V
0.5
V
±2.8
A
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any
set of conditions, DO NOT exceed the specified
IOUT or TJ.
Operating Ambient Temperature
TA
–20 to 85
ºC
Maximum Junction Temperature
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Storage Temperature
Range S
Units
36
–0.3 to 7
VSENSE
Output Current, Repetitive
Rating
Package Thermal Characteristics*
Characteristic
Symbol
RθJA
Note
Package Thermal Resistance
Measured on 2-layer PCB with 2 in. 2-oz. copper each side
*Additional information is available on the Allegro website.
2
Rating
Units
52
°C/W
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3949
DMOS Full-Bridge Motor Driver
ELECTRICAL CHARACTERISTICS at TA = 25°C, VBB = 8 V to 36 V (unless otherwise noted)
Characteristics
Min.
Typ.
Max.
Units
Source driver, IOUT = –2.8 A, TJ= 25°C
–
.4
.48
Ω
Source driver, IOUT = –2.8 A, TJ= 125°C
–
.68
–
Ω
Sink driver, IOUT = 2.8 A, TJ= 25°C
–
.3
.43
Ω
Sink driver, IOUT = –2.8 A, TJ= 125°C
–
.576
–
Ω
Source diode, IF = –2.8 A
–
1.1
1.3
V
Sink diode, IF = 2.8 A
–
1
1.3
V
fPWM < 50 kHz
–
6
8.5
mA
Charge pump turned on; outputs disabled
–
3
4.5
mA
Sleep mode
–
–
10
μA
VIN(1)
2.0
–
–
V
VIN(0)
–
–
0.8
V
Logic Input Voltage
SLEEP
VIN(1)
2.7
–
–
V
VIN(0)
–
–
0.8
V
Logic Input Current
PHASE, MODE pins
IIN(1)
VIN = 2.0 V
–
< 1.0
20
μA
IIN(0)
VIN = 0.8 V
–
< –2.0
–20
μA
Logic Input Current
ENABLE pin
IIN(1)
VIN = 2.0 V
–
40
100
μA
IIN(0)
VIN = 0.8 V
–
16
40
μA
IIN(1)
VIN = 2.7 V
–
27
50
μA
IIN(0)
VIN = 0.8 V
–
<1
10
μA
From PWM change to source or sink turn on
–
600
–
ns
From PWM change to source or sink turn off
–
100
–
ns
–
500
–
ns
–
6
–
V
–
250
–
mV
TJ
–
170
–
°C
ΔTJ
–
15
–
°C
Output-On Resistance
Body Diode Forward Voltage
Motor Supply Current
Logic Input Voltage
PHASE, ENABLE, MODE
Logic Input Current
SLEEP pin
Propagation Delay Times
Crossover Delay
Symbol
RDSON
VF
IBB
tpd
Test Conditions
tCOD
Protection Circuitry
UVLO Enable Threshold
VBB rising
UVLO Hysteresis
Thermal Shutdown Temp.
Thermal Shutdown Hysteresis
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3949
DMOS Full-Bridge Motor Driver
PWM Control Timing Diagram
SLEEP
ENABLE
PHASE
MODE
VBB
OUTA
0V
VBB
OUTB
0V
IOUT
0A
A
1
2
3
4
5
6
7
8
9
VBB
VBB
6
7
OUTB
OUTA
1
OUTA
OUTB
5
9
3
2
8
4
A
Charge pump and VREG power-up delay (approximately 200 us)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3949
DMOS Full-Bridge Motor Driver
Functional Description
VREG. This supply voltage is used to operate the sinkside DMOS outputs. VREG is internally monitored and in
the case of a fault condition, the outputs of the device are
disabled. The VREG pin should be decoupled with a 0.22 F
capacitor to ground.
Charge Pump. The charge pump is used to generate a
supply above VBB to drive the source-side DMOS gates. A
0.1 uF ceramic monolithic capacitor should be connected
between CP1 and CP2 for pumping purposes. A 0.1 uF
ceramic monolithic capacitor should be connected between
VCP and VBB to act as a reservoir to run the high side
DMOS devices. The VCP voltage is internally monitored,
and in the case of a fault condition, the outputs of the device
are disabled.
Shutdown. In the event of a fault due to excessive junction
temperature, or low voltage on VCP or VREG, the outputs of
the device are disabled until the fault condition is removed.
At power-up, the UVLO circuit disables the drivers.
Sleep Mode. Control input SLEEP is used to minimize
power consumption when the A3949 is not in use. This
disables much of the internal circuitry, including the low-side
gate supply and the charge pump. A logic low on this pin
puts the device into Sleep mode. A logic high allows normal
operation. After coming out of Sleep mode, the user should
wait 1 ms before applying PWM signals, to allow the charge
pump to stabilize.
Braking. The braking function is implemented by driving the device in slow decay mode via the MODE pin, and
applying an enable chop command. Because it is possible to
drive current in both directions through the DMOS switches,
this configuration effectively shorts out the motor-generated
BEMF, as long as the enable chop mode is asserted on the
ENABLE pin. The maximum current can be approximated
by VBEMF / RL. Care should be taken to insure that the maximum ratings of the device are not exceeded in worse case
braking situations of high speed and high inertial loads.
Control Logic Table
PHASE ENABLE MODE
SLEEP
OUTA
OUTB
Function
1
1
X
1
H
L
Forward
0
1
X
1
L
H
Reverse
X
0
1
1
L
L
Brake (slow decay)
1
0
0
1
L
H
Fast decay SR*
0
0
0
1
H
L
Fast decay SR*
X
X
X
0
Hi-Z
Hi-Z
Sleep mode
* To prevent reversal of current during fast decay SR (synchronous rectification), the outputs
go to the high impedance state as the current approaches zero.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A3949
DMOS Full-Bridge Motor Driver
LB Package
N/C
1
16 N/C
MODE
2
15 VREG
PHASE
3
14 VCP
GND
4
13 GND
SLEEP
5
12 CP2
ENABLE
6
11
OUTA
7
10 OUTB
SENSE
8
9
Name
N/C
Description
CP1
VBB
Number
Not used
1
MODE
Logic input
2
PHASE
Logic input for direction control
3
Ground
4*
SLEEP
Logic input
5
ENABLE
Logic input
6
Output A for full bridge
7
Power return
8
Load supply voltage
9
OUTB
Output B for full bridge
10
CP1
Charge pump capacitor
11
CP2
Charge pump capacitor
12
GND
Ground
13*
VCP
Reservoir capacitor
14
Low side gate supply decoupler
15
Not used
16
GND
OUTA
SENSE
VBB
VREG
N/C
*These pins are internally connected.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A3949
DMOS Full-Bridge Motor Driver
LB 16-Pin SOICW
10.30
4º
1.27
0.65
16
0.27
7.50
10.30
9.50
A
0.84
2.25
1
2
B
0.25
16X
SEATING
PLANE
0.10 C
0.41
1.27
C
All dimensions nominal, not for tooling use
Dimensions in millimeters
(reference JEDEC MS-013 AA)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Pins 4 and 13 fused internally
SEATING PLANE
GAUGE PLANE
2.65 MAX
0.20
PCB Layout Reference View
A Terminal #1 mark area
B
Reference pad layout (reference IPC SOIC127P1030X265-16M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Copyright ©2003-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
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