A3950 Datasheet

A3950
DMOS Full-Bridge Motor Driver
Features and Benefits
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Description
Low RDS(on) outputs
Overcurrent protection
Motor lead short-to-supply protection
Short-to-ground protection
Sleep function
Synchronous rectification
Diagnostic output
Internal undervoltage lockout (UVLO)
Crossover-current protection
Designed for PWM (pulse width modulated) control of DC
motors, the A3950 is capable of peak output currents to ±2.8 A
and operating voltages to 36 V.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a DC motor with externally
applied PWM control signals. Internal synchronous rectification
control circuitry is provided to lower power dissipation during
PWM operation.
Internal circuit protection includes motor lead short-tosupply / short-to-ground, thermal shutdown with hysteresis,
undervoltage monitoring of VBB and VCP, and crossover-current
protection.
Packages:
Package LP, 16 pin TSSOP
with Exposed Thermal Pad
Package EU, 16 pin QFN
with Exposed Thermal Pad
The A3950 is supplied in a thin profile (<1.2 mm overall height)
16 pin TSSOP package (LP), and a very thin (0.75 mm nominal
height) QFN package. Both packages provide an exposed pad
for enhanced thermal dissipation, and are lead (Pb) free with
100% matte tin leadframe plating.
Approximate Scale 1:1
Typical Application Diagrams
5 kΩ
GND
SLEEP
VCP
VREG
PHASE
MODE
VDD
NFAULT
0.22 µF
25 V
A3950
EU Package
ENABLE
VBB
100 µF
50 V
CP2
CP1
VDD
5 kΩ
0.1 µF
50 V
VREG
MODE
VCP
PHASE
GND
SLEEP
A3950
LP Package
VBB
0.1 µF
50 V
0.1 µF
50 V
A3950DS, Rev. 7
CP2
OUTB
SENSE
Package LP
0.1 µF
50 V
GND
CP1
ENABLE
OUTA
Package EU
0.22 µF
25 V
NC
NFAULT
VBB
SENSE
OUTA
0.1 µF
50 V
GND
OUTB
NC
VBB
0.1 µF
50 V
100 µF
50 V
A3950
DMOS Full-Bridge Motor Driver
Selection Guide
Part Number
Packing
Package
A3950SLPTR-T
13 in. reel, 4000 pieces / reel
16 pin TSSOP with exposed thermal pad
A3950SEUTR-T
7 in. reel, 1500 pieces / reel
16 pin QFN with exposed thermal pad
Absolute Maximum Ratings
Characteristic
Symbol
Load Supply Voltage
VBB
Output Current
IOUT
Transient Output Current
IOUT
Sense Voltage
Notes
TW < 500 ns
VSENSE
VBB to OUTx
OUTx to SENSE
Logic Input Voltage
VIN
Operating Ambient Temperature
TA
Maximum Junction Temperature
Storage Temperature
Rating
Units
36
V
2.8
A
6
A
±500
mV
36
V
36
V
–0.3 to 7
V
–20 to 85
ºC
TJ(max)
150
ºC
Tstg
–40 to 125
ºC
Range S
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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2
A3950
DMOS Full-Bridge Motor Driver
Functional Block Diagram
0.1 µF
CP2
CP1
VCP
Charge
Pump
0.1 µF
VREG
VBB
Low-Side
Gate Supply
0.22 µF
25 V
Bias
Supply
MODE
0.1 µF
PHASE
100 µF
OUTA
Control Logic
VDD
Load Supply
OUTB
ENABLE
5 kΩ
SENSE
SLEEP
5 kΩ
NFAULT
UVLO
STB
STG
TSD Warning
GND
Pad
Motor Lead
Protection
VBB
OUTA
OUTB
SENSE
GND
Terminal List Table
Name
NFAULT
MODE
PHASE
GND
SLEEP
ENABLE
OUTA
SENSE
VBB
OUTB
CP1
CP2
VCP
VREG
NC
Pad
Number
EU
15
16
1
2, 12
3
4
6
7
8
9
10
11
13
14
5
–
LP
1
2
3
4,13
5
6
7
8
9
10
11
12
14
15
16
–
Description
Fault output, open drain
Logic input
Logic input for direction control
Ground
Logic input
Logic input
DMOS full-bridge output A
Power return
Load supply voltage
DMOS full-bridge output B
Charge pump capacitor terminal
Charge pump capacitor terminal
Reservoir capacitor terminal
Regulator decoupling terminal
No connection
Exposed pad for thermal dissipation connect to GND pins
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115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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3
A3950
DMOS Full-Bridge Motor Driver
ELECTRICAL CHARACTERISTICS at TJ = 25°C, VBB = 8 to 36 V, unless noted otherwise
Characteristics
Symbol
Test Conditions
fPWM < 50 kHz
Motor Supply Current
IBB
Charge pump on, outputs disabled
Sleep mode
VIH
PHASE, ENABLE, MODE Input
Voltage
VIL
VIH
SLEEP Input Voltage
VIL
IIH
VIN = 2.0 V
PHASE, MODE Input Current1
IIL
VIN = 0.8 V
IIH
VIN = 2.0 V
ENABLE Input Current
IIL
VIN = 0.8 V
IIH
VIN = 2.7 V
SLEEP Input Current
IIL
VIN = 0.8 V
NFAULT Output Voltage
VOL
Isink = 1.0 mA
Input Hysteresis, except SLEEP
VIHys
Source driver, IOUT = -2.8 A, TJ=25°C
Source driver, IOUT = -2.8 A, TJ=125°C
Output On Resistance
RDS(on)
Sink driver, IOUT = 2.8 A, TJ=25°C
Sink driver, IOUT = 2.8 A, TJ=125°C
Source diode, If = –2.8 A
Body Diode Forward Voltage1
Vf
Sink diode, If = 2.8 A
PWM, change to source or sink ON
Propagation Delay Time
tpd
PWM, change to source or sink OFF
Crossover Delay
tCOD
Protection Circuitry
UVLO Threshold
VUV
VBB increasing
UVLO Hysteresis
VUVHys
Overcurrent Threshold2
IOCP
Overcurrent Protection Period
tOCP
Thermal Warning Temperature
TJW
Temperature increasing
Thermal Warning Hysteresis
TJWHys Recovery = TJW – TJWHys
Thermal Shutdown Temperature
TJTSD
Temperature increasing
Thermal Shutdown Hysteresis
TJTSDHys Recovery = TJTSD – TJTSDHys
1For
Min. Typ. Max. Units
–
6
8.5
mA
–
3
4.5
mA
–
–
10
µA
2.0
–
–
V
–
–
0.8
V
2.7
–
–
V
–
–
0.8
V
–
<1.0
20
µA
–20 <–2.0 20
µA
–
40
100
µA
–
16
40
µA
–
27
50
µA
–
<1
10
µA
–
–
0.4
V
100 150 250
mV
–
0.35 0.48
Ω
–
0.55 0.8
Ω
–
0.3 0.43
Ω
–
0.45 0.7
Ω
–
–
1.4
V
–
–
1.4
V
–
600
–
ns
–
100
–
ns
–
500
–
ns
–
–
3
–
–
–
–
–
6.5
250
–
1.2
160
15
175
15
–
–
–
–
–
–
–
–
V
mV
A
ms
°C
°C
°C
°C
Value
Units
Preliminary: EU package, 4-layer PCB based on JEDEC standard
30
ºC/W
LP package, 4-layer PCB based on JEDEC standard
34
ºC/W
LP package, 2-layer PCB with 3.8 in.2 copper both sides, connected by
thermal vias
43
ºC/W
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
protection is tested at 25°C in a restricted range and guaranteed by characterization.
2Overcurrent
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic
Package Thermal Resistance
Symbol
RθJA
Test Conditions*
*Additional thermal data available on the Allegro Web site.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
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4
A3950
DMOS Full-Bridge Motor Driver
Timing Diagram: PWM Control
SLEEP
ENABLE
PHASE
MODE
VBB
VOUTA
0
VBB
VOUTB
0
IOUTX
0
A
1
2
3
4
5
6
7
VBB
8
9
VBB
1 5
6
OutA
OutB
3
2 4
7
OutA
OutB
8
9
A Charge pump and VREG power-on delay (≈200 µs)
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115 Northeast Cutoff, Box 15036
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5
A3950
DMOS Full-Bridge Motor Driver
Timing Diagram: Overcurrent Control
VOUTA
VOUTB High-Z
IPEAK
IOUTx
IOCP
ENABLE,
Source
or Sink
BLANK
Charge Pump
Counter
tBLANK
tOCP
NFAULT
Motor lead
short condition
Normal dc
motor capacitance
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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6
A3950
DMOS Full-Bridge Motor Driver
Functional Description
Device Operation. The A3950 is designed to operate one DC
motor. The output drivers are all low RDS(on) N-channel DMOS
drivers that feature internal synchronous rectification to reduce
power dissipation. PHASE and ENABLE inputs allow two-wire
control with an additional MODE pin for the brake function. A
low current Sleep mode is provided to minimize power consumption when the driver is disabled. In addition, the driver also has
built-in protection from short-to-ground, short-to-battery, and
shorted load events.
Logic Inputs. If logic inputs are pulled up to VDD , it is good
practice to use a high value pull-up resistor in order to limit current to the logic inputs should an overvoltage event occur. Logic
inputs include: SLEEP, MODE, PHASE, and ENABLE. The
voltage on any logic input cannot exceed the specified maximum
of 7 V.
VREG. This supply voltage is used to run the sink-side DMOS
outputs. VREG is internally monitored and in the case of a fault
condition, the outputs of the device are disabled. The VREG pin
should be decoupled with a 0.22 μF capacitor to ground.
Charge Pump. The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1 µF
ceramic monolithic capacitor should be connected between CP1
and CP2 for pumping purposes. A 0.1 µF ceramic monolithic
capacitor should be connected between VCP and VBB to act as a
reservoir to run the high-side DMOS devices. The VCP voltage
level is internally monitored and, in the case of a fault condition,
the outputs of the device are disabled.
Shutdown. In the event of a fault due to excessive junction
temperature, or low voltage on VCP or VREG, the outputs of
the device are disabled until the fault condition is removed. At
power-on the UVLO circuit disables the drivers.
Sleep Mode. Control input SLEEP is used to minimize power
consumption when the A3950 is not in use. This disables much
of the internal circuitry, including the regulator and charge pump.
A logic low setting puts the device into Sleep mode, and a logic
high setting allows normal operation. After coming out of Sleep
mode, provide a 1 ms interval before applying PWM signals, to
allow the charge pump to stabilize.
MODE. Control input MODE is used to toggle between fast
decay mode and slow decay mode. A logic high puts the device in
slow decay mode. Synchronous rectification is always enabled.
Braking. The braking function is implemented by driving the
device in slow decay mode via the MODE setting and applying
an enable chop command. Because it is possible to drive current
in both directions through the DMOS switches, this configuration
effectively shorts out the motor generated BEMF as long as the
ENABLE chop mode is asserted. The maximum current can be
approximated by VBEMF/RL. Care should be taken to insure that
the maximum ratings of the device are not exceeded in worse
case braking situations: high speed and high-inertia loads.
Diagnostic Output. The NFAULT pin signals a problem with
the chip via an open drain output. A motor fault, undervoltage
condition, or TJ > 160°C will drive the pin active low. This output
is not valid when SLEEP puts the device into minimum power
dissipation mode.
TSD. Two die temperature monitors are integrated on the chip.
As die temperature increases towards the maximum, a thermal
warning signal will be triggered at 160°C. This fault drives the
Control Logic Table1
Pin
1X
Function
PHASE
ENABLE
MODE
SLEEP
OUTA
OUTB
1
1
X
1
H
L
Forward
0
1
X
1
L
H
Reverse
X
0
1
1
L
L
Brake (slow decay)
1
0
0
1
L
H
Fast Decay Synchronous Rectification2
0
0
0
1
H
L
Fast Decay Synchronous Rectification2
X
X
X
0
Z
Z
Sleep Mode
indicates “don’t care,” Z indicates high impedance.
prevent reversal of current during fast decay synchronous rectification, outputs go to the high impedance state as the current approaches 0 A.
2To
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7
A3950
DMOS Full-Bridge Motor Driver
NFAULT low, but does not disable the operation of the chip. If
the die temperature increases further, to approximately 175°C, the
full-bridge outputs will be disabled until the internal temperature
falls below a hysteresis of 15°C.
Overcurrent Protection. Referring to the figures below, the
voltage on the output pins relative to supply are monitored to
ensure that the motor lead is not shorted to supply or ground.
If a short is detected, the full-bridge outputs are turned off, flag
NFAULT is driven low, and a 1.2 ms fault timer is started.
After this 1.2 ms period, tOCP , the device will then be allowed
to follow the input commands and another turn-on is attempted.
If there is still a fault condition, the cycle repeats. If, after tOCP
expires, it is determined that the short condition is not present, the
NFAULT pin is released and normal operation resumes.
2 µs / div.
2 A / div.
ISHORT
Fault asserted
NFAULT
Shorted load condition, output current waveform is shown along with the NFAULT output.
TOCP = 1.2 ms
200 µs / div.
2 A / div.
ISHORT
Fault asserted
NFAULT
Shorted load condition illustrating repetitive cycles with a 1.2 ms delay.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
A3950
DMOS Full-Bridge Motor Driver
Applications Information
Power Dissipation. First order approximation of power
dissipation in the A3950 can be calculated by first examining
the power dissipation in the full-bridge during each of the
operation modes. The A3950 features synchronous rectification, a feature that effectively shorts out the body diode by
turning on the low RDS(on) DMOS driver during the decay
cycle. This significantly reduces power dissipation in the
full-bridge. In order to prevent shoot-through, where both
VBB
source and sink driver are on at the same time, the A3950
implements a 500 ns typical crossover delay time. For this
period, the body diode in the decay current path conducts
the current until the DMOS driver turns on. This does affect
power dissipation and should be considered in high current,
high ambient temperature applications. In addition, motor
parameters and switching losses can add power dissipation
that could affect critical applications.
Drive Current. This current path is through source DMOS
driver, motor winding, and sink DMOS driver. Power dissipation is I2R loses in one source and one sink DMOS driver,
as shown in the following equation:
PD = I 2 ( RDS(on)Source + RDS(on)Sink )
1
3
2
1 Drive current
2 Fast decay with synchronous rectification (reverse)
3 Slow decay with synchronous rectification (brake)
Figure 1. Current Decay Patterns
(1)
Fast Decay with Synchronous Rectification. This
decay mode is equivalent to a phase change where the opposite drivers are switched on. When in fast decay, the motor
current is not allowed to go negative (direction change).
Instead, as the current approaches zero, the drivers turn off.
The power calculation is the same as the drive current calculation, equation 1:
Slow Decay SR (Brake Mode). In this decay mode, both
sink drivers turn on, allowing the current to circulate through
the sink drivers and the load. Power dissipation is I2R loses
in the two sink DMOS drivers:
PD = I 2 ( 2 × RDS(on)Sink )
(2)
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A3950
DMOS Full-Bridge Motor Driver
SENSE Pin. A low value resistor can be placed between the
SENSE pin and ground for current sensing purposes. To minimize ground-trace IR drops in sensing the output current level,
the current sensing resistor should have an independent ground
return to the star ground point. This trace should be as short as
possible. For low value sense resistors, the IR drops in the PCB
can be significant, and should be taken into account.
When selecting a value for the sense resistor be sure not to
exceed the maximum voltage on the SENSE pin of ±500 mV.
Ground. A star ground should be located as close to the A3950
as possible. The copper ground plane directly under the exposed
thermal pad makes a good location for the star ground point. The
exposed pad can be connected to ground for this purpose.
Layout. The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the
A3950 must be soldered directly onto the board. On the underside of the A3950 package is an exposed pad, which provides a
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
are used to transfer heat to other layers of the PCB.
The load supply pin, VBB, should be decoupled with an electrolytic capacitor (typically 100 µF) in parallel with a ceramic
capacitor placed as close as possible to the device. The ceramic
capacitors between VCP and VBB, connected to VREG, and
between CP1 and CP2, should be as close to the pins of the
device as possible, in order to minimize lead inductance.
VBB
VBB
C1
U1
GND
GND
VCP
VREG
PHASE
NFAULT
CVBB1
C2
MODE
C1
CP2
PAD
CP1
ENABLE
CVBB1
GND
A3950
EU Package
SLEEP
C3
VBB
SENSE
OUTA
OUTB
NC
C3
C2
GND
CVBB2
CVBB2
OUTA
OUTB
EU package shown
10
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115 Northeast Cutoff, Box 15036
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A3950
DMOS Full-Bridge Motor Driver
EU Package, 16 Pin QFN with Exposed Thermal Pad
0.35
4.00 ±0.15
0.65
16
16
1.15
1
A
1
2
2
4.00 ±0.15
2.15
3.80
2.15
3.80
17X
D
SEATING
PLANE
0.08 C
0.30 ±0.05
0.75 ±0.05
0.65
C
C
PCB Layout Reference View
For Reference Only
(reference JEDEC MO-220WGGC)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
0.40 ±0.10
B
2.15
2
1
C Reference land pattern layout (reference IPC7351
QFN65P400X400X80-17BM)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
16
2.15
11
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
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A3950
DMOS Full-Bridge Motor Driver
LP Package, 16 Pin TSSOP with Exposed Thermal Pad
0.45
5.00 ±0.10
16
+0.05
0.15 –0.06
0.65
16
4° ±4
1.70
B
4.40 ±0.10
3.00
6.40 ±0.20
0.60 ±0.15
A
1
6.10
(1.00)
2
3.00
16X
0.25
SEATING
PLANE
0.10 C
+0.05
0.25 –0.06
3.00
0.65
1.20 MAX
0.15 MAX
C
SEATING PLANE
GAUGE PLANE
1 2
3.00
C
PCB Layout Reference View
For Reference Only
(reference JEDEC MO-153 ABT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351 SOP65P640X110-17M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
12
Allegro MicroSystems, LLC
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A3950
DMOS Full-Bridge Motor Driver
Revision History
Revision
Revision Date
7
June 11, 2014
Description of Revision
Added Transient Output Current to Abs. Max. Ratings
Copyright ©2005-2014, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
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