Fujitsu Microelectronics Europe
Application Note
MCU-AN-300200-E-V13
F²MC-16FX FAMILY
16-BIT MICROCONTROLLER
ALL SERIES
I/O-PORT
APPLICATION NOTE
I/O-port
Revision History
Revision History
Date
2006-04-20
2006-12-05
2007-02-21
2007-08-02
Issue
V1.0, First release, MWi
V1.1, Reviewed the document and updated with review findings, MPi
V1.2, some clarifications added, MPi
V1.3, typos corrected; small clarifications, MPi
This document contains 21 pages.
MCU-AN-300200-E-V13
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© Fujitsu Microelectronics Europe GmbH
I/O-port
Warranty and Disclaimer
Warranty and Disclaimer
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts
its warranties and its liability for all products delivered free of charge (e.g. software include or
header files, application examples, target boards, evaluation boards, engineering samples of IC’s
etc.), its performance and any consequential damages, on the use of the Product in accordance with
(i) the terms of the License Agreement and the Sale and Purchase Agreement under which
agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying
written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu
Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the
Product and any consequential damages in cases of unauthorised decompiling and/or reverse
engineering and/or disassembling. Note that all these products are intended and must only be
used in an evaluation laboratory environment.
1.
Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in
accordance with the accompanying written materials for a period of 90 days form the date of
receipt by the customer. Concerning the hardware components of the Product, Fujitsu
Microelectronics Europe GmbH warrants that the Product will be free from defects in material
and workmanship under use and service as specified in the accompanying written materials
for a duration of 1 year from the date of receipt by the customer.
2.
Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability
and the customer’s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH´s
sole discretion, either return of the purchase price and the license fee, or replacement of the
Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in
original packing and without further defects resulting from the customer’s use or the transport.
However, this warranty is excluded if the defect has resulted from an accident not attributable
to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the
customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH.
3.
To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH
disclaims all other warranties, whether expressed or implied, in particular, but not limited to,
warranties of merchantability and fitness for a particular purpose for which the Product is not
designated.
4.
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH´s
and its suppliers´ liability is restricted to intention and gross negligence.
NO LIABILITY FOR CONSEQUENTIAL DAMAGES
To the maximum extent permitted by applicable law, in no event shall Fujitsu
Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever
(including but without limitation, consequential and/or indirect damages for personal
injury, assets of substantial value, loss of profits, interruption of business operation,
loss of information, or any other monetary or pecuniary loss) arising from the use of
the Product.
Should one of the above stipulations be or become invalid and/or unenforceable, the remaining
stipulations shall stay in full effect
© Fujitsu Microelectronics Europe GmbH
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I/O-port
Contents
Contents
REVISION HISTORY ............................................................................................................ 2
WARRANTY AND DISCLAIMER ......................................................................................... 3
CONTENTS .......................................................................................................................... 4
1 INTRODUCTION.............................................................................................................. 6
1.1
Key features ............................................................................................................ 6
2 THE I/O-PORT ................................................................................................................. 7
2.1
Block Diagram......................................................................................................... 7
2.2
Registers................................................................................................................. 8
2.3
2.2.1
Port Data Register (PDR) ........................................................................... 8
2.2.2
Data Direction Register (DDR) .................................................................... 8
2.2.3
Port Input Enable Register (PIER) ............................................................. 9
2.2.4
External Pin State Register (EPSR) ............................................................ 9
2.2.5
(Extended) Port Input Level Register (PILR, EPILR)................................. 9
2.2.6
Port Output Drive Register (PODR) and Port High Drive Register (PHDR) ... 9
2.2.7
Pull-up Control Register (PUCR) ................................................................. 9
Input Mode ............................................................................................................ 11
2.3.1
Digital Port Input ...................................................................................... 11
2.3.2
Resource Input ........................................................................................ 12
2.4
Pull-up control register........................................................................................... 13
2.5
Output-mode ......................................................................................................... 14
2.5.1
Digital Port Output ................................................................................... 14
2.5.2
Resource Output...................................................................................... 14
3 PORT INPUT / UNUSED PINS....................................................................................... 15
3.1
Port Input / Unused Pins........................................................................................ 15
4 TECHNICAL INFORMATION......................................................................................... 17
4.1
Hysteresis Inputs................................................................................................... 17
5 TIPS AND TRICKS ........................................................................................................ 18
5.1
Initial Value............................................................................................................ 18
5.2
Bit Instructions....................................................................................................... 18
5.3
RMW Instructions .................................................................................................. 18
6 ADDITIONAL INFORMATION ....................................................................................... 19
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Contents
LIST OF FIGURES ............................................................................................................. 20
LIST OF TABLES............................................................................................................... 21
© Fujitsu Microelectronics Europe GmbH
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Chapter 1 Introduction
1 Introduction
The I/O-port functionality is the simplest peripheral function of the Fujitsu 16FX
microcontroller.
Nevertheless, some details should be considered while programming.
This application note reflects the functionality and describes the different modes.
Please note that in this document each port number is given with the 2-digit placeholder “xy”.
“z” always means the bit position 0 – 7.
Example: “PDR02_P3” means Port 02 Bit 3.
1.1
Key features
•
Port direction settable
•
Usage of I/O Port or Resource Pin, both states readable
•
Input can be disabled, if corresponding pin is unused
•
Internal pull-up resistor can be enabled
•
Input level can be set to CMOS (0307), CMOS (0208), Automotive Hysteresis, and
TTL
•
Output drive strength can be set
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I/O-port
Chapter 2 The I/O-port
2 The I/O-port
BASIC FUNCTIONALITY OF THE I/O PORTS
2.1
Block Diagram
Figure 2-1 shows the internal block diagram of an external I/O-pin.
Up to 8 I/O-pins may be encapsulated into one port and one register set. The registers are
described below.
Internal data bus
Pull-up resistor
(about 50 kK)
Data register read
Data register
Data register write
Pin
Direction register
Direction register write
Direction register read
External pin state read
Resistor register
Resistor register write
Resistor register read
Figure 2-1: I/O-port block diagram
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I/O-port
Chapter 2 The I/O-port
2.2
Registers
2.2.1 Port Data Register (PDR)
This register contains the data bits, if the corresponding port acts as a simple digital output.
The contents are output, if the Port Direction Register is set to output mode.
Please note that a resource output control bit overwrites the PDR bit value.
PDRxy_Pz
0
1
Pin Function
Pin State Low (VSS)
Pin State High (VDD)
Table 2-1: PDR
The read value of PDR register depends on the following:
The corresponding bit in DDR register
The Current status of the resource that is connected to the same pin
The type of instruction used (Read/Read-modify-write)
The following table describes the above discussed behaviour:
DDR Value
0 (Input)
Resource
Output
Enabled
Disabled
1 (Output)
Enabled
Disabled
Pin Value
Value of
Resource Input
Port Input
Value of
Resource Output
Value of PDR
Read Value of
‘Read
Instructions’
Read Value of
‘Read-modifywrite
Instructions’
Input Pin State
Value of PDR
Input Pin State
Value of PDR
Value of PDR
Value of PDR
Value of PDR
Value of PDR
Table 2-2: Reading PDR
2.2.2 Data Direction Register (DDR)
This register contains the bit information of the corresponding pins if they should act as input
or output.
DDRxy_Dz
0
0
1
1
Resource Output
Disabled
Enabled
Disabled
Enabled
Pin Function
Port Input1
Resource Output
Port Output
Resource Output logically OR with Port Output
Table 2-3: DDR
1
Please note that an input always must be enabled by the PIER, regardless whether digital input or
resource input is used.
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I/O-port
Chapter 2 The I/O-port
2.2.3 Port Input Enable Register (PIER)
This registers enables the input functionality of a MCU pin. If a corresponding bit is set to “0”
(default value) the pin can be left unconnected regardless of the settings of all port and
resource registers.
PIERxy_IEz
Function
0
Digital Input disabled
1
Digital Input enabled
Table 2-4: PIER
2.2.4 External Pin State Register (EPSR)
This register always contains the state of the corresponding external pin.
Please note that the corresponding bit in the Port Input Enable Register must also be set to
“1”, otherwise the read-back value is undefined.
2.2.5 (Extended) Port Input Level Register (PILR, EPILR)
With these registers one of the following input levels can be chosen. The input level applies
to both pin input and resource input (e.g. TINn input of Reload Timer, INn input of Input
Capture).
PILRxy_ILz EPILRxy_EILz
0
0
1
0
0
1
1
1
Input Level
CMOS (0307)
Automotive Hysteresis
TTL
CMOS (0208)
VIL
0.3 VDD
0.5 VDD
0.8 V
0.2 VDD
VIH
0.7 VDD
0.8 VDD
2.1 V
0.8 VDD
Table 2-5: PILR, EPILR
2.2.6 Port Output Drive Register (PODR) and Port High Drive Register (PHDR)
With these registers the strength of the output current of a pin can be adjusted:
PHDRxy_HDz
0
0
1
PODRxy_ODz
0
1
X
Output Current
Normal Current
Reduced Current
High Current
Table 2-6: PODR, PHDR
High current outputs are only available with ports those provide the stepper motor
functionality i.e. Port 8, 9 and 10. It is driven by DVCC. It should be noted that the Output
Current also influences the slew rate and therefore EMI emission. The higher the output
current the more the slew rate and hence higher the EMI noise.
Please see datasheet for current values. The current values depend on VCC and DVCC
respectively.
2.2.7 Pull-up Control Register (PUCR)
These registers connect
PIERxy_IEz
Function
0
Digital Input disabled
1
Digital Input enabled
an internal pull-up resistor to a port pin.
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Chapter 2 The I/O-port
Pull-Up
Resistor
Disabled
Enabled
PUCRxy_PUz
0
1
Table 2-7: PUCR
The nominal value for this pull-up resistor is 50 kK. It may vary between 25 kK to 100 kK
depending upon the doping process and temperature.
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I/O-port
Chapter 2 The I/O-port
2.3
Input Mode
In general, if a pin should acts as a digital input, the corresponding bit in the Port Input
Enable Register (2.2.3) must be set to “1”.
2.3.1 Digital Port Input
The following example shows the register configuration that needs to be done on MB96340
Series, if a pin should act as a digital input:
PIER06_IE0 = 1;
DDR06_D0 = 0;
ADER0_ADE0 = 0;
//
//
//
//
port input enable
data direction - input
disable AN0 input that is shared with port 06
pin 0
As shown above, the resource input AN0 (Analog Input 0 of ADC) which shares port 06 pin 0
input has to be disabled for digital port input functionality.
After configuring a pin as digital port input, the level of the input pin can be determined as
follows:
if ( 1 == PDR06_P0 )
{
// do something
}
else
{
// do something
}
// if pin high?
// pin low
Additionally the level of the input pin can also be read out via the External Pin State Register
(2.2.4) as follows:
if ( 1 == EPSR06_PS0 )
{
// do something
}
else
{
// do something
}
// if pin high?
// pin low
Optionally the input level can be set via the (Extended) Port Input Level Register (2.2.5) as
follows:
PILR06_IL0 = 1;
// set input detection level as CMOS (0208)
EPILR06_EIL0 = 1; //
If the connected external source may change to high-Z state, please use an external pull-up
or –down resistor or set the corresponding bit in the Pull-up Control Register (2.2.7).
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Chapter 2 The I/O-port
2.3.2 Resource Input
The following example shows the register configuration that needs to be done on MB96340
Series, if a pin should act as resource input (ADC input AN0 in this case):
PIER06_IE0 = 1;
ADER0_ADE0 = 1;
// port input enable
// AN0 pin as analog input
Optionally the input level can be set via the (Extended) Port Input Level Register (2.2.5).
If the connected external source may change to high-Z state, please use an external pull-up
or –down resistor or set the corresponding bit in the Pull-up Control Register (2.2.7).
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I/O-port
Chapter 2 The I/O-port
2.4
Pull-up control register
All ports, while in input-mode, have the possibility to enable an internal pull-up resistor
(about 50 kK) by programming the Pull-up Control Register (2.2.7).
The initial value of “0” disconnects the internal pull-up resistor, writing “1” to the
corresponding bit-position in the PUCRxy enables the resistor.
If the port-pin is used as an output the value of the register-bit has no meaning and the pullup resistor is disabled (Exception: For I2C pins SDA and SCL, the setting remains. Also for
UART output SOT the internal pull-up can be used if not provided by line driver).
Enabled pull-up resistors will be disabled while the microcontroller is in stop mode or timer
mode, if the SPL bit of SMCR register is configured as 1 before entering these modes. The
resistor is also disabled if the pin is used as ADC input.
If the external pin is used by the external bus-interface, the internal pull-up resistor cannot be
used too.
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Chapter 2 The I/O-port
2.5
Output-mode
2.5.1 Digital Port Output
The following example shows the register configuration that needs to be done on MB96340
Series, if a pin should act as a digital output:
PIER08_IE1 = 1;
PDR08_P1 = 0;
DDR08_D1 = 1;
TMCSR0_OUTE = 0;
//
//
//
//
//
//
//
//
this configuration is required only if the external
pin status needs to be read via EPSR
clear output before setting the data direction,
this is required to guarantee the initial value
when the data direction is set as output
data direction - output
disable TOT0 output that is shared with port 08
pin 1
As shown above, the resource output TOT0 (Output of RLT0) which shares port 08 pin 1
output has to be disabled for digital port output functionality.
Optionally the output current strength can be set by the Port Output/High Drive Registers
(2.2.6) as follows:
PODR08_OD1 = 1;
PHDR08_HD1 = 0;
// reduced current output
//
2.5.2 Resource Output
The following register settings have to be done, if a pin should act as a resource output:
PIER08_IE1 = 1;
TMCSR0_OUTE = 1;
// this configuration is required only if the external
// pin status needs to be read via EPSR
// enable TOT0 output
Optionally the output current strength can be set by the Port Output/High Drive Registers
(2.2.6).
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I/O-port
Chapter 3 Port Input / Unused Pins
3 Port Input / Unused Pins
How to connect Input Port Pins and how to proceed with unused Pins
3.1
Port Input / Unused Pins
It is strongly recommended not to leave the pins unconnected, while they are switched to
input and are enabled. In this case those pins can enter a so-called floating state. This can
cause a high ICC current, which is adverse to low power modes. Also damage of the MCU
can happen.
Use the internal pull-up resistors in this case. If not, use external pull-up or pull-down
resistors to define the input-level.
The recommended way is to set the port input enable to “0”, if a port pin is
unconnected.
Never connect a potential divider with almost same resistor values.
Figure 3-1: Recommended Connections for Port Input and Unused Pins
Be careful with connection of input pins to other devices, which can go into High-Z states.
Always use internal pull-up or external pull-up or pull-down resistors in this case.
Outputs from external circuits should always be connected via a serial resistor to a MCU
input pin to prevent latch-up effects caused by under- or overshoots.
Debouncing and decoupling capacitors should always be chosen as smallest as possible. For
detailed information please refer the chapter 3.2 of Hardware Setup application note MCUAN-300223.
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Chapter 3 Port Input / Unused Pins
All pins are set to input disabled (i.e. corresponding DDR and PIER bits are 0) after any
reset.
Do not connect any input ports directly to VCC or VSS (GND)! Always use pull up or
down resistors.
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I/O-port
Chapter 4 Technical information
4 Technical information
ELECTRICAL CHARACTERISTICS OF THE INPUT HYSTERESIS
4.1
Hysteresis Inputs
A hysteresis describes the behaviour of an input pin where the input level at which ‘1’ is
detected, and the level at which ‘0’ is detected are different.
The levels are described in chapter 2.2.5.
Kindly note that the power supply current i.e. the power consumption of the device may
increase, while the input voltage is within the hysteresis area, however the input current of
the I/O pin remains constant.
Detected
Level
1
Hysteresis
0
VI [V]
0V
Vil
VIH
5V
Input
current
Clamping diode
Leakage current
VI [V]
5V
Power supply
current
Clamping diode
VI [V]
VIL
VIH
5V
Figure 4-1: Hysteresis
Port hysteresis input level (low-level) specified in the datasheet
Port hysteresis input level (high-level) specified in the datasheet
Real hysteresis area
© Fujitsu Microelectronics Europe GmbH
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Chapter 5 Tips and Tricks
5 Tips and Tricks
THIS CHAPTER GIVES SOME HINTS ON USING I/O PORTS
5.1
Initial Value
Ensure that the port-data is defined before the pin-direction is changed to output. Otherwise
undefined data might be output to the I/O-pin, until PDR00 is written.
PDR00 = 0x00;
DDR00 = 0xFF;
5.2
// define initial value before port 0 is set to output
// set port 0 to output, after initial value is defined
Bit Instructions
Use byte-instructions which will be executed faster instead of using bit instructions since all
bit instructions are essentially read-modify-write instructions.
5.3
RMW Instructions
Accessing to the Port Data Register (2.2.1) via a read-modify-write instruction always returns
the contents of the register itself during read cycle (of the same read-modify-write
instruction) regardless whether the resource output of the corresponding pin is enabled or
not.
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© Fujitsu Microelectronics Europe GmbH
I/O-port
Chapter 6 Additional Information
6 Additional Information
Information about FUJITSU Microcontrollers can be found on the following Internet page:
http://mcu.emea.fujitsu.com/
The software example related to this application note is:
96340_io
It can be found on the following Internet page:
http://mcu.emea.fujitsu.com/mcu_product/mcu_all_software.htm
© Fujitsu Microelectronics Europe GmbH
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I/O-port
List of Figures
List of Figures
Figure 2-1: I/O-port block diagram.......................................................................................... 7
Figure 3-1: Recommended Connections for Port Input and Unused Pins............................. 15
Figure 4-1: Hysteresis .......................................................................................................... 17
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I/O-port
List of Tables
List of Tables
Table 2-1: PDR ....................................................................................................................... 8
Table 2-2: Reading PDR ......................................................................................................... 8
Table 2-3: DDR ....................................................................................................................... 8
Table 2-4: PIER ..................................................................................................................... 9
Table 2-5: PILR, EPILR......................................................................................................... 9
Table 2-6: PODR, PHDR........................................................................................................... 9
Table 2-7: PUCR ................................................................................................................... 10
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