Fujitsu Microelectronics Europe
Application Note
MCU-AN-300201-E-V16
F²MC-16FX FAMILY
16-BIT MICROCONTROLLER
ALL SERIES
PROGRAMMABLE PULSE
GENERATOR
APPLICATION NOTE
PROGRAMMABLE PULSE GENERATOR
Revision History
Revision History
Date
2006-04-20
2006-05-23
2006-12-08
2007-02-21
2007-08-14
2008-01-04
2008-06-24
Issue
V1.0, First release, MWi
V1.1, Group diagram and example added
V1.2, Reviewed the document and updated with review findings, MPi
V1.3, Fixed typos and clarified various items, MPi
V1.4, Added list of tables and figures and fixed typos, MPi
V1.5, Fix document number in footer, PHu
V1.6; update information on PPG groups; add information about external pin
trigger; PHu
This document contains 20 pages.
MCU-AN-300201-E-V16
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© Fujitsu Microelectronics Europe GmbH
PROGRAMMABLE PULSE GENERATOR
Warranty and Disclaimer
Warranty and Disclaimer
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts
its warranties and its liability for all products delivered free of charge (e.g. software include or
header files, application examples, target boards, evaluation boards, engineering samples of IC’s
etc.), its performance and any consequential damages, on the use of the Product in accordance with
(i) the terms of the License Agreement and the Sale and Purchase Agreement under which
agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying
written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu
Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the
Product and any consequential damages in cases of unauthorised decompiling and/or reverse
engineering and/or disassembling. Note, all these products are intended and must only be used
in an evaluation laboratory environment.
1.
Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in
accordance with the accompanying written materials for a period of 90 days form the date of
receipt by the customer. Concerning the hardware components of the Product, Fujitsu
Microelectronics Europe GmbH warrants that the Product will be free from defects in material
and workmanship under use and service as specified in the accompanying written materials
for a duration of 1 year from the date of receipt by the customer.
2.
Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH´s entire liability
and the customer’s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH´s
sole discretion, either return of the purchase price and the license fee, or replacement of the
Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in
original packing and without further defects resulting from the customer’s use or the transport.
However, this warranty is excluded if the defect has resulted from an accident not attributable
to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the
customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH.
3.
To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH
disclaims all other warranties, whether expressed or implied, in particular, but not limited to,
warranties of merchantability and fitness for a particular purpose for which the Product is not
designated.
4.
To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH´s
and its suppliers´ liability is restricted to intention and gross negligence.
NO LIABILITY FOR CONSEQUENTIAL DAMAGES
To the maximum extent permitted by applicable law, in no event shall Fujitsu
Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever
(including but without limitation, consequential and/or indirect damages for personal
injury, assets of substantial value, loss of profits, interruption of business operation,
loss of information, or any other monetary or pecuniary loss) arising from the use of
the Product.
Should one of the above stipulations be or become invalid and/or unenforceable, the remaining
stipulations shall stay in full effect
© Fujitsu Microelectronics Europe GmbH
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MCU-AN-300201-E-V16
PROGRAMMABLE PULSE GENERATOR
Contents
Contents
REVISION HISTORY ............................................................................................................ 2
WARRANTY AND DISCLAIMER ......................................................................................... 3
CONTENTS .......................................................................................................................... 4
1 INTRODUCTION.............................................................................................................. 5
1.1
Key Features........................................................................................................... 5
2 THE PROGRAMMABLE PULSE GENERATOR.............................................................. 6
2.1
Block Diagram......................................................................................................... 6
2.2
Simplified Block Diagram......................................................................................... 7
2.3
PPG Grouping......................................................................................................... 8
2.4
Registers................................................................................................................. 9
2.4.1
PPG Control Status Register (PCN)............................................................ 9
2.4.2
General Control Register 1 (GCN1) .......................................................... 10
2.4.3
Lower General Control Register 2 (GCN2L).............................................. 10
2.4.4
Upper General Control Register 2 (GCN2H).............................................. 10
2.4.5
PPG Cycle Setting Register (PCSR) ......................................................... 11
2.4.6
PPG Duty Setting Register (PDUT)........................................................... 11
2.4.7
PPG Timer Register (PTMR)..................................................................... 11
2.5
PPG Counter Behaviour ........................................................................................ 11
2.6
Frequency Examples............................................................................................. 12
2.6.1
2.7
Accuracy of Duty Cycle............................................................................ 12
External Trigger..................................................................................................... 13
3 PPG EXAMPLES ........................................................................................................... 14
3.1
Basic PPG Functionality ........................................................................................ 14
3.2
Changing Clock Source......................................................................................... 14
3.3
Triggering by Reload Timer ................................................................................... 15
3.4
Synchronize PPG Group ....................................................................................... 16
4 ADDITIONAL INFORMATION ....................................................................................... 18
LIST OF FIGURES ............................................................................................................. 19
LIST OF TABLES............................................................................................................... 20
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© Fujitsu Microelectronics Europe GmbH
PROGRAMMABLE PULSE GENERATOR
Chapter 1 Introduction
1 Introduction
This application note reflects the functionality and describes the different modes of the
Programmable Pulse Generator. The PPG is a 16-bit down counter with selectable duty
cycle (counter value match for output pin state change).
1.1
Key Features
•
Selectable 16-bit reload value and 16-bit duty cycle
•
Actual count readable
•
Prescaler dividers: 1, 4, 16, 64
•
Frequency Range from 3.8 Hz to 8 MHz with Peripheral Clock at 16 MHz
•
Reload Timer 6 Underflow as Clock Source selectable (allows frequencies from
about 0.9 µHz (with maximum possible clock divider & period settings of PPG) to 4
MHz with Peripheral Clock at 16 MHz)
•
Accuracy of Duty Cycle up to 65536 steps (0.0015%)
•
Trigger Inputs with Edge Selection: External, Reload Timer 0 or 1, Internal
•
Output polarity and Clamped H/L selectable
•
Interrupt at Trigger, Counter Borrow, Duty Value Match, and Borrow or Match.
•
One Shot / PWM Mode
© Fujitsu Microelectronics Europe GmbH
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PROGRAMMABLE PULSE GENERATOR
Chapter 2 The Programmable Pulse Generator
2 The Programmable Pulse Generator
THE BASIC FUNCTIONALITY OF THE PPG
2.1
Block Diagram
Figure 2-1 shows the internal block diagram of a PPG channel.
n = Number of PPG
g = Group number of PPG
i = Index of PPG within the group
Figure 2-1: PPG Block Diagram
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© Fujitsu Microelectronics Europe GmbH
PROGRAMMABLE PULSE GENERATOR
Chapter 2 The Programmable Pulse Generator
2.2
Simplified Block Diagram
Period Value
Reload
Count
Clock
Down Counter
Borrow
Output
Value
Match
Invert
Pin
Latch
Buffer
Duty Value
Figure 2-2: Simplified PPG Block Diagram
© Fujitsu Microelectronics Europe GmbH
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PROGRAMMABLE PULSE GENERATOR
Chapter 2 The Programmable Pulse Generator
2.3
PPG Grouping
The following block diagram shows, how the PPGs are grouped.
Figure 2-3: Grouping of the PPGs
Different PPGs of this group can share one common trigger and clock source. The trigger
type of a group is controlled by corresponding GCN1n register. The clock source for PPGn to
PPGn+3 is controlled by corresponding GCN2n register.
Note, while using Reload Timer 0 or 1 as trigger source for all PPGs, all these PPGs can be
synchronized to this trigger source.
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© Fujitsu Microelectronics Europe GmbH
PROGRAMMABLE PULSE GENERATOR
Chapter 2 The Programmable Pulse Generator
2.4
Registers
2.4.1 PPG Control Status Register (PCN)
The PCN contains almost all control bits for the functionality of the PPG
Bit No.
Name
Explanation
15
CNTE
Count Enable
14
STGR
Software Trigger
13
MDSE
Mode Selection
12
RTRG
Restart Enable
11, 10
CKS1, 0
9
PGMS
8
-
7, 6
EGS1, 0
5
IREN
Interrupt Enable
4
IRQF
Interrupt Request Flag
3, 2
IRS1, 0
Counter Clock Selection
PPG Output Mask Selection
Undefined
Trigger Input Edge
Selection
Interrupt Cause Selection
Value
0
1
0
1
0
1
0
1
0, 0
0, 1
1, 0
1, 1
0
1
0, 0
0, 1
1, 0
1, 1
0
1
0
1
0, 0
0, 1
1, 0
1, 1
1
OE
Output Enable
0
OSEL
Output Polarity
0
1
0
1
Operation
PPG disabled
PPG enabled
No trigger
Trigger activated
Continuous Mode
One-Shot Operation
Disable Restart
Enable Restart
Clock selected by CKSEL
Clock selected by CKSEL / 4
Clock selected by CKSEL / 16
Clock selected by CKSEL / 64
No Output Mask
Output Mask (Clamped by
OSEL)
Always write 0
No Selection
Rising Edge
Falling Edge
Both Edges
Interrupt Disabled
Interrupt Enabled
Clear Interrupt Request
No Effect
Software or External Trigger
Counter Borrow
Counter matches Duty Value
Counter Borrow or Duty Value
match
Output Disabled
Output Enabled
Normal Polarity
Inverted Polarity
Table 2-1: PCN
© Fujitsu Microelectronics Europe GmbH
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PROGRAMMABLE PULSE GENERATOR
Chapter 2 The Programmable Pulse Generator
2.4.2 General Control Register 1 (GCN1)
The GCN1 consists of 4 blocks of Trigger Selection Control Bits. These blocks are related to
a group of 4 PPGs. The Trigger Activation works together with the EGS1-0 bits of the PPG
Control Status Register (2.4.1).
TSELi3 TSELi2 TSELi1 TSELi0 Activation Trigger Specification
EN0 Bit (GCN2 Register)
0
0
0
0
EN1 Bit (GCN2 Register)
0
0
0
1
EN2 Bit (GCN2 Register)
0
0
1
0
EN3 Bit (GCN2 Register)
0
0
1
1
0
1
0
0
16-Bit Reload Timer Output 0
0
1
0
1
16-Bit Reload Timer Output 1
1
0
0
0
External Trigger (Group*4 + 0)
1
0
0
1
External Trigger (Group*4 + 1)
1
0
1
0
External Trigger (Group*4 + 2)
1
0
1
1
External Trigger (Group*4 + 3)
All other settings
Disabled
Table 2-2: GCN1
Note, that “i” is the PPG number. It rises in foursome blocks from Bit#0 to Bit#15 in the
GCN1.
2.4.3 Lower General Control Register 2 (GCN2L)
The lower 4 Bits of the GCN2L contains the Trigger Level Control Bits.
EN0 … 3
0
1
Internal Triggers EN0 ... 3
Set Level to „L“
Set Level to „H“
Table 2-3: GCN2L
2.4.4 Upper General Control Register 2 (GCN2H)
The lower 4 Bits of the GCN2H contains the Prescaler Clock Source Selection Control Bits.
CKSEL0 … 3
0
1
Clock Source
CLKP1
Reload Timer 6
Table 2-4: GCN2H
Please consider that the CLKP1 frequency depends on the setting of the Peripheral Clock 1
Divider.
CKFCRH_PC1D[3:0]
CLKS1
Peripheral Clock 1
Divider (div-1 to div-16)
CLKP1
to PPG
Figure 2-4: PPG Clock
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© Fujitsu Microelectronics Europe GmbH
PROGRAMMABLE PULSE GENERATOR
Chapter 2 The Programmable Pulse Generator
2.4.5 PPG Cycle Setting Register (PCSR)
This 16-Bit register contains the period value for a PPG channel.
2.4.6 PPG Duty Setting Register (PDUT)
This 16-Bit register contains the duty time in which the PPG changes its output. Please set a
value smaller than the PCSR cycle for normal PPG operation. If these values are equal, the
PPG output is “H”, if OSEL=0 or “L”, if OSEL=1 (OSEL is Bit#0 of PCN: 2.4.1).
2.4.7 PPG Timer Register (PTMR)
This 16-Bit register is the counter of the PPG. Read access returns the current counter
value.
2.5
PPG Counter Behaviour
The following diagram shows, how the PPG works in the basic mode (free running, no
trigger):
Counter
Value
(PTMR)
PCSR
Match
PDUT
Underflow
PPG
Output
Figure 2-5: PPG Behaviour
The non-inverted PPG output is set to “L” if an underflow of the counter value occurs. After
this, the period value (PCSR) is reloaded. The PPG output is set to “H”, if the duty cycle value
(PDUT) matches the actual counter value.
© Fujitsu Microelectronics Europe GmbH
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Chapter 2 The Programmable Pulse Generator
2.6
Frequency Examples
The following table shows some frequency settings for PPG clocked by CLKP1.
CKS1, 0
Division
CLKP1
1
4
16 MHz
16
64
1
4
24 MHz
16
64
1
4
50 MHz
16
64
Period Value
PCSR
0xFFFF
0x0001
0xFFFF
0x0001
0xFFFF
0x0001
0xFFFF
0x0001
0xFFFF
0x0001
0xFFFF
0x0001
0xFFFF
0x0001
0xFFFF
0x0001
0xFFFF
0x0001
0xFFFF
0x0001
0xFFFF
0x0001
0xFFFF
0x0001
Period
Time
4.096 ms
125 ns
16.38 ms
500 ns
65.54 ms
2 Ps
262 ms
8 Ps
2.731 ms
83.3 ns
10.92 ms
333.3 ns
43.69 ms
1.33 Ps
174.7 ms
5.33 Ps
1.311 ms
40 ns
5.243 ms
160 ns
20.97 ms
0.64 Ps
83.8 ms
2.56 Ps
Period
Frequency
244.1 Hz
8 MHz
61 Hz
2 MHz
15.3 Hz
500 kHz
3.8 Hz
125 kHz
366.2 Hz
12 MHz
91.6 Hz
3 MHz
22.9 Hz
750 kHz
5.7 Hz
187.5 kHz
763 Hz
25 MHz
190.7Hz
6.25 MHz
47.7 Hz
1.56 MHz
11.92 Hz
390.63 kHz
Granulation
Time
62.5 ns
250 ns
1 Ps
4 Ps
41.7 ns
166.7 ns
0.67 Ps
2.67 Ps
20 ns
80 ns
0.32 Ps
1.28 Ps
Table 2-5: Frequency Settings
The formula for the PPG frequency fPPG using fCLKP1 (CLKP1) as clock source is:
f PPG =
f CLKP1
divCKS 1, 0 (P + 1)
, where divCKS1,0 is the CKS1,0 division factor and P the Period Value
Note, that CLKP1 can also be divided by the settings in the Peripheral Clock 1 Divider, so
that for high System Clocks (CLKS1) low frequencies for PPG can be used.
For low frequencies it is also possible to use Reload Timer 6 as a prescaler. The formula for
the resulting PPG frequencies is:
f PPG =
divCKS 1, 0
f CLKP1
divFSEL (P + 1) (R + 1)
, where divFSEL is the division factor of the
Reload Timer and R the Period Value
2.6.1 Accuracy of Duty Cycle
The accuracy of the duty cycle depends on the used period value caused on the resulting
granularity.
The formula for the accuracy a in per cent is:
a=
MCU-AN-300201-E-V16
1
100%
P +1
, where P is the Period Value
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© Fujitsu Microelectronics Europe GmbH
PROGRAMMABLE PULSE GENERATOR
Chapter 2 The Programmable Pulse Generator
2.7
External Trigger
Any PPG channel can be triggered by an edge on a port pin. It can be selected which on of
the up to 4 trigger pins of a group is assigned to the PPG channels. This is done by the
GCN1n and GCN2n registers.
Please note that the trigger pin works as an input pin. All input pins must be enabled by the
respective PIER register.
Example:
PPG1 shall be triggered by pin TTG3. Pin TTG3 shares port pin P02_7.
The remaining configuration is arbitrarily selected as follows:
•
Period length: 4096 CLKP1 cycles
•
Duty length: 2048 CLKP1 cycles
•
Output pin enabled
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
void InitPPG0(void)
{
PCSR0 = 0x0FFF;
PDUT0 = 0x07FF;
PIER02_IE7 = 1;
GCN11 = 321B
}
PCNL0 = 0x02;
PCNH0 = 0x90;
//
//
//
//
//
//
//
always set cycle value PERIOD 1st
set duty value DUTY CYCLE
enable input on P02_7, TTG3
setting PPG1 trigger to TTG3; other settings as
initial values
Output enable
Count enable, Retrigger, CLK - no div
© Fujitsu Microelectronics Europe GmbH
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Chapter 3 PPG Examples
3 PPG Examples
EXAMPLES FOR PPG OPERATION
3.1
Basic PPG Functionality
The following code shows how to initialize the PPG for basic operation.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
void InitPPG0(void)
{
PCSR0 = 0x1000;
PDUT0 = 0x0800;
PCNL0 = 0x02;
PCNH0 = 0xD0;
}
//
//
//
//
always set cycle value PERIOD 1st
set duty value DUTY CYCLE
Output enable
Count enable, S-Trigger, Retrigger, CLK - no div
This example code generates a PPG signal with a duty cycle of 50%. The output frequency
depends on the MCU clock settings. Here it is clock source (CKSEL) divided by 0x1000 +
1. For a frequency of 16 MHz for CLKP1, the resulting PPG frequency is 3905 Hz.
3.2
Changing Clock Source
The PPG can be clocked by CLKP1 or Reload Timer 6. The following example shows how to
operate the PPG with the Reload Timer.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
void InitReloadTimer6(void)
{
TMRLR6 = 0x0001;
// set reload value
TMCSR6 = 0x1013;
// prescaler 1:1, no interrupts
}
void InitPPG0(void)
{
PCSR0 = 0x1000;
PDUT0 = 0x0800;
PCNL0 = 0x02;
PCNH0 = 0xD0;
GCN2H0 = 0x01;
}
MCU-AN-300201-E-V16
//
//
//
//
//
always set cycle value PERIOD 1st
set duty value DUTY CYCLE
Output enable
Count enable, SW-Trigger, Retrigger, CLK - no div
Clock Source: Reload Timer 6
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© Fujitsu Microelectronics Europe GmbH
PROGRAMMABLE PULSE GENERATOR
Chapter 3 PPG Examples
3.3
Triggering by Reload Timer
The PPG can be triggered by Reload Timer 0 or 1. The following example shows how to
trigger the PPG with the Reload Timer. Note that the PPG is in single shot mode.
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
void InitReloadTimer0(void)
{
TMRLR0 = 0x2000;
// set reload value
TMCSR0 = 0x1053;
// prescaler 1:1, no interrupts, output enable
}
void InitPPG0(void)
{
PCSR0 = 0x1000;
PDUT0 = 0x0A00;
PCNL0 = 0x42;
PCNH0 = 0xB0;
}
GCN1L0 = 0x04;
//
//
//
//
//
//
always set cycle value PERIOD 1st
set duty value DUTY CYCLE
Trigger rising edge, Output enable
Count enable, One Shot, Retrigger,
CLK - no div
Trigger Source: Reload Timer 0
The generated waveforms look like the following graphic.
PPG0
TOT0
PPG
Low Phase
PPG
High Phase
Reload Timer Cycle
Trigger
Figure 3-1: Timing Diagram
© Fujitsu Microelectronics Europe GmbH
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PROGRAMMABLE PULSE GENERATOR
Chapter 3 PPG Examples
3.4
Synchronize PPG Group
If you initialize the PPGs sequentially, but with the same frequency, the starting falling edges
(no inversion) of each channel will have a phase shift.
PPG0
PPG1
PPG2
PPG3
Figure 3-2: Timing Diagram of Phase Shift
It is possible to synchronize 4 PPG channels with the Internal Triggers.
To synchronize 4 channels, set the EGSn Bits of the PPG Control Status Registers (PCNn) to
rising edge. Set all 4 channel Trigger Selections to EN0 by setting the General Control
Register (GCN1n) to 0x0000. The sequence GCN2Ln = 0x00 and GCN2Ln = 0x01
creates a rising edge on ENn.
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© Fujitsu Microelectronics Europe GmbH
PROGRAMMABLE PULSE GENERATOR
Chapter 3 PPG Examples
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES.
*/
/*
(C) Fujitsu Microelectronics Europe GmbH
*/
/*---------------------------------------------------------------------------*/
void InitPPG0(void)
{
PCSR0 = 0x0FFF;
PDUT0 = 0x0700;
PCNL0 = 0x42;
PCNH0 = 0xD0;
}
PCSR1
PDUT1
PCNL1
PCNH1
=
=
=
=
0x0FFF;
0x0400;
0x42;
0xD0;
PCSR2
PDUT2
PCNL2
PCNH2
=
=
=
=
0x0FFF;
0x0900;
0x42;
0xD0;
PCSR3
PDUT3
PCNL3
PCNH3
=
=
=
=
0x0FFF;
0x0800;
0x42;
0xD0;
//
//
//
//
always set cycle value PERIOD 1st
set duty value DUTY CYCLE
Rising edge trigger, Output enable
Count enable, SW-Trigger, Retrigger, CLK - no div
GCN10 = 0x0000;
// PPG0 -> EN0, PPG1 -> EN0, ...
GCN2L0 = 0x00;
GCN2L0 = 0x01;
// Generate Rising Edge
// Trigger EN0
© Fujitsu Microelectronics Europe GmbH
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PROGRAMMABLE PULSE GENERATOR
Chapter 4 Additional Information
4 Additional Information
Information about FUJITSU Microcontrollers can be found on the following Internet page:
http://mcu.emea.fujitsu.com/
The software examples related to this application note is:
96340_ppg0
96340_ppg0_rlt6
96340_ppg0_rlt0_trg
96340_ppg_rlt_adc_dma
It can be found on the following Internet page:
http://mcu.emea.fujitsu.com/mcu_product/mcu_all_software.htm
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© Fujitsu Microelectronics Europe GmbH
PROGRAMMABLE PULSE GENERATOR
List of Figures
List of Figures
Figure 2-1: PPG Block Diagram ............................................................................................. 6
Figure 2-2: Simplified PPG Block Diagram............................................................................. 7
Figure 2-3: Grouping of the PPGs.......................................................................................... 8
Figure 2-4: PPG Clock ......................................................................................................... 10
Figure 2-5: PPG Behaviour .................................................................................................. 11
Figure 3-1: Timing diagram .................................................................................................. 15
Figure 3-2: Timing diagram of phase shift ............................................................................ 16
© Fujitsu Microelectronics Europe GmbH
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PROGRAMMABLE PULSE GENERATOR
List of Tables
List of Tables
Table 2-1: PCN ....................................................................................................................... 9
Table 2-2: GCN1 ................................................................................................................... 10
Table 2-3: GCN2L ................................................................................................................. 10
Table 2-4: GCN2H ................................................................................................................. 10
Table 2-4: Frequency Settings ............................................................................................. 12
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© Fujitsu Microelectronics Europe GmbH