bq24308 www.ti.com SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 Overvoltage and Overcurrent Protection IC and Li+ Charger Front-End Protection IC Check for Samples :bq24308 FEATURES APPLICATIONS • • • • • • 1 2 • • • • • • Provides Protection for Three Variables: – Input Overvoltage – Input Overcurrent with Current Limiting – Battery Overvoltage 30V Maximum Input Voltage Supports Up to 1.5A Input Current Robust Against False Triggering Due to Current Transients Thermal Shutdown LDO Mode Voltage Regulation of 5V Small 2 mm × 2 mm 8-Pin SON Package Mobile and Smart Phones PDAs MP3 Players Low-Power Handheld Devices Bluetooth Headsets DESCRIPTION The bq24308 is a highly integrated circuit designed to provide protection to Li-ion batteries from failures of the charging circuit. The IC continuously monitors the input voltage, the input current and the battery voltage. In case of an input over-voltage condition, the IC immediately removes power from the charging circuit by turning off an internal switch. In the case of an over-current condition, it limits the current to a safe value for a blanking duration before turning the switch off. Battery voltage may also be monitored and if the battery voltage exceeds the specified value the internal switch is turned off. Additionally, the IC also monitors its own die temperature and switches off if it becomes too hot. The input over-current threshold can be increased using an external resistor. The IC also offers optional protection against reverse voltage at the input using an external P-channel FET. PINOUT TYPICAL APPLICATION CIRCUIT IN 1 8 OUT VSS 2 7 ILIM bq24308 PGATE 3 NC 4 6 VBAT 5 CE 5 CE 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated bq24308 SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE DISSIPATION RATINGS (1) PACKAGE RθJC RθJA DSG 5°C/W (1) 75°C/W This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. The pad is connected to the ground plane by a 2x3 via matrix. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Input voltage Input current Output current ESD Withstand voltages VALUE UNIT IN, PGATE (with respect to VSS) –0.3 to 30 V OUT (with respect to VSS) –0.3 to 12 V ILIM, CE, VBAT (with respect to VSS) –0.3 to 7 V IN 2.0 A OUT 2.0 A PGATE 5 mA All (Human body Model per JESD22-A114-E) 2000 V All (Machine Model per JESD22-A115-A) 200 V All (Charged Device Model per JESD22-C101-C) 500 V 15 (Air discharge) 8 (Contact) kV Junction temperature, TJ –40 to 150 °C Storage temperature, TSTG –65 to 150 °C IN (IEC 61000-4-2) (with IN pin bypassed to VSS with 1.0-µF low-ESR ceramic capacitor) (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN 3.3 MAX UNIT VIN Input voltage range 26 V IIN Input current, IN pin 1.5 A IOUT Current, OUT pin 1.5 A RILIM OCP programming resistor TJ Junction temperature 31 –40 kΩ 125 °C ORDERING INFORMATION 2 PART NUMBER MARKING MEDIUM QUANTITY PACKAGE bq24308DSGR DAS Tape and Reel 3000 2mm × 2mm SON bq24308DSGT DAS Tape and Reel 250 2mm × 2mm SON Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 bq24308 www.ti.com SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 ELECTRICAL CHARACTERISTICS over junction temperature range –40°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IN VUVLO Under-voltage lock-out, input power detected threshold CE= Low, VIN: 0 V → 3 V 2.5 2.7 2.8 V VHYS-UVLO Hysteresis on UVLO CE= Low, VIN: 3 V → 0 V 200 260 300 mV tDGL(PGOOD) Deglitch time, input power detected status CE = Low. Time measured from VIN 0V → 4V 1 µs rise-time, to output turning ON IDD Operating current CE= Low, VIN = 5 V, no load on OUT pin 410 500 μA ISTDBY Standby current CE= High, VIN = 5 V 65 95 μA CE = Low, VIN = 4 V, IOUT = 250 mA 45 75 mV 8 ms INPUT TO OUTPUT CHARACTERISTICS VDO Drop-out voltage IN to OUT INPUT OVER-VOLTAGE PROTECTION VOVP Input over-voltage protection threshold CE= Low, VIN: 4 V → 10 V 6.1 6.3 6.5 V VHYS-OVP Hysteresis on OVP CE= Low, VIN: 10 V → 4 V 20 60 110 mV tPD(OVP) Input OVP propagation delay (1) CE= Low, Time measured from VIN 4 V → 10 V, 1µs rising time, to output turning OFF 0.2 1 μs tON(OVP) Recovery time from input overvoltage condition CE = Low, Time measured from VIN 10 V → 4V, 1 µs fall-time, to output turning ON 8 ms OUTPUT VOLTAGE REGULATION VO(REG) Output voltage CE = Low, VIN= 6 V, IOUT = 250 mA 4.85 5.0 5.15 V CE= Low, VIN = 5V, ILIM floating; TJ = 0°C to 125°C 630 700 770 mA 1500 mA INPUT OVER-CURRENT PROTECTION IOCP Internal input over-current protection threshold Input over-current protection range CE = Low, VIN = 5V; TJ = 0°C to 125°C ΔIOCP OCP threshold accuracy KILIM Current limit programming: IOCP(program) = IOCP + KILIM ÷ RILIM tBLANK(OCP) Blanking time, input over-current detected tREC(OCP) Recovery time from input over-current condition 630 TJ = 0°C to 125°C ±10% TJ = –40°C to 125°C ±13% 25000 AΩ CE= Low 5 ms CE = Low 64 ms BATTERY OVER-VOLTAGE PROTECTION BVOVP Battery overvoltage protection threshold CE = Low, VIN > 4.4 V, VVBAT: 4.2 V → 4.5 V 4.30 4.35 4.40 V VHYS-BOVP Hysteresis on BVOVP CE= Low, VIN > 4.4 V, VVBAT: 4.5 V → 3.9 V 200 275 320 mV IVBAT Input bias current on VBAT pin VVBAT = 4.4 V, TJ = 25°C 10 nA tDGL(BOVP) Deglitch time, battery overvoltage detected CE= Low, VIN > 4.4 V, time measured from VVBAT 4.2 V → 4.5 V, 1µs rising time, to output turning OFF 176 µs THERMAL PROTECTION TJ(OFF) Thermal shutdown temperature TJ(OFF-HYS) Thermal shutdown hysteresis 140 150 20 °C °C P-FET Gate Driver VGCLMP (1) Gate driver clamp voltage VIN >17V 13 15 17 V Not tested in production. Specified by design. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 3 bq24308 SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over junction temperature range –40°C ≤ TJ ≤ 125°C and recommended supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC LEVELS ON CE VIL Low-level input voltage 0 VIH High-level input voltage 1.4 IIL Low-level input current IIH High-level input current 0.4 V 1 μA 15 μA V VCE = 1.8 V AC Adapter VDC CIN GND 1 IN OUT 8 1 mF COUT Charging Circuit 1 mF bq24308 SYSTEM ILIM 5 7 VSS CE VBAT 6 2 RILIM Optional Figure 1. Overvoltage, Overcurrent, and Battery Overvoltage Protection QEXT AC Adapter VDC GND 100 KΩ CIN 1 IN 1 μF OUT 8 COUT 1 μF 3 PGATE bq24080 Charger IC bq24308 SYSTEM 100 KΩ VBAT 6 RBAT 7 ILIM VSS 47 KΩ RILIM Optional CE 5 2 RCE Figure 2. OVP, OCP, BATOVP With Input Reverse-Polarity Protection 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 bq24308 www.ti.com SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 Q1 IN Charge Pump, Bandgap, Bias Gen OUT V REF VISNS VREF VREF Current limiting loop VO(REG)Loop V REF ILIM OFF OCP Comparator VREF - Δ tBLANK(OCP) VI SNS VIN VVLIM CONTROL AND STATUS OVP Comparator tBLANK(OVP) VIN VREF CE tDGL(PGOOD) UVLO VBAT PGATE level shift THERMAL VREF SHUTDOWN tDGL(BOVP) VIN VGCLMP VSS Figure 3. Simplified Block Diagram Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 5 bq24308 SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 www.ti.com PIN FUNCTIONS PIN NAME NO. IN I/O DESCRIPTION 1 I Input power, connect to external DC supply. Connect external 0.1μF (minimum) ceramic capacitor to VSS 8 O Output terminal to the charging system. Connect external 1μF capacitor (minimum) ceramic capacitor to VSS VBAT 6 I Battery voltage sense input. Connect to pack positive terminal through a resistor. NC 4 – Do not connect to any external circuit. This pin may have internal connections used for test purpose. 7 I Input over-current threshold programming. An optional external resistor can be used to increase input over-current threshold. Connect a resistor to VSS to increase the OCP threshold. OUT ILIM VSS 2 – Ground terminal PGATE 3 O Gate drive for optional external P-FET CE 5 I Chip enable input. Active low. When CE= High, the input FET is off. Internally pulled down. - There is an internal electrical connection between the exposed thermal pad and the VSS pin of the device. The thermal pad must be connected to the same potential as the VSS pin on the printed circuit board. Do not use the thermal pad as the primary ground input for the device. VSS pin must be connected to ground at all times. ThermalPAD 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 bq24308 www.ti.com SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 TYPICAL OPERATING PERFORMANCE Test conditions (unless otherwise noted) for typical operating performance are: VIN = 5 V, CIN = 1 μF, COUT = 1μF, RBAT = 100 kΩ, ROUT = 16Ω, TA = 25°C (see Figure 1 - Typical Application Circuit) VIN VIN VOUT tDGL(PGOOD) VOUT IOUT IOUT Figure 4. Normal Power-On Showing Soft-Start. VIN 0 V to 6.0 V, tR = 20μs Figure 5. Power-On with Input Overvoltage. VIN 0 V to 12.0 V, tR = 50 μs 8.8V 8.4V VIN IN 6.4V 5.92V VOUT Figure 6. bq24308 OVP Response for Input Step. VIN 5 V to 8 V, tR = 3μs. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 7 bq24308 SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL OPERATING PERFORMANCE VIN < VUVLO VIN < VOVP VVININ VIN < VO(REG) VIN tON(OVP) VOUT VOUT VOUT Figure 7. OUT Pin Response to Slow Input Ramp. Figure 8. bq24308 Recovery from Input OVP. VIN 8 V to 5 V, tF = 100 μs ROUT = 16W VOUT VIN ROUT = 2.8W IOUT limited to 700mA IOUT tREC(OCP) IOUT tBLANK(OCP) Figure 9. OCP, Powering up with OUT Pin Shorted to VSS 8 Figure 10. OCP, Showing Current Limiting, ROUT 16 Ω to 2.8 Ω Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 bq24308 www.ti.com SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 TYPICAL OPERATING PERFORMANCE (continued) ROUT = 16W VVOUT OUT ROUT = 2.8W VOUT VOUT IOUT limited to 700mA IOUT IOUT tBLANK(OCP) Figure 11. OCP, Showing Current Limiting and OCP Blanking. ROUT 16 Ω to 2.8 Ω Figure 12. Zoom-in on Turn-off Region of Figure 11, Showing Soft-Stop VVBAT tDGL(BOVP) VOUT Figure 13. Battery OVP. VVBAT Steps from 4.3 V to 4.5 V. Shows tDGL(BOVP) and Soft-Stop Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 9 bq24308 SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL OPERATING PERFORMANCE (continued) UNDERVOLTAGE LOCKOUT vs FREE-AIR TEMPERATURE DROPOUT VOLTAGE (IN to OUT) vs FREE-AIR TEMPERATURE 70 2.75 2.7 60 VIN Increasing VIN = 5 V 50 VDO @ 250 mA - mV VUVLO, VHYS-UVLO - V 2.65 2.6 2.55 2.5 40 30 20 VIN Decreasing 10 2.45 2.4 -50 -30 -10 10 30 50 70 Temperature - °C 90 110 0 -50 130 0 50 Temperature - °C Figure 14. Figure 15. REGULATION VOLTAGE (OUT pin) vs FREE-AIR TEMPERATURE OVP THRESHOLD vs FREE-AIR TEMPERATURE 100 150 100 150 5.07 6.34 6.32 VOVP VHYS-OVP - V VO - Output Voltage - V 5.05 5.03 5.01 6.3 VIN Increasing 6.28 6.26 6.24 VIN Decreasing 4.99 6.22 4.97 -50 0 50 Temperature - °C 100 150 6.2 -50 Figure 16. 10 0 50 Temperature - °C Figure 17. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 bq24308 www.ti.com SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 TYPICAL OPERATING PERFORMANCE (continued) OCP THRESHOLD vs FREE-AIR TEMPERATURE BATTERY OVP THRESHOLDS vs FREE-AIR TEMPERATURE 695 4.4 690 4.35 BVOVP (VVBAT Increasing) 685 4.3 BVOVP - V IOCP - mA 680 675 4.25 4.2 670 4.15 665 4.1 660 655 -50 0 50 Temperature - °C 100 Bat-OVP Recovery (VVBAT Decreasing) 4.05 -50 150 -30 -10 10 30 50 70 Temperature - °C Figure 18. Figure 19. LEAKAGE CURRENT (BAT pin) vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs INPUT VOLTAGE 90 110 130 1200 2.5 CE = L 1000 2 IDD, ISTDBY - mA IVBAT - nA 800 1.5 1 600 400 CE = H 200 0.5 0 0 -50 0 50 Temperature - °C 100 150 -200 0 5 10 15 20 25 30 35 VIN - V Figure 20. Figure 21. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 11 bq24308 SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 www.ti.com TYPICAL OPERATING PERFORMANCE (continued) PGATE VOLTAGE vs INPUT VOLTAGE 18 16 14 VPGATE - V 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 VIN - V Figure 22. 12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 bq24308 www.ti.com SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 DETAILED FUNCTIONAL DESCRIPTION The bq24308 is a highly integrated circuit designed to provide protection to Li-ion batteries from failures of the charging circuit. The IC continuously monitors the input voltage, the input current and the battery voltage. In case of an input over-voltage condition, the IC immediately removes power from the charging circuit by turning off an internal switch. In the case of an over-current condition, it limits the current to a safe value for a blanking duration before turning the switch off. Additionally, the IC also monitors its own die temperature and switches off if it becomes too hot. The input and over-current threshold is user-programmable. The IC can be controlled by a processor using the CE pin. POWER DOWN The device remains in power down mode when the input voltage at the IN pin is below the under-voltage lock-out threshold, VUVLO. The FET Q1 (see Figure 3) connected between IN and OUT pins is off. POWER-ON RESET The device resets all internal timers when the input voltage at the IN pin exceeds the UVLO threshold. The gate driver for the external P-FET is enabled. The IC then waits for duration tDGL(PGOOD) for the input voltage to stabilize. If, after tDGL(PGOOD), the input voltage and battery voltage are safe, FET Q1 is turned ON. The IC has a soft-start feature to control the inrush current. This soft-start minimizes voltage ringing at the input (the ringing occurs because the parasitic inductance of the adapter cable and the input bypass capacitor form a resonant circuit). Figure 4 shows the power-up behavior of the device. Because of the deglitch time at power-on, if the input voltage rises rapidly to beyond the OVP threshold, the device will not switch on at all, as shown in Figure 5. OPERATION The device continuously monitors the input voltage, the input current and the battery voltage as described in detail in the following sections. Input Overvoltage Protection If the input voltage rises above VOVP, the internal FET Q1 is turned off, removing power from the circuit. As shown in Figure 6 to Figure 7, the response is very rapid, with the FET turning off in less than a microsecond. When the input voltage returns below VOVP – Vhys(OVP) (but is still above UVLO), the FET Q1 is turned on again after a deglitch time of tON(OVP) to ensure that the input supply has stabilized. Figure 8 shows the recovery from input OVP. Input Overcurrent Protection The device can supply load current up to IOCP continuously. If the load current tries to exceed this threshold, the current is limited to IOCP for a maximum duration of tBLANK(OCP). If the load current returns to less than IOCP before tBLANK(OCP) times out, the device continues to operate (see Figure 9). However, if the overcurrent situation persists for tBLANK(OCP), FET Q1 is turned off for a duration of tREC(OCP). It is then turned on again and the current is monitored all over again (see Figure 10 and Figure 11). To prevent the input voltage from spiking up due to the inductance of the input cable, Q1 is not turned off rapidly in an overcurrent fault condition. Instead, the gate drive of Q1 is reduced slowly, resulting in a "soft-stop", as shown in Figure 12. The over-current threshold can be programmed to level greater than IOCP by connecting a resistor R(ILIM) from the ILIM pin to VSS. The programmed over-current threshold is given by IOCP(program) = IOCP + KILIM ÷ R(ILIM). Battery Overvoltage Protection The battery overvoltage threshold BVOVP is internally set to 4.35V. If the battery voltage exceeds the BVOVP threshold for longer than tDGL(BOVP), FET Q1 is turned off (see Figure 13). This switch-off is also a soft-stop. Q1 is turned ON (soft-start) once the battery voltage drops to BVOVP – VHYS-BOVP. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 13 bq24308 SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 www.ti.com Thermal Protection If the junction temperature of the device exceeds TJ(OFF), FET Q1 is turned off. The FET is turned back on when the junction temperature falls below TJ(OFF) – TJ(OFF-HYS). Enable Function The IC has an enable pin which can be used to enable or disable the device. When the CE pin is driven high, the internal FET is turned off. When the CE pin is low, the FET is turned on if other conditions are safe. The CE pin has an internal pull-down resistor of 200 kΩ (typical) and can be left floating. 14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 bq24308 www.ti.com SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 Any State If VIN < VUVLO, go to Power Down Power Down All IC functions OFF VIN > VUVLO? No Yes Reset Timers reset Q1 off Turn on PGATE No CE = Low ? Yes VIN < VOVP ? Turn off Q1 No Yes I < IOCP ? Turn off Q1 No Wait tREC(OCP) Yes VVBAT < BVOVP ? Turn off Q1 No Yes TJ < TJ(OFF) ? No Turn off Q1 Yes Turn on Q1 Figure 23. State Diagram Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 15 bq24308 SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 www.ti.com APPLICATION INFORMATION Selection of RBAT: It is strongly recommended that the battery not be tied directly to the VBAT pin of the device, as under some failure modes of the IC, the voltage at the IN pin may appear on the VBAT pin. This voltage can be as high as 30V, and applying 30V to the battery in case of the failure of the device can be hazardous. Connecting the VBAT pin through RBAT prevents a large current from flowing into the battery in case of failure of the IC. In the interests of safety, RBAT should have a very high value. The problem with a large RBAT is that the voltage drop across this resistor because of the VBAT bias current IVBAT causes an error in the BVOVP threshold. This error is over and above the tolerance on the nominal 4.35V BVOVP threshold. Choosing RBAT in the range 100KΩ to 470kΩ is a good compromise. In the case of IC failure, with RBAT equal to 100kΩ, the maximum current flowing into the battery would be (30V – 3V) ÷ 100kΩ = 270μA, which is low enough to be absorbed by the bias currents of the system components. RBAT equal to 100kΩ would result in a worst-case voltage drop of RBAT X IVBAT ≈ 1mV. This is negligible compared to the internal tolerance of 50mV on the BVOVP threshold. If the Bat-OVP function is not required, the VBAT pin should be connected to VSS. Selection of RCE: The CE pin can be used to enable and disable the IC. If host control is not required, the CE pin can be tied to ground or left un-connected, permanently enabling the device. In applications where external control is required, the CE pin can be controlled by a host processor. As in the case of the VBAT pin (see above), the CE pin should be connected to the host GPIO pin through a resistor as large as possible. The limitation on the resistor value is that the minimum VOH of the host GPIO pin less the drop across the resistor should be greater than VIH of the bq24308 CE pin. The drop across the resistor is given by RCE X IIH. Selection of Input and Output Bypass Capacitors: The input capacitor CIN in Figure 1 and Figure 2 is for decoupling, and serves an important purpose. Whenever there is a step change downwards in the system load current, the inductance of the input cable causes the input voltage to spike up. CIN prevents the input voltage from overshooting to dangerous levels. It is strongly recommended that a ceramic capacitor of at least 1μF be used at the input of the device. It should be located in close proximity to the IN pin. COUT in Figure 1 and Figure 2 is also important: If a very fast (< 1µs rise-time) overvoltage transient occurs at the input, the current that charges COUT causes the device’s current-limiting loop to kick in, reducing the gate-drive to FET Q1. This results in improved performance for input overvoltage protection. COUT should also be a ceramic capacitor of at least 1µF, located close to the OUT pin. COUT also serves as the input decoupling capacitor for the charging circuit downstream of the protection IC. PCB Layout Guidelines: 1. This device is a protection device, and is meant to protect down-stream circuitry from hazardous voltages. Potentially, high voltages may be applied to this IC. It has to be ensured that the edge-to-edge clearances of PCB traces satisfy the design rules for the maximum voltages expected to be seen in the system. 2. The device uses SON packages with a PowerPAD™. For good thermal performance, the PowerPAD should be thermally coupled with the PCB ground plane. In most applications, this will require a copper pad directly under the IC. This copper pad should be connected to the ground plane with an array of thermal vias. 3. CIN and COUT should be located close to the IC. Other components like RBAT should also be located close to the IC. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 bq24308 www.ti.com SLUS977A – SEPTEMBER 2009 – REVISED NOVEMBER 2009 REVISION HISTORY NOTE: Page numbers of current version may differ from previous versions. Changes from Original (September 2009) to Revision A Page • Changed Units from V to A for Input and Output Current spec in Absolute Maximum Ratings table. ................................. 2 • Added ESD Withstand voltage specifications to Absolute Maximum Ratings table. ............................................................ 2 • Changed VO(REG) test condition, IOUT value from 50 mA to 250 mA ...................................................................................... 3 • Added TJ = 0°C to 125°C to test conditions for IOCP spec. ................................................................................................... 3 • Changed QEXT device symbol in the Input Reverse-Polarity Protection schematic. ............................................................. 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :bq24308 17 PACKAGE OPTION ADDENDUM www.ti.com 29-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty BQ24308DSGR ACTIVE SON DSG 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ24308DSGT ACTIVE SON DSG 8 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Oct-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BQ24308DSGR SON DSG 8 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 BQ24308DSGT SON DSG 8 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Oct-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ24308DSGR SON DSG 8 3000 195.0 200.0 45.0 BQ24308DSGT SON DSG 8 250 195.0 200.0 45.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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