ds91230-ds07-16506-3e.pdf

FUJITSU MICROELECTRONICS
DATA SHEET
DS07–16506–3E
32-bit Microcontroller
CMOS
FR60Lite MB91230 Series
MB91233L/F233A/F233L/V230
■ DESCRIPTION
The MB91230 series is a line of standard microcontrollers, based on a 32-bit high-performance RISC CPU
(FR* family) and containing variety of I/O resources, for embedded control applications which require high
CPU performance at high speed processing.
Audio motor control storage : Designed to specifications for embedded control applications which high CPU
performance power processing.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of Fujitsu Microelectronics Limited.
■ FEATURES
• 32-bit RISC, load/store architecture with a 5 stage pipeline
• Maximum operating frequency: 33.6 MHz (oscillation frequency = 4.2 MHz, oscillation frequency 8-multiplier (PLL clock multiplication method) )
• 16-bit fixed length instructions (basic instructions)
• Execution speed of instructions : 1 instruction per cycle
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2004-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.11
MB91230 Series
(Continued)
• Memory-to-memory transfer, bit handling, and barrel shift instructions, etc. : Instructions suitable for embedded applications
• Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for
C-language
• Register interlock function : Facilitates coding in assembler
• Built-in multiplier with instruction-level support
- 32-bit multiplication with sign : 5 cycles
- 16-bit multiplication with sign : 3 cycles
• Interrupt (PC and PS save) : 6 cycles (16 priority levels)
• Harvard architecture allowing program access and data access to be executed simultaneously
• Instruction compatible with FR family
• Capacity of built-in ROM and ROM type
- MASK ROM
: 256 Kbytes
- Flash ROM
: 256 Kbytes
• Capacity of built-in RAM : 16 Kbytes
• General-purpose ports : Maximum 98 ports (including N-ch open-drain port : 4 ports)
• A/D converter (series-parallel type)
- Resolution : 10-bit : 8 channels (4 channels × 2 units)
- Conversion time : 1.69 µs (Minimum conversion time)
• D/A converter (R-2R type)
- Resolution : 8-bit : 2 channels (independence)
- Conversion speed : 0.6 µs (when load capacitance 20 pF)
• External interrupt input : 16 channels
• Bit search module (for REALOS)
- Function for searching the MSB (Upper bit) in each word for the first “0” or “1” inverted point
• UART (full-duplex double buffer) : 4 channels
- Selectable parity On/Off
- Asynchronous (start-stop synchronized) or clock-synchronous communications selectable
- Internal timer for dedicated baud rate (U-timer) on each channel
- External clock can be used as transfer clock
- Error detection function for parity, frame and overrun
• PPG : 16-bit × 6 channels
• Up/down counter : 2 channels (8-bit × 2 channels or 16-bit × 1 channel)
• Reload timer : 16-bit × 4 channels
• Free-run timer : 16-bit × 2 channels
• Watch timer : 15-bit × 1 channel
• PWC : 8-bit × 2 channels
• Input capture : 2 channels (interface with free-run timer 0)
• Output compare : 4 channels (free-run timer 0 and output compare units 0/1 cooperate, free-run timer 1
and output compare units 2/3)
• LCD controller : SEG0 to SEG31/COM0 to COM3 (also serving as a port)
• Clock monitor (peripheral clock output function) : 1 channel
• Timebase/watchdog timer (26-bit)
• Real-time clock (counting even with the real-time clock stopped)
• Low Power Consumption Mode
• Sleep/stop function
• Package : LQFP-120, FLGA-128
• Technology : CMOS 0.35 µm
• Power supply
• Dual power supply configuration [internal logic 3.3 V, I/O 5.5 V(3.3 V for A/D converter and D/A converter
input/output)]
Note : Do not set the external bus mode in which the MB91230 series cannot operate.
2
DS07–16506–3E
MB91230 Series
■ PIN ASSIGNMENT
• MB91233L, MB91F233A, MB91F233L
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
P25/SOT2
P24/SIN2
P23/PWI1/OP3
P22/PWI0/OP2
P21/CKI1/OP1
P20/CKI0/OP0
P17/INT7
P16/INT6
P15/INT5
P14/INT4
P13/INT3
P12/INT2
X0
X1
VSS
VCC
P11/INT1
P10/INT0
P07/IC1
P06/IC0
P05/SCK1
P04/SOT1
P03/SIN1
P02/SCK0
P01/SOT0
P00/SIN0
V3
V2
V1
V0
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
LQFP-120
INIT
MD0
MD1
MD2
P73/COM3
P72/COM2
P71/COM1
P70/COM0
P67/SEG31∗
P66/SEG30∗
P65/SEG29∗
P64/SEG28∗
PB3/SEG27
PB2/SEG26
VSS
VCC
PB1/SEG25
PB0/SEG24
PA7/SEG23
PA6/SEG22
PA5/SEG21
PA4/SEG20
PA3/SEG19
PA2/SEG18
PA1/SEG17
PA0/SEG16
P97/SEG15
P96/SEG14
P95/SEG13
P94/SEG12
P57/INT15/TIN0/ADTG0
PF3/TOT3
PF4/TIN3/ADTG1
PD0/DA0
PD1/DA1
AVCC
AVRH
AVSS
PC0/AN0
PC1/AN1
PC2/AN2
PC3/AN3
PC4/AN4
PC5/AN5
PC6/AN6
PC7/AN7
VSS
VCC3IO
P80/SEG0
P81/SEG1
P82/SEG2
P83/SEG3
P84/SEG4
P85/SEG5
P86/SEG6
P87/SEG7
P90/SEG8
P91/SEG9
P92/SEG10
P93/SEG11
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
P26/SCK2
P27/SIN3
P30/SOT3
P31/SCK3
P32/AIN0
P33/BIN0
P34/ZIN0
P35/AIN1
P36/BIN1
P37/ZIN1
P40/PPG0
P41/PPG1
X0A
X1A
VCC3B
VSS
VCC3
P42/PPG2
P43/PPG3
P44/TOT0
P45/TOT1
P46/TOT2
P47/CKOT
P50/INT8
P51/INT9
P52/INT10
P53/INT11/PPG4
P54/INT12/PPG5
P55/INT13/TIN2
P56/INT14/TIN1
* : Open-drain
(FPT-120P-M24)
(Continued)
DS07–16506–3E
3
MB91230 Series
(Continued)
• MB91233L, MB91F233L
M
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10 M11 M12
L
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
K
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
J
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
H
H1
H2
H3
H4
H9
H10
H11
H12
G
G1
G2
G3
G4
G9
G10
G11
G12
BOTTOM VIEW
F
F1
F2
F3
F4
F9
F10
F11
F12
E
E1
E2
E3
E4
E9
E10
E11
E12
D
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
C
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
B
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
A
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
1
2
3
4
5
6
7
8
9
10
11
12
INDEX
(LGA-128P-M01)
4
DS07–16506–3E
MB91230 Series
Pin correspondence table of LQFP-120 and FLGA-128 in MB91230 series
FLGAFLGA-128
LQFP128 No.
Signal
LQFPNo.
Signal
LQFP120 No.
(JEDEC
name
120 No.
(JEDEC
name
120 No.
No.)
No.)
FLGA-128
No.
(JEDEC
No.)
Signal
name
1
A1
P26/SCK2
98
C9
P03/SIN1
18
G1
P42/PPG2
120
A2
P25/SOT2
93
C10
V2
15
G2
VCC3B
117
A3
P22/PWI0/
OP2
85
C11
P72/COM2
*2
G3*4
VCC3*4
114
A4
P17/INT7
87
C12
MD2
17
G4
VCC3
⎯
A5
*5
10
D1
P37/ZIN1
71
G9
PA6/
SEG22
109
A6
P12/INT2
6
D2
P33/BIN0
75
G10
VCC
107
A7
X1
8
D3
P35/AIN1
74
G11
PB1/
SEG25
103
A8
P10/INT0
119
D4
P24/SIN2
77
G12
PB2/
SEG26
100
A9
P05/SCK1
111
D5
P14/INT4
21
H1
P45/TOT1
97
A10
P02/SCK0
⎯
D6
*
19
H2
P43/PPG3
94
A11
V3
101
D7
P06/IC0
23
H3
P47/CKOT
91
A12
V0
95
D8
P00/SIN0
20
H4
P44/TOT0
4
B1
P31/SCK3
89
D9
MD0
65
H9
PA0/
SEG16
118
B2
P23/PWI1/
OP3
86
D10
P73/COM3
72
H10
PA7/
SEG23
115
B3
P20/CKI0/
OP0
82
D11
P67/
SEG31*1
69
H11
PA4/
SEG20
112
B4
P15/INT5
84
D12
P71/COM1
73
H12
PB0/
SEG24
110
B5
P13/INT3
13
E1
X0A
24
J1
P50/INT8
106
B6
VSS
9
E2
P36/BIN1
22
J2
P46/TOT2
104
B7
P11/INT1
12
E3
P41/PPG1
26
J3
P52/INT10
99
B8
P04/SOT1
5
E4
P32/AIN0
29
J4
P55/
INT13/
TIN2
96
B9
P01/SOT0
81
E9
P66/
SEG30*1
35
J5
PD1/DA1
92
B10
V1
83
E10
P70/COM0
40
J6
PC1/AN1
88
B11
MD1
80
E11
P65/
SEG29*1
47
J7
VSS
90
B12
INIT
⎯
E12
*5
50
J8
P81/SEG1
5
(Continued)
DS07–16506–3E
5
MB91230 Series
(Continued)
LQFP120 No.
FLGA128 No.
(JEDEC
No.)
Signal
name
LQFP120 No.
FLGA128 No.
(JEDEC
No.)
Signal
name
LQFP-120
No.
FLGA-128
No.
(JEDEC
No.)
Signal
name
7
C1
P34/ZIN0
16
F1
VSS
59
J9
P92/
SEG10
2
C2
P27/SIN3
⎯
F2
*5
68
J10
PA3/
SEG19
3
C3
P30/
SOT3
14
F3
X1A
66
J11
PA1/
SEG17
116
C4
P21/CKI1/
OP1
11
F4
P40/PPG0
70
J12
PA5/
SEG21
113
C5
P16/INT6
78
F9
PB3/
SEG27
27
K1
P53/
INT11/
PPG4
108
C6
X0
79
F10
P64/
SEG28*1
25
K2
P51/INT9
105
C7
VCC
76
F11
VSS
33
K3
PF4/TIN3/
ADTG1
102
C8
P07/IC1
⎯
F12
*5
38
K4
AVSS
41
K5
PC2/AN2
36
L4
AVCC
37
M3
AVRH
44
K6
PC5/AN5
*3
L5*4
AVRL*4
39
M4
PC0/AN0
48
K7
VCC3IO
43
L6
PC4/AN4
42
M5
PC3/AN3
53
K8
P84/
SEG4
45
L7
PC6/AN6
46
M6
PC7/AN7
56
K9
P87/
SEG7
49
L8
P80/SEG0
⎯
M7
*5
63
K10
P96/
SEG14
52
L9
P83/SEG3
51
M8
P82/SEG2
62
K11
P95/
SEG13
55
L10
P86/SEG6
54
M9
P85/SEG5
67
K12
PA2/
SEG18
58
L11
P91/SEG9
57
M10
P90/SEG8
30
L1
P56/
INT14/
TIN1
64
L12
P97/
SEG15
60
M11
P93/
SEG11
28
L2
P54/
INT12/
PPG5
31
M1
P57/
INT15/
TIN0/
ADTG0
61
M12
P94/
SEG12
32
L3
PF3/
TOT3
34
M2
PD0/DA0
*1 : Open-drain
*2 : Connected to pin 17(VCC3) on the LQFP product
*3 : Connected to pin 38(AVSS) on the LQFP product
*4 : Signals added to the FLGA product
*5 : NC pin on the FLGA product
6
DS07–16506–3E
MB91230 Series
■ PIN DESCRIPTION
Pin no.
LQFP
FLGA
Pin name
I/O circuit
type
SCK2
1
2
A1
D
General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.
SIN3
UART3 data input.
When using this function, corresponding bit of DDR2
register is set to input.
C2
D
General purpose input/output port.
This function is always valid.
SOT3
4
5
6
7
8
UART2 clock input/output.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.
P26
P27
3
Description
C3
B
UART3 data output.
This function is valid when corresponding bit of PFR3
register is set to peripheral function.
P30
General purpose input/output port.
This function is valid when corresponding bit of PFR3
register is set to port function.
SCK3
UART3 clock input/output.
This function is valid when corresponding bit of PFR3
register is set to peripheral function.
B1
B
P31
General purpose input/output port.
This function is valid when corresponding bit of PFR3
register is set to port function.
AIN0
Up/down counter 0 AIN input.
When using this function, corresponding bit of DDR3
register is set to input.
E4
B
P32
General purpose input/output port.
This function is always valid.
BIN0
Up/down counter 0 BIN input.
When using this function, corresponding bit of DDR3
register is set to input.
D2
B
P33
General purpose input/output port.
This function is always valid.
ZIN0
Up/down counter 0 ZIN input.
When using this function, corresponding bit of DDR3
register is set to input.
C1
B
P34
General purpose input/output port.
This function is always valid.
AIN1
Up/down counter 1 AIN input.
When using this function, corresponding bit of DDR3
register is set to input.
D3
B
P35
General purpose input/output port.
This function is always valid.
(Continued)
DS07–16506–3E
7
MB91230 Series
Pin no.
LQFP
FLGA
Pin name
I/O circuit
type
BIN1
9
10
E2
B
General purpose input/output port.
This function is always valid.
ZIN1
Up/down counter 1 ZIN input.
When using this function, corresponding bit of DDR3
register is set to input.
D1
B
General purpose input/output port.
This function is always valid.
PPG0
12
F4
D
General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.
PPG1
PPG1 output.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
E3
D
13
E1
X0A
14
F3
X1A
15
G2
16
17
General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.
K
Sub-clock oscillation pins (32 kHz)
VCC3B
⎯
Power supply pin for backup (RTC)
F1
VSS
⎯
Power supply pin (GND)
G4
VCC3
⎯
Power supply pin (3.3 V internal logic)
PPG2
19
PPG0 output.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
P40
P41
18
Up/down counter 1 BIN input.
When using this function, corresponding bit of DDR3
register is set to input.
P36
P37
11
Description
G1
D
PPG2 output.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
P42
General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.
PPG3
PPG3 output.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
H2
D
P43
General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.
(Continued)
8
DS07–16506–3E
MB91230 Series
Pin no.
LQFP
FLGA
Pin name
I/O circuit
type
TOT0
20
21
22
23
24
25
H4
D
Reload timer 0 output port.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
P44
General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.
TOT1
Reload timer 1 output port.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
H1
D
P45
General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.
TOT2
Reload timer 2 output port.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
J2
D
P46
General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.
CKOT
Clock monitor function output pin.
This function is valid when corresponding bit of PFR4
register is set to peripheral function.
H3
D
P47
General purpose input/output port.
This function is valid when corresponding bit of PFR4
register is set to port function.
INT8
External interrupt input.
When using this function, corresponding bit of DDR5
register is set to input.
J1
C
P50
General purpose input/output port.
This function is always valid.
INT9
External interrupt input.
When using this function, corresponding bit of DDR5
register is set to input.
K2
C
General purpose input/output port.
This function is always valid.
P51
INT10
26
Description
J3
C
P52
External interrupt input.
When using this function, corresponding bit of DDR5
register is set to input.
General purpose input/output port.
This function is always valid.
(Continued)
DS07–16506–3E
9
MB91230 Series
Pin no.
LQFP
27
28
29
30
FLGA
K1
L2
J4
L1
Pin name
I/O circuit
type
Description
PPG4
PPG4 output.
This function is valid when corresponding bit of PFR5
register is set to peripheral function.
INT11
External interrupt input.
This function is enabled when corresponding bit of
PFR5 register is set to port function and corresponding
bit of DDR5 resister is set to input.
C
P53
General purpose input/output port.
This function is valid when corresponding bit of PFR5
register is set to port function.
PPG5
PPG5 output.
This function is valid when corresponding bit of PFR5
register is set to peripheral function.
INT12
External interrupt input.
This function is enabled when corresponding bit of
PFR5 register is set to port function and corresponding
bit of DDR5 resister is set to input.
C
P54
General purpose input/output port.
This function is valid when corresponding bit of PFR5
register is set to port function.
TIN2
Reload timer 2 event input pin.
This function is valid when corresponding bit of DDR5
register is set to input.
INT13
C
External interrupt input.
This function is valid when corresponding bit of DDR5
register is set to input.
P55
General purpose input/output port.
This function is always valid.
TIN1
Reload timer 1 event input pin.
This function is valid when corresponding bit of DDR5
register is set to input.
INT14
P56
C
External interrupt input.
This function is valid when corresponding bit of DDR5
register is set to input.
General purpose input/output port.
This function is always valid.
(Continued)
10
DS07–16506–3E
MB91230 Series
Pin no.
LQFP
31
FLGA
Pin name
I/O circuit
type
ADTG0
External trigger input pin of A/D converter 0.
This function is valid when corresponding bit of DDR5 register is set to input.
TIN0
Reload timer 0 event input pin.
This function is valid when corresponding bit of DDR5 register is set to input.
M1
C
External interrupt input.
This function is valid when corresponding bit of DDR5 register is set to input.
INT15
General purpose input/output port.
This function is always valid.
P57
TOT3
32
33
34
L3
K3
D
Reload timer 3 output port.
This function is valid when corresponding bit of PFRF
register is set to peripheral function.
PF3
General purpose input/output port.
This function is valid when corresponding bit of PFRF
register is set to port function.
ADTG1
External trigger input pin of A/D converter 1.
This function is valid when corresponding bit of DDRF
register is set to input.
TIN3
D
Reload timer 3 event input pin.
This function is valid when corresponding bit of DDRF
register is set to input.
PF4
General purpose input/output port.
This function is always valid.
DA0
D/A converter 0 output pin.
This function is valid when corresponding bit of PFRD
register is set to peripheral function.
M2
35
Description
F
PD0
General purpose input/output port.
This function is valid when corresponding bit of PFRD
register is set to port function.
DA1
D/A converter 1 output pin.
This function is valid when corresponding bit of PFRD
register is set to peripheral function.
J5
F
PD1
General purpose input/output port.
This function is valid when corresponding bit of PFRD
register is set to port function.
36
L4
AVCC
⎯
Analog power supply (for A/D, D/A converter) .
37
M3
AVRH
⎯
Analog reference power supply (for A/D, D/A converter) .
38
K4
AVSS
⎯
GND level input for analog circuit (for A/D, D/A converter) .
(Continued)
DS07–16506–3E
11
MB91230 Series
Pin no.
LQFP
39 to 46
FLGA
M4, J6, K5,
M5, L6, K6,
L7, M6
Pin name
I/O
circuit
type
AN0 to AN7
E
PC0 to PC7
Description
Analog input pins for A/D converter.
This function is valid when corresponding bit of PFRC
register is set to peripheral function.
General purpose input/output ports.
This function is valid when corresponding bit of PFRC
register is set to port function.
47
J7
VSS
⎯
Power supply pin (GND)
48
K7
VCC3IO
⎯
Power supply pin (analog-shared pin I/O)
49 to 56
57 to 64
65 to 72
73, 74
L8, J8, M8,
L9, K8, M9,
L10, K9
M10, L11, J9,
M11, M12,
K11, K10, L12
H9, J11, K12,
J10, H11, J12,
G9, H10
SEG0 to
SEG7
I
LCD controller/driver LCD segment output pins.
This function is valid when corresponding bit of PFR8
register is set to peripheral function.
P80 to P87
General purpose input/output ports.
This function is valid when corresponding bit of PFR8
register is set to port function.
SEG8 to
SEG15
LCD controller/driver LCD segment output pins.
This function is valid when corresponding bit of PFR9
register is set to peripheral function.
I
P90 to P97
General purpose input/output ports.
This function is valid when corresponding bit of PFR9
register is set to port function.
SEG16 to
SEG23
LCD controller/driver LCD segment output pins.
This function is valid when corresponding bit of PFRA
register is set to peripheral function.
I
PA0 to PA7
General purpose input/output ports.
This function is valid when corresponding bit of PFRA
register is set to port function.
SEG24,
SEG25
LCD controller/driver LCD segment output pins.
This function is valid when corresponding bit of PFRB
register is set to peripheral function.
H12, G11
I
PB0, PB1
General purpose input/output ports.
This function is valid when corresponding bit of PFRB
register is set to port function.
Power supply pin (5 V I/O MB91V230/F233A)
75
G10
VCC
⎯
Power supply pin (3.3 V internal logic, I/O
MB91F233L/MB91233L)
76
F11
VSS
⎯
Power supply pin (GND)
SEG26,
SEG27
77, 78
G12, F9
I
PB2, PB3
LCD controller/driver LCD segment output pins.
This function is valid when corresponding bit of PFRB
register is set to peripheral function.
General purpose input/output ports.
This function is valid when corresponding bit of PFRB
register is set to port function.
(Continued)
12
DS07–16506–3E
MB91230 Series
Pin no.
LQFP
79 to 82
83 to 86
FLGA
F10, E11, E9,
D11
E10, D12,
C11, D10
Pin name
I/O circuit
type
SEG28 to
SEG31
J
Description
LCD controller/driver LCD segment output pins.
This function is valid when corresponding bit of PFR6
register is set to peripheral function.
P64 to P67
General purpose input/output ports. (open-drain)
This function is valid when corresponding bit of PFR6
register is set to port function.
COM0 to
COM3
LCD controller/driver common output pins.
This function is valid when corresponding bit of PFR7
register is set to peripheral function.
I
P70 to P73
General purpose input/output ports.
This function is valid when corresponding bit of PFR7
register is set to port function.
87 to 89
C12, B11, D9
MD2,
MD1,
MD0
H
Mode input pins.
90
B12
INIT
G
External reset input.
91 to 94
A12, B10,
C10, A11
V0 to V3
⎯
LCD controller/driver reference power supply input
pins.
D
UART0 data input.
When using this function, corresponding bit of DDR0
register is set to input.
SIN0
95
D8
General purpose input/output port.
This function is always valid.
P00
SOT0
96
97
98
B9
D
UART0 data output.
This function is valid when corresponding bit of PFR0
register is set to peripheral function.
P01
General purpose input/output port.
This function is valid when corresponding bit of PFR0
register is set to port function.
SCK0
UART0 clock input/output.
This function is valid when corresponding bit of PFR0
register is set to peripheral function.
A10
D
P02
General purpose input/output port.
This function is valid when corresponding bit of PFR0
register is set to port function.
SIN1
UART1 data input.
This function is valid when corresponding bit of DDR0
register is set to input.
C9
D
P03
General purpose input/output port.
This function is always valid.
(Continued)
DS07–16506–3E
13
MB91230 Series
Pin no.
LQFP
FLGA
Pin name
I/O circuit
type
SOT1
99
100
101
102
103
104
B8
D
Description
UART1 data output.
This function is valid when corresponding bit of PFR0 register is set to peripheral function.
P04
General purpose input/output port.
This function is valid when corresponding bit of PFR0 register is set to port function.
SCK1
UART1 clock input/output.
This function is valid when corresponding bit of PFR0 register is set to peripheral function.
A9
D
P05
General purpose input/output port.
This function is valid when corresponding bit of PFR0 register is set to port function.
IC0
Input capture input 0.
This function is valid when corresponding bit of DDR0
register is set to input.
D7
D
P06
General purpose input/output port.
This function is always valid.
IC1
Input capture input 1.
This function is valid when corresponding bit of DDR0
register is set to input.
C8
D
P07
General purpose input/output port.
This function is always valid.
INT0
External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.
A8
A
P10
General purpose input/output port.
This function is always valid.
INT1
External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.
B7
A
General purpose input/output port.
This function is always valid.
P11
Power supply pin (5 V I/O MB91V230/F233A)
105
C7
VCC
⎯
Power supply pin (3.3 V internal logic, I/O MB91F233L/
MB91233L)
106
B6
VSS
⎯
Power supply pin (GND)
107
A7
X1
108
C6
X0
K
Main-clock oscillation pins
(Continued)
14
DS07–16506–3E
MB91230 Series
Pin no.
LQFP
FLGA
Pin name
I/O circuit
type
INT2
109
110
111
112
113
114
115
A6
A
External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.
P12
General purpose input/output port.
This function is always valid.
INT3
External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.
B5
A
P13
General purpose input/output port.
This function is always valid.
INT4
External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.
D5
A
P14
General purpose input/output port.
This function is always valid.
INT5
External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.
B4
A
P15
General purpose input/output port.
This function is always valid.
INT6
External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.
C5
A
P16
General purpose input/output port.
This function is always valid.
INT7
External interrupt input.
This function is valid when corresponding bit of DDR1
register is set to input.
A4
B3
Description
A
P17
General purpose input/output port.
This function is always valid.
CKI0
External clock input pin for free-run timer 0.
This function is enabled when corresponding bit of PFR2
register is set to port function and corresponding bit of
DDR2 register is set to input.
OP0
P20
D
Output compare 0 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.
(Continued)
DS07–16506–3E
15
MB91230 Series
(Continued)
Pin no.
LQFP
FLGA
Pin name
I/O circuit
type
External clock input pin for free-run timer 1.
This function is enabled when corresponding bit of
PFR2 register is set to port function and corresponding
bit of DDR2 register is set to input.
CKI1
116
C4
OP1
D
Pulse width counter 0 input.
This function is enabled when corresponding bit of
PFR2 register is set to port function and corresponding
bit of DDR2 register is set to input.
PWI0
A3
OP2
D
Pulse width counter 1 input.
This function is enabled when corresponding bit of
PFR2 register is set to port function and corresponding
bit of DDR2 register is set to input.
PWI1
119
B2
OP3
D
General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.
SIN2
UART2 data input.
This function is valid when corresponding bit of DDR2
register is set to input.
D4
D
General purpose input/output port.
This function is always valid.
SOT2
A2
D
P25
16
Output compare3 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.
P23
P24
120
Output compare2 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.
P22
118
Output compare1 output pin.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.
P21
117
Description
UART2 data output.
This function is valid when corresponding bit of PFR2
register is set to peripheral function.
General purpose input/output port.
This function is valid when corresponding bit of PFR2
register is set to port function.
(38)
L5
AVRL
⎯
Analog reference power supply (for A/D converter)
AVRL pin is connected to AVSS inside the IC on LQFP
package product.
⎯
A5, D6, E12,
F2, F12, M7
NC
⎯
Unconnected pins.
DS07–16506–3E
MB91230 Series
■ I/O CIRCUIT TYPE
Type
Circuit type
A
P-ch
P-ch
Pull-up control
Output drive P-ch
N-ch
Output drive N-ch
Remarks
• With Pull-up control (50 kΩ)
• CMOS level output
IOH = 4 mA/IOL = 4 mA
• CMOS hysteresis input
(with standby control)
CMOS hysteresis
input
Standby control
B
P-ch
P-ch
Pull-up control
Output drive P-ch
N-ch
Output drive N-ch
• With Pull-up control (50 kΩ)
• CMOS level output
IOH = 4 mA/IOL = 4 mA
• CMOS hysteresis input
(with standby control)
• Test pin for Flash
CMOS hysteresis
input
Standby control
Test pin for Flash
Analog SW control
N-ch
C
P-ch
Output drive P-ch
N-ch
Output drive N-ch
• CMOS level output
• CMOS hysteresis input
(with standby control)
CMOS hysteresis
input
Standby control
D
P-ch
Output drive P-ch
N-ch
Output drive N-ch
• CMOS level output
IOH = 4 mA/IOL = 4 mA
• CMOS hysteresis input
(with standby control)
• Test pin for Flash
CMOS hysteresis
input
Standby control
Test pin for Flash
Analog SW control
N-ch
(Continued)
DS07–16506–3E
17
MB91230 Series
Type
Circuit type
E
P-ch
Output drive P-ch
N-ch
Output drive N-ch
Remarks
• CMOS level output
IOH = 4 mA/IOL = 4 mA
• CMOS hysteresis input
(with standby control)
• Also serving as an analog input
CMOS hysteresis
input
Standby control
Analog input
Analog SW control
N-ch
F
P-ch
Output drive P-ch
N-ch
Output drive N-ch
• CMOS level output
IOH = 4 mA/IOL = 4 mA
• CMOS hysteresis input
(with standby control)
• Also serving as an analog input
CMOS hysteresis
input
Standby control
Analog input
Analog SW control
N-ch
With Pull-up (50 kΩ)
CMOS hysteresis input
G
P-ch
P-ch
N-ch
CMOS hysteresis
input
H
Low impedance input
N-ch
• High withstand-voltage input
• CMOS input
(hysteresis level)
High impedance input
N-ch
N-ch
N-ch
N-ch
High voltage
detection
output
(Continued)
18
DS07–16506–3E
MB91230 Series
(Continued)
Type
Circuit type
Remarks
I
P-ch
Output drive P-ch
N-ch
Output drive N-ch
• CMOS level output
IOH = 4 mA/IOL = 4 mA
• CMOS hysteresis input
(with standby control)
• LCDC output
CMOS hysteresis
input
Standby control
LCDC output
J
P-ch
N-ch
Output drive N-ch
• CMOS level output (open-drain)
IOL = 20 mA
• CMOS hysteresis input
(with standby control)
• LCDC output
CMOS hysteresis
input
Standby control
LCDC output
K
Oscillation circuit
X1, X1A
Oscillation
output
X0, X0A
Standby
control
DS07–16506–3E
19
MB91230 Series
■ HANDLING DEVICES
Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or
output pin or if an above-rating voltage is applied between VCC and VSS pins.
A latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction
of an element. When you use a CMOS IC, be very careful not to exceed the absolute maximum rating.
Treatment of Unused Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a
pull-up or pull-down resistor.
Treatment of Pins at Unusing LCD
Leave COM0 to COM3 pins open.
V0 to V3 pins should always be pulled up or down through resistance of at least 2 kΩ.
About Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power
supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of
strobe signals caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS
near this device.
About Crystal Oscillator Circuit
Noise near the X0, X1, X0A and X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0, X1, X0A and X1A the crystal oscillator (or ceramic oscillator) , and the bypass capacitor
to ground are located as close to the device as possible.
It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded
by ground plane because stable operation can be expected with such a layout.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
Treatment of NC and OPEN Pins
Pins marked as NC and OPEN must be left open-circuit.
About Mode Pins (MD0 to MD2)
These pins should be connected directly to VCC or VSS.
To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such
that the distance between the mode pins and VCC or VSS is as short as possible and the connection impedance
is low.
20
DS07–16506–3E
MB91230 Series
Operation at Start-up
Be sure to execute setting initialized reset (INIT) with INIT pin immediately after start-up.
Also, in order to provide the oscillation stabilization wait time for the oscillation circuit immediately after startup, hold the “L” level input to the INIT pin for the required stabilization wait time. (For INIT via the INIT pin,
the oscillation stabilization wait time setting is initialized to the minimum value) .
About Oscillation Input at Power On
When turning the power on, maintain clock input until the device is released from the oscillation stabilization
wait state.
Clock Control Block
Input the “L” signal to the INIT pin to assure the clock oscillation stabilization wait time.
Switch Shared Port Function
To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR) .
Low Power Consumption Mode
To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR :
timebase counter control register) and be sure to use the following sequence
(LDI
#value_of_standby, R0) : value_of_standby is write data to STCR.
(LDI
#_STCR, R12)
: _STCR is address (481H) of STCR.
STB
R0, @R12
: Writing to standby control register (STCR)
LDUB
@R12, R0
: STCR read for synchronous standby
LDUB
@R12, R0
: Dummy re-read of STCR
NOP
: NOP × 5 for arrangement of timing
NOP
NOP
NOP
NOP
In addition, please set I flag, ILM, and ICR to diverge to the interruption handler that is the return factor after
the standby returns.
• Please do not do the following when the monitor debugger is used.
• Break point setting for above instruction lines
• Step execution for above instruction lines
Power-on sequence for dual-power-supply model
• Notes on the power-on and power-off sequences
Power-on sequence : Vcc3B, Vcc3→Vcc→Vcc3IO, AVRH, V0 to V3
Power-off sequence : Vcc3IO, AVRH, V0 to V3, Vcc3→Vcc→Vcc3B, Vcc3
When VCC is turned on earlier, a potential difference between VCC and VCC3 must fall within 3.6 V.
• The LCD power supply V3 must not exceed VCC in voltage. Apply V3 after turning on VCC3.
• Turn on VCC3 before applying the analog power supply AVCC or an analog signal.
DS07–16506–3E
21
MB91230 Series
Notes on the PS register
As the PS register is processed by some instructions in advance, exception handling below may cause the
interrupt handling routine to break when the debugger is used or the display contents of flags in the PS
register to be updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,
it performs operations before and after the EIT as specified in either case.
• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS
instruction is (a) acceptance of a user interrupt, (b) single-stepped, or (c) breaks in response to a data
event or emulator menu :
1) The D0 and D1 flags are updated in advance.
2) An EIT handling routine (user interrupt or emulator) is executed.
3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed, and the D0 and D1 flags are
updated to the same values as in 1).
• The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed
to allow the interrupt.
1) The PS register is updated in advance.
2) An EIT handling routine (user interrupt) is executed.
3) Upon returning from the EIT, the above instructions are executed, and the PS register is updated to the
same value as in 1).
Watchdog Timer
The watchdog timer built in this model monitors a program that it defers a reset within a certain period of
time. The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer
function from being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog
timer keeps on operating programs until it resets the CPU.
As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops
program execution.
For those conditions to which this exception applies, see Section “•Watchdog timer suspension (Automatic
generation postponement) ” in “■Time-base Counter” of Section “3.11.7 Peripheral Circuits in the Clock
Control Unit” in Hardware manual.
Step execution of RETI instruction
If an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is executed repeatedly after step execution. This will prevent the main routine and low-interrupt-level programs
from being executed.
Do not execute step of RETI instruction for escape.
Disable the corresponding interrupt and execute debugger when the corresponding interrupt routine no
longer needs debugging.
Operand Break
Do not apply a data event break to access to the area containing the address of a system stack pointer.
22
DS07–16506–3E
MB91230 Series
■ BLOCK DIAGRAM
FR60Lite
CPU Core
32
32
Bit Search
ROM 256 Kbytes
Flash 256 Kbytes
Bus Converter
RAM 16 Kbytes
X0, X1
MD0 to MD2
INIT
X0A, X1A
Clock Control
(Clock, Standby,
Reset, Watchdog,
TBT,
Main-ClockStabilizationTimer)
32
32 ↔ 16
Adapter
16
Watch Timer
VCC3B
Real Time Clock
Interruption
Controller
INT0 to INT15
SIN0 to SIN3
SOT0 to SOT3
SCK0 to SCK3
External interrupt
0 to 15
UART
0 to 3
External Memory
I/F
(MB91230 series
is not supported)
PORT I/F
VCC
PORTs
CKOT
Clock Monitor
LCDC/Driver
Internal Reference
Voltage
Up/Down Counter
0, 1
Reload Timer
0 to 3
PPG
0 to 5
COM0 to COM3
SEG0 to SEG31
V0 to V3
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
TOT0 to TOT3
PPG0 to PPG5
U-TIMER
0 to 3
AN0 to AN3
ADTG0
AVRH
AN4 to AN7
ADTG1
AVCC
DA0, DA1
4-channel Input
A/D converter 0
4-channel Input
A/D converter 1
2-channel Output
D/A converter 0, 1
Input Capture 0, 1
Free Run Timer 0
Output Compare 0, 1
Free Run Timer 1
Output Compare 2, 3
8-bit PWC 0, 1
IC0, IC1
CKI0
OP0, OP1
CKI1
OP2, OP3
PWI0, PWI1
: Trriger signal
DS07–16506–3E
23
MB91230 Series
■ MEMORY SPACE
1. Memory space
FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
• Direct Addressing Areas
The following address space areas are used as I/O areas.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.
The size of directly addressable areas depends on the length of the data being accessed as shown below.
• byte data access
: 000H to 0FFH
• half word data access : 000H to 1FFH
• word data access
: 000H to 3FFH
2. Memory Map
MB91V230
0000 0000H
0000 0400H
0001 0000H
0003 A000H
0004 0000H
0008 0000H
MB91F233A/L, MB91233L
I/O
Direct Addressing
Areas
I/O
I/O
“Refer to “■I/O MAP”.
I/O
Access
disallowed
Built-in RAM
24 Kbytes
Access
disallowed
Emulation
SRAM area
512 Kbytes
0010 0000H
0001 0000H
Access
disallowed
0003 C000H
Built-in RAM
16 Kbytes
0004 0000H
000C 0000H
Built-in
Flash ROM
256 Kbytes
0010 0000H
Access
disallowed
FFFF FFFFH
Access
disallowed
Access
disallowed
FFFF FFFFH
Note : The external bus mode cannot be used in the MB91230 series.
24
DS07–16506–3E
MB91230 Series
■ MODE SETTINGS
The FR family uses mode pins (MD2 to MD0) and a mode data to set the operation mode.
• Mode Pins
The MD2 to MD0 pins specify how the mode vector fetch and reset vector fetch is performed.
Setting is prohibited other than that shown in the following table.
Mode Pins
Mode name
Reset vector
access area
0
Internal ROM mode vector
Internal
1
External ROM mode vector
External
MD2
MD1
MD0
0
0
0
0
Remarks
Not supported by this model.
• Mode data
Data written to the internal mode register (MODR) by a mode vector fetch is called mode data.
After an operation mode has been set in the mode register, the device operates in the operation mode.
The mode data is set by all reset source. User programs cannot set data to the mode register.
Details of mode data description
bit
31
30
29
28
27
26
25
24
0
0
0
0
0
1
1
1
Operation mode setting bits
Bit31 to bit24 are all reserved bits.
Be sure to set this bit to “00000111”.
Operation is not guaranteed when any value other than “00000111” is set.
Note : Mode data set in the mode vector must be placed as byte data at 000FFFF8H.
Use the highest byte from bit31 to bit24 for placement as the FR family uses the big endian for byte
endian.
bit 31
Incorrect
Correct
DS07–16506–3E
24 23
16 15
87
0
000FFFF8H
XXXXXXXX
XXXXXXXX
XXXXXXXX
Mode Data
000FFFF8H
Mode Data
XXXXXXXX
XXXXXXXX
XXXXXXXX
000FFFFCH
Reset Vector
25
MB91230 Series
■ I/O MAP
[How to read the table]
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Block
T-unit
Port data register
Read/write attribute Access unit
(B : byte, H : half word, W : word)
Initial value of register after reset
Register name (column 1 of the register is at address 4n, column 2 is
at address 4n + 1...)
Leftmost register address (For word-length access, column 1 of the
register becomes the MSB of the data.)
Note : Initial values of register bits are represented as follows :
“ 1 ” : Initial Value “ 1 ”
“ 0 ” : Initial Value “ 0 ”
“ X ” : Initial Value “ undefined”
“ - ” : No physical register at this location
Access is barred with an undefined data access attribute.
26
DS07–16506–3E
MB91230 Series
Register
Address
+0
+1
+2
+3
000000H
PDR0 [R/W] B
XXXXXXXX
PDR1 [R/W] B
XXXXXXXX
PDR2 [R/W] B
XXXXXXXX
PDR3 [R/W] B
XXXXXXXX
000004H
PDR4 [R/W] B
XXXXXXXX
PDR5 [R/W] B
XXXXXXXX
PDR6 [R/W] B
XXXX----
PDR7 [R/W] B
----XXXX
000008H
PDR8 [R/W] B
XXXXXXXX
PDR9 [R/W] B
XXXXXXXX
PDRA [R/W] B
XXXXXXXX
PDRB [R/W] B
----XXXX
00000CH
PDRC [R/W] B
XXXXXXXX
PDRD [R/W] B
------XX
⎯
PDRF [R/W] B
---XX---
000010H
to
00003CH
⎯
⎯
⎯
⎯
000040H
EIRR0 [R/W]
B, H, W
00000000
ENIR0 [R/W]
B, H, W
00000000
ELVR0 [R/W] B, H, W
00000000 00000000
000044H
DICR [R/W]
B, H, W
-------0
⎯
⎯
TMRLR0 [W] H
XXXXXXXX XXXXXXXX
TMR0 [R] H
XXXXXXXX XXXXXXXX
00004CH
⎯
TMCSR0 [R/W] H
----0000 00000000
000050H
TMRLR1 [W] H
XXXXXXXX XXXXXXXX
TMR1 [W] H
XXXXXXXX XXXXXXXX
000054H
⎯
TMCSR1 [R/W] H
----0000 00000000
000058H
TMRLR2 [W] H
XXXXXXXX XXXXXXXX
TMR2 [W] H
XXXXXXXX XXXXXXXX
00005CH
⎯
TMCSR2 [R/W] H
----0000 00000000
000060H
UTIM0 [R] H (UTIMR0 [W] H)
00000000 00000000
000064H
000068H
SIDR0 [R] B, H, W
SODR0 [W]
B, H, W
XXXXXXXX
SSR1 [R/W]
B, H, W
00001000
00006CH
SIDR1 [R] B, H, W
SODR1 [W] B, H,
W
XXXXXXXX
UTIM1 [R] H (UTIMR1 [W] H)
00000000 00000000
SCR0 [R/W]
B, H, W
00000100
⎯
SCR1 [R/W]
B, H, W
00000100
⎯
Port data
register
Unused
External
interrupt (INT0 to
INT7)
Delay interrupt
000048H
SSR0 [R/W]
B, H, W
00001000
Block
SMR0 [R/W]
B, H, W
00--0-0-
Reload timer 0
Reload timer 1
Reload timer 2
UART0
UTIMC0 [R/W] B
U-TIMER0
0--00001
SMR1 [R/W]
B, H, W
00--0-0-
UART1
UTIMC1 [R/W] B
U-TIMER1
0--00001
(Continued)
DS07–16506–3E
27
MB91230 Series
Address
000070H
Register
+0
+1
+2
+3
SSR2 [R/W]
B, H, W
00001000
SIDR2 [R] B, H, W
SODR2 [W]
B, H, W
XXXXXXXX
SCR2 [R/W]
B, H, W
00000100
SMR2 [R/W]
B, H, W
00--0-0-
000074H
UTIM2 [R] H (UTIMR1 [W] H)
00000000 00000000
000078H
ADCS0 [R/W] H, W
0000--00 000-0000
00007CH
000080H
000084H
000088H
00008CH
000090H
⎯
Block
UART2
UTIMC2 [R/W] B
U-TIMER2
0--00001
ADCT0 [R/W] H, W
XXXXXXXX XXXXXXXX
A/D converter 0
ADT00 (ADTH00/ADTL00) [R] B, H, W ADT01 (ADTH01/ADTL01) [R] B, H, W
(series-parallel
000000XX XXXXXXXX
000000XX XXXXXXXX
type)
ADT02 (ADTH02/ADTL02) [R] B, H, W ADT03 (ADTH03/ADTL03) [R] B, H, W
000000XX XXXXXXXX
000000XX XXXXXXXX
ADCS1 [R/W] H, W
0000--00 000-0000
ADCT1 [R/W] H, W
XXXXXXXX XXXXXXXX
A/D converter 1
ADT10 (ADTH10/ADTL10) [R] B, H, W ADT11 (ADTH11/ADTL11) [R] B, H, W
(series-parallel
000000XX XXXXXXXX
000000XX XXXXXXXX
type)
ADT12 (ADTH12/ADTL12) [R] B, H, W ADT13 (ADTH13/ADTL13) [R] B, H, W
000000XX XXXXXXXX
000000XX XXXXXXXX
⎯
⎯
DACR1 [R/W]
B, H, W
-------0
DACR0 [R/W]
B, H, W
-------0
DADR0 [R/W]
B, H, W
XXXXXXXX
000094H
⎯
⎯
DADR1 [R/W]
B, H, W
XXXXXXXX
000098H
LCDCMR [R/W]
B, H, W
----0000
⎯
LCR0 [R/W]
B, H, W
00010000
LCR1 [R/W]
B, H, W
00000000
00009CH
VRAM0 [R/W]
B, H, W
XXXXXXXX
VRAM1 [R/W]
B, H, W
XXXXXXXX
VRAM2 [R/W]
B, H, W
XXXXXXXX
VRAM3 [R/W]
B, H, W
XXXXXXXX
0000A0H
VRAM4 [R/W]
B, H, W
XXXXXXXX
VRAM5 [R/W]
B, H, W
XXXXXXXX
VRAM6 [R/W]
B, H, W
XXXXXXXX
VRAM7 [R/W]
B, H, W
XXXXXXXX
0000A4H
VRAM8 [R/W]
B, H, W
XXXXXXXX
VRAM9 [R/W]
B, H, W
XXXXXXXX
VRAM10 [R/W]
B, H, W
XXXXXXXX
VRAM11 [R/W]
B, H, W
XXXXXXXX
0000A8H
VRAM12 [R/W]
B, H, W
XXXXXXXX
VRAM13 [R/W]
B, H, W
XXXXXXXX
VRAM14 [R/W]
B, H, W
XXXXXXXX
VRAM15 [R/W]
B, H, W
XXXXXXXX
0000ACH
CKR [R/W]
B, H, W
----0000
⎯
⎯
⎯
D/A converter
LCD controller/
driver
Clock monitor
(Continued)
28
DS07–16506–3E
MB91230 Series
Register
Address
Block
+0
+1
+2
+3
0000B0H
RCR1 [W]
B, H, W
00000000
RCR0 [W]
B, H, W
00000000
UDCR1 [R]
B, H, W
00000000
UDCR0 [R]
B, H, W
00000000
0000B4H
CCRH0 [R/W]
B, H, W
00000000
CCRL0 [R/W]
B, H, W
00001000
⎯
CSR0 [R/W]
B, H, W
00000000
0000B8H
CCRH1 [R/W]
B, H, W
00000000
CCRL1 [R/W]
B, H, W
00001000
⎯
CSR1 [R/W]
B, H, W
00000000
0000BCH
⎯
⎯
⎯
⎯
Unused
0000C0H
SSR3 [R/W]
B, H, W
00001000
SIDR3 [R] B, H, W
SODR3 [W] B, H, W
XXXXXXXX
SCR3 [R/W]
B, H, W
00000100
SMR3 [R/W]
B, H, W
00--0-0-
UART3
0000C4H
UTIM3 [R] H (UTIMR [W] H)
00000000 00000000
0000C8H
TMRLR3 [W] H
XXXXXXXX XXXXXXXX
TMR3 [W] H
XXXXXXXX XXXXXXXX
⎯
TMCSR3 [R/W] H
---00000 00000000
0000CCH
0000D0H
EIRR1 [R/W]
B, H, W
00000000
ENIR1 [R/W]
B, H, W
00000000
⎯
Up/down
counter0, 1
UTIMC3 [R/W] B
U-TIMER3
0--00001
ELVR1 [R/W] B, H, W
00000000 00000000
Reload
timer 3
External
interrupt (INT8 to
INT15)
0000D4H
TCDT0 [R/W] H, W
00000000 00000000
⎯
TCCS0 [R/W]
B, H, W
00000000
Free-run timer 0
0000D8H
TCDT1 [R/W] H, W
00000000 00000000
⎯
TCCS1 [R/W]
B, H, W
00000000
Free-run timer 1
0000DCH
IPCP1 [R] H, W
XXXXXXXX XXXXXXXX
0000E0H
⎯
⎯
IPCP0 [R] H, W
XXXXXXXX XXXXXXXX
⎯
ICS01 [R/W]
B, H, W
00000000
0000E4H
OCCP1 [R/W] H, W
XXXXXXXX XXXXXXXX
OCCP0 [R/W] H, W
XXXXXXXX XXXXXXXX
0000E8H
OCCP3 [R/W] H, W
XXXXXXXX XXXXXXXX
OCCP2 [R/W] H, W
XXXXXXXX XXXXXXXX
0000ECH
OCS23 [R/W] B, H, W
---0--00 0000--00
OCS01 [R/W] B, H, W
---0--00 0000--00
Input capture 0,
1
Output compare
0 to 3
(Continued)
DS07–16506–3E
29
MB91230 Series
Address
Register
+0
+1
+2
+3
0000F0H
PWCC0 [R/W]
B, H, W
0---00-0
PWCD0 [R]
B, H, W
XXXXXXXX
PWCC1 [R/W]
B, H, W
0---00-0
PWCD1 [R]
B, H, W
XXXXXXXX
0000F4H
⎯
WTDBL [R/W] B
-------0
0000F8H
⎯
WTBR0 [R/W] B
---XXXXX
WTBR1 [R/W] B
XXXXXXXX
0000FCH
WTHR [R/W]
B, H
---XXXXX
WTMR [R/W]
B, H
--XXXXXX
WTSR [R/W] B
--XXXXXX
⎯
000100H
to
000114H
⎯
⎯
⎯
⎯
000118H
GCN10 [R/W] H
00110010 00010000
⎯
GCN20 [R/W] B
00000000
00011CH
⎯
⎯
000120H
PTMR0 [R] H
11111111 11111111
PCSR0 [W] H
XXXXXXXX XXXXXXXX
000124H
PDUT0 [W] H
XXXXXXXX XXXXXXXX
000128H
PTMR1 [R] H
11111111 11111111
00012CH
PDUT1 [W] H
XXXXXXXX XXXXXXXX
000130H
PTMR2 [R] H
11111111 11111111
000134H
PDUT2 [W] H
XXXXXXXX XXXXXXXX
000138H
PTMR3 [R] H
11111111 11111111
00013CH
PDUT3 [W] H
XXXXXXXX XXXXXXXX
000140H
PTMR4 [R] H
11111111 11111111
000144H
PDUT4 [W] H
XXXXXXXX XXXXXXXX
Block
PWC0, 1
WTCR [R/W] B, H
00000000 000-00-X
PCNH0 [R/W]
B, H
00000000
WTBR2 [R/W] B
Real-time clock
XXXXXXXX
Unused
PPG
Unused
PCNL0 [R/W]
B, H
00000000
PPG0
PCSR1 [W] H
XXXXXXXX XXXXXXXX
PCNH1 [R/W]
B, H
00000000
PCNL1 [R/W]
B, H
00000000
PPG1
PCSR2 [W] H
XXXXXXXX XXXXXXXX
PCNH2 [R/W]
B, H
00000000
PCNL2 [R/W]
B, H
00000000
PPG2
PCSR3 [W] H
XXXXXXXX XXXXXXXX
PCNH3 [R/W]
B, H
00000000
PCNL3 [R/W]
B, H
00000000
PPG3
PCSR4 [W] H
XXXXXXXX XXXXXXXX
PCNH4 [R/W]
B, H
00000000
PCNL4 [R/W]
B, H
00000000
PPG4
(Continued)
30
DS07–16506–3E
MB91230 Series
Register
Address
+0
+1
000148H
PTMR5 [R] H
11111111 11111111
00014CH
PDUT5 [W] H
XXXXXXXX XXXXXXXX
+2
Block
+3
PCSR5 [W] H
XXXXXXXX XXXXXXXX
PCNH5 [R/W]
B, H
00000000
PCNL5 [R/W]
B, H
00000000
PPG5
000150H
to
0001FCH
⎯
⎯
⎯
⎯
Unused
000200H
to
0003ECH
⎯
⎯
⎯
⎯
Unused
0003F0H
BSD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Bit search
000400H
DDR0 [R/W] B
00000000
DDR1 [R/W] B
00000000
DDR2 [R/W] B
00000000
DDR3 [R/W] B
00000000
000404H
DDR4 [R/W] B
00000000
DDR5 [R/W] B
00000000
DDR6 [R/W] B
0000----
DDR7 [R/W] B
----0000
000408H
DDR8 [R/W] B
00000000
DDR9 [R/W] B
00000000
DDRA [R/W] B
00000000
DDRB [R/W] B
----0000
00040CH
DDRC [R/W] B
00000000
DDRD [R/W] B
------00
⎯
DDRF [R/W] B
---00---
000410H
to
00041CH
⎯
⎯
⎯
⎯
000420H
PFR0 [R/W] B
--00-00-
PFR1 [R/W] B
--------
PFR2 [R/W] B
-00-0000
PFR3 [R/W] B
------00
000424H
PFR4 [R/W] B
00000000
PFR5 [R/W] B
---00---
PFR6 [R/W] B
0000----
PFR7 [R/W] B
----0000
000428H
PFR8 [R/W] B
00000000
PFR9 [R/W] B
00000000
PFRA [R/W] B
00000000
PFRB [R/W] B
----0000
00042CH
PFRC [R/W] B
--------
PFRD [R/W] B
------00
⎯
PFRF [R/W] B
----0---
000430H
to
00043CH
⎯
⎯
⎯
⎯
Data direction
register
Unused
Port function register
Unused
(Continued)
DS07–16506–3E
31
MB91230 Series
Address
Register
+0
+1
+2
+3
000440H
ICR00 [R/W]
B, H, W
---11111
ICR01 [R/W]
B, H, W
---11111
ICR02 [R/W]
B, H, W
---11111
ICR03 [R/W]
B, H, W
---11111
000444H
ICR04 [R/W]
B, H, W
---11111
ICR05 [R/W]
B, H, W
---11111
ICR06 [R/W]
B, H, W
---11111
ICR07 [R/W]
B, H, W
---11111
000448H
ICR08 [R/W]
B, H, W
---11111
ICR09 [R/W]
B, H, W
---11111
ICR10 [R/W]
B, H, W
---11111
ICR11 [R/W]
B, H, W
---11111
00044CH
ICR12 [R/W]
B, H, W
---11111
ICR13 [R/W]
B, H, W
---11111
ICR14 [R/W]
B, H, W
---11111
ICR15 [R/W]
B, H, W
---11111
000450H
ICR16 [R/W]
B, H, W
---11111
ICR17 [R/W]
B, H, W
---11111
ICR18 [R/W]
B, H, W
---11111
ICR19 [R/W]
B, H, W
---11111
000454H
ICR20 [R/W]
B, H, W
---11111
ICR21 [R/W]
B, H, W
---11111
ICR22 [R/W]
B, H, W
---11111
ICR23 [R/W]
B, H, W
---11111
000458H
ICR24 [R/W]
B, H, W
---11111
ICR25 [R/W]
B, H, W
---11111
ICR26 [R/W]
B, H, W
---11111
ICR27 [R/W]
B, H, W
---11111
00045CH
ICR28 [R/W]
B, H, W
---11111
ICR29 [R/W]
B, H, W
---11111
ICR30 [R/W]
B, H, W
---11111
ICR31 [R/W]
B, H, W
---11111
000460H
ICR32 [R/W]
B, H, W
---11111
ICR33 [R/W]
B, H, W
---11111
ICR34 [R/W]
B, H, W
---11111
ICR35 [R/W]
B, H, W
---11111
000464H
ICR36 [R/W]
B, H, W
---11111
ICR37 [R/W]
B, H, W
---11111
ICR38 [R/W]
B, H, W
---11111
ICR39 [R/W]
B, H, W
---11111
000468H
ICR40 [R/W]
B, H, W
---11111
ICR41 [R/W]
B, H, W
---11111
ICR42 [R/W]
B, H, W
---11111
ICR43 [R/W]
B, H, W
---11111
00046CH
ICR44 [R/W]
B, H, W
---11111
ICR45 [R/W]
B, H, W
---11111
ICR46 [R/W]
B, H, W
---11111
ICR47 [R/W]
B, H, W
---11111
000470H
to
00047CH
⎯
⎯
⎯
⎯
Block
Interrupt
controller
Unused
(Continued)
32
DS07–16506–3E
MB91230 Series
(Continued)
Register
Address
Block
+0
+1
+2
+3
000480H
RSRR [R/W]
B, H
10000000
STCR [R/W]
B, H
00110011
TBCR [R/W]
B
00XXXX00
CTBR [W]
B
XXXXXXXX
000484H
CLKR [R/W]
B
00000000
WPR [R/W]
B
XXXXXXXX
DIVR0 [R/W]
B, H
00000011
DIVR1 [R/W]
B, H
00000000
000488H
⎯
⎯
OSCCR [R/W] B
XXXXXXX0
⎯
00048CH
WPCR [R/W] B
00---000
⎯
⎯
⎯
Watch timer
000490H
OSCR [R/W] B
00---000
⎯
⎯
⎯
Main clock
oscillation
stabilization wait
timer
000494H
to
0004FCH
⎯
⎯
⎯
⎯
Unused
000500H
⎯
PCR1 [R/W] B
00000000
⎯
PCR3 [R/W] B
00000000
000504H
to
00051CH
⎯
⎯
⎯
⎯
Unused
000520H
to
0007F8H
⎯
⎯
⎯
⎯
Unused
0007FCH
⎯
MODR*
XXXXXXXX
⎯
⎯
Operation mode
000800H
to
000AFCH
⎯
⎯
⎯
⎯
Unused
000B00H
to
000FFCH
⎯
⎯
⎯
⎯
Unused
001000H
to
006FFCH
⎯
⎯
⎯
⎯
Unused
007000H
FLCR [R/W] B
01101000
⎯
⎯
⎯
007004H
FLWC [R/W] B
00000011
⎯
⎯
⎯
007008H
to
00FFFCH
⎯
⎯
⎯
⎯
Clock control
Pull-up control
register
Flash
Unused
* : This register is set when the mode vector is fetched. Not user-accessible.
DS07–16506–3E
33
MB91230 Series
■ INTERRUPT VECTOR
Interrupt source
Interrupt number
Interrupt level
Offset
TBR default
address
10
16
Reset
0
00
⎯
3FCH
000FFFFCH
Mode vector
1
01
⎯
3F8H
000FFFF8H
System reserved
2
02
⎯
3F4H
000FFFF4H
System reserved
3
03
⎯
3F0H
000FFFF0H
System reserved
4
04
⎯
3ECH
000FFFECH
System reserved
5
05
⎯
3E8H
000FFFE8H
System reserved
6
06
⎯
3E4H
000FFFE4H
Coprocessor absent trap
7
07
⎯
3E0H
000FFFE0H
Coprocessor error trap
8
08
⎯
3DCH
000FFFDCH
INTE instruction
9
09
⎯
3D8H
000FFFD8H
Instruction break exception
10
0A
⎯
3D4H
000FFFD4H
Operand break trap
11
0B
⎯
3C0H
000FFFD0H
Step trace trap
12
0C
⎯
3CCH
000FFFCCH
NMI request (tool)
13
0D
⎯
3C8H
000FFFC8H
Undefined instruction exception
14
0E
⎯
3C4H
000FFFC4H
NMI request
(This model has no NMI request)
15
0F
15 (FH) fixed
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
Reload timer 1
25
19
ICR09
398H
000FFF98H
Reload timer 2
26
1A
ICR10
394H
000FFF94H
UART0(Reception completed)
27
1B
ICR11
390H
000FFF90H
UART0 (Transmission completed)
28
1C
ICR12
38CH
000FFF8CH
UART1 (Reception completed)
29
1D
ICR13
388H
000FFF88H
UART1 (Transmission completed)
30
1E
ICR14
384H
000FFF84H
UART2 (Reception completed)
31
1F
ICR15
380H
000FFF80H
UART2 (Transmission completed)
32
20
ICR16
37CH
000FFF7CH
(Continued)
34
DS07–16506–3E
MB91230 Series
Interrupt number
Interrupt level
Offset
TBR default
address
21
ICR17
378H
000FFF78H
34
22
ICR18
374H
000FFF74H
A/D ch.0
35
23
ICR19
370H
000FFF70H
A/D ch.1
36
24
ICR20
36CH
000FFF6CH
External interrupt8
37
25
ICR21
368H
000FFF68H
External interrupt9
38
26
ICR22
364H
000FFF64H
External interrupt 10
39
27
ICR23
360H
000FFF60H
External interrupt 11
40
28
ICR24
35CH
000FFF5CH
External interrupt 12
41
29
ICR25
358H
000FFF58H
External interrupt 13
42
2A
ICR26
354H
000FFF54H
External interrupt 14
43
2B
ICR27
350H
000FFF50H
External interrupt 15
44
2C
ICR28
34CH
000FFF4CH
Real-time clock
45
2D
ICR29
348H
000FFF48H
Main clock oscillation
stabilization wait timer
46
2E
ICR30
344H
000FFF44H
Timebase timer
47
2F
ICR31
340H
000FFF40H
Reload timer 3
48
30
ICR32
33CH
000FFF3CH
Watch timer
49
31
ICR33
338H
000FFF38H
UD Counter 0
50
32
ICR34
334H
000FFF34H
UD Counter 1
51
33
ICR35
330H
000FFF30H
PPG 0/1
52
34
ICR36
32CH
000FFF2CH
PPG 2/3
53
35
ICR37
328H
000FFF28H
PPG 4/5
54
36
ICR38
324H
000FFF24H
Free-run timer 0
55
37
ICR39
320H
000FFF20H
Free-run timer 1
56
38
ICR40
31CH
000FFF1CH
ICU 0 (capture)
57
39
ICR41
318H
000FFF18H
ICU 1 (capture)
58
3A
ICR42
314H
000FFF14H
OCU 0 (match)
59
3B
ICR43
310H
000FFF10H
OCU 1 (match)
60
3C
ICR44
30CH
000FFF0CH
OCU 2 (match)
61
3D
ICR45
308H
000FFF08H
OCU 3 (match)
62
3E
ICR46
304H
000FFF04H
Delay interrupt source bit
63
3F
ICR47
300H
000FFF00H
System reserved (Used by REALOS)
64
40
⎯
2FCH
000FFEFCH
System reserved (Used by REALOS)
65
41
⎯
2F8H
000FFEF8H
System reserved
66
42
⎯
2F4H
000FFEF4H
Interrupt source
10
16
UART3 (Reception completed)
33
UART3 (Transmission completed)
(Continued)
DS07–16506–3E
35
MB91230 Series
(Continued)
Interrupt number
Interrupt level
Offset
TBR default
address
43
⎯
2F0H
000FFEF0H
68
44
⎯
2ECH
000FFEECH
System reserved
69
45
⎯
2E8H
000FFEE8H
System reserved
70
46
⎯
2E4H
000FFEE4H
System reserved
71
47
⎯
2E0H
000FFEE0H
System reserved
72
48
⎯
2DCH
000FFEDCH
System reserved
73
49
⎯
2D8H
000FFED8H
System reserved
74
4A
⎯
2D4H
000FFED4H
System reserved
75
4B
⎯
2D0H
000FFED0H
System reserved
76
4C
⎯
2CCH
000FFECCH
System reserved
77
4D
⎯
2C8H
000FFEC8H
System reserved
78
4E
⎯
2C4H
000FFEC4H
System reserved
79
4F
⎯
2C0H
000FFEC0H
Used by INT instruction
80
to
255
50
to
FF
⎯
2BCH
to
000H
000FFEBCH
to
000FFC00H
Interrupt source
10
16
System reserved
67
System reserved
36
DS07–16506–3E
MB91230 Series
■ PIN STATUS IN EACH CPU STATE
Terms used as the status of pins mean as follows.
• Input enabled
Indicates that the input function can be used.
• Input 0 fixed
Indicates that the input level has been internally fixed to be “0” to prevent leakage when the input is released.
• Output Hi-Z
Means the placing of a pin in a high impedance state by preventing the transistor for driving the pin from
driving.
• Output is maintained
Indicates the output in the output state existing immediately before this mode is established. If the device
enters this mode with an internal output peripheral operating or while serving as an output port, the output
is performed by the internal peripheral or the port output is maintained, respectively.
• State existing immediately before is maintained
When the device serves for output or input immediately before entering this mode, the device maintains
the output or is ready for the input, respectively.
DS07–16506–3E
37
MB91230 Series
• Pin Status List
Specified function
name
Pin Pin
Port
no. name name
Input/
Input Output
1
P26/
P26
SCK2
2
P27/
SIN3
3
P30/
P30
SOT3
4
P31/
P31
SCK3
5
P32/
AIN0
6
P33/
BIN0
7
P34/
ZIN0
8
P35/
AIN1
9
P36/
BIN1
10
P37/
ZIN1
11
12
P27
P32
P33
P34
P35
P36
⎯
⎯
SIN3
⎯
⎯
⎯
AIN0
BIN0
ZIN0
AIN1
BIN1
SOT3
⎯
⎯
⎯
⎯
⎯
⎯
Output
At initializing
Function
name
Remarks
HIZ = 0
HIZ = 1
SCK2 P26
⎯
P27
P30
Pull-up
options
can be
selected
SCK3 P31
Pull-up
options
can be
selected
⎯
⎯
⎯
⎯
⎯
⎯
P32
Pull-up
options
can be
selected
P33
Pull-up
options
can be
selected
P34
Output
Hi-Z/
Input
enabled
Retention
of the
immediately
prior state
Retention
of the
immediately
prior state
Output
Hi-Z/
Input 0
fixed
Pull-up
options
can be
selected
P35
Pull-up
options
can be
selected
P36
Pull-up
options
can be
selected
Pull-up
options
can be
selected
ZIN1
⎯
⎯
P37
P40/
P40
PPG0
⎯
PPG
0
⎯
P40
P41/
P41
PPG1
⎯
PPG
1
⎯
P41
P37
Reset
initialization
At Stop mode
At sleep
mode
(Continued)
38
DS07–16506–3E
MB91230 Series
Pin
no.
Pin
name
Port
name
Specified function
name
Input
Input/
Output Output
At initializing
Function
name
Reset
initialization
At Stop mode
At sleep
mode
Remarks
HIZ = 0
HIZ = 1
13 X0A
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
14 X1A
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
15 VCC3B
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
16 VSS
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
17 VCC3
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
18
P42/
PPG2
P42
⎯
PPG2
⎯
P42
19
P43/
PPG3
P43
⎯
PPG3
⎯
P43
20
P44/
TOT0
P44
⎯
TOT0
⎯
P44
21
P45/
TOT1
P45
⎯
TOT1
⎯
P45
22
P46/
TOT2
P46
⎯
TOT2
⎯
P46
23
P47/
CKOT
P47
⎯
CKOT
⎯
P47
24
P50/
INT8
P50
INT8
⎯
⎯
P50
25
P51/
INT9
P51
INT9
⎯
⎯
P51
26
P52/
INT10
P52
INT10
⎯
⎯
P52
P53/
27 INT11/ P53
PPG4
INT11 PPG4
⎯
P53
P54/
28 INT12/ P54
PPG5
INT12 PPG5
⎯
P54
P55/
29 INT13/ P55
TIN2
INT13
TIN2
⎯
⎯
P55
P56/
30 INT14/ P56
TIN1
INT14
TIN1
⎯
⎯
P56
Retention
of the
immediately
prior state
Output
Hi-Z/
Input
enabled
Output
Hi-Z/
Input 0
fixed
Retention
of the
immediately
prior state
P:
P:
Retention
Output
of the
Hi-Z
immediately
prior state
F:
Input
F:
enInput
abled
enabled
Note : P : Port selected, F : Specified function selected
(Continued)
DS07–16506–3E
39
MB91230 Series
Pin
no.
Pin
name
Port
name
Specified function
name
Input
P57/
INT15/
31
P57
TIN0/
ADTG0
32
PF3/
TOT3
PF3
PF4/
33 TIN3/
PF4
ADTG1
INT15
TIN0
ADTG0
Input/
Output Output
⎯
⎯
At initializing
Function
name
Reset
initialization
At Stop mode
At sleep
mode
P57
⎯
TOT3
⎯
PF3
TIN3
ADTG1
⎯
⎯
PF4
Output
Hi-Z/
Input
enabled
Retention
of the
immediately
prior state
HIZ = 0
HIZ = 1
Remarks
P:
Retention
P:
of the
Output
immediately Hi-Z
prior state
F:
F:
Input 0
Input
enabled
enabled
Retention
of the
immediately
prior state
Output
Hi-Z/
Input 0
fixed
34
PD0/
DA0
PD0
⎯
DA0
⎯
PD0
35
PD1/
DA1
PD1
⎯
DA1
⎯
PD1
36 AVCC
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
37 AVRH
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
38 AVSS
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
39
PC0/
AN0
PC0
AN0
⎯
⎯
PC0
40
PC1/
AN1
PC1
AN1
⎯
⎯
PC1
41
PC2/
AN2
PC2
AN2
⎯
⎯
PC2
42
PC3/
AN3
PC3
AN3
⎯
⎯
PC3
43
PC4/
AN4
PC4
AN4
⎯
⎯
PC4
44
PC5/
AN5
PC5
AN5
⎯
⎯
PC5
45
PC6/
AN6
PC6
AN6
⎯
⎯
PC6
46
PC7/
AN7
PC7
AN7
⎯
⎯
PC7
Output
Hi-Z/
Input
enabled
Retention
of the
immediately
prior state
Retention
of the
immediately
prior state
Output
Hi-Z/
Input 0
fixed
Output
Hi-Z/
Input
enabled
Retention
of the
immediately
prior state
Retention
of the
immediately
prior state
Output
Hi-Z/
Input 0
fixed
Note : P : Port selected, F : Specified function selected
(Continued)
40
DS07–16506–3E
MB91230 Series
Pin Pin
Port
no. name name
Specified function
name
Input
Output
At initializing
Input/ Function
Output name
Reset
initialization
At Stop mode
At sleep
mode
HIZ = 0
HIZ = 1
47 VSS
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
48 VCC3IO
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
49
P80/
SEG0
P80
⎯
SEG0
⎯
P80
50
P81/
SEG1
P81
⎯
SEG1
⎯
P81
51
P82/
SEG2
P82
⎯
SEG2
⎯
P82
52
P83/
SEG3
P83
⎯
SEG3
⎯
P83
53
P84/
SEG4
P84
⎯
SEG4
⎯
P84
54
P85/
SEG5
P85
⎯
SEG5
⎯
P85
55
P86/
SEG6
P86
⎯
SEG6
⎯
P86
P87/
56
SEG7
P87
⎯
SEG7
⎯
P87
57
P90/
SEG8
P90
⎯
SEG8
⎯
P90
58
P91/
SEG9
P91
⎯
SEG9
⎯
P91
59
P92/
P92
SEG10
⎯
SEG10
⎯
P92
60
P93/
P93
SEG11
⎯
SEG11
⎯
P93
61
P94/
P94
SEG12
⎯
SEG12
⎯
P94
62
P95/
P95
SEG13
⎯
SEG13
⎯
P95
63
P96/
P96
SEG14
⎯
SEG14
⎯
P96
Output
Hi-Z/
Input
enabled
Retention
of the
immediately
prior state
Remarks
P:
Output
Hi-Z/
Input 0
fixed
Retention
of the
immediately
F:
prior state
Retention
of the
immediately
prior state
Note : P : Port selected, F : Specified function selected
(Continued)
DS07–16506–3E
41
MB91230 Series
Specified function
name
Pin Pin
Port
no. name name
Input/
Input
At initializing
FuncOutput Output tion
name
64
P97/
P97
SEG15
⎯
SEG15
⎯
P97
65
PA0/
PA0
SEG16
⎯
SEG16
⎯
PA0
66
PA1/
PA1
SEG17
⎯
SEG17
⎯
PA1
67
PA2/
PA2
SEG18
⎯
SEG18
⎯
PA2
68
PA3/
PA3
SEG19
⎯
SEG19
⎯
PA3
PA4/
69
PA4
SEG20
⎯
SEG20
⎯
PA4
70
PA5/
PA5
SEG21
⎯
SEG21
⎯
PA5
71
PA6/
PA6
SEG22
⎯
SEG22
⎯
PA6
72
PA7/
PA7
SEG23
⎯
SEG23
⎯
PA7
73
PB0/
PB0
SEG24
⎯
SEG24
⎯
PB0
74
PB1/
PB1
SEG25
⎯
SEG25
⎯
PB1
75 VCC
⎯
⎯
⎯
⎯
76 VSS
⎯
⎯
⎯
77
PB2/
PB2
SEG26
⎯
78
PB3/
PB3
SEG27
⎯
79
P64/
P64
SEG28
⎯
Reset
initialization
At Stop mode
At sleep
mode
HIZ = 0
HIZ = 1
P:
Output
Hi-Z/
Input 0 fixed
Output
Hi-Z/
Input
enabled
Retention
of the
immediately
prior state
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SEG26
⎯
PB2
SEG27
⎯
PB3
SEG28
⎯
Output
Hi-Z/
Input
enabled
P64
Retention
of the
immediately
prior state
Remarks
Retention
of the
immediately F :
prior state
Retention
of the
immediately
prior state
P:
Output
Hi-Z/
Input 0
fixed
Retention
of the
immediately
F:
prior state
Retention
of the
immediately
prior state
opendrain
pin,
IOL =
20 mA
Note : P : Port selected, F : Specified function selected
(Continued)
42
DS07–16506–3E
MB91230 Series
Specified function
name
Pin Pin
Port
no. name name
Input/
Input
80
81
P65/
P65
SEG29
P66/
P66
SEG30
⎯
⎯
At initializing
FuncOutput Output tion
name
SEG29
SEG30
⎯
⎯
Reset
initialization
At Stop mode
At sleep
mode
HIZ = 0
Remarks
HIZ = 1
P65
opendrain
pin,
IOL =
20 mA
P66
opendrain
pin,
IOL =
20 mA
Output
Hi-Z/
Input
enabled
Retention
of the
immediately
prior state
P:
Output
Hi-Z/
Input 0
fixed
Retention
of the
immediately F :
prior state
Retention
of the
immediately prior
state
82
P67/
P67
SEG31
⎯
SEG31
⎯
P67
83
P70/
P70
COM0
⎯
COM0
⎯
P70
84
P71/
P71
COM1
⎯
COM1
⎯
P71
85
P72/
P72
COM2
⎯
COM2
⎯
P72
86
P73/
P73
COM3
⎯
COM3
⎯
P73
87 MD2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
88 MD1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
89 MD0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
90 INIT
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
91 V0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
92 V1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
93 V2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
94 V3
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
opendrain
pin,
IOL =
20 mA
Note : P : Port selected, F : Specified function selected
(Continued)
DS07–16506–3E
43
MB91230 Series
Specified function
name
Pin Pin
Port
no. name name
Input/
At initializing
FuncInput Output Output tion
name
95
P00/
SIN0
P00
SIN0
⎯
⎯
P00
96
P01/
SOT0
P01
⎯
SOT0
⎯
P01
97
P02/
SCK0
P02
⎯
⎯
98
P03/
SIN1
P03
SIN1
⎯
⎯
P03
99
P04/
SOT1
P04
⎯
SOT1
⎯
P04
100
P05/
SCK1
P05
⎯
⎯
101
P06/
IC0
P06
IC0
⎯
⎯
P06
102
P07/
IC1
P07
IC1
⎯
⎯
P07
P10/
103
INT0
P11/
104
INT1
P10
P11
INT0
⎯
Reset
initialization
At Stop mode
At sleep
mode
Remarks
HIZ = 0
HIZ = 1
SCK0 P02
SCK1 P05
⎯
Retention
of the
immediately
prior state
Output
Hi-Z/
Input
enabled
Retention
of the
immediately
prior state
P:
Retention
P : Output
of the
Hi-Z
immediately
prior state
F : Input
enabled
F : Input
enabled
P10
INT1
⎯
⎯
P11
Output
Hi-Z/
Input 0
fixed
105 VCC
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
106 VSS
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
107 X1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
108 X0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Pull-up
options
can be
selected
Pull-up
options
can be
selected
Note : P : Port selected, F : Specified function selected
(Continued)
44
DS07–16506–3E
MB91230 Series
(Continued)
Specified function
name
Pin Pin
Port
no. name name
Input/
Input
P12/
109
INT2
P13/
110
INT3
P14/
111
INT4
P15/
112
INT5
P16/
113
INT6
P17/
114
INT7
P12
P13
P14
P15
P16
INT2
INT3
INT4
INT5
INT6
At initializing
FuncOutput
tion
Output name
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
P13
P15
⎯
P20
P21/
116 CKI1/ P21
OP1
CKI1 OP1
⎯
P21
P22/
117 PWI0/ P22
OP2
PWI0 OP2
⎯
P22
P23/
118 PWI1/ P23
OP3
PWI1 OP3
⎯
P23
SIN2
⎯
⎯
P24
⎯
SOT2
⎯
P25
120
P25/
P25
SOT2
Output
Hi-Z/
Input
enabled
Pull-up
options
can be
selected
Pull-up
options
can be
selected
Pull-up
options
can be
selected
P16
CKI0 OP0
P24
P:
Retention
P:
of the
Output
immediately
Hi-Z
prior state
F:
F:
Input
Input
enabled
enabled
P14
P20/
115 CKI0/ P20
OP0
P24/
SIN2
HIZ = 1
Pull-up
options
can be
selected
P17
119
HIZ = 0
P12
⎯
INT7
Remarks
Pull-up
options
can be
selected
⎯
P17
Reset
initialization
At Stop mode
At sleep
mode
Retention
of the
immediately
prior state
Pull-up
options
can be
selected
Retention
of the
immediately
prior state
Output
Hi-Z/
Input 0
fixed
Note : P : Port selected, F : Specified function selected
DS07–16506–3E
45
MB91230 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
MB91V230, MB91F233A
Parameter
Symbol
Rating
Unit
Min
Max
VCC
VSS−0.5
VSS + 6.0
V
VCC3
VSS−0.5
VSS + 4.0
V
VCC3IO
VSS−0.5
VSS + 4.0
V
AVCC
VSS−0.5
VSS + 4.0
V
VI
VSS−0.5
VCC + 0.5
V
Input voltage* (open-drain)
VIND
VSS−0.5
VCC + 0.5
V
Analog pin input voltage*
VIA
VSS−0.5
AVCC + 0.5
V
Output voltage*
VO
VSS−0.5
VCC + 0.5
V
Operating ambient temperature
Ta
−40
+ 85
°C
Tstg
−55
+ 125
°C
L level maximum output current
⎯
⎯
10
mA
L level average output current
⎯
⎯
4
mA
L level maximum total output
current
⎯
⎯
100
mA
L level average total output
current
⎯
⎯
50
mA
H level maximum output current
⎯
⎯
−10
mA
H level average output current
⎯
⎯
−4
mA
H level maximum total output
current
⎯
⎯
−60
mA
H level average total output
current
⎯
⎯
−30
mA
Power consumption
⎯
⎯
600
mW
Power supply voltage*
Analog power supply voltage*
Input voltage*
Storage temperature
Remarks
20 mA for
the pin 79
to pin 82
* : This parameter is based on VSS = AVSS = 0.0 V.
46
DS07–16506–3E
MB91230 Series
MB91F233L, MB91233L
Parameter
Symbol
Rating
Unit
Min
Max
VCC
VSS−0.5
VSS + 4.0
V
VCC3
VSS−0.5
VSS + 4.0
V
VCC3IO
VSS−0.5
VSS + 4.0
V
AVCC
VSS−0.5
VSS + 4.0
V
VI
VSS−0.5
VCC + 0.5
V
Input voltage* (open-drain)
VIND
VSS−0.5
VCC + 0.5
V
Analog pin input voltage*
VIA
VSS−0.5
AVCC + 0.5
V
Output voltage*
VO
VSS−0.5
VCC + 0.5
V
Operating ambient temperature
Ta
−40
+ 85
°C
Tstg
−55
+ 125
°C
L level maximum output current
⎯
⎯
10
mA
L level average output current
⎯
⎯
4
mA
L level maximum total output
current
⎯
⎯
100
mA
L level average total output
current
⎯
⎯
50
mA
H level maximum output current
⎯
⎯
−10
mA
H level average output current
⎯
⎯
−4
mA
H level maximum total output
current
⎯
⎯
−60
mA
H level average total output
current
⎯
⎯
−30
mA
Power consumption
⎯
⎯
600
mW
Power supply voltage*
Analog power supply voltage*
Input voltage*
Storage temperature
Remarks
20 mA for
the pin 79
to pin 82
* : This parameter is based on VSS = AVSS = 0.0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07–16506–3E
47
MB91230 Series
2. Recommended Operating Conditions
MB91V230, MB91F233A
(VSS = AVSS = 0.0 V)
Parameter
Symbol
Operating ambient temperature
Power supply voltage
Analog power supply voltage
LCD reference voltage
Value
Unit
Remarks
Min
Max
Ta
−40
+ 85
°C
VCC
4.00
5.25
V
*1
VCC3
3.00
3.60
V
*4
3.00
3.60
V
2.20
3.60
V
VCC3IO
3.00
3.60
V
AVCC
3.00
3.60
V
V3
⎯
5.25
V
VCC3B
*2
*3
MB91F233L, MB91233L
(VSS = AVSS = 0.0 V)
Parameter
Symbol
Operating ambient temperature
Power supply voltage
Analog power supply voltage
LCD reference voltage
Value
Unit
Remarks
Min
Max
Ta
−40
+ 85
°C
VCC
3.00
3.60
V
*1
VCC3
3.00
3.60
V
*4
3.00
3.60
V
2.20
3.60
V
VCC3IO
3.00
3.60
V
AVCC
3.00
3.60
V
V3
⎯
3.60
V
VCC3B
*2
*3
*1 : The standard power-supply voltage varies with the model of product.
*2 : Only for backup. Set VCC3 = AVCC = VCC3IO.
*3 : V3 must not exceed VCC.
*4 : For the relationships between VCC3 and operating frequencies, see section “4. AC Characteristics
(3) Operation Assurance Range”.
For the MB91V230, please inquire separately.
Note : For normal use, set VCC3 = VCC3B = AVCC = VCC3IO.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
48
DS07–16506–3E
MB91230 Series
3. DC Characteristics
MB91V230, MB91F233A
(VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C)
Parameter
Symbol
Pin name
ICC
Power supply
current
ICCT
VCC3
ICCH
ICCS
"H" level input
voltage
Conditions
VIL
"H" level output
voltage
VOH
"L" level output
voltage
VOL
Unit
Min
Typ
Max
Flash model normal
operation,
Ta = +25 °C,
FCP = 33 MHz,
FCPP = 16.5 MHz
⎯
65
75
mA
Flash model normal
operation,
Ta = +25 °C,
FCP = 33 MHz,
FCPP = 33 MHz
⎯
73
83
mA
RTC mode,
Ta = +25 °C,
FCP = 32 kHz
⎯
20
50
µA
STOP mode,
Ta = +25 °C,
FCP = 0 kHz
⎯
5
50
µA
SLEEP mode
FCP = 33 MHz,
FCPP = 16.5 MHz
⎯
21
25
mA
SLEEP mode
FCP = 33 MHz,
FCPP = 33 MHz
⎯
30
35
mA
⎯
⎯
VCC ×
0.8
⎯
VCC
V
X0A
VCC3B = 2.2 V to 3.6 V
VCC3
B×
0.8
⎯
VCC3B
V
⎯
⎯
VSS
⎯
VCC
× 0.2
V
X0A
VCC3B = 2.2 V to 3.6 V
VSS
⎯
VSS
+ 0.4
V
⎯
IOH = −4 mA
VCC
−0.5
⎯
VCC
V
⎯
IOL = 4 mA
VSS
⎯
0.4
V
VIH
“L” level input
voltage
Value
P64 to P67 IOL = 20 mA
Input leakage
current
IIL
⎯
⎯
−5
⎯
+5
µA
Open-drain
output leakage
current
Ileak
⎯
⎯
−10
⎯
+ 10
µA
Remarks
Watch timer,
RTC, LCDC
VCC3 = VCC3B =
2.4 V
When external
clock is used
When external
clock is used
(Continued)
DS07–16506–3E
49
MB91230 Series
(Continued)
(VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C)
Parameter
Symbol Pin name
Conditions
Value
Unit
Min
Typ
Max
50
100
200
kΩ
⎯
⎯
2.5
kΩ
⎯
⎯
15
kΩ
LCD internal
division resistance
RLCD
V0 - V1,
V1 - V2,
V2 - V3
COM0 to COM3
output impedance
RVCOM
COM0 to
COM3
SEG0 to SEG31
output impedance
RVSEG
SEG0 to
SEG31
LCDC leakage
current
ILCDC
V0 to V3,
COM0 to
COM3,
SEG0 to
SEG31
⎯
−5
⎯
+5
µA
INIT pin
pull-up resistor
INIT
INIT
⎯
25
50
100
kΩ
50
⎯
Remarks
V1 to V3 = 5.0 V
DS07–16506–3E
MB91230 Series
MB91F233L, MB91233L
(VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C)
Parameter
Symbol
Pin
name
ICC
ICC
Power supply
current
Vcc3
Value
Unit
Min
Typ
Max
Flash model normal
operation,
Ta = +25 °C,
FCP = 33 MHz,
FCPP = 16.5 MHz
⎯
65
75
mA
Flash model normal
operation,
Ta = +25 °C,
FCP = 33 MHz,
FCPP = 33 MHz
⎯
73
83
mA
ROM model normal
operation,
Ta = +25 °C,
FCP = 33 MHz,
FCPP = 16.5 MHz
⎯
45
55
mA
ROM model normal
operation,
Ta = +25 °C,
FCP = 33 MHz,
FCPP = 33 MHz
⎯
55
65
mA
ICCT
RTC mode,
Ta = +25 °C,
FCP = 32 kHz
⎯
20
50
µA
ICCH
STOP mode,
Ta = +25 °C,
FCP = 0 MHz
⎯
5
50
µA
SLEEP mode
FCP = 33 MHz,
FCPP = 16.5 MHz
⎯
21
25
mA
SLEEP mode
FCP = 33 MHz,
FCPP = 33 MHz
⎯
30
35
mA
ICCS
"H" level input
voltage
Conditions
⎯
⎯
VCC
× 0.8
⎯
VCC
V
X0A
VCC3B = 2.2 V to 3.6 V
VCC3B
× 0.8
⎯
VCC3B
V
⎯
⎯
VSS
⎯
VCC
× 0.15
V
X0A
VCC3B = 2.2 V to 3.6 V
VSS
⎯
VSS
+ 0.4
V
VCC = 3.3 V,
IOH = −2 mA
VCC
−0.5
⎯
VCC
V
VIH
"L" level input
voltage
VIL
"H" level output
voltage
VOH
⎯
Remarks
Watch timer,
RTC, LCDC
VCC3 = VCC3B =
2.4 V
When external
clock is used
When external
clock is used
(Continued)
DS07–16506–3E
51
MB91230 Series
(Continued)
(VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = −40 °C to +85 °C)
Parameter
"L" level output
voltage
Input leakage
current
Symbol
VOL
Pin
name
⎯
Conditions
IOL = 2 mA
P64 to 67 IOL = 10 mA
Value
Unit
Min
Typ
Max
VSS
⎯
0.4
V
IIL
⎯
⎯
−5
⎯
+5
µA
Open-drain output
leakage current
Ileak
⎯
⎯
−10
⎯
+ 10
µA
LCD internal
division resistance
RLCD
V0 - V1,
V1 - V2,
V2 - V3
⎯
50
100
200
kΩ
COM0 to COM3
output impedance
RVCOM
COM0 to
COM3
⎯
⎯
2.5
kΩ
SEG0 to SEG31
output impedance
RVSEG
SEG0 to
SEG31
⎯
⎯
15
kΩ
LCDC leakage
current
ILCDC
V0 to V3,
COM0 to
COM3,
SEG0 to
SEG31
⎯
−5
⎯
+5
µA
INIT pin
pull-up resistor
INIT
INIT
⎯
25
87
150
kΩ
52
Remarks
V1 to V3 = 5.0 V
DS07–16506–3E
MB91230 Series
4. AC Characteristics
(1) Main clock input standard
(MB91V230, MB91F233A : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −40 °C to +85 °C)
(MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −40 °C to +85 °C)
Symbol
Parameter
Pin
name
Value
Conditions
Min
Typ
Max
Unit
Input frequency
FC
⎯
3.6
4
4.2
MHz
Input clock cycle
tCYL
⎯
⎯
250
⎯
ns
Input clock pulse width
⎯
PWH/tCYL
PWL/tCYL
40
⎯
60
%
Input clock rise time
and fall time
tCR
tCF
⎯
⎯
⎯
5
ns
Internal operating
clock frequency
FCP
⎯
⎯
⎯
⎯
33.6
MHz
Internal operating
clock cycle time
tCP
⎯
⎯
29.7
⎯
⎯
ns
Peripheral clock
frequency
FCPP
⎯
⎯
⎯
⎯
33.6
MHz
Peripheral clock cycle
time
tCYCP
⎯
⎯
29.7
⎯
⎯
ns
X0
Remarks
At external clock
Peripheral clock
is derived from
internal operating clock divided
by 1/1 to 1/16.
tCYL
VSS + 0.4
PWH
VSS + 0.4
PWL
tCF
DS07–16506–3E
0.8 × VCC3
0.8 × VCC3
0.8 × VCC3
X0
tCR
53
MB91230 Series
(2) Subclock input standard
(MB91V230, MB91F233A : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −40 °C to +85 °C)
(MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −40 °C to +85 °C)
Symbol
Parameter
Input frequency
FCL
Input clock cycle
tLCYL
Pin
name
Value
Conditions
Remarks
kHz
At external
clock
Typ
Max
⎯
32.768
⎯
28.571
32.768
35.714
⎯
28.0
⎯
35.0
µs
⎯
X0A
Unit
Min
Input clock pulse width
⎯
PWLH/tLCYL
PWLL/tLCYL
45
⎯
55
%
Input clock rise time
and fall time
⎯
tCR/tLCYL
tCF/tLCYL
⎯
⎯
5
%
At external
clock
tLCYL
VSS + 0.4
PWLH
VSS + 0.4
PWLL
tCF
54
0.8 × VCC3B
0.8 × VCC3B
0.8 × VCC3B
X0A
tCR
DS07–16506–3E
MB91230 Series
(3) Operation Assurance Range
4.0
Internal power supply voltage VCC3 [V]
3.8
FCP = 33.6 MHz,VCC3 = 3.6 V
3.6
3.4
FCP = 33.6 MHz,VCC3 = 3.3 V
FCP = 8 MHz
3.2
3.0
PLL OFF
FCP = 32 MHz,
VCC3 = 3.0 V
PLL ON
FCP = 33.6 MHz,VCC3 = 3.0 V
2.8
2.6
FCP = 28 MHz,VCC3 = 2.7 V
2.4
2.2
MB91F233A
MB91F233L
2.0
MB91233L
1.8
32 kHz
5
10
15
20
25
30
35
40
Internal operation frequency FCP [MHz]
DS07–16506–3E
55
MB91230 Series
(4) PLL oscillation stabilization time (LOCK UP time)
(MB91V230, MB91F233A : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −40 °C to + 85 °C)
(MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −40 °C to + 85 °C)
Parameter
PLL oscillation stabilization
(LOCK UP time)
Symbol
tLOCK
Value
Min
Max
500
⎯
Unit
Remarks
µs
Time from when the PLL
starts operating to when its
oscillation becomes stable
(5) Reset input standards
(MB91V230, MB91F233A : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −40 °C to + 85 °C)
(MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −40 °C to + 85 °C)
Parameter
INIT input time
(at power-on)
INIT input time
(other than at power-on)
Symbol
tINITX
Pin
name
INIT
Value
Conditions
Unit
Remarks
⎯
ns
*1
⎯
ns
*2
Min
Max
⎯
tCP × 10
⎯
*1 : When turning the power on, keep INIT input until the oscillation circuit provides stable oscillation.
*2 : tCP indicates cycle time of CPU operating clock.
tINITX
INIT
56
VIL
VIL
DS07–16506–3E
MB91230 Series
(6)UART timing
(MB91V230, MB91F233A : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −40 °C to +85 °C)
(MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −40 °C to +85 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOV
Valid SIN → SCK ↑
tIVSH
SCK ↑ → Valid SIN hold time
Value
Conditions
Unit
Min
Max
SCK0 to SCK3
tCYCP * × 8
⎯
ns
SCK0 to SCK3,
SOT0 to SOT3
−80
+ 15
ns
Internal shift clock
SCK0 to SCK3, operation
SIN0 to SIN3
80
⎯
ns
tSHIX
SCK0 to SCK3,
SIN0 to SIN3
0
⎯
ns
Serial clock “H” pulse width
tSHSL
SCK0 to SCK3
tCYCP * × 4
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK0 to SCK3
tCYCP* × 4
⎯
ns
SCK ↓ → SOT delay time
tSLOV
⎯
150
ns
Valid SIN → SCK ↑
tIVSH
60
⎯
ns
SCK ↑ → Valid SIN hold time
tSHIX
60
⎯
ns
SCK0 to SCK3,
SOT0 to SOT3 External shift
clock operation
SCK0 to SCK3,
SIN0 to SIN3
SCK0 to SCK3,
SIN0 to SIN3
Remarks
* : tCYCP represents the cycle time of peripheral operating clock.
Note : The above specification applies to clock synchronous mode operation.
DS07–16506–3E
57
MB91230 Series
• Internal shift clock mode
tSCYC
VOH
SCK0 to SCK3
VOL
VOL
tSLOV
VOH
SOT0 to SOT3
VOL
tIVSH
SIN0 to SIN3
tSHIX
VOH
VOH
VOL
VOL
• External shift clock mode
tSLSH
SCK0 to SCK3
tSHSL
VOH
VOL
VOH
VOL
tSLOV
VOH
SOT0 to SOT3
VOL
tIVSH
SIN0 to SIN3
58
tSHIX
VOH
VOH
VOL
VOL
DS07–16506–3E
MB91230 Series
(7) Free-run timer clock, Reload timer event input, Up/down counter input, Input capture input,
Interrupt input timing
(MB91V230, MB91F233A : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −40 °C to + 85 °C)
(MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V,
Ta = −40 °C to + 85 °C)
Parameter
Symbol
Input pulse width
Conditions
Pin name
CKI0, CKI1
TIN0 to TIN3
IC0, IC1
AIN0, AIN1
BIN0, BIN1
ZIN0, ZIN1
tTIWH
tTIWL
⎯
INT0 to INT15
Value
Unit
Remarks
Min
Max
tCYCP × 2
⎯
ns
*
tCYCP × 3
⎯
ns
*
* : tCYCP indicates peripheral clock cycle time.
tTIWH
tTIWL
VIH
VIL
VIH
VIL
(8) A/D trigger, PWI (PWC) input timing
(MB91V230, MB91F233A : VCC = 4.0 V to 5.25 V, VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V,
VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C)
(MB91F233L, MB91233L : VCC = VCC3 = VCC3B = VCC3IO = AVCC = 3.0 V to 3.6 V,
VSS = AVSS = 0.0 V, Ta = −40 °C to + 85 °C)
Value
CondiParameter
Symbol
Pin name
Unit Remarks
tions
Min
Max
A/D trigger input (falling)
tTADTG
ADTG0
ADTG1
⎯
tCYCP × 2
⎯
ns
*
PWI (PWC) input (rising)
tPWI
PWI0, PWI1
⎯
tCYCP × 2
⎯
ns
*
* : tCYCP indicates peripheral clock cycle time.
tTADTG
tPWI
VIH
VIL
DS07–16506–3E
VIH
VIL
59
MB91230 Series
5. Electrical Characteristics for the A/D Converter
(VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, AVRH = 3.0 V to 3.6 V, Ta = 0 °C to +85 °C)
Value
Parameter
Unit
Remarks
Min
Typ
Max
⎯
⎯
10
bit
−5.0
⎯
+5.0
LSB
−3.5
⎯
+3.5
LSB
−2.5
⎯
+2.5
LSB
Zero transition voltage*1
AVRL −
2.0 LSB
AVRL +
1.0 LSB
AVRL +
6.0 LSB
V
Full scale transition voltage*1
AVRH−
5.5 LSB
AVRH−
1.0 LSB
AVRH+
3.0 LSB
V
1.69*2
⎯
⎯
µs
Power supply current
(analog+digital)
⎯
3.6
⎯
mA
⎯
⎯
10
µA
At power-down*4
Reference power supply current
(between AVRH and AVRL)
⎯
470
⎯
µA
AVRH = 3.0 V,
At AVRL = 0.0 V*3
⎯
⎯
5
µA
At power-down*4
Analog input capacitance
⎯
40
⎯
pF
Inter-channel disparity
⎯
⎯
4
LSB
Resolution
Total error*
1
Nonlinear error*
1
Differential linear error*
1
Conversion time
AVCC = 3.3 V,
At AVRH = 3.3 V
At CPU sleep mode
*1 : Measured in the CPU sleep state
*2 : It depends on the clock cycle supplied to peripheral resources.
*3 : AVRL pin is only for FLGA package product. AVRL pin is connected to AVSS inside the IC on LQFP package
product.
*4 : The current when the CPU is in stop mode and the A/D converter is not operating.
60
DS07–16506–3E
MB91230 Series
• About the external impedance of the analog input and its sampling time
• A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely
affecting A/D conversion precision.
• Analog input circuit model
R
Analog input
Comparator
C
During sampling : ON
R
C
MB91233L
0.18 kΩ (Max)
63.0 pF (Max)
MB91F233A
0.18 kΩ (Max)
39.0 pF (Max)
MB91F233L
0.18 kΩ (Max)
39.0 pF (Max)
Note : The values are reference values.
• To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the
external impedance so that the sampling time is longer than the minimum value.
• The relationship between the external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
MB91F233A
MB91F233L
100
90
80
70
60
50
40
30
20
10
0
External impedance (kΩ)
External impedance (kΩ)
(External impedance = 0 kΩ to 100 kΩ)
MB91233L
0
5
10
15
20
25
30
Minimum sampling time (µs)
35
MB91F233A
MB91F233L
20
18
16
14
12
10
8
6
4
2
0
MB91233L
0
1
2
3
4
5
6
7
8
Minimum sampling time (µs)
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• About errors
As |AVRH − AVRH (AVSS)| becomes smaller, values of relative errors grow larger.
DS07–16506–3E
61
MB91230 Series
6. Electrical Characteristics for the D/A Converter
(VCC3IO = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0.0 V, Ta = 0 °C to +85 °C)
Parameter
Value
Unit
Remarks
Min
Typ
Max
⎯
⎯
8
bit
Nonlinear error
−2.0
⎯
+2.0
LSB
When the output is unloaded
Differential linear error
−1.0
⎯
+1.0
LSB
When the output is unloaded
⎯
0.6
⎯
µs
When load capacitance
(CL) = 20 pF
⎯
3.0
⎯
µs
When load capacitance
(CL) = 100 pF
2.0
2.9
3.8
kΩ
⎯
40
⎯
µA
10 µs conversion, when the
output is unloaded
⎯
⎯
460*
µA
When the input digital code is
fixed at 7AH or 85H
⎯
0.1
⎯
µA
At power-down
Resolution
Conversion speed
Output impedance
Analog current
* : The current consumption by D/A converter varies with input digital code.
The standard value indicates the current consumed when the digital code that maximizes the current consumption is input.
7. Flash Memory Write/Erase Characteristics
Parameter
Conditions
Value
Min
Typ
Max
Unit
Remarks
Sector erase time
Ta = + 25 °C,
Vcc = 5.0 V
⎯
1
15
s
Excludes 00H programming prior erasure
Chip erase time
Ta = + 25 °C,
Vcc = 5.0 V
⎯
10
⎯
s
Excludes 00H programming prior erasure
Byte write time
Ta = + 25 °C,
Vcc = 5.0 V
⎯
8
3600
µs
Not including systemlevel overhead time.
Chip write time
Ta = + 25 °C,
Vcc = 5.0 V
⎯
2.1
⎯
s
Not including systemlevel overhead time.
10000
⎯
⎯
cycle
20
⎯
⎯
year
Erase/write cycle
⎯
Flash data retention time Average Ta = + 85 °C
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C).
62
DS07–16506–3E
MB91230 Series
■ ORDERING INFORMATION
Part number
Package
MB91F233APMC1-GE1
120-pin plastic LQFP
(FPT-120P-M24)
MB91F233LPMC1-GE1
120-pin plastic LQFP
(FPT-120P-M24)
MB91F233LLGA-GE1
128-pin plastic FLGA
(LGA-128P-M01)
MB91233LPMC1-G-XXXE1
120-pin plastic LQFP
(FPT-120P-M24)
MB91233LLGA-G-xxx-BNDE1
128-pin plastic FLGA
(LGA-128P-M01)
MB91V230CR-ES
401-pin ceramic PGA
(PGA-401C-A02)
DS07–16506–3E
Remarks
For evaluation
63
MB91230 Series
■ PACKAGE DIMENSIONS
120-pin plastic LQFP
Lead pitch
0.40 mm
Package width ×
package length
14.0 mm × 14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LFQFP120-14×14-0.40
(FPT-120P-M24)
120-pin plastic LQFP
(FPT-120P-M24)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
* 14.00±0.10(.551±.004)SQ
90
61
91
60
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
INDEX
120
31
"A"
0~8˚
LEAD No.
1
0.40(.016)
30
0.16±0.05
(.006±.002)
0.07(.003)
M
0.145±0.055
(.006±.002)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
©2006-2008
FUJITSU MICROELECTRONICS LIMITED F120036S-c-1-2
C
2006 FUJITSU LIMITED F120036S-c-1-1
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
(Continued)
64
DS07–16506–3E
MB91230 Series
(Continued)
128-pin plastic FLGA
Lead pitch
0.65 mm
Package width ×
package length
9.0 × 9.0 mm
Lead shape
Land
Sealing method
Plastic mold
Mounting height
1.00 mm MAX
Weight
0.14 g
(LGA-128P-M01)
128-pin plastic FLGA
(LGA-128P-M01)
8.30(.327)
REF
7.15(.282)
REF
9.00±0.10(.354±.004)SQ
0.65(.026)
TYP
12
11
10
9
8
7
6
5
4
3
2
1
8.30(.327)
REF
7.15(.282)
REF
0.65(.026)
TYP
(0.50)
((.020))
M L K J H G F E D C B A
INDEX AREA
1.00(.040)MAX
(Seated Height)
3-ø0.50
(3-ø.020)
(0.50)
((.020))
Index
128-ø0.35±0.05
(128-ø.014±.002)
ø0.08(ø.003)
M
0.08(.003)
C
2004-2008 FUJITSU MICROELECTRONICS LIMITED L128001S-c-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/package/en-search/
DS07–16506–3E
65
MB91230 Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
⎯
⎯
Change Results
Changed the package;
FPT-120P-M05 → FPT-120P-M24
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Added the items in MB91V230, MB91F233A.
50
3. DC Characteristics
• MB91V230, MB91F233A
Added the “INIT pin pull-up resistor”
52
3. DC Characteristics
• MB91F233L, MB91233L
Added the “INIT pin pull-up resistor”
4. AC Characteristics
(6) UART timing
Changed the values for the symbols below.
- tSLOV ; 80 → + 15 (Max value)
- tIVSH ; 100 → 80 (Min value)
- tSHIX ; 60 → 0 (Min value)
5. Electrical Characteristics for the
A/D Converter
Changed the descriptions of values for "Zero transition
voltage" and "Full scale transition voltage".
Unit : LSB → V
[Numerical value] → AVRL ± [Numerical value] LSB
AVRH ± [Numerical value] →
AVRH ± [Numerical value] LSB
46
47
57
Added the items in MB91F233L, MB91233L.
Changed as follows for “Power supply voltage (analog +
digital)”
Parameter : power supply voltage →
power supply current
Value (Max) 5 → 10
Remarks : At power-down*4
60
Changed the maximum value at power-down for
“Reference power supply current (between AVRH and
AVRL)”.
10 → 5
■ ORDERING INFORMATION
Changed the part numbers;
MB91F233APFF-GE1 → MB91F233APMC1-GE1
MB91F233LPFF-GE1 → MB91F233LPMC1-GE1
MB91233LPFF-G-XXXE1 →
MB91233LPMC1-G-XXXE1
■ PACKAGE DIMENSIONS
Changed the figure of package.
FPT-120P-M05 → FPT-120P-M24
63
64
The vertical lines marked in the left side of the page show the changes.
66
DS07–16506–3E
MB91230 Series
MEMO
DS07–16506–3E
67
MB91230 Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3347 Fax: +81-3-5322-3387
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
FUJITSU MICROELECTRONICS AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://www.fma.fujitsu.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://www.fmal.fujitsu.com/
Europe
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Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
Rm. 3102, Bund Center, No.222 Yan An Road (E),
Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or
any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other
right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property
rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
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weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages
arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
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