ds91265-ds07-16702-3e.pdf

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16702-4E
32-bit Microcontrollers
CMOS
FR60Lite MB91265A Series
MB91267A/267NA/F267A/F267NA/V265A
■ DESCRIPTION
The MB91265A series is a 32-bit RISC microcontroller designed by Fujitsu for embedded control applications
which require high-speed processing.
The CPU is used the FR family* and the compatibility of FR60Lite.
MB91267NA/F267NA loads the C-CAN (1 channel) .
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
■ FEATURES
• FR60Lite CPU
• 32-bit RISC, load/store architecture with a five-stage pipeline
• Maximum operating frequency : 33 MHz (oscillation frequency 4.192 MHz, oscillation frequency 8-multiplier
(PLL clock multiplication method)
• 16-bit fixed length instructions (basic instructions)
• Execution speed of instructions : 1 instruction per cycle
• Memory-to-memory transfer, bit handling, barrel shift instructions, etc. : Instructions suitable for embedded
applications
• Function entry/exit instructions, multiple-register load/store instructions : Instructions adapted for C-language
• Register interlock function : Facilitates coding in assembler.
• Built-in multiplier with instruction-level support
• 32-bit multiplication with sign : 5 cycles
• 16-bit multiplication with sign : 3 cycles
• Interrupt (PC, PS save) : 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• Instruction compatible with FR family
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2005-2007 FUJITSU LIMITED All rights reserved
MB91265A Series
(Continued)
• Internal peripheral functions
MB91V265A
Evaluation
product
MB91F267A
MB91F267NA
MB91267A
Flash memory product
MASK ROM product
PGA-401
(Lead pitch
2.54 mm
interstitial)
LQFP-64
(Lead pitch 0.65 mm)
External SRAM
128 Kbytes
RAM size
24 Kbytes
4 Kbytes
C-CAN
1 channel
Package
ROM/Flash size
No
MB91267NA
1 channel
No
1 channel
• A/D converter (sequential comparison type)
Resolution : 8/10 bits : 4 channels × 1 unit, 7 channels × 1 unit
Conversion time : 1.2 µs (Minimum conversion time system clock at 33 MHz)
1.35 µs (Minimum conversion time system clock at 20 MHz)
• External interrupt input : 8 channels
• Bit search module (for REALOS)
Function for searching the MSB (upper bit) in each word for the first 1-to-0 inverted bit position
• C-CAN 32MSB : 1 channel (loaded in MB91267NA/F267NA)
• UART (Full-duplex double buffer) : 2 channels
Selectable parity On/Off
Asynchronous (start-stop synchronized) or clock-synchronous communications selectable
Internal timer for dedicated baud rate (U-TIMER) on each channel
External clock can be used as transfer clock
Error detection function for parity, frame, and overrun errors
• 8/16-bit PPG timer : 8 channels (at 8-bit) / 4 channels (at 16-bit)
• Timing generator
• 16-bit reload timer : 3 channels (with cascade mode, without output of reload timer 0)
• 16-bit free-run timer : 3 channels
• 16-bit PWC timer : 1 channel
• Input capture : 4 channels (interface with free-run timer)
• Output compare : 6 channels (interface with free-run timer)
• Waveform generator
Various waveforms which are generated by using output compare, 16-bit PPG timer 0, and 16-bit dead timer
• SUM of products macro
RAM : instruction RAM (I-RAM) 256 × 16-bit
coefficient RAM (X-RAM) 64 × 16-bit
variable RAM (Y-RAM)
64 × 16-bit
Execution of 1 cycle MAC (16-bit × 16-bit + 40 bits)
Operation results are extracted rounded from 40 to 16 bits
• DMAC (DMA Controller) : 5 channels
Operation of transfer and activation by internal peripheral interrupts and software
• Watchdog timer
• Low-power consumption mode
Sleep/stop function
• Package : LQFP-64
• Technology : CMOS 0.35 µm
• Power supply : 1-power supply (Vcc = 4.0 V to 5.5 V)
2
MB91265A Series
■ PIN ASSIGNMENT
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVCC
AVRH2
AVRH1
P43/INT3
P42/INT2
P41/INT1
P40/INT0
P30/RTO0
P31/RTO1
P32/RTO2
P33/RTO3
P34/RTO4
P35/RTO5
INIT
P36/PPG7/INT7
P37/PPG4
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LQFP-64
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VSS
X1
X0
MD0
MD1
MD2
PG1/PPG0
P27
P26/IC1
P25/IC0
P24/CKI
P23/DTTI
P22/PWI0
P21/ADTG2/IC3
P20/ADTG1/IC2
P17/PPG6/TX0∗
VCC
P00/PPG1/INT4
P01/PPG2
P02/PPG3/INT5
P03/TIN0
P04/TIN1
P05/TIN2
P06/TOT1
P07/TOT2
P10/SOT0
P11/SIN0
P12/SCK0
P13/SOT1
P14/SIN1
P15/SCK1
P16/PPG5/INT6/RX0∗
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVSS
ACC
AN0/P50
AN1/P51
AN2/P52
AN3/P53
AN4/P54
AN5/P55
AN6/P56
AN7/P57
AN8/P44
AN9/P45
AN10/P46
NMI
C
VSS
(FPT-64P-M23)
* : C-CAN pin is loaded in MB91267NA/F267NA.
3
MB91265A Series
■ PIN DESCRIPTION
Pin no.
I/O
Pin
Circuit
name
type*1
AN0
3
G
Description
Analog input terminal of A/D converter 1.
This function becomes valid when set the corresponding AICR1 register to analog input.
P50
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
AN1
Analog input terminal of A/D converter 1.
This function becomes valid when set the corresponding AICR1 register to analog input.
4
G
P51
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
AN2
Analog input terminal of A/D converter 1.
This function becomes valid when set the corresponding AICR1 register to analog input.
5
G
P52
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
AN3
Analog input terminal of A/D converter 1.
This function becomes valid when set the corresponding AICR1 register to analog input.
6
G
P53
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
AN4
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
7
G
P54
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
AN5
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
8
G
P55
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
AN6
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
9
G
P56
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
AN7
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
10
G
P57
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
AN8
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
11
G
P44
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
AN9
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog input.
12
G
P45
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
(Continued)
4
MB91265A Series
Pin no.
I/O
Pin
Circuit
name
type*1
AN10
13
G
NMI
H
PPG1
E
PPG2
20
Output terminal of PPG timer 1.
This function becomes valid when output of PPG timer 1 is set to enabled.
General purpose input/output port.
This function becomes valid when output of PPG timer 1 and external interrupt input
are set to disabled.
P00
19
NMI (Non Maskable Interrupt) input terminal.
External interrupt input terminal.
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
INT4
18
Analog input terminal of A/D converter 2.
This function becomes valid when set the corresponding AICR2 register to analog
input.
General purpose input/output port.
This function becomes valid when analog input is set to disabled.
P46
14
Description
D
Output terminal of PPG timer 2.
This function becomes valid when output of PPG timer 2 is set to enabled.
P01
General purpose input/output port.
This function becomes valid when output of PPG timer 2 is set to disabled.
INT5
External interrupt input terminal.
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
PPG3
E
Output terminal of PPG timer 3.
This function becomes valid when output of PPG timer 3 is set to enabled.
P02
General purpose input/output port.
This function becomes valid when output of PPG timer 3 and external interrupt input
are set to disabled.
TIN0
External trigger input terminal of reload timer 0.
Since this input is used as required while the trigger input is enabled, the port output
must remain off unless intentionally used.
21
D
P03
General purpose input/output port.
This function becomes valid when external clock input of reload timer 0 is set to
disabled.
TIN1
External trigger input terminal of reload timer 1.
Since this input is used as required while the trigger input is enabled, the port output
must remain off unless intentionally used.
22
D
P04
General purpose input/output port.
This function becomes valid when external clock input of reload timer 1 is set to
disabled.
TIN2
External trigger input terminal of reload timer 2.
Since this input is used as required while the trigger input is enabled, the port output
must remain off unless intentionally used.
23
D
P05
General purpose input/output port.
This function becomes valid when external clock input of reload timer 2 is set to
disabled.
(Continued)
5
MB91265A Series
Pin no.
I/O
Pin
Circuit
name
type*1
TOT1
24
D
Description
Output terminal of reload timer 1.
This function becomes valid when output of reload timer 1 is set to enabled.
P06
General purpose input/output port.
This function becomes valid when output of reload timer 1 is set to disabled.
TOT2
Output terminal of reload timer 2.
This function becomes valid when output of reload timer 2 is set to enabled.
25
D
P07
SOT0
26
D
General purpose input/output port.
This function becomes valid when output of reload timer 2 is set to disabled.
UART0 data output terminal.
This function becomes valid when data output of UART0 is set to enabled.
P10
General purpose input/output port.
This function becomes valid when data output of UART0 is set to disabled.
SIN0
UART0 data input terminal.
Since this input is used as required while the UART0 input is enabled, the port output
must remain off unless intentionally used.
27
D
General purpose input/output port.
This function becomes valid when data input of UART0 is set to disabled.
P11
SCK0
28
D
UART0 clock input/output terminal.
This function becomes valid when clock output of UART0 is set to enabled.
P12
General purpose input/output port.
This function becomes valid when clock output of UART0 is set to disabled.
SOT1
UART1 data output terminal.
This function becomes valid when data output of UART1 is set to enabled.
29
D
P13
General purpose input/output port.
This function becomes valid when data output of UART1 is set to disabled.
SIN1
UART1 data input terminal.
Since this input is used as required while the UART1 input is enabled, the port output
must remain off unless intentionally used.
30
D
General purpose input/output port.
This function becomes valid when data input of UART1 is set to disabled.
P14
SCK1
31
D
P15
UART1 clock input/output terminal.
This function becomes valid when clock output of UART1 is set to enabled.
General purpose input/output port.
This function becomes valid when clock output of UART1 is set to disabled.
(Continued)
6
MB91265A Series
Pin no.
Pin
name
I/O
Circuit
type*1
INT6
External interrupt input terminal.
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
PPG5
Output terminal of PPG timer 5.
This function becomes valid when output of PPG timer 5 is set to enabled.
32
E
RX0
RX0 input terminal of C-CAN0 (MB91267NA/F267NA ) .
Since this input is used as required while the RX0 input is enabled, port output must
remain off unless intentionally used.
P16
General purpose input/output port.
This function becomes valid when output of PPG timer 5 and RX0 input*2 of C-CAN0
are set to disabled.
Output terminal of PPG timer 6.
This function becomes valid when output of PPG timer 6 is set to enabled.
PPG6
33
34
TX0
D
TX0 output terminal of C-CAN0 (MB91267NA/F267NA) .
This function becomes valid when TX0 output of C-CAN0 is set to enabled.
P17
General purpose input/output port.
This function becomes valid when output of PPG timer 6 and TX0 output*2 of C-CAN0
are set to disabled.
ADTG1
External trigger input terminal of A/D converter 1.
Since this input is used as required while it selects as A/D activation trigger cause, the
port output must remain off unless intentionally used.
IC2
Trigger input terminal of input capture 2.
The port can serve as an input when set for input with the setting of the input capture
trigger input. When the port is used for input capture input, this input is used as
required. The port output must therefore remain off unless intentionally used.
D
General purpose input/output port.
This function becomes valid when the setting of the external trigger input of A/D
converter 1 or the setting of the input capture trigger input is set to disabled.
P20
35
Description
ADTG2
External trigger input terminal of A/D converter 2.
Since this input is used as required while it selects as A/D activation trigger cause, the
port output must remain off unless intentionally used.
IC3
Trigger input terminal of input capture 3.
The port can serve as an input when set for input with the setting of the input capture
trigger input. When the port is used for input capture input, this input is used as
required. The port output must therefore remain off unless intentionally used.
D
General purpose input/output port.
This function becomes valid when the setting of the external trigger input of A/D
converter 2 or the setting of the input capture trigger input is set to disabled.
P21
PWI0
36
D
P22
Pulse width counter input of PWC timer 0
This function becomes valid when pulse width counter input of PWC timer 0 is set to
enabled.
General purpose input/output port.
This function becomes valid when pulse width counter input of PWC timer 0 is set to
disabled.
(Continued)
7
MB91265A Series
Pin no.
I/O
Pin
Circuit
name
type*1
DTTI
37
D
Control input signal of multi-function timer waveform generator output RTO0 to RTO5.
This function becomes valid when DTTI input is set to enabled.
P23
General purpose input/output port.
This function becomes valid when input of DTTI is set to disabled.
CKI
External clock input terminal of free-run timer.
Since this input is used as required while the port is used for external clock input
terminal of free-run timer, the port output must remain off unless intentionally used.
38
D
P24
General purpose input/output port.
This function becomes valid when external clock input of free-run timer is set to
disabled.
IC0
Trigger input terminal of input capture 0.
The port can serve as an input when set for input with the setting of the trigger input of
input capture 0. When the port is used for input capture input, this input is used as
required. The port output must therefore remain off unless intentionally used.
39
D
P25
General purpose input/output port.
This function becomes valid when trigger input of input capture 0 is set to disabled.
IC1
Trigger input terminal of input capture 1.
The port can serve as an input when set for input with the setting of the trigger input of
input capture 1. When the port is used for input capture input, this input is used as
required. The port output must therefore remain off unless intentionally used.
40
D
General purpose input/output port.
This function becomes valid when trigger input of input capture 1 is set to disabled.
P26
41
Description
P27
D
PPG0
42
D
PG1
General purpose input/output port.
Output terminal of PPG timer 0.
This function becomes valid when output of PPG timer 0 is set to enabled.
General purpose input/output port.
This function becomes valid when output of PPG timer 0 is set to disabled.
43
MD2
H, K
Mode terminal 2.
Setting this pin determines the basic operation mode. Connect to VCC or VSS.
The circuit type of flash memory models is K.
44
MD1
H, K
Mode terminal 1.
Setting this pin determines the basic operation mode. Connect to VCC or VSS.
The circuit type of flash memory models is K.
45
MD0
H
Mode terminal 0.
Setting this pin determines the basic operation mode. Connect to VCC or VSS.
46
X0
A
Clock (oscillation) input terminal.
47
X1
A
Clock (oscillation) output terminal.
PPG4
49
D
P37
Output terminal of PPG timer 4.
This function becomes valid when output of PPG timer 4 is set to enabled.
General purpose input/output port.
This function becomes valid when output of PPG timer 4 is set to disabled.
(Continued)
8
MB91265A Series
Pin no.
I/O
Pin
Circuit
name
type*1
External interrupt input terminal.
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
INT7
50
PPG7
E
INIT
I
External reset input terminal.
J
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator. This function becomes
valid when waveform generator output of multi-function timer is set to enabled.
RTO5
52
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
P35
RTO4
53
J
RTO3
J
RTO2
J
RTO1
J
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator. This function becomes
valid when waveform generator output of multi-function timer is set to enabled.
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
P31
RTO0
57
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator. This function becomes
valid when waveform generator output of multi-function timer is set to enabled.
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
P32
56
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator. This function becomes
valid when waveform generator output of multi-function timer is set to enabled.
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
P33
55
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator. This function becomes
valid when waveform generator output of multi-function timer is set to enabled.
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
P34
54
Output terminal of PPG timer 7.
This function becomes valid when output of PPG timer 7 is set to enabled.
General purpose input/output port.
This function becomes valid when output of PPG timer 7 is set to disabled.
P36
51
Description
J
Waveform generator output terminal of multi-function timer.
This terminal outputs waveform set at the waveform generator. This function becomes
valid when waveform generator output of multi-function timer is set to enabled.
P30
General purpose input/output port.
This function becomes valid when output of waveform generator is set to disabled.
INT0
External interrupt input terminal.
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
58
E
P40
General purpose input/output port.
This function becomes valid when external interrupt input is set to disabled.
(Continued)
9
MB91265A Series
(Continued)
Pin no.
I/O
Pin
Circuit
name
type*1
INT1
59
E
Description
External interrupt input terminal.
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
P41
General purpose input/output port.
This function becomes valid when external interrupt input is set to disabled.
INT2
External interrupt input terminal.
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
60
E
P42
General purpose input/output port.
This function becomes valid when external interrupt input is set to disabled.
INT3
External interrupt input terminal.
Since this input is used as required while the corresponding external interrupt is
enabled, the port output must remain off unless intentionally used.
61
E
P43
General purpose input/output port.
This function becomes valid when external interrupt input is set to disabled.
*1 : For the I/O circuit type, refer to “ ■ I/O CIRCUIT TYPE ”
*2 : C-CAN is set in MB91267NA/F267NA.
• Power supply and GND pins
Pin no.
Pin name
10
Description
16, 48
Vss
GND pins.
Apply equal potential to all of the pins.
17
Vcc
Power supply pin.
Apply equal potential to all of the pins.
64
AVcc
63
AVRH2
Analog reference power supply pin for A/D converter 2.
62
AVRH1
Analog reference power supply pin for A/D converter 1.
1
AVss
15
C
2
ACC
Analog power supply pin for A/D converter.
Analog GND pin for A/D converter.
Condenser connection pin for internal regulator.
Condenser connection pin for analog.
MB91265A Series
■ I/O CIRCUIT TYPE
Type
Circuit type
Remarks
X1
Clock input
A
Oscillation feedback resistance
for high speed (main clock oscillation) :
approx. 1 MΩ
X0
Standby control
P-ch
Pull-up control
• CMOS level output
• CMOS level hysteresis input
Digital output
• With standby control
• With Pull-up control
P-ch
D
Digital output
• IOL = 4 mA
N-ch
Digital input
Standby control
P-ch
Pull-up control
• CMOS level output
• CMOS level hysteresis input
Digital output
• Without standby control
• With Pull-up control
P-ch
E
Digital output
• IOL = 4 mA
N-ch
Digital input
(Continued)
11
MB91265A Series
Type
Circuit type
Remarks
Digital output
P-ch
Digital output
G
N-ch
Digital input
Standby control
Analog input
• Analog/CMOS level hysteresis
input/output pin
• CMOS level output
• CMOS level hysteresis input
(attached with standby control)
• Analog input
(Analog input is enabled when AICR’s
corresponding bit is set to “1”.)
• IOL = 4 mA
• CMOS level hysteresis input
• Without standby control
P-ch
H
N-ch
Digital input
• CMOS level hysteresis input
P-ch
• With pull-up resistor
• Without standby control
P-ch
I
N-ch
Digital input
(Continued)
12
MB91265A Series
(Continued)
Type
Circuit type
Remarks
• CMOS level output
• CMOS level hysteresis input
Digital output
• With standby control
P-ch
Digital output
J
• IOL = 12 mA
N-ch
Digital input
Standby control
Flash memory product only
• CMOS level input
N-ch
• High voltage control for test of flash
N-ch
K
N-ch
N-ch
Control signal
N-ch
Mode input
13
MB91265A Series
■ HANDLING DEVICES
Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage greater than VCC pin or less than VSS pin is applied to an input or
output pin or if an above-rating voltage is applied between VCC and VSS pins.
A latch-up, if it occurs, significantly increases the power supply current and may cause thermal destruction of
an element. When you use a CMOS IC, be very careful not to exceed the absolute maximum rating.
Treatment of Unused Input Pins
Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor.
About Power Supply Pins
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply
and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals
caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 µF between VCC and VSS pins
near this device.
About Crystal Oscillator Circuit
Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that X0
and X1 pins the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as
close to the device as possible.
It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane
because stable operation can be expected with such a layout.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
About Mode Pins (MD0 to MD2)
These pins should be connected directly to VCC or VSS pins.
To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that
the distance between the mode pins and VCC or VSS pins is as short as possible and the connection impedance
is low.
Operation at Start-up
Be sure to execute setting initialized reset (INIT) with INIT pin immediately after start-up.
Also, in order to provide the oscillation stabilization wait time for the oscillation circuit immediately after start-up,
hold the “L” level input to the INIT pin for the required stabilization wait time (For INIT via the INIT pin, the
oscillation stabilization wait time setting is initialized to the minimum value) .
14
MB91265A Series
Order of power turning ON/OFF
Use the following procedure for turning the power on or off.
Note that, even if the A/D converter is not used, keep the following pins connected with the level as described
below.
AVCC = VCC level
AVSS = VSS level
• When Powering ON : VCC→AVCC→AVRH
• When Powering OFF : AVRH→AVCC→VCC
About Oscillation Input at Power On
When turning the power on, maintain clock input until the device is released from the oscillation stabilization
wait state.
15
MB91265A Series
Caution for operation during PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
External clock
When external clock is selected, the opposite phase clock to X0 pin must be supplied to X1 pin simultaneously.
If the STOP mode (oscillation stop mode) is used simultaneously, the X1 pin is stopped with the "H" output. So,
when STOP mode is specified, approximately 1 kΩ of resistance should be added externally to avoid the collision
of output.
The following figure shows using an external clock.
X0
X1
MB91265A series
Using an external clock
C pin
A bypass capacitor of approximately 0.1 µF should be connected the C pin for built-in regulator.
C
MB91265A series
0.1 µF
VSS
GND
ACC pin
A capacitor of approximately 0.1 µF should be inserted between the ACC pin and the AVSS pin as this product
has built-in A/D converter.
ACC
MB91265A series
0.1 µF
AVSS
16
MB91265A Series
Clock Control Block
Input the “L” signal to the INIT pin to assure the clock oscillation stabilization wait time.
Switch Shared Port Function
To switch between the use as a port and the use as a dedicated pin, use the port function register (PFR) .
Low Power Consumption Mode
To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR :
timebase counter control register) and be sure to use the following sequence
(LDI
#value_of_standby, R0) : value_of_standby is write data to STCR.
(LDI
#_STCR, R12)
: _STCR is address (481H) of STCR.
STB
R0, @R12
: Writing to standby control register (STCR)
LDUB
@R12, R0
: STCR read for synchronous standby
LDUB
@R12, R0
: Dummy re-read of STCR
NOP
: NOP × 5 for arrangement of timing
NOP
NOP
NOP
NOP
In addition, please set I flag, ILM, and ICR to diverge to the interruption handler that is the return factor after the
standby returns.
• Please do not do the following when the monitor debugger is used.
• Break point setting for above instruction lines
• Step execution for above instruction lines
17
MB91265A Series
Notes on the PS register
As the PS register is processed by some instructions in advance, exception handling below may cause the
interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register
to be updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it
performs operations before and after the EIT as specified in either case.
• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS
instruction is (a) acceptance of a user interrupt, (b) single-stepped, or (c) breaks in response to a data event
or emulator menu :
1) The D0 and D1 flags are updated in advance.
2) An EIT handling routine (user interrupt or emulator) is executed.
3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed, and the D0 and D1 flags are updated
to the same values as in 1).
• The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed
to allow the interrupt.
1) The PS register is updated in advance.
2) An EIT handling routine (user interrupt) is executed.
3) Upon returning from the EIT, the above instructions are executed, and the PS register is updated to the
same value as in 1).
Watchdog Timer
The watchdog timer built in this model monitors a program that it defers a reset within a certain period of time.
The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer function from
being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on
operating programs until it resets the CPU.
As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops
program execution.
For those conditions to which this exception applies, refer to “ ■ NOTE ON DEBUGGER”.
18
MB91265A Series
■ NOTE ON DEBUGGER
• Step execution of RETI command
If an interrupt occurs frequently during step execution, the corresponding interrupt handling routine is executed
repeatedly after step execution.
This will prevent the main routine and low-interrupt-level programs from being executed.
Do not execute step of RETI instruction for escape.
Disable the corresponding interrupt and execute debugger when the corresponding interrupt handling routine
no longer needs debugging.
• Operand break
Do not apply a data event break to access to the area containing the address of a system stack pointer.
• Execution in an unused area of flash memory
Accidentally executing an instruction in an unused area of flash memory (with data placed at 0xFFFF) prevents
breaks from being accepted.
To prevent this, the code event address mask function of the debugger should be used to cause a break when
accessing an instruction in an unused area.
• Power-on debugging
All of the following three conditions must be satisfied when the power supply is turned off by power-on debugging.
(1) The time for the user power to fall from 0.9 VCC to 0.5 VCC is 25 µs or longer.
Note : In a dual-power system, VCC indicates the external I/O power supply voltage.
(2) CPU operating frequency must be higher than 1 MHz.
(3) During execution of user program
• Interrupt handler for NMI request (tool)
Add the following program to the interrupt handler to prevent the device from malfunctioning in case the factor
flag to be set only in response to a break request from the ICE is set, for example, by an adverse effect of noise
to the DSU pin while the ICE is not connected. Enable to use the ICE while adding this program.
Additional location
Next interrupt handler
Interrupt source
: NMI request (tool)
Interrupt number
: #13 (decimal) , 0D (hexadecimal)
Offset
: 3C8H
Address TBR is default
: 000FFFC8H
Additional program
STM
(R0, R1)
LDI
#B00H, R0;
LDI
#0, R1
STB
R1, @R0
LDM
(R0, R1)
: B00H is the address of DSU break factor register.
: Clear the break factor register.
RETI
19
MB91265A Series
■ BLOCK DIAGRAM
FR60 Lite CPU core
32
32
DMAC 5 channels
Bit search module
16-bit MAC
ROM 64 Kbytes/
Flash 128 Kbytes
Bus converter
RAM 2 Kbytes/
RAM 4 Kbytes
X0, X1
MD0 to MD2
INIT
Clock
control
32
16-bit ↔ 32-bit
Adapter
16
Interrupt
controller
INT0 to INT7
NMI
SIN0, SIN1
SOT0, SOT1
SCK0, SCK1
8 channels
external interrupt
1 channel
C-CAN
(Built-in MB91267NA/F267NA)
Port I/F
3 channels
16-bit reload timer
1 channel
16-bit PWC timer
2 channels
UART
TX0
RX0
4 channels 16-bit/
8 channels 8-bit
PPG timer
PORT
TIN0 to TIN2
TOT1, TOT2
PWI0
PPG0 to PPG7
2 channels
U-TIMER
AVCC
20
ADTG1
AVRH1
AN0 to AN3
4 channels input
8/10-bit A/D converter-1
ADTG2
AVRH2
AN4 to AN10
7 channels input
8/10-bit A/D converter-2
Timing generator
Multi-function timer
16-bit free-run timer 3 channels
CKI
Input capture 4 channels
IC0 to IC3
Output compare 6 channels
RTO0 to RTO5
Waveform generator
DTTI
MB91265A Series
■ MEMORY SPACE
1. Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
• Direct Addressing Areas
The following address space areas are used as I/O areas.
These areas are called direct addressing areas, in which the address of an operand can be specified directly
during an instruction.
The size of directly addressable areas depends on the data size to be being accessed as follows.
→ byte data access
: 000H to 0FFH
→ half word data access : 000H to 1FFH
→ word data access
: 000H to 3FFH
2. Memory Map
MB91267A/267NA/F267A/F267NA
Single chip mode
0000 0000H
I/O
Direct
addressing area
I/O
Refer to ■ I/O MAP
0000 0400H
0001 0000H
Access
disallowed
0003 F000H
Internal RAM
4 Kbytes
0004 0000H
Access
disallowed
000E 0000H
Internal ROM
128 Kbytes
0010 0000H
Access
disallowed
FFFF FFFFH
21
MB91265A Series
■ MODE SETTINGS
The FR family uses mode pins (MD2 to MD0) and a mode data to set the operation mode.
• Mode Pins
The MD2 to MD0 pins specify how the mode vector fetch and reset vector fetch is performed.
Setting is prohibited other than that shown in the following table.
Mode Pins
Mode name
Reset vector
access area
0
Internal ROM mode vector
Internal
1
External ROM mode vector
External
MD2
MD1
MD0
0
0
0
0
Remarks
Not supported by this model.
• Mode data
Data written to the internal mode register (MODR) by a mode vector fetch is called mode data.
After an operation mode has been set in the mode register, the device operates in the operation mode.
The mode data is set by all reset source. User programs cannot set data to the mode register.
Details of mode data description
bit
31
30
29
28
27
26
25
24
0
0
0
0
0
1
1
1
Operation mode setting bits
Bit31 to bit24 are all reserved bits.
Be sure to set this bit to “00000111”.
Operation is not guaranteed when any value other than “00000111” is set.
Note : Mode data set in the mode vector must be placed as byte data at 0x000FFFF8H.
Use the highest byte from bit31 to bit24 for placement as the FR family uses the big endian for byte
endian.
bit 31
Incorrect
16 15
87
0
XXXXXXXX
XXXXXXXX
XXXXXXXX
Mode Data
0x000FFFF8H
Mode Data
XXXXXXXX
XXXXXXXX
XXXXXXXX
Correct
0x000FFFFCH
22
24 23
0x000FFFF8H
Reset Vector
MB91265A Series
■ I/O MAP
[How to read the table]
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B PDR3 [R/W] B
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
Block
T-unit
Port data register
Read/write attribute Access unit
(B : byte, H : half word, W : word)
Initial value of register after reset
Register name (column 1 of the register is at address 4n, column 2 is
at address 4n + 1...)
Leftmost register address (For word-length access, column 1 of the
register becomes the MSB of the data.)
Note : Initial values of register bits are represented as follows :
“ 1 ” : Initial Value “ 1 ”
“ 0 ” : Initial Value “ 0 ”
“ X ” : Initial Value “ undefined”
“ - ” : No physical register at this location
Access is barred with an undefined data access attribute.
23
MB91265A Series
Address
Register
+0
+1
+2
+3
000000H
PDR0 [R/W] B, H, W
XXXXXXXX
PDR1 [R/W] B, H, W
XXXXXXXX
PDR2 [R/W] B, H, W
XXXXXXXX
PDR3 [R/W] B, H, W
XXXXXXXX
000004H
PDR4 [R/W] B, H, W
-XXXXXXX
PDR5 [R/W] B, H, W
XXXXXXXX
000008H,
00000CH
000010H
⎯
Port data
register
⎯
PDRG [R/W] B, H, W
------X-
Block
⎯
000014H
to
00003CH
⎯
Reserved
000040H
EIRR0 [R/W] B, H, W
00000000
ENIR0 [R/W] B, H, W
00000000
ELVR0 [R/W] B, H, W
00000000 00000000
External interrupt
(INT0 to INT7)
000044H
DICR [R/W] B, H, W
-------0
HRCL [R/W, R] B, H, W
0--11111
⎯
Delay interrupt/
Hold request
TMRLR0 [W] H, W
XXXXXXXX XXXXXXXX
TMR0 [R] H, W
XXXXXXXX XXXXXXXX
00004CH
⎯
TMCSR0 [R/W, R] B, H, W
---00000 00000000
000050H
TMRLR1 [W] H, W
XXXXXXXX XXXXXXXX
TMR1 [R] H, W
XXXXXXXX XXXXXXXX
000054H
⎯
TMCSR1 [R/W, R] B, H, W
---00000 00000000
000058H
TMRLR2 [W] H, W
XXXXXXXX XXXXXXXX
TMR2 [R] H, W
XXXXXXXX XXXXXXXX
00005CH
⎯
TMCSR2 [R/W, R] B, H, W
---00000 00000000
000048H
000060H
000064H
000068H
00006CH
SSR0 [R/W, R] B, H, W
00001000
SIDR0 [R]/SODR0[W]
B, H, W
XXXXXXXX
UTIM0 [R] H / UTIMR0 [W] H
00000000 00000000
SSR1 [R/W, R] B, H, W
00001000
SIDR1 [R]/SODR1[W]
B, H, W
XXXXXXXX
UTIM1 [R] H / UTIMR1 [W] H
00000000 00000000
Reload
timer 1
Reload
timer 2
SCR0 [R/W] B, H, W
00000100
SMR0 [R/W, W]
B, H, W
00--0-0-
UART0
DRCL0 [W] B
--------
UTIMC0 [R/W] B
0--00001
U-TIMER 0
SCR1 [R/W] B, H, W SMR1 [R/W] B, H, W
00000100
00--0-0DRCL1 [W] B
--------
UTIMC1 [R/W] B
0--00001
000070H
to
00007CH
⎯
000080H
ADCH1 [R/W] B, H, W ADMD1 [R/W] B, H, W ADCD11 [R] B, H, W ADCD10 [R] B, H, W
XXXX0XX0
00001111
XXXXXXXX
XXXXXXXX
000084H
ADCS1 [R/W, W] B, H,
W
00000X00
⎯
Reload
timer 0
UART1
U-TIMER 1
Reserved
AICR1 [R/W] B, H, W
----0000
⎯
A/D
converter 1/
AICR1
(Continued)
24
MB91265A Series
Address
Register
+0
+1
+2
+3
000088H
ADCH2 [R/W] B, H, W
XXXX0XX0
ADMD2 [R/W] B, H, W
00001111
ADCD21 [R] B, H, W
XXXXXXXX
ADCD20 [R] B, H, W
XXXXXXXX
00008CH
ADCS2 [R/W, W] B, H, W
00000X00
⎯
AICR2 [R/W] B, H, W
-0000000
⎯
000090H
OCCPBH0, OCCPBL0[W] /
OCCPH0, OCCPL0[R] H, W
00000000 00000000
OCCPBH1, OCCPBL1[W] /
OCCPH1, OCCPL1 [R] H, W
00000000 00000000
000094H
OCCPBH2, OCCPBL2[W] /
OCCPH2, OCCPL2 [R] H, W
00000000 00000000
OCCPBH3, OCCPBL3[W] /
OCCPH3, OCCPL3 [R] H, W
00000000 00000000
000098H
OCCPBH4, OCCPBL4[W] /
OCCPH4, OCCPL4 [R] H, W
00000000 00000000
OCCPBH5, OCCPBL5[W] /
OCCPH5, OCCPL5 [R] H, W
00000000 00000000
00009CH
OCSH1 [R/W] B, H, W
X1100000
OCSL0 [R/W] B, H, W
00001100
0000A0H
OCSH5 [R/W] B, H, W
X1100000
OCSL4 [R/W] B, H, W OCMOD [R/W] B, H, W
00001100
XX000000
0000A4H
0000A8H
CPCLRBH0, CPCLRBL0[W]/
CPCLRH0, CPCLRL0[R] H, W
11111111 11111111
TCCSH0 [R/W] B, H, W
00000000
OCSH3 [R/W] B, H, W
X1100000
⎯
ADTRGC [R/W] B, H, W
XXXX0000
IPCPH0, IPCPL0 [R] H, W
XXXXXXXX XXXXXXXX
IPCPH1, IPCPL1 [R] H, W
XXXXXXXX XXXXXXXX
0000B0H
IPCPH2, IPCPL2 [R] H, W
XXXXXXXX XXXXXXXX
IPCPH3, IPCPL3 [R] H, W
XXXXXXXX XXXXXXXX
PICSH01 [W] B, H, W
00000000
PICSL01 [R/W] B, H, W
00000000
ICSH23 [R] B, H, W
XXXXXX00
TMRRH0, TMRRL0 [R/W] H, W
XXXXXXXX XXXXXXXX
TMRRH1, TMRRL1 [R/W] H, W
XXXXXXXX XXXXXXXX
0000C0H
TMRRH2, TMRRL2 [R/W] H, W
XXXXXXXX XXXXXXXX
⎯
0000C4H
DTCR0 [R/W] B, H, W
00000000
DTCR1 [R/W] B, H, W
00000000
DTCR2 [R/W] B, H, W
00000000
⎯
0000C8H
⎯
SIGCR1 [R/W] B, H, W
00000000
⎯
SIGCR2 [R/W] B, H, W
XXXXXXX1
⎯
0000D0H
ADCOMP2 [R/W] H, W
00000000 00000000
0000D4H
to
0000DCH
16-bit
input
capture
Reserved
0000BCH
0000CCH
16-bit
free-run
timer 0
ICSL23 [R/W]B, H, W
00000000
⎯
0000B8H
16-bit
output
compare
⎯
0000ACH
0000B4H
A/D
converter 2/
AICR2
OCSL2 [R/W] B, H, W
00001100
TCDTH0, TCDTL0 [R/W] H, W
00000000 00000000
TCCSL0 [R/W] B, H, W
01000000
Block
Waveform
generator
ADCOMP1 [R/W] H, W
00000000 00000000
ADCOMPC2 [R/W]
B, H, W
XX0000XX
⎯
ADCOMPC1 [R/W]
B, H, W
XXXXX00X
A/D COMP
Reserved
(Continued)
25
MB91265A Series
Address
0000E0H
Register
+0
+1
PWCSR0 [R/W, R] B, H, W
00000000 00000000
+3
16-bit PWC
timer
PDIVR0 [R/W] B, H, W
XXXXX000
⎯
0000ECH
to
0000FCH
⎯
⎯
Reserved
000100H
PRLH0 [R/W] B, H, W
XXXXXXXX
PRLL0 [R/W] B, H, W
XXXXXXXX
PRLH1 [R/W] B, H, W
XXXXXXXX
PRLL1 [R/W] B, H, W
XXXXXXXX
000104H
PRLH2 [R/W] B, H, W
XXXXXXXX
PRLL2 [R/W] B, H, W
XXXXXXXX
PRLH3 [R/W] B, H, W
XXXXXXXX
PRLL3 [R/W] B, H, W
XXXXXXXX
000108H
PPGC0 [R/W] B, H, W PPGC1 [R/W] B, H, W PPGC2 [R/W] B, H, W PPGC3 [R/W] B, H, W
00000000
00000000
00000000
00000000
00010CH
PRLH4 [R/W] B, H, W
XXXXXXXX
PRLL4 [R/W] B, H, W
XXXXXXXX
PRLH5 [R/W] B, H, W
XXXXXXXX
PRLL5 [R/W] B, H, W
XXXXXXXX
000110H
PRLH6 [R/W] B, H, W
XXXXXXXX
PRLL6 [R/W] B, H, W
XXXXXXXX
PRLH7 [R/W] B, H, W
XXXXXXXX
PRLL7 [R/W] B, H, W
XXXXXXXX
000114H
PPGC4 [R/W] B, H, W PPGC5 [R/W] B, H, W PPGC6 [R/W] B, H, W PPGC7 [R/W] B, H, W
00000000
00000000
00000000
00000000
000118H
to
00012CH
⎯
000130H
TRG [R/W] B, H, W
-------- 00000000
000134H
REVC [R/W] B, H, W
-------- 00000000
000138H
to
000140H
Block
PWCR0 [R] H, W
00000000 00000000
⎯
0000E4H
0000E8H
+2
8/16-bit
PPG timer
0 to 7
Reserved
⎯
GATEC [R/W] B, H, W
XXXXXX00
⎯
⎯
8/16-bit
PPG timer
0 to 7
Reserved
000144H
TTCR0 [R/W] B, H, W
00000000
TSTPR0 [R] B, H, W
00000000
000148H
COMP0 [R/W] B, H, W COMP2 [R/W] B, H, W COMP4 [R/W] B, H, W COMP6 [R/W] B, H, W
00000000
00000000
00000000
00000000
00014CH,
000150H
⎯
⎯
000154H
CPCLRBH1, CPCLRBL1 [W] /
CPCLRH1, CPCLRL1 [R] H, W
11111111 11111111
TCDTH1, TCDTL1 [R/W] H, W
00000000 00000000
000158H
TCCSH1 [R/W] B, H,
TCCSL1 [R/W] B, H, W
W
01000000
00000000
⎯
Timing
generator
16-bit
free-run
timer 1
(Continued)
26
MB91265A Series
Address
00015CH
000160H
Register
+0
+1
CPCLRBH2, CPCLRBL2 [W] /
CPCLRH2, CPCLRL2 [R] H, W
11111111 11111111
TCCSH2 [R/W] B, H, W
00000000
⎯
⎯
FSR2 [R/W] B, H, W
00000000
⎯
00016CH
to
0001A4H
0001A8H
+3
TCDTH2, TCDTL2 [R/W] H, W
00000000 00000000
TCCSL2 [R/W] B, H, W
01000000
000164H
000168H
+2
16-bit
free-run
timer 2
Reserved
FSR1 [R/W] B, H, W
----0000
⎯
CANPRE [R, R/W] B, H, W
00000000
Block
FSR0 [R/W] B, H, W
00000000
FRT
selector
Reserved
⎯
C-CAN*1
prescaler
0001ACH
to
0001FCH
⎯
000200H
DMACA0 [R/W] B, H, W *2
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W] B, H, W*2
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W] B, H, W *2
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W] B, H, W *2
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W] B, H, W *2
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to
00023CH
⎯
Reserved
000240H
DMACR [R/W] B
0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX
DMAC
000244H
to
000398H
⎯
Reserved
Reserved
DMAC
(Continued)
27
MB91265A Series
Address
Register
+0
+1
+3
DSP-PC [R/W]
XXXXXXXX
DSP-CSR [R/W, R, W]
00000000
DSP-LY [R/W]
XXXXXXXX XXXXXXXX
0003A4H
DSP-OT0 [R]
XXXXXXXX XXXXXXXX
DSP-OT1 [R]
XXXXXXXX XXXXXXXX
0003A8H
DSP-OT2 [R]
XXXXXXXX XXXXXXXX
DSP-OT3 [R]
XXXXXXXX XXXXXXXX
0003B0H
DSP-OT4 [R]
XXXXXXXX XXXXXXXX
DSP-OT5 [R]
XXXXXXXX XXXXXXXX
0003B4H
DSP-OT6[R]
XXXXXXXX XXXXXXXX
DSP-OT7 [R]
XXXXXXXX XXXXXXXX
0003B8H
⎯
0003BCH
to
0003ECH
⎯
0003F0H
BSD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H
DDR0 [R/W] B, H, W
00000000
DDR1 [R/W] B, H, W
00000000
000404H
DDR4 [R/W] B, H, W
-0000000
DDR5 [R/W] B, H, W
00000000
000408H,
00040CH
DDR2 [R/W] B, H, W
00000000
Bit search
module
DDR3 [R/W] B, H, W
00000000
⎯
DDRG [R/W] B, H, W
------0-
Data
direction
register
⎯
⎯
PFR0 [R/W] B, H, W
00------
PFR1 [R/W] B, H, W
0-0-00-0
000424H
to
00042CH
000430H
Reserved
⎯
000414H
to
00041CH
000420H
16-bit MAC
⎯
0003ACH
000410H
Block
⎯
00039CH
0003A0H
+2
Reserved
⎯
Port
function
register
⎯
⎯
PTFR0 [R/W] B, H, W
00000000
(Continued)
28
MB91265A Series
Address
Register
+0
+1
+2
+3
000434H
to
00043CH
⎯
000440H
ICR00 [R/W, R] B, H, W ICR01 [R/W, R] B, H, W ICR02 [R/W, R] B, H, W ICR03 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000444H
ICR04 [R/W, R] B, H, W ICR05 [R/W, R] B, H, W ICR06 [R/W, R] B, H, W ICR07 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000448H
ICR08 [R/W, R] B, H, W ICR09 [R/W, R] B, H, W ICR10 [R/W, R] B, H, W ICR11 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
00044CH
ICR12 [R/W, R] B, H, W ICR13 [R/W, R] B, H, W ICR14 [R/W, R] B, H, W ICR15 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000450H
ICR16 [R/W, R] B, H, W ICR17 [R/W, R] B, H, W ICR18 [R/W, R] B, H, W ICR19 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000454H
ICR20 [R/W, R] B, H, W ICR21 [R/W, R] B, H, W ICR22 [R/W, R] B, H, W ICR23 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000458H
ICR24 [R/W, R] B, H, W ICR25 [R/W, R] B, H, W ICR26 [R/W, R] B, H, W ICR27 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
00045CH
ICR28 [R/W, R] B, H, W ICR29 [R/W, R] B, H, W ICR30 [R/W, R] B, H, W ICR31 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000460H
ICR32 [R/W, R] B, H, W ICR33 [R/W, R] B, H, W ICR34 [R/W, R] B, H, W ICR35 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000464H
ICR36 [R/W, R] B, H, W ICR37 [R/W, R] B, H, W ICR38 [R/W, R] B, H, W ICR39 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000468H
ICR40 [R/W, R] B, H, W ICR41 [R/W, R] B, H, W ICR42 [R/W, R] B, H, W ICR43 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
00046CH
ICR44 [R/W, R] B, H, W ICR45 [R/W, R] B, H, W ICR46 [R/W, R] B, H, W ICR47 [R/W, R] B, H, W
----1111
----1111
----1111
----1111
000470H
to
00047CH
⎯
Reserved
RSRR [R/W] B, H, W
10000000
STCR [R/W] B, H, W
00110011
TBCR [R/W] B, H, W
00XXXX00
CTBR [W] B, H, W
XXXXXXXX
000484H
CLKR [R/W] B, H, W
00000000
WPR [W] B, H, W
XXXXXXXX
DIVR0 [R/W] B, H, W
00000011
DIVR1 [R/W] B, H, W
00000000
⎯
000494H
to
0005FCH
⎯
Interrupt
control
unit
Reserved
000480H
000488H
to
000490H
Block
Clock
control
Reserved
(Continued)
29
MB91265A Series
Address
Register
+0
+1
+2
+3
000600H
PCR0 [R/W] B, H, W
00000000
PCR1 [R/W] B, H, W
00000000
PCR2 [R/W] B, H, W
00000000
PCR3 [R/W] B, H, W
00------
000604H
PCR4 [R/W] B, H, W
----0000
000608H,
00060CH
000610H
⎯
⎯
PCRG [R/W] B, H, W
------0-
Block
Pull-up
Control Unit
⎯
000614H
to
000FFCH
⎯
001000H
DMASA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
to
006FFCH
⎯
Reserved
Reserved
007000H
FLCR [R/W] B
01101000
⎯
007004H
FLWC [R/W] B
00000011
⎯
007008H
to
007010H
⎯
007014H
to
00BFFCH
⎯
DMAC
Flash
Reserved
(Continued)
30
MB91265A Series
Address
Register
+0
+1
+2
00C000H
to
00C07CH
X-RAM (coefficient RAM) [R/W]
64 × 16-bit
00C080H
to
00C0FCH
Y-RAM (variable RAM) [R/W]
64 × 16-bit
00C100H
to
00C2FCH
I-RAM (instruction RAM) [R/W]
256 × 16-bit
00C300H
to
00FFFCH
⎯
+3
16-bit MAC
Reserved
020000H
CTRLR0 [R, R/W]
00000000 00000001
STATR0 [R, R/W]
00000000 00000000
020004H
ERRCNT0 [R]
00000000 00000000
BTR0 [R, R/W]
00100011 00000001
020008H
INTR0 [R]
00000000 00000000
TESTR0 [R, R/W]
00000000 X0000000
02000CH
BRPER0 [R, R/W]
00000000 00000000
⎯
020010H
IF1CREQ0 [R, R/W]
00000000 00000000
IF1CMSK0 [R, R/W]
00000000 00000000
020014H
IF1MSK20 [R, R/W]
11111111 11111111
IF1MSK10 [R/W]
11111111 11111111
020018H
IF1ARB20 [R/W]
00000000 00000000
IF1ARB10 [R/W]
00000000 00000000
02001CH
IF1MCTR0 [R, R/W]
00000000 00000000
⎯
020020H
IF1DTA10 [R/W]
00000000 00000000
IF1DTA20 [R/W]
00000000 00000000
020024H
IF1DTB10 [R/W]
00000000 00000000
IF1DTB20 [R/W]
00000000 00000000
020030H
Block
C-CAN*1
Reserved (IF1 data mirror, little endian byte ordering)
020040H
IF2CREQ0 [R, R/W]
00000000 00000000
IF2CMSK0 [R, R/W]
00000000 00000000
020044H
IF2MSK20 [R, R/W]
11111111 11111111
IF2MSK10 [R/W]
11111111 11111111
020048H
IF2ARB20 [R/W]
00000000 00000000
IF2ARB10 [R/W]
00000000 00000000
02004CH
IF2MCTR0 [R, R/W]
00000000 00000000
⎯
020050H
IF2DTA10 [R/W]
00000000 00000000
IF2DTA20 [R/W]
00000000 00000000
(Continued)
31
MB91265A Series
(Continued)
Address
020054H
020060H
020080H
020084H
020090H
020094H
0200A0H
0200A4H
0200B0H
0200B4H
Register
+0
+1
IF2DTB10 [R/W]
00000000 00000000
+2
+3
Block
IF2DTB20 [R/W]
00000000 00000000
Reserved (IF2 data mirror, little endian byte ordering)
TREQR20 [R]
00000000 00000000
TREQR10 [R]
00000000 00000000
Reserved (>32..128 Message buffer)
NEWDT20 [R]
00000000 00000000
NEWDT10 [R]
00000000 00000000
C-CAN*1
Reserved (>32..128 Message buffer)
INTPND20 [R]
00000000 00000000
INTPND10 [R]
00000000 00000000
Reserved (>32..128 Message buffer)
MESVAL20 [R]
00000000 00000000
MESVAL10 [R]
00000000 00000000
Reserved (>32..128 Message buffer)
*1 : C-CAN is loaded in MB91267NA/F267NA.
*2 : The lower 16 bits (DTC15 to DTC0) of DMACA0 to DMACA4 cannot be accessed in bytes.
Notes : • The initial value of FLWC (7004H) is “00010011B” on EVA tool. Writing “00000011B” on the evaluation
model has no effect on its operation.
• Do not execute Read Modify Write instructions on registers having a write-only bit.
• Data is undefined in reserved or (-) area.
32
MB91265A Series
■ INTERRUPT VECTOR
Interrupt number
Interrupt source
HexaDecimal
decimal
Interrupt
level
Offset
TBR default
address
Reset
0
00
⎯
3FCH
000FFFFCH
Mode vector
1
01
⎯
3F8H
000FFFF8H
System reserved
2
02
⎯
3F4H
000FFFF4H
System reserved
3
03
⎯
3F0H
000FFFF0H
System reserved
4
04
⎯
3ECH
000FFFECH
System reserved
5
05
⎯
3E8H
000FFFE8H
System reserved
6
06
⎯
3E4H
000FFFE4H
Coprocessor absent trap
7
07
⎯
3E0H
000FFFE0H
Coprocessor error trap
8
08
⎯
3DCH
000FFFDCH
INTE instruction
9
09
⎯
3D8H
000FFFD8H
System reserved
10
0A
⎯
3D4H
000FFFD4H
System reserved
11
0B
⎯
3D0H
000FFFD0H
Step trace trap
12
0C
⎯
3CCH
000FFFCCH
NMI request (tool)
13
0D
⎯
3C8H
000FFFC8H
Undefined instruction exception
14
0E
⎯
3C4H
000FFFC4H
NMI request
15
0F
15 (FH) fixed
3C0H
000FFFC0H
External interrupt 0
16
10
ICR00
3BCH
000FFFBCH
External interrupt 1
17
11
ICR01
3B8H
000FFFB8H
External interrupt 2
18
12
ICR02
3B4H
000FFFB4H
External interrupt 3
19
13
ICR03
3B0H
000FFFB0H
External interrupt 4
20
14
ICR04
3ACH
000FFFACH
External interrupt 5
21
15
ICR05
3A8H
000FFFA8H
External interrupt 6/C-CAN wake up*
22
16
ICR06
3A4H
000FFFA4H
External interrupt 7
23
17
ICR07
3A0H
000FFFA0H
Reload timer 0
24
18
ICR08
39CH
000FFF9CH
Reload timer 1
25
19
ICR09
398H
000FFF98H
Reload timer 2
26
1A
ICR10
394H
000FFF94H
UART0(Reception completed)
27
1B
ICR11
390H
000FFF90H
UART0 (RX completed)
28
1C
ICR12
38CH
000FFF8CH
DTTI
29
1D
ICR13
388H
000FFF88H
DMAC0 (end, error)
30
1E
ICR14
384H
000FFF84H
DMAC1 (end, error)
31
1F
ICR15
380H
000FFF80H
DMAC2/DMAC3/DMAC4 (end, error)
32
20
ICR16
37CH
000FFF7CH
(Continued)
33
MB91265A Series
Interrupt number
Interrupt
level
Offset
TBR default
address
21
ICR17
378H
000FFF78H
34
22
ICR18
374H
000FFF74H
C-CAN0*
35
23
ICR19
370H
000FFF70H
System reserved
36
24
ICR20
36CH
000FFF6CH
16-bit MAC
37
25
ICR21
368H
000FFF68H
PPG0/PPG1
38
26
ICR22
364H
000FFF64H
PPG2/PPG3
39
27
ICR23
360H
000FFF60H
PPG4/PPG5/PPG6/PPG7
40
28
ICR24
35CH
000FFF5CH
System reserved
41
29
ICR25
358H
000FFF58H
Waveform0/1/2 (underflow)
42
2A
ICR26
354H
000FFF54H
Free-run timer 1 (compare clear)
43
2B
ICR27
350H
000FFF50H
Free-run timer 1 (zero detection)
44
2C
ICR28
34CH
000FFF4CH
Free-run timer 2 (compare clear)
45
2D
ICR29
348H
000FFF48H
Free-run timer 2 (zero detection)
46
2E
ICR30
344H
000FFF44H
Timebase timer overflow
47
2F
ICR31
340H
000FFF40H
Free-run timer 0 (compare clear)
48
30
ICR32
33CH
000FFF3CH
Free-run timer 0 (zero detection)
49
31
ICR33
338H
000FFF38H
System reserved
50
32
ICR34
334H
000FFF34H
A/D converter 1
51
33
ICR35
330H
000FFF30H
A/D converter 2
52
34
ICR36
32CH
000FFF2CH
PWC0 (measurement completed)
53
35
ICR37
328H
000FFF28H
System reserved
54
36
ICR38
324H
000FFF24H
PWC0 (overflow)
55
37
ICR39
320H
000FFF20H
System reserved
56
38
ICR40
31CH
000FFF1CH
ICU0 (capture)
57
39
ICR41
318H
000FFF18H
ICU1 (capture)
58
3A
ICR42
314H
000FFF14H
ICU2/3 (capture)
59
3B
ICR43
310H
000FFF10H
OCU0/1 (match)
60
3C
ICR44
30CH
000FFF0CH
OCU2/3 (match)
61
3D
ICR45
308H
000FFF08H
OCU4/5 (match)
62
3E
ICR46
304H
000FFF04H
Delay interrupt source bit
63
3F
ICR47
300H
000FFF00H
System reserved (Used by REALOS)
64
40
⎯
2FCH
000FFEFCH
System reserved (Used by REALOS)
65
41
⎯
2F8H
000FFEF8H
Interrupt source
Decimal
Hexadecimal
UART1(Reception completed)
33
UART1 (RX completed)
(Continued)
34
MB91265A Series
(Continued)
Interrupt number
Interrupt
level
Offset
TBR default
address
42
⎯
2F4H
000FFEF4H
67
43
⎯
2F0H
000FFEF0H
System reserved
68
44
⎯
2ECH
000FFEECH
System reserved
69
45
⎯
2E8H
000FFEE8H
System reserved
70
46
⎯
2E4H
000FFEE4H
System reserved
71
47
⎯
2E0H
000FFEE0H
System reserved
72
48
⎯
2DCH
000FFEDCH
System reserved
73
49
⎯
2D8H
000FFED8H
System reserved
74
4A
⎯
2D4H
000FFED4H
System reserved
75
4B
⎯
2D0H
000FFED0H
System reserved
76
4C
⎯
2CCH
000FFECCH
System reserved
77
4D
⎯
2C8H
000FFEC8H
System reserved
78
4E
⎯
2C4H
000FFEC4H
System reserved
79
4F
⎯
2C0H
000FFEC0H
Used by INT instruction
80
to
255
50
to
FF
⎯
2BCH
to
000H
000FFEBCH
to
000FFC00H
Interrupt source
Decimal
Hexadecimal
System reserved
66
System reserved
* : C-CAN interrupt is only loaded in MB91267NA/F267NA.
35
MB91265A Series
■ PIN STATUS IN EACH CPU STATE
Terms used as the status of pins mean as follows.
• Input enabled
Indicates that the input function can be used.
• Input 0 fixed
Indicates that the input level has been internally fixed to be 0 to prevent leakage when the input is released.
• Output Hi-Z
• Output is maintained.
Indicates the output in the output state existing immediately before this mode is established.
If the device enters this mode with an internal output peripheral operating or while serving as an output port,
the output is performed by the internal peripheral or the port output is maintained, respectively.
• State existing immediately before is maintained.
When the device serves for output or input immediately before entering this mode, the device maintains the
output or is ready for the input, respectively.
• List of pin status (single chip mode)
Pin no. Pin name
Function
3 to 10 P50 to P57
AN0 to AN7
11 to 13 P44 to P46 AN8 to AN10
14
NMI
NMI
18
P00
PPG1/INT4
19
P01
PPG2
20
P02
PPG3/INT5
At initializing
INIT = L*
1
INIT = H*
2
Output Hi-Z/ Output Hi-Z/
Input
Input
disabled
enabled
Input
enabled
Input
enabled
At Stop mode
At sleep
mode
Hi-Z = 0
Hi-Z = 1
Retention of
the immediately prior
state
Retention
of the
immediately
prior state
Output Hi-Z/
Input 0 fixed
Input
enabled
Input
enabled
Input
enabled
Retention
of the
immediately
prior state
Retention
of the
immediately
prior state
Output Hi-Z/
Input 0 fixed
Input enabled Input enabled Input enabled
21 to 23 P03 to P05 TIN0 to TIN2
24, 25
P06, P07
TOT1, TOT2
26
P10
SOT0
27
P11
SIN0
28
P12
SCK0
29
P13
SOT1
30
P14
SIN1
31
P15
SCK1
32
P16
PPG5/INT6/
RX0*3
Output Hi-Z/ Output Hi-Z/
Input
Input
disabled
enabled
Retention
of the
immediately
prior state
Retention
of the
immediately
prior state
Output Hi-Z/
Input 0 fixed
Input enabled Input enabled Input enabled
(Continued)
36
MB91265A Series
(Continued)
Pin no. Pin name
At initializing
Function
INIT = L*
INIT = H*
2
At Stop mode
At sleep
mode
Hi-Z = 0
Hi-Z = 1
Retention
of the
immediately
prior state
Retention
of the
immediately
prior state
Output Hi-Z/
Input 0 fixed
3
33
P17
PPG6/TX0*
34
P20
ADTG1/IC2
35
P21
ADTG2/IC3
36
P22
PWI0
37
P23
DTTI
38
P24
CKI
39
P25
IC0
40
P26
IC1
41
P27
General port
42
PG1
PPG0
49
P37
PPG4
50
P36
PPG7/INT7
52 to 57 P35 to P30
1
Output Hi-Z/ Output Hi-Z/
Input
Input
disabled
enabled
RTO5 to
RTO0
58 to 61 P40 to P43 INT0 to INT3
Input enabled Input enabled Input enabled
Retention
of the
immediately
prior state
Retention
of the
immediately
prior state
Output Hi-Z/
Input 0 fixed
Input enabled Input enabled Input enabled
*1 : INIT = L : Indicates the pin status with INIT remaining at the “L” level.
*2 : INIT = H : Indicates the pin status existing immediately after INIT transition from “L” to “H” level.
*3 : C-CAN terminal is loaded in MB91267NA/F267NA.
37
MB91265A Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.5
VSS + 6.0
V
AVCC
VSS − 0.5
VSS + 6.0
V
*2
AVRHn*6
VSS − 0.5
VSS + 6.0
V
*2
VI
VSS − 0.3
VCC + 0.3
V
VIA
VSS − 0.3
AVcc + 0.3
V
VO
VSS − 0.3
VCC + 0.3
V
IOL
⎯
10
mA
*3
“L” level average output current
IOLAV
⎯
8
mA
*4
“L” level total maximum output current
ΣIOL
⎯
60
mA
ΣIOLAV
⎯
30
mA
*5
IOH
⎯
− 10
mA
*3
“H” level average output current
IOHAV
⎯
−4
mA
*4
“H” level total maximum output current
ΣIOH
⎯
− 30
mA
ΣIOHAV
⎯
− 12
mA
Power consumption
PD
⎯
600
mW
Operating temperature
Ta
− 40
+ 105
°C
Tstg
− 55
+ 125
°C
Power supply voltage*1
Analog power supply voltage*
1
Analog reference voltage*1
Input voltage*1
Analog pin input voltage*1
Output voltage*
1
“L” level maximum output current
“L” level total average output current
“H” level maximum output current
“H” level total average output current
Storage temperature
*5
At single chip operating
*1 : The parameter is based on VSS = AVSS = 0 V.
*2 : Be careful not to exceed VCC + 0.3 V, for example, when the power is turned on.
Be careful not to let AVCC exceed VCC, for example, when the power is turned on.
*3 : The maximum output current is the peak value for a single pin.
*4 : The average output current is the average current for a single pin over a period of 100 ms.
*5 : The total average output current is the average current for all pins over a period of 100 ms.
*6 : AVRHn = AVRH1, AVRH2
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
38
MB91265A Series
2. Recommended Operating Conditions
(Vss = AVss = 0 V)
Parameter
Symbol
Value
Min
Max
Unit
Remarks
Power supply voltage
VCC
4.0
5.5
V
Analog power supply
voltage
AVCC
VSS + 4.0
VSS + 5.5
V
AVRH1
AVSS
AVCC
V
For A/D converter 1
AVRH2
AVSS
AVCC
V
For A/D converter 2
Ta
− 40
+ 105
°C
At single chip operating
Analog reference voltage
Operating temperature
At normal operating
Note : Upon power up, it takes approx. 100 µs for stabilization of internal power supply after the VCC power supply
is stabilized. Keep applying “L” to INIT pin signal during that period.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
39
MB91265A Series
3. DC Characteristics
(VCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Pin Name
Value
Conditions
Min
Typ
Max
Unit Remarks
"H" level input
voltage
VIHS
Hysteresis
input pin
⎯
Vcc × 0.8
⎯
Vcc + 0.3
V
"L" level input
voltage
VILS
Hysteresis
input pin
⎯
Vss − 0.3
⎯
Vss × 0.2
V
VOH
Other than
P30 to P35
VCC = 5.0 V,
IOH = 4.0 mA
Vcc − 0.5
⎯
⎯
V
VOH2
P30 to P35
VCC = 5.0 V,
IOH = 8.0 mA
Vcc − 0.7
⎯
⎯
V
VOL
Other than
P30 to P35
VCC = 5.0 V,
IOL = 4.0 mA
⎯
⎯
0.4
V
VOL2
P30 to P35
VCC = 5.0 V,
IOL = 12 mA
⎯
⎯
0.6
V
VCC = 5.0 V,
VSS < VI < VCC
−5
⎯
+5
µA
⎯
⎯
50
⎯
kΩ
"H" level output
voltage
"L" level output
voltage
Input leak
current
ILI
Pull-up
resistance
RPULL
Power supply
current
⎯
INIT,
Pull-up pin
ICC
VCC
VCC = 5.0 V, 33 MHz
⎯
90
100
mA
ICCS
VCC
VCC = 5.0 V, 33 MHz
⎯
60
80
mA At SLEEP
ICCH
VCC
VCC = 5.0 V,
Ta = + 25 °C
⎯
300
⎯
µA
CIN
Other than VCC,
VSS, AVCC, AVSS,
AVRH1, AVRH2
⎯
5
15
pF
Input
capacitance
⎯
At STOP
4. Flash Memory Write/Erase Characteristics
Parameter
Conditions
Sector erase time
(4 Kbytes sector)
Byte write time
Erase/write cycle
Flash memory data
retention time
Value
Unit
Remarks
Min
Typ
Max
Ta = + 25 °C,
Vcc = 5.0 V
⎯
0.2
0.5
s
Not including time for internal
writing before deletion.
Ta = + 25 °C,
Vcc = 5.0 V
⎯
32
3600
µs
Not including system-level
overhead time.
⎯
10000
⎯
⎯
cycle
20
⎯
⎯
year
Average
Ta = + 85 °C
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C) .
40
MB91265A Series
5. AC Characteristics
(1) Clock Timing Ratings
(VCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V)
Symbol
Pin
Name
Clock frequency
fC
X0
X1
Clock cycle time
tC
X0
X1
Input clock pulse
width
PWH
PWL
X0
Input clock
rising, falling time
tCF
tCR
X0
Internal operating
clock frequency
fCP
Parameter
Internal operating
clock cycle time
fCPP
Unit
Typ
Max
3.6*2
⎯
12
MHz
83.3
⎯
278*2
ns
⎯
100
⎯
⎯
ns
The standard of the
duty ratio is 40 % to 60
%.
⎯
⎯
⎯
5
ns
At external clock
⎯
33
⎯
33
When 4.125 MHz is 2.06*1
input as the X0
2.06*1
clock frequency and
30.3
×8 multiplication is
set for the PLL of
30.3
the oscillator circuit.
⎯
⎯
Remarks
Min
⎯
tCP
tCPP
Value
Conditions
For using the PLL
within the self-oscillation enabled range,
set the multiplier for
the internal clock not
to let the operating frequency exceed
33 MHz.
MHz CPU
MHz Peripheral
⎯
1
485*
ns
CPU
⎯
485*1
ns
Peripheral
*1 : The values assume a gear cycle of 1/16.
*2 : When the PLL is used, the lower-limit frequency of the input clock to the X0 and X1 pins determines depending
on the PLL multiplication.
At × 1 multiplication : more than 8 MHz
At × 2 to × 8 multiplication : more than 4 MHz
• Conditions for measuring the clock timing ratings
tC
0.8 VCC
X0,
X1
0.2 VCC
Output pin
C = 50 pF
PWL
PWH
tCF
tCR
41
MB91265A Series
• Operation Assurance Range
Power supply voltage
VCC (V)
5.5
4.0
0 0.25
33
fCP , fCPP
(MHz)
Internal clock
• Internal clock setting range
(MHz)
CPU (CLKB) :
Internal clock
33
Peripheral (CLKP) :
16.5
Oscillation input clock fC = 4.192 MHz
(PLL multiplied by 8)
4.125
8:8
4:4
1:1
CPU : Divided ratio for peripherals.
Notes : • Oscillation stabilization time of PLL > 600 µs
• The internal clock gear setting should be within the value shown in clock timing ratings table.
42
MB91265A Series
(2) Reset Input Ratings
(VCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V)
Parameter
INIT input time
(at power-on and STOP mode)
INIT input time
(other than the above)
Symbol
tINTL
Pin
Name
INIT
Value
Conditions
⎯
Unit
Min
Max
Oscillation time of
oscillator + tC × 10
⎯
ns
tC × 10
⎯
ns
Remarks
*
* : After the power is stable, L level is kept inputting to INIT pin for the duration of approximately 100 µs until the internal
power is stabilized.
tINTL
INIT
0.2 VCC
43
MB91265A Series
(3) UART Timing
(VCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Pin Name
Serial clock cycle time
tSCYC
SCK0, SCK1
SCK ↓ → SOT delay time
tSLOV
SCK0, SCK1,
SOT0, SOT1
Conditions
Internal shift
clock mode
Unit
Min
Max
8 tCYCP
⎯
ns
− 80
+ 80
ns
100
⎯
ns
Valid SIN → SCK ↑
tIVSH
SCK0, SCK1,
SIN0, SIN1
SCK ↑ → valid SIN hold time
tSHIX
SCK0, SCK1,
SIN0, SIN1
60
⎯
ns
Serial clock “H” pulse width
tSHSL
SCK0, SCK1
4 tCYCP
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK0, SCK1
4 tCYCP
⎯
ns
SCK ↓ → SOT delay time
tSLOV
SCK0, SCK1,
SOT0, SOT1
⎯
150
ns
Valid SIN → SCK ↑
tIVSH
SCK0, SCK1,
SIN0, SIN1
60
⎯
ns
SCK ↑ → valid SIN hold time
tSHIX
SCK0, SCK1,
SIN0, SIN1
60
⎯
ns
External shift
clock mode
Notes : • The above ratings are the values for clock synchronous mode.
• tCYCP indicates the peripheral clock cycle time.
44
Value
MB91265A Series
• Internal shift clock mode
tSCYC
SCK0, SCK1
VOH
VOL
VOL
tSLOV
VOH
VOL
SOT0, SOT1
tIVSH
tSHIX
VOH
VOL
SIN0, SIN1
VOH
VOL
• External shift clock mode
tSLSH
tSHSL
VOH
SCK0, SCK1
VOL
VOL
VOL
tSLOV
SOT0, SOT1
VOH
VOL
tIVSH
SIN0, SIN1
VOH
VOL
tSHIX
VOH
VOL
45
MB91265A Series
(4) Free-run Timer Clock, PWC Input, and Reload Timer Trigger Timing
(VCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Pin Name
Conditions
tTIWH
tTIWL
CKI, PWI0,
TIN0 to TIN2
⎯
Input pulse width
Value
Min
Max
4 tCYCP
⎯
Unit
ns
Note : tCYCP indicates the peripheral clock cycle time.
VOH
VOH
CKI, PWI0,
TIN0 to TIN2
VOL
VOL
tTIWL
tTIWH
(5) Trigger Input Timing
(VCC = 4.0 V to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Pin Name
Conditions
tIC
IC0 to IC3
tADTG
ADTG1,
ADTG2
Input capture
trigger input
A/D Converter activation trigger input
Value
Max
⎯
5 tCYCP
⎯
ns
⎯
5 tCYCP
⎯
ns
Note : tCYCP indicates the peripheral clock cycle time.
tADTG, tIC
IC0 to IC3
ADTG1, ADTG2
46
VOL
Unit
Min
VOL
MB91265A Series
6. Electrical Characteristics for the A/D Converter
(VCC = AVcc = 5.0 V, VSS = AVSS = 0 V)
Parameter
Resolution
Total error*
1
Linearity error*
1
Differential linearity
error*1
Symbol
Pin Name
⎯
Value
Unit
Min
Typ
Max
⎯
⎯
⎯
10
bit
⎯
⎯
−4
⎯
+4
LSB
⎯
⎯
− 3.5
⎯
+ 3.5
LSB
⎯
⎯
−3
⎯
+3
LSB
AVss +
0.5LSB
AVss +
4.5LSB
V
At AVRHn*4 = 5.0 V
Zero transition voltage*1
VOT
AN0 to AN10
AVss −
3.5LSB
Full transition voltage*1
VFST AN0 to AN10
AVRH −
5.5LSB
AVRH −
1.5LSB
AVRH +
2.5LSB
V
Conversion time
⎯
⎯
1.2*2
⎯
⎯
µs
Analog port
Input current
IAIN
AN0 to AN10
⎯
⎯
10
µA
Analog input voltage
VAIN
AN0 to AN10
AVss
⎯
AVRH
V
AVss
⎯
AVcc
V
⎯
2
⎯
⎯
⎯
100
⎯
1
⎯
⎯
⎯
100
µA
Reference voltage
⎯
Analog power supply
current
(analog + digital)
IA
AVRHn*
4
AVcc
IAH*3
mA Per 1 unit
µA
IRH*3
Analog input capacitance
⎯
⎯
⎯
10
⎯
pF
Inter-channel disparity
⎯
AN0 to AN10
⎯
⎯
4
LSB
AVRHn*4
Per 1 unit
Per 1 unit
mA AVRHn*4 = 5.0 V,
at AVSS = 0 V
Reference power supply
current
(between AVRH and
AVSS)
IR
Remarks
Per 1 unit
at STOP
*1 : Measured in the CPU sleep state
*2 : Vcc = AVcc = 5.0 V, machine clock at 33 MHz
*3 : The current when the CPU is in stop mode and the A/D converter is not operating (at Vcc = AVcc = AVRHn = 5.0 V)
*4: AVRHn = AVRH1, AVRH2
Note : The above does not guarantee the inter-unit accuracy.
Set the output impedance of the external circuit ≤ 2 kΩ.
47
MB91265A Series
Definition of A/D Converter Terms
• Resolution : Analog variation that is recognized by an A/D converter.
• Linearity error : Zero transition point (00 0000 0000 ←→ 00 0000 0001) and full-scale transition point.
Difference between the line connected (11 1111 1110 ←→ 11 1111 1111) and actual conversion characteristics.
• Differential linearity error : Deviation of input voltage, that is required for changing output code by 1 LSB, from
an ideal value.
• Total error : This error indicates the difference between actual and ideal values, including the zero transition
error/full-scale transition error/linearity error..
Total error
3FFH
Digital output
1.5 LSB'
Actual conversion
characteristics
3FEH
3FDH
{1 LSB' (N − 1) + 0.5 LSB'}
004H
VNT
(measurement value)
003H
Actual conversion
characteristics
002H
Ideal characteristics
001H
0.5 LSB'
AVSS
AVRH
Analog input
1LSB’
(Ideal value)
=
AVRH − AVSS
1024
[V] Total error of digital output N
=
VNT − {1 LSB’ × (N − 1) + 0.5 LSB’}
1 LSB’
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N + 1)H to NH.
VOT’ (Ideal value) = AVSS + 0.5LSB’ [V]
VFST’ (Ideal value) = AVRH − 1.5 LSB’ [V]
(Continued)
48
MB91265A Series
(Continued)
Linearity error
3FFH
Actual conversion
characteristics
3FEH
Actual conversion
characteristics
(N + 1)H
{1 LSB (N − 1) + VOT}
3FDH
Ideal
characteristics
VFST
(measurement
value)
Digital output
Digital output
Differential linearity error
004H
VNT
003H
(measurement value)
002H
Actual conversion
characteristics
Ideal characteristics
NH
(N − 1)H
VFST
(measurement
value)
VNT
(measurement value)
(N − 2)H
001H
Actual conversion
characteristics
VOT (measurement value)
AVSS
AVRH
AVSS
Analog input
AVRH
Analog input
Linearity error in digital output N =
Differential linearity error in digital output N =
1 LSB
=
VNT − { 1 LSB × (N − 1) + VOT }
1 LSB
V (N + 1) T − VNT
1 LSB
VFST − VOT
1022
−1
[LSB]
[LSB]
[V]
N : A/D converter digital output value
VOT : A voltage at which digital output transits from 000H to 001H.
VFST : A voltage at which digital output transits from 3FEH to 3FFH .
49
MB91265A Series
■ EXAMPLE CHARACTERISTICS
“L” Level Output Voltage vs.
“H” Level Output Voltage vs.
Power Supply Voltage
Power Supply Voltage
6
400
5
350
300
VOL (mV)
VOH (V)
4
3
2
250
200
150
1
100
0
4.0
50
4.5
5.0
5.5
0
4.0
VCC (V)
4.5
5.0
5.5
VCC (V)
Power Supply Current (at stop) vs.
Power Supply Voltage
Pull-up Resistor vs. Power Supply Voltage
100
80
90
70
80
70
ICCH (µA)
R (kΩ)
60
50
40
30
60
50
40
30
20
20
10
0
4.0
10
4.5
5.0
0
4.0
5.5
4.5
VCC (V)
A/D Conversion Block Per 1 Unit (33 MHz)
Analog Power Supply Current vs.
Power Supply Voltage
5.5
A/D Conversion Block Per 1 Unit (33 MHz)
Reference Power Supply Current vs.
Power Supply Voltage
2
1.0
1.5
0.8
IR (mA)
IA (mA)
5.0
VCC (V)
1
0.6
0.4
0.5
0.2
0
4.0
4.5
5.0
VCC (V)
50
5.5
0.0
4.0
4.5
5.0
VCC (V)
5.5
MB91265A Series
■ ORDERING INFORMATION
Part number
Package
Remarks
MB91267APMC
MB91267NAPMC
MB91F267APMC
64-pin plastic LQFP
(FPT-64P-M23)
MB91F267NAPMC
MB91V265ACR-ES
Package loaded C-CAN
Package loaded C-CAN
401-pin ceramic PGA
(PGA-401C-A02)
51
MB91265A Series
■ PACKAGE DIMENSION
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12.0 × 12.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LFQFP64-12×12-0.65
(FPT-64P-M23)
64-pin plastic LQFP
(FPT-64P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00±0.20(.551±.008)SQ
*12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.0057±.0022)
33
32
49
0.10(.004)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0.25(.010)
INDEX
0~8˚
17
64
1
0.65(.026)
C
"A"
16
0.32±0.05
(.013±.002)
0.13(.005)
0.10±0.10
(.004±.004)
(Stand off)
M
2003 FUJITSU LIMITED F64034S-c-1-1
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
52
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values
MB91265A Series
■ MAIN CHANGES IN THIS EDITION
Page
Section
Change Results
⎯
⎯
Deleted the MB91266A (MASK ROM Product)
Added the MB91267A and MB91267NA (MASK ROM Product)
53
MB91265A Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
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Fujitsu assumes no liability for any infringement of the intellectual
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The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
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satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
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Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
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over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
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registered trademarks of their respective owners.
Edited
Business Promotion Dept.
F0708
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