ds91F467CA-v0.13.pdf

FUJITSU SEMICONDUCTOR
MB91F467CA preliminary datasheet
MB91460 series
European MCU Design Centre (EMDC)
Fujitsu Microelectronics Europe GmbH
Pittlerstrasse 47
63225 Langen, Germany
Version 0.13
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Revision History
Version
0.01
0.02
0.03
0.04
0.05
0.06
Date
2006-06-02
2006-06-07
2006-07-28
2006-08-08
2006-08-24
2006-09-05
Remark
Initial draft
Corrected EMPDSU group/channel data
Corrected D-Bus RAM and F-Bus RAM sizes in IO Map
Corrected IO Pins and their functions
IO Map reviewed and corrected, beautification
Correct: x04CC, I-RAM, D-RAM, I/D-RAM in IO-map
0.07
0.08
0.11
0.12
0.13
2006-11-13
2006-11-29
2007-02-23
2007-03-26
2007-03-26
Corrected formatting accoring to new datasheet style
Updated after Specification Review
corrected unified flash settings, NMIX pin type, section sequence
corrected the block diagram
corrected ALARM thresholds, added ADC comparision time
0.13
Latest revision
Fujitsu Microelectronics Europe GmbH
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MB91F467CA preliminary datasheet ver. 0.13
Table of contents
1
Overview........................................................................................................................ 5
1.1
2
Block Diagram .......................................................................................................... 5
Feature List ................................................................................................................... 6
2.1
Overview Table ........................................................................................................ 6
2.2
Core Functionality..................................................................................................... 7
2.2.1
Memory Map ...................................................................................................... 8
2.2.2
FR70 CPU Core................................................................................................. 9
2.2.3
Instruction Cache ............................................................................................... 9
2.2.4
Interrupt Controller ............................................................................................. 9
2.2.5
Internal Data RAM.............................................................................................10
2.2.6
Internal Program/Data RAM ..............................................................................10
2.2.7
External Bus Interface.......................................................................................10
2.2.8
DMA Controller .................................................................................................10
2.3
Peripheral Function .................................................................................................10
2.4
Embedded Program/Data Memory (Flash) ..............................................................16
2.4.1
Flash features ...................................................................................................16
2.4.2
CPU Mode ........................................................................................................17
2.4.2.1
Flash configuration in CPU mode .......................................................................................... 17
2.4.2.2
Flash access timing settings in CPU mode............................................................................ 18
2.4.2.3
Address mapping from CPU to parallel programming mode.................................................. 19
2.4.3
2.4.3.1
Flash configuration in parallel flash programming mode........................................................ 20
2.4.3.2
Pin connections in parallel programming mode ..................................................................... 21
2.4.4
3
4
Parallel flash programming mode......................................................................20
Flash Security ...................................................................................................22
2.4.4.1
Vector addresses................................................................................................................... 22
2.4.4.2
Security Vector FSV1 ............................................................................................................ 22
2.4.4.3
Security Vector FSV2 ............................................................................................................ 25
2.4.4.4
Register description for Flash Security .................................................................................. 26
Package and Pin Assignment .....................................................................................27
3.1
Package ..................................................................................................................27
3.2
I/O Pins and their functions......................................................................................28
3.3
I/O Pin Types...........................................................................................................31
Recommended Settings ..............................................................................................32
4.1
PLL and Clockgear settings.....................................................................................32
Fujitsu Microelectronics Europe GmbH
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MB91F467CA preliminary datasheet ver. 0.13
4.2
Flash interface settings............................................................................................33
4.3
Clock Modulator settings .........................................................................................34
5
Interrupt Vector Table..................................................................................................39
6
I/O Map..........................................................................................................................47
7
Electrical Characteristics ............................................................................................78
7.1
Absolute Maximum Ratings .....................................................................................78
7.2
Operating Conditions...............................................................................................79
7.3
Converter Characteristics ........................................................................................81
Fujitsu Microelectronics Europe GmbH
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MB91F467CA preliminary datasheet ver. 0.13
1 Overview
The MB91F467CA is a device of the M91460 family. The corresponding evaluation device is
the MB91V460.
1.1 Block Diagram
4 MHz
Clock modulation
Clock Control
Clock Supervisor
Power Control
Subclock 32 kHz
32 kHz
FRT x 8 (5 ext)
Int. Control
EDSU/MPU
4 ch
FR70
FR70CPU
CPU
0.18 +m
0.18 +m
100 MHz
100 MHz
Watchdog
Bit Search
RC Osc. 100 kHz
RAM 32KByte
INSTR
Pre-fetch 8 KByte Cache
DATA
Core: 1.8 V
IO: 5.0 V
ICU x 8
OCU x 4
PPG x 12
I2 C x 3
R-Timer x 8
LIN-USART x 5
PFM
CAN x 3
32 msg
RTC
Ext. Int x 15
+ NMI
U/DCnt x 3
GPIO
RAM 32KByte
Sound
10-bit ADC x 30
BootROM
4 KByte
Alarm x 1
FLASH
1 MByte
Harvard Bus
Converter
DMA (5 ch)
QFP144
SMC x 6
4 x LIN-USART
with FIFO
V1.3 32bit_blockdia
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MB91F467CA preliminary datasheet ver. 0.13
2 Feature List
2.1 Overview Table
Feature
MB91V460
MB91F467CA
MB91F467DA
Max. Core frequency
(CLKB)
80 MHz
100 MHz
96 MHz
Max. Resource
frequency (CLKP)
40 MHz
50 MHz
48 MHz
Max. Ext-Bus
frequency (CLKT)
40 MHz
-
48 MHz
Max. CAN frequency
(CLKCAN)
20 MHz
50 MHz
48 MHz
-
-
-
Watchdog
yes
yes
yes
Bit Search
yes
yes
yes
Reset Input
yes
yes
yes
Clock Modulator
(yes)
yes
yes
DMA
5 ch
5 ch
5 ch
32 BP
(16 MPU ch)
16 BP
(8 MPU ch)
16 ch
(8 MPU ch)
Flash
external
1 MB + 64 KB
1 MB + 64 KB
Satellite Flash
external
-
-
n.a.
yes
yes
Data RAM
64 kB
32 kB
32 kB
GP RAM
64 kB
32 kB
32 kB
Direct mapped cache
16kB
8 kB
8 kB
Boot-ROM
4 kB
4 kB
4 kB
RTC
1 ch
1 ch
1 ch
Free Running Timer
8 ch
8 ch
8 ch
ICU
8 ch
8 ch
8 ch
OCU
8 ch
4 ch
4 ch
Max. FlexRay
frequency (SCLK)
EDSU/MPU
Flash Protection
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Feature
MB91F467CA preliminary datasheet ver. 0.13
MB91V460
MB91F467CA
MB91F467DA
Reload Timer
8 ch
8 ch
8 ch
PPG
16 ch
12 ch
12 ch
PFM
1 ch
1 ch
1 ch
Sound Generator
1 ch
1 ch
1 ch
UpDown Counter
4 ch
3 ch
3 ch
C_CAN
6 ch
(128 msg buffer)
3 ch
(32 msg buffer)
3 ch
(32 msg buffer)
FlexRay
-
-
-
16 ch (4 ch FIFO)
5 ch (4 ch FIFO)
5 ch (4 ch FIFO)
4 ch
3 ch
3 ch
32-bit address /
32-bit data
-
26-bit address /
32-bit data
External Interrupts
16 ch
15 ch
14 ch
NMI
1 ch
1 ch
-
SMC (quad option)
6 ch
6 ch
6 ch
1 ch 40x4
-
-
ADC (10-bit)
32 ch
30 ch
24 ch
Alarm Comparator
2 ch
1 ch
1 ch
Low voltage detection
yes
yes
yes
Clock Supervisor
yes
yes
yes
Clock Monitor Output
yes
yes
yes
General Purpose IO,
non-multiplexed
-
1 port with 8 pins
-
BGA 660
QFP-144
QFP-208
LIN-USART
I2C
FR external bus
LCD
Package
2.2 Core Functionality
Fujitsu Microelectronics Europe GmbH
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MB91F467CA preliminary datasheet ver. 0.13
2.2.1 Memory Map
0000:0000h0000:00FFh
I/O Byte Data
0000:0000h0000:00FFh
I/O Byte Data
0000:0100h0000:01FFh
I/O Halfword Data
0000:0100h0000:01FFh
I/O Halfword Data
0000:0200h0000:03FFh
I/O Word Data
0000:0200h0000:03FFh
I/O Word Data
0000:0400h0000:0FFFh
I/O
0000:0400h0000:0FFFh
I/O
0000:1000h0000:10FFh
DMA
0000:1000h0000:10FFh
DMA
0000:2000h0000:5FFFh
Flash Memory I-Cache (8 kB) or
Instruction RAM (8 kB)
available, but no
memory mapped
access
0000:2000h0000:5FFFh
Flash Memory I-Cache (16 kB) or
Instruction RAM (16 kB)
0000:7000h0000:70FFh
Flash Memory Control
Flash Memory I-Cache Control
0000:7000h0000:70FFh
Flash Memory Control
Flash Memory I-Cache Control
0000:8000h0000:BFFFh
Boot ROM (4 kB)
0000:8000h0000:BFFFh
Boot ROM (4 kB)
0000:C000h0000:CFFFh
CAN
0000:C000h0000:CFFFh
CAN
0001:0000h0001:FFFFh
External Bus I-Cache (4 kB) or
Instruction RAM (4 kB)
0001:0000h0001:FFFFh
External Bus I-Cache (4 kB) or
Instruction RAM (4 kB)
0002:0000h0002:FFFFh
Data RAM (64 kB)
0002:0000h0002:FFFFh
Data RAM (32 kB)
0003:0000h0003:FFFFh
Instruction/Data RAM (64 kB)
0003:0000h0003:FFFFh
Instruction/Data RAM (32 kB)
0004:0000h0005:FFFFh
ROMS00
(128 kB)
0004:0000h0005:FFFFh
0006:0000h0007:FFFFh
ROMS01
(128 kB)
0006:0000h0007:FFFFh
0008:0000h0009:FFFFh
ROMS02
(128 kB)
0008:0000h0009:FFFFh
Flash Memory Area
(1024 kB + 64 kB)
000A:0000h000B:FFFFh
ROMS03
(128 kB)
000A:0000h000B:FFFFh
or
000C:0000h000D:FFFFh
ROMS04
(128 kB)
000C:0000h000D:FFFFh
000E:0000h000F:FFFFh
ROMS05
(128 kB)
000E:0000h000F:FFFFh
ROMS06
(256 kB)
0010:0000h0013:FFFFh
ROMS07
(256 kB)
0014:0000h0017:FFFFh
ROMS08
(256 kB)
0018:0000h001B:FFFFh
ROMS09
(256 kB)
001C:0000h001F:FFFFh
0020:0000h0027:FFFFh
ROMS10
(512 kB)
0020:0000h0027:FFFFh
0028:0000h002F:FFFFh
ROMS11
(512 kB)
0028:0000h002F:FFFFh
0030:0000h0037:FFFFh
ROMS12
(512 kB)
0030:0000h0037:FFFFh
0038:0000h003F:FFFFh
ROMS13
(512 kB)
0038:0000h003F:FFFFh
0040:0000h0047:FFFFh
ROMS14
(512 kB)
0040:0000h0047:FFFFh
0048:0000h004F:FFFFh
ROMS15
(512 kB)
0048:0000h004F:FFFFh
0010:0000h0013:FFFFh
0014:0000h0017:FFFFh
0018:0000h001B:FFFFh
001C:0000h001F:FFFFh
0050:0000hFFFF:FFFFh
Legend
Emulation SRAM Area
(max 4.864 kB)
or
External Bus Area
depending on ROMA/ROMS
setting
External Bus Area
0050:0000hFFFF:FFFFh
External Bus Area
depending on ROMA
setting
External Bus Area
ROMS0-7 setting fixed to internal area
MB91F467CA
ROMS8-15 setting fixed to external area
MB91V460
External Bus Area
Memory available in this area
Memory not available in this area
Note: MB91F467CA does not have an external bus interface.
Fujitsu Microelectronics Europe GmbH
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MB91F467CA preliminary datasheet ver. 0.13
2.2.2 FR70 CPU Core
• 32-bit RISC, load/store architecture, pipeline 5 stages
• Maximum operating frequency: Core clock = 100 MHz
(Source oscillation= 4 MHz, multiplied by 25 (PLL clock multiplier method))
• General-purpose registers: 16 x 32 bits
• 16-bit fixed-length instruction (Base instruction)
• 32-bit linear address space: 4 Gbytes
• Instructions suitable for embedded application
•
Transfer command between memories
•
Bit-processing instruction
•
Barrel-shift instructions
• Instructions supporting C-language
• Function's enter command /exit command
• Multi-load/store command of register contents
• Assembler statement is also easily available
Register's interlock function
• Multiplier's embedded application/command level support
•
Signed 32-bit multiplication: 5 cycles
•
Signed 16-bit multiplication: 3 cycles
• Interrupt (PC/PS are saved): 6 cycles (16 priority level)
• Harvard architecture enables simultaneous execution of program access and data access
• Memory protection function
• Embedded debug support
• Commands compatible with FR family
2.2.3 Instruction Cache
• Direct mapped I-cache
•
8 kByte integrated
•
Lock function enabling programs to be resident
2.2.4 Interrupt Controller
• A total of 15 external interrupt lines ( 7 normal interrupt pins, 8 interrupt pins shared (with
peripheral inputs for Wake Up from STOP mode, e.g. CAN RX)
• Non maskable interrupt (NMI) pin
• Interrupts from internal peripherals (128 interrupt vectors)
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MB91F467CA preliminary datasheet ver. 0.13
• Priority levels programmable for normal interrupt lines excluding the nonmaskable one (16
levels)
• Capable of using the normal interrupt and nonmaskable interrupt pins for Wake Up from
STOP mode
2.2.5 Internal Data RAM
• 32 kBytes integrated
• Zero wait state for read/write access
2.2.6 Internal Program/Data RAM
• 32 kBytes integrated
• Zero wait state for read/write access of instructions
• One wait state for read/write access of data
2.2.7 External Bus Interface
• This device does not have an external bus interface.
2.2.8 DMA Controller
• Four transfer modes supported: single/block, burst, continuous transfer
• 5 channels
• 3 types of transfer sources (external pins/internal peripherals/and software)
• Up to 128 selectable internal transfer sources
• Addressing mode: Specifying up to 32-bit addresses (Increment/decrement/fixed)
• Transfer mode (Demand transfer/burst transfer/step transfer/block transfer)
• Transferred data size selectable from among 8, 16, and 32 bits
2.3 Peripheral Function
• General-purpose port: All functional pins can be used as general-purpose ports, if the
corresponding function is not needed.
•
2
N channel open drain port out of above: 6 (for I C)
• A/D converter : 30 channels (1 unit)
•
Series-parallel type
•
Resolution: 10 bits
•
Minimum conversion time: 3 us
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MB91F467CA preliminary datasheet ver. 0.13
•
Single conversion mode
•
Continuous conversion mode
•
Stop conversion mode
•
Activation by software or external trigger can be selected
•
Reload timer 7 and A/D Converter co-operate
• Alarm comparator : 1 channel
•
Monitors an external voltage and generates an interrupt in case of a voltage lower or
higher than the defined thresholds
•
Status is readable, interrupts can be masked separately
• External interrupt input : 15 channels
•
Can be programmed to be edge sensitive or level sensitive
•
Interrupt mask and request pending bits per channel
•
3 channels combined with CAN RX for wakeup
• Bit search module (using REALOS)
•
Function to search the first bit position of “1”, “0”, “Changed” from MSB (most significant
bit) within 1 word
• Up/down counter : 16 bits x 2 channels (8 bits x 3 channels)
•
Timer mode, up/down count mode, phase difference mode (x2, x4)
•
Includes clock prescaler (fRES/2 , fRES/2 )
1
3
1
3
• Reload timer : 16 bits x 8 channels
•
16-bit reload counter
•
Includes clock prescaler (fRES/2 , fRES/2 , fRES/2 , fRES/2 , fRES/2 )
5
6
7
• Free-run timer : 16 bits x 8 channels
•
16-bit free running counter, signals an interrupt when overflow or match with compare
register
•
Includes prescaler (fRES/2 , fRES/2 , fRES/2 , fRES/2 )
•
Timer data register has R/W access
2
Fujitsu Microelectronics Europe GmbH
4
5
6
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MB91F467CA preliminary datasheet ver. 0.13
• PPG : 16 bit x 12 channels
•
16 bit down counter, cycle and duty setting registers
•
Interrupt at triggering, cycle or duty match
•
PWM operation and one-shot operation
•
Internal prescaler allows fRES/2 , fRES/2 , fRES/2 , fRES/2 as counter clock
•
Can be triggered by software or reload timer
•
Reload timer 2/3 available as trigger for PPG 4/5/6/7
•
Reload timer 4/5 available as trigger for PPG 8/9/10/11
•
Reload timer 6/7 available as trigger for PPG 12/13/14/15
•
External trigger for PPG 8 (shared)
•
External trigger for PPG 9 (shared)
•
External trigger for PPG 10 (shared)
•
External trigger for PPG 11 (shared)
•
External trigger for PPG 4/12 (shared)
•
External trigger for PPG 5/13 (shared)
•
External trigger for PPG 6/14 (shared)
•
External trigger for PPG 7/15 (shared)
0
2
4
6
• Input capture : 16 bits x 8 channels
•
Rising edge, falling edge or rising & falling edge sensitive
•
Free-run timer 0 and input capture 0/1 co-operate
•
Free-run timer 1 and input capture 2/3 co-operate
•
Free-run timer 4 and input capture 4/5 co-operate
•
Free-run timer 5 and input capture 6/7 co-operate
• Output compare : 16 bits x 4 channels
•
Signals an interrupt when a match with of 16-bit IO timer occurs
•
An output signal can be generated
•
Free-run timer 2 and output compare 0/1 co-operate
•
Free-run timer 3 and output compare 2/3 co-operate
• LIN-USART (LIN=Local Interconnect Network) : 5 channels
•
Full-duplex double buffer system (4 ch with 16 byte RX/TX FIFO buffer each)
•
With parity/without parity selectable
•
1 or 2 stop bits selectable
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MB91F467CA preliminary datasheet ver. 0.13
•
7 or 8 bits data length selectable
•
NRZ type transfer format
•
Asynchronous /synchronous communications selectable
•
Master-slave communication function (multiprocessor mode)
•
Dedicated baud rate prescaler is embedded in each channel
•
External clock is able to use as transfer clock
•
Parity error, frame error, and overrun error detecting functions
•
SPI compatible
•
LIN master and slave
•
LIN USART 2 and ICU 2 co-operate (for LIN sync field in slave mode)
•
LIN USART 4 and ICU 4 co-operate (for LIN sync field in slave mode)
•
LIN USART 5 and ICU 5 co-operate (for LIN sync field in slave mode)
•
LIN USART 6 and ICU 6 co-operate (for LIN sync field in slave mode)
•
LIN USART 7 and ICU 7 co-operate (for LIN sync field in slave mode)
• CAN : 3 channels
•
Supports CAN protocol version 2.0 part A and B
•
Bit rates up to 1 Mbit/s
•
32 message objects
•
Each message object has its own identifier mask
•
Programmable FIFO mode (cocatenation of message objects)
•
Maskable interrupt
•
Programmable loop-back mode for self-test operation
2
• I C (400k fast mode) : 3 channels
•
Master or slave transmission
•
Arbitration function
•
Clock synchronization function
•
Slave address and general call address detect function
•
Transfer direction detect function
•
Start condition repeat generation and detection function
•
Bus error detect function
•
Compatible to I2C standard and fast mode specification (operation up to 400 kHz, 10 bit
addressing)
•
Includes clock divider functionality
•
SCL and SDA lines include optional noise filter. The noise filter allows the suppression of
spikes in the range of 1 to 1.5 cycles of RES
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MB91F467CA preliminary datasheet ver. 0.13
• PFM (pulse frequency modulator) : 16 bits x 1 channel
•
16-bit reload timers for generating high/low pulse waveforms
•
Includes clock prescaler (fRES/2 , fRES/2 , fRES/2 , fRES/2 , fRES/2 )
1
3
5
6
7
• Sound Generator : 1 channel
•
8-bit PWM signal is mixed with tone frequency from 16-bit reload counter
•
PWM clock by internal prescaler: fRES/2 , fRES/2 , fRES/2 , fRES/2 , fRES/2
•
Tone frequency: PWM frequency / 2 / (reload value + 1)
0
1
2
3
4
• Stepper Motor Controller : 6 channels
•
Four high current outputs for each channel
•
Two synchronized 8/10-bit PWMs per channel
•
Internal prescaling for PMW clock: fRES/1, fRES/4, fRES/5, fRES/6, fRES/8, fRES/10, fRES/12,
fRES/16
• Timebase/watchdog timer (26 bits)
•
20
Adjustable watchdog timer interval (between 2 and 2
26
system clock cycles)
• Real-time clock (counts during stop mode)
•
RTC module can be clocked either from 32 kHz quartz, 4 MHz quartz or from the RC
Oscillator
•
Facility to correct oscillation deviation (subclock calibration)
•
Read/write accessible second/minute/ hour registers
•
Can signal interrupts every halfsecond/second/ minute/hour/day
•
Internal clock divider and prescaler provide exact 1s clock based on a 4 MHz or a 32 kHz
clock input
•
Prescaler value for 4 MHz is 1E847FH
•
Prescaler value for 32 kHz is 003FFFH
• Clock supervisor
•
Monitors external 32kHz and 4MHz for fails (e.g. crystal breaks)Switches in case of fail to
an available recovery clock (other oscillator, or RC oscillator)
• Clock modulator
•
Reduction of Electro Magnetic Emission (EME)
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MB91F467CA preliminary datasheet ver. 0.13
• Subclock calibration
•
Calibration of the RTC timer in 32 kHz or RC oscillator operation, based on the more
accurate 4 MHz quartz is possible
• Main oscillation stabilisation timer
•
23 bit counter for main oscillation stabilisation wait when running in sub clock mode
•
Generates an interrupt when stabilisation time has elapsed
• Sub oscillation stabilisation timer
•
15 bit counter for sub oscillation stabilisation wait when running in main clock mode
•
Generates an interrupt when stabilisation time has elapsed
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MB91F467CA preliminary datasheet ver. 0.13
2.4 Embedded Program/Data Memory (Flash)
2.4.1 Flash features
• 1024kB + 64kB Flash (1088kB : 16x64kB + 8x8kB = 8.5Mbits)
• Power: Single +3.0-5.5V supply
• Programmable wait state for read/write access
• Flash security with security vector at 0x0014:8000 – 0x0014:800F
1
• Basic specification: Same as MBM29LV400TC (except size and part of sector configuration)
• Operation modes:
(1) 64-bit CPU mode:
• CPU reads and executes programs in word (32-bit) length units.
• Flash writing is not possible.
• Actual Flash Memory access is performed in d-word (64-bit) length units.
(2) 32-bit CPU mode:
• CPU reads, writes and executes programs in word (32-bit) length units.
• Actual Flash Memory access is performed in word (32-bit) length units.
(3) 16-bit CPU mode:
• CPU reads and writes in half-word (16-bit) length units.
• Program execution from the Flash is not possible.
• Actual Flash Memory access is performed in word (16-bit) length units.
(4) Flash memory mode (external access to Flash memory enabled)
• Features (through combination of Flash memory macro and FR-CPU interface circuit):
• Functions as CPU program/data storage memory.
• Enables access to 16/32/64-bit bus width.
• Enables read/write/erase by CPU (auto program algorithm*).
• Functions equivalent to MBM29LV400TC stand-alone Flash-memory product.
• Enables read/write/erase by parallel Flash programmer (auto program algorithm*).
*: Auto program algorithm = Embedded Algorithm TM
1
See MB91460 hardware manual for further details.
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MB91F467CA preliminary datasheet ver. 0.13
2.4.2 CPU Mode
2.4.2.1
Flash configuration in CPU mode
Flash memory map in CPU mode (MD[2:0] = 00x):
addr
0014:FFFFh
0014:C000h
SA6 (8kB)
SA7 (8kB)
0014:BFFFh
0014:8000h
SA4 (8kB)
SA5 (8kB)
0014:7FFFh
0014:4000h
SA2 (8kB)
SA3 (8kB)
0014:3FFFh
0014:0000h
SA0 (8kB)
SA1 (8kB)
0013:FFFFh
0012:0000h
SA22 (64kB)
SA23 (64kB)
0011:FFFFh
0010:0000h
SA20 (64kB)
SA21 (64kB)
000F:FFFFh
000E:0000h
SA18 (64kB)
SA19 (64kB)
ROMS5
000D:FFFFh
000C:0000h
SA16 (64kB)
SA17 (64kB)
ROMS4
000B:FFFFh
000A:0000h
SA14 (64kB)
SA15 (64kB)
ROMS3
0009:FFFFh
0008:0000h
SA12 (64kB)
SA13 (64kB)
ROMS2
0007:FFFFh
0006:0000h
SA10 (64kB)
SA11 (64kB)
ROMS1
0005:FFFFh
0004:0000h
SA8 (64kB)
SA9 (64kB)
ROMS0
ROMS7
ROMS6
addr+0
16bit write mode
32bit write mode
addr+1
addr+2
dat[31:16]
addr+3
dat[15:0]
dat[31:0]
Fujitsu Microelectronics Europe GmbH
addr+4
addr+5
addr+6
dat[31:16]
addr+7
dat[15:0]
dat[31:0]
Page 17 of 81
European MCU Design Centre
2.4.2.2
MB91F467CA preliminary datasheet ver. 0.13
Flash access timing settings in CPU mode
The Flash access timing settings described below are valid for MB91F467CA in the 1.8V operation
2
mode of the Main regulator and Flash .
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB
or maximum clock modulation) for Flash read and write access.
Flash read timing settings for MB91F467CA
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 24 MHz
0
0
0
-
1
to 48 MHz
0
0
1
-
2
to 100 MHz
1
1
3
-
4
Flash write timing settings for MB91F467CA (synchronous write)
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 16 MHz
0
-
-
0
3
to 32 MHz
0
-
-
0
4
to 48 MHz
0
-
-
0
5
to 64 MHz
1
-
-
0
6
to 96 MHz
1
-
-
0
7
to 100 MHz
1
-
-
1
8
2
Keep REGSEL_FLASHSEL=0 and REGSEL_MAINSEL=0 at their initial value (HWM Chapter
52.3.1)
Fujitsu Microelectronics Europe GmbH
Page 18 of 81
European MCU Design Centre
2.4.2.3
MB91F467CA preliminary datasheet ver. 0.13
Address mapping from CPU to parallel programming mode
8kB Sectors (SA0 – SA7)
SA0, SA2, SA4, SA6:
Condition: addr >= 14:0000h && addr <= 14:FFFFh && addr[2]==0 :
FA := addr - addr%00:4000h + (addr%00:4000h)/2 - (addr/2)%4 + addr%4 - 05:0000h
SA1, SA3, SA5, SA7:
Condition: addr >= 14:0000h && addr <= 14:FFFFh && addr[2]==1:
FA := addr - addr%00:4000h + (addr%00:4000h)/2 + 00:2000h - (addr/2)%4 + addr%4 - 05:0000h
64kB Sectors (SA8 – SA23)
SA8, SA10, SA12, SA14, SA16, SA18, SA20, SA22:
Condition: addr >= 04:0000h && addr <= 13:FFFFh && addr[2]==0:
FA := addr - addr%02:0000 + (addr%02:0000h)/2 - (addr/2)%4 + addr%4 + 0C:0000h
SA9, SA11, SA13, SA15, SA17, SA19, SA21, SA23:
Condition: addr >= 04:0000h && addr <= 13:FFFFh && addr[2]==1:
FA := addr - addr%02:0000h + (addr%02:0000h)/2 + 01:0000h - (addr/2)%4 + addr%4 + 0C:0000h
3
Remark: FA result is without 20:0000h offset for parallel flash programming .
3
Set offset by keeping FA[21] = 1 as described in section 2.4.3.
Fujitsu Microelectronics Europe GmbH
Page 19 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
2.4.3 Parallel flash programming mode
2.4.3.1
Flash configuration in parallel flash programming mode
Parallel Flash programming mode (MD[2:0] = 111):
FA[21:0]
003F:FFFFh
003F:0000h
SA23 (64kB)
003E:FFFFh
003E:0000h
SA22 (64kB)
003D:FFFFh
003D:0000h
SA21 (64kB)
003C:FFFFh
003C:0000h
SA20 (64kB)
003B:FFFFh
003B:0000h
SA19 (64kB)
003A:FFFFh
003A:0000h
SA18 (64kB)
0039:FFFFh
0039:0000h
SA17 (64kB)
0038:FFFFh
0038:0000h
SA16 (64kB)
0037:FFFFh
0037:0000h
SA15 (64kB)
0036:FFFFh
0036:0000h
SA14 (64kB)
0035:FFFFh
0035:0000h
SA13 (64kB)
0034:FFFFh
0034:0000h
SA12 (64kB)
0033:FFFFh
0033:0000h
SA11 (64kB)
0032:FFFFh
0032:0000h
SA10 (64kB)
0031:FFFFh
0031:0000h
SA9 (64kB)
0030:FFFFh
0030:0000h
SA8 (64kB)
002F:FFFFh
002F:E000h
SA7 (8kB)
002F:DFFFh
002F:C000h
SA6 (8kB)
002F:BFFFh
002F:A000h
SA5 (8kB)
002F:9FFFh
002F:8000h
SA4 (8kB)
002F:7FFFh
002F:6000h
SA3 (8kB)
002F:5FFFh
002F:4000h
SA2 (8kB)
002F:3FFFh
002F:2000h
SA1 (8kB)
002F:1FFFh
002F:0000h
SA0 (8kB)
16bit write mode
FA[1:0]=00
FA[1:0]=10
DQ[15:0]
DQ[15:0]
Remark: Always keep FA[0] = 0 and FA[21] = 1 in parallel programming mode.
Fujitsu Microelectronics Europe GmbH
Page 20 of 81
European MCU Design Centre
2.4.3.2
MB91F467CA preliminary datasheet ver. 0.13
Pin connections in parallel programming mode
Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash
memory's interface circuit enables direct control of the Flash memory unit from external pins by
directly linking some of the signals to GP-Ports. Please see table below for signal mapping.
In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is
generally set when writing/erasing using the parallel Flash programmer. In this mode, all operations of
the 8.5 Mbits Flash memory's Auto Algorithms are available.
Correspondence between MBM29LV400TC and Flash Memory Control Signals
MB91F467CA external pins
MBM29LV400TC
External pins
FR-CPU mode
-
INITX
Flash memory
mode
-
RESET
-
-
Comment
Normal function
Pin number
INITX
84
FRSTX
NMIX
85
-
MD2
MD2
76
Set to ‘1’
-
-
MD1
MD1
75
Set to ‘1’
-
-
MD0
MD0
74
Set to ‘1’
RY/BY
FMCS:RDY bit
RY/BYX
GP28_0
100
BYTE
Internally fixed to ‘H’
BYTEX
GP28_2
102
WE
WEX
GP28_5
111
OE
OEX
GP28_4
110
CEX
GP20_0
38
ATDIN
GP17_7
27
Set to ‘0’
EQIN
GP17_6
26
Set to ‘0’
-
TESTX
GP28_3
103
Set to ‘1’
-
RDYI
GP28_1
101
Set to ‘0’
A-1
FA0
GP17_5
25
Set to ‘0’
A0 to A3
FA1 to FA4
GP29_0 to GP29_3
92 to 95
A4 to A7
FA5 to FA8
GP29_4 to GP29_7
96 to 99
FA9 to FA12
GP16_0 to GP16_3
28 to 31
A12 to A15
FA13 to FA16
GP16_4 to GP16_7
32 to 35
A16 to A19
FA17 to FA20
GP15_0 to GP15_3
20 to 23
CE
-
A8 to A11
Internal control signal
+ control via interface
circuit
Internal address bus
-
FA21
GP17_4
24
DQ0 to DQ7
DQ0 to DQ7
GP14_0 to GP14_7
10 to 17
DQ8 to DQ15
GP02_0 to GP02_7
2 to 9
DQ8 to DQ15
Internal data bus
Fujitsu Microelectronics Europe GmbH
Set to ‘1’
Page 21 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
2.4.4 Flash Security
2.4.4.1
Vector addresses
Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1,
BSV2) controlling the protection functions of the flash security module:
FSV1: 0x14:8000
BSV1: 0x14:8004
FSV2: 0x14:8008
BSV2: 0x14:800C
2.4.4.2
Security Vector FSV1
The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes
and the individual write protection of the 8 kB sectors.
X FSV1 (bits 31 to 16)
The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write
protection modes.
Fujitsu Microelectronics Europe GmbH
Page 22 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Explanation of the bits in the Flash Security Vector FSV1[31:16]
FSV1[18]
FSV1[31:19]
Write Protection
Level
FSV1[17]
FSV1[16]
Write Protection
Read Protection
Flash Security Mode
set all to ‘0’
set to ‘0’
set to ‘0’
set to ‘1’
set all to ‘0’
set to ‘0’
set to ‘1’
set to ‘0’
set all to ‘0’
set to ‘0’
set to ‘1’
set to ‘1’
Read Protection (all device modes, except
INTVEC mode MD[2:0]=”000”)
Write Protection (all device modes, without
exception)
Read Protection (all device modes, except
INTVEC mode MD[2:0]=”000”) and Write
Protection (all device modes)
set all to ‘0’
set to ‘1’
set to ‘0’
set to ‘1’
set all to ‘0’
set to ‘1’
set to ‘1’
set to ‘0’
Read Protection (all device modes, except
INTVEC mode MD[2:0]=”000”)
Write Protection (all device modes, except
INTVEC mode MD[2:0]=”000”)
Read Protection (all device modes, except
set all to ‘0’
set to ‘1’
set to ‘1’
set to ‘1’
INTVEC mode MD[2:0]=”000”) and Write
Protection (all device modes except INTVEC
mode MD[2:0]=”000”)
Fujitsu Microelectronics Europe GmbH
Page 23 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
X FSV1 (bits 15 to 0)
The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write
protection of the 8 kB sectors. It is only evaluated if write protection bit FSV1[17] is set.
Explanation of the bits in the Flash Security Vector FSV1[15:0]
Enable Write
Disable Write
Protection
Protection
SA0
set to ‘0’
set to ‘1’
FSV1[1]
SA1
set to ‘0’
set to ‘1’
FSV1[2]
SA2
set to ‘0’
set to ‘1’
FSV1[3]
SA3
set to ‘0’
set to ‘1’
FSV1[4]
SA4
set to ‘0’
-
FSV1[5]
SA5
set to ‘0’
set to ‘1’
FSV1[6]
SA6
set to ‘0’
set to ‘1’
FSV1[7]
SA7
set to ‘0’
set to ‘1’
FSV1[8]
-
set to ‘0’
set to ‘1’
not available
FSV1[9]
-
set to ‘0’
set to ‘1’
not available
FSV1[10]
-
set to ‘0’
set to ‘1’
not available
FSV1[11]
-
set to ‘0’
set to ‘1’
not available
FSV1[12]
-
set to ‘0’
set to ‘1’
not available
FSV1[13]
-
set to ‘0’
set to ‘1’
not available
FSV1[14]
-
set to ‘0’
set to ‘1’
not available
FSV1[15]
-
set to ‘0’
set to ‘1’
not available
FSV1 bit
Sector
FSV1[0]
Comment
Write protection is mandatory!
Remark: It is mandatory to always set the sector where the Flash Security Vectors FSV1 and
FSV2 are located to write protected (here sector SA4). Otherwise it is possible to overwrite the
Security Vector to a setting where it is possible to either read out the flash content or
manipulate data by writing.
See section 2.4.2.1 for an overview about the sector organisation of the Flash Memory.
Fujitsu Microelectronics Europe GmbH
Page 24 of 81
European MCU Design Centre
2.4.4.3
MB91F467CA preliminary datasheet ver. 0.13
Security Vector FSV2
The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write
protection of the 64 kB sectors. It is only evaluated if write protection bit FSV1[17] is set.
Explanation of the bits in the Flash Security Vector FSV2[31:0]
Enable Write
Disable Write
Protection
Protection
SA8
set to ‘0’
set to ‘1’
FSV2[1]
SA9
set to ‘0’
set to ‘1’
FSV2[2]
SA10
set to ‘0’
set to ‘1’
FSV2[3]
SA11
set to ‘0’
set to ‘1’
FSV2[4]
SA12
set to ‘0’
set to ‘1’
FSV2[5]
SA13
set to ‘0’
set to ‘1’
FSV2[6]
SA14
set to ‘0’
set to ‘1’
FSV2[7]
SA15
set to ‘0’
set to ‘1’
FSV2[8]
SA16
set to ‘0’
set to ‘1’
FSV2[9]
SA17
set to ‘0’
set to ‘1’
FSV2[10]
SA18
set to ‘0’
set to ‘1’
FSV2[11]
SA19
set to ‘0’
set to ‘1’
FSV2[12]
SA20
set to ‘0’
set to ‘1’
FSV2[13]
SA21
set to ‘0’
set to ‘1’
FSV2[14]
SA22
set to ‘0’
set to ‘1’
FSV2[15]
SA8
set to ‘0’
set to ‘1’
FSV2[16]
SA9
set to ‘0’
set to ‘1’
not available
FSV2[17]
SA10
set to ‘0’
set to ‘1’
not available
FSV2[18]
SA11
set to ‘0’
set to ‘1’
not available
FSV2[19]
SA12
set to ‘0’
set to ‘1’
not available
FSV2[20]
SA13
set to ‘0’
set to ‘1’
not available
FSV2[21]
SA14
set to ‘0’
set to ‘1’
not available
FSV1 bit
Sector
FSV2[0]
Fujitsu Microelectronics Europe GmbH
Comment
Page 25 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
FSV2[22]
SA15
set to ‘0’
set to ‘1’
not available
FSV2[23]
SA16
set to ‘0’
set to ‘1’
not available
FSV2[24]
SA17
set to ‘0’
set to ‘1’
not available
FSV2[25]
SA18
set to ‘0’
set to ‘1’
not available
FSV2[26]
SA19
set to ‘0’
set to ‘1’
not available
FSV2[27]
SA20
set to ‘0’
set to ‘1’
not available
FSV2[28]
SA21
set to ‘0’
set to ‘1’
not available
FSV2[29]
SA22
set to ‘0’
set to ‘1’
not available
FSV2[30]
SA23
set to ‘0’
set to ‘1’
not available
FSV2[31]
SA23
set to ‘0’
set to ‘1’
not available
See section 2.4.2.1 for an overview about the sector organisation of the Flash Memory.
2.4.4.4
Register description for Flash Security
For a description of Flash Security registers please refer to Hardware Manual chapter 55.
Fujitsu Microelectronics Europe GmbH
Page 26 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
3 Package and Pin Assignment
3.1 Package
VDD5
P22_2- / INT13
P22_0- / INT12
P25_7 / SMC2M5
P25_6 / SMC2P5
P25_5 / SMC1M5
P25_4 / SMC1P5
HVSS5
HVDD5
P25_3 / SMC2M4
P25_2 / SMC2P4
P25_1 / SMC1M4
P25_0 / SMC1P4
P26_7 / SMC2M3 / AN31
P26_6 / SMC2P3 / AN30
P26_5 / SMC1M3 / AN29
P26_4 / SMC1P3 / AN28
HVSS5
HVDD5
P26_3 / SMC2M2 / AN27
P26_2 / SMC2P2 / AN26
P26_1 / SMC1M2 / AN25
P26_0 / SMC1P2 / AN24
P27_7 / SMC2M1 / AN23
P27_6 / SMC2P1 / AN22
P27_5 / SMC1M1 / AN21
P27_4 / SMC1P1 / AN20
HVSS5
HVDD5
P27_3 / SMC2M0 / AN19
P27_2 / SMC2P0 / AN18
P27_1 / SMC1M0 / AN17
P27_0 / SMC1P0 / AN16
P28_5 / AN13
P28_4 / AN12
VSS5
A QFP144 package will be used for MB91F467CA. The package code is FPT-144P-M08
(144-pin plastic QFP, lead pitch: 0.50mm, 20.0 x 20.0 mm,
Theta-ja = 34 degr.C / W using 4-layer PCB and about 50 degr.C / W using 1-layer PCB).
MB91F467C Pad Layout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSS5
P02_0
P02_1
P02_2
P02_3
P02_4
P02_5
P02_6
P02_7
P14_0
P14_1
P14_2
P14_3
P14_4
P14_5
P14_6
P14_7
VDD5
VSS5
P15_0
P15_1
P15_2
P15_3
P17_4
P17_5
P17_6
P17_7
P16_0
P16_1
P16_2
P16_3
P16_4
P16_5
P16_6
P16_7
VDD5
MB91F467C
VDD5
AVCC5
AVRH5
AVSS
ALARM_0
P28_3
P28_2
P28_1
P28_0
P29_7
P29_6
P29_5
P29_4
P29_3
P29_2
P29_1
P29_0
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X0
X1
MD_3
MONCLK
MD_2
MD_1
MD_0
VSS5
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD5
AVCC5
AVRH5
AVSS
ALARM_0
P28_3 / AN11
P28_2 / AN10
P28_1 / AN9
P28_0 / AN8
P29_7 / AN7
P29_6 / AN6
P29_5 / AN5
P29_4 / AN4
P29_3 / AN3
P29_2 / AN2
P29_1 / AN1
P29_0 / AN0
VSS5
VDD5
VDD5R
VDD5R
VCC18C
VSS5
NMIX
INITX
X1A
X0A
VSS5
X0
X1
MD_3
MONCLK
MD_2
MD_1
MD_0
VSS5
VSS5
P20_0 / SIN2 / AIN0
P20_1 / SOT2 / BIN0
P20_2 / SCK2 / ZIN0/CK2
P19_0 / SIN4 / ^
P19_1 / SOT4 / ^
P19_2 / SCK4 / CK4
P19_4 / SIN5 / ^
P19_5 / SOT5 / ^
P19_6 / SCK5 / CK5
P18_0 / SIN6 / AIN2
P18_1 / SOT6 / BIN2
P18_2 / SCK6 / ZIN2/CK6
P18_4 / SIN7 / AIN3
P18_5 / SOT7 / BIN3
P18_6 / SCK7 / ZIN3/CK7
P23_6- / INT11
VDD5
VSS5
P24_0 / INT0
P24_1 / INT1
P24_2 / INT2
P24_3 / INT3
P24_4 / INT4 / SDA2
P24_5 / INT5 / SCL2
P24_6 / INT6 / SDA3
P24_7 / INT7 / SCL3
P23_0 / RX0 / INT8
P23_1 / TX0
P23_2 / RX1 / INT9
P23_3 / TX1
P23_4 / RX2 / INT10
P23_5 / TX2
P22_4 / SDA0 / INT14
P22_5 / SCL0
VDD5
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSS5
P20_0
P20_1
P20_2
P19_0
P19_1
P19_2
P19_4
P19_5
P19_6
P18_0
P18_1
P18_2
P18_4
P18_5
P18_6
P23_6
VDD5
VSS5
P24_0
P24_1
P24_2
P24_3
P24_4
P24_5
P24_6
P24_7
P23_0
P23_1
P23_2
P23_3
P23_4
P23_5
P22_4
P22_5
VDD5
VSS5
P02_0P02_1P02_2P02_3P02_4P02_5P02_6P02_7P14_0 / ICU0/TIN0 / TIN0 / TTG8/0
P14_1 / ICU1/TIN1 / TIN1 / TTG9/1
P14_2 / ICU2/TIN2 / TIN2 / TTG10/2
P14_3 / ICU3/TIN3 / TIN3 / TTG11/3
P14_4 / ICU4/TIN4 / TIN4 / TTG12/4
P14_5 / ICU5/TIN5 / TIN5 / TTG13/5
P14_6 / ICU6/TIN6 / TIN6 / TTG14/6
P14_7 / ICU7/TIN7 / TIN7 / TTG15/7
VDD5
VSS5
P15_0 / OCU0 / TOT0
P15_1 / OCU1 / TOT1
P15_2 / OCU2 / TOT2
P15_3 / OCU3 / TOT3
P17_4 / PPG4
P17_5 / PPG5
P17_6 / PPG6
P17_7 / PPG7
P16_0 / PPG8 / ^
P16_1 / PPG9 / ^
P16_2 / PPG10 / ^
P16_3 / PPG11 / ^
P16_4 / PPG12 / SGA
P16_5 / PPG13 / SGO
P16_6 / PPG14 / PFM
P16_7 / PPG15 / ATGX
VDD5
VDD5 144
P22_2 143
P22_0 142
P25_7 141
P25_6 140
P25_5 139
P25_4 138
HVSS5 137
HVDD5 136
P25_3 135
P25_2 134
P25_1 133
P25_0 132
P26_7 131
P26_6 130
P26_5 129
P26_4 128
HVSS5 127
HVDD5 126
P26_3 125
P26_2 124
P26_1 123
P26_0 122
P27_7 121
P27_6 120
P27_5 119
P27_4 118
HVSS5 117
HVDD5 116
P27_3 115
P27_2 114
P27_1 113
P27_0 112
P28_5 111
P28_4 110
VSS5 109
2006-06-02
Fujitsu Microelectronics Europe GmbH
Page 27 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
3.2 I/O Pins and their functions
Pin
I/O
PFR=1
EPFR=1
Special
Pad
Type
9
8
7
6
5
4
3
2
79
80
83
82
77
17
16
15
14
13
12
11
10
23
22
21
20
35
34
33
32
31
30
29
28
27
26
25
24
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
71
70
143
142
53
69
68
67
66
65
P02_7
P02_6
P02_5
P02_4
P02_3
P02_2
P02_1
P02_0
X1
X0
X1A
X0A
MONCLK
P14_7
P14_6
P14_5
P14_4
P14_3
P14_2
P14_1
P14_0
P15_3
P15_2
P15_1
P15_0
P16_7
P16_6
P16_5
P16_4
P16_3
P16_2
P16_1
P16_0
P17_7
P17_6
P17_5
P17_4
P18_6
P18_5
P18_4
P18_2
P18_1
P18_0
P19_6
P19_5
P19_4
P19_2
P19_1
P19_0
P20_2
P20_1
P20_0
P22_5
P22_4
P22_2
P22_0
P23_6
P23_5
P23_4
P23_3
P23_2
P23_1
--------ICU7/TIN7
ICU6/TIN6
ICU5/TIN5
ICU4/TIN4
ICU3/TIN3
ICU2/TIN2
ICU1/TIN1
ICU0/TIN0
OCU3
OCU2
OCU1
OCU0
PPG15
PPG14
PPG13
PPG12
PPG11
PPG10
PPG9
PPG8
PPG7
PPG6
PPG5
PPG4
SCK7
SOT7
SIN7
SCK6
SOT6
SIN6
SCK5
SOT5
SIN5
SCK4
SOT4
SIN4
SCK2
SOT2
SIN2
SCL0
SDA0
---TX2
RX2
TX1
RX1
TX0
TIN7
TIN6
TIN5
TIN4
TIN3
TIN2
TIN1
TIN0
TOT3
TOT2
TOT1
TOT0
ATGX
PFM
SGO
SGA
ZIN3/CK7
BIN3
AIN3
ZIN2/CK6
BIN2
AIN2
CK5
CK4
ZIN0/CK2
BIN0
AIN0
INT14
INT13
INT12
INT11
INT10
INT9
-
TTG15/7
TTG14/6
TTG13/5
TTG12/4
TTG11/3
TTG10/2
TTG9/1
TTG8/0
-
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TO00_1
TO00_0
TO01_1
TO01_0
TC10_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP02_0
TP02_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
TP04_0
Fujitsu Microelectronics Europe GmbH
Comments
General Purpose Port 00
4 MHz Oscillator
32 kHz Oscillator
Clock Monitor output
General Purpose Port 14
ICU: Input Capture Unit event input
TIN: Reload Timer external trigger input
TTG: PPG external trigger input
Note: Setting EPFR connects ICU to LIN-Break
outputs of USART
General Purpose Port 15
OCU: Output Compare waveform output
TOT: Reload Timer output
ATGX: ADC external trigger
PFM: Pulse Frequency Modulator output
SGO, SGA: Sound Generator outputs
General Purpose Port 16
PPG: PPG waveform output
General Purpose Port 17
PPG: PPG waveform output
General Purpose Port 18
SCK, SOT, SIN: see below
CK: Free Run Timer external clock input
AIN, BIN, ZIN: Up-/Down Counter inputs
General Purpose Port 19
SCK: LIN-USART serial clock in/out
SOT: LIN-USART serial data output
SIN: LIN-USART serial data input
CK: Free Run Timer external clock input
General Purpose Port 20
AIN, BIN, ZIN: Up-/Down Counter inputs
SCK, SIN, SOT: LIN-USART I/O
General Purpose Port 22
SCL, SDA: I2C Clock/Data in/out (open drain)
INT: External Interrupt inputs (I2C wakeup)
General Purpose Port 23
TX, RX: CAN Transmit / Receive out/in
INT: External Interrupt inputs (CAN wakeup)
Page 28 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Pin
I/O
PFR=1
EPFR=1
Special
64
63
62
61
60
59
58
57
56
141
140
139
138
135
134
133
132
131
130
129
128
125
124
123
122
121
120
119
118
115
114
113
112
104
111
110
103
102
101
100
99
98
97
96
95
94
93
92
84
85
78
76
75
74
18
36
54
72
90
108
144
1
19
37
55
73
P23_0
P24_7
P24_6
P24_5
P24_4
P24_3
P24_2
P24_1
P24_0
P25_7
P25_6
P25_5
P25_4
P25_3
P25_2
P25_1
P25_0
P26_7
P26_6
P26_5
P26_4
P26_3
P26_2
P26_1
P26_0
P27_7
P27_6
P27_5
P27_4
P27_3
P27_2
P27_1
P27_0
ALARM_0
P28_5
P28_4
P28_3
P28_2
P28_1
P28_0
P29_7
P29_6
P29_5
P29_4
P29_3
P29_2
P29_1
P29_0
INITX
NMIX
MD_3
MD_2
MD_1
MD_0
VDD5
VDD5
VDD5
VDD5
VDD5
VDD5
VDD5
VSS5
VSS5
VSS5
VSS5
VSS5
RX0
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
SMC2M5
SMC2P5
SMC1M5
SMC1P5
SMC2M4
SMC2P4
SMC1M4
SMC1P4
SMC2M3
SMC2P3
SMC1M3
SMC1P3
SMC2M2
SMC2P2
SMC1M2
SMC1P2
SMC2M1
SMC2P1
SMC1M1
SMC1P1
SMC2M0
SMC2P0
SMC1M0
SMC1P0
AN13
AN12
AN11
AN10
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
-
INT8
AN31
AN30
AN29
AN28
AN27
AN26
AN25
AN24
AN23
AN22
AN21
AN20
AN19
AN18
AN17
AN16
-
SCL3
SDA3
SCL2
SDA2
-
Fujitsu Microelectronics Europe GmbH
Pad
Type
TP04_0
TP02_0
TP02_0
TP02_0
TP02_0
TP04_0
TP04_0
TP04_0
TP04_0
TP05_1
TP05_1
TP05_1
TP05_1
TP05_1
TP05_1
TP05_1
TP05_1
TP05_0
TP05_0
TP05_0
TP05_0
TP05_0
TP05_0
TP05_0
TP05_0
TP05_0
TP05_0
TP05_0
TP05_0
TP05_0
TP05_0
TP05_0
TP05_0
TA02_0
TP03_0
TP03_0
TP03_0
TP03_0
TP03_0
TP03_0
TP03_0
TP03_0
TP03_0
TP03_0
TP03_0
TP03_0
TP03_0
TP03_0
TC02_0
TC02_0
TC01_0
TC01_0
TC01_0
TC01_0
Comments
General Purpose Port 24
SCL, SDA: I2C Clock/Data in/out (open drain)
INT: External Interrupt input
General Purpose Port 25
SMC: Stepper Motor Control 5
SMC: Stepper Motor Control 4
General Purpose Port 26
SMC: Stepper Motor Control 3
AN: ADC analog input
SMC: Stepper Motor Control 2
AN: ADC analog input
General Purpose Port 27
SMC: Stepper Motor Control 1
AN: ADC analog input
SMC: Stepper Motor Control 0
AN: ADC analog input
ALARM Comparator analog input
General Purpose Port 28
AN: ADC analog input
General Purpose Port 29
AN: ADC analog input
Initialization input (low active)
Non-Maskable Interrupt input
To be connected to VSS
Device Mode inputs
Power Supply 5 Volt
Ground Supply
Page 29 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Pin
I/O
PFR=1
EPFR=1
Special
81
86
91
109
116
126
136
117
127
137
105
106
107
88
89
87
VSS5
VSS5
VSS5
VSS5
HVDD5
HVDD5
HVDD5
HVSS5
HVSS5
HVSS5
AVSS
AVRH5
AVCC5
VDD5R
VDD5R
VCC18C
-
-
-
Fujitsu Microelectronics Europe GmbH
Pad
Type
Comments
Ground Supply
SMC Hi-Current Power supply
SMC Hi-Current Ground supply
TA03_0
TA01_0
TA00_0
Analog Ground + Low-Reference voltage
Analog High-Reference voltage
Analog Power supply
Voltage Regulator Power supply
Voltage Regulator Capacitance pin
Page 30 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
3.3 I/O Pin Types
Pin
Type
Pull Up/
Down
Input Type
STOP
control
Output
Driver
TP02_0
U/D control
CH / A / TTL / CH2
Stop
3 mA
TP03_0
U/D control
CH / A / TTL / CH2
Stop
2/5 mA
General Purpose I/O with 1 analog input line
TP04_0
U/D control
CH / A / TTL / CH2
Stop
2/5 mA
General Purpose I/O
TP05_0
U/D control
CH / A / TTL / CH2
Stop
2/5/30 mA
General Purpose I/O, 30mA SMC, 2 analog lines
General Purpose I/O, 30mA SMC, 1 analog line
Comment
I2C Pin (open drain if PFR=1)
TP05_1
U/D control
CH / A / TTL / CH2
Stop
2/5/30 mA
TC01_0
-
C2
no
-
Mode Pin
TC02_0
Up
C2
no
-
Input pin (INITX, NMIX)
TC10_0
-
-
no
5 mA
TA00_0
-
-
-
-
Analog power supply pin
TA01_0
-
-
-
-
Analog I/O pin
TA02_0
-
-
-
-
Analog I/O pin
TA03_0
-
-
-
-
Analog Ground pin
Threestate Output port 5mA for MONCLK
Notes:
•
The pull-up / pull-down resistors are typical 50 kOhm.
The controlled pull-up/down's can be enabled by register setting.
•
Input Types: CH
CMOS Schmitt trigger
CH2
CMOS Schmitt trigger 2
A
CMOS Automotive Schmitt trigger
TTL
TTL
(for input high/low voltages, please see section Operating Conditions)
•
Stop control: Switch to HiZ in STOP mode by register setting, and disable input lines
in STOP if the port is not configuerd to be external interrupt input.
•
Default output driver strength is 3 mA (I2C pins) and 5 mA (all other pins).
Fujitsu Microelectronics Europe GmbH
Page 31 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
4 Recommended Settings
4.1 PLL and Clockgear settings
Please note that for MB91F467CA the core base clock frequencies are valid in the 1.8V operation
4
mode of the Main regulator and Flash .
Recommended PLL divider and clockgear settings
Frequency
Parameter
PLL Input
(CK)
[MHz]
Clockgear
Parameter
PLL Output
(X)
[MHz]
Core base
Clock
[MHz]
DIVM
DIVN
DIVG
MULG
4
2
25
16
24
200
100
4
2
24
16
24
192
96
4
2
23
16
24
184
92
4
2
22
16
24
176
88
4
2
21
16
20
168
84
4
2
20
16
20
160
80
4
2
19
16
20
152
76
4
2
18
16
20
144
72
4
2
17
16
16
136
68
4
2
16
16
16
128
64
4
2
15
16
16
120
60
4
2
14
16
16
112
56
4
2
13
16
12
104
52
4
2
12
16
12
96
48
4
2
11
16
12
88
44
4
4
10
16
24
160
40
4
4
9
16
24
144
36
4
4
8
16
24
128
32
4
Keep REGSEL_FLASHSEL=0 and REGSEL_MAINSEL=0 at their initial value (HWM Chapter
52.3.1)
Fujitsu Microelectronics Europe GmbH
Page 32 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
4
4
7
16
24
112
28
4
6
6
16
24
144
24
4
8
5
16
28
160
20
4
10
4
16
32
160
16
4
12
3
16
32
144
12
4.2 Flash interface settings
Please refer to section 2.4.2.2 ‘Flash access timing settings in CPU mode’ for the recommended Flash
interface settings.
Fujitsu Microelectronics Europe GmbH
Page 33 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
4.3 Clock Modulator settings
The following table shows all possible settings for the Clock Modulator in a base clock frequency
range from 32MHz up to 88MHz. Fmax must not exceed the maximum specified frequency of
100MHz.
The flash access time settings (see section 2.4.2.2) need to be adjusted according to Fmax while the
PLL and clockgear settings (see section 4.1) should be set according to base clock frequency.
Clock Modulator settings and frequency range
Modulation
Degree
(k)
Random No
CMPR
Baseclk
Fmin
Fmax
(N)
[hex]
[MHz]
[MHz]
[MHz]
1
3
026F
88
79.5
98.5
1
3
026F
84
76.1
93.8
1
3
026F
80
72.6
89.1
1
5
02AE
80
68.7
95.8
2
3
046E
80
68.7
95.8
1
3
026F
76
69.1
84.5
1
5
02AE
76
65.3
90.8
1
7
02ED
76
62
98.1
2
3
046E
76
65.3
90.8
3
3
066D
76
62
98.1
1
3
026F
72
65.5
79.9
1
5
02AE
72
62
85.8
1
7
02ED
72
58.8
92.7
2
3
046E
72
62
85.8
3
3
066D
72
58.8
92.7
1
3
026F
68
62
75.3
1
5
02AE
68
58.7
80.9
1
7
02ED
68
55.7
87.3
1
9
032C
68
53
95
2
3
046E
68
58.7
80.9
2
5
04AC
68
53
95
3
3
066D
68
55.7
87.3
4
3
086C
68
53
95
1
3
026F
64
58.5
70.7
1
5
02AE
64
55.3
75.9
1
7
02ED
64
52.5
82
1
9
032C
64
49.9
89.1
1
11
036B
64
47.6
97.6
2
3
046E
64
55.3
75.9
2
5
04AC
64
49.9
89.1
3
3
066D
64
52.5
82
4
3
086C
64
49.9
89.1
5
3
0A6B
64
47.6
97.6
Fujitsu Microelectronics Europe GmbH
Page 34 of 81
European MCU Design Centre
Modulation
Degree
(k)
MB91F467CA preliminary datasheet ver. 0.13
Random No
CMPR
Baseclk
Fmin
Fmax
(N)
[hex]
[MHz]
[MHz]
[MHz]
1
3
026F
60
54.9
66.1
1
5
02AE
60
51.9
71
1
7
02ED
60
49.3
76.7
1
9
032C
60
46.9
83.3
1
11
036B
60
44.7
91.3
2
3
046E
60
51.9
71
2
5
04AC
60
46.9
83.3
3
3
066D
60
49.3
76.7
4
3
086C
60
46.9
83.3
5
3
0A6B
60
44.7
91.3
1
3
026F
56
51.4
61.6
1
5
02AE
56
48.6
66.1
1
7
02ED
56
46.1
71.4
1
9
032C
56
43.8
77.6
1
11
036B
56
41.8
84.9
1
13
03AA
56
39.9
93.8
2
3
046E
56
48.6
66.1
2
5
04AC
56
43.8
77.6
2
7
04EA
56
39.9
93.8
3
3
066D
56
46.1
71.4
3
5
06AA
56
39.9
93.8
4
3
086C
56
43.8
77.6
5
3
0A6B
56
41.8
84.9
6
3
0C6A
56
39.9
93.8
1
3
026F
52
47.8
57
1
5
02AE
52
45.2
61.2
1
7
02ED
52
42.9
66.1
1
9
032C
52
40.8
71.8
1
11
036B
52
38.8
78.6
1
13
03AA
52
37.1
86.8
1
15
03E9
52
35.5
96.9
2
3
046E
52
45.2
61.2
2
5
04AC
52
40.8
71.8
2
7
04EA
52
37.1
86.8
3
3
066D
52
42.9
66.1
3
5
06AA
52
37.1
86.8
4
3
086C
52
40.8
71.8
5
3
0A6B
52
38.8
78.6
6
3
0C6A
52
37.1
86.8
7
3
0E69
52
35.5
96.9
1
3
026F
48
44.2
52.5
1
5
02AE
48
41.8
56.4
1
7
02ED
48
39.6
60.9
1
9
032C
48
37.7
66.1
1
11
036B
48
35.9
72.3
1
13
03AA
48
34.3
79.9
Fujitsu Microelectronics Europe GmbH
Page 35 of 81
European MCU Design Centre
Modulation
Degree
(k)
MB91F467CA preliminary datasheet ver. 0.13
Random No
CMPR
Baseclk
Fmin
Fmax
(N)
[hex]
[MHz]
[MHz]
[MHz]
1
15
03E9
48
32.8
89.1
2
3
046E
48
41.8
56.4
2
5
04AC
48
37.7
66.1
2
7
04EA
48
34.3
79.9
3
3
066D
48
39.6
60.9
3
5
06AA
48
34.3
79.9
4
3
086C
48
37.7
66.1
5
3
0A6B
48
35.9
72.3
6
3
0C6A
48
34.3
79.9
7
3
0E69
48
32.8
89.1
1
3
026F
44
40.6
48.1
1
5
02AE
44
38.4
51.6
1
7
02ED
44
36.4
55.7
1
9
032C
44
34.6
60.4
1
11
036B
44
33
66.1
1
13
03AA
44
31.5
73
1
15
03E9
44
30.1
81.4
2
3
046E
44
38.4
51.6
2
5
04AC
44
34.6
60.4
2
7
04EA
44
31.5
73
2
9
0528
44
28.9
92.1
3
3
066D
44
36.4
55.7
3
5
06AA
44
31.5
73
4
3
086C
44
34.6
60.4
4
5
08A8
44
28.9
92.1
5
3
0A6B
44
33
66.1
6
3
0C6A
44
31.5
73
7
3
0E69
44
30.1
81.4
8
3
1068
44
28.9
92.1
1
3
026F
40
37
43.6
1
5
02AE
40
34.9
46.8
1
7
02ED
40
33.1
50.5
1
9
032C
40
31.5
54.8
1
11
036B
40
30
59.9
1
13
03AA
40
28.7
66.1
1
15
03E9
40
27.4
73.7
2
3
046E
40
34.9
46.8
2
5
04AC
40
31.5
54.8
2
7
04EA
40
28.7
66.1
2
9
0528
40
26.3
83.3
3
3
066D
40
33.1
50.5
3
5
06AA
40
28.7
66.1
3
7
06E7
40
25.3
95.8
4
3
086C
40
31.5
54.8
4
5
08A8
40
26.3
83.3
5
3
0A6B
40
30
59.9
Fujitsu Microelectronics Europe GmbH
Page 36 of 81
European MCU Design Centre
Modulation
Degree
(k)
Random No
MB91F467CA preliminary datasheet ver. 0.13
CMPR
Baseclk
Fmin
Fmax
(N)
[hex]
[MHz]
[MHz]
[MHz]
6
3
0C6A
40
28.7
66.1
7
3
0E69
40
27.4
73.7
8
3
1068
40
26.3
83.3
9
3
1267
40
25.3
95.8
1
3
026F
36
33.3
39.2
1
5
02AE
36
31.5
42
1
7
02ED
36
29.9
45.3
1
9
032C
36
28.4
49.2
1
11
036B
36
27.1
53.8
1
13
03AA
36
25.8
59.3
1
15
03E9
36
24.7
66.1
2
3
046E
36
31.5
42
2
5
04AC
36
28.4
49.2
2
7
04EA
36
25.8
59.3
2
9
0528
36
23.7
74.7
3
3
066D
36
29.9
45.3
3
5
06AA
36
25.8
59.3
3
7
06E7
36
22.8
85.8
4
3
086C
36
28.4
49.2
4
5
08A8
36
23.7
74.7
5
3
0A6B
36
27.1
53.8
6
3
0C6A
36
25.8
59.3
7
3
0E69
36
24.7
66.1
8
3
1068
36
23.7
74.7
9
3
1267
36
22.8
85.8
1
3
026F
32
29.7
34.7
1
5
02AE
32
28
37.3
1
7
02ED
32
26.6
40.2
1
9
032C
32
25.3
43.6
1
11
036B
32
24.1
47.7
1
13
03AA
32
23
52.5
1
15
03E9
32
22
58.6
2
3
046E
32
28
37.3
2
5
04AC
32
25.3
43.6
2
7
04EA
32
23
52.5
2
9
0528
32
21.1
66.1
2
11
0566
32
19.5
89.1
3
3
066D
32
26.6
40.2
3
5
06AA
32
23
52.5
3
7
06E7
32
20.3
75.9
4
3
086C
32
25.3
43.6
4
5
08A8
32
21.1
66.1
5
3
0A6B
32
24.1
47.7
5
5
0AA6
32
19.5
89.1
6
3
0C6A
32
23
52.5
7
3
0E69
32
22
58.6
Fujitsu Microelectronics Europe GmbH
Page 37 of 81
European MCU Design Centre
Modulation
Degree
(k)
MB91F467CA preliminary datasheet ver. 0.13
Random No
CMPR
Baseclk
Fmin
Fmax
(N)
[hex]
[MHz]
[MHz]
[MHz]
3
1068
32
21.1
66.1
9
3
1267
32
20.3
75.9
10
3
1466
32
19.5
89.1
8
Fujitsu Microelectronics Europe GmbH
Page 38 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
5 Interrupt Vector Table
This section shows the allocation of interrupt and interrupt vector/interrupt register.
Interrupt number
Interrupt level
*1
Interrupt vector
*2
Interrupt
Decimal
Hexadecimal
Setting
Register
Register
address
Offset
Default Vector
address
Reset
0
00
-
-
0x3FC
0x000FFFFC
Mode vector
1
01
-
-
0x3F8
0x000FFFF8
System reserved
2
02
-
-
0x3F4
0x000FFFF4
System reserved
3
03
-
-
0x3F0
0x000FFFF0
System reserved
4
04
-
-
0x3EC
0x000FFFEC
CPU supervisor mode
*6
(INT #5 instruction)
5
05
-
-
0x3E8
0x000FFFE8
Memory Protection
*6
exception
6
06
-
-
0x3E4
0x000FFFE4
Co-processor
*5
fault trap
7
07
-
-
0x3E0
0x000FFFE0
Co-processor
*5
error trap
8
08
-
-
0x3DC
0x000FFFDC
9
09
-
-
0x3D8
0x000FFFD8
10
0A
-
-
0x3D4
0x000FFFD4
INTE instruction
Instruction break
*5
exception
*5
Fujitsu Microelectronics Europe GmbH
RN
Page 39 of 81
European MCU Design Centre
Operand break trap
*5
MB91F467CA preliminary datasheet ver. 0.13
11
0B
-
-
0x3D0
0x000FFFD0
12
0C
-
-
0x3CC
0x000FFFCC
13
0D
-
-
0x3C8
0x000FFFC8
Undefined instruction
exception
14
0E
-
-
0x3C4
0x000FFFC4
NMI request
15
0F
FH fixed
0x3C0
0x000FFFC0
External Interrupt 0
16
10
0x3BC
0x000FFFBC
0, 16
0x3B8
0x000FFFB8
1, 17
0x3B4
0x000FFFB4
2, 18
0x3B0
0x000FFFB0
3, 19
0x3AC
0x000FFFAC
20
0x3A8
0x000FFFA8
21
0x3A4
0x000FFFA4
22
0x3A0
0x000FFFA0
23
0x39C
0x000FFF9C
0x398
0x000FFF98
0x394
0x000FFF94
0x390
0x000FFF90
0x38C
0x000FFF8C
0x388
0x000FFF88
0x384
0x000FFF84
Step trace trap
*5
NMI interrupt (tool)
*5
ICR00
External Interrupt 1
17
11
External Interrupt 2
18
12
ICR01
External Interrupt 3
19
13
External Interrupt 4
20
14
ICR02
External Interrupt 5
21
15
External Interrupt 6
22
16
ICR03
External Interrupt 7
23
17
External Interrupt 8
24
18
ICR04
External Interrupt 9
25
19
External Interrupt 10
26
1A
ICR05
External Interrupt 11
27
1B
External Interrupt 12
28
1C
ICR06
External Interrupt 13
29
1D
External Interrupt 14
30
1E
Fujitsu Microelectronics Europe GmbH
ICR07
0x440
0x441
0x442
0x443
0x444
0x445
0x446
0x447
Page 40 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
External
reservedInterrupt 15
31
1F
Reload Timer 0
32
20
ICR08
Reload Timer 1
33
21
Reload Timer 2
34
22
ICR09
Reload Timer 3
35
23
Reload Timer 4
36
24
ICR10
Reload Timer 5
37
25
Reload Timer 6
38
26
ICR11
Reload Timer 7
39
27
Free Run Timer 0
40
28
ICR12
Free Run Timer 1
41
29
Free Run Timer 2
42
2A
ICR13
Free Run Timer 3
43
2B
Free Run Timer 4
44
2C
ICR14
Free Run Timer 5
45
2D
Free Run Timer 6
46
2E
ICR15
Free Run Timer 7
47
2F
CAN 0
48
30
ICR16
CAN 1
49
31
CAN 2
50
32
ICR17
CAN
3
reserved
51
33
CAN
4
reserved
52
34
Fujitsu Microelectronics Europe GmbH
ICR18
0x380
0x000FFF80
0x37C
0x000FFF7C
4, 32
0x378
0x000FFF78
5, 33
0x374
0x000FFF74
34
0x370
0x000FFF70
35
0x36C
0x000FFF6C
36
0x368
0x000FFF68
37
0x364
0x000FFF64
38
0x360
0x000FFF60
39
0x35C
0x000FFF5C
40
0x358
0x000FFF58
41
0x354
0x000FFF54
42
0x350
0x000FFF50
43
0x34C
0x000FFF4C
44
0x348
0x000FFF48
45
0x344
0x000FFF44
46
0x340
0x000FFF40
47
0x33C
0x000FFF3C
0x338
0x000FFF38
0x334
0x000FFF34
0x330
0x000FFF30
0x32C
0x000FFF2C
0x448
0x449
0x44A
0x44B
0x44C
0x44D
0x44E
0x44F
0x450
0x451
0x452
Page 41 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
CAN
5
reserved
53
35
USART
reserved(LIN) 0 RX
54
36
ICR19
USART
reserved(LIN) 0 TX
55
37
USART
reserved(LIN) 1 RX
56
38
57
39
USART (LIN) 2 RX
58
3A
59
3B
reserved
60
3C
0x324
0x000FFF24
6, 48
0x320
0x000FFF20
7, 49
0x31C
0x000FFF1C
8, 50
0x318
0x000FFF18
9, 51
0x314
0x000FFF14
52
0x310
0x000FFF10
53
0x30C
0x000FFF0C
54
55
0x454
ICR21
USART (LIN) 2 TX
0x000FFF28
0x453
ICR20
USART
(LIN) 1 TX
reserved
0x328
0x455
ICR22
0x456
reserved
61
3D
0x308
0x000FFF08
System reserved
62
3E
0x304
0x000FFF04
0x300
0x000FFF00
0x2FC
0x000FFEFC
0x2F8
0x000FFEF8
0x2F4
0x000FFEF4
10, 56
0x2F0
0x000FFEF0
11, 57
0x2EC
0x000FFEEC
12, 58
0x2E8
0x000FFEE8
13, 59
0x2E4
0x000FFEE4
60
0x2E0
0x000FFEE0
61
0x2DC
0x000FFEDC
62
0x2D8
0x000FFED8
63
ICR23
Delayed Interrupt
System reserved
*3
63
3F
64
40
*4
(ICR24)
System reserved
*3
USART (LIN, FIFO) 4 RX
65
41
66
42
ICR25
USART (LIN, FIFO) 4 TX
67
43
USART (LIN, FIFO) 5 RX
68
44
ICR26
USART (LIN, FIFO) 5 TX
69
45
USART (LIN, FIFO) 6 RX
70
46
ICR27
USART (LIN, FIFO) 6 TX
71
47
USART (LIN, FIFO) 7 RX
72
48
ICR28
USART (LIN, FIFO) 7 TX
73
49
Fujitsu Microelectronics Europe GmbH
0x457
(0x458)
0x459
0x45A
0x45B
0x45C
Page 42 of 81
European MCU Design Centre
I2C 0 / I2C 2
74
MB91F467CA preliminary datasheet ver. 0.13
4A
ICR29
I2C
I2C 1
3 / I2C 3
75
4B
USART
reserved(LIN) 8 RX
76
4C
ICR30
USART (LIN) 8 TX
reserved
77
4D
reserved
USART (LIN) 9 RX
78
4E
ICR31
USART (LIN) 9 TX
reserved
79
4F
USART
reserved(LIN) 10 RX
80
50
ICR32
USART
reserved(LIN) 10 TX
81
51
USART
reserved(LIN) 11 RX
82
52
ICR33
USART
reserved(LIN) 11 TX
83
53
USART (LIN) 12 RX
reserved
84
54
ICR34
USART (LIN) 12 TX
reserved
85
55
USART
reserved(LIN) 13 RX
86
56
ICR35
USART (LIN) 13 TX
reserved
87
57
reserved
USART (LIN) 14 RX
88
58
ICR36
USART (LIN) 14 TX
reserved
89
59
USART
reserved(LIN) 15 RX
90
5A
ICR37
USART (LIN) 15 TX
reserved
91
5B
Input Capture 0
92
5C
ICR38
Input Capture 1
93
5D
Input Capture 2
94
5E
ICR39
Input Capture 3
95
5F
Fujitsu Microelectronics Europe GmbH
0x2D4
0x000FFED4
0x2D0
0x000FFED0
0x2CC
0x000FFECC
64
0x2C8
0x000FFEC8
65
0x2C4
0x000FFEC4
66
0x2C0
0x000FFEC0
67
0x2BC
0x000FFEBC
68
0x2B8
0x000FFEB8
69
0x2B4
0x000FFEB4
70
0x2B0
0x000FFEB0
71
0x2AC
0x000FFEAC
72
0x2A8
0x000FFEA8
73
0x2A4
0x000FFEA4
74
0x2A0
0x000FFEA0
75
0x29C
0x000FFE9C
76
0x298
0x000FFE98
77
0x294
0x000FFE94
78
0x290
0x000FFE90
79
0x28C
0x000FFE8C
80
0x288
0x000FFE88
81
0x284
0x000FFE84
82
0x280
0x000FFE80
83
0x45D
0x45E
0x45F
0x460
0x461
0x462
0x463
0x464
0x465
0x466
0x467
Page 43 of 81
European MCU Design Centre
Input Capture 4
96
MB91F467CA preliminary datasheet ver. 0.13
60
ICR40
Input Capture 5
97
61
Input Capture 6
98
62
ICR41
Input Capture 7
99
63
Output Compare 0
100
64
101
65
Output Compare 2
102
66
103
67
Output
Compare 4
reserved
104
68
105
69
Output
Compare 6
reserved
106
6A
107
6B
Sound Generator
108
6C
109
6D
System reserved
110
6E
ICR47
System reserved
111
6F
Prog.
Pulse Gen. 0
reserved
112
70
ICR48
Prog.
Pulse Gen. 1
reserved
113
71
reserved
Prog.
Pulse Gen. 2
114
72
ICR49
Prog.
Pulse Gen. 3
reserved
115
73
Prog. Pulse Gen. 4
116
74
ICR50
Prog. Pulse Gen. 5
117
75
Fujitsu Microelectronics Europe GmbH
85
0x274
0x000FFE74
86
0x270
0x000FFE70
87
0x26C
0x000FFE6C
88
0x268
0x000FFE68
89
0x264
0x000FFE64
90
0x260
0x000FFE60
91
0x25C
0x000FFE5C
92
0x258
0x000FFE58
93
0x254
0x000FFE54
94
0x250
0x000FFE50
95
0x24C
0x000FFE4C
0x248
0x000FFE48
0x244
0x000FFE44
0x240
0x000FFE40
0x23C
0x000FFE3C
15, 96
0x238
0x000FFE38
97
0x234
0x000FFE34
98
0x230
0x000FFE30
99
0x22C
0x000FFE2C
100
0x228
0x000FFE28
101
0x46D
ICR46
Phase Frequ. Modulator
0x000FFE78
0x46C
ICR45
Output
Compare 7
reserved
0x278
0x46B
ICR44
reserved
Output
Compare 5
84
0x46A
ICR43
Output Compare 3
0x000FFE7C
0x469
ICR42
Output Compare 1
0x27C
0x468
0x46E
*4
0x46F
0x470
0x471
0x472
Page 44 of 81
European MCU Design Centre
Prog. Pulse Gen. 6
118
MB91F467CA preliminary datasheet ver. 0.13
76
ICR51
Prog. Pulse Gen. 7
119
77
Prog. Pulse Gen. 8
120
78
ICR52
Prog. Pulse Gen. 9
121
79
Prog. Pulse Gen. 10
122
7A
ICR53
Prog. Pulse Gen. 11
123
7B
Prog. Pulse Gen. 12
124
7C
ICR54
0x224
0x000FFE24
102
0x220
0x000FFE20
103
0x21C
0x000FFE1C
104
0x218
0x000FFE18
105
0x214
0x000FFE14
106
0x210
0x000FFE10
107
0x20C
0x000FFE0C
108
0x473
0x474
0x475
0x476
Prog. Pulse Gen. 13
125
7D
0x208
0x000FFE08
109
Prog. Pulse Gen. 14
126
7E
0x204
0x000FFE04
110
0x200
0x000FFE00
111
0x1FC
0x000FFDFC
0x1F8
0x000FFDF8
0x1F4
0x000FFDF4
0x1F0
0x000FFDF0
0x1EC
0x000FFDEC
0x1E8
0x000FFDE8
0x1E4
0x000FFDE4
0x1E0
0x000FFDE0
0x1DC
0x000FFDDC
0x1D8
0x000FFDD8
0x1D4
0x000FFDD4
ICR55
Prog. Pulse Gen. 15
127
7F
Up/Down Counter 0
128
80
ICR56
Up/Down
reserved Counter 1
129
81
Up/Down Counter 2
130
82
ICR57
Up/Down Counter 3
131
83
Real Time Clock
132
84
ICR58
Calibration Unit
133
85
A/D Converter 0
134
86
ICR59
-
135
87
Alarm Comparator 0
136
88
ICR60
Alarm
Comparator 1
reserved
137
89
Low Voltage Detection
138
8A
Fujitsu Microelectronics Europe GmbH
ICR61
0x477
0x478
0x479
0x47A
14, 112
0x47B
0x47C
0x47D
Page 45 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
SMC Comparator 0-5
139
8B
Timebase Overflow
140
8C
ICR62
PLL Clock Gear
141
8D
DMA Controller
142
8E
ICR63
0x1D0
0x000FFDD0
0x1CC
0x000FFDCC
0x1C8
0x000FFDC8
0x1C4
0x000FFDC4
0x1C0
0x000FFDC0
0x47E
0x47F
Main/Sub OSC stability wait
143
8F
Security vector
144
90
-
-
0x1BC
0x000FFDBC
Used by the INT
instruction.
145
to
255
91
to
FF
-
-
0x1B8
to
0x000
0x000FFDB8
to
0x000FFC00
Notes:
*1
The ICRs are located in the interrupt controller and set the interrupt level for each interrupt request.
An ICR is provided for each interrupt request.
*2
The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset
to the table base register value (TBR). The TBR specifies the top of the EIT vector table. The
addresses listed in the table are for the default TBR value (0x000FFC00). The TBR is initialized to this
value by a reset. After execution of the internal boot ROM TBR is set to 0x000FFC00.
*3
Used by REALOS
*4
ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0x0C03 : IOS[0])
*5
System reserved
*6
Memory Protection Unit (MPU) support
Fujitsu Microelectronics Europe GmbH
Page 46 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
6 I/O Map
This section shows the association between memory space and each register of peripheral
resources.
• Table convention
Address
000000H
Address offset/Register name
+0
+1
+2
PDRD[R/W]
PDR2[R/W]
PDR1[R/W]
xxxxxxxx
xxxxxxxx
xxxxxxxx
+3
PDR3[R/W]
xxxxxxxx
MSB
Block
T-unit
Port data register
LSB
Read/Write attribute (R: Read, W: Write)
Register initial value ("0", "1", "X" : undefined, "-" : not implemented)
Register name (First column register is 4n address,
Second column register is 4n+2 address...)
Leftmost register address
(For Word access, first register becomes MSB side of the data.)
Note :
Bit value of register shows initial values as follows.
•"1": Initial value is "1".
• "0": Initial value is "0".
• "X": Initial value is indeterminate.
• "-": No physical register exists in the position.
Do not use other data access attributes to access data.
Fujitsu Microelectronics Europe GmbH
Page 47 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
Block
+0
+1
+2
+3
000000H
res
res
PDR02 [R/W]
XXXXXXXX
res
000004H
res
res
res
res
000008H
res
res
res
res.
00000CH
res.
res
PDR14 [R/W]
XXXXXXXX
PDR15 [R/W]
- - - - XXXX
000010H
PDR16 [R/W]
XXXXXXXX
PDR17 [R/W]
XXXX - - - -
PDR18 [R/W]
- XXX - XXX
PDR19 [R/W]
- XXX - XXX
000014H
PDR20 [R/W]
- - - - - XXX
res.
PDR22 [R/W]
- - XX - X - X
PDR23 [R/W]
- XXXXXXX
000018H
PDR24 [R/W]
XXXXXXXX
PDR25 [R/W]
XXXXXXXX
PDR26 [R/W]
XXXXXXXX
PDR27 [R/W]
XXXXXXXX
00001CH
PDR28 {R/W}
- -XXXXX
PDR29 [R/W]
XXXXXXXX
res.
res.
000020H
00002CH
R-bus
Port Data
Register
reserved
000030H
EIRR0 [R/W]
XXXXXXXX
ENIR0 [R/W]
00000000
ELVR0 [R/W]
00000000 00000000
Ext. INT 0-7
NMI
000034H
EIRR1 [R/W]
XXXXXXXX
ENIR1 [R/W]
00000000
ELVR1 [R/W]
00000000 00000000
Ext. INT 8-15
000038H
DICR [R/W]
-------0
HRCL [R/W]
0 - - 11111
res.
DLYI/I-unit
00003CH
00004CH
000050H
000054H
reserved
SCR02 [R/W,W]
00000000
SMR02 [R/W,W]
00000000
ESCR02 [R/W]
00000X00
ECCR02
[R/W,R,W]
-00000XX
Fujitsu Microelectronics Europe GmbH
RDR02/TDR02
[R/W]
00000000
SSR02 [R/W,R]
00001000
USART (LIN)
2
res.
Page 48 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
+1
000058H
00005CH
Block
+2
+3
reserved
000060H
SCR04 [R/W,W]
00000000
SMR04 [R/W,W]
00000000
SSR04 [R/W,R]
00001000
RDR04/TDR04
[R/W]
00000000
000064H
ESCR04 [R/W]
00000X00
ECCR04
[R/W,R,W]
-00000XX
FSR04 [R]
- - - 00000
FCR04 [R/W]
0001 - 000
000068H
SCR05 [R/W,W]
00000000
SMR05 [R/W,W]
00000000
SSR05 [R/W,R]
00001000
RDR05/TDR05
[R/W]
00000000
00006CH
ESCR05 [R/W]
00000X00
ECCR05
[R/W,R,W]
-00000XX
FSR05 [R]
- - - 00000
FCR05 [R/W]
0001 - 000
000070H
SCR06 [R/W,W]
00000000
SMR06 [R/W,W]
00000000
SSR06 [R/W,R]
00001000
RDR06/TDR06
[R/W]
00000000
000074H
ESCR06 [R/W]
00000X00
ECCR06
[R/W,R,W]
-00000XX
FSR06 [R]
- - - 00000
FCR06 [R/W]
0001 - 000
000078H
SCR07 [R/W,W]
00000000
SMR07 [R/W,W]
00000000
SSR07 [R/W,R]
00001000
RDR07/TDR07
[R/W]
00000000
00007CH
ESCR07 [R/W]
00000X00
ECCR07
[R/W,R,W]
-00000XX
FSR07 [R]
- - - 00000
FCR07 [R/W]
0001 - 000
000080H
USART (LIN)
5
with FIFO
USART (LIN)
6
with FIFO
USART (LIN)
7
with FIFO
reserved
000084H
BGR102 [R/W]
00000000
BGR002 [R/W]
00000000
res.
res.
000088H
BGR104 [R/W]
00000000
BGR004 [R/W]
00000000
BGR105 [R/W]
00000000
BGR005 [R/W]
00000000
00008CH
BGR106 [R/W]
00000000
BGR006 [R/W]
00000000
BGR107 [R/W]
00000000
BGR007 [R/W]
00000000
000090H
USART (LIN)
4
with FIFO
PWC20 [R/W]
- - - - - - XX XXXXXXXX
Baudrate
Generator
USART (LIN)
0-7
PWC10 [R/W]
- - - - - - XX XXXXXXXX
Stepper Motor 0
000094H
res.
res.
Fujitsu Microelectronics Europe GmbH
PWS20 [R/W]
-0000000
PWS10 [R/W]
- -000000
Page 49 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
000098H
+1
Block
+2
PWC21 [R/W]
- - - - - - XX XXXXXXXX
+3
PWC11 [R/W]
- - - - - - XX XXXXXXXX
Stepper Motor 1
00009CH
res.
0000A0H
PWC22 [R/W]
- - - - - - XX XXXXXXXX
PWS21 [R/W]
-0000000
res.
PWS11 [R/W]
- -000000
PWC12 [R/W]
- - - - - - XX XXXXXXXX
Stepper Motor 2
0000A4H
res.
0000A8H
PWC23 [R/W]
- - - - - - XX XXXXXXXX
PWS22 [R/W]
-0000000
res.
PWS12 [R/W]
- -000000
PWC13 [R/W]
- - - - - - XX XXXXXXXX
Stepper Motor 3
0000ACH
res.
0000B0H
PWC24 [R/W]
- - - - - - XX XXXXXXXX
PWS23 [R/W]
-0000000
res.
0000B4H
res.
0000B8H
PWC25 [R/W]
- - - - - - XX XXXXXXXX
PWS13 [R/W]
- -000000
PWC14 [R/W]
- - - - - - XX XXXXXXXX
PWS24 [R/W]
-0000000
res.
Stepper Motor 4
PWS14 [R/W]
- -000000
PWC15 [R/W]
- - - - - - XX XXXXXXXX
Stepper Motor 5
0000BCH
res.
res.
PWS25 [R/W]
-0000000
0000C0H
res.
PWC0 [R/W]
-00000--
res.
PWS15 [R/W]
- -000000
PWC1 [R/W]
-00000--
0000C4H
res.
PWC2 [R/W]
-00000--
res.
PWC3 [R/W]
-00000--
0000C8H
res.
PWC4 [R/W]
-00000--
res.
PWC5 [R/W]
-00000--
0000CCH
Fujitsu Microelectronics Europe GmbH
Stepper Motor
Control
0-5
reserved
Page 50 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
Block
+0
+1
+2
+3
0000D0H
IBCR0 [R/W]
00000000
IBSR0 [R]
00000000
ITBAH0 [R/W]
- - - - - - 00
ITBAL0 [R/W]
00000000
0000D4H
ITMKH0 [R/W]
00 - - - - 11
ITMKL0 [R/W]
11111111
ISMK0 [R/W]
01111111
ISBA0 [R/W]
- 0000000
0000D8H
res.
IDAR0 [R/W]
00000000
ICCR0 [R/W]
- 0011111
res.
0000DCH
000100H
I2C 0
reserved
000104H
GCN11 [R/W]
00110010 00010000
res.
GCN21 [R/W]
- - - - 0000
PPG Control
4-7
000108H
GCN12 [R/W]
00110010 00010000
res.
GCN22 [R/W]
- - - - 0000
PPG Control
8-11
000110H
00012CH
000130H
reserved
PTMR04 [R]
11111111 11111111
PCSR04 [W]
XXXXXXXX XXXXXXXX
PPG 4
000134H
PDUT04 [W]
XXXXXXXX XXXXXXXX
000138H
PTMR05 [R]
11111111 11111111
00013CH
PDUT05 [W]
XXXXXXXX XXXXXXXX
000140H
PTMR06 [R]
11111111 11111111
000144H
PDUT06 [W]
XXXXXXXX XXXXXXXX
000148H
PTMR07 [R]
11111111 11111111
00014CH
PDUT07 [W]
XXXXXXXX XXXXXXXX
PCNH04 [R/W]
0000000 -
PCNL04 [R/W]
000000 - 0
PCSR05 [W]
XXXXXXXX XXXXXXXX
PPG 5
PCNH05 [R/W]
0000000 -
PCNL05 [R/W]
000000 - 0
PCSR06 [W]
XXXXXXXX XXXXXXXX
PPG 6
PCNH06 [R/W]
0000000 -
PCNL06 [R/W]
000000 - 0
PCSR07 [W]
XXXXXXXX XXXXXXXX
PPG 7
Fujitsu Microelectronics Europe GmbH
PCNH07 [R/W]
0000000 -
PCNL07 [R/W]
000000 - 0
Page 51 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
+1
000150H
PTMR08 [R]
11111111 11111111
000154H
PDUT08 [W]
XXXXXXXX XXXXXXXX
000158H
PTMR09 [R]
11111111 11111111
00015CH
PDUT09 [W]
XXXXXXXX XXXXXXXX
000160H
PTMR10 [R]
11111111 11111111
000164H
PDUT10 [W]
XXXXXXXX XXXXXXXX
000168H
PTMR11 [R]
11111111 11111111
00016CH
PDUT11 [W]
XXXXXXXX XXXXXXXX
Block
+2
+3
PCSR08 [W]
XXXXXXXX XXXXXXXX
PCNH08 [R/W]
0000000 -
PPG 8
PCNL08 [R/W]
000000 - 0
PCSR09 [W]
XXXXXXXX XXXXXXXX
PPG 9
PCNH09 [R/W]
0000000 -
PCNL09 [R/W]
000000 - 0
PCSR10 [W]
XXXXXXXX XXXXXXXX
PPG 10
PCNH10 [R/W]
0000000 -
PCNL10 [R/W]
000000 - 0
PCSR11 [W]
XXXXXXXX XXXXXXXX
PPG 11
000170H
P0TMCSRH
[R/W]
- 0000000
P0TMCSRL
[R/W]
01000000
PCNH11 [R/W]
0000000 -
PCNL11 [R/W]
000000 - 0
P1TMCSRH
[R/W]
- 0000000
P1TMCSRL
[R/W]
01000000
000174H
P0TMRLR [W]
XXXXXXXX XXXXXXXX
P0TMR [R]
XXXXXXXX XXXXXXXX
000178H
P1TMRLR [W]
XXXXXXXX XXXXXXXX
P1TMR [R]
XXXXXXXX XXXXXXXX
00017CH
Pulse
Frequency
Modulator
reserved
ICS01 [R/W]
00000000
res.
000184H
IPCP0 [R]
XXXXXXXX XXXXXXXX
IPCP1 [R]
XXXXXXXX XXXXXXXX
000188H
IPCP2 [R]
XXXXXXXX XXXXXXXX
IPCP3 [R]
XXXXXXXX XXXXXXXX
Fujitsu Microelectronics Europe GmbH
res.
ICS23 [R/W]
00000000
000180H
Input
Capture
0-3
Page 52 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
+1
Block
+2
+3
00018CH
OCS01 [R/W]
- - - 0 - - 00 0000 - - 00
OCS23 [R/W]
- - - 0 - - 00 0000 - - 00
000190H
OCCP0 [R/W]
XXXXXXXX XXXXXXXX
OCCP1 [R/W]
XXXXXXXX XXXXXXXX
000194H
OCCP2 [R/W]
XXXXXXXX XXXXXXXX
OCCP3 [R/W]
XXXXXXXX XXXXXXXX
000198H
00019CH
0001A0H
SGCRH [R/W]
0000 - - 00
SGCRL [R/W]
- - 0 - - 000
SGAR [R/W]
00000000
res.
SGFR [R/W, R]
XXXXXXXX XXXXXXXX
SGTR [R/W]
XXXXXXXX
ADERH [R/W]
00000000 00000000
SGDR [R/W]
XXXXXXXX
Output
Compare
0-3
Sound
Generator
ADERL [R/W]
00000000 00000000
0001A4
ADCS1 [R/W]
00000000
ADCS0 [R/W]
00000000
ADCR1 [R]
000000XX
ADCR0 [R]
XXXXXXXX
0001A8H
ADCT1 [R/W]
00010000
ADCT0 [R/W]
00101100
ADSCH [R/W]
- - - 00000
ADECH [R/W]
- - - 00000
0001ACH
res.
ACSR0 [R/W]
- 11XXX00
res.
res.
A/D
Converter
Alarm
Comparator 0
0001B0H
reserved
0001BCH
0001C0H
TMRLR2 [W]
XXXXXXXX XXXXXXXX
0001C4H
res.
0001C8H
TMRLR3 [W]
XXXXXXXX XXXXXXXX
0001CCH
res.
Fujitsu Microelectronics Europe GmbH
TMR2 [R]
XXXXXXXX XXXXXXXX
TMCSRH2
[R/W]
- - - 00000
TMCSRL2
[R/W]
0 - 000000
TMR3 [R]
XXXXXXXX XXXXXXXX
TMCSRH3
[R/W]
- - - 00000
TMCSRL3
[R/W]
0 - 000000
Reload Timer 2
(PPG 4-5)
Reload Timer 3
(PPG 6-7)
Page 53 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
+1
Block
+2
+3
0001D0H
TMRLR4 [W]
XXXXXXXX XXXXXXXX
TMR4 [R]
XXXXXXXX XXXXXXXX
0001D4H
res.
0001D8H
TMRLR5 [W]
XXXXXXXX XXXXXXXX
0001DCH
res.
0001E0H
TMRLR6 [W]
XXXXXXXX XXXXXXXX
0001E4H
res.
0001E8H
TMRLR7 [W]
XXXXXXXX XXXXXXXX
0001ECH
res.
TMCSRH7
[R/W]
- - - 00000
TMCSRL7
[R/W]
0 - 000000
0001F0H
TCDT0 [R/W]
XXXXXXXX XXXXXXXX
res.
TCCS0 [R/W]
00000000
TMCSRH4
[R/W]
- - - 00000
TMCSRL4
[R/W]
0 - 000000
TMR5 [R]
XXXXXXXX XXXXXXXX
TMCSRH5
[R/W]
- - - 00000
TMCSRL5
[R/W]
0 - 000000
TMR6 [R]
XXXXXXXX XXXXXXXX
TMCSRH6
[R/W]
- - - 00000
TMCSRL6
[R/W]
0 - 000000
TMR7 [R]
XXXXXXXX XXXXXXXX
Reload Timer 4
(PPG 8-9)
Reload Timer 5
(PPG 10-11)
Reload Timer 6
(PPG 12-13)
Reload Timer 7
(PPG 14-15)
(ADC)
Free Running
Timer 0
(ICU 0-1)
0001F4H
TCDT1 [R/W]
XXXXXXXX XXXXXXXX
res.
TCCS1 [R/W]
00000000
Free Running
Timer 1
(ICU 2-3)
0001F8H
TCDT2 [R/W]
XXXXXXXX XXXXXXXX
res.
TCCS2 [R/W]
00000000
Free Running
Timer 2
(OCU 0-1)
0001FCH
TCDT3 [R/W]
XXXXXXXX XXXXXXXX
res.
TCCS3 [R/W]
00000000
Free Running
Timer 3
(OCU 2-3)
Fujitsu Microelectronics Europe GmbH
Page 54 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
+1
Block
+2
000200H
DMACA0 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
00023CH
reserved
000240H
DMACR [R/W]
0 - -0 0000
+3
DMAC
reserved
000244H
-
reserved
0002CCH
Fujitsu Microelectronics Europe GmbH
Page 55 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
Block
+0
+1
+2
+3
0002D0H
res.
ICS045 [R/W]
00000000
res.
ICS67 [R/W]
00000000
0002D4H
IPCP4 [R]
XXXXXXXX XXXXXXXX
IPCP5 [R]
XXXXXXXX XXXXXXXX
0002D8H
IPCP6 [R]
XXXXXXXX XXXXXXXX
IPCP7 [R]
XXXXXXXX XXXXXXXX
0002DCH
0002ECH
0002F0H
Input
Capture
4-7
reserved
TCDT4 [R/W]
XXXXXXXX XXXXXXXX
res.
TCCS4 [R/W]
00000000
Free Running
Timer 4
(ICU 4-5)
0002F4H
TCDT5 [R/W]
XXXXXXXX XXXXXXXX
res.
TCCS5 [R/W]
00000000
Free Running
Timer 5
(ICU 6-7)
0002F8H
TCDT6 [R/W]
XXXXXXXX XXXXXXXX
res.
TCCS6 [R/W]
00000000
Free Running
Timer 6
0002FCH
TCDT7 [R/W]
XXXXXXXX XXXXXXXX
res.
TCCS7 [R/W]
00000000
Free Running
Timer 7
000300H
UDRC1 [W]
00000000
UDRC0 [W]
00000000
UDCR1 [R]
00000000
UDCR0 [R]
00000000
000304H
UDCCH0 [R/W]
00000000
UDCCL0 [R/W]
00000000
res.
UDCS0 [R/W]
00000000
UDCR3 [R]
00000000
UDCR2 [R]
00000000
Up/Down
Counter
0
000308H
-
reserved
00030CH
000310H
UDRC3 [W]
00000000
UDRC2 [W]
00000000
000314H
UDCCH2 [R/W]
00000000
UDCCL2 [R/W]
00000000
res.
UDCS2 [R/W]
00000000
000318H
UDCCH3 [R/W]
00000000
UDCCL3 [R/W]
00000000
res.
UDCS3 [R/W]
00000000
00031CH
Fujitsu Microelectronics Europe GmbH
Up/Down
Counter
2-3
reserved
Page 56 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
000320H
+1
GCN13 [R/W]
00110010 00010000
000324H
00032CH
000330H
Block
+2
+3
res.
GCN23 [R/W]
- - - - 0000
PPG Control
12-15
reserved
PTMR12 [R]
11111111 11111111
PCSR12 [W]
XXXXXXXX XXXXXXXX
PPG 12
000334H
PDUT12 [W]
XXXXXXXX XXXXXXXX
000338H
PTMR13 [R]
11111111 11111111
00033CH
PDUT13 [W]
XXXXXXXX XXXXXXXX
000340H
PTMR14 [R]
11111111 11111111
PCNH12 [R/W]
0000000 -
PCNL12 [R/W]
000000 - 0
PCSR13 [W]
XXXXXXXX XXXXXXXX
PPG 13
PCNH13 [R/W]
0000000 -
PCNL13 [R/W]
000000 - 0
PCSR14 [W]
XXXXXXXX XXXXXXXX
PPG 14
000344H
PDUT14 [W]
XXXXXXXX XXXXXXXX
000348H
PTMR15 [R]
11111111 11111111
00034CH
PDUT15 [W]
XXXXXXXX XXXXXXXX
PCNH14 [R/W]
0000000 -
PCNL14 [R/W]
000000 - 0
PCSR15 [W]
XXXXXXXX XXXXXXXX
PPG 15
000350H
000364H
PCNH15 [R/W]
0000000 -
PCNL15 [R/W]
000000 - 0
reserved
000368H
IBCR2 [R/W]
00000000
IBSR2 [R]
00000000
ITBAH2 [R/W]
- - - - - - 00
ITBAL2 [R/W]
00000000
00036CH
ITMKH2 [R/W]
00 - - - - 11
ITMKL2 [R/W]
11111111
ISMK2 [R/W]
01111111
ISBA2 [R/W]
- 0000000
000370H
res.
IDAR2 [R/W]
00000000
ICCR2 [R/W]
- 0011111
res.
Fujitsu Microelectronics Europe GmbH
I2C 2
Page 57 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
Block
+0
+1
+2
+3
00374H
IBCR3 [R/W]
00000000
IBSR3 [R]
00000000
ITBAH3 [R/W]
- - - - - - 00
ITBAL3 [R/W]
00000000
000378H
ITMKH3 [R/W]
00 - - - - 11
ITMKL3 [R/W]
11111111
ISMK3 [R/W]
01111111
ISBA3 [R/W]
- 0000000
00037CH
res.
IDAR3 [R/W]
00000000
ICCR3 [R/W]
- 0011111
res.
000380H
00038CH
000390H
I2C 3
reserved
ROMS [R]
11111111 00000000
res.
000394H
0003ECH
reserved
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H
00043CH
reserved
Fujitsu Microelectronics Europe GmbH
ROM Select
Register
Bit Search
Module
Page 58 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
Block
+0
+1
+2
+3
000440H
ICR00 [R/W]
---11111
ICR01 [R/W]
---11111
ICR02 [R/W]
---11111
ICR03 [R/W]
---11111
000444H
ICR04 [R/W]
---11111
ICR05 [R/W]
---11111
ICR06 [R/W]
---11111
ICR07 [R/W]
---11111
000448H
ICR08 [R/W]
---11111
ICR09 [R/W]
---11111
ICR10 [R/W]
---11111
ICR11 [R/W]
---11111
00044CH
ICR12 [R/W]
---11111
ICR13 [R/W]
---11111
ICR14 [R/W]
---11111
ICR15 [R/W]
---11111
000450H
ICR16 [R/W]
---11111
ICR17 [R/W]
---11111
ICR18 [R/W]
---11111
ICR19 [R/W]
---11111
000454H
ICR20 [R/W]
---11111
ICR21 [R/W]
---11111
ICR22 [R/W]
---11111
ICR23 [R/W]
---11111
000458H
ICR24 [R/W]
---11111
ICR25 [R/W]
---11111
ICR26 [R/W]
---11111
ICR27 [R/W]
---11111
00045CH
ICR28 [R/W]
---11111
ICR29 [R/W]
---11111
ICR30 [R/W]
---11111
ICR31 [R/W]
---11111
000460H
ICR32 [R/W]
---11111
ICR33 [R/W]
---11111
ICR34 [R/W]
---11111
ICR35 [R/W]
---11111
000464H
ICR36 [R/W]
---11111
ICR37 [R/W]
---11111
ICR38 [R/W]
---11111
ICR39 [R/W]
---11111
000468H
ICR40 [R/W]
---11111
ICR41 [R/W]
---11111
ICR42 [R/W]
---11111
ICR43 [R/W]
---11111
00046CH
ICR44 [R/W]
---11111
ICR45 [R/W]
---11111
ICR46 [R/W]
---11111
ICR47 [R/W]
---11111
000470H
ICR48 [R/W]
---11111
ICR49 [R/W]
---11111
ICR50 [R/W]
---11111
ICR51 [R/W]
---11111
000474H
ICR52 [R/W]
---11111
ICR53 [R/W]
---11111
ICR54 [R/W]
---11111
ICR55 [R/W]
---11111
000478H
ICR56 [R/W]
---11111
ICR57 [R/W]
---11111
ICR58 [R/W]
---11111
ICR59 [R/W]
---11111
00047CH
ICR60 [R/W]
---11111
ICR61 [R/W]
---11111
ICR62 [R/W]
---11111
ICR63 [R/W]
---11111
Fujitsu Microelectronics Europe GmbH
Interrupt
Control
Unit
Page 59 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
Block
+0
+1
+2
+3
000480H
RSRR [R/W]
10000000
STCR [R/W]
00110011
TBCR [R/W]
00XXX – 00
CTBR [W]
XXXXXXXX
000484H
CLKR [R/W]
---- 0000
WPR [W]
XXXXXXXX
DIVR0 [R/W]
00000011
DIVR1 [R/W]
00000000
000488H
CTEST [R/W]
XXXX00XX
res.
res.
res.
00048CH
PLLDIVM [R/W]
- - - 00000
PLLDIVN [R/W]
- - - 00000
PLLDIVG [R/W]
- - - 00000
PLLDIVG [W]
00000000
000490H
PLLCTRL [R/W]
- - - - 0000
res.
res.
res.
OSCC1 [R/W]
- - - - - 010
OSCS1 [R/W]
00001111
OSCC2 [R/W]
- - - - - 010
OSCS2 [R/W]
00001111
PORTEN [R/W]
- - - - - - 00
res.
res.
res.
000494H
000498H
00049CH
C-Unit Test
(hidden)
PLL Clock
Gear Unit
Main/Sub
Oscillator
Control
Port Input
Enable Control
reserved
WTCER [R/W]
- - - - - - 00
WTCR [R/W]
00000000 000 – 00 – 0
0004A0H
res.
0004A4H
res.
0004A8H
WTHR [R/W]
- - - 00000
WTMR [R/W]
- - 000000
WTSR [R/W]
- - 000000
res.
0004ACH
CSVTR [R/W]
- - - 00010
CSVCR [R/W]
00011100
CSCFG [R/W]
0X000000
CMCFG [R/W]
00000000
WTBR [R/W]
- - - XXXXX XXXXXXXX XXXXXXXX
0004B0H
CUCR [R/W]
- - - - - - - - - - - 0 - - 00
CUTD [R/W]
10000000 00000000
0004B4H
CUTR1 [R]
- - - - - - - - 00000000
CUTR2 [R]
00000000 00000000
0004B8H
CMPR [R/W]
- - 000010 11111101
0004BCH
Clock
Control
Unit
CMT1 [R/W]
00000000 1 - - - 0000
Fujitsu Microelectronics Europe GmbH
res.
CMCR [R/W]
- 001 - - 00
CMT2 [R/W]
- - 000000 - - 000000
Real Time
Clock
(Watch Timer)
ClockSupervisor /
Selector /
Monitor
Calibration Unit
of Sub
Oscillation
Clock
Modulation
Page 60 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
Block
+0
+1
+2
+3
0004C0H
CANPRE [R/W]
0 - - - 0000
CANCKD [R/W]
5
- - - - - 000
res.
res.
CAN Clock
Control
0004C4H
LVSEL [R/W]
00000111
LVDET [R/W]
0000 0 – 00
HWWDE [R/W]
- - - - - - 00
HWWD [R/W,W]
00011000
LV Detection/
HardwareWatchdog
0004C8H
OSCRH [R/W]
000 - - 001
OSCRL [R/W]
- - - - - 000
WPCRH [R/W]
00 - - - 000
WPCRL [R/W]
- - - - - - 00
Main-/SubOscillation
Stabilisation
Timer
REGCTR [R/W]
- - - 0 - - 00
MainOscillation
Standby Control
Main/Sub
Regulator
Control
res.
res.
Mode Register
res.
IOS [R/W]
00000000
I-Unit Test
(hidden)
0004CCH
OSCCR [R/W]
- - - - - - 00
res.
REGSEL [R/W]
- - 000110
0004D0H
-
reserved
0007F8H
0007FCH
res.
MODR [W]
XXXXXXXX
000800H
-
reserved
000BFCH
000C00H
TVCTW [W]
XXXXXXXX
TVCTR [R]
- - XXXXXX
000C04H
-
reserved
000CFCH
5
depends on the number of available CAN channels
Fujitsu Microelectronics Europe GmbH
Page 61 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
Block
+0
+1
+2
+3
000D00H
res
res
PDRD02 [R]
XXXXXXXX
res
000D04H
res
res
res
res
000D08H
res
res
res
res.
000D0CH
res.
res
PDRD14 [R]
XXXXXXXX
PDRD15 [R]
- - - - XXXX
000D10H
PDRD16 [R]
XXXXXXXX
PDRD17 [R]
XXXX - - - -
PDRD18 [R]
- XXX - XXX
PDRD19 [R]
- XXX - XXX
000D14H
PDRD20 [R]
- - - - - XXX
res.
PDRD22 [R]
- - XX - X - X
PDRD23 [R]
- XXXXXXX
000D18H
PDRD24 [R]
XXXXXXXX
PDRD25 [R]
XXXXXXXX
PDRD26 [R]
XXXXXXXX
PDRD27 [R]
XXXXXXXX
000D1CH
PDRD28 [R]
- - XXXXX
PDRD29 [R]
XXXXXXXX
res.
res.
000D20H
000D3CH
R-bus
Port Data
Direct Read
Register
reserved
000D40H
res
res
DDR02 [R/W]
00000000
res
000D44H
res
res
res
res
000D48H
res
res
res
res.
000D4CH
res.
res
DDR14 [R/W]
00000000
DDR15 [R/W]
- - - - 0000
000D50H
DDR16 [R/W]
00000000
DDR17 [R/W]
0000 - - - -
DDR18 [R/W]
- 000 - 000
DDR19 [R/W]
- 000 - 000
000D54H
DDR20 [R/W]
- - - - - 000
res.
DDR22 [R/W]
- - 00 - 0 - 0
DDR23 [R/W]
- 0000000
000D58H
DDR24 [R/W]
00000000
DDR25 [R/W]
00000000
DDR26 [R/W]
00000000
DDR27 [R/W]
00000000
000D5CH
DDR28 [R/W]
- - 00000
DDR29 [R/W]
00000000
res.
res.
R-bus
Port Direction
Register
000D60H
000D7CH
Fujitsu Microelectronics Europe GmbH
reserved
Page 62 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
Block
+0
+1
+2
+3
000D80H
res
res
PFR02 [R/W]
--------
res
000D84H
res
res
res
res
000D88H
res
res
res
res.
000D8CH
res.
res
PFR14 [R/W]
00000000
PFR15 [R/W]
- - - - 0000
000D90H
PFR16 [R/W]
00000000
PFR17 [R/W]
0000 - - - -
PFR18 [R/W]
- 000 - 000
PFR19 [R/W]
- 000 - 000
000D94H
PFR20 [R/W]
- - - - - 000
res.
PFR22 [R/W]
- - 00 - 0 - 0
PFR23 [R/W]
- 000000
000D98H
PFR24 [R/W]
00000000
PFR25 [R/W]
00000000
PFR26 [R/W]
00000000
PFR27 [R/W]
00000000
000D9CH
PFR28 [R/w]
- - 00000
PFR29 [R/W]
00000000
res.
res.
R-bus
Port Function
Register
000DA0H
-
reserved
000DBCH
000DC0H
res
res
EPFR02 [R/W]
--------
res
000DC4H
res
res
res
res
000DC8H
res
res
res
res.
000DCCH
res.
res
EPFR14 [R/W]
00000000
EPFR15 [R/W]
- - - - 0000
000DD0H
EPFR16 [R/W]
0000 - - - -
EPFR17 [R/W]
--------
EPFR18 [R/W]
- 00 - - 00 -
EPFR19 [R/W]
-0---0--
000DD4H
EPFR20 [R/W]
- - - - - 00 -
res.
EPFR22 [R/W]
--------
EPFR23 [R/W]
--------
000DD8H
EPFR24 [R/W]
--------
EPFR25 [R/W]
--------
EPFR26 [R/W]
00000000
EPFR27 [R/W]
00000000
000DDCH
EPFR28 [R/w]
--------
EPFR29 [R/W]
--------
res.
res.
000DE0H
000DFCH
Fujitsu Microelectronics Europe GmbH
R-bus Port
Extra Function
Register
reserved
Page 63 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
Block
+0
+1
+2
+3
000E00H
res
res
PODR02 [R/W]
00000000
res
000E04H
res
res
res
res
000E08H
res
res
res
res.
000E0CH
res.
res
PODR14 [R/W]
00000000
PODR15 [R/W]
- - - - 0000
000E10H
PODR16 [R/W]
00000000
PODR17 [R/W]
0000 - - - -
PODR18 [R/W]
- 000 - 000
PODR19 [R/W]
- 000 - 000
000E14H
PODR20 [R/W]
- - - - - 000
res.
PODR22 [R/W]
- - 00 - 0 - 0
PODR23 [R/W]
- 0000000
000E18H
PODR24 [R/W]
00000000
PODR25 [R/W]
00000000
PODR26 [R/W]
00000000
PODR27 [R/W]
00000000
000E1CH
PODR28 [R/W]
- - 00000
PODR29 [R/W]
00000000
res.
res.
R-bus Port
Output Drive
Select
Register
000E20H
-
reserved
000E3CH
000E40H
res
res
PILR02 [R/W]
00000000
res
000E44H
res
res
res
res
000E48H
res
res
res
res.
000E4CH
res.
res
PILR14 [R/W]
00000000
PILR15 [R/W]
- - - - 0000
000E50H
PILR16 [R/W]
00000000
PILR17 [R/W]
0000 - - - -
PILR18 [R/W]
- 000 - 000
PILR19 [R/W]
- 000 - 000
PILR20 [R/W]
- - - - - 000
res.
PILR22 [R/W]
- - 00 - 0 - 0
PILR23 [R/W]
- 0000000
000E58H
PILR24 [R/W]
00000000
PILR25 [R/W]
00000000
PILR26 [R/W]
00000000
PILR27 [R/W]
00000000
000E5CH
PILR28 [R/W]
- - 000000
PILR29 [R/W]
00000000
res.
res.
000E54H
000E60H
000E7CH
Fujitsu Microelectronics Europe GmbH
R-bus Port
Input Level
Select
Register
reserved
Page 64 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
Block
+0
+1
+2
+3
000E80H
res
res
EPILR02 [R/W]
00000000
res
000E84H
res
res
res
res
000E88H
res
res
res
res.
000E8CH
res.
res
EPILR14 [R/W]
00000000
EPILR15 [R/W]
- - - - 0000
000E90H
EPILR16 [R/W]
00000000
EPILR17 [R/W]
0000 - - - -
EPILR18 [R/W]
- 000 - 000
EPILR19 [R/W]
- 000 - 000
000E94H
EPILR20 [R/W]
- - - - - 000
res.
EPILR22 [R/W]
- - 00 - 0 - 0
EPILR23 [R/W]
- 0000000
000E98H
EPILR24 [R/W]
00000000
EPILR25 [R/W]
00000000
EPILR26 [R/W]
00000000
EPILR27 [R/W]
00000000
000E9CH
EPILR28 [R/W]
- - 00000
EPILR29 [R/W]
00000000
res.
res.
R-bus Port
Extra Input
Level Select
Register
000EA0H
-
reserved
000EBCH
000EC0H
res
res
PPER02 [R/W]
00000000
res
000EC4H
res
res
res
res
000EC8H
res
res
res
res.
000ECCH
res.
res
PPER14 [R/W]
00000000
PPER15 [R/W]
- - - - 0000
000ED0H
PPER16 [R/W]
00000000
PPER17 [R/W]
0000 - - - -
PPER18 [R/W]
- 000 - 000
PPER19 [R/W]
- 000 - 000
000ED4H
PPER20 [R/W]
- - - - - 000
res.
PPER22 [R/W]
- - 00 - 0 - 0
PPER23 [R/W]
- 0000000
000ED8H
PPER24 [R/W]
00000000
PPER25 [R/W]
00000000
PPER26 [R/W]
00000000
PPER27 [R/W]
00000000
000EDCH
PPER28 [R/W]
- - 00000
PPER29 [R/W]
00000000
res.
res.
000EE0H
000EFCH
Fujitsu Microelectronics Europe GmbH
R-bus Port
Pull-Up/Down
Enable
Register
reserved
Page 65 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
Block
+0
+1
+2
+3
000F00H
res
res
PPCR02 [R/W]
11111111
res
000F04H
res
res
res
res
000F08H
res
res
res
res.
000F0CH
res.
res
PPCR14 [R/W]
11111111
PPCR15 [R/W]
- - - - 1111
000F10H
PPCR16 [R/W]
11111111
PPCR17 [R/W]
1111 - - - -
PPCR18 [R/W]
- 111 - 111
PPCR19 [R/W]
- 111 - 111
000F14H
PPCR20 [R/W]
- - - - - 111
res.
PPCR22 [R/W]
- - 11 - 1 - 1
PPCR23 [R/W]
-1111111
000F18H
PPCR24 [R/W]
11111111
PPCR25 [R/W]
11111111
PPCR26 [R/W]
11111111
PPCR27 [R/W]
11111111
000F1CH
PPCR28 [R/W]
- - 11111
PPCR29 [R/W]
11111111
res.
res.
R-bus Port
Pull-Up/Down
Control
Register
000F20H
-
reserved
000F3CH
Fujitsu Microelectronics Europe GmbH
Page 66 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
+1
Block
+2
001000H
DMASA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
DMAC
001014H
DMADA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
003FFCH
reserved
004000H
005FFCH
MB91F467C Instruction RAM size is 8 KB
006000H
006FFCH
reserved
007000H
007004H
007008H
FMCS [R/W]
01101000
FMCR [R]
- - - 00000
FMWT [R/W]
11111111 11111111
Instruction RAM
8 kB
FCHCR [R/W]
- - - - - - 00 10000011
FMWT2 [R]
- 001 - - - -
FMPS [R/W]
- - - - - 000
Flash Memory/
- Cache
Control
Register
FMAC [R]
00000000 00000000 00000000 00000000
Fujitsu Microelectronics Europe GmbH
Page 67 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
+1
Block
+2
+3
00700CH
FCHA0 [R/W]
- - - - - - - - - - - 00000 00000000 00000000
007010H
FCHA1 [R/W]
- - - - - - - - - - - 00000 00000000 00000000
007014H
007FFCH
reserved
008000H
00BFFCH
MB91F467C Boot-ROM size is 4kB : 00B000H – 00BFFCH
(instruction access is 1 waitcycle, data access is 1 waitcycle)
00C000H
CTRLR0 [R/W]
00000000 00000001
STATR0 [R/W]
00000000 00000000
00C004H
ERRCNT0 [R]
00000000 00000000
BTR0 [R/W]
00100011 00000001
00C008H
INTR0 [R]
00000000 00000000
TESTR0 [R/W]
00000000 X0000000
00C00CH
BRPE0 [R/W]
00000000 00000000
res.
00C010H
IF1CREQ0 [R/W]
00000000 00000001
IF1CMSK0 [R/W]
00000000 00000000
00C014H
IF1MSK20 [R/W]
11111111 11111111
IF1MSK10 [R/W]
11111111 11111111
00C018H
IF1ARB20 [R/W]
00000000 00000000
IF1ARB10 [R/W]
00000000 00000000
00C01CH
IF1MCTR0 [R/W]
00000000 00000000
res.
00C020H
IF1DTA10 [R/W]
00000000 00000000
IF1DTA20 [R/W]
00000000 00000000
00C024H
IF1DTB10 [R/W]
00000000 00000000
IF1DTB20 [R/W]
00000000 00000000
00C028H
00C02CH
I-Cache Noncacheable area
setting
Register
Boot ROM
16 kB
CAN 0
Control
Register
CAN 0
IF 1 Register
reserved
00C030H
IF1DTA20 [R/W]
00000000 00000000
IF1DTA10 [R/W]
00000000 00000000
00C034H
IF1DTB20 [R/W]
00000000 00000000
IF1DTB10 [R/W]
00000000 00000000
Fujitsu Microelectronics Europe GmbH
Page 68 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
+1
Block
+2
+3
00C038H
-
reserved
00C03CH
00C040H
IF2CREQ0 [R/W]
00000000 00000001
IF2CMSK0 [R/W]
00000000 00000000
00C044H
IF2MSK20 [R/W]
11111111 11111111
IF2MSK10 [R/W]
11111111 11111111
00C048H
IF2ARB20 [R/W]
00000000 00000000
IF2ARB10 [R/W]
00000000 00000000
00C04CH
IF2MCTR0 [R/W]
00000000 00000000
res.
00C050H
IF2DTA10 [R/W]
00000000 00000000
IF2DTA20 [R/W]
00000000 00000000
00C054H
IF2DTB10 [R/W]
00000000 00000000
IF2DTB20 [R/W]
00000000 00000000
00C058H
00C05CH
reserved
00C060H
IF2DTA20 [R/W]
00000000 00000000
IF2DTA10 [R/W]
00000000 00000000
00C064H
IF2DTB20 [R/W]
00000000 00000000
IF2DTB10 [R/W]
00000000 00000000
00C068H
00C07CH
00C080H
reserved
TREQR20 [R]
00000000 00000000
00C084H
00C08CH
00C090H
TREQR10 [R]
00000000 00000000
reserved
NEWDT20 [R]
00000000 00000000
00C094H
00C09CH
00C0A0H
CAN 0
IF 2 Register
NEWDT10 [R]
00000000 00000000
CAN 0
Status Flags
reserved
INTPND20 [R]
00000000 00000000
Fujitsu Microelectronics Europe GmbH
INTPND10 [R]
00000000 00000000
Page 69 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
+1
00C0A4H
00C0ACH
00C0B0H
Block
+2
+3
reserved
CAN 0
Status Flags
MSGVAL20 [R]
00000000 00000000
00C0B4H
00C0FCH
MSGVAL10 [R]
00000000 00000000
reserved
00C100H
CTRLR1 [R/W]
00000000 00000001
STATR1 [R/W]
00000000 00000000
00C104H
ERRCNT1 [R]
00000000 00000000
BTR1 [R/W]
00100011 00000001
00C108H
INTR1 [R]
00000000 00000000
TESTR1 [R/W]
00000000 X0000000
00C10CH
BRPE1 [R/W]
00000000 00000000
res.
00C110H
IF1CREQ1 [R/W]
00000000 00000001
IF1CMSK1 [R/W]
00000000 00000000
00C114H
IF1MSK21 [R/W]
11111111 11111111
IF1MSK11 [R/W]
11111111 11111111
00C118H
IF1ARB21 [R/W]
00000000 00000000
IF1ARB11 [R/W]
00000000 00000000
00C11CH
IF1MCTR1 [R/W]
00000000 00000000
res.
00C120H
IF1DTA11 [R/W]
00000000 00000000
IF1DTA21 [R/W]
00000000 00000000
00C124H
IF1DTB11 [R/W]
00000000 00000000
IF1DTB21 [R/W]
00000000 00000000
00C128H
00C12CH
CAN 1
Control
Register
CAN 1
IF 1 Register
reserved
00C130H
IF1DTA21 [R/W]
00000000 00000000
IF1DTA11 [R/W]
00000000 00000000
00C134H
IF1DTB21 [R/W]
00000000 00000000
IF1DTB11 [R/W]
00000000 00000000
Fujitsu Microelectronics Europe GmbH
Page 70 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
+1
00C138H
00C13CH
Block
+2
+3
reserved
00C140H
IF2CREQ1 [R/W]
00000000 00000001
IF2CMSK1 [R/W]
00000000 00000000
00C144H
IF2MSK21 [R/W]
11111111 11111111
IF2MSK11 [R/W]
11111111 11111111
00C148H
IF2ARB21 [R/W]
00000000 00000000
IF2ARB11 [R/W]
00000000 00000000
00C14CH
IF2MCTR1 [R/W]
00000000 00000000
res.
00C150H
IF2DTA11 [R/W]
00000000 00000000
IF2DTA21 [R/W]
00000000 00000000
00C154H
IF2DTB11 [R/W]
00000000 00000000
IF2DTB21 [R/W]
00000000 00000000
00C158H
00C15CH
reserved
00C160H
IF2DTA21 [R/W]
00000000 00000000
IF2DTA11 [R/W]
00000000 00000000
00C164H
IF2DTB21 [R/W]
00000000 00000000
IF2DTB11 [R/W]
00000000 00000000
00C168H
00C17CH
00C180H
reserved
TREQR21 [R]
00000000 00000000
00C184H
00C18CH
00C190H
CAN 1
IF 2 Register
TREQR11 [R]
00000000 00000000
CAN 1
Status Flags
reserved
NEWDT21 [R]
00000000 00000000
00C194H
00C19CH
Fujitsu Microelectronics Europe GmbH
NEWDT11 [R]
00000000 00000000
reserved
Page 71 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
00C1A0H
+1
00C1B0H
+2
+3
INTPND11 [R]
00000000 00000000
INTPND21 [R]
00000000 00000000
00C1A4H
00C1ACH
Block
reserved
MSGVAL21 [R]
00000000 00000000
00C1B4H
00C1FCH
MSGVAL11 [R]
00000000 00000000
reserved
00C200H
CTRLR2 [R/W]
00000000 00000001
STATR2 [R/W]
00000000 00000000
00C204H
ERRCNT2 [R]
00000000 00000000
BTR2 [R/W]
00100011 00000001
00C208H
INTR2 [R]
00000000 00000000
TESTR2 [R/W]
00000000 X0000000
00C20CH
BRPE2 [R/W]
00000000 00000000
res.
00C210H
IF1CREQ2 [R/W]
00000000 00000001
IF1CMSK2 [R/W]
00000000 00000000
00C214H
IF1MSK22 [R/W]
11111111 11111111
IF1MSK12 [R/W]
11111111 11111111
00C218H
IF1ARB22 [R/W]
00000000 00000000
IF1ARB12 [R/W]
00000000 00000000
00C21CH
IF1MCTR2 [R/W]
00000000 00000000
res.
00C220H
IF1DTA12 [R/W]
00000000 00000000
IF1DTA22 [R/W]
00000000 00000000
00C224H
IF1DTB12 [R/W]
00000000 00000000
IF1DTB22 [R/W]
00000000 00000000
00C228H
00C22CH
00C230H
CAN 1
Status Flags
CAN 2
Control
Register
CAN 2
IF 1 Register
reserved
IF1DTA22 [R/W]
00000000 00000000
Fujitsu Microelectronics Europe GmbH
IF1DTA12 [R/W]
00000000 00000000
Page 72 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
00C234H
+1
+2
IF1DTB22 [R/W]
00000000 00000000
00C238H
00C23CH
Block
+3
IF1DTB12 [R/W]
00000000 00000000
reserved
00C240H
IF2CREQ2 [R/W]
00000000 00000001
IF2CMSK2 [R/W]
00000000 00000000
00C244H
IF2MSK22 [R/W]
11111111 11111111
IF2MSK12 [R/W]
11111111 11111111
00C248H
IF2ARB22 [R/W]
00000000 00000000
IF2ARB12 [R/W]
00000000 00000000
00C24CH
IF2MCTR2 [R/W]
00000000 00000000
res.
00C250H
IF2DTA12 [R/W]
00000000 00000000
IF2DTA22 [R/W]
00000000 00000000
00C254H
IF2DTB12 [R/W]
00000000 00000000
IF2DTB22 [R/W]
00000000 00000000
00C258H
00C25CH
reserved
00C260H
IF2DTA22 [R/W]
00000000 00000000
IF2DTA12 [R/W]
00000000 00000000
00C264H
IF2DTB22 [R/W]
00000000 00000000
IF2DTB12 [R/W]
00000000 00000000
00C268H
00C27CH
00C280H
reserved
TREQR22 [R]
00000000 00000000
00C284H
00C28CH
00C290H
CAN 2
IF 2 Register
TREQR12 [R]
00000000 00000000
CAN 2
Status Flags
reserved
NEWDT22 [R]
00000000 00000000
00C294H
00C29CH
Fujitsu Microelectronics Europe GmbH
NEWDT12 [R]
00000000 00000000
reserved
Page 73 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
00C2A0H
+1
00C2B0H
+2
+3
INTPND12 [R]
00000000 00000000
INTPND22 [R]
00000000 00000000
00C2A4H
00C2ACH
Block
reserved
MSGVAL22 [R]
00000000 00000000
MSGVAL12 [R]
00000000 00000000
00C2B4H
00EFFCH
reserved
00F000H
BCTRL [R/W]
- - - - - - - - - - - - - - - - 11111100 00000000
00F004H
BSTAT [R/W]
- - - - - - - - - - - - - 000 00000000 10 - - 0000
00F008H
BIAC [R]
- - - - - - - - - - - - - - - - 00000000 00000000
00F00CH
BOAC [R]
- - - - - - - - - - - - - - - - 00000000 00000000
00F010H
BIRQ [R/W]
- - - - - - - - - - - - - - - - 00000000 00000000
CAN 2
Status Flags
EDSU / MPU
00F014H
00F01CH
reserved
00F020H
BCR0 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F024H
BCR1 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F028H
BCR2 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F02CH
BCR3 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F030H
reserved
00F07CH
Fujitsu Microelectronics Europe GmbH
Page 74 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
+1
Block
+2
00F080H
BAD0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F084H
BAD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F088H
BAD2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F08CH
BAD3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F090H
BAD4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F094H
BAD5 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F098H
BAD6 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F09CH
BAD7 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A0H
BAD8 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A4H
BAD9 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A8H
BAD10 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0ACH
BAD11 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B0H
BAD12 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B4H
BAD13 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B8H
BAD14 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0BCH
BAD15 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
+3
EDSU / MPU
00F0C0H
-
reserved
027FFCH
Fujitsu Microelectronics Europe GmbH
Page 75 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
+1
Block
+2
+3
028000H
02FFFCH
MB91F467CA D-RAM size is 32kB
(data access is 0 waitcycles)
D-RAM
32 kB
030000H
037FFCH
MB91F467CA I-/D-RAM size is 32kB
(instruction access is 0 waitcycles, data access is 1 waitcycle)
I-/D-RAM
32 kB
038000H
03FFFCH
reserved
040000H
05FFFCH
ROMS00 area (128kB)
060000H
07FFFCH
ROMS01 area (128kB)
080000H
09FFFCH
ROMS02 area (128kB)
0A0000H
0BFFFCH
ROMS03 area (128kB)
0C0000H
0DFFFCH
ROMS04 area (128kB)
0E0000H
0FFFF4H
ROMS05 area (128kB)
0FFFF8H
FMV [R]
06 00 00 00H
0FFFFCH
FRV [R]
00 00 BF F8H
100000H
13FFFCH
ROMS06 area (256kB)
140000H
17FFFCH
ROMS07 area (256kB)
Fujitsu Microelectronics Europe GmbH
Fixed
Reset/Mode
Vector
Page 76 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
Register
Address
+0
+1
180000H
4FFFFCH
Block
+2
+3
reserved
Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values
shown above will be read.
Fujitsu Microelectronics Europe GmbH
Page 77 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
7 Electrical Characteristics
7.1 Absolute Maximum Ratings
Parameter
Symbol
min.
max.
Unit
Digital supply voltage
VDD-VSS
-0.3
6.0
V
Stepper motor control
supply voltage
HVDD-HVSS
-0.3
6.0
V
Storage temperature
TST
-55
125
°C
Power consumption
PTOT
1000
mW
TA = 25°C
VDD+0.3
V
Non SMC Ports
Ports 25 to 27 (SMC)
Digital input voltage
*
Condition
VIDIG
VSS-0.3
Analog input voltage
VIA
HVSS-0.3
AVSS-0.3
HVDD+0.3
AVCC+0.3
V
V
AVCC=AVRH
Analog supply voltage
AVCC-AVSS
-0.3
5.8
V
AVSS=0V
Analog reference
voltage
AVRH-AVSS
-0.3
5.8
V
AVSS=0V
Static DC current into
digital I/O
II/ODC
-2
2
mA
Relationship of the
supply voltages
HVDD
VDD - 0.3
VDD + 0.3
V
SMC mode
VSS - 0.3
VDD + 0.3
V
VDD - 0.3
VDD + 0.3
V
General purpose
port mode
At least one pin of the
Ports 25 to 29 (SMC,
ANx) is used as digital
input or output
VSS - 0.3
VDD + 0.3
V
VSS - 0.3
VDD + 0.3
V
*
AVCC
VDD35
II/ODC < ISRUN
All pins of the Ports 25
to 29 (SMC, ANx) follow the condition of VIA
not available on
MB91F467CA
* Making full use of the allowed static DC current into digital I/Os will lead to lower values here.
Fujitsu Microelectronics Europe GmbH
Page 78 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
7.2 Operating Conditions
Parameter
Symbol
min.
Operating temperature
TOP
Supply voltage
- Digital supply
VDD5-VSS
- External Bus supply
not available
- Stepper motor control
supply
HVDD-HVSS
- Analog supply
Current consumption
-Run mode
AVCC-AVSS
typ.
max.
Unit
Condition
-40
105
°C
3.0
5.5
V
VSS = 0V
Internal voltage regulator:
VDDCORE = 1.8V
4.75
5.25
V
HVSS = 0V
3.0
5.5
V
All SMC pins are used as
general purpose ports
3.0
5.5
V
AVSS = 0V
IsRUN
140
mA
- Sleep mode
IsSLEEP
25
mA
-RTC mode
IsRTC
100
50
µA
µA
f = 4MHz, TA = 25°C
f 100kHz, TA = 25°C
500
250
µA
µA
f = 4MHz, TA = 105°C
f 100kHz, TA = 105°C
40
200
µA
µA
TA = 25°C
TA = 105°C
-Stop mode
IsSTOP
Stepper motor control
- SMC-ports output voltage
4.75V
VOHH
VOHL
HVDD-500
HVSS+500
40
- Slew rate
VDD
5.25V
mV
mV
Iload = ±27mA, TA= 105°C
Iload = ±30mA, TA= 25°C
ns
Cload = 0 pF
Alarm comparator
-Threshold voltages
- overvoltage
VTAH
AVCC*0.78
-3%
AVCC*0.78
AVCC*0.78
+3%
V
- undervoltage
VTAL
AVCC*0.36
-5%
AVCC*0.36
AVCC*0.36
+5%
V
- Switching hysteresis
VTAHYS
50
250
mV
at VTAH, VTAL
- Alarm sense time
tAS
0.2/23)
µs
selectable by register
- Input resistance
Rin
5
Fujitsu Microelectronics Europe GmbH
M
Page 79 of 81
European MCU Design Centre
ADC inputs 2)
- Reference voltage
input
- Input voltage range
MB91F467CA preliminary datasheet ver. 0.13
AVRH
AVRL
AVCC*0.75
AVSS
Vimax
Vimin
AVRL
AVCC
AVCC*0.25
V
V
AVRH
V
V
- Input resistance
RI
2.6
12.1
k
k
- Input capacitance
CI
8.5
pF
100
k
- Impedance of external
output driving the ADC input
4.5V
3.0V
AVCC
AVCC
5.5V
4.5V
- Input leakage current
IIL
-1
1
µA
TA = 25°C
Digital outputs
- Output “H” voltage
VOH
VDD-0.5
VDD
V
4.5V VDD 5.5V,
Iload = ±2mA / ±5mA
- Output “L” voltage
VOL
VSS
VSS+0.4
V
Digital outputs (I2C port)
- Output “H” voltage
VOH
VDD-0.5
VDD
V
- Output “L” voltage
VOL
VSS
VSS+0.4
V
Digital Inputs 1)
CMOS Schmitt-Trigger (C)
- High voltage range
- Low voltage range
VIH
VIL
0.7*VDD
VSS
VDD
0.3*VDD
V
V
CMOS Schmitt-Trigger (CH)
- High voltage range
- Low voltage range
VIH
VIL
0.8*VDD
VSS
VDD
0.2*VDD
V
V
CMOS Automotive SchmittTrigger (A)
- High voltage range
- Low voltage range
VIH
VIL
0.8*VDD
VSS
VDD
0.5*VDD
V
V
- Hysteresis voltage
VHYS
0.2
0.5
V
TLL (TTL)
- High voltage range
- Low voltage range
VIH
VIL
2.0
VSS
VDD
0.8
V
V
- Input capacitance
- Input leakage current
- Pull up resistor
- Pull down resistor
CIN
IIL
Rup
Rdown
-1
tbd
1
pF
µA
k
k
VDD
VSS+0.4
V
V
mA
0.6
ms
50
50
3.0V
Iload =
4.5V
Iload =
VDD 4.5V,
±1.6mA / ±3mA
VDD 5.5V,
±3mA
3.0V VDD
Iload = ±2mA
4.5V,
4.5V
5.5V
VDD
TA = 25°C
I2C Bus Interface4)
- Output voltage
- Output current
VOH
VOL
Iout
VSS
3
Lock-up time PLL1
(4MHz->16…100MHz)
Fujitsu Microelectronics Europe GmbH
Open Drain Output
Page 80 of 81
European MCU Design Centre
MB91F467CA preliminary datasheet ver. 0.13
ESD Protection
(Human body model)
Vsurge
2
RC Oscillator
fRC100KHz
fRC2MHz
50
1
kV
100
2
200
4
kHz
MHz
Rdischarge = 1.5k
Cdischarge = 100pF
VDDCORE ` 1.65V
1)
Valid for bidirectional tristate I/O PAD cell
2)
The protection diodes at the analog inputs are connected to the digital supply voltage
3)
The longer alarm sense time can be selected for power safe modes in order to reduce the current
consumption
7.3 Converter Characteristics
• A/D Converter
Parameter
Symbol
Rating
Minimum
Typical
Unit
Maximum
Resolution
10
Bit
Conversion error
+/- 3.0
LSB
Non-linearity
+/-2.5
LSB
Differential
Non-linearity
+/-1.9
LSB
Zero Reading
voltage
V0T
Full scale reading VFST
voltage
AVRL -1.5
AVRL+0.5
AVRL+2.5
LSB
AVRH-3.5
AVRH-1.5
AVRH+0.5
LSB
Input current
IA @
AVCC
2.4
4.7
mA
Reference
voltage
current
IR
0.65
1.0
mA
-
-
ns
Comparision
Time
TCOMP
680
2080
Remark
Overall error
4.5V b Avcc b 5.5V
3.0V b Avcc b 4.5V
• Sampling Time Calculation
TSAMP = ( 2.6 kOhm + Rext) * 8.5pF * 7; for 4.5V
TSAMP = (12.1 kOhm + Rext) * 8.5pF * 7; for 3.0V
Avcc
Avcc
5.5V
4.5V
• Conversion Time Calculation
TCONV = TSAMP + TCOMP
Fujitsu Microelectronics Europe GmbH
Page 81 of 81
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