ds91F465KA-v1.11.pdf

FUJITSU SEMICONDUCTOR
MB91F465KA preliminary datasheet
MB91460 series
European MCU Design Centre (EMDC)
Fujitsu Microelectronics Europe GmbH
Pittlerstrasse 47
63225 Langen, Germany
Version 1.11
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Revision History
Version
0.10
0.11
0.30
Date
2005-09-20
2005-10-10
2005-11-19
0.31
0.32
0.33
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.10
1.11
2006-01-09
2006-01-19
2006-01-23
2006-02-14
2006-02-22
2006-05-02
2006-05-12
2006-05-23
2006-06-19
2006-06-19
2006-10-12
2007-03-26
1.11
Remark
Initial draft
1st. customer version (update of RAM size)
Updated pinout + resource mix + RAM sizes
(design spec.rev.3.0)
Absolute max. ratings corrected
MONCLK has threestate output pin
Added: Relationship of supply voltages
Added IO-Map as Appendix 1
Corrected section 4.2. (AVCC5/AVSS pin comment)
Flash memory access timing settings added
ADC operating conditions updated, ICC run mode updated
IO-Map added with new formatting
ROMS setting corrected in memory map
Special notes: Flash write only with 16bit
First public release
Added ADC comparision time values, corrected PLL1 lock up time
corrected unified flash settings, corrected chapter sequence
Latest revision
Fujitsu Microelectronics Europe GmbH
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MB91F465KA preliminary datasheet ver. 1.11
Table of contents
1
Overview........................................................................................................................ 5
1.1
2
Block Diagram .......................................................................................................... 5
Feature List ................................................................................................................... 6
2.1
Overview Table ........................................................................................................ 6
2.2
Core Functionality..................................................................................................... 7
2.2.1
Memory Map ...................................................................................................... 8
2.2.2
FR70 CPU Core................................................................................................. 9
2.2.3
Instruction Cache ............................................................................................... 9
2.2.4
Interrupt Controller ............................................................................................. 9
2.2.5
External Bus Interface.......................................................................................10
2.2.6
DMA Controller .................................................................................................10
2.2.7
Internal Data RAM.............................................................................................10
2.2.8
Internal Program/Data RAM ..............................................................................10
2.3
Peripheral Function .................................................................................................11
2.4
Embedded Program/Data Memory (Flash) ..............................................................15
2.4.1
Flash Features ..................................................................................................15
2.4.2
CPU Mode ........................................................................................................16
2.4.2.1
Flash configuration in CPU mode .......................................................................................... 16
2.4.2.2
Flash access timing settings in CPU mode............................................................................ 17
2.4.3
2.4.3.1
Flash configuration in parallel flash programming mode........................................................ 18
2.4.3.2
Pin connections in parallel programming mode ..................................................................... 19
2.4.4
3
4
Parallel flash programming mode......................................................................18
Flash Security ...................................................................................................20
2.4.4.1
Vector addresses................................................................................................................... 20
2.4.4.2
Security Vector FSV1 ............................................................................................................ 20
2.4.4.3
Security Vector FSV2 ............................................................................................................ 22
2.4.4.4
Register description for Flash Security .................................................................................. 22
Package and Pin Assignment .....................................................................................23
3.1
Package ..................................................................................................................23
3.2
I/O Pins and their functions......................................................................................24
3.3
I/O Pin Types...........................................................................................................27
Recommended Settings ..............................................................................................28
4.1
PLL and Clockgear settings.....................................................................................28
4.2
Flash interface settings............................................................................................29
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4.3
MB91F465KA preliminary datasheet ver. 1.11
Clock Modulator settings .........................................................................................29
5
Interrupt Vector Table..................................................................................................32
6
I/O Map..........................................................................................................................42
7
Electrical Characteristics ............................................................................................64
7.1
Absolute Maximum Ratings .....................................................................................64
7.2
Operating Conditions...............................................................................................64
7.3
Converter Characteristics ........................................................................................67
Fujitsu Microelectronics Europe GmbH
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MB91F465KA preliminary datasheet ver. 1.11
1 Overview
The MB91F465KA is the 120-pin body control flash MCU of the M91460 family.
The corresponding evaluation device is the MB91V460.
1.1 Block Diagram
4MHz
FRT x 8
Clock modulation
Clock Control
Clock Supervisor
Int. Control
Power Control
EDSU/MPU
2 channels
32 kHz
Subclock 32 kHz
FR70
FR70CPU
CPU
0.18
0.18um
um
80 MHz
80 MHz
Watchdog
Bit Search
RC Osc. 100kHz / 2MHz
ICU x 8
OCU x 8
R-Timer x 8
PPG x 12
RTC
Ext. Int. x 10
RAM 8KB
Pre-fetch Cache/
I-RAM 4KB
FLASH
512 KB
RAM 8KB
DATA
INSTR
Core: 1.8V/IO: 5V
Harvard Bus
Converter
10Bit ADC x 26
DMA (5 ch)
LIN-USART x 5
CAN x 1
(32 msg)
I2C x 1
LQFP-120
BootROM 4KB
Fujitsu Microelectronics Europe GmbH
General Purpose
Port I/O x 7
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MB91F465KA preliminary datasheet ver. 1.11
2 Feature List
2.1 Overview Table
Feature
MB91V460
MB91F464AA
MB91F465KA
Max. Core frequency
(CLKB)
80 MHz
80 MHz
80 MHz
Max. Resource
frequency (CLKP)
40 MHz
40 MHz
40 MHz
Max. Ext-Bus
frequency (CLKT)
40 MHz
-
-
Max. CAN frequency
(CLKCAN)
20 MHz
40 MHz
40 MHz
Watchdog
yes
yes
yes
Bit Search
yes
yes
yes
Reset Input
yes
yes
yes
Clock Modulator
(yes)
yes
yes
DMA
5 ch
5 ch
5 ch
MPU/EDSU
16 ch
2 ch
2 ch
Flash
external
384 KB + 32 KB
512 KB + 32 KB
Satellite Flash
external
-
-
n.a.
yes
yes
D-bus RAM
64 KB
8 KB
8 KB
GP RAM
64 KB
8 KB
8 KB
Direct mapped cache
16 KB
-
4 KB
Boot-ROM
4 kB
4 KB
4 KB
RTC
1 ch
1 ch
1 ch
Free Running Timer
8 ch
8 ch
8 ch
ICU
8 ch
8 ch
8 ch
OCU
8 ch
6 ch
8 ch
Reload Timer
8 ch
8 ch
8 ch
PPG
16 ch
10 ch
12 ch
PFM
1 ch
-
-
Sound Generator
1 ch
-
-
Flash Protection
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Feature
MB91F465KA preliminary datasheet ver. 1.11
MB91V460
MB91F464AA
MB91F465KA
4 ch
-
-
6 ch (128 msg buffer)
1 ch (32 msg.)
1 ch (32 msg.)
16 ch (4 ch FIFO)
5 ch (1 ch FIFO)
5 ch (1 ch FIFO)
4 ch
1 ch
1 ch
32-bit address /
32-bit data /
8 chip select
-
-
External Interrupts
16 ch
10 ch
10 ch
NMI
1 ch
-
-
SMC (Quad Option)
6 ch
-
-
1 ch 40x4
-
-
ADC (10-bit)
32 ch
20 ch
26 ch
Alarm Comparator
2 ch
-
-
General Purpose
Port I/O
14
-
7
Low voltage detection
yes
yes
yes
Clock Supervisor
yes
yes
yes
BGA 666
LQFP-100
LQFP-120
UpDown Counter
C_CAN
LIN-USART
I2C
FR external bus
LCD
Package
2.2 Core Functionality
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MB91F465KA preliminary datasheet ver. 1.11
2.2.1 Memory Map
MB91V460A
MB91F465KA
I/O Byte Data
0000:0000h0000:00FFh
I/O Byte Data
0000:0100h0000:01FFh
I/O Halfword Data
0000:0100h0000:01FFh
I/O Halfword Data
0000:0200h0000:03FFh
I/O Word Data
0000:0200h0000:03FFh
I/O Word Data
0000:0400h0000:0FFFh
I/O
0000:0400h0000:0FFFh
I/O
0000:1000h0000:10FFh
DMA
0000:1000h0000:10FFh
DMA
0000:2000h0000:5FFFh
Flash Memory I-Cache (4 KB) or
Instruction RAM (4 KB)
Flash Memory Control
Flash Memory I-Cache Control
available, but no
memory mapped
access
0000:2000h0000:5FFFh
Flash Memory I-Cache (16 kB) or
Instruction RAM (16 kB)
0000:7000h0000:70FFh
Flash Memory Control
Flash Memory I-Cache Control
0000:7000h0000:70FFh
0000:8000h0000:BFFFh
Boot ROM (4 kB)
0000:8000h0000:BFFFh
0000:C000h0000:CFFFh
CAN
0000:C000h0000:CFFFh
0001:0000h0001:FFFFh
External Bus I-Cache (4 kB) or
Instruction RAM (4 kB)
0001:0000h0001:FFFFh
0002:0000h0002:FFFFh
Data RAM (64 kB)
0002:0000h0002:FFFFh
Data RAM (8 KB)
0003:0000h0003:FFFFh
Instruction/Data RAM (64 kB)
0003:0000h0003:FFFFh
Instruction/Data RAM (8 kB)
ROMS00
(128 kB)
0004:0000h0005:FFFFh
0006:0000h0007:FFFFh
ROMS01
(128 kB)
0006:0000h0007:FFFFh
0008:0000h0009:FFFFh
ROMS02
(128 kB)
0008:0000h0009:FFFFh
000A:0000h000B:FFFFh
ROMS03
(128 kB)
000A:0000h000B:FFFFh
000C:0000h000D:FFFFh
ROMS04
(128 kB)
000C:0000h000D:FFFFh
000E:0000h000F:FFFFh
ROMS05
(128 kB)
000E:0000h000F:FFFFh
ROMS06
(256 kB)
CAN
External Bus Area
(not available on MB91F465KA)
0010:0000h0013:FFFFh
External Bus Area
(not available on MB91F465KA)
ROMS6 setting
fixed to external
area
ROMS07
(256 kB)
0014:0000h0017:FFFFh
Flash Memory Area
(32 KB)
ROMS7 setting
fixed to internal
area
ROMS08
(256 kB)
0018:0000h001B:FFFFh
ROMS09
(256 kB)
001C:0000h001F:FFFFh
0020:0000h0027:FFFFh
ROMS10
(512 kB)
0020:0000h0027:FFFFh
0028:0000h002F:FFFFh
ROMS11
(512 kB)
0028:0000h002F:FFFFh
0030:0000h0037:FFFFh
ROMS12
(512 kB)
0030:0000h0037:FFFFh
0038:0000h003F:FFFFh
ROMS13
(512 kB)
0038:0000h003F:FFFFh
0040:0000h0047:FFFFh
ROMS14
(512 kB)
0040:0000h0047:FFFFh
0048:0000h004F:FFFFh
ROMS15
(512 kB)
0048:0000h004F:FFFFh
0010:0000h0013:FFFFh
0014:0000h0017:FFFFh
0018:0000h001B:FFFFh
001C:0000h001F:FFFFh
0050:0000hFFFF:FFFFh
Legend
Emulation SRAM Area
(max 4.864 kB)
or
External Bus Area
depending on ROMA/ROMS
setting
External Bus Area
0050:0000hFFFF:FFFFh
External Bus Area
(not available on MB91F465KA)
ROMS8-15 setting fixed to external area
Flash Memory Area
(512 kB)
ROMS2-5 setting fixed to
internal area
0004:0000h0005:FFFFh
Boot ROM (4 KB)
ROMS0-1
setting fixed to
external area
0000:0000h0000:00FFh
External Bus Area
(not available on MB91F465KA)
Memory available in this area
Memory not available in this area
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MB91F465KA preliminary datasheet ver. 1.11
2.2.2 FR70 CPU Core
• 32-bit RISC, load/store architecture, pipeline 5 stages
• Maximum operating frequency: Core clock = 64 MHz to 100 MHz (device dependent)
(Source oscillation= 4 MHz, multiplied by 16 to 25 (PLL clock multiplier method))
• General-purpose registers: 16 x 32 bits
• 16-bit fixed-length instruction (Base instruction)
• 32-bit linear address space: 4 Gbytes
• Instructions suitable for embedded application
•
Transfer command between memories
•
Bit-processing instruction
•
Barrel-shift instructions
• Instructions supporting C-language
• Function's enter command /exit command
• Multi-load/store command of register contents
• Assembler statement is also easily available
Register's interlock function
• Multiplier's embedded application/command level support
•
Signed 32-bit multiplication: 5 cycles
•
Signed 16-bit multiplication: 3 cycles
• Interrupt (PC/PS are saved): 6 cycles (16 priority level)
• Harvard architecture enables simultaneous execution of program access and data access
• Memory protection function
• Embedded debug support
• Commands compatible with FR family
2.2.3 Instruction Cache
• Direct mapped I-cache
• 4 kByte integrated
• Lock function enabling programs to be resident
2.2.4 Interrupt Controller
• A total of 10 external interrupt lines ( 8 normal interrupt pins, 2 interrupt pins shared with
2
peripheral inputs for Wake Up from STOP mode (CAN RX and I C SDA)
• Interrupts from internal peripherals (128 interrupt vectors)
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MB91F465KA preliminary datasheet ver. 1.11
• Priority levels programmable for normal interrupt lines excluding the nonmaskable one (16
levels)
• Capable of using the normal interrupt pins for Wake Up from STOP mode
2.2.5 External Bus Interface
• An External Bus Interface is not available on MB91F465KA.
2.2.6 DMA Controller
• Four transfer modes supported: single/block, burst, continuous transfer, and fly-by
• 5 channels
• 3 types of transfer sources (external pins/internal peripherals/and software)
• Up to 128 selectable internal transfer sources
• Addressing mode: Specifying up to 32-bit addresses (Increment/decrement/fixed)
• Transfer mode (Demand transfer/burst transfer/step transfer/block transfer)
• Transferred data size selectable from among 8, 16, and 32 bits
2.2.7 Internal Data RAM
• 8 KBytes integrated
• Zero wait state for read/write access
2.2.8 Internal Program/Data RAM
• 8 kBytes integrated
• Zero wait state for read/write access of instructions
• One wait state for read/write access of data
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MB91F465KA preliminary datasheet ver. 1.11
2.3 Peripheral Function
• General-purpose port : All functional pins can be used as general-purpose ports, if the
corresponding function is not needed.
2
•
N channel open drain port out of above: 2 (for I C)
•
MB91F465KA has 7 general purpose ports without corresponding peripheral function.
• A/D converter : 26 channels (1 unit)
•
Series-parallel type
•
Resolution: 10 bits
•
Minimum conversion time: 3µs
•
Single conversion mode
•
Continuous conversion mode
•
Stop conversion mode
•
Activation by software or external trigger can be selected
•
Reload timer 7 and A/D Converter co-operate
• External interrupt input : 8 + 2 channels
•
Can be programmed to be edge sensitive or level sensitive
•
Interrupt mask and request pending bits per channel
•
1 channel combined with CAN RX for wakeup
•
1 channel combined with I C SDA for wakeup
2
• Bit search module (using REALOS)
•
Function to search the first bit position of “1”, “0”, “Changed” from MSB (most significant
bit) within 1 word
• Reload timer : 16 bits x 8 channels
•
16-bit reload counter
•
Includes clock prescaler (fRES/2 , fRES/2 , fRES/2 , fRES/2 , fRES/2 )
1
3
5
6
7
• Free-run timer : 16 bits x 8 channels
•
16-bit free running counter, signals an interrupt when overflow or match with compare
register
•
Includes prescaler (fRES/2 , fRES/2 , fRES/2 , fRES/2 )
•
Timer data register has R/W access
2
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4
5
6
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European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
• PPG : 16 bit x 12 channels
•
16 bit down counter, cycle and duty setting registers
•
Interrupt at triggering, cycle or duty match
•
PWM operation and one-shot operation
•
Internal prescaler allows fRES/2 , fRES/2 , fRES/2 , fRES/2 as counter clock
•
Can be triggered by software, reload timer or external trigger event
•
Reload timer 0/1 available as trigger for PPG 0/1/2/3
•
Reload timer 4/5 available as trigger for PPG 8/9/10/11
0
2
4
6
• Input capture : 16 bits x 8 channels
•
Rising edge, falling edge or rising & falling edge sensitive
•
Free-run timer 0 and input capture 0/1 co-operate
•
Free-run timer 1 and input capture 2/3 co-operate
•
Free-run timer 4 and input capture 4/5 co-operate
•
Free-run timer 5 and input capture 6/7 co-operate
• Output compare : 16 bits x 8 channels
•
Signals an interrupt when a match with of 16-bit IO timer occurs
•
An output signal can be generated
•
Free-run timer 2 and output compare 0/1 co-operate
•
Free-run timer 3 and output compare 2/3 co-operate
•
Free-run timer 6 and output compare 4/5 co-operate
•
Free-run timer 7 and output compare 6/7 co-operate
• LIN-USART (LIN=Local Interconnect Network) : 5 channels
•
Full-duplex double buffer system
•
With parity/without parity selectable
•
1 or 2 stop bits selectable
•
7 or 8 bits data length selectable
•
NRZ type transfer format
•
Asynchronous /synchronous communications selectable
•
Master-slave communication function (multiprocessor mode)
•
Dedicated baud rate prescaler is embedded in each channel
•
External clock is able to use as transfer clock
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MB91F465KA preliminary datasheet ver. 1.11
•
Parity error, frame error, and overrun error detecting functions
•
SPI compatible
•
LIN master and slave
•
LIN-USART 0 and ICU 0 co-operate (for LIN sync field in slave mode)
•
LIN-USART 1 and ICU 1 co-operate (for LIN sync field in slave mode)
•
LIN-USART 2 and ICU 2 co-operate (for LIN sync field in slave mode)
•
LIN USART 3 and ICU 3 co-operate (for LIN sync field in slave mode)
•
LIN USART 4 and ICU 4 co-operate (for LIN sync field in slave mode)
• CAN : 1 channel
•
Supports CAN protocol version 2.0 part A and B
•
Bit rates up to 1 Mbit/s
•
32 message objects
•
Each message object has its own identifier mask
•
Programmable FIFO mode (cocatenation of message objects)
•
Maskable interrupt
•
Disabled Automatic Retransmission mode for Time Triggered CAN applications
•
Programmable loop-back mode for self-test operation
2
• I C (400k fast mode) : 1 channel
•
Master or slave transmission
•
Arbitration function
•
Clock synchronization function
•
Slave address and general call address detect function
•
Transfer direction detect function
•
Start condition repeat generation and detection function
•
Bus error detect function
•
Compatible to I2C standard and fast mode specification (operation up to 400 kHz, 10 bit
addressing)
•
Includes clock divider functionality
•
SCL and SDA lines include optional noise filter. The noise filter allows the suppression of
spikes in the range of 1 to 1.5 cycles of the Peripheral Clock.
• Timebase/watchdog timer (26 bits)
•
20
Adjustable watchdog timer interval (between 2 and 2
Fujitsu Microelectronics Europe GmbH
26
system clock cycles)
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MB91F465KA preliminary datasheet ver. 1.11
• Real-time clock (counts during stop mode)
•
RTC module can be clocked either from 32 kHz quartz, 4 MHz quartz or from the RC
Oscillator
•
Facility to correct oscillation deviation (subclock calibration)
•
Read/write accessible second/minute/ hour registers
•
Can signal interrupts every halfsecond/second/ minute/hour/day
•
Internal clock divider and prescaler provide exact 1s clock based on a 4 MHz or a 32 kHz
clock input
•
Prescaler value for 4 MHz is 1E847FH
•
Prescaler value for 32 kHz is 003FFFH
• Clock supervisor
•
Monitors external 32kHz and 4MHz for fails (e.g. crystal breaks)
•
Switches in case of fail to an available recovery clock (other oscillator, or RC oscillator)
• Clock modulator (reduction of EME)
• Subclock calibration
•
Calibration of the RTC timer in 32 kHz or RC oscillator operation, based on the more
accurate 4 MHz quartz is possible
• Main oscillation stabilisation timer
•
23 bit counter for main oscillation stabilisation wait when running in sub clock mode
•
Generates an interrupt when stabilisation time has elapsed
• Sub oscillation stabilisation timer
•
15 bit counter for sub oscillation stabilisation wait when running in main clock mode
•
Generates an interrupt when stabilisation time has elapsed
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MB91F465KA preliminary datasheet ver. 1.11
2.4 Embedded Program/Data Memory (Flash)
2.4.1 Flash Features
• 512 + 32 KByte Flash
• Power: Single +3.0-5.5V supply
• Programmable wait states for read/write access;
• Read 16/32bit width, write 16 bit width
• Flash security with security vector at 0x0014:8000 – 0x0014:800F
1
• Operation modes:
• (1) 32-bit CPU mode:
•CPU reads and executes programs in word (32-bit) length units.
•Flash writing is not possible.
•Actual Flash Memory access is performed in word (32-bit) length units.
• (2) 16-bit CPU mode:
•CPU reads and writes in half-word (16-bit) length units.
•Program execution from the Flash is not possible.
•Actual Flash Memory access is performed in word (16-bit) length units.
• (3) Flash memory mode (external access to Flash memory enabled)
•Features (Through combination of Flash memory macro and FR-CPU interface circuit):
•Functions as CPU program/data storage memory.
•Enables access to 32-bit bus width.
•Enables read/write/erase by CPU (auto program algorithm*).
•Functions equivalent to MBM29LV400TC stand-alone Flash-memory product.
•Enables read/write/erase by parallel Flash programmer (auto program algorithm*).
*: Auto program algorithm = Embedded Algorithm TM
1
See MB91460 hardware manual for further details.
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MB91F465KA preliminary datasheet ver. 1.11
2.4.2 CPU Mode
2.4.2.1
Flash configuration in CPU mode
Flash memory map in CPU mode (MD[2:0] = 00x)
addr
0014:FFFFh
0014:C000h
SA6 (8kB)
SA7 (8kB)
0014:BFFFh
0014:8000h
SA4 (8kB)
SA5 (8kB)
0014:7FFFh
0014:4000h
SA2 (8kB)
SA3 (8kB)
0014:3FFFh
0014:0000h
SA0 (8kB)
SA1 (8kB)
0013:FFFFh
0012:0000h
SA22 (64kB)
SA23 (64kB)
0011:FFFFh
0010:0000h
SA20 (64kB)
SA21 (64kB)
000F:FFFFh
000E:0000h
SA18 (64kB)
SA19 (64kB)
ROMS5
000D:FFFFh
000C:0000h
SA16 (64kB)
SA17 (64kB)
ROMS4
000B:FFFFh
000A:0000h
SA14 (64kB)
SA15 (64kB)
ROMS3
0009:FFFFh
0008:0000h
SA12 (64kB)
SA13 (64kB)
ROMS2
0007:FFFFh
0006:0000h
SA10 (64kB)
SA11 (64kB)
ROMS1
0005:FFFFh
0004:0000h
SA8 (64kB)
SA9 (64kB)
ROMS0
ROMS7
ROMS6
addr+0
16bit read/write
32bit read
addr+1
addr+2
dat[31:16]
addr+3
dat[15:0]
dat[31:0]
addr+4
addr+5
addr+6
dat[31:16]
addr+7
dat[15:0]
dat[31:0]
Legend
Memory available in this area
Memory not available in this area
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2.4.2.2
MB91F465KA preliminary datasheet ver. 1.11
Flash access timing settings in CPU mode
The Flash access timing settings described below are valid for MB91F465KA in the 1.8V operation
2
mode of the Main regulator and Flash .
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB
or maximum clock modulation) for Flash read and write access.
Flash read timing settings for MB91F465KA
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 24 MHz
0
0
0
-
1
to 48 MHz
0
0
1
-
2
to 80 MHz
1
1
3
-
4
Flash write timing settings for MB91F465KA (synchronous write)
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 16 MHz
0
-
-
0
3
to 32 MHz
0
-
-
0
4
to 48 MHz
0
-
-
0
5
to 64 MHz
1
-
-
0
6
to 80 MHz
1
-
-
0
7
2
Keep REGSEL_FLASHSEL=0 and REGSEL_MAINSEL=0 at their initial value (HWM Chapter
52.3.1)
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MB91F465KA preliminary datasheet ver. 1.11
2.4.3 Parallel flash programming mode
2.4.3.1
Flash configuration in parallel flash programming mode
Parallel Flash programming mode (MD[2:0] = 111)
FA[20:0]
001F:FFFFh
001F:0000h
SA19 (64kB)
001E:FFFFh
001E:0000h
SA18 (64kB)
001D:FFFFh
001D:0000h
SA17 (64kB)
001C:FFFFh
001C:0000h
SA16 (64kB)
001B:FFFFh
001B:0000h
SA15 (64kB)
001A:FFFFh
001A:0000h
SA14 (64kB)
0019:FFFFh
0019:0000h
SA13 (64kB)
0018:FFFFh
0018:0000h
SA12 (64kB)
0017:FFFFh
0017:E000h
SA7 (8kB)
0017:DFFFh
0017:C000h
SA6 (8kB)
0017:BFFFh
0017:A000h
SA5 (8kB)
0017:9FFFh
0017:8000h
SA4 (8kB)
16bit write mode
FA[1:0]=00
FA[1:0]=10
DQ[15:0]
DQ[15:0]
Remark: Always keep FA[0] = 0 and FA[20] = 1
Fujitsu Microelectronics Europe GmbH
Page 18 of 67
European MCU Design Centre
2.4.3.2
MB91F465KA preliminary datasheet ver. 1.11
Pin connections in parallel programming mode
Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash
memory's interface circuit enables direct control of the Flash memory unit from external pins by
directly linking some of the signals to GP-Ports. Please see table below for signal mapping.
In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is
generally set when writing/erasing using the parallel Flash programmer. In this mode, all operations of
the 16.5 Mbit Flash memory's Auto Algorithms are available.
Correspondence between MBM29LV400TC and Flash Memory Control Signals
MB91F465KA external pins
MBM29LV400TC
External pins
FR-CPU mode
-
INITX
Flash memory
mode
-
INITX
62
RESET
-
FRSTX
GP16_7
63
-
-
MD2
MD2
118
Set to ‘1’
-
-
MD1
MD1
117
Set to ‘1’
-
-
MD0
MD0
111
Set to ‘1’
RY/BY
FMCS:RDY bit
RY/BYX
GP24_0
89
BYTE
Internally fixed to
‘H’
BYTEX
GP24_2
93
WE
WEX
GP28_3
34
OE
OEX
GP28_2
33
CEX
GP28_1
32
ATDIN
GP22_1
88
Set to ‘0’
EQIN
GP22_0
87
Set to ‘0’
-
TESTX
GP24_3
94
Set to ‘1’
-
RDYI
GP24_1
92
Set to ‘0’
A0
FA0
GP19_2
55
Set to ‘0’
A1 to A8
FA1 to FA8
GP27_0 to
GP27_7
21 to 28
FA9 to FA16
GP15_0 to
GP15_5,
GP21_0, GP21_1
83 to 86,
10, 11,
68, 69
A17 to A19
FA17 to FA19
GP21_2,
GP21_4,
GP21_5
70, 72, 73
A20 to A21
FA20, FA21
GP21_6, GP28_0
74, 29
DQ0 to DQ7
DQ0 to DQ7
GP17_0 to
GP17_7
58, 59, 65, 66,
67, 78, 79, 80
DQ8 to DQ15
GP14_0 to
GP14_7
2 to 9
CE
-
A9 to A16
Internal control
signal + control
via interface
circuit
Internal address
bus
Internal data bus
DQ8 to DQ15
Fujitsu Microelectronics Europe GmbH
Normal function
Comment
Pin number
Set to ‘1’
Page 19 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
2.4.4 Flash Security
2.4.4.1
Vector addresses
Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1,
BSV2) controlling the protection functions of the flash security module:
FSV1: 0x14:8000
BSV1: 0x14:8004
FSV2: 0x14:8008
BSV2: 0x14:800C
2.4.4.2
Security Vector FSV1
The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes
and the individual write protection of the 8 kByte sectors.
V FSV1 (bits 31 to 16)
The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write
protection modes.
Explanation of the bits in the Flash Security Vector FSV1[31:16]
FSV1[18]
FSV1[31:19]
Write Protection
Level
FSV1[17]
FSV1[16]
Write Protection
Read Protection
Flash Security Mode
set all to ‘0’
set to ‘0’
set to ‘0’
set to ‘1’
set all to ‘0’
set to ‘0’
set to ‘1’
set to ‘0’
Read Protection (all device modes, except
INTVEC mode MD[2:0]=”000”)
Write Protection (all device modes, without
exception)
Read Protection (all device modes, except
set all to ‘0’
set to ‘0’
set to ‘1’
set to ‘1’
INTVEC mode MD[2:0]=”000”) and Write
Protection (all device modes)
set all to ‘0’
set to ‘1’
set to ‘0’
set to ‘1’
set all to ‘0’
set to ‘1’
set to ‘1’
set to ‘0’
Read Protection (all device modes, except
INTVEC mode MD[2:0]=”000”)
Write Protection (all device modes, except
INTVEC mode MD[2:0]=”000”)
Read Protection (all device modes, except
set all to ‘0’
set to ‘1’
set to ‘1’
set to ‘1’
INTVEC mode MD[2:0]=”000”) and Write
Protection (all device modes except INTVEC
mode MD[2:0]=”000”)
Fujitsu Microelectronics Europe GmbH
Page 20 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
V FSV1 (bits 15 to 0)
The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write
protection of the 8 kByte sectors. It is only evaluated if write protection bit FSV1[17] is set.
Explanation of the bits in the Flash Security Vector FSV1[15:0]
Enable Write
Disable Write
Protection
Protection
-
set to ‘0’
set to ‘1’
not available
FSV1[1]
-
set to ‘0’
set to ‘1’
not available
FSV1[2]
-
set to ‘0’
set to ‘1’
not available
FSV1[3]
-
set to ‘0’
set to ‘1’
not available
FSV1[4]
SA4
set to ‘0’
-
Write protection is mandatory!
FSV1[5]
SA5
set to ‘0’
set to ‘1’
FSV1[6]
SA6
set to ‘0’
set to ‘1’
FSV1[7]
SA7
set to ‘0’
set to ‘1’
FSV1[8]
-
set to ‘0’
set to ‘1’
not available
FSV1[9]
-
set to ‘0’
set to ‘1’
not available
FSV1[10]
-
set to ‘0’
set to ‘1’
not available
FSV1[11]
-
set to ‘0’
set to ‘1’
not available
FSV1[12]
-
set to ‘0’
set to ‘1’
not available
FSV1[13]
-
set to ‘0’
set to ‘1’
not available
FSV1[14]
-
set to ‘0’
set to ‘1’
not available
FSV1[15]
-
set to ‘0’
set to ‘1’
not available
FSV1 bit
Sector
FSV1[0]
Comment
Remark: It is mandatory to always set the sector where the Flash Security Vectors FSV1 and
FSV2 are located to write protected (here sector SA4). Otherwise it is possible to overwrite the
Security Vector to a setting where it is possible to either read out the flash content or
manipulate data by writing.
Fujitsu Microelectronics Europe GmbH
Page 21 of 67
European MCU Design Centre
2.4.4.3
MB91F465KA preliminary datasheet ver. 1.11
Security Vector FSV2
The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write
protection of the 64 kByte sectors. It is only evaluated if write protection bit FSV1[17] is set.
Explanation of the bits in the Flash Security Vector FSV2[31:0]
Enable Write
Disable Write
Protection
Protection
-
set to ‘0’
set to ‘1’
not available
FSV2[1]
-
set to ‘0’
set to ‘1’
not available
FSV2[2]
-
set to ‘0’
set to ‘1’
not available
FSV2[3]
-
set to ‘0’
set to ‘1’
not available
FSV2[4]
SA12
set to ‘0’
set to ‘1’
FSV2[5]
SA13
set to ‘0’
set to ‘1’
FSV2[6]
SA14
set to ‘0’
set to ‘1’
FSV2[7]
SA15
set to ‘0’
set to ‘1’
FSV2[8]
SA16
set to ‘0’
set to ‘1’
FSV2[9]
SA17
set to ‘0’
set to ‘1’
FSV2[10]
SA18
set to ‘0’
set to ‘1’
FSV2[11]
SA19
set to ‘0’
set to ‘1’
FSV2[12-32]
-
-
-’
FSV1 bit
Sector
FSV2[0]
2.4.4.4
Comment
not available
Register description for Flash Security
For a description of Flash Security registers please refer to Hardware Manual chapter 55.
Fujitsu Microelectronics Europe GmbH
Page 22 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
3 Package and Pin Assignment
3.1 Package
VSS5
MONCLK
MD_2
MD_1
X0
X1
VSS5
X1A
X0A
MD_0
P16_1 / PPG9
P16_0 / PPG8
P20_7
P20_6 / SCK3 / FRCK3
P20_5 / SOT3
P20_4 / SIN3
P20_3
P20_2 / SCK2 / FRCK2
P20_1 / SOT2
P20_0 / SIN2
P16_5
P16_4
P24_7 / INT7
P24_6 / INT6
P24_5 / INT5
P24_4 / INT4
P24_3 / INT3
P24_2 / INT2
P24_1 / INT1
VDD5
A LQFP-120 package will be used for MB91F465KA. The package code is FPT-120P-M21
(120-pin plastic QFP, lead pitch: 0.50mm, 16.0 x 16.0 mm, Theta-ja = 30 degr. C / W)
VSS5 120
MONCLK 119
MD_2 118
MD_1 117
X0 116
X1 115
VSS5 114
X1A 113
X0A 112
MD_0 111
P16_1 110
P16_0 109
P20_7 108
P20_6 107
P20_5 106
P20_4 105
P20_3 104
P20_2 103
P20_1 102
P20_0 101
P16_5 100
P16_4 99
P24_7 98
P24_6 97
P24_5 96
P24_4 95
P24_3 94
P24_2 93
P24_1 92
VDD5 91
MB91F465KA LQFP-120
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDD5
P14_0
P14_1
P14_2
P14_3
P14_4
P14_5
P14_6
P14_7
P15_4
P15_5
P15_6
P15_7
P19_6
VDD5R
VCC18C
VSS5
VDD5
P26_0
P26_1
P27_0
P27_1
P27_2
P27_3
P27_4
P27_5
P27_6
P27_7
P28_0
VDD5
MB91F465KA
QFP-120
VSS5
P24_0
P22_1
P22_0
P15_3
P15_2
P15_1
P15_0
P16_3
P16_2
P17_7
P17_6
P17_5
VSS5
VDD5
P21_7
P21_6
P21_5
P21_4
P21_3
P21_2
P21_1
P21_0
P17_4
P17_3
P17_2
P16_6
P16_7
INITX
VSS5
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VSS5
P24_0 / INT0
P22_1 / TX4
P22_0 / RX4 / INT12
P15_3 / OCU3 / TOT3
P15_2 / OCU2 / TOT2
P15_1 / OCU1 / TOT1
P15_0 / OCU0 / TOT0
P16_3 / PPG11
P16_2 / PPG10
P17_7 / PPG7
P17_6 / PPG6
P17_5 / PPG5
VSS5
VDD5
P21_7
P21_6 / SCK1 / FRCK1
P21_5 / SOT1
P21_4 / SIN1
P21_3
P21_2 / SCK0 / FRCK0
P21_1 / SOT0
P21_0 / SIN0
P17_4 / PPG4
P17_3 / PPG3
P17_2 / PPG2
P16_6
P16_7 / ATGX
INITX
VSS5
VSS5
P28_1 / AN9
P28_2 / AN10
P28_3 / AN11
P28_4 / AN12
AVCC5
AVRH5
AVSS
P29_0 / AN0
P29_1 / AN1
P29_2 / AN2
P29_3 / AN3
P29_4 / AN4
P29_5 / AN5
P29_6 / AN6
P29_7 / AN7
P28_5 / AN13
VSS5
P28_6 / AN14
P28_7 / AN15
P22_4 / SDA0 / INT14
P22_5 / SCL0
P19_0 / SIN4
P19_1 / SOT4
P19_2 / SCK4 / FRCK4
P18_2 / FRCK6
P18_6 / FRCK7
P17_0 / PPG0
P17_1 / PPG1
VDD5
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VSS5
P28_1
P28_2
P28_3
P28_4
AVCC5
AVRH5
AVSS
P29_0
P29_1
P29_2
P29_3
P29_4
P29_5
P29_6
P29_7
P28_5
VSS5
P28_6
P28_7
P22_4
P22_5
P19_0
P19_1
P19_2
P18_2
P18_6
P17_0
P17_1
VDD5
VDD5
P14_0 / ICU0+TIN0 / TIN0 / TTG8/0
P14_1 / ICU1+TIN1 / TIN1 / TTG9/1
P14_2 / ICU2+TIN2 / TIN2 / TTG10/2
P14_3 / ICU3+TIN3 / TIN3 / TTG11/3
P14_4 / ICU4+TIN4 / TIN4 / TTG12/4
P14_5 / ICU5+TIN5 / TIN5 / TTG13/5
P14_6 / ICU6+TIN6 / TIN6 / TTG14/6
P14_7 / ICU7+TIN7 / TIN7 / TTG15/7
P15_4 / OCU4 / TOT4
P15_5 / OCU5 / TOT5
P15_6 / OCU6 / TOT6
P15_7 / OCU7 / TOT7
P19_6 / FRCK5
VDD5R
VCC18C
VSS5
VDD5
P26_0 / AN24
P26_1 / AN25
P27_0 / AN16
P27_1 / AN17
P27_2 / AN18
P27_3 / AN19
P27_4 / AN20
P27_5 / AN21
P27_6 / AN22
P27_7 / AN23
P28_0 / AN8
VDD5
Fujitsu Microelectronics Europe GmbH
Page 23 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
3.2 I/O Pins and their functions
Pin
Number
Name
PFR=1
EPFR=1
Special
Pad
Type
115
X1
-
-
-
TO00_1
116
X0
-
-
-
TO00_0
113
X1A
-
-
-
TO01_1
112
X0A
-
-
-
TO01_0
9
P14_7
ICU7+TIN7
TIN7
TTG15/7
TP04_0
8
P14_6
ICU6+TIN6
TIN6
TTG14/6
TP04_0
7
P14_5
ICU5+TIN5
TIN5
TTG13/5
TP04_0
6
P14_4
ICU4+TIN4
TIN4
TTG12/4
TP04_0
ICU: Input Capture Unit event input
5
P14_3
ICU3+TIN3
TIN3
TTG11/3
TP04_0
TIN: Reload Timer external trigger input
4
P14_2
ICU2+TIN2
TIN2
TTG10/2
TP04_0
TTG: PPG external trigger input
3
P14_1
ICU1+TIN1
TIN1
TTG9/1
TP04_0
Description
4 MHz Quarz Oscillator
32 kHz Quarz Oscillator
General Purpose Port 14
2
P14_0
ICU0+TIN0
TIN0
TTG8/0
TP04_0
13
P15_7
OCU7
TOT7
-
TP04_0
12
P15_6
OCU6
TOT6
-
TP04_0
11
P15_5
OCU5
TOT5
-
TP04_0
10
P15_4
OCU4
TOT4
-
TP04_0
OCU: Output Compare waveform output
86
P15_3
OCU3
TOT3
-
TP04_0
TOT: Reload Timer output
85
P15_2
OCU2
TOT2
-
TP04_0
84
P15_1
OCU1
TOT1
-
TP04_0
83
P15_0
OCU0
TOT0
-
TP04_0
63
P16_7
--
ATGX
-
TP04_0
64
P16_6
--
--
-
TP04_0
100
P16_5
--
--
-
TP04_0
99
P16_4
--
--
-
TP04_0
82
P16_3
PPG11
--
-
TP04_0
81
P16_2
PPG10
--
-
TP04_0
110
P16_1
PPG9
--
-
TP04_0
109
P16_0
PPG8
--
-
TP04_0
80
P17_7
PPG7
-
-
TP04_0
79
P17_6
PPG6
-
-
TP04_0
78
P17_5
PPG5
-
-
TP04_0
67
P17_4
PPG4
-
-
TP04_0
66
P17_3
PPG3
-
-
TP04_0
65
P17_2
PPG2
-
-
TP04_0
59
P17_1
PPG1
-
-
TP04_0
58
P17_0
PPG0
-
-
TP04_0
57
P18_6
--
FRCK7
-
TP04_0
Fujitsu Microelectronics Europe GmbH
General Purpose Port 15
ATGX: ADC external trigger
General Purpose Port 16
PPG: PPG waveform output
General Purpose Port 17
PPG: PPG waveform output
General Purpose Port 19
Page 24 of 67
European MCU Design Centre
56
P18_2
14
55
MB91F465KA preliminary datasheet ver. 1.11
--
FRCK6
-
TP04_0
P19_6
--
FRCK5
-
TP04_0
P19_2
SCK4
FRCK4
-
TP04_0
SCK: LIN-USART serial clock in/out
54
P19_1
SOT4
--
-
TP04_0
SOT: LIN-USART data output
53
P19_0
SIN4
--
-
TP04_0
SIN: LIN-USART data input
108
P20_7
--
--
-
TP04_0
107
P20_6
SCK3
FRCK3
-
TP04_0
General Purpose Port 20
106
P20_5
SOT3
--
-
TP04_0
FRCK: Free Run Timer external clock input
105
P20_4
SIN3
--
-
TP04_0
SCK: LIN-USART serial clock in/out
104
P20_3
--
--
-
TP04_0
SOT: LIN-USART data output
103
P20_2
SCK2
FRCK2
-
TP04_0
SIN: LIN-USART data input
102
P20_1
SOT2
--
-
TP04_0
101
P20_0
SIN2
--
-
TP04_0
75
P21_7
--
--
-
TP04_0
74
P21_6
SCK1
FRCK1
-
TP04_0
General Purpose Port 21
73
P21_5
SOT1
--
-
TP04_0
FRCK: Free Run Timer external clock input
72
P21_4
SIN1
--
-
TP04_0
SCK: LIN-USART serial clock in/out
71
P21_3
--
--
-
TP04_0
SOT: LIN-USART data output
70
P21_2
SCK0
FRCK0
-
TP04_0
SIN: LIN-USART data input
69
P21_1
SOT0
--
-
TP04_0
68
P21_0
SIN0
--
-
TP04_0
52
P22_5
SCL0
-
-
TP02_0
51
P22_4
SDA0
-
INT14
TP02_0
88
P22_1
TX4
-
-
TP04_0
General Purpose Port 22
SCL, SDA: I2C Clock/Data in/out (open
drain)
TX, RX: CAN Transmit / Receive out/in
87
P22_0
RX4
-
INT12
TP04_0
INT: External Interrupt (I2C/CAN-Wakeup)
98
P24_7
INT7
-
--
TP04_0
97
P24_6
INT6
-
--
TP04_0
96
P24_5
INT5
-
--
TP04_0
95
P24_4
INT4
-
--
TP04_0
94
P24_3
INT3
-
-
TP04_0
93
P24_2
INT2
-
-
TP04_0
92
P24_1
INT1
-
-
TP04_0
89
P24_0
INT0
-
-
TP04_0
20
P26_1
-
AN25
-
TP03_0
General Purpose Port 26
19
P26_0
-
AN24
-
TP03_0
AN: ADC Analog input
28
P27_7
-
AN23
-
TP03_0
27
P27_6
-
AN22
-
TP03_0
26
P27_5
-
AN21
-
TP03_0
25
P27_4
-
AN20
-
TP03_0
General Purpose Port 27
24
P27_3
-
AN19
-
TP03_0
AN: ADC Analog input
23
P27_2
-
AN18
-
TP03_0
22
P27_1
-
AN17
-
TP03_0
21
P27_0
-
AN16
-
TP03_0
Fujitsu Microelectronics Europe GmbH
FRCK: Free Run Timer external clock input
General Purpose Port 24
INT: External Interrupt input
Page 25 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
50
P28_7
AN15
-
-
TP03_0
49
P28_6
AN14
-
-
TP03_0
47
P28_5
AN13
-
-
TP03_0
35
P28_4
AN12
-
-
TP03_0
General Purpose Port 28
34
P28_3
AN11
-
-
TP03_0
AN: ADC Analog input
33
P28_2
AN10
-
-
TP03_0
32
P28_1
AN9
-
-
TP03_0
29
P28_0
AN8
-
-
TP03_0
46
P29_7
AN7
-
-
TP03_0
45
P29_6
AN6
-
-
TP03_0
44
P29_5
AN5
-
-
TP03_0
43
P29_4
AN4
-
-
TP03_0
General Purpose Port 29
42
P29_3
AN3
-
-
TP03_0
AN: ADC Analog input
41
P29_2
AN2
-
-
TP03_0
40
P29_1
AN1
-
-
TP03_0
39
P29_0
AN0
-
-
TP03_0
119
MONCLK
-
-
-
TC10_0
Clock Monitor output (threestate)
62
INITX
-
-
-
TC02_0
Initialization input (low active)
118
MD_2
-
-
-
TC01_0
117
MD_1
-
-
-
TC01_0
111
MD_0
-
-
-
TC01_0
1
VDD5
-
-
-
TS02_0
18
VDD5
-
-
-
TS02_0
30
VDD5
-
-
-
TS02_0
60
VDD5
-
-
-
TS02_0
76
VDD5
-
-
-
TS02_0
91
VDD5
-
-
-
TS02_0
17
VSS5
-
-
-
TS00_0
31
VSS5
-
-
-
TS00_0
48
VSS5
-
-
-
TS00_0
61
VSS5
-
-
-
TS00_0
77
VSS5
-
-
-
TS00_0
90
VSS5
-
-
-
TS00_0
114
VSS5
-
-
-
TS00_0
120
VSS5
-
-
-
TS00_0
36
AVCC5
-
-
-
TA03_0
37
AVRH5
-
-
-
TA01_0
Analog High Reference, up to 5 Volt
38
AVSS
-
-
-
TA00_0
Analog Ground Supply
15
VDD5R
-
-
-
TA00_0
Voltage Regulator Supply 5 Volt
16
VCC18C
-
-
-
TA10_0
Voltage Regulator Capacitance pin
Fujitsu Microelectronics Europe GmbH
Device Mode inputs
Power Supply 5 Volt
Ground Supply
Analog Power Supply 5 Volt
Page 26 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
3.3 I/O Pin Types
Pin
Type
Pull Up/
Down
Input Type
STOP
control
Output
Driver
TP02_0
U/D control
CH / A / TTL / CH2
Stop
3 mA
TP03_0
U/D control
CH / A / TTL / CH2
Stop
2/5 mA
General Purpose I/O with 1 analog input line
TP04_0
U/D control
CH / A / TTL / CH2
Stop
2/5 mA
General Purpose I/O
TP05_0
U/D control
CH / A / TTL / CH2
Stop
2/5/30 mA
General Purpose I/O, 30mA SMC, 2 analog lines
General Purpose I/O, 30mA SMC, 1 analog line
Comment
I2C Pin (open drain if PFR=1)
TP05_1
U/D control
CH / A / TTL / CH2
Stop
2/5/30 mA
TC01_0
-
C2
no
-
Mode Pin
TC02_0
Up
C2
no
-
INITX
TC10_0
-
-
no
5 mA
Threestate Output port 5mA for MONCLK
Notes:
•
The pull-up / pull-down resistors are typical 50 kOhm. The controlled pull-up/down's
can be enabled by register setting.
•
Input Types: CH
CMOS Schmitt trigger
CH2
CMOS Schmitt trigger 2
A
CMOS Automotive Schmitt trigger
TTL
TTL
(for input high/low voltages, please see section Operating Conditions)
•
Stop control: Switch to HiZ in STOP mode by register setting, and disable input lines
in STOP if the port is not configuerd to be external interrupt input.
•
Default output driver strength is 3 mA (I2C pins) and 5 mA (all other pins).
Fujitsu Microelectronics Europe GmbH
Page 27 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
4 Recommended Settings
4.1 PLL and Clockgear settings
Please note that for MB91F465KA core base clock frequencies above 80MHz are not allowed
Recommended PLL divider and clockgear settings
Frequency
Parameter
PLL Input (CK)
[MHz]
Clockgear
Parameter
PLL Output (X)
[MHz]
Core base Clock
[MHz]
DIVM
DIVN
DIVG
MULG
4
2
20
16
20
160
80
4
2
19
16
20
152
76
4
2
18
16
20
144
72
4
2
17
16
16
136
68
4
2
16
16
16
128
64
4
2
15
16
16
120
60
4
2
14
16
16
112
56
4
2
13
16
12
104
52
4
2
12
16
12
96
48
4
2
11
16
12
88
44
4
4
10
16
24
160
40
4
4
9
16
24
144
36
4
4
8
16
24
128
32
4
4
7
16
24
112
28
4
6
6
16
24
144
24
4
8
5
16
28
160
20
4
10
4
16
32
160
16
4
12
3
16
32
144
12
Fujitsu Microelectronics Europe GmbH
Page 28 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
4.2 Flash interface settings
Please refer to section 2.4.2.2 ‘Flash access timing settings in CPU mode’ for the recommended Flash
interface settings.
4.3 Clock Modulator settings
The following table shows all possible settings for the Clock Modulator in a base clock frequency
range from 32MHz up to 80MHz.
Please note that Fmax must not exceed 80MHz.
The flash access time settings (see section 2.4.2.2) need to be adjusted according to Fmax while the
PLL and clockgear settings (see section 4.1) should be set according to base clock frequency.
Clock Modulator settings, frequency range and supported supply voltage
Modulation Degree
(k)
1
1
1
1
2
1
1
1
3
1
1
1
1
2
2
3
4
1
1
1
1
1
2
2
3
4
5
1
1
1
1
1
1
2
2
2
3
Random No
(N)
3
3
3
5
3
3
5
7
3
3
5
7
9
3
5
3
3
3
5
7
9
11
3
5
3
3
3
3
5
7
9
11
13
3
5
7
3
Fujitsu Microelectronics Europe GmbH
CMPR
[hex]
026F
026F
026F
02AE
046E
026F
02AE
02ED
066D
026F
02AE
02ED
032C
046E
04AC
066D
086C
026F
02AE
02ED
032C
036B
046E
04AC
066D
086C
0A6B
026F
02AE
02ED
032C
036B
03AA
046E
04AC
04EA
066D
Baseclk
[MHz]
72
68
64
64
64
60
60
60
60
56
56
56
56
56
56
56
56
52
52
52
52
52
52
52
52
52
52
48
48
48
48
48
48
48
48
48
48
Fmin
[MHz]
65.5
62
58.5
55.3
55.3
54.9
51.9
49.3
49.3
51.4
48.6
46.1
43.8
48.6
43.8
46.1
43.8
47.8
45.2
42.9
40.8
38.8
45.2
40.8
42.9
40.8
38.8
44.2
41.8
39.6
37.7
35.9
34.3
41.8
37.7
34.3
39.6
Fmax
[MHz]
79.9
75.3
70.7
75.9
75.9
66.1
71
76.7
76.7
61.6
66.1
71.4
77.6
66.1
77.6
71.4
77.6
57
61.2
66.1
71.8
78.6
61.2
71.8
66.1
71.8
78.6
52.5
56.4
60.9
66.1
72.3
79.9
56.4
66.1
79.9
60.9
Page 29 of 67
European MCU Design Centre
Modulation Degree
(k)
3
4
5
6
1
1
1
1
1
1
2
2
2
3
3
4
5
6
1
1
1
1
1
1
1
2
2
2
3
3
4
5
6
7
1
1
1
1
1
1
1
2
2
2
2
3
3
4
4
5
6
7
8
1
1
1
1
1
1
1
2
2
2
2
MB91F465KA preliminary datasheet ver. 1.11
Random No
(N)
5
3
3
3
3
5
7
9
11
13
3
5
7
3
5
3
3
3
3
5
7
9
11
13
15
3
5
7
3
5
3
3
3
3
3
5
7
9
11
13
15
3
5
7
9
3
5
3
5
3
3
3
3
3
5
7
9
11
13
15
3
5
7
9
Fujitsu Microelectronics Europe GmbH
CMPR
[hex]
06AA
086C
0A6B
0C6A
026F
02AE
02ED
032C
036B
03AA
046E
04AC
04EA
066D
06AA
086C
0A6B
0C6A
026F
02AE
02ED
032C
036B
03AA
03E9
046E
04AC
04EA
066D
06AA
086C
0A6B
0C6A
0E69
026F
02AE
02ED
032C
036B
03AA
03E9
046E
04AC
04EA
0528
066D
06AA
086C
08A8
0A6B
0C6A
0E69
1068
026F
02AE
02ED
032C
036B
03AA
03E9
046E
04AC
04EA
0528
Baseclk
[MHz]
48
48
48
48
44
44
44
44
44
44
44
44
44
44
44
44
44
44
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
40
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
32
32
32
32
32
32
32
32
32
32
32
Fmin
[MHz]
34.3
37.7
35.9
34.3
40.6
38.4
36.4
34.6
33
31.5
38.4
34.6
31.5
36.4
31.5
34.6
33
31.5
37
34.9
33.1
31.5
30
28.7
27.4
34.9
31.5
28.7
33.1
28.7
31.5
30
28.7
27.4
33.3
31.5
29.9
28.4
27.1
25.8
24.7
31.5
28.4
25.8
23.7
29.9
25.8
28.4
23.7
27.1
25.8
24.7
23.7
29.7
28
26.6
25.3
24.1
23
22
28
25.3
23
21.1
Fmax
[MHz]
79.9
66.1
72.3
79.9
48.1
51.6
55.7
60.4
66.1
73
51.6
60.4
73
55.7
73
60.4
66.1
73
43.6
46.8
50.5
54.8
59.9
66.1
73.7
46.8
54.8
66.1
50.5
66.1
54.8
59.9
66.1
73.7
39.2
42
45.3
49.2
53.8
59.3
66.1
42
49.2
59.3
74.7
45.3
59.3
49.2
74.7
53.8
59.3
66.1
74.7
34.7
37.3
40.2
43.6
47.7
52.5
58.6
37.3
43.6
52.5
66.1
Page 30 of 67
European MCU Design Centre
Modulation Degree
(k)
3
3
3
4
4
5
6
7
8
9
MB91F465KA preliminary datasheet ver. 1.11
Random No
(N)
3
5
7
3
5
3
3
3
3
3
Fujitsu Microelectronics Europe GmbH
CMPR
[hex]
066D
06AA
06E7
086C
08A8
0A6B
0C6A
0E69
1068
1267
Baseclk
[MHz]
32
32
32
32
32
32
32
32
32
32
Fmin
[MHz]
26.6
23
20.3
25.3
21.1
24.1
23
22
21.1
20.3
Fmax
[MHz]
40.2
52.5
75.9
43.6
66.1
47.7
52.5
58.6
66.1
75.9
Page 31 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
5 Interrupt Vector Table
This section shows the allocation of interrupt and interrupt vector/interrupt register.
Interrupt number
Interrupt level
*1
*2
Interrupt vector
Interrupt
Decimal
Hexadecimal
Setting
Register
Register
address
Offset
Default Vector
address
Reset
0
00
-
-
0x3FC
0x000FFFFC
Mode vector
1
01
-
-
0x3F8
0x000FFFF8
System reserved
2
02
-
-
0x3F4
0x000FFFF4
System reserved
3
03
-
-
0x3F0
0x000FFFF0
System reserved
4
04
-
-
0x3EC
0x000FFFEC
CPU supervisor mode
*6
(INT #5 instruction)
5
05
-
-
0x3E8
0x000FFFE8
Memory Protection
*6
exception
6
06
-
-
0x3E4
0x000FFFE4
Co-processor
*5
fault trap
7
07
-
-
0x3E0
0x000FFFE0
Co-processor
*5
error trap
8
08
-
-
0x3DC
0x000FFFDC
9
09
-
-
0x3D8
0x000FFFD8
10
0A
-
-
0x3D4
0x000FFFD4
INTE instruction
Instruction break
*5
exception
*5
Fujitsu Microelectronics Europe GmbH
RN
Page 32 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Interrupt number
Interrupt level
*1
*2
Interrupt vector
Interrupt
Decimal
Hexadecimal
Setting
Register
Register
address
Offset
Default Vector
address
11
0B
-
-
0x3D0
0x000FFFD0
12
0C
-
-
0x3CC
0x000FFFCC
13
0D
-
-
0x3C8
0x000FFFC8
Undefined instruction
exception
14
0E
-
-
0x3C4
0x000FFFC4
NMI request (n.a. on
MB91F465KA)
15
0F
FH fixed
0x3C0
0x000FFFC0
External Interrupt 0
16
10
0x3BC
0x000FFFBC
0, 16
0x3B8
0x000FFFB8
1, 17
0x3B4
0x000FFFB4
2, 18
0x3B0
0x000FFFB0
3, 19
0x3AC
0x000FFFAC
20
0x3A8
0x000FFFA8
21
0x3A4
0x000FFFA4
22
0x3A0
0x000FFFA0
23
0x39C
0x000FFF9C
0x398
0x000FFF98
0x394
0x000FFF94
0x390
0x000FFF90
Operand break trap
Step trace trap
*5
*5
NMI interrupt (tool)
*5
ICR00
External Interrupt 1
17
11
External Interrupt 2
18
12
ICR01
External Interrupt 3
19
13
External Interrupt 4
20
14
ICR02
External Interrupt 5
21
15
External Interrupt 6
22
16
ICR03
External Interrupt 7
23
17
reserved
24
18
ICR04
reserved
25
19
reserved
26
1A
ICR05
reserved
27
1B
Fujitsu Microelectronics Europe GmbH
RN
0x440
0x441
0x442
0x443
0x444
0x445
Page 33 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Interrupt number
Interrupt level
*1
*2
Interrupt vector
Interrupt
External Interrupt 12
Decimal
Hexadecimal
28
1C
reserved
29
1D
External Interrupt 14
30
1E
Setting
Register
Register
address
ICR06
0x446
ICR07
reserved
31
1F
Reload Timer 0
32
20
ICR08
Reload Timer 1
33
21
Reload Timer 2
34
22
ICR09
Reload Timer 3
35
23
Reload Timer 4
36
24
ICR10
Reload Timer 5
37
25
Reload Timer 6
38
26
ICR11
Reload Timer 7
39
27
Free Run Timer 0
40
28
ICR12
Free Run Timer 1
41
29
Free Run Timer 2
42
2A
ICR13
Free Run Timer 3
43
2B
Free Run Timer 4
44
2C
ICR14
Free Run Timer 5
45
2D
Fujitsu Microelectronics Europe GmbH
Offset
Default Vector
address
0x38C
0x000FFF8C
0x388
0x000FFF88
0x384
0x000FFF84
0x380
0x000FFF80
0x37C
0x000FFF7C
4, 32
0x378
0x000FFF78
5, 33
0x374
0x000FFF74
34
0x370
0x000FFF70
35
0x36C
0x000FFF6C
36
0x368
0x000FFF68
37
0x364
0x000FFF64
38
0x360
0x000FFF60
39
0x35C
0x000FFF5C
40
0x358
0x000FFF58
41
0x354
0x000FFF54
42
0x350
0x000FFF50
43
0x34C
0x000FFF4C
44
0x348
0x000FFF48
45
RN
0x447
0x448
0x449
0x44A
0x44B
0x44C
0x44D
0x44E
Page 34 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Interrupt number
Interrupt level
*1
*2
Interrupt vector
Interrupt
Free Run Timer 6
Decimal
Hexadecimal
46
2E
Free Run Timer 7
47
2F
reserved
48
30
Setting
Register
Register
address
ICR15
0x44F
ICR16
reserved
49
31
reserved
50
32
51
33
CAN 4
52
34
53
35
USART (LIN) 0 RX
54
36
55
37
USART (LIN) 1 RX
56
38
57
39
USART (LIN) 2 RX
58
3A
0x000FFF44
46
0x340
0x000FFF40
47
0x33C
0x000FFF3C
0x338
0x000FFF38
0x334
0x000FFF34
0x330
0x000FFF30
0x32C
0x000FFF2C
0x328
0x000FFF28
0x324
0x000FFF24
6, 48
0x320
0x000FFF20
7, 49
0x31C
0x000FFF1C
8, 50
0x318
0x000FFF18
9, 51
0x314
0x000FFF14
52
0x453
ICR20
USART (LIN) 1 TX
0x344
0x452
ICR19
USART (LIN) 0 TX
RN
0x451
ICR18
reserved
Default Vector
address
0x450
ICR17
reserved
Offset
0x454
ICR21
0x455
USART (LIN) 2 TX
59
3B
0x310
0x000FFF10
53
USART (LIN) 3 RX
60
3C
0x30C
0x000FFF0C
54
0x308
0x000FFF08
55
0x304
0x000FFF04
0x300
0x000FFF00
ICR22
USART (LIN) 3 TX
61
3D
System reserved
62
3E
Delayed Interrupt
63
3F
Fujitsu Microelectronics Europe GmbH
ICR23
0x456
*4
0x457
Page 35 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Interrupt number
Interrupt level
*1
*2
Interrupt vector
Interrupt
System reserved
System reserved
*3
*3
USART (LIN, FIFO) 4 RX
Decimal
Hexadecimal
64
40
65
41
66
42
Setting
Register
Register
address
(ICR24)
(0x458)
ICR25
USART (LIN, FIFO) 4 TX
67
43
reserved
68
44
ICR26
reserved
69
45
reserved
70
46
ICR27
reserved
71
47
reserved
72
48
ICR28
reserved
73
49
I2C 0
74
4A
ICR29
reserved
75
4B
reserved
76
4C
ICR30
reserved
77
4D
reserved
78
4E
ICR31
reserved
79
4F
reserved
80
50
Fujitsu Microelectronics Europe GmbH
ICR32
Offset
Default Vector
address
0x2FC
0x000FFEFC
0x2F8
0x000FFEF8
0x2F4
0x000FFEF4
10, 56
0x2F0
0x000FFEF0
11, 57
0x2EC
0x000FFEEC
12, 58
0x2E8
0x000FFEE8
13, 59
0x2E4
0x000FFEE4
60
0x2E0
0x000FFEE0
61
0x2DC
0x000FFEDC
62
0x2D8
0x000FFED8
63
0x2D4
0x000FFED4
0x2D0
0x000FFED0
0x2CC
0x000FFECC
64
0x2C8
0x000FFEC8
65
0x2C4
0x000FFEC4
66
0x2C0
0x000FFEC0
67
0x2BC
0x000FFEBC
68
RN
0x459
0x45A
0x45B
0x45C
0x45D
0x45E
0x45F
0x460
Page 36 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Interrupt number
Interrupt level
*1
*2
Interrupt vector
Interrupt
Decimal
Hexadecimal
reserved
81
51
reserved
82
52
Setting
Register
ICR33
reserved
83
53
reserved
84
54
ICR34
reserved
85
55
reserved
86
56
ICR35
reserved
87
57
reserved
88
58
ICR36
reserved
89
59
reserved
90
5A
ICR37
reserved
91
5B
Input Capture 0
92
5C
ICR38
Input Capture 1
93
5D
Input Capture 2
94
5E
ICR39
Input Capture 3
95
5F
Input Capture 4
96
60
ICR40
Input Capture 5
97
61
Input Capture 6
98
62
Fujitsu Microelectronics Europe GmbH
ICR41
Register
address
Offset
Default Vector
address
RN
0x2B8
0x000FFEB8
69
0x2B4
0x000FFEB4
70
0x2B0
0x000FFEB0
71
0x2AC
0x000FFEAC
72
0x2A8
0x000FFEA8
73
0x2A4
0x000FFEA4
74
0x2A0
0x000FFEA0
75
0x29C
0x000FFE9C
76
0x298
0x000FFE98
77
0x294
0x000FFE94
78
0x290
0x000FFE90
79
0x28C
0x000FFE8C
80
0x288
0x000FFE88
81
0x284
0x000FFE84
82
0x280
0x000FFE80
83
0x27C
0x000FFE7C
84
0x278
0x000FFE78
85
0x274
0x000FFE74
86
0x461
0x462
0x463
0x464
0x465
0x466
0x467
0x468
0x469
Page 37 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Interrupt number
Interrupt level
*1
*2
Interrupt vector
Interrupt
Decimal
Hexadecimal
Input Capture 7
99
63
Output Compare 0
100
64
Setting
Register
ICR42
Output Compare 1
101
65
Output Compare 2
102
66
103
67
Output Compare 4
104
68
105
69
Output Compare 6
106
6A
107
6B
reserved
108
6C
109
6D
System reserved
110
6E
ICR47
System reserved
111
6F
Prog. Pulse Gen. 0
112
70
ICR48
Prog. Pulse Gen. 1
113
71
Prog. Pulse Gen. 2
114
72
ICR49
Prog. Pulse Gen. 3
115
73
Prog. Pulse Gen. 4
116
74
Fujitsu Microelectronics Europe GmbH
ICR50
0x270
0x000FFE70
87
0x26C
0x000FFE6C
88
0x268
0x000FFE68
89
0x264
0x000FFE64
90
0x260
0x000FFE60
91
0x25C
0x000FFE5C
92
0x258
0x000FFE58
93
0x254
0x000FFE54
94
0x250
0x000FFE50
95
0x24C
0x000FFE4C
0x248
0x000FFE48
0x244
0x000FFE44
0x240
0x000FFE40
0x23C
0x000FFE3C
15, 96
0x238
0x000FFE38
97
0x234
0x000FFE34
98
0x230
0x000FFE30
99
0x22C
0x000FFE2C
100
0x46D
ICR46
reserved
RN
0x46C
ICR45
Output Compare 7
Default Vector
address
0x46B
ICR44
Output Compare 5
Offset
0x46A
ICR43
Output Compare 3
Register
address
0x46E
*4
0x46F
0x470
0x471
0x472
Page 38 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Interrupt number
Interrupt level
*1
*2
Interrupt vector
Interrupt
Decimal
Hexadecimal
Prog. Pulse Gen. 5
117
75
Prog. Pulse Gen. 6
118
76
Setting
Register
ICR51
Prog. Pulse Gen. 7
119
77
Prog. Pulse Gen. 8
120
78
ICR52
Prog. Pulse Gen. 9
121
79
Prog. Pulse Gen. 10
122
7A
ICR53
Prog. Pulse Gen. 11
123
7B
reserved
124
7C
ICR54
Register
address
Offset
Default Vector
address
RN
0x228
0x000FFE28
101
0x224
0x000FFE24
102
0x220
0x000FFE20
103
0x21C
0x000FFE1C
104
0x218
0x000FFE18
105
0x214
0x000FFE14
106
0x210
0x000FFE10
107
0x20C
0x000FFE0C
108
0x473
0x474
0x475
0x476
reserved
125
7D
0x208
0x000FFE08
109
reserved
126
7E
0x204
0x000FFE04
110
111
ICR55
0x477
reserved
127
7F
0x200
0x000FFE00
reserved
128
80
0x1FC
0x000FFDFC
ICR56
0x478
reserved
129
81
0x1F8
0x000FFDF8
reserved
130
82
0x1F4
0x000FFDF4
0x1F0
0x000FFDF0
0x1EC
0x000FFDEC
ICR57
reserved
131
83
Real Time Clock
132
84
Fujitsu Microelectronics Europe GmbH
ICR58
0x479
0x47A
Page 39 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Interrupt number
Interrupt level
*1
*2
Interrupt vector
Interrupt
Decimal
Hexadecimal
Calibration Unit
133
85
A/D Converter 0
134
86
Setting
Register
ICR59
reserved
135
87
reserved
136
88
ICR60
reserved
137
89
Low Voltage Detection
138
8A
ICR61
reserved
139
8B
Timebase Overflow
140
8C
ICR62
PLL Clock Gear
141
8D
DMA Controller
142
8E
ICR63
Register
address
Offset
Default Vector
address
0x1E8
0x000FFDE8
0x1E4
0x000FFDE4
0x1E0
0x000FFDE0
0x1DC
0x000FFDDC
0x1D8
0x000FFDD8
0x1D4
0x000FFDD4
0x1D0
0x000FFDD0
0x1CC
0x000FFDCC
0x1C8
0x000FFDC8
0x1C4
0x000FFDC4
0x1C0
0x000FFDC0
RN
14, 112
0x47B
0x47C
0x47D
0x47E
0x47F
Main/Sub OSC stability wait
143
8F
Security vector
144
90
-
-
0x1BC
0x000FFDBC
Used by the INT
instruction.
145
to
255
91
to
FF
-
-
0x1B8
to
0x000
0x000FFDB8
to
0x000FFC00
Notes:
*1
The ICRs are located in the interrupt controller and set the interrupt level for each interrupt request.
An ICR is provided for each interrupt request.
Fujitsu Microelectronics Europe GmbH
Page 40 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
*2
The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset
to the table base register value (TBR). The TBR specifies the top of the EIT vector table. The
addresses listed in the table are for the default TBR value (0x000FFC00). The TBR is initialized to this
value by a reset. After execution of the internal boot ROM TBR is set to 0x000FFC00.
*3
Used by REALOS
*4
ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0x0C03 : IOS[0])
*5
System reserved
*6
Memory Protection Unit (MPU) support
Fujitsu Microelectronics Europe GmbH
Page 41 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
6 I/O Map
This section shows the association between memory space and each register of peripheral resources.
• Table convention:
Address
000000H
Address offset/Register name
+0
+1
+2
PDRD[R/W]
PDR2[R/W]
PDR1[R/W]
xxxxxxxx
xxxxxxxx
xxxxxxxx
+3
PDR3[R/W]
xxxxxxxx
MSB
Block
T-unit
Port data register
LSB
Read/Write attribute (R: Read, W: Write)
Register initial value ("0", "1", "X" : undefined, "-" : not implemented)
Register name (First column register is 4n address,
Second column register is 4n+2 address...)
Leftmost register address
(For Word access, first register becomes MSB side of the data.)
Note: Bit value of register shows initial values as follows.
• "1": Initial value is "1".
• "0": Initial value is "0".
• "X": Initial value is indeterminate.
• "-": No physical register exists in the position.
Do not use other data access attributes to access data.
Fujitsu Microelectronics Europe GmbH
Page 42 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Table 6-1 I/O Map
Register
Address
+0
+1
000000H
000008H
Block
+2
+3
reserved
00000CH
res.
res.
PDR14 [R/W]
XXXXXXXX
PDR15 [R/W]
XXXXXXXX
000010H
PDR16 [R/W]
XXXXXXXX
PDR17 [R/W]
XXXXXXXX
PDR18 [R/W]
-X---X--
PDR19 [R/W]
- X - - - XXX
000014H
PDR20 [R/W]
XXXXXXXX
PDR21 [R/W]
XXXXXXXX
PDR22 [R/W]
- - XX - - XX
res.
000018H
PDR24 [R/W]
XXXXXXXX
res.
PDR26 [R/W]
- - - - - - XX
PDR27 [R/W]
XXXXXXXX
00001CH
PDR28 [R/W]
XXXXXXXX
PDR29 [R/W]
XXXXXXXX
res.
res.
000020H
00002CH
R-bus
Port Data
Register
reserved
000030H
EIRR0 [R/W]
00000000
ENIR0 [R/W]
00000000
ELVR0 [R/W]
00000000 00000000
Ext. INT 0-7
NMI
000034H
EIRR1 [R/W]
00000000
ENIR1 [R/W]
00000000
ELVR1 [R/W]
00000000 00000000
Ext. INT 8-15
000038H
DICR [R/W]
-------0
HRCL [R/W]
0 - - 11111
00003CH
000040H
000044H
RBSYNC
*1
DLYI/I-unit
reserved
SCR00 [R/W,W]
00000000
SMR00 [R/W,W]
00000000
ESCR00 [R/W]
00000X00
ECCR00
[R/W,R,W]
-00000XX
Fujitsu Microelectronics Europe GmbH
RDR00/TDR00
[R/W]
00000000
SSR00 [R/W,R]
00001000
USART (LIN)
0
res.
Page 43 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
Block
+0
+1
+2
+3
SCR01 [R/W,W]
00000000
SMR01 [R/W,W]
00000000
SSR01 [R/W,R]
00001000
RDR01/TDR01
[R/W]
00000000
00004CH
ESCR01 [R/W]
00000X00
ECCR01
[R/W,R,W]
-00000XX
000050H
SCR02 [R/W,W]
00000000
SMR02 [R/W,W]
00000000
000054H
ESCR02 [R/W]
00000X00
ECCR02
[R/W,R,W]
-00000XX
000058H
SCR03 [R/W,W]
00000000
SMR03 [R/W,W]
00000000
00005CH
ESCR03 [R/W]
00000X00
ECCR03
[R/W,R,W]
-00000XX
000060H
SCR04 [R/W,W]
00000000
SMR04 [R/W,W]
00000000
SSR04 [R/W,R]
00001000
RDR04/TDR04
[R/W]
00000000
000064H
ESCR04 [R/W]
00000X00
ECCR04
[R/W,R,W]
-00000XX
FSR04 [R]
- - - 00000
FCR04 [R/W]
0001 - 000
000048H
000068H
00007CH
USART (LIN)
1
res.
RDR02/TDR02
[R/W]
00000000
SSR02 [R/W,R]
00001000
USART (LIN)
2
res.
RDR03/TDR03
[R/W]
00000000
SSR03 [R/W,R]
00001000
USART (LIN)
3
res.
USART (LIN)
4
with FIFO
reserved
000080H
BGR100 [R/W]
00000000
BGR000 [R/W]
00000000
BGR101 [R/W]
00000000
BGR001 [R/W]
00000000
000084H
BGR102 [R/W]
00000000
BGR002 [R/W]
00000000
BGR103 [R/W]
00000000
BGR003 [R/W]
00000000
000088H
BGR104 [R/W]
00000000
BGR004 [R/W]
00000000
res.
res.
Baudrate
Generator
USART (LIN)
0-7
00008CH
-
reserved
0000CCH
Fujitsu Microelectronics Europe GmbH
Page 44 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
Block
+0
+1
+2
+3
0000D0H
IBCR0 [R/W]
00000000
IBSR0 [R]
00000000
ITBAH0 [R/W]
- - - - - - 00
ITBAL0 [R/W]
00000000
0000D4H
ITMKH0 [R/W]
00 - - - - 11
ITMKL0 [R/W]
11111111
ISMK0 [R/W]
01111111
ISBA0 [R/W]
- 0000000
0000D8H
res.
IDAR0 [R/W]
00000000
ICCR0 [R/W]
- 0011111
res.
0000DCH
0000FCH
I2C 0
reserved
000100H
GCN10 [R/W]
00110010 00010000
res.
GCN20 [R/W]
- - - - 0000
PPG Control
0-3
000104H
GCN11 [R/W]
00110010 00010000
res.
GCN21 [R/W]
- - - - 0000
PPG Control
4-7
000108H
GCN12 [R/W]
00110010 00010000
res.
GCN22 [R/W]
- - - - 0000
PPG Control
8-11
000110H
PTMR00 [R]
11111111 11111111
000114H
PDUT00 [W]
XXXXXXXX XXXXXXXX
000118H
PTMR01 [R]
11111111 11111111
00011CH
PDUT01 [W]
XXXXXXXX XXXXXXXX
000120H
PTMR02 [R]
11111111 11111111
000124H
PDUT02 [W]
XXXXXXXX XXXXXXXX
000128H
PTMR03 [R]
11111111 11111111
00012CH
PDUT03 [W]
XXXXXXXX XXXXXXXX
PCSR00 [W]
XXXXXXXX XXXXXXXX
PPG 0
PCNH00 [R/W]
0000000 -
PCNL00 [R/W]
000000 - 0
PCSR01 [W]
XXXXXXXX XXXXXXXX
PPG 1
PCNH01 [R/W]
0000000 -
PCNL01 [R/W]
000000 - 0
PCSR02 [W]
XXXXXXXX XXXXXXXX
PPG 2
PCNH02 [R/W]
0000000 -
PCNL02 [R/W]
000000 - 0
PCSR03 [W]
XXXXXXXX XXXXXXXX
PPG 3
Fujitsu Microelectronics Europe GmbH
PCNH03 [R/W]
0000000 -
PCNL03 [R/W]
000000 - 0
Page 45 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
+0
+1
000130H
PTMR04 [R]
11111111 11111111
000134H
PDUT04 [W]
XXXXXXXX XXXXXXXX
000138H
PTMR05 [R]
11111111 11111111
00013CH
PDUT05 [W]
XXXXXXXX XXXXXXXX
000140H
PTMR06 [R]
11111111 11111111
000144H
PDUT06 [W]
XXXXXXXX XXXXXXXX
000148H
PTMR07 [R]
11111111 11111111
00014CH
PDUT07 [W]
XXXXXXXX XXXXXXXX
000150H
PTMR08 [R]
11111111 11111111
000154H
PDUT08 [W]
XXXXXXXX XXXXXXXX
000158H
PTMR09 [R]
11111111 11111111
00015CH
PDUT09 [W]
XXXXXXXX XXXXXXXX
000160H
PTMR10 [R]
11111111 11111111
000164H
PDUT10 [W]
XXXXXXXX XXXXXXXX
000168H
PTMR11 [R]
11111111 11111111
00016CH
PDUT11 [W]
XXXXXXXX XXXXXXXX
Block
+2
+3
PCSR04 [W]
XXXXXXXX XXXXXXXX
PPG 4
PCNH04 [R/W]
0000000 -
PCNL04 [R/W]
000000 - 0
PCSR05 [W]
XXXXXXXX XXXXXXXX
PPG 5
PCNH05 [R/W]
0000000 -
PCNL05 [R/W]
000000 - 0
PCSR06 [W]
XXXXXXXX XXXXXXXX
PPG 6
PCNH06 [R/W]
0000000 -
PCNL06 [R/W]
000000 - 0
PCSR07 [W]
XXXXXXXX XXXXXXXX
PPG 7
PCNH07 [R/W]
0000000 -
PCNL07 [R/W]
000000 - 0
PCSR08 [W]
XXXXXXXX XXXXXXXX
PPG 8
PCNH08 [R/W]
0000000 -
PCNL08 [R/W]
000000 - 0
PCSR09 [W]
XXXXXXXX XXXXXXXX
PPG 9
PCNH09 [R/W]
0000000 -
PCNL09 [R/W]
000000 - 0
PCSR10 [W]
XXXXXXXX XXXXXXXX
PPG 10
PCNH10 [R/W]
0000000 -
PCNL10 [R/W]
000000 - 0
PCSR11 [W]
XXXXXXXX XXXXXXXX
PPG 11
Fujitsu Microelectronics Europe GmbH
PCNH11 [R/W]
0000000 -
PCNL11 [R/W]
000000 - 0
Page 46 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
+0
+1
000170H
00017CH
Block
+2
+3
res.
ICS23 [R/W]
00000000
reserved
ICS01 [R/W]
00000000
000180H
res.
000184H
IPCP0 [R]
XXXXXXXX XXXXXXXX
IPCP1 [R]
XXXXXXXX XXXXXXXX
000188H
IPCP2 [R]
XXXXXXXX XXXXXXXX
IPCP3 [R]
XXXXXXXX XXXXXXXX
00018CH
OCS01 [R/W]
- - - 0 - - 00 0000 - - 00
OCS23 [R/W]
- - - 0 - - 00 0000 - - 00
000190H
OCCP0 [R/W]
XXXXXXXX XXXXXXXX
OCCP1 [R/W]
XXXXXXXX XXXXXXXX
000194H
OCCP2 [R/W]
XXXXXXXX XXXXXXXX
OCCP3 [R/W]
XXXXXXXX XXXXXXXX
000198H
00019CH
0001A0H
Input
Capture
0-3
Output
Compare
0-3
reserved
ADERH [R/W]
00000000 00000000
ADERL [R/W]
00000000 00000000
0001A4
ADCS1 [R/W]
00000000
ADCS0 [R/W]
00000000
ADCR1 [R]
000000XX
ADCR0 [R]
XXXXXXXX
0001A8H
ADCT1 [R/W]
00010000
ADCT0 [R/W]
00101100
ADSCH [R/W]
- - - 00000
ADECH [R/W]
- - - 00000
0001ACH
A/D
Converter
reserved
0001B0H
TMRLR0 [W]
XXXXXXXX XXXXXXXX
0001B4H
res.
Fujitsu Microelectronics Europe GmbH
TMR0 [R]
XXXXXXXX XXXXXXXX
TMCSRH0
[R/W]
- - - 00000
TMCSRL0
[R/W]
0 - 000000
Reload Timer
0
Page 47 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
+0
+1
Block
+2
+3
0001B8H
TMRLR1 [W]
XXXXXXXX XXXXXXXX
TMR1 [R]
XXXXXXXX XXXXXXXX
0001BCH
res.
0001C0H
TMRLR2 [W]
XXXXXXXX XXXXXXXX
0001C4H
res.
0001C8H
TMRLR3 [W]
XXXXXXXX XXXXXXXX
0001CCH
res.
0001D0H
TMRLR4 [W]
XXXXXXXX XXXXXXXX
0001D4H
res.
0001D8H
TMRLR5 [W]
XXXXXXXX XXXXXXXX
0001DCH
res.
0001E0H
TMRLR6 [W]
XXXXXXXX XXXXXXXX
0001E4H
res.
0001E8H
TMRLR7 [W]
XXXXXXXX XXXXXXXX
0001ECH
res.
TMCSRH7
[R/W]
- - - 00000
TMCSRL7
[R/W]
0 - 000000
0001F0H
TCDT0 [R/W]
XXXXXXXX XXXXXXXX
res.
TCCS0 [R/W]
00000000
TMCSRH1
[R/W]
- - - 00000
TMCSRL1
[R/W]
0 - 000000
TMR2 [R]
XXXXXXXX XXXXXXXX
TMCSRH2
[R/W]
- - - 00000
TMCSRL2
[R/W]
0 - 000000
TMR3 [R]
XXXXXXXX XXXXXXXX
TMCSRH3
[R/W]
- - - 00000
TMCSRL3
[R/W]
0 - 000000
TMR4 [R]
XXXXXXXX XXXXXXXX
TMCSRH4
[R/W]
- - - 00000
TMCSRL4
[R/W]
0 - 000000
TMR5 [R]
XXXXXXXX XXXXXXXX
TMCSRH5
[R/W]
- - - 00000
TMCSRL5
[R/W]
0 - 000000
TMR6 [R]
XXXXXXXX XXXXXXXX
TMCSRH6
[R/W]
- - - 00000
Reload Timer
1
TMCSRL6
[R/W]
0 - 000000
TMR7 [R]
XXXXXXXX XXXXXXXX
Reload Timer
2
(PPG 4-5)
Reload Timer
3
(PPG 6-7)
Reload Timer
4
(PPG 8-9)
Reload Timer
5
(PPG 10-11)
Reload Timer
6
(PPG 12-13)
Reload Timer
7
(PPG 14-15)
(ADC)
Free Running
Timer 0
(ICU 0-1)
Fujitsu Microelectronics Europe GmbH
Page 48 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
+0
0001F4H
+1
TCDT1 [R/W]
XXXXXXXX XXXXXXXX
Block
+2
+3
res.
TCCS1 [R/W]
00000000
Free Running
Timer 1
(ICU 2-3)
0001F8H
TCDT2 [R/W]
XXXXXXXX XXXXXXXX
res.
TCCS2 [R/W]
00000000
Free Running
Timer 2
(OCU 0-1)
0001FCH
TCDT3 [R/W]
XXXXXXXX XXXXXXXX
res.
TCCS3 [R/W]
00000000
Free Running
Timer 3
(OCU 2-3)
000200H
DMACA0 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
00023CH
reserved
000240H
DMACR [R/W]
00 - - 0000
Fujitsu Microelectronics Europe GmbH
DMAC
reserved
Page 49 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
+0
+1
000244H
00024CH
reserved
000250H
reserved
000254H
reserved
000258H
0002CCH
reserved
ICS045 [R/W]
00000000
Block
+2
+3
res.
ICS67 [R/W]
00000000
0002D0H
res.
0002D4H
IPCP4 [R]
XXXXXXXX XXXXXXXX
IPCP5 [R]
XXXXXXXX XXXXXXXX
0002D8H
IPCP6 [R]
XXXXXXXX XXXXXXXX
IPCP7 [R]
XXXXXXXX XXXXXXXX
0002DCH
OCS45 [R/W]
- - - 0 - - 00 0000 - - 00
OCS67 [R/W]
- - - 0 - - 00 0000 - - 00
0002E0H
OCCP4 [R/W]
XXXXXXXX XXXXXXXX
OCCP5 [R/W]
XXXXXXXX XXXXXXXX
0002E4H
OCCP6 [R/W]
XXXXXXXX XXXXXXXX
OCCP7 [R/W]
XXXXXXXX XXXXXXXX
0002E8H
0002ECH
0002F0H
Input
Capture
4-7
Output
Compare
4-7
reserved
TCDT4 [R/W]
XXXXXXXX XXXXXXXX
res.
TCCS4 [R/W]
00000000
Free Running
Timer 4
(ICU 4-5)
0002F4H
TCDT5 [R/W]
XXXXXXXX XXXXXXXX
res.
TCCS5 [R/W]
00000000
Free Running
Timer 5
(ICU 6-7)
0002F8H
TCDT6 [R/W]
XXXXXXXX XXXXXXXX
res.
TCCS6 [R/W]
00000000
Free Running
Timer 6
0002FCH
TCDT7 [R/W]
XXXXXXXX XXXXXXXX
res.
TCCS7 [R/W]
00000000
Free Running
Timer 7
Fujitsu Microelectronics Europe GmbH
Page 50 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
+0
+1
000300H
00038CH
000390H
Block
+2
+3
reserved
ROMS [R]
11111111 01000011
ROM Select
Register
res.
000394H
0003ECH
reserved
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H
00043CH
reserved
Bit Search
Module
000440H
ICR00 [R/W]
---11111
ICR01 [R/W]
---11111
ICR02 [R/W]
---11111
ICR03 [R/W]
---11111
000444H
ICR04 [R/W]
---11111
ICR05 [R/W]
---11111
ICR06 [R/W]
---11111
ICR07 [R/W]
---11111
000448H
ICR08 [R/W]
---11111
ICR09 [R/W]
---11111
ICR10 [R/W]
---11111
ICR11 [R/W]
---11111
00044CH
ICR12 [R/W]
---11111
ICR13 [R/W]
---11111
ICR14 [R/W]
---11111
ICR15 [R/W]
---11111
000450H
ICR16 [R/W]
---11111
ICR17 [R/W]
---11111
ICR18 [R/W]
---11111
ICR19 [R/W]
---11111
000454H
ICR20 [R/W]
---11111
ICR21 [R/W]
---11111
ICR22 [R/W]
---11111
ICR23 [R/W]
---11111
000458H
ICR24 [R/W]
---11111
ICR25 [R/W]
---11111
ICR26 [R/W]
---11111
ICR27 [R/W]
---11111
00045CH
ICR28 [R/W]
---11111
ICR29 [R/W]
---11111
ICR30 [R/W]
---11111
ICR31 [R/W]
---11111
Fujitsu Microelectronics Europe GmbH
Interrupt
Control
Unit
Page 51 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
Block
+0
+1
+2
+3
000460H
ICR32 [R/W]
---11111
ICR33 [R/W]
---11111
ICR34 [R/W]
---11111
ICR35 [R/W]
---11111
000464H
ICR36 [R/W]
---11111
ICR37 [R/W]
---11111
ICR38 [R/W]
---11111
ICR39 [R/W]
---11111
000468H
ICR40 [R/W]
---11111
ICR41 [R/W]
---11111
ICR42 [R/W]
---11111
ICR43 [R/W]
---11111
00046CH
ICR44 [R/W]
---11111
ICR45 [R/W]
---11111
ICR46 [R/W]
---11111
ICR47 [R/W]
---11111
000470H
ICR48 [R/W]
---11111
ICR49 [R/W]
---11111
ICR50 [R/W]
---11111
ICR51 [R/W]
---11111
000474H
ICR52 [R/W]
---11111
ICR53 [R/W]
---11111
ICR54 [R/W]
---11111
ICR55 [R/W]
---11111
000478H
ICR56 [R/W]
---11111
ICR57 [R/W]
---11111
ICR58 [R/W]
---11111
ICR59 [R/W]
---11111
00047CH
ICR60 [R/W]
---11111
ICR61 [R/W]
---11111
ICR62 [R/W]
---11111
ICR63 [R/W]
---11111
000480H
RSRR [R/W]
10000000
STCR [R/W]
00110011
TBCR [R/W]
X0000X00
CTBR [W]
XXXXXXXX
000484H
CLKR [R/W]
00000000
WPR [W]
XXXXXXXX
DIVR0 [R/W]
00000011
DIVR1 [R/W]
00000000
000488H
res.
res.
res.
res.
00048CH
PLLDIVM [R/W]
- - - - 0000
PLLDIVN [R/W]
- - 000000
PLLDIVG [R/W]
- - - - 0000
PLLMULG [W]
00000000
000490H
PLLCTRL [R/W]
- - - - 0000
res.
res.
res.
000494H
OSCC1 [R/W]
- - - - - 010
OSCS1 [R/W]
00001111
OSCC2 [R/W]
- - - - - 010
OSCS2 [R/W]
00001111
000498H
PORTEN [R/W]
- - - - - - 00
res.
res.
res.
Fujitsu Microelectronics Europe GmbH
Clock
Control
Unit
PLL Clock
Gear Unit
Main/Sub
Oscillator
Control
Port Input
Enable Control
Page 52 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
Block
+0
+1
+2
+3
0004A0H
res.
WTCER [R/W]
- - - - - - 00
0004A4H
res.
0004A8H
WTHR [R/W]
- - - 00000
WTMR [R/W]
- - 000000
WTSR [R/W]
- - 000000
res.
0004ACH
CSVTR [R/W]
- - - 00010
CSVCR [R/W]
00011100
CSCFG [R/W]
0X000000
CMCFG [R/W]
0 - - - 0000
WTCR [R/W]
00000000 000 - 00 - 0
WTBR [R/W]
- - - XXXXX XXXXXXXX XXXXXXXX
0004B0H
CUCR [R/W]
- - - - - - - - - - - 0 - - 00
CUTD [R/W]
10000000 00000000
0004B4H
CUTR1 [R]
- - - - - - - - 00000000
CUTR2 [R]
00000000 00000000
0004B8H
CMPR [R/W]
- - 000010 11111101
0004BCH
res.
CMT1 [R/W]
00000000 1 - - - 0000
CMCR [R/W]
- 001 - - 00
CMT2 [R/W]
- - 000000 - - 000000
Real Time
Clock
(Watch Timer)
ClockSupervisor /
Selector /
Monitor
Calibration
Unit of Sub
Oscillation
Clock
Modulation
0004C0H
CANPRE [R/W]
0 - - - 0000
CANCKD [R/W]
---0----
res.
res.
0004C4H
LVSEL [R/W]
00000111
LVDET [R/W]
00000-00
HWWDE [R/W]
- - - - - - 00
HWWD [R/W,W]
00011000
LV Detection
/ HardwareWatchdog
0004C8H
OSCRH [R/W]
000 - - 001
OSCRL [R/W]
- - - - - 000
WPCRH [R/W]
00 - - - 000
WPCRL [R/W]
- - - - - - 00
Main-/SubOscillation
Stabilisation
Timer
0004CCH
OSCCR [R/W]
-------0
res.
0004D0H
000BFCH
000C00H
REGSEL [R/W]
- - 000110
REGCTR [R/W]
- - - 0 - - 00
CAN Clock
Control
MainOscillation
Standby
Control /
Main/Sub
Regulator
Control
reserved
res.
res.
Fujitsu Microelectronics Europe GmbH
res.
res.
Page 53 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
+0
+1
000C04H
000D08H
Block
+2
+3
reserved
res.
res.
PDRD14 [R]
XXXXXXXX
PDRD15 [R]
XXXXXXXX
000D10
PDRD16 [R]
XXXXXXXX
PDRD17 [R]
XXXXXXXX
PDRD18 [R]
-X---X--
PDRD19 [R]
- X - - - XXX
000D14H
PDRD20 [R]
XXXXXXXX
PDRD21 [R]
XXXXXXXX
PDRD22 [R]
- - XX - - XX
res.
000D18H
PDRD24 [R]
XXXXXXXX
res.
PDRD26 [R]
- - - - - - XX
PDRD27 [R]
XXXXXXXX
000D1CH
PDRD28 [R]
XXXXXXXX
PDRD29 [R]
XXXXXXXX
res.
res.
000D0CH
000D20H
000D48H
R-bus
Port Data
Direct Read
Register
reserved
000D4CH
res.
res.
DDR14 [R/W]
00000000
DDR15 [R/W]
00000000
000D50H
DDR16 [R/W]
00000000
DDR17 [R/W]
00000000
DDR18 [R/W]
-0---0--
DDR19 [R/W]
- 0 - - - 000
000D54H
DDR20 [R/W]
00000000
DDR21 [R/W]
00000000
DDR22 [R/W]
- - 00 - - 00
res.
000D58H
DDR24 [R/W]
00000000
res.
DDR26 [R/W]
- - - - - - 00
DDR27 [R/W]
00000000
000D5CH
DDR28 [R/W]
00000000
DDR29 [R/W]
00000000
res.
res.
000D60H
000D88H
R-bus
Port Direction
Register
reserved
000D8CH
res.
res.
PFR14 [R/W]
00000000
PFR15 [R/W]
00000000
000D90H
PFR16 [R/W]
00000000
PFR17 [R/W]
00000000
PFR18 [R/W]
-0---0--
PFR19 [R/W]
- 0 - - - 000
000D94H
PFR20 [R/W]
00000000
PFR21 [R/W]
00000000
PFR22 [R/W]
- - 00 - - 00
res.
Fujitsu Microelectronics Europe GmbH
R-bus
Port Function
Register
Page 54 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
Block
+0
+1
+2
+3
000D98H
PFR24 [R/W]
00000000
res.
PFR26 [R/W]
- - - - - - 00
PFR27 [R/W]
00000000
000D9CH
PFR28 [R/W]
00000000
PFR29 [R/W]
00000000
res.
res.
000DA0H
000DC8H
reserved
000DCCH
res.
res.
EPFR14 [R/W]
00000000
EPFR15 [R/W]
00000000
000DD0H
EPFR16 [R/W]
0-------
EPFR17 [R/W]
--------
EPFR18 [R/W]
-0---0--
EPFR19 [R/W]
-0---0--
000DD4H
EPFR20 [R/W]
-0---0--
EPFR21 [R/W]
-0---0--
EPFR22 [R/W]
--------
res.
000DD8H
EPFR24 [R/W]
--------
res.
EPFR26 [R/W]
- - - - - - 00
EPFR27 [R/W]
00000000
000DDCH
res.
EPFR29 [R/W]
--------
res.
res.
000DE0H
000E08H
R-bus Port
Extra Function
Register
reserved
000E0CH
res.
res.
PODR14 [R/W]
00000000
PODR15 [R/W]
00000000
000E10H
PODR16 [R/W]
00000000
PODR17 [R/W]
00000000
PODR18 [R/W]
-0---0--
PODR19 [R/W]
- 0 - - - 000
000E14H
PODR20 [R/W]
00000000
PODR21 [R/W]
00000000
PODR22 [R/W]
- - 00 - - 00
res.
000E18H
PODR24 [R/W]
00000000
res.
PODR26 [R/W]
- - - - - - 00
PODR27 [R/W]
00000000
000E1CH
PODR28 [R/W]
00000000
PODR29 [R/W]
00000000
res.
res.
R-bus Port
Output Drive
Select
Register
000E20H
-
reserved
000E48H
Fujitsu Microelectronics Europe GmbH
Page 55 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
Block
+0
+1
+2
+3
000E4CH
res.
res.
PILR14 [R/W]
00000000
PILR15 [R/W]
00000000
000E50H
PILR16 [R/W]
00000000
PILR17 [R/W]
00000000
PILR18 [R/W]
-0---0--
PILR19 [R/W]
- 0 - - - 000
000E54H
PILR20 [R/W]
00000000
PILR21 [R/W]
00000000
PILR22 [R/W]
- - 00 - - 00
res.
000E58H
PILR24 [R/W]
00000000
res.
PILR26 [R/W]
- - - - - - 00
PILR27 [R/W]
00000000
000E5CH
PILR28 [R/W]
00000000
PILR29 [R/W]
00000000
res.
res.
000E60H
000E88H
R-bus Port
Input Level
Select
Register
reserved
000E8CH
res.
res.
EPILR14 [R/W]
00000000
EPILR15 [R/W]
00000000
000E90H
EPILR16 [R/W]
00000000
EPILR17 [R/W]
00000000
EPILR18 [R/W]
-0---0--
EPILR19 [R/W]
- 0 - - - 000
000E94H
EPILR20 [R/W]
00000000
EPILR21 [R/W]
00000000
EPILR22 [R/W]
- - 00 - - 00
res.
000E98H
EPILR24 [R/W]
00000000
res.
EPILR26 [R/W]
- - - - - - 00
EPILR27 [R/W]
00000000
000E9CH
EPILR28 [R/W]
00000000
EPILR29 [R/W]
00000000
res.
res.
000EA0H
000EC8H
R-bus Port
Extra Input
Level Select
Register
reserved
000ECCH
res.
res.
PPER14 [R/W]
00000000
PPER15 [R/W]
00000000
000ED0H
PPER16 [R/W]
00000000
PPER17 [R/W]
00000000
PPER18 [R/W]
-0---0--
PPER19 [R/W]
- 0 - - - 000
000ED4H
PPER20 [R/W]
00000000
PPER21 [R/W]
00000000
PPER22 [R/W]
- - 00 - - 00
res.
000ED8H
PPER24 [R/W]
00000000
res.
PPER26 [R/W]
- - - - - - 00
PPER27 [R/W]
00000000
Fujitsu Microelectronics Europe GmbH
R-bus Port
Pull-Up/Down
Enable
Register
Page 56 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
000EDCH
Block
+0
+1
+2
+3
PPER28 [R/W]
00000000
PPER29 [R/W]
00000000
res.
res.
000EE0H
000F08H
reserved
000F0CH
res.
res.
PPCR14 [R/W]
11111111
PPCR15 [R/W]
11111111
000F10H
PPCR16 [R/W]
11111111
PPCR17 [R/W]
11111111
PPCR18 [R/W]
-1---1--
PPCR19 [R/W]
- 1 - - - 111
000F14H
PPCR20 [R/W]
11111111
PPCR21 [R/W]
11111111
PPCR22 [R/W]
- - 11 - - 11
res.
000F18H
PPCR24 [R/W]
11111111
res.
PPCR26 [R/W]
- - - - - - 11
PPCR27 [R/W]
11111111
000F1CH
PPCR28 [R/W]
11111111
PPCR29 [R/W]
11111111
res.
res.
000F20H
000F3CH
reserved
001000H
DMASA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Fujitsu Microelectronics Europe GmbH
R-bus Port
Pull-Up/Down
Control
Register
DMAC
Page 57 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
+0
+1
Block
+2
+3
001020H
DMASA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
001FFCH
reserved
002000H
005FFCH
MB91F465KA Instruction RAM size is 8kB : 005000H - 005FFCH
006000H
006FFCH
reserved
007000H
007004H
FMCS [R/W]
01101000
FMCR [R]
- - - 00000
FCHCR [R/W]
- - - - - - 00 10000011
FMWT [R/W]
11111111 11111111
FMWT2 [R]
- 001 - - - -
FMPS [R/W]
- - - - - 000
007008H
FMAC [R]
00000000 00000000 00000000 00000000
00700CH
FCHA0 [R/W]
- - - - - - - - - - - 00000 00000000 00000000
007010H
FCHA1 [R/W]
- - - - - - - - - - - 00000 00000000 00000000
007014H
007FFCH
reserved
008000H
00BFFCH
MB91F465KA Boot-ROM size is 4kB : 00B000H - 00BFFCH
(instruction access is 1 waitcycle, data access is 1 waitcycle)
Instruction
RAM 16 kB
Flash Memory/
I-Cache
Control
Register
I-Cache Noncacheable
area setting
Register
Boot ROM
16 kB
00C0000
-
reserved
00C3FCH
Fujitsu Microelectronics Europe GmbH
Page 58 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
+0
+1
Block
+2
+3
00C400H
CTRLR4 [R/W]
00000000 00000001
STATR4 [R/W]
00000000 00000000
00C404H
ERRCNT4 [R]
00000000 00000000
BTR4 [R/W]
00100011 00000001
00C408H
INTR4 [R]
00000000 00000000
TESTR4 [R/W]
00000000 X0000000
00C40CH
BRPE4 [R/W]
00000000 00000000
00C410H
IF1CREQ4 [R/W]
00000000 00000001
IF1CMSK4 [R/W]
00000000 00000000
00C414H
IF1MSK24 [R/W]
11111111 11111111
IF1MSK14 [R/W]
11111111 11111111
00C418H
IF1ARB24 [R/W]
00000000 00000000
IF1ARB14 [R/W]
00000000 00000000
00C41CH
IF1MCTR4 [R/W]
00000000 00000000
res.
00C420H
IF1DTA14 [R/W]
00000000 00000000
IF1DTA24 [R/W]
00000000 00000000
00C424H
IF1DTB14 [R/W]
00000000 00000000
IF1DTB24 [R/W]
00000000 00000000
CBSYNC4
CAN 4
Control
Register
*2
CAN 4
IF 1 Register
00C428H
00C42CH
reserved
00C430H
IF1DTA24 [R/W]
00000000 00000000
IF1DTA14 [R/W]
00000000 00000000
00C434H
IF1DTB24 [R/W]
00000000 00000000
IF1DTB14 [R/W]
00000000 00000000
00C438H
-
reserved
00C43CH
Fujitsu Microelectronics Europe GmbH
Page 59 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
+0
+1
Block
+2
+3
00C440H
IF2CREQ4 [R/W]
00000000 00000001
IF2CMSK4 [R/W]
00000000 00000000
00C444H
IF2MSK24 [R/W]
11111111 11111111
IF2MSK14 [R/W]
11111111 11111111
00C448H
IF2ARB24 [R/W]
00000000 00000000
IF2ARB14 [R/W]
00000000 00000000
00C44CH
IF2MCTR4 [R/W]
00000000 00000000
res.
00C450H
IF2DTA14 [R/W]
00000000 00000000
IF2DTA24 [R/W]
00000000 00000000
00C454H
IF2DTB14 [R/W]
00000000 00000000
IF2DTB24 [R/W]
00000000 00000000
00C458H
00C45CH
reserved
00C460H
IF2DTA24 [R/W]
00000000 00000000
IF2DTA14 [R/W]
00000000 00000000
00C464H
IF2DTB24 [R/W]
00000000 00000000
IF2DTB14 [R/W]
00000000 00000000
00C468H
00C47CH
00C480H
reserved
TREQR24 [R]
00000000 00000000
00C484H
00C48CH
00C490H
TREQR14 [R]
00000000 00000000
CAN 4
Status Flags
reserved
NEWDT24 [R]
00000000 00000000
00C494H
00C49CH
00C4A0H
CAN 4
IF 2 Register
NEWDT14 [R]
00000000 00000000
reserved
INTPND24 [R]
00000000 00000000
00C4A4H
00C4ACH
Fujitsu Microelectronics Europe GmbH
INTPND14 [R]
00000000 00000000
reserved
Page 60 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
+0
00C4B0H
+1
Block
+2
MSGVAL24 [R]
00000000 00000000
MSGVAL14 [R]
00000000 00000000
00C4B4H
00EFFCH
reserved
00F000H
BCTRL [R/W]
- - - - - - - - - - - - - - - - 11111100 00000000
00F004H
BSTAT [R/W]
- - - - - - - - - - - - - 000 00000000 10 - - 0000
00F008H
BIAC [R]
- - - - - - - - - - - - - - - - - - - - - - - - 00000000
00F00CH
BOAC [R]
- - - - - - - - - - - - - - - - - - - - - - - - 00000000
00F010H
BIRQ [R/W]
- - - - - - - - - - - - - - - - - - - - - - - - 00000000
00F014H
00F01CH
reserved
00F020H
BCR0 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F024H
BCR1 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F028H
00F07CH
reserved
00F080H
BAD0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F084H
BAD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F088H
BAD2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F08CH
BAD3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F090H
BAD4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Fujitsu Microelectronics Europe GmbH
+3
EDSU / MPU
EDSU / MPU
Page 61 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
+0
+1
Block
+2
+3
00F094H
BAD5 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F098H
BAD6 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F09CH
BAD7 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A0H
027FFCH
reserved
028000H
02FFFCH
MB91F465KA D-RAM size is 8kB : 02E000H - 02FFFCH
(data access is 0 waitcycles)
030000H
037FFCH
MB91F465KA I-/D-RAM size is 8kB : 030000H - 031FFCH
(instruction access is 0 waitcycles, data access is 1 waitcycle)
038000H
07FFFCH
reserved
080000H
09FFFCH
ROMS02 area (128kB)
0A0000H
0BFFFCH
ROMS03 area (128kB)
0C0000H
0DFFFCH
ROMS04 area (128kB)
0E0000H
0FFFF4H
ROMS05 area (128kB)
0FFFF8H
FMV [R]
06 00 00 00H
0FFFFCH
FRV [R]
00 00 BF F8H
100000H
147FFCH
reserved
Fujitsu Microelectronics Europe GmbH
D-RAM
32 kB
I-/D-RAM
32 kB
Fixed
Reset/Mode
Vector
Page 62 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Register
Address
+0
+1
Block
+2
148000H
14FFFCH
ROMS07 area (32kB)
150000H
4FFFFCH
reserved
+3
Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values
shown above will be read.
Fujitsu Microelectronics Europe GmbH
Page 63 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
7 Electrical Characteristics
7.1 Absolute Maximum Ratings
Parameter
Digital supply voltage
Symbol
VDD-VSS
min.
-0.3
max.
6.0
Unit
V
Condition
Storage temperature
TST
-55
125
°C
Power consumption
PTOT
1000
mW
Digital input voltage
VIDIG
VSS-0.3 *
VDD+0.3
V
Analog input voltage
VIA
AVSS-0.3 *
AVDD+0.3
V
Analog supply voltage
AVCC-AVSS
-0.3
5.8
V
Analog reference voltage
AVRH-AVSS
-0.3
5.8
V
Static DC current into
digital I/O
II/ODC
-2
2
mA
Relationship of the supply
voltages
AVCC
VDD - 0.3
VDD + 0.3
V
At least one pin of the
ports 26 - 29 (AN*) is
used as digital input or
output
VSS - 0.3
VDD + 0.3
V
All pins of the ports 26
- 29 (AN*) follow the
condition of VIA
TA = 25°C
AVCC=AVRH
II/ODC < ISRUN
* Making full use of the allowed static DC current into digital I/Os will lead to lower values here.
7.2 Operating Conditions
Parameter
Symbol
min.
Operating temperature
TOP
Supply voltage
- Digital supply
- Analog supply
max.
Unit
-40
105
°C
VDD5-VSS
3.0
5.5
V
Internal voltage reg.
VDDCORE =1.8V
AVCC-AVSS
3.0
5.5
V
AVSS=0V
Fujitsu Microelectronics Europe GmbH
typ.
Condition
Page 64 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
Current consumption
-Run mode, flash unused
-Run mode, flash accessed
Isrun
Isrun
80
110
mA
mA
- Sleep mode
IsSLEEP
40
mA
f = 80 MHz (1.0 mA/MHz)
f = 80 MHz (1.3 mA/MHz
+5 mA)
f = 80 MHz (0.5 mA/MHz)
-RTC mode
IsRTC
100
40
500
250
µA
µA
µA
µA
f = 4MHz, TA =25 ºC
f \ 100kHz, TA =25 ºC
f = 4MHz, TA =105 ºC
f \ 100kHz, TA =105 ºC
-Stop mode
Isstop
30
200
µA
µA
TA =25 ºC
TA =105 ºC
all voltage ranges valid at
4.5V \ VDD \ 5.5V
Digital Inputs 1)
CMOS Schmitt-Trigger:
- High voltage range
- Low voltage range
VIH
VIL
0.7*VDD
VSS
VDD
0.3*VDD
V
V
CMOS Schmitt-Trigger 2:
- High voltage range
- Low Voltage range
VIH
VIL
0.8*VDD
VSS
VDD
0.2*VDD
V
V
CMOS Automotive SchmittTrigger:
- High voltage range
- Low voltage range
VIH
VIL
0.8*VDD
VSS
VDD
0.5*VDD
V
V
0.2
0.5
V
2.0
VSS
VDD
0.8
V
V
-1
tbd
1
pF
µA
k
k
- hysteresis voltage
TTL:
- High voltage range
- Low voltage range
VIH
VIL
all inputs:
- Input capacitance
- Input leakage current
- Pull up resistor
- Pull down resistor
Digital outputs
CIN
IIL
Rup
Rdown
- Output "H" voltage
VOH
VDD-0.5
VDD
V
- Output "L" voltage
VOL
VSS
VSS+0.4
V
50
50
Digital outputs I2C Port
- Output "H" voltage
VOH
VDD-0.5
VDD
V
- Output "L" voltage
VOL
VSS
VSS+0.4
V
Fujitsu Microelectronics Europe GmbH
TA =25 ºC
4.5V \ VDD \ 5.5V
Iload = ±2mA / ±5mA
3.0V \ VDD \ 4.5V
Iload = ±1.6mA/ ±3mA
4.5V \ VDD \ 5.5V
Iload = ±3 mA
3.0V \ VDD \ 4.5V
Iload = ±2mA
Page 65 of 67
European MCU Design Centre
ADC inputs 2)
- Reference voltage
input
- Input voltage range
MB91F465KA preliminary datasheet ver. 1.11
AVRH
AVRL
AVCC*0.75
AVSS
Vimax
Vimin
AVRL
AVCC
AVCC*0.25
V
V
AVRH
V
V
- Input resistance
RI
2.6
12.1
k
k
- Input capacitance
CI
8.5
pF
100
k
- Impedance of external
output driving the ADC input
- Input leakage current
IIL
-1
1
µA
VOH
VOL
VSS
VDD
VSS+0.4
V
V
Iout
3
4.5V < AVCC < 5.5V
3.0V < AVCC < 4.5V
TA =25 ºC
2
I C Bus Interface
Open Drain Output
- Output voltage
- Output current
mA
Lock-up time PLL1
(4MHz->16…100MHz)
0.6
ESD Protection
(Human body model)
Vsurge
2
RC Oscillator
fRC100KHz
fRC2MHz
50
1
ms
kV
100
2
200
4
kHz
MHz
1)
valid for bidirectional tristate I/O PAD cell
2)
The protection diodes at the analog inputs are connected to the digital supply voltage
Fujitsu Microelectronics Europe GmbH
Iload = 3mA
Rdischarge=1.5k
Cdischarge= 100pF
VDDCORE `1.65V
Page 66 of 67
European MCU Design Centre
MB91F465KA preliminary datasheet ver. 1.11
7.3 Converter Characteristics
• A/D Converter
Parameter
Symbol
Rating
Minimum
Typical
Unit
Maximum
Resolution
10
Bit
Conversion error
+/- 3.0
LSB
Non-linearity
+/-2.5
LSB
Differential
Non-linearity
+/-1.9
LSB
Zero Reading
voltage
V0T
Full scale reading VFST
voltage
AVRL -1.5
AVRL+0.5
AVRL+2.5
LSB
AVRH-3.5
AVRH-1.5
AVRH+0.5
LSB
Input current
IA @
AVCC
2.4
4.7
mA
Reference
voltage
current
IR
0.65
1.0
mA
-
-
ns
Comparision
Time
TCOMP
680
2080
Remark
Overall error
4.5V \ Avcc \ 5.5V
3.0V \ Avcc \ 4.5V
• Sampling Time Calculation
TSAMP = ( 2.6 kOhm + Rext) * 8.5pF * 7; for 4.5V
TSAMP = (12.1 kOhm + Rext) * 8.5pF * 7; for 3.0V
Avcc
Avcc
5.5V
4.5V
• Conversion Time Calculation
TCONV = TSAMP + TCOMP
Fujitsu Microelectronics Europe GmbH
Page 67 of 67
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