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SID11x2K
SCALE-iDriver Family
Up to 8 A Single Channel IGBT/MOS Gate Driver
Providing Reinforced Galvanic Isolation
PRELIMINARY
Product Highlights
Description
Highly Integrated, Compact Footprint
The SID11x2K is a single channel IGBT and MOSFET driver in an
eSOP package. Reinforced galvanic isolation is provided by Power
Integrations’ innovative solid insulator FluxLink technology. The up to
8 A peak output drive current enables the product to drive devices up
to 450 A (typ) without requiring any additional active components. For
gate drive requirements that exceed the stand-alone capability of the
SID1182K’s, an external amplifier (booster) may be added. Stable
positive and negative voltages for gate control are provided by one
unipolar isolated voltage source.
• Split outputs providing up to 8 A peak drive current
• Integrated FluxLink™ technology providing safe isolation between
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primary-side and secondary-side
Rail-to-rail stabilized output voltage
Unipolar supply voltage for secondary-side
Suitable for 600 V / 650 V / 1200 V IGBT and MOSFET switches
Up to 250 kHz switching frequency
Low propagation delay time 260 ns
Propagation delay jitter ±5 ns
-40 °C to 125 °C operating ambient temperature
High common-mode transient immunity
eSOP package with 9.5 mm creepage and clearance
Advanced Protection / Safety Features
• Undervoltage lock-out protection for primary and secondary-side
(UVLO) and fault feedback
• Short-circuit protection using VCESAT monitoring and fault feedback
diodes* or resistor chain** (see Figure 1)
• Advanced Soft Shut Down (ASSD)
Additional features such as short-circuit protection (DESAT) with
Advanced Soft Shut Down (ASSD), undervoltage lock-out (UVLO) for
primary-side and secondary-side and rail-to-rail output with temperature and process compensated output impedance guarantee safe
operation even in harsh conditions.
Controller (PWM and fault) signals are compatible with 5 V CMOS logic,
which may also be adjusted to 15 V levels by using external resistor divider.
Product Portfolio
Product1
Peak Output Drive Current
SID1132K
2.5 A
SID1152K
5.0 A
SID1182K
8.0 A
Full Safety and Regulatory Compliance
• 100% production partial discharge test
• 100% production HIPOT compliance testing at 6 kV RMS 1 s
• Reinforced insulation meets VDE 0884-10
Green Package
Table 1. SCALE-iDriver Portfolio.
Notes:
1. Package: eSOP-R16B.
• Halogen free and RoHS compliant
Applications
• General purpose and servo drives
• UPS, solar, welding inverters and power supplies
Figure 2. eSOP-R16B Package.
SCALE-iDriver
Primary-Side
Logic
Secondary-Side
Logic
G
IN
D
SO
RSO
C1
VCC
RVCEX**
RVCE
CRES
RRES*
S
Fault
Output
VIN
VCE
VISO
CS1
VEE
CS2
VTOT +
-
FluxLink
DVCE*
DCL**
COM
+ VVCC
-
DSTO
VGXX
GND
CGXX
G
S
GH
RGON
D
GL
RGOFF
Figure 1. Typical Application Schematic.
www.power.com Collector
Gate
Emitter
PI-7949-050316
May 2016
This Product is Covered by Patents and/or Pending Patent Applications.
SID11x2K
VCE
+
VDES
G
D
VGXX
S
COM
SHORT-CIRCUIT
DETECTION
BOOTSTRAP
CHARGE PUMP
VCC
LEVEL
SHIFTER
ASSD
D
G
IN
G
D
S
GH
FluxLink
SO
GND
VISO
TRANSCEIVER
(BIDIRECTIONAL)
TRANSCEIVER
(BIDIRECTIONAL)
GL
S
CORE LOGIC
SUPPLY
MONITORING
AUXILIARY
POWER SUPPLIES
CORE LOGIC
SUPPLY
MONITORING
AUXILIARY
POWER SUPPLIES
G
D
S
COM
VISO
VEE
VEE CONTROL
PI-7654-050616
Figure 3. Functional Block Diagram.
Pin Functional Description
VCC Pin (Pin 1):
This pin is the primary-side supply voltage connection.
GND Pin (Pin 3-6):
This pin is the connection for the primary-side ground potential.
All primary-side voltages refer to the pin.
VISO Pin (Pin 14):
This pin is the input for the secondary-side positive supply voltage.
COM Pin (Pin 15):
This pin provides the secondary-side reference potential.
GL Pin (Pin 16):
This pin is the driver output – sinking current (turn-off).
IN Pin (Pin 7):
This pin is the input for the logic command signal.
SO Pin (Pin 8):
This pin is the output for the logic fault signal (open drain).
NC Pin (Pin 9):
This pin must be un-connected. Minimum PCB pad size for soldering
is required.
VCC 1
VEE Pin (Pin 10):
Common (IGBT emitter/MOSFET source) output supply voltage.
GND 3-6
VCE Pin (Pin 11):
This pin is the desaturation monitoring voltage input connection.
IN 7
SO 8
VGXX Pin (Pin 12):
This pin is the bootstrap and charge pump supply voltage source.
GH Pin (Pin 13):
This pin is the driver output – sourcing current (turn-on) connection.
PI-7648-041415
Figure 4.
2
Rev. A 05/16
16 GL
15 COM
14 VISO
13 GH
12 VGXX
11 VCE
10 VEE
9 NC
Pin Configuration.
PRELIMINARY
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
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SID11x2K
SCALE-iDriver Functional Description
SCALE-iDriver
The single channel SCALE-iDriver™ family is designed to drive IGBTs
and MOSFETs or other semiconductor power switches with a blocking
voltage of up to 1200 V and provide reinforced isolation between
micro-controller and the power semiconductor switch. The logic
input (PWM) command signals applied via the IN pin and the primary
supply voltage supplied via the VCC pin are both reference to the
GND pin. The working status of the power semiconductor switch and
SCALE-iDriver is monitored via the SO pin.
R1
R2
Gate driver commands are transferred from the IN pin to the GH and
GL pins with a propagation delay tP(LH) and tP(HL) as described in the
data sheet.
During normal operation, when there is no fault detected, the SO pin
stays at high impedance (open). Any fault is reported by connecting
the SO pin to GND. The SO pin stays low as long as the V VCC voltage
(primary-side) stays below UVLOVCC, and the propagation delay is
negligible. If desaturation is detected (there is a short-circuit), or the
supply voltages V VISO, V VEE, (secondary-side) drop below UVLOVISO,
UVLOVEE, the SO status changes with a delay time tFAULT and keeps
status low for a time defined as tSO. In case of a fault condition the
driver applies the off-state (the GL pin is connected to COM). During
the tSO period, command signal transitions from the IN pin are
ignored. A new turn-on command transition is required before the
driver will enter the on-state.
The SO pin current is defined as ISO; voltage during low status is
defined as VSO(FAULT).
Output (Secondary-Side)
The gate of the power semiconductor switch to be driven can be
connected to the SCALE-iDriver output via pins GH and GL, using two
GND
PI-7950-050916
Figure 5. Increased Threshold Voltages VIN+LT and V IN+HT. For R1 = 3.3 kW and R 2 = 1 kW the IN Logic Level is 15 V.
different resistor values. Turn-on gate resistor RGON needs to be
connected to the GH pin and turn-off gate resistor RGOFF to the GL pin.
If both gate resistors have the same value, the GL and GH pins can be
connected together. Note: The SCALE-iDriver data sheet defines the
RGH and RGL values as total resistances connected to the respective
pins GH and GL. Note that most power semiconductor data sheets
specify an internal gate resistor RGINT which is already integrated into
the power semiconductor switch. In Addition to RGINT, external
resistor devices RGON and RGOFF are specified to setup the gate current
levels to the application requirements. Consequently, RGH is the sum
of RGON and RGINT, as shown in Figures 9 and 10. Careful consideration
should be given to the power dissipation and peak current associated
with the external gate resistors.
The GH pin output current source (IGH) of SID1182K is capable of
handling up to 7.3 A during turn-on, and the GL pin output current
source (IGL) is able to sink up to 8.0 A during turn-off. The SCALEiDriver’s internal resistances are described as RGHI and RGLI respectively. If the gate resistors for SCALE-iDriver family attempt to draw
a higher peak current, the peak current will be internally limited to a
9
PI-7910-050916
Input and Fault Logic (Primary-Side)
The input (IN) and output (SO) logic is designed to work directly with
micro-controllers using 5 V CMOS logic. If the physical distance
between the controller and the SCALE-iDriver is large or if a different
logic level is required the resistive divider in Figure 5, or Schmitt-trigger
ICs (Figures 13 and 14) can be used. Both solutions adjust the logic level
as necessary and will also improve the driver’s noise immunity.
8
7
6
5
4
4
RGH = 4 Ω, RGL = 3.4 Ω, CLOAD = 47 nF
RGH = 4 Ω, RGL = 3.4 Ω, CLOAD = 100 nF
RGH = RGL = 0 Ω, CLOAD = 47 nF
3
1
0
-60
-40
-20
0
20
40
60
80
100
120
140
Ambient Temperature (°C)
Figure 6. Turn-On Peak Output Current (Source) vs. Ambient Temperature. Conditions: VCC = 5 V, V TOT = 25 V, fS = 20 kHz, Duty Cycle = 50%.
PRELIMINARY
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VCC
C1
Turn-On Peak Gate Current IGH (A)
Power Supplies
The SID11x2K normally requires two power supplies. One is the
primary-side (V VCC) which powers the primary-side logic and communication with the secondary (insulated) side. One supply voltage is
required for the secondary-side, V TOT is applied between the VISO pin
and the COM pin. V TOT needs to be insulated from the primary-side
and must provide at least the same insulation capabilities as the
SCALE-iDriver. V TOT must have a low capacitive coupling to the
primary or any other secondary-side. The positive gate-emitter
voltage is provided by V VISO which is internally generated and stabilized
to 15 V (typically) with respect to VEE. The negative gate-emitter
voltage is provided by V VEE with respect to COM. Due to the limited
current sourcing capabilities of the VEE pin, any additional load needs
to be applied between the VISO and COM pins. No additional load
between VISO and VEE pins or between VEE and COM pins is allowed.
SO
RSO
PMW command signals are transferred from the primary (IN) to
secondary-side via FluxLink isolation technology. The GH pin supplies
a positive gate voltage and charges the semiconductor gate during
the turn-on process. The GL pin supplies the negative voltage and
discharges the gate during the turn-off process.
Short-circuit protection is implemented using a desaturation detection
technique monitored via the VCE pin. After the SCALE-iDriver detects
a short-circuit, the semiconductor turn-off process is implemented
using an Advanced Soft Shut Down (ASSD) technique.
IN
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
3
Rev. A 05/16
SID11x2K
RGH = 4 Ω, RGL = 3.4 Ω, CLOAD = 47 nF
RGH = 4 Ω, RGL = 3.4 Ω, CLOAD = 100 nF
RGH = RGL = 0 Ω, CLOAD = 47 nF
-2
-3
-4
-5
-6
-7
-8
PI-7912-042816
PI-7911-042816
-1
7
6
Gate Peak Current (A)
Turn-Off Peak Gate Current IGL (A)
0
5
4
3
2
IGH, Turn-On Peak Gate Current
IGL, Turn-Off Peak Gate Current
1
-9
0
-10
-60
-40
-20
0
20
40
60
80
100
120
140
Ambient Temperature (°C)
Figure 7. Turn-Off Peak Output Current (Sink) vs. Ambient Temperature. Conditions: VVCC = 5 V, V TOT = 25 V, fS = 20 kHz, Duty Cycle = 50%
safe value, see Figures 6 and 7. Figure 8 shows the peak current
that can be achieved for a given supply voltage for same gate resistor
values, load capacitance and layout design.
Short-Circuit Protection
The SCALE-iDriver uses the semiconductor desaturation effect to
detect short-circuits and protects the device against damage by
employing an Advanced Soft Shut Down (ASSD) technique. Desaturation can be detected using two different circuits, either with diode
sense circuitry DVCE (Figure 9) or with resistors RVCEX (Figure 10). With
the help of a well stabilized V VISO and a Schottky diode (DSTO) connected
between semiconductor gate and VISO pin the short-circuit current
value can be limited to a safe value.
During the off-state, the VCE pin is internally connected to the COM
pin and CRES is discharged (red curve in Figure 11 represents the
potential of the VCE pin). When the power semiconductor switch
receives a turn-on command, the collector-emitter voltage (VCE)
decreases from the off-state level same as the DC-link voltage to a
normally much lower on-state level (see blue curve in Figure 11) and
CRES begins to be charged up to the VCE saturation level (VCE SAT). CRES
charging time depends on the resistance of RVCEX (Figure 10), DC-link
voltage and CRES value. The VCE voltage during on-state is continuously
observed and compared with a reference voltage, VDES. The VDES level
is optimized for IGBT applications. As soon as VCE>VDES (red circle in
Figure 11), the driver turns off the power semiconductor switch with a
controlled collector current slope, limiting the VCE overvoltage
excursions to below the maximum collector-emitter voltage (VCES).
Turn-on commands during this time and during tSO are ignored, and
the SO pin is connected to GND.
The response time tRES is the CRES charging time and describes the
delay between VCE asserting and the voltage on the VCE pin rising
(see Figure 11). Response time should be long enough to avoid false
tripping during semiconductor turn-on and is adjustable via RRES and
CRES (Figure 9) or RVCE and CRES (Figure 10) values. It should not be
longer than the period allowed by the semiconductor manufacturer.
Safe Power-Up and Power-Down
During driver power-up and power-down, several unintended input /
output states may occur. In order to avoid these effects, it is
recommended that the IN pin is kept at logic low during power-up
4
Rev. A 05/16
20
21
22
23
24
25
26
27
28
29
30
Secondary-Side Total Supply Voltage – VTOT (V)
Figure 8. Turn-On and Turn-Off Peak Output Current vs. Secondary-Side Total
Supply Voltage (V TOT). Conditions: VVCC = 5 V, TA = 25 °C, RGH = 4 W, RGL = 3.4 W, CLOAD = 100 nF, fS = 1 kHz, Duty Cycle = 50%.
SCALE-iDriver
RVCE
VCE
CRES
DVCE
RRES
VISO
VEE
COM
DSTO
VGXX
Collector
CGXX
Gate RGINT
GH
GL
RGON
RGOFF
Emitter
PI-7951-050316
Figure 9. Short-Circuit Protection using Rectifier Diode DVCE.
and power-down. Any supply voltage related to VCC, VISO, VEE and
VGXX pins should be stabilized using ceramic capacitors C1, CS1, CS2,
CGXX respectively as shown in Figure 1. After supply voltages reach
their nominal values, the driver will begin to function after a time
delay tSTART.
Short-Pulse Operation
If command signals applied to the IN pin are shorter than the minimum
specified by tGE(MIN), then SCALE-iDriver output signals, GH and GL
pins, will extend to value tGE(MIN). The duration of pulses longer than
tGE(MIN) will not be changed.
PRELIMINARY
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
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SID11x2K
SCALE-iDriver
RVCE
VCE
CRES
V
RVCEX
DCL
VISO
VCE (IGBT) Signal
VEE
Fault
VDES
VCE SAT
COM
DSTO
tRES
t
VGXX
Collector
CGXX
Gate RGINT
GH
VCE Pin Signal
RGON
GL
RGOFF
Emitter
-VVEE
PI-7671-050616
PI-7952-050316
Figure 10. Short-Circuit Protection using a Resistor Chain RVCEX.
Figure 11. Short-Circuit Protection using Resistors Chain RVCEX.
Advanced Soft Shut Down (ASSD)
This function is activated after a short-circuit is detected. It protects
the IGBT against destruction by ending the turn-on state and limiting
the current slope in order to keep momentary VCE overvoltages below
VCES. This function is particularly suited to IGBT applications. Figure 12
shows how the ASSD function operates. The VCE desaturation is
visible during time period P1 (yellow line). During this time, the
gate-emitter voltage (VGE – green line) is kept very stable. Collector
current (pink line) is also well stabilized and limited to a safe value.
At the end of period P1, VGE is reduced during tFSSD1. Due to collector
current decrease a small VCE overvoltage is seen. During tFSSD1 VGE is
further reduced and the gate of the power semiconductor switch is
further discharged. During tFSSD2 additional small VCE overvoltage
events may occur. Once VGE drops below the gate threshold of the
IGBT, the collector current has decayed almost to zero and the
remaining gate charge is removed - ending the short-circuit event.
The whole short-circuit current detection and safe switch-off is lower
than 10 µs (8 µs in this example).
VGE
tFSSD1
IGE
VCE
ICE
P1
tFSSD2
Figure 12. Advanced Soft Shut Down Function.
PRELIMINARY
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This document contains information on a new product. Specifications and information herein
are subject to change without notice.
5
Rev. A 05/16
SID11x2K
Application Examples and Components Selection
Figures 13 and 14 show the schematic and typical components used
for a SCALE-iDriver design. In both cases the primary-side supply
voltage (V VCC) is connected between VCC and GND pins and supported
through a blocking ceramic capacitor C1 (4.7 mF typically). If the
command signal voltage level is higher than the rated IN pin voltage
(in this case 15 V) a resistive voltage divider should be used. Additional
capacitor CF and Schmitt trigger IC1 can be used to provide input
signal filtering. The SO output has 5 V logic and the RSO is selected
so that it does not exceed absolute maximum rated ISO current.
The secondary-side isolated power supply (V TOT) is connected between
VISO and COM. The positive voltage rail (V VISO) is supported through
4.7 µF ceramic capacitors CS21 and CS22 connected in parallel. The
negative voltage rail (V VEE) is similarly supported through capacitors
CS11 and CS12. The gate charge will vary according to the type of
power semiconductor switch that is being driven. Typically, CS11 +
CS12 should be at least 3 mF multiplied by the total gate charge of the
power semiconductor switch (QGATE) divided by 1 mC. A 10 nF
capacitor CGXX is connected between the GH and VGXX pins.
The gate of the power semiconductor switch is connected through
resistor RGON to the GH pin and by RGOFF to the GL pin. If the value of
RGON is the same as RGOFF the GH pin can be connected to the GL pin
and a common gate resistor can be connected to the gate. In each
case, proper consideration needs to be given to the power dissipation
and temperature performance of the gate resistors.
To ensure gate voltage stabilization and collector current limitation
during a short-circuit, the gate is connected to the VISO pin through
a Schottky diode DSTO (for example PMEG4010).
SCALE-iDriver
Primary-Side
Logic
Command
Signal
IC1
74LVC
R1
3.3 kΩ
Secondary-Side
Logic
G
IN
S
SO
VEE
CS22
4.7 µF
VTOT +
-
SO
RSO
4.7 kΩ
VCC
GND
CS21
4.7 µF
VISO
D
CF
C1
4.7 µF
R2
1 kΩ
FluxLink
VCC
CS11
4.7 µF
COM
GND
G
RGE
6.8 kΩ
CS12
4.7 µF
VGXX
S
RVCE2-11
100 kΩ × 10
CRES RVCE
DCL
33 pF 120 kΩ BAS416
VCE
DSTO
CGXX
10 nF
GH
Collector
RGON
D
Gate
RGOFF
GL
Emitter
PI-7954-50616
Figure 13. SCALE-iDriver Application Example using a Resistor Chain for Desaturation Detection.
SCALE-iDriver
Primary-Side
Logic
Command
Signal
R1
3.3 kΩ
IC1
74LVC
Secondary-Side
Logic
G
IN
D
S
SO
VISO
VEE
CF
R2
1 kΩ
C1
4.7 µF
VCC
FluxLink
COM
G
S
GH
D
GL
RVCE
330 Ω
DVCE2
DVCE1
CS22
4.7 µF
CS11
4.7 µF
CS12
4.7 µF
RGE
6.8 kΩ
DSTO
VGXX
GND
CRES
33-330 pF
CS21
4.7 µF
VTOT +
-
SO
RSO
4.7 kΩ
VCC
GND
RRES
24-62 kΩ
VCE
CGXX
10 nF
RGON
RGOFF
Collector
Gate
Emitter
PI-7953-050616
Figure 14. SCALE-iDriver Application Example using Diodes for Desaturation Detection.
6
Rev. A 05/16
PRELIMINARY
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
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SID11x2K
To avoid parasitic power-switch-conduction during system power-on,
the gate is connected to COM through 6.8 kΩ resistor.
Figure 13 shows how switch desaturation can be measured using
resistors RVCE2 – RVCE11. In this example all the resistors have a value
of 100 kW and 1206 size. The total resistance is 1 MW. The resistors
should be chosen to limit current to between 0.6 mA to 0.8 mA at
maximum DC-link voltage. The sum of RVCE2 – RVCE11 should be
approximately 1 MW for 1200 V semiconductors and 500 kW for 600 V
semiconductors. In each case the resistor string must be selected so
as to provide (at least) functional insolation between collector of the
semiconductor and SCALE-iDriver. The low leakage diode DCL keeps
the short-circuit duration constant over a wide DC-link voltage range.
Response time is set up through RVCE and CRES (typically 120 kW and
33 pF respectively for 1200 V semiconductors). If short-circuit
detection proves to be too sensitive, the CRES value can be increased.
The maximum short-circuit duration must be limited to the maximum
value given in the semiconductor data sheet.
Figure 14 illustrates how diodes DVCE1 and DVCE2 may be used to
measure switch desaturation. For insulation, two diodes in SMD
packages are used (STTH212U for example). RRES connected to VISO
guarantees current flow through the diodes when the semiconductor
is in the on-state. When the switch desaturates, CRES starts to be
charged through RRES. In this configuration the response time is
controlled by RRES and CRES. In this application example CRES = 33 pF
and RRES = 62 kW; if desaturation is too sensitive or the short-circuit
duration too long, both CRES and RRES can be adjusted.
Figure 15 shows the recommended PCB layout and corresponds to
the schematic in Figure 13. The 10 1206 package resistors are
replaced by 2 470 kW MiniMelf resistors. The PCB is a two layer
design. It is important to ensure that PCB traces do not cover the
area below the desaturation resistors or diodes DVCE1 and DVCE2. This
is a critical design requirement to avoid coupling capacitance with the
SCALE-iDriver’s VCE pin and isolation issues within the PCB.
In addition to PDRV, PP (primary-side IC power dissipation) and PSNL
(secondary-side IC power dissipation without capacitive load) must be
considered. Both are ambient temperature and switching frequency
dependent (see typical performance characteristics).
PP = VVCC # I VCC
(2)
(3)
PSNL = VTOT # I VISO During IC operation, the PDRV power is shared between turn-on (RGH),
turn-off (RGL) external gate resistors and internal driver resistances
RGHI and RGLI. For junction temperature estimation purposes, the
dissipated power under load (POL) inside the IC can be calculated
accordingly to equation 4:
R GHI
R GHL l
POL = 0.5 # Q GATE # fS # VTOT # b R +
R GH + R GHL + R GL
GHI
(4)
RGH and RGL represent sum of external (RGON, RGOFF) and power
semiconductor internal gate resistance (RGINT):
RGH = RGon + RGINT, RGL = RGoff + RGINT.
Total IC power dissipation (PDIS) is estimated as sum of equations 2, 3
and 4:
PDIS = PP + PSNL + POL (5)
The operating junction temperature (TJOP) for given ambient
temperature (TA) can be estimated according to equation 6:
TJOP
= i JA # PDIS + T A
(6)
Example
An example is given below,
ƒS = 20 kHz, TA = 85 °C, V TOT = 25 V, V VCC = 5 V.
QGATE = 2.5 mC (the gate charge value here should correspond to
selected V TOT), RGINT = 2.5 W, RGON = RGOFF = 1.8 W.
Gate resistors are located physically close to the power semiconductor
switch. As these components can get hot, it is recommended that
they are placed away from the SCALE-iDriver.
PDRV = 2.5 mC × 20 kHz × 25 V = 1.25 W, according to equation 1.
PP = 5 V × 13.5 mA = 67 mW, according to equation 2 (see Figure 18).
PSNL = 25 V × 7.5 mA = 185 mW, according to equation 3 (see Figure 20).
Power Dissipation and IC Junction
Temperature Estimation
The dissipated power underload is:
First calculation in designing the power semiconductor switch gate
driver stage is to calculate the required gate power - PDRV. The power
is calculated based on equation 1:
where,
PDRV = Q GATE # fS # VTOT
(1)
QGATE – Controlled power semiconductor switch gate charge (derived
for the particular gate potential range defined by V TOT). See semiconductor manufacturer data sheet.
ƒS – switching frequency which is same as applied to the IN pin of
SCALE-iDriver.
V TOT – SCALE-iDriver secondary-side supply voltage.
POL = 0.5 # 2.5 nC # 20 kHz # 25 V #
1.45 X
1.2 X
b
l , 0.3 W,
+
1.45 X + 4.3 X 1.2 X + 4.3 X
according to equation 4.
RGHI = 1.45 W as maximum data sheet value.
RGHL = 1.2 W as maximum data sheet value.
RGH = RGL = 1.8 W + 2.5 W = 4.3 W.
PDIS = 67 mW + 185 mW + 0.3 W = 0.552 W according to equation 5.
TJOP = 67 °C/W × 0.552 W + 85 °C = 122 °C according to equation 6.
Estimated junction temperature for this design would be approximately
122 °C and is lower than the recommended maximum value. As the
gate charge is not adjusted to selected V TOT and internal IC resistor
values are maximum values, it is understood that the example
represents worst-case conditions.
PRELIMINARY
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are subject to change without notice.
7
Rev. A 05/16
SID11x2K
Table 2 describes the recommended capacitor and resistor
characteristics and layout requirements to achieve optimum
performances of SCALE-iDriver.
Pin
Return to Pin
Recommended
Value
Symbol
Notes
VCC
GND
4.7 mF
C1
VCC blocking capacitor needs to be placed close to IC.
Enlarged loop could result in inadequate VCC supply
voltage during operation.
VISO
VEE
4.7 mF
CS21/CS22
25V X7R type is recommended. Example part number
could be Murata 25 V part #GRM31CR71E475KA88.
This capacitor needs to be close to IC pins.
VEE
COM
4.7 mF
CS11/CS12
25 V X7R type is recommended. Example part
number could be Murata 25 V part #GRM31CR71E475KA88. This capacitor needs to be close to IC pins.
CGXX
To avoid mis-operation, this pin should not be
connected to anything else. This capacitor needs to
be as close to IC pins as possible. 25 V X7R type is
recommended. Example part number could be Yageo
25 V part#CC0603KRX7R9BB103.
CRES
Select CRES to achieve needed desaturation protection
response time. 50 V COG/NPO is recommended. A
value of 33 pF is initially recommended. Example part
number could be KEMET 50 V part C0603C330J5GACTU.
Any net and any other layer should provide a distance
of greater than 4 mm to components CRES in order to
avoid parasitic effects (capacitance, creepage and CAF)
VGXX
VCE
GH
COM
8
Rev. A 05/16
33 pF
RVCE, DVCE, CRES,
RRES, DCL
VCE
Table 2.
10 nF
Select RVCE or RRES for the proper operation of the
short-circuit protection. Any net and any other layer
should provide a distance of greater than 4 mm to
components RVCE, DVCE, RRES, and DCL in order to avoid
parasitic effects (capacitance, creepage and CAF).
PCB Layout Guidelines.
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are subject to change without notice.
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SID11x2K
PI-7955-050216
Figure 15a. Top View of Recommended PCB Layout. Corresponds to Schematic Shown in Figure 13.
PI-7956-050216
Figure 15b. Bottom View of Recommended PCB Layout. Corresponds to Schematic Shown in Figure 13.
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9
Rev. A 05/16
SID11x2K
Absolute Maximum Ratings1
Parameter
Symbol
Remarks
Min
Max
Units
V VCC
VCC - GND
-0.5
6.5
V
Secondary-Side Total Supply Voltage
V TOT
VISO - COM
-0.5
30
V
Secondary-Side Positive Supply Voltage
V VISO
VISO - VEE
-0.5
17.5
V
Secondary-Side Negative Supply Voltage
V VEE
VEE - COM
-0.5
15
V
Primary-Side Supply Voltage2
Logic Input Voltage (command signal)
VIN
IN - GND
-0.5
V VCC + 0.5
V
Logic Output Voltage (fault signal)
VSO
SO - GND
-0.5
V VCC + 0.5
V
Logic Output Current (fault signal)
ISO
Positive Current Flowing in to the Pin
10
mA
VCE Pin Voltage
V VCE
VCE - COM
-0.5
V TOT + 0.5
V
250
kHz
Switching Frequency
fS
Storage Temperature
TS
-65
150
°C
Operating Junction Temperature
TJOP
-40
1503
°C
Operating Ambient Temperature
TA
-40
125
°C
Input Power Dissipation
PP
4
Output Power Dissipation4
PS
Total IC Power Dissipation4
PDJS
188
V VCC = 5 V, V TOT = 28 V,
TA = 25 °C
fS = 250 kHz
1602
1790
mW
mW
NOTES:
1. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
2. Defined as peak voltage measured directly on VCC pin.
3. Transmission of command signals could be affected by PCB layout parasitic inductances at junction temperatures higher than recommended.
4. Input Power Dissipation refers to equation 2. Output Power Dissipation is secondary-side IC power dissipation without capacitive load
(PSNL, equation 3) and dissipated power under load (POL, equation 4). Total IC power dissipation is sum of PP and PS.
Thermal Resistance
Thermal Resistance: eSOP-R16B Package:
(Primary-side qJA) ............................... 51 °C/W1
(Secondary-side qJA) ........................... 67 °C/W1
(Primary-side qJC) ...............................22 °C/W2
(Secondary-side qJC) ...........................34 °C/W2
Parameter
Symbol
Notes:
1.2 oz. (610 g/m2) copper clad. Measured with layout shown in Figure 15.
2.The case temperature is measured at the plastic surface at the top
of the package.
Conditions
TA = -40 °C to +125 °C
See Note 1 (Unless Otherwise Specified)
Min
Typ
Max
Units
Recommended Operation Conditions
Primary-Side
Supply Voltage
V VCC
VCC - GND
4.75
5.25
V
Secondary-Side
Total Supply Voltage
V TOT
VISO - COM
22
28
V
0.5
V
Logic Low Input Voltage
VIL
Logic High
Input Voltage
VIH
3.3
Switching Frequency
fS
0
75
kHz
Operating IC Junction
Temperature
TJOP
-40
125
°C
10
Rev. A 05/16
V
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SID11x2K
Symbol
Conditions
TA = -40 °C to +125 °C
See Note 1 (Unless Otherwise Specified)
Min
Typ
Max
Units
Logic Low Input
Threshold Voltage
VIN+LT
fS = 0 Hz
0.6
1.25
1.8
V
Logic High Input
Threshold Voltage
VIN+HT
fS = 0 Hz
1.7
2.2
3.05
V
Logic Input
Voltage Hysteresis
VIN+HS
fS = 0 Hz
0.1
VIN = 5 V
56
Parameter
Electrical Characteristics
Input Bias Current
Supply Current
(Primary-Side)
IIN
IVCC
Supply Current
(Secondary-Side)
IVISO
Power Supply
Monitoring Threshold
(Primary-Side)
Power Supply
Monitoring Threshold
(Secondary-Side,
Positive Rail V VISO)
Power Supply Monitoring Blanking Time, V VISO
Power Supply
Monitoring Threshold
(Secondary-Side,
Negative Rail V VEE)
UVLOVCC
UVLOVISO(BL)
11.0
18
VIN = 5 V
16
24
fS = 20 kHz
14.5
22
fS = 75 kHz
16.3
24
VIN = 0 V
6.0
9.0
VIN = 5 V
7.0
10.0
fS = 20 kHz
7.4
10.0
fS = 75 kHz
10.3
14
Clear Fault
4.28
4.65
Set Fault
3.85
Hysteresis, See Notes 3, 4
0.02
Set Fault, Note 3
11.7
Hysteresis
0.3
Voltage Drop 13.5 V to 11.5 V
See Note 12
0.5
Set Fault, V TOT = 20 V
4.67
Hysteresis
0.1
0.5
Secondary-Side
Positive Supply Voltage
Regulation
V VISO(HS)
21 V ≤ V TOT ≤ 30 V,
|i(VEE)| ≤ 1.5 mA
14.4
V TOT = 15 V, V VEE set to 0 V
0.1
V TOT = 25 V, V VEE set to 7.5 V
Absolute Values
V TOT = 25 V, V VEE set to 12.5 V
Absolute Values
IVEE(SI)
PRELIMINARY
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mA
mA
V
13.5
12.35
V
3.0
ms
5.15
Voltage Drop 5.5 V to 4.5 V
See Note 12
VEE Sink Capability
4.12
12.85
UVLOVEE(BL)
IVEE(SO)
mA
VIN = 0 V
Power Supply Monitoring Blanking Time, V VEE
VEE Source Capability
165
106
Clear Fault, V TOT = 20 V
UVLOVEE
113
VIN > 3 V
See Note 12
Clear Fault
UVLOVISO
V
5.5
4.93
V
ms
15.07
15.75
1.85
3.3
4.5
1.74
3.1
4.5
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
V
mA
mA
11
Rev. A 05/16
SID11x2K
Parameter
Symbol
Conditions
TA = -40 °C to +125 °C
See Note 1 (Unless Otherwise Specified)
Min
Typ
Max
Units
Electrical Characteristics (cont.)
DESAT Detection Level
VDES
VCE-VEE, VIN = 5 V
7.2
7.8
8.3
V
DESAT Sink Current
IDES
V VCE = 10 V, VIN = 0 V
15
28
50
mA
DESAT Bias Current
IDES(BS)
VDES > V VCE > 0 V, VIN = 5 V
1.0
mA
VCE Pin Capacitance
C VCE
Between VCE and COM pins, See Note 12
Turn-On
Propagation Delay
tP(LH)
Turn-Off
Propagation Delay
tP(HL)
Minimum Turn-On and
Off Pulses
180
253
340
TA = 125 °C, See Note 5
210
278
364
TA = 25 °C, See Note 6
200
262
330
TA = 125 °C, See Note 6
211
287
359
tGE(MIN)
tR
See Note 12
650
CG = 10 nF,
See Note 7
CG = 10 nF
See Note 8
225
18
40
SID1132K
See Note 12
450
SID1152K
See Note 12
225
40
81
950
1828
tSTART
ns
ns
VGE change from 14.5 V to 2.5 V, See Note 12
150
2800
ns
See Note 12
±5
See Note 10
190
750
ns
10
13.4
µs
10000
ms
6.8
See Note 11
VGH ≥ VTOT - 8.8 V
CG = 470 nF
See Note 13
IGH
RG = 0, CG = 47 nF
See Notes 2, 13
12
5
tFSSD2
tSO
Rev. A 05/16
150
60
SO Fault
Signalization time
Gate Sourcing
Peak Current, GH Pin
90
TBD
tFAULT
Power-On
Start-Up Time
55
VGE change from 14.5 V to 14 V, See Note 12
Fault Signalization
Delay Time
ns
ns
tFSSD1
Propagation Delay Jitter
ns
45
SID1152K
See Note 12
SID1182K
ASSD Rate of Change
22
450
CG = 0, See Note 8
tF
10
SID1132K
See Note 12
SID1182K
Output Fall Time
pF
TA = 25 °C, See Note 5
CG = 0, See Note 7
Output Rise Time
12.5
SID1132K
See Note 12
1.2
SID1152K
See Note 12
2.4
SID1182K
3.6
4.6
SID1132K
2.4
SID1152K
4.8
SID1182K
7.3
ns
5.5
A
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SID11x2K
Parameter
Symbol
Conditions
TA = -40 °C to +125 °C
See Note 1 (Unless Otherwise Specified)
Min
Typ
Max
Units
4.8
5.5
A
Electrical Characteristics (cont.)
Gate Sinking Peak
Current GL Pin
VGL ≤ 7.5 V
CG = 470 nF
VGL is Referenced
to COM
SID1132K
See Note 12
1.3
SID1152K
See Note 12
2.6
SID1182K
4
IGL
RG = 0, CG = 47 nF
See Note 2
Turn-On Internal
Gate Resistance
RGHI
I(GH) = -250 mA
VIN= 5 V
SID1132K
2.6
SID1152K
5.2
SID1182K
8.0
SID1132K
See Note 12
4.8
SID1152K
See Note 12
2.4
SID1182K
Turn-Off Internal
Gate Resistance
RGLI
I(GL) = 250 mA
VIN = 0 V
0.76
Turn-On Gate
Output Voltage
VGH(ON)
Turn-Off Gate
Output Voltage
(Referred to COM Pin)
SO Output Voltage
VGL(OFF)
VSO(FAULT)
1.2
SID1132K
See Note 12
4
SID1152K
See Note 12
2
SID1182K
I(GH) = -6.6 mA
VIN = 5 V
SID1132K
See Note 12
I(GH) = -10 mA
VIN = 5 V
SID1152K
See Note 12
I(GH) = -20 mA
VIN = 5 V
SID1182K
I(GL) = -6.6 mA
VIN = 0 V
SID1132K
See Note 12
I(GL) = -10 mA
VIN = 0 V
SID1152K
See Note 12
I(GL) = -20 mA
VIN = 0 V
SID1182K
0.68
Ω
1.1
V TOT-0.04
Fault Condition, ISO = 3.4 mA, V VCC ≥ 3.9 V
Ω
V
250
0.04
V
450
mV
Electrical Characteristics (EMI)
Common-Mode
Transient Immunity,
Logic High
CMH
VCM = 1500 V
See Note 15
TBD
kV/ms
Static Common-Mode
Transient Immunity,
Logic Low
CML
VCM = 1500 V
See Note 15
TBD
kV/ms
HHPEAK
See Note 16
1000
HLPEAK
See Note 16
1000
Variable Magnetic Field
Immunity
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A/m
13
Rev. A 05/16
SID11x2K
Parameter
Symbol
Conditions
TA = -40 °C to +125 °C
See Note 1 (Unless Otherwise Specified)
Min
Typ
0.46
Max
Units
Package Characteristics (See Notes 12, 14)
Distance Through the
Insulation
DTI
Minimum Internal Gap (Internal Clearance)
0.4
mm
Minimum Air Gap
(Clearance)
L1 (IO1)
Shortest Terminal-to-Terminal Distance
Through Air
9.5
mm
Minimum External
Tracking (Creepage)
L2 (IO2)
Shortest Terminal-to-Terminal Distance
Across the Package Surface
9.5
mm
Tracking Resistance
(Comparative Tracking
Index)
CTI
DIN EN 60112 (VDE 0303-11): 2010-05
EN / IEC 30112:2003 + A1:2009
600
Isolation Resistance,
Input to Output *
R IO
VIO = 500 V, TA = 25 °C
1012
VIO = 500 V, 100 °C ≤ TA ≤ Max
1011
Isolation Capacitance,
Input to Output *
CIO
W
1
pF
1414
VPEAK
Package Insulation Characteristics
Maximum Repetitive
Peak Isolation Voltage
Input to Output
Test Voltage
VIORM
VPD
Method A, After Environmental Tests
Subgroup 1, VPR = 1.6 × VIORM, t = 10 s
(qualification) Partial Discharge < 5 pC
2263
Method A, After Input/Output Safety Test
Subgroup 2/3, VPR = 1.2 x VIORM, t = 10 s,
(qualification) Partial Discharge < 5 pC
1697
Method B1, 100% Production Test,
VPR = 1.875 × VIORM, t = 1 s
Partial Discharge < 5 pC
2652
VPEAK
Maximum Transient
Isolation Voltage
VIOTM
V TEST = VIOTM, t = 60 s (qualification),
t = 1 s (100% production)
8000
VPEAK
Maximum Surge
Isolation Voltage
VIOSM
Test Method Per IEC 60065, 1.2/50 μs
Waveform, V TEST = 1.6 x VIOSM = 12800 V
(qualification)
8000
VPEAK
Insulation Resistance
RS
VIO = 500 V at TS
>109
W
Maximum Case
Temperature
TS
150
°C
Safety Total
Dissipated Power
PS
1.79
W
TA = 25 °C
Pollution Degree
2
Climatic Classification
50/105/21
UL1577
Withstanding
Isolation Voltage
VISO
V TEST = VISO, t = 60 s (qualification),
V TEST = 1.2 × VISO = 6000 VRMS, t = 1 s
(100% production)
5000
VRMS
* Note: All pins on each side of the barrier tied together creating a two-terminal device.
14
Rev. A 05/16
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SID11x2K
Safe O
operating Power [W]
Thermal Derating Curve
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
0
20
40
60
80
100
120
140
160
Ta [°C]
Power derating curve
Figure 16. Thermal Derating Curve Showing Dependence of Limited Dissipated Power on Case Temperature
(DIN V VDE V 0884-10).
Continuous device operating is allowed until reaching TJOP or case temperature of 125 °C. Thermal stress beyond those values but below
thermal derating curve may lead to permanent functional product damage. Operating beyond thermal derating curve may affect product
reliability.
NOTES:
1. V VCC = 5 V, V TOT = 25 V; GH and GL pins are shorted together. RG = 4W, CG = 0; VCC pin is connected to the SO pin through a 2 kW resistor.
The VGXX pin is connected to the GH pin through a 10 nF capacitor. Typical values are defined at TA = 25 °C; fS = 20 kHz, Duty Cycle =
50%. Positive currents are assumed to be flowing into pins.
2. Pulse width ≤ 10 ms, duty cycle ≤ 1%. The maximum value is controlled by the ASIC to a safe level. There is no need to limit the current by
the application. The internal peak power is safely controlled for RG ≥0 and power semiconductor module input gate capacitance (CIES) ≤47 nF.
3. During very slow V VCC power-up and power-down related to V TOT, V VCC and V VEE respectively, several SO fault pulses may be generated.
4. SO pin connected to GND as long as V VCC stays below minimum value. No signal transferred from primary to secondary-side.
5.VIN potential changes from 0 V to 5 V within 10 ns. Delay is measured from 50% voltage increase on IN pin to 10% voltage increase
on GH pin.
6.VIN potential changes from 5 V to 0 V within 10 ns. Delay is measured from 50% voltage decrease on IN pin to 10% voltage decrease
on GL pin.
7. Measured from 10% to 90% of VGE (CG simulates semiconductor gate capacitance). The VGE is measured across CG.
8. Measured from 90% to 10% of VGE (CG simulates semiconductor gate capacitance). The VGE is measured across CG.
9. ASSD function limits G-E voltage of controlled semiconductor in specified time. Conditions: CG = 10 nF, V TOT = V VISO = 15 V,
V VEE = 0 V (VEE shorted to COM).
10. The amount of time needed to transfer fault event (UVLO or DESAT) from secondary-side to SO pin.
11. The amount of time after primary and secondary-side supply voltages (V VCC and V TOT) reach minimal required level for driver proper
operation. No signal is transferred from primary to secondary-side during that time, and no fault condition will be transferred from the
secondary-side to the primary-side.
12. Guaranteed by design.
13. Positive current is flowing out of the pin.
14. Safety distances are application dependent and the creepage and clearance requirements should follow specific equipment isolation
standards of an application. Board design should ensure that the soldering pads of an IC maintain required safety relevant distances.
15. According to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12. Furthermore, safe command and fault signal transfer are assured during the
common-mode noise duration.
16. Measured accordingly to IEC 61800-4-8 (fS = 50 Hz, and 60 Hz) and IEC 61800-4-9.
PRELIMINARY
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15
Rev. A 05/16
SID11x2K
Typical Performance Characteristics
115
114
113
112
111
110
109
IN = 0 V DC
IN = 5 V DC
fS = 20 kHz
fS = 75 kHz
19
18
17
16
15
14
13
12
11
10
108
-60
-40
-20
0
20
40
60
80
100
120
-60
140
-40
-20
20
40
60
80
100
120
140
Figure 18. Supply Current Primary-Side I VCC vs. Ambient Temperature.
Conditions: V VCC = 5 V, V TOT = 25 V, No-Load.
35
30
25
20
15
10
5
11
0
PI-7915-050416
PI-7947-042816
40
Supply Current IVISO (mA)
Figure 17. Input Bias Current vs. Ambient Temperature.
Conditions: V VCC = 5 V, VIN = 5 V, V TOT = 25 V.
Supply Current IVCC (mA)
0
Ambient Temperature (°C)
Ambient Temperature (°C)
11
10
10
IN = 0 V DC
IN = 5 V DC
fS = 20 kHz
fS = 75 kHz
9
9
8
8
7
7
6
0
50
100
150
200
250
300
-60
-40
-20
Switching Frequency – fS (kHz)
15
VTOT = 22 V
VTOT = 25 V
VTOT = 28 V
10
40
60
80
100
120 140
5
0
PI-7918-041416
350
Propagation Delay (ns)
20
20
Figure 20. Supply Current Secondary-Side I VISO vs. Ambient Temperature. Conditions: V VCC = 5 V, V TOT = 25 V, No-Load.
PI-7916-050416
25
0
Ambient Temperature (°C)
Figure 19. Supply Current Primary-Side I VCC vs. Switching Frequency. Conditions: V VCC = 5 V, V TOT = 25 V, TA= 25 °C, fS ≥ 0 Hz
≤ 250 kHz, No-Load.
Supply Current IVISO (mA)
PI-7917-050416
116
20
Supply Current IVCC (mA)
PI-7913-0040116
Input Bias Current IIN (µA)
117
300
250
tP(HL), Turn-On Delay
tP(LH), Turn-Off Delay
200
150
100
50
0
0
50
100
150
200
250
300
-60
-40
Switching Frequency – fS (kHz)
Figure 21. Supply Current Secondary-Side I VISO vs. Ambient Temperature. Conditions: V VCC = 5 V, V TOT = 25 V, No-Load.
16
Rev. A 05/16
-20
0
20
40
60
80
100
120
140
Ambient Temperature (°C)
Figure 22. Propagation Delay Time vs. Ambient Temperature.
Conditions: V VCC = 5 V, V TOT = 25 V, fS = 20 kHz, CLOAD = 2.2 nF.
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SID11x2K
10.0
8.0
6.0
4.0
2.0
4.5
0.0
-40
-20
0
20
40
60
80
100
120
3.5
Clear Fault
Set Fault
3.0
2.5
2.0
1.5
1.0
0.5
0.0
140
-60
-40
-20
Ambient Temperature (°C)
140
120
100
80
60
40
20
00
0
20
40
60
80
100
120
140
600
500
400
300
200
100
0
0
20
40
60
80
100
120
140
12
10
140
Clear Fault
Set Fault
8
6
4
2
0
-60
-40
-20
0
20
40
60
80
100
120
6
5
Clear Fault
Set Fault
4
140
3
2
1
0
-60
-40
Ambient Temperature (°C)
Figure 27 Power Supply Monitoring Positive Rail Hysteresis UVLOVISO vs. Ambient Temperature. Conditions: V VCC = 5 V.
-20
0
20
40
60
80
100
120
Ambient Temperature (°C)
Figure 28. Power Supply Monitoring Negative Rail UVLOVEE vs. Ambient Temperature. Conditions: V VCC = 5 V.
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120
Figure 26. Power Supply Monitoring Positive Rail UVLOVISO vs. Ambient Temperature. Conditions: V VCC = 5 V.
Secondary-Side Power Supply
Monitoring Negative Rail UVLOVEE (V)
PI-7923-040116
Secondary-Side Power Supply Monitoring
Positive Rail Hysteresis UVLOVISO (mV)
700
-20
100
Ambient Temperature (°C)
800
-40
80
14
Ambient Temperature (°C)
Figure 25. Power Supply Monitoring Hysteresis UVLOVCC vs. Ambient Temperature. Conditions: V TOT = 25 V.
-60
60
PI-7924-040116
160
Secondary-Side Power Supply
Monitoring Positive Rail UVLOVISO (V)
PI-7922-040116
Primary-Side Power Supply
Monitoring Hysteresis UVLOVCC (mV)
180
-20
40
Ambient Temperature (°C)
200
-40
20
Figure 24. Power Supply Monitoring UVLOVCC vs. Ambient Temperature. Conditions: V TOT = 25 V.
Figure 23. SO Fault Signalization Time vs. Ambient Temperature.
Conditions: V VCC = 5 V, V TOT = 25 V, RSO = 4.7 kW.
-60
0
PI-7926-040116
-60
4.0
PI-7921-040116
PI-7919-040116
12.0
Primary-Side Power Supply
Monitoring UVLOVCC (V)
SO Fault Signalization Time – tSO (µs)
Typical Performance Characteristics
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are subject to change without notice.
17
Rev. A 05/16
140
SID11x2K
200
150
100
50
0
-40
-20
0
20
40
60
80
100
120
8.5
8.0
VTOT = 22 V
VTOT = 25 V
VTOT = 28 V
7.5
7.0
6.5
6.0
5.5
5.0
-60
140
-40
-20
40
60
80
100
120
140
PI-7928-050416
2.9
VTOT = 22 V and VVISO = 17.5 V
VTOT = 25 V and VVISO = 17.5 V
VTOT = 28 V and VVISO = 17.5 V
3.1
3.2
3.3
3.4
3.5
Figure 30. Desaturation Detection Level VDES vs. Ambient Temperature. Conditions: V VCC = 5 V.
3.50
IVEE(SI) Sink Capability (mA)
Figure 29. Power Supply Monitoring Negative Rail Hysteresis UVLOVEE vs. Ambient Temperature. Conditions: V VCC = 5 V.
IVEE(SO) Source Capability (mA)
20
Ambient Temperature (°C)
Ambient Temperature (°C)
3.0
0
PI-7948-050416
-60
9.0
PI-7927-040116
250
DESAT Detection Level VDES (V)
300
PI-7925-040116
Secondary-Side Power Supply Monitoring
Negative Rail Hysteresis UVLOVEE (V)
Typical Performance Characteristics
VTOT = 22 V and VVISO = 12.5 V
VTOT = 25 V and VVISO = 12.5 V
VTOT = 28 V and VVISO = 12.5 V
3.45
3.40
3.35
3.30
3.25
3.20
3.15
3.10
3.05
3.00
3.6
-60
-40
-20
0
20
40
60
80
100
120
140
-60
-40
Ambient Temperature (°C)
Figure 31. VEE Source Capability I VEE(SO) vs. Ambient Temperature and V VISO. Conditions: V VCC = 5 V, fS = 20 kHz, Duty Cycle = 50%.
18
Rev. A 05/16
-20
0
20
40
60
80
100
120
140
Ambient Temperature (°C)
Figure 32. VEE Sink Capability I VEE(SI) vs. Ambient Temperature and V VISO. Conditions: V VCC = 5 V, fS = 20 kHz, Duty Cycle = 50%.
PRELIMINARY
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
www.power.com
SID11x2K
eSOP-R16B
3
2X
4
0.023 [0.58] 13X
0.018 [0.46]
0.010 [0.25] M C A B
2X
0.004 [0.10] C B
0.050 [1.27]
0.400 [10.16]
A
8 Lead Tips
0.006 [0.15] C
9
16
0.057 [1.45] Ref.
2
H
9
10 11 12 13 14 15 16
0.010 [0.25]
Gauge Plane
2
0.059 [1.50]
Ref. Typ.
0.464 [11.79]
0.350 [8.89]
B
0.004 [0.10] C A
0° - 8°
0.059 [1.50]
Ref. Typ.
8
7
0.006 [0.15] C
4 Lead Tips
3
4
0.158 [4.01]
0.045 [1.14] Ref.
0.152 [3.86]
1
8
Pin #1 I.D.
(Laser Marked)
6
5
4
3
Seating Plane
DETAIL A
0.020 [0.51]
Ref.
1
0.010 [0.24]
Ref.
0.022 [0.56] Ref.
0.019 [0.48]
Ref.
0.080 [2.03] Ref.
TOP VIEW
0.032 [0.81]
0.029 [0.74]
0.028 [0.71]
Ref.
BOTTOM VIEW
C
0.040 [1.02]
0.028 [0.71]
0.010 [0.25] Ref.
Detail A
0.356 [9.04]Ref.
0.105 [2.67]
0.093 [2.36]
0.012 [0.30]
0.004 [0.10]
Seating Plane to
Molded Bumps
Standoff
0.306 [7.77] Ref.
0.049 [1.23]
0.046 [1.16]
7
C
0.004 [0.10] C
12 Leads
SIDE VIEW
0.71 [.028]
1.27 [.050]
3
0.016 [0.41]
0.011 [0.28]
12X
Seating
Plane
0.092 [2.34]
0.086 [2.18]
END VIEW
1.78 [.070]
11.68 [.460]
Reference
Solder Pad
Dimensions
4.11 [.162]
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold
flash, tie bar burrs, gate burrs, and inter-lead flash, but including any mismatch between the top
and bottom of the plastic body. Maximum mold protrusion is 0.007 [0.18] per side.
3. Dimensions noted are inclusive of plating thickness.
4.19 [.165]
7.62 [.300]
8.89 [.350]
mm [INCH]
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in inches [mm].
6. Datums A and B to be determined in Datum H.
7. Exposed metal at the plastic package body outline/surface between leads 6 and 7, connected
internally to wide lead 3/4/5/6.
PRELIMINARY
www.power.com
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
PI-6995-050416
POD-eSOP-R16B Rev B
19
Rev. A 05/16
SID11x2K
MSL Table
Part Number
MSL Rating
SID11x2K
3
ESD and Latch-Up Table
Test
Conditions
Latch-up at 125 °C
JESD78D
Human Body Model ESD
JESD22-A114F
Results
> ±100 mA or > 1.5 V (max) on all pins
> ±2000 V on all pins
IEC 60664-1 Rating Table
Parameter
Conditions
Specifications
Basic Isolation Group
Material Group
I
Rated mains voltage ≤ 150 VRMS
I - IV
Rated mains voltage ≤ 300 VRMS
I - IV
Rated mains voltage ≤ 600 VRMS
I - IV
Rated mains voltage ≤ 1000 VRMS
I - III
Installation Classification
Regulatory Information Table
VDE
UL
CSA
Certified according to (DIN V VDE V 0884-10
(VDE V 0884-10):2006-12
UR recognized under UL1577 Component
Recognition Program
UR recognized to CSA Component Acceptance
Notice 5A
Reinforced insulation for Max. Transient
Isolation voltage 8 kVPEAK, Max. Surge
Isolation voltage 8 kVPEAK, Max. Repetitive
Peak isolation voltage 1414 VPEAK
Single protection, 5000 VRMS dielectric voltage
withstand*
Single protection, 5000 VRMS dielectric voltage
withstand*
Certification pending
File E358471
File E358471
*Note: Production tested at 6 k VRMS for 1s in accordance with UL 1577.
Part Ordering Information
• SCALE-iDriver Product Family
• Series Number
• Package Identifier
K
eSOP-R16B
• Tape & Reel and Other Options
Blank
SID 11x2 K - TL
20
Rev. A 05/16
TL
Tube of 48 pcs.
Tape & Reel, 2500 pcs min/mult.
PRELIMINARY
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
www.power.com
SID11x2K
Notes
PRELIMINARY
www.power.com
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
21
Rev. A 05/16
Revision Notes
A
Date
Initial Release.
05/16
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at http://www.power.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, SENZero, SCALE-iDriver, Qspeed, PeakSwitch, LYTSwitch, LinkZero, LinkSwitch, InnoSwitch, HiperTFS,
HiperPFS, HiperLCS, DPA-Switch, CAPZero, Clampless, EcoSmart, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are trademarks of
Power Integrations, Inc. Other trademarks are property of their respective companies. ©2016, Power Integrations, Inc.
Power Integrations Worldwide Sales Support Locations
World Headquarters
5245 Hellyer Avenue
San Jose, CA 95138, USA.
Main: +1-408-414-9200
Customer Service:
Phone: +1-408-414-9665
Fax: +1-408-414-9765
e-mail: [email protected]
China (Shanghai)
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North Caoxi Road
Shanghai, PRC 200030
Phone: +86-21-6354-6323
Fax: +86-21-6354-6325
e-mail: [email protected]
Germany
Lindwurmstrasse 114
80337 Munich
Germany
Phone: +49-895-527-39110
Fax: +49-895-527-39200
e-mail: [email protected]
Germany
HellwegForum 1
59469 Ense
Germany
Tel: +49-2938-64-39990
e-mail: igbt-driver.sales@
power.com
India
China (Shenzhen)
#1, 14th Main Road
17/F, Hivac Building, No. 2, Keji Nan Vasanthanagar
8th Road, Nanshan District,
Bangalore-560052 India
Shenzhen, China, 518057
Phone: +91-80-4113-8020
Phone: +86-755-8672-8689
Fax: +91-80-4113-8023
Fax: +86-755-8672-8690
e-mail: [email protected]
e-mail: [email protected]
Italy
Via Milanese 20, 3rd. Fl.
20099 Sesto San Giovanni (MI) Italy
Phone: +39-024-550-8701
Fax: +39-028-928-6009
e-mail: [email protected]
Japan
Kosei Dai-3 Bldg.
2-12-11, Shin-Yokohama,
Kohoku-ku
Yokohama-shi, Kanagawa
222-0033 Japan
Phone: +81-45-471-1021
Fax: +81-45-471-3717
e-mail: [email protected]
Korea
RM 602, 6FL
Korea City Air Terminal B/D, 159-6
Samsung-Dong, Kangnam-Gu,
Seoul, 135-728, Korea
Phone: +82-2-2016-6610
Fax: +82-2-2016-6630
e-mail: [email protected]
Singapore
51 Newton Road
#19-01/05 Goldhill Plaza
Singapore, 308900
Phone: +65-6358-2160
Fax: +65-6358-2015
e-mail: [email protected]
Taiwan
5F, No. 318, Nei Hu Rd., Sec. 1
Nei Hu Dist.
Taipei 11493, Taiwan R.O.C.
Phone: +886-2-2659-4570
Fax: +886-2-2659-4550
e-mail: [email protected]
UK
Cambridge Semiconductor,
a Power Integrations company
Westbrook Centre, Block 5, 2nd Floor
Milton Road
Cambridge CB4 1YG
Phone: +44 (0) 1223-446483
e-mail: [email protected]
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