DESIGN IDEAS I2C Dual Fan Speed Controller Increases Efficiency and by Dilian Reyes Reduces Noise Busy servers and rack-based network and telecom equipment rely on hard-working cooling systems to keep from melting down. The simplest cooling system is a bank of fans running at full tilt, all of the time. This approach ensures a cool environment, but overcompensation is neither efficient, nor is it good for the fans. High output fans that work full time do not last very long (their bearings wear out), are not very efficient (they use power also), and are noisy (especially when their bearings wear out). The LTC1840 dual fan speed controller reduces the wear on bearings, and noise, by continuously adjusting fan speed to match the instantaneous cooling requirements of the system. REGULATOR 12V VIN FAN POWER (1.36V TO 12VMAX) VO VFB 1.23V FB R1 105k 1% FAN 1 TACH OUT FAN 2 TACH OUT LTC1840 SCL IDAC SDA TACH I2C R2 1M 1% IDAC (0µA TO 100µA) Figure 1. LTC1840 fan speed control block diagram The LTC1840 monitors and controls multiple fans via an I2C and SMBus compatible 2-wire serial interface. It provides two fan speed control channels, features fan tachometer and fault monitoring, nine slave addresses and four general-pur- pose programmable I/O pins, all in a convenient 16-pin SSOP package. Figure 1 shows a block diagram for a fan speed control system using the LTC1840. The LTC1840 contains two current output DACs that control fan speed. The scaled currents individu- 12V TP0101TS 12V 100k BAT54 TN0205A RC1 10k CC1 220pF RSENSE1 0.05Ω VIN RUN/SS SENSE LTC1771 PGATE ITH CVIN1 22µF + Si6447DQ L1 47µH RFB1B 1M GND 1 SCL 2 SDA 10k NC 130Ω FAULT NC LED1 3.3V 10k -A- 3 4 5 6 7 8 SCL VCC SDA IDACOUTA A1 IDACOUTB + 14 FAULT 13 SYSTEM BLAST RESET 12 TACHB GPIO1 TACHA GPIO2 GPIO4 GND GPIO3 12V 9 RSENSE2 0.05Ω VIN RUN/SS SENSE LTC1771 ITH PGATE 11 10 10k L1 = SUMIDA CDRH125-15OMC (847) 956-0667 R1, R2, RFB = 1% 16 15 TACH OUT -A- 10µF LTC1840 A0 10k 10k DC FAN TACH OUT 2-PAPST 4312/2 MULTIFAN 12V DC 420mA 5W UPS5817 0.1µF DC FAN COUT2 150µF 16V 3.3V 3.3V 3.3V (4.5V TO 12V) RFB1A 105k MODE VFB CFB1 100pF + RC2 10k CC2 220pF VFB CFB2 100pF + CVIN2 22µF Si6447DQ L2 47µH + RFB2B 1M MODE GND BYS10-25 RFB2A 105k COUT2 150µF 16V TACH OUT DC FAN DC FAN TACH OUT UPS5817 2-PAPST 4312/2 MULTIFAN 12V DC 420mA 5W ADDRESS = 1110010 (8 OTHERS POSSIBLE) TO AUTOMATICALLY MUX TACHB BETWEEN THE TWO PARALLEL FANS, SET GPIO2 TO BLINK Figure 2. Controlling four fans with the LTC1840 Linear Technology Magazine • December 2001 35 DESIGN IDEAS ally adjust the fan-driving output voltage of a switching regulator. VO increases as the current IDAC is increased under command of the serial interface. The number of fans controlled by one DAC is limited only by the switching regulator output power. The TACH pin of the LTC1840 monitors the speed of fans that include a tachometer output. Internal logic accumulates a maximum of 255 counts between the fan tachometer’s rising edges. The rate of the counter is determined by a divisor (2, 4, 8 or 16 chosen via the serial interface) from the 50kHz internal oscillator. Fans slowing down due to worn bearings or halted from a jam will cause an overflow in the internal counter and a corresponding bit is set low in the fault register. The system controller can then take action, shutting down the faulty fan and summoning maintenance. The chip contains four generalpurpose input/output (GPIO) pins, which are configured independently. As open-drain outputs, they can be set high, low or to pulse at a 1.5Hz rate. The outputs are rated at 10mA sink current so they can drive LEDs. When the GPIO pins are configured as inputs, they can monitor thermal switches, push buttons and the fault or power good outputs of switching regulators and Hot Swap™ control- lers. A fault register detects and flags state changes. Internal data registers are read and programmed via I2C by specifying device address and register address. DACA and DACB registers control the 100µA current outputs on a 255-step scale. The STATUS register allows the user to enable the TACHA and TACHB fault data and set the divisor for the internal counter frequency. The internal count, which is inversely proportional to tachometer speed, is stored in the TACHA and TACHB registers. Unmasked faults set the FAULT pin high as an instant hardware alert. The GPIO setup and GPIO data registers configure the GPIO pins, assign output and fault status, and read input state. Continuous System Cooling and Tachometer Monitoring The circuit in Figure 2 demonstrates the capabilities of the LTC1840. Each of the two LTC1771 high efficiency step-down regulators can supply power for up to four 12V, 420mA fans. As shown, the upper LTC1771 drives a single fan backed up by an idle, redundant fan. In the event the primary fan fails, GPIO3 turns off the LTC1771 and simultaneously activates the backup fan at full speed. These two fans operate one at a time so their tachometer outputs are wired OR, and only one input (TACHA) is required to monitor their speed. The other two fans are driven in parallel by the second LTC1771 and alternately monitored by TACHB. These fans operate concurrently, so their tachometer outputs are muxed by a quad NAND gate. GPIO2 operates in pulsing mode and serves to clock the mux. Additional Features For applications requiring multiple fan controllers, the LTC1840’s threestate (high, low, no connect) address programming inputs support nine user-selectable slave addresses. The FAULT output bypasses the serial interface and brings immediate attention to fault conditions detected by the LTC1840, including slowdowns in the tachometer and changes in GPIO logic state. If the BLAST pin is high at startup or presented with a high to low transition at anytime, the DAC output currents are immediately forced to full scale and the chip awaits commands from the serial bus. In addition, when BLAST is set high the LTC1840 guards against system controller crashes with an internal watchdog timer. If the device is not accessed for a period of more than 1.5 minutes, both DAC outputs go to full scale to guarantee adequate cooling. LTC1960, continued from page 16 situations. Accurate wall adapter voltage detection can be critical. The LTC1960 has a user adjustable wall adapter input voltage trip point setting with less than a 2% error. For example, you can have valid AC present detection with a wall adapter rated as low as 13.2V and still charge a 12.6V 3-cell Li-Ion battery. Simple Serial Interface The serial connections are based on the Serial Peripheral Interface (SPI) protocol, a communications system that allows a host CPU to communicate with many peripheral devices. SPI is a very simple TTL level interface 36 that does not require any special interface requirements from the host microprocessor. A simple bit-banging method using standard logic outputs makes the part compatible with any microprocessor. Given the high level of LTC1960 functional integration, the serial interface dramatically reduces the number of required signals between the host and the IC, freeing up host pins for other functions. Conclusion The LTC1960 represents the first complete dual battery discharge-charge system solution on a chip. It reduces solution cost, development time, PCB space and part count while at the same time providing more control, safety, and automatic crisis management relative to any other solution available today. Combined with a host microcontroller, it has the flexibility to work in both user proprietary and Smart Battery based applications. The limits of what can be accomplished with LTC1960 are solely dependent on the software controlling the IC. Although the primary LTC1960 market is notebooks and portable battery applications, its expandability also makes it a good solution for many battery backup applications, such as those in small servers. Linear Technology Magazine • December 2001