MCT3A65P100F2, MCT3D65P100F2 Semiconductor CE April 1999 [ /Title (MCT3 A65P1 00F2, MCT3 D65P1 00F2) /Subject (65A, 1000V, PType MOSControlled Thyristor (MCT) ) /Autho r () /Keywords () /Creator () /DOCI NFO pdfmark IGNS WN DRA EW DES H T I TW ON PAR ETE - N L BSO SS O PRO 65A, 1000V, P-Type MOS-Controlled Thyristor (MCT) Features Description • 65A, -1000V The MCT is an MOS Controlled Thyristor designed for switching currents on and off by negative and positive pulsed control of an insulated MOS gate. It is designed for use in motor controls, inverters, line switches, and other power switching applications. • VTM = -1.4V (Max) at I = 65A and 150oC • 2000A Surge Current Capability The MCT is especially suited for resonant (zero voltage or zero current switching) applications. The SCR like forward drop greatly reduces conduction power loss. • 2000A/µs di/dt Capability • MOS Insulated Gate Control • 100A Gate Turn-Off Capability at 150oC MCTs allow the control of high power circuits with very small amounts of input energy. They feature the high peak current capability common to SCR type thyristors, and operate at junction temperatures up to 150oC with active switching. Part Number Information PART NUMBER PACKAGE MCT3A65P100F2 TO-247 M65P100F2 MCT3D65P100F2 MO-093AA M65P100F2 NOTE: Formerly developmental type TA49226. BRAND Symbols When ordering, use the entire part number. ANODE GATE (ANODE KELVIN) GATE RETURN ANODE GATE CATHODE CATHODE (TAB) CATHODE Packaging JEDEC MO-093AA CATHODE (FLANGE) JEDEC STYLE TO-247 ANODE ANODE CATHODE GATE RETURN GATE CATHODE (BOTTOM SIDE METAL) ANODE ANODE CATHODE GATE RETURN GATE [ /PageMode /UseOutlines /DOCVIEW CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper ESD Handling Procedures. Copyright © Harris Corporation 1999 1 File Number 4454.2 MCT3A65P100F2, MCT3D65P100F2 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified MCT3A65P100F2 MCT3D65P100F2 UNITS Peak Off-State Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDRM -1000 V Peak Reverse Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VRRM 5 V 85 A Continuous Cathode Current At TC = 25oC (Package Limited). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IK25 At TC = 110oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IK110 65 A Non-repetitive Peak Cathode Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IKSM 2000 A Peak Controllable Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IKC 100 A Gate to Anode Voltage (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGA ±15 V Gate to Anode Voltage (Peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGA ±20 V Rate of Change of Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dv/dt Figure 11 Rate of Change of Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . di/dt 2000 A/µs Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT 290 W Power Dissipation Derating TC > 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.32 W/oC Operating and Storage Junction Temperature Range . . . . . . . . . . . . . . . . . . . . TJ , TSTG -55 to 150 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL 300 oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum Pulse Width of 200µs (Half Sine). Assume TJ (Initial) = 90oC and TJ (Final) = TJ (Max) = 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER Peak Off-State Blocking Current Peak Reverse Blocking Current On-State Voltage SYMBOL IDRM IRRM VTM TEST CONDITIONS VKA = -1000V VGA = 15V VK = 5V VGA = 15V IK = IK110 VGA = -10V TC = 150oC TC = 25oC TC = 150oC TC = 25oC TC = 150oC TC = 25oC MIN TYP MAX UNITS - - 3 mA - - 100 µA - - 4 mA - - 100 µA - 1.25 1.4 V - 1.35 1.5 V Gate to Anode Leakage Current IGAS VGA = ±20V - - 200 nA Input Capacitance CISS VGA = 15V, VKA = -20V, f = 1MHz - 12 - nF TC = 150oC - 125 - ns - 70 - ns - 770 - ns - 1000 1400 ns - 2.8 - mJ - 15 - mJ 0.43 oC/W Current Turn-On Delay Time Current Rise Time Current Turn-Off Delay Time td(ON)I trI td(OFF)I Current Fall Time tfI Turn-On Energy EON Turn-Off Energy (Note 2) EOFF Thermal Resistance Junction To Case L = 200µH IK = IK110 = 65A VKA = -400V VGA = 15V/-10V RG = 2.2Ω Test Circuit (Figure 13) RθJC - - NOTE: 2. Turn-Off Energy Loss (EOFF) is defined as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and ending at the point where the cathode current equals zero (IK = 0A). All devices were tested per JEDEC Standard No. 24-1 Method for Measurement of Power Device Turn-Off Switching Loss. This test method produces the true total Turn-Off Energy Loss. Turn-On losses include losses due to diode recovery. 2 MCT3A65P100F2, MCT3D65P100F2 Typical Performance Curves (Unless Otherwise Specified) 100 PULSE TEST PULSE DURATION - 250µs 100 DUTY CYCLE < 2% PACKAGE LIMIT IK , DC CATHODE CURRENT (A) IK , CATHODE CURRENT (A) 300 TJ = 150oC 10 TJ = 25oC TJ = -40oC 1 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 VTM , CATHODE VOLTAGE (V) 1.8 60 40 20 0 20 2.0 60 40 120 140 160 td(OFF)i , TURN-OFF DELAY TIME (µs) 2.0 TJ = 150oC, RG = 2.2Ω, L = 200µH 160 VKA = -400V 140 120 VKA = -500V 100 80 0 10 20 30 40 50 60 70 80 90 TJ = 150oC, RG = 2.2Ω, L = 200µH 1.8 1.6 1.4 1.2 VKA = -500V 1.0 0.8 VKA = -400V 0.6 0.4 0.2 0 60 100 0 10 20 30 40 50 60 70 80 90 100 IK , CATHODE CURRENT (A) IK , CATHODE CURRENT (A) FIGURE 3. TURN-ON DELAY TIME vs CATHODE CURRENT FIGURE 4. TURN-OFF DELAY TIME vs CATHODE CURRENT 80 1.2 TJ = 150oC, RG = 2.2Ω, L = 200µH TJ = 150oC, RG = 2.2Ω, L = 200µH VKA = -400V 1.0 VKA = -400V 60 tfI , FALL TIME (µs) trI , RISE TIME (ns) 100 FIGURE 2. DC CATHODE CURRENT vs CASE TEMPERATURE 180 70 80 TC , CASE TEMPERATURE (oC) FIGURE 1. CATHODE CURRENT vs SATURATION VOLTAGE td(ON)I , TURN-ON DELAY TIME (ns) 80 50 VKA = -500V 40 30 20 0.8 VKA = -500V 0.6 0.4 0.2 10 0 0 10 20 30 40 50 60 70 80 90 0 100 IK , CATHODE CURRENT (A) FIGURE 5. TURN-ON RISE TIME vs CATHODE CURRENT 0 10 20 30 40 50 60 70 IK , CATHODE CURRENT (A) 80 90 100 FIGURE 6. TURN-OFF FALL TIME vs CATHODE CURRENT 3 MCT3A65P100F2, MCT3D65P100F2 Typical Performance Curves (Unless Otherwise Specified) (Continued) TJ = 150oC, RG = 2.2Ω, L = 200µH EOFF , TURN-OFF ENERGY LOSS (mJ) EON , TURN-ON ENERGY LOSS (mJ) 10 VKA = -500V VKA = -400V 1 0.4 0 10 20 30 40 50 60 70 80 90 30 VKA = -500V VKA = -400V 10 1 100 TJ = 150oC, RG = 2.2Ω, L = 200µH 0 10 20 IK , CATHODE CURRENT (A) TJ = 150oC, L = 200µH RG = 2.2Ω 10 TC = 75oC VKA = - 400V VKA = - 500V 100 IK , CATHODE CURRENT (A) 200 FIGURE 9. OPERATING FREQUENCY vs CATHODE CURRENT 80 90 100 CS = 1.0µF CS = 0.7µF 80 CS = 0µF 60 40 20 0 -1000 -400 -600 -800 -200 VKA , PEAK TURN OFF VOLTAGE (V) FIGURE 10. TURN-OFF CAPABILITY vs ANODE TO CATHODE VOLTAGE CS = 0.1µF, TJ = 150oC CS = 0.1µF, TJ = 25oC CS = 1.0µF, TJ = 150oC TJ = 150oC, VGA = 15V VSPIKE , SPIKE VOLTAGE (V) VDRM , BREAKDOWN VOLTAGE (V) 70 100 100 1100 60 TJ = 150oC, RG = 2.2Ω, L = 200µH 0 1 10 50 120 fMAX1 = 0.05/(td(OFF)I + td(ON)I) fMAX2 = (PD - PC)/(EON + EOFF) PD = ALLOWABLE DISSIPATION PC = CONDUCTION DISSIPATION (DUTY FACTOR = 50%) RθJC = 0.43oC/W TC = 110oC 40 FIGURE 8. TURN-OFF ENERGY LOSS vs CATHODE CURRENT IK , PEAK CATHODE CURRENT (A) fMAX , MAX OPERATING FREQUENCY (kHz) FIGURE 7. TURN-ON ENERGY LOSS vs CATHODE CURRENT 100 30 IK , CATHODE CURRENT (A) 1050 1000 950 900 CS = 1.0µF, TJ = 25oC CS = 2.0µF, TJ = 150oC CS = 2.0µF, TJ = 25oC 10 850 1 800 10-1 100 101 102 103 0 104 10 20 30 40 50 60 70 80 90 di/dt, RATE OF CHANGE OF CURRENT (A/µs) dv/dt, RATE OF CHANGE OF VOLTAGE (V/µs) FIGURE 12. SPIKE VOLTAGE vs RATE OF CHANGE OF CURRENT FIGURE 11. BLOCKING VOLTAGE vs RATE OF CHANGE OF VOLTAGE 4 100 MCT3A65P100F2, MCT3D65P100F2 Test Circuits and Waveforms MAXIMUM RISE AND FALL TIME OF VG IS 200ns 200µH VG 90% 10% VK IK EOFF + EON -VKA VG 90% DUT 10% Ik trI td(off)I td(on)I tfI DIODES RURG75120 FIGURE 13. INDUCTIVE SWITCHING TEST CIRCUIT FIGURE 14. SWITCHING TEST WAVEFORMS VG VG + di/dt 9V - VA 500Ω + IK 20V + VSPIKE 10kΩ 4.7kΩ CS DUT VTM IK VAK FIGURE 15. VSPIKE TEST CIRCUIT FIGURE 16. VSPIKE TEST WAVEFORMS 5 MCT3A65P100F2, MCT3D65P100F2 Handling Precautions for MCTs Operating Frequency Information MOS Controlled Thyristors are susceptible to gate-insulation damage by the electrostatic discharge of energy through the devices. When handling these devices, care should be exercised to assure that the static charge built in the handler’s body capacitance is not discharged through the device. MCTs can be handled safely if the following basic precautions are taken: Operating frequency information for a typical device (Figure 9) is presented as a guide for estimating device performance for a specific application. Other typical frequency vs cathode current (IAK) plots are possible using the information shown for a typical unit in Figures 3 to 8. The operating frequency plot (Figure 9) of a typical device shows fMAX1 or fMAX2 whichever is smaller at each point. The information is based on measurements of a typical device and is bounded by the maximum rated junction temperature. 1. Prior to assembly into a circuit, all leads should be kept shorted together either by the use of metal shorting springs or by the insertion into conductive material such as “ECCOSORBD™ LD26” or equivalent. fMAX1 is defined by fMAX1 = 0.05/(td(OFF)I + td(ON)I). Deadtime (the denominator) has been arbitrarily held to 10% of the on- state time for a 50% duty factor. Other definitions are possible. td(OFF)I and td(ON)I are defined in Figure 14. Device turn-off delay can establish an additional frequency limiting condition for an application other than TJMAX. td(OFF) is important when controlling output ripple under a lightly loaded condition. 2. When devices are removed by hand from their carriers, the hand being used should be grounded by any suitable means - for example, with a metallic wristband. 3. Tips of soldering irons should be grounded. 4. Devices should never be inserted into or removed from circuits with power on. fMAX2 is defined by fMAX2 = (PD - PC)/(EOFF + EON). The allowable dissipation (PD) is defined by PD = (TJMAX - TC)/RθJC. The sum of device switching and conduction losses must not exceed PD . A 50% duty factor was used (Figure 9) and the conduction losses (PC) are approximated by PC = (VAK x IAK)/2. 5. Gate Voltage Rating - Never exceed the gate-voltage rating of VGAM. Exceeding the rated VGA can result in permanent damage to the oxide layer in the gate region. 6. Gate Termination - The gates of these devices are essentially capacitors. Circuits that leave the gate opencircuited or floating should be avoided. These conditions can result in turn-on of the device due to voltage buildup on the input capacitor due to leakage currents or pickup. EON and EOFF are defined in the switching waveforms shown in Figure 14. EON is the integral of the instantaneous power loss (IAK x VAK) during turn-on and EOFF is the integral of the instantaneous power loss (IAK x VAK) during turn-off. All tail losses are included in the calculation for EOFF; i.e. the cathode current equals zero (IK = 0). 7. Gate Protection - These devices do not have an internal monolithic zener diode from gate to anode. If gate protection is required an external zener is recommended. ECCOSORBD is a Trademark of Emerson and Cumming, Inc. 6 MCT3A65P100F2, MCT3D65P100F2 TO-247 5 LEAD JEDEC STYLE TO-247 PLASTIC PACKAGE E A INCHES TERM. 6 ØS ØP SYMBOL Q ØR D b1 L1 b2 L b 1 2 3 4 5 J1 e 4 3 2 1 BACK VIEW e1 MILLIMETERS MIN MAX NOTES 0.180 0.190 4.58 4.82 - b 0.046 0.051 1.17 1.29 2, 3 b1 0.060 0.070 1.53 1.77 1, 2 b2 0.095 0.105 2.42 2.66 1, 2 c 0.020 0.026 0.51 0.66 1, 2, 3 D 0.800 0.820 20.32 20.82 - E 0.605 0.625 15.37 15.87 e1 5 MAX A e c MIN 0.110 TYP 0.438 BSC - 2.79 TYP 4 11.12 BSC 4 J1 0.090 0.105 2.29 2.66 5 L 0.620 0.640 15.75 16.25 - L1 0.145 0.155 3.69 3.93 1 ØP 0.138 0.144 3.51 3.65 - Q 0.210 0.220 5.34 5.58 - LEAD 1 - GATE LEAD 2 - GATE RETURN ØR 0.195 0.205 4.96 5.20 - LEAD 3 - CATHODE ØS 0.260 0.270 6.61 6.85 - LEAD 4 - ANODE LEAD 5 ANODE TERM. 6 CATHODE NOTES: 1. Lead dimension and finish uncontrolled in L1. 2. Lead dimension (without solder). 3. Add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 5. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 6. Controlling dimension: Inch. 7. Revision 1 dated 1-93. 7 MCT3A65P100F2, MCT3D65P100F2 MO-093AA 5 LEAD JEDEC MO-093AA PLASTIC PACKAGE INCHES E SYMBOL A1 Q H1 TERM. 6 D b1 L1 L 1 2 3 4 5 b e J1 e1 LEAD 1 - GATE LEAD 2 - GATE RETURN LEAD 3 - CATHODE LEAD 4 - ANODE LEAD 5 ANODE TERM. 6 CATHODE MIN MAX MIN MAX NOTES A 0.185 0.195 4.70 4.95 - A1 0.058 0.062 1.48 1.57 - b 0.049 0.053 1.25 1.34 3, 4, 5 b1 0.070 0.080 1.78 2.03 3, 4 c 0.018 0.022 0.46 0.55 3, 4, 5 D 0.800 0.820 20.32 20.82 - E 0.615 0.625 15.63 15.87 2 e c 75o MILLIMETERS A ØP 0.110 TYP 2.80 TYP 7 e1 0.438 BSC 11.12 BSC 7 H1 - - 8.38 - 0.330 J1 0.115 0.125 2.93 3.17 8 L 0.575 0.600 14.61 15.24 - L1 - 0.130 - 3.30 3 ØP 0.159 0.163 4.04 4.14 - Q 0.176 0.186 4.48 4.72 2 NOTES: 1. These dimensions are within allowable dimensions of Rev. A of JEDEC MO-093AA outline dated 2-90. 2. Tab outline optional within boundaries of dimensions E and Q. 3. Lead dimension and finish uncontrolled in L1. 4. Lead dimension (without solder). 5. Add typically 0.002 inches (0.05mm) for solder coating. 6. Maximum radius of 0.050 inches (1.27mm) on all body edges and corners. 7. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 8. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 9. Controlling dimension: Inch. 10. Revision 1 dated 1-93. 8