Datasheet

AS1376
1A, Low Input Voltage, Low Quiescent
Current LDO
General Description
The AS1376 is a Dual Supply Rail Linear Regulator designed to
deliver 1A of load current while consuming only 67μA (typ) of
ground current. In the typical post regulation application VBIAS
is directly connected to the main input supply, (range 2.5V …
5.5V) and VIN is supplied by the output voltage of a host DC-DC
Converter (range 0.7V … 4.5V).
The device offers excellent dropout (120mV @ 1A) and transient
performance.
In shutdown (Enable pin pulled low), the device turns off and
reduces quiescent current consumption to 10nA (typ) at both
VBIAS and VIN terminals.
In shutdown, a 100Ω (typ) discharge path is connected between
output and ground to provide rapid discharge of the overall
load capacitance connected to the AS1376 output terminal.
Auto-discharge minimizes the possibility that VOUT > VIN
during shutdown. When VOUT > VIN, reverse current flows
through the inherent body diode of the N-channel series pass
transistor.
The AS1376 also features internal protection against
over-temperature, over-current and under-voltage conditions.
The AS1376 is available in an 8-pin 2x2 TDFN package and
AS1376B is available in a 6-balls WL-CSP. Both package options
are qualified for operation over the -40ºC to 85ºC temperature
range.
Ordering Information and Content Guide appear at end of
datasheet.
ams Datasheet
[v2-04] 2015-Aug-16
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AS1376 − General Description
Key Benefits & Features
The benefits and features of this device are listed below:
Figure 1:
Added Value of Using AS1376
Benefits
Features
• Less internal voltage losses and minimized
self-heating
• Ultra-Low Dropout Voltage: <120mV @ 1A load
• Supports a variety of low voltage end applications
• Output Voltage from 0.5V to 3.3V
• Ideal as follower of a buck converter
• Input Voltage from 0.7V to 3.6V
• Independent bias supply ensures more robustness
due to heavy load changes
• Bias Supply Voltage from 2.5V to 5.5V
• Supports a variety of high load applications
• Maximum Output Current up to 1A
• Cost effective, small package
• 8-pin TDFN 2x2mm package
• 6-balls WL-CSP with 0.4mm pitch
Applications
The devices are ideal for powering cordless and mobile phones,
MP3 players, CD and DVD players, PDAs, hand-held computers,
digital cameras and any other hand-held and/or
battery-powered device.
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ams Datasheet
[v2-04] 2015-Aug-16
AS1376 − General Description
Block Diagram
The functional blocks of this device for reference are shown
below:
Figure 2:
Functional Blocks of AS1376
AS1376
VIN
VIN
QP OWER
VBIAS
Error
Amplifier
FB
Reference Core
VOUT
Thermal Overload
Pr otection
RDIS CHARGE
EN
Bandgab
Voltage & Cur rent
Reference
QDIS CHARGE
Shutdown Power O n
Control Logic
GND
Block Diagram: This figure shows the block diagram of AS1376
Figure 3:
Functional Blocks of AS1376B
AS1376B
VIN
QP OWER
VBIAS
Error
Amplifier
VOUT
Reference Core
Thermal Overload
Protection
RDIS CHARGE
EN
Bandgab
Voltage & Cur rent
Reference
Shutdown Power O n
Control Logic
QDIS CHARGE
GND
Block Diagram: This figure shows the block diagram of AS1376B
ams Datasheet
[v2-04] 2015-Aug-16
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AS1376 − Pin Assignments
Pin Assignments
Figure 4:
Pin Diagram of AS1376 and AS1376B
Pin A1
indicator
VIN
1
VIN
2
AS1376
8
VOUT
7
FB
6
GND
5
EN
A1
VOUT
A2
VIN
B1
GND
B2
VBIAS
C1
GND
C2
EN
TDFN 8-pin 2x2mm
VBIAS
3
GND
4
Exposed pad: GND
9
Pin Assignment: These figures show the top view pin assignment of AS1376 in 8-pin TDFN package and AS1376B
in 6-balls WL-CSP.
Figure 5:
Pin Description of AS1376 and AS1376B
Pin Number
Pin
Name
Description
8-Pin TDFN
(AS1376)
6-Pin WL-CSP
(AS1376B)
1,2
A2
VIN
3
B2
VBIAS
Bias Input Voltage. 2.5V to 5.5V.
Bypass this pin with a capacitor to GND
4,6
B1,C1
GND
Ground.
5
C2
EN
Enable. Pull this pin low to disable the device.
Feedback Pin. Connect to VOUT to select the factory
preset output voltage. For the adjustable version
connect to an external resistor divider to set the output
voltage.
7
-
FB
8
A1
VOUT
9
-
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Unregulated Input Voltage. 0.6V to 3.6V. Bypass this
pin with a capacitor to GND
Regulated Output Voltage. 0.5V to 3.3V.
Bypass this pin with a capacitor to GND
Exposed Pad. This pad is not connected internally.
Ensure a good connection to the PCB to achieve
optimal thermal performance.
ams Datasheet
[v2-04] 2015-Aug-16
AS1376 − Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated under Electrical
Characteristics is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Figure 6:
Absolute Maximum Ratings of AS1376
Symbol
Parameter
Min
Max
Units
Comments
Electrical Parameters
VIN to GND
-0.3
5.0
V
Applicable for pin: VIN
VBIAS, EN to GND
-0.3
6.5
V
Applicable for pins: VBIAS, EN
VOUT to GND
-0.3
VIN + 0.3
V
Applicable for pin: VOUT
Output Short-Circuit
Duration
ISCR
Indefinite
Input Current (latch-up
immunity)
± 100
mA
Norm: JEDEC JESD78D Nov 2011
Continuous Power Dissipation (TA = 70°C)
PT(1)
Continuous power
dissipation
0.6
W
WL-CSP
1.5
W
TDFN
V
Norm: JS-001-2014
Electrostatic Discharge
ESDHBM
Electrostatic Discharge HBM
± 1000
Temperature Ranges and Storage Conditions
TA
Operating Ambient
Temperature
RTHJA (1)
Junction to Ambient
Thermal Resistance
TJ
Operating Junction
Temperature
TSTRG
-40
85
°C
95
°C/W
WL-CSP
36
°C/W
TDFN
125
°C
-55
125
°C
WL-CSP
-55
150
°C
TDFN
Storage Temperature Range
ams Datasheet
[v2-04] 2015-Aug-16
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AS1376 − Absolute Maximum Ratings
Symbol
TBODY
RHNC
MSL
Parameter
Min
Max
Units
260
°C
Comments
WL-CSP
Norm: IPC/JEDEC
J-STD-020 (2)
TDFN
Norm: IPC/JEDEC
J-STD-020 (2)
The lead finish for
Pb-free leaded
packages is “Matte Tin”
(100% Sn)
1
WL-CSP
Represents an
unlimited floor time
1
TDFN
Represents an
unlimited floor time
Package Body Temperature
Relative Humidity
(non-condensing)
5
260
°C
85
%
Moisture Sensitivity Level
Note(s) and/or Footnote(s):
1. Depending on actual PCB layout and PCB used
2. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity
Classification for Non hermetic Solid State Surface Mount Devices
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AS1376 − Electrical Characteristics
Electrical Characteristics
All limits are guaranteed. The parameters with min and max
values are guaranteed with production tests or SQC (Statistical
Quality Control) methods.
Figure 7:
Electrical Characteristics of AS1376
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIN
Input Voltage
0.7
3.6
V
VBIAS
Bias Supply Voltage
2.5
5.5
V
VOUT
Output Voltage
Available in 100mV steps
0.5
3.3
V
IOUT = 100uA
-1.5
+1.5
-2
+2
VOUT_nom
- VOUT
VFB
%
Output Voltage Accuracy
IOUT = 0A to 1A
Feedback Voltage
IOUT = 100uA
492
500
508
mV
IOUT = 0A to 1A
490
500
510
mV
(1)
ΔVOUT /
ΔVIN
Line Regulation VIN
IOUT = 100uA
40
uV/V
ΔVOUT /
ΔVBIAS
Line Regulation VBIAS
IOUT = 100uA
135
uV/V
ΔVOUT /
ΔIOUT
Load Regulation
IOUT = 1mA to 1A
0.0002
%/mA
IOUT
Output Current (2)
ILIM
Current Limit
VDROP_
VIN
Output Voltage Dropout
VIN
VDROP_
VBIAS
Output Voltage Dropout
VBIAS
eN
Output Voltage Noise
ams Datasheet
[v2-04] 2015-Aug-16
1
A
VOUT forced to 90% of nominal
VOUT
1.35
VBIAS = VOUT + 1.5V, IOUT = 1A
120
VBIAS = VOUT + 1.8V, IOUT = 1A
115
VBIAS = VOUT + 2.1V, IOUT = 1A
110
VBIAS = 5.5V, IOUT = 1A
105
IOUT = 500mA
0.85
IOUT = 1A
1.1
f = 10Hz to 100kHz, IOUT = 1mA
65
A
mV
V
uVRMS
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AS1376 − Electrical Characteristics
Symbol
PSRR_
VIN
PSRR_
VBIAS
Parameter
Power Supply Rejection
Ratio Sine modulated
VIN
Power Supply Rejection
Ratio Sine modulated
VBIAS
Conditions
Min
Typ
f = 100Hz, IOUT = 10mA
78
f = 1kHz, IOUT = 10mA
61
f = 10kHz, IOUT = 10mA
54
f = 100kHz, IOUT = 10mA
60
f = 100Hz, IOUT = 10mA
69
f = 1kHz, IOUT = 10mA
51
f = 10kHz, IOUT = 10mA
45
f = 100kHz, IOUT = 10mA
45
Max
Unit
dB
dB
IQ_VBIAS
Quiescent Current into
VBIAS
IQ_VIN
Quiescent Current into
VIN
IOUT = 0mA
6.5
ISHDN_
VBIAS
Shutdown Current into
VBIAS
EN = 0V
0.02
uA
ISHDN_VIN
Shutdown Current into
VIN
EN = 0V
0.02
uA
IEN
Enable Input Bias Current
60
120
uA
0.001
VIH
8
1
uA
1
Enable Input Threshold
VIN = 0.7 to 3.6V
V
VIL
0.4
TSHDN
Thermal Shutdown
Temperature
155
°C
ΔTSHDN
Thermal Shutdown
Hysteresis
30
°C
ΔVOUT
Dynamic Load Transient
Response VBIAS
±35
mV
tON
Exit Delay from
Shutdown
72
us
COUT
Output Capacitor
Settling to 95%, no Load
Load Capacitor Range
Maximum ESR Load
1
10
uF
500
mΩ
Electrical Characteristics: VIN = VOUT + 0.2V, VBIAS = VOUT + 1.5V (or 2.5V whichever is larger), EN = VBIAS, CIN =
COUT = 1uF, CBIAS = 4.7uF, TAMB = -40°C to 85°C. Typical values are at TAMB = 25°C (unless otherwise specified)
Note(s) and/or Footnote(s):
1. Valid only for AS1376-BTDT-AD (adjustable output versions)
2. Limit guaranteed by design and characterization
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AS1376 − Typical Operating Characteristics
Typical Operating
Characteristics
Figure 8:
Bias Supply Current vs. Bias Supply Voltage
70
80
75
Bias Supply Current (µA)
Bias Supply Current (µA)
TAMB = 25°C
65
60
55
no load
Iout = 700mA
Iout = 1A
No load
70
65
60
55
50
- 40°C
45
+ 25°C
+ 90°C
50
40
2.5
3
3.5
4
4.5
5
5.5
2.5
Bias Supply Voltage (V)
3
3.5
4
4.5
5
5.5
Bias Supply Voltage (V)
Bias Supply Current vs. Bias Supply Voltage: VIN = 1.2V, EN = VBIAS, VOUT = 1.0V, CIN = COUT = 1uF, CBIAS = 4.7uF
Figure 9:
GND Current vs. Bias Supply Voltage
GND Current vs. Bias Supply Voltage:
VIN = 1.2V, EN = VBIAS, VOUT = 1.0V,
CIN = COUT = 1uF, CBIAS = 4.7uF
95
90
Ground Current (µA)
85
80
75
70
65
60
55
50
45
-40°C, no load
-40°C, Iout = 1A
+25°C, no load
+25°C, Iout = 1A
+85°C, no load
+85°C, Iout = 1A
40
2.5
3
3.5
4
4.5
5
5.5
Bias Supply Voltage (V)
ams Datasheet
[v2-04] 2015-Aug-16
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AS1376 − Typical Operating Characteristics
Figure 10:
GND Current vs. Load Current
GND Current vs. Load Current:
VIN = 1.2V, EN = VBIAS, VOUT = 1.0V,
CIN = COUT = 1uF, CBIAS = 4.7uF
85
Ground Current (µA)
80
75
70
65
-40°C
+25°C
60
+90°C
55
50
0
100 200 300 400 500 600 700 800 900 1000
Load Current (mA)
Figure 11:
PSRR vs. Frequency
PSRR vs. Frequency: PSRRVIN
(EN = VBIAS = 2.5V, VOUT = 1.0V, no CIN,
COUT = CBIAS = 1uF, RLOAD = 100Ω);
PSRRVBIAS (EN = VIN = 1.2V, VOUT =
1.0V, CIN = COUT = 1uF, no CBIAS,
RLOAD = 100Ω)
-40
-50
PSRR (dB)
-60
IOUT = 10mA
-70
-80
PSRR VBIAS; VBIAS = 3.5VDC + 500mVpk
-90
PSRR VIN; VIN = 1.5VDC + 300mVpk
-100
100
1000
10000
100000
Frequency (Hz)
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[v2-04] 2015-Aug-16
AS1376 − Typical Operating Characteristics
1.005
1.005
1.004
1.004
Output Voltage (V)
Output Voltage (V)
Figure 12:
Line Regulation
1.003
1.002
1.001
1.003
1.002
1.001
1
1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
1
2.5 2.75
Input Voltage (V)
3
3.25 3.5 3.75
4
4.25 4.5
Bias Supply Voltage (V)
Line Regulation: LNRVIN (EN = VBIAS = 2.5V, VOUT = 1.0V, CIN = COUT = 1uF, CBIAS = 4.7uF, IOUT = 100uA);
LNRVBIAS (EN = VBIAS, VIN = 1.2V, VOUT = 1.0V, CIN = COUT = 1uF, CBIAS = 4.7uF, IOUT = 100uA)
Figure 13:
Load Regulation
Load Regulation: EN = VBIAS = 2.5V,
VIN = 1.2V, VOUT = 1.0V,
CIN = COUT = 1uF, CBIAS = 4.7uF
1.005
Output Voltage (V)
1.004
1.003
1.002
1.001
1
0
200
400
600
800
1000
Output Current (mA)
ams Datasheet
[v2-04] 2015-Aug-16
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AS1376 − Typical Operating Characteristics
Figure 14:
Output Voltage vs. Temperature
Output Voltage vs. Temperature:
EN = VBIAS = 2.5V, VIN = 1.2V,
VOUT = 1.0V, CIN = COUT = 1uF,
CBIAS = 4.7uF, IOUT = 1mA
1.01
Output Voltage (V)
IOUT = 1mA
1.005
1
0.995
0.99
-40
-20
0
20
40
60
80
60
80
Temperature (°C)
Figure 15:
Dropout VIN vs. Temperature
Dropout VIN vs. Temperature:
EN = VBIAS = 2.5V, VIN = 1.2V,
VOUT = 1.0V, CIN = COUT = 1uF,
CBIAS = 4.7uF, IOUT = 1A
200
IOUT = 1A
Dropout VIN (mV)
175
150
125
100
75
50
-40
-20
0
20
40
Temperature (°C)
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ams Datasheet
[v2-04] 2015-Aug-16
AS1376 − Typical Operating Characteristics
Figure 16:
Enable Start-Up
Enable Start-Up: EN = VBIAS = 2.5V,
VIN = 1.2V, settling to 95% of VOUT
(950mV), CIN = COUT = 1uF,
CBIAS = 4.7uF, no load
500mV/Div
EN
500mV/Div
VOUT
50us/Div
ams Datasheet
[v2-04] 2015-Aug-16
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AS1376 − Detailed Description
Detailed Description
The AS1376 is a low-dropout, low-quiescent-current linear
regulator intended for LDO regulator applications where
output current load requirements range from no load to 1A. All
devices come with fixed output voltage from 0.5V to 3.3V.
Shutdown current for the whole regulator is typically 20nA. The
device has integrated short-circuit and over current protection.
Under-Voltage lockout prevents erratic operation when the
input voltage is slowly decaying (e.g. in a battery powered
application). Thermal Protection shuts down the device when
die temperature reaches 150°C. This is a useful protection when
the device is under sustained short circuit conditions.
As illustrated in the block diagram on page 3, the devices
comprise voltage reference, error amplifier, N-channel MOSFET
pass transistor, internal voltage divider, current limiter, thermal
sensor and shutdown logic.
The bandgap reference is connected to the inverting input of
the error amplifier. The error amplifier compares this reference
with the feedback voltage and amplifies the difference. If the
feedback voltage is lower than the reference voltage, the
N-channel MOSFET gate is pulled higher, allowing more current
to pass to the output, and increases the output voltage. If the
feedback voltage is too high, the pass-transistor gate is pulled
down, allowing less current to pass to the output.
When the adjustable output variant is selected, an external
resistor voltage divider is connected to FB pin and a sample of
the output is compared to the 500mV reference.
When a fixed output variant is chosen, FB must be connected
to the Output pin. Depending upon the variant chosen, the
internal reference is trimmed to the final output voltage.
Advantage of Dual Supply Architecture vs.
Traditional Single Supply Approach
Compared to the traditional single supply approach, employing
a P-channel series pass MOSFET, the dual rail architecture
ensures improved performances in a LDO when operating at
very low input voltages below the threshold of the internal
series power N-channel MOSFET. The extra supply voltage at
pin VBIAS (V BIAS > V IN) ensures that the N-channel MOSFET
always operates above its threshold voltage.
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[v2-04] 2015-Aug-16
AS1376 − Detailed Description
Figure 17:
Single vs. Dual Supply
Single Supply
Dual Supply
VIN
Bandgap
Core
blocks
VIN
VBIAS
Bandgap
PMOS
Error
amplifier
VO UT
Core
blocks
NMO S
Error
amplifier
VO UT
Single vs. Dual Supply: This figure shows simplified block diagrams of single supply P-channel LDO and dual rail
N-channel series pass architectures.
The P-channel LDO uses a PMOS output transistor connected
in a common source configuration. During regulation, the
PMOS
gate-source voltage moves between VIN and GND as the load
demands. The dual supply approach is based on a NMOS output
transistor in common drain configuration where the source is
connected to the regulated output. During regulation, the
NMOS gate source voltage increases from VOUT to VBIAS as the
load demands. As the drain voltage is not shared with the
remaining blocks of the circuit, its value can be chosen
independently. The NMOS source follower design allows
improved efficiency and dropout at low input voltages and
provides faster load transient response.
Dropout Voltage
Dropout is the input to output voltage difference, below which
the linear regulator ceases to regulate. At this point, the output
voltage change follows the input voltage change. Dropout
voltage may be measured at different currents and, in particular
at the regulator maximum one. From this is obtained the
MOSFET maximum series resistance over temperature.
(EQ1)
V DROPOUT = I LOAD * RSERIES
Dropout is probably the most important specification when the
regulator is used in a battery application. The dropout
performance of the regulator defines the useful “end of life” of
the battery before replacement or re-charge is required.
ams Datasheet
[v2-04] 2015-Aug-16
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AS1376 − Detailed Description
Figure 18:
Graphical Representation of Dropout Voltage
Dropout Voltage: This figure shows the
variation of VOUT as VIN is varied for a
certain load current. The practical value
of dropout is the differential voltage
(VOUT - VIN) measured at the point
where the LDO output voltage has fallen
by 100mV below the nominal, fully
regulated output value. The nominal
regulated output voltage of the LDO is
that obtained when there is 500mV (or
greater) input-output voltage
differential.
VOUT
VIN
VIN ≥ V OUT + 0.5V
Dropout
Voltage
VOUT
100mV
VIN
VOUT
VIN
Auto-Discharge
AS1376 features an auto-discharge function that discharges the
load capacitance through a 100Ω (typ) path to ground when
the device is placed in shutdown. This helps to minimizes the
possibility that VOUT> VIN during shutdown caused by
differing capacitance discharge rates at VIN and VOUT
terminals. When VOUT> VIN, reverse current flows through the
inherent body diode of the NMOS series pass transistor. This
current should be limited to 50mA or less. If this is not possible,
then an external Schottky diode should be connected between
VOUT (anode) and VIN (cathode) to bypass the discharge
current around the AS1376.
Efficiency
Low quiescent current and low input-output voltage
differential are important in battery applications amongst
others, as the regulator efficiency is directly related to
quiescent current and dropout voltage.
(EQ2)
V LOAD × I LOAD
Efficiency = ----------------------------------------------- x 100%
V IN ⋅ ( I Q + I LOAD )
IQ… Quiescent current of LDO measured at VBIAS
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AS1376 − Detailed Description
Power Dissipation
Maximum power dissipation (PD) of the LDO is the sum of the
power dissipated by the internal series MOSFET and the
quiescent current required to bias the internal voltage
reference and the internal error amplifier.
(EQ3)
PD (MAX)(Seriespass) = I LOAD(MAX) * (V IN(MAX) - V OUT(MIN))
Internal power dissipation as a result of the bias current for the
internal voltage reference and the error amplifier is calculated
as:
(EQ4)
PD (MAX)(Bias) = V IN(MAX) * I Q
Total LDO power dissipation is calculated as:
(EQ5)
PD (MAX)(TOTAL) = PD (MAX)(Seriespass) + PD (MAX)(Bias)
Junction Temperature
Under all operating conditions, the maximum junction
temperature should not exceed 125ºC (unless the data sheet
specifically allows). Limiting the maximum junction
temperature requires knowledge of the heat path from junction
to case (θ JCºC/W fixed by the IC manufacturer), and adjustment
of the case to ambient heat path (θCAºC/W) by manipulation of
the PCB copper area adjacent to the IC position.
Figure 19:
Steady State Heat Flow Equivalent Circuit
Junction
TJ
Package
TC
RθJ C
PCB
TS
RθCS
Ambient
TA
RθS A
RθJ A
Total Thermal Path Resistance
(EQ6)
Rθ JA = Rθ JC + Rθ CS + Rθ SA
Junction Temperature (TJºC) is determined by:
(EQ7)
ams Datasheet
[v2-04] 2015-Aug-16
TJ = (PD (MAX) * Rθ JA) + TAMB
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AS1376 − Detailed Description
Explanation of Steady State Specifications
Line Regulation
Line regulation is defined as the change in output voltage when
the input voltage is changed by a known quantity. It is a
measure of the regulator’s ability to maintain a constant output
voltage when the input voltage changes. Line regulation is a
measure of the DC open loop gain of the error amplifier.
(EQ8)
ΔV OUT
LNR = -----------------ΔV IN
In practice, line regulation is referred to the regulator output
voltage in terms of %/VOUT. This is particularly useful when the
same regulator is available with numerous output voltage trim
options.
(EQ9)
ΔV OUT
100
LNR = ------------------ * -------------- %
ΔV IN
V OUT
Load Regulation
Load regulation is defined as the change of the output voltage
when the load current is changed by a known quantity. It is a
measure of the regulator’s ability to maintain a constant output
voltage when the load changes. Load regulation is a measure
of the DC closed loop output resistance of the regulator.
(EQ10)
ΔV OUT
LDR = -----------------ΔI OUT
In practice, load regulation is referred to the regulator output
voltage in terms of %/mA. This is particularly useful when the
same regulator is available with numerous output voltage trim
options.
(EQ11)
ΔV OUT
100
LDR = ------------------ * -------------- %
ΔI OUT
V OUT
Output Voltage Setting
For the adjustable Output Voltage version the final output
voltage can be calculated by the ratio of R UP and RDN, the
internal reference voltage (= FB voltage) and the input offset
voltage of the error amplifier.
(EQ12)
R UP
V OUT = ( V FB ) ×  1 + ----------- – R UP × 0.45μA

R DN
Total Accuracy
Away from dropout, total steady state accuracy is the sum of
setting accuracy, load regulation and line regulation.
(EQ13)
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AccuracyTotal = Accuracy Setting + LDR + LNR
ams Datasheet
[v2-04] 2015-Aug-16
AS1376 − Detailed Description
Explanation of Dynamic Specifications
Power Supply Rejection Ratio (PSRR)
Known also as Ripple Rejection, this specification measures the
ability of the regulator to reject noise and ripple beyond DC.
PSRR is a summation of the individual rejections of the error
amplifier, reference and AC leakage through the series pass
transistor. The specification, in the form of a typical attenuation
plot with respect to frequency, shows up the gain bandwidth
compromises forced upon the designer in low quiescent
current conditions.
(EQ14)
δV OUT
PSRR = 20 log ----------------δV IN
Power supply rejection ratio is fixed by the internal design of
the regulator. Additional rejection must be provided externally.
Output Capacitor ESR
The series regulator is a negative feedback amplifier, and as
such is conditionally stable. The ESR of the output capacitor is
usually used to cancel one of the open loop poles of the error
amplifier in order to produce a single pole response. Excessive
ESR values may actually cause instability by excessive changes
to the closed loop unity gain frequency crossover point. The
range of ESR values for stability is usually shown either by a plot
of stable ESR versus load current, or a limit statement in the
datasheet.
Some ceramic capacitors exhibit large capacitance and ESR
variations with temperature and DC bias. Z5U and Y5V
capacitors may be required to ensure stability at temperatures
below TAMB= -10ºC. With X7R or X5R capacitors, a 1μF capacitor
should be sufficient at all operating temperatures.
Larger output capacitor values (10μF max) help to reduce noise
and improve load transient-response, stability and
power-supply rejection.
Input Capacitor
If the AS1376 is used stand alone, an input capacitor at VIN is
required for stability. It is recommended to connect a 1μF
capacitor between the AS1376 power supply input pin VIN and
GND (capacitance value may be increased without limit).
This capacitor must be located as close as possible to the VIN
pin and returned to a clean analog ground. A X5R or X7R type
or better may be used at the input.
A capacitor at VBIAS is not required if the distance to the supply
does not exceed 5cm.
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AS1376 − Detailed Description
Noise
The regulator output is a DC voltage with noise superimposed
on the output. The noise comes from three sources; the
reference, the error amplifier input stage, and the output
voltage setting resistors. Noise is a random fluctuation and if
not minimized in some applications, will produce system
problems.
Transient Response
The series regulator is a negative feedback system, and
therefore any change at the output will take a finite time to be
corrected by the error loop. This “propagation time” is related
to the bandwidth of the error loop. The initial response to an
output transient comes from the output capacitance, and
during this time, ESR is the dominant mechanism causing
voltage transients at the output.
(EQ15)
δV TRANSIENT = δI OUTPUT × R ESR
Thus an initial +50mA change of output current will produce a
-12mV transient when the ESR=240mΩ. Remember to keep the
ESR within stability recommendations when reducing ESR by
adding multiple parallel output capacitors.
After the initial ESR transient, there follows a voltage droop
during the time that the LDO feedback loop takes to respond
to the output change. This drift is approx. linear in time and
sums with the ESR contribution to make a total transient
variation at the output.
(EQ16)
T
δV TRANSIENT = δI OUTPUT ×  R ESR + ------------------
C LOAD
CLOAD… Output Capacitor
T … Propagation Delay of the LDO
This shows why it is convenient to increase the output capacitor
value for a better support for fast load changes. Of course the
formula holds for t < “propagation time”, so that a faster LDO
needs a smaller cap at the load to achieve a similar transient
response. For instance 50mA load current step produces 50mV
output drop if the LDO response is 1usec and the load cap is 1μF.
There is also a steady state error caused by the finite output
impedance of the regulator. This is derived from the load
regulation specification discussed above.
Exit from Shutdown Delay
This specification defines the time taken for the LDO to awake
from shutdown. The time is measured from the release of the
enable pin to the time that the output voltage is within 5% of
the final value. It assumes that the voltage at VIN is stable and
within the regulator min and max limits. Shutdown reduces the
quiescent current to very low, mostly leakage values (<1μA).
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AS1376 − Detailed Description
Thermal Protection
To prevent operation under extreme fault conditions, such as a
permanent short circuit at the output, thermal protection is
built into the device. Die temperature is measured, and when a
150ºC threshold is reached, the device enters shutdown. When
the die cools sufficiently, the device will restart (assuming input
voltage exists and the device is enabled). Hysteresis of 25ºC
prevents low frequency oscillation between start-up and
shutdown around the temperature threshold.
Power Supply Sequencing
The AS1376 requires two different supply voltages active at the
same time for correct operation.
• V IN: Input Supply Voltage
• V BIAS: Bias Supply Voltage
It's important that VIN does not exceed VBIAS at any time. If the
device is used in the typical post regulation application as
shown in Figure 20, the sequencing of the two power supplies
is not an issue as VBIAS supplies both, the DC-DC regulator and
the AS1376. The output voltage of the DC-DC regulator will take
some time to rise up and supply VIN of AS1376. In this
application VIN will always ramp up more slowly than VBIAS. In
case VIN is shorted to VBIAS, the voltages at the two supply pins
will ramp up simultaneously causing no problem. Only in
applications with two independent supplies connected to the
AS1376 special care must be taken to guarantee that VIN is
always ≤ V BIAS.
Auto Discharge
When the AS1376 is placed in shutdown, a 100Ω path to ground
is connected at the output. This path speeds up the discharge
of the capacitor(s) connected to the regulator output.
Assuming that VIN remains constant and always >VOUT, output
discharge time is calculated as follows:
(EQ17)
V ( t ) = V REG × e
t
– -------RC
t… specified time after regulator shutdown (sec)
VREG… Regulated Output Voltage (initial condition)
R … 100Ω(typ) discharge resistor
C … Output Capacitor (F)
ams Datasheet
[v2-04] 2015-Aug-16
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AS1376 − Application Information
Application Information
Figure 20:
Typical Application Diagram
VBIAS
Bias Supply
2.5V to 5.5V
VIN
CB IA S
4.7uF
LX
ON
VIN
VO UT
EN
COUT
1uF
FB
AS1376B
CIN
1uF
DC/DC
EN
1.3V
1.1V, 1A
VO UT
(AS1376 only)
GND
GND
OFF
Typical Application: This figure shows the typical application of the AS1376B for the 6-pin WL-CSP. The FB pin
and the dotted line would be valid only for the AS1376 TDFN version
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ams Datasheet
[v2-04] 2015-Aug-16
AS1376 − Package Drawings & Markings
Package Drawings & Markings
Figure 21:
MLPD-8 2x2 0.5mm Pitch Package Drawing
RoHS
Green
Note(s) and/or Footnote(s):
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Coplanarity applies to the exposed heat slug as well as the terminal.
4. Radius on terminal is optional.
5. N is the total number of terminals.
ams Datasheet
[v2-04] 2015-Aug-16
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AS1376 − Package Drawings & Mark ings
Figure 22:
WL-CSP-6 0.4mm Pitch Package Drawing
Top Through View
Bottom View (Ball Side)
RoHS
Green
Note(s) and/or Footnote(s):
1. Pin 1 = A1
2. ccc Coplanarity
3. All dimensions are in μm.
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ams Datasheet
[v2-04] 2015-Aug-16
AS1376 − Package Drawings & Markings
Figure 23:
TDFN and WL-CSP Marking
TDFN package
WL-CSP
XXX
ZZZ
XXXX
ZZ
AS1376 Marking: Shows the package marking of the TDFN and the WL-CSP product version
Figure 24:
Package Code
XXX
ZZZ
XXXX
ZZ
Tracecode for TDFN
Marking Code for TDFN
Tracecode for WL-CSP
Marking Code for WL-CSP
Package Codes: Shows the package codes of the TDFN and the WL-CSP product version
PCB Pad Layout
Figure 25:
PCB Layout Recommendation for the 6-Balls WL-CSP Option
VIN
VOUT
A1
VOUT
VBIAS
A2
OUT
VIN
COUT
1uF
0805
2.0mm x 1.2mm
B1
GND
B2
VBIAS
CIN
C2
EN
1uF
0805
2.0mm x 1.2mm
C1
GND
CBIAS
4.7uF
0805
2.0mm x 1.2mm
EN
GND
WL-CSP Layout Guidelines: This figure shows the recommended layout and placement of the external
components for the AS1376B version. Red lines are connections on TOP layer. Grey lines are GND connections on
ams Datasheet
[v2-04] 2015-Aug-16
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AS1376 − Package Drawings & Mark ings
TOP layer.
Figure 26:
PCB Layout Recommendation for the 8-Pins TDFN Package Option
VOUT
GND
COUT
1uF
0805
2.0mm x
1.2mm
CIN
1uF
0805
2.0mm x 1.2mm
1
VIN
2
8
AS1376
7
TDFN 8-pin 2x2mm
3
VBIAS
Exposed pad: GND
4
9
FB
6
5
EN
CBIAS
4.7uF
0805
2.0mm x 1.2mm
GND
TDFN Layout Guidelines: This figure shows the recommended layout and placement of the external
components for the AS1376 version for fixed trimmed output voltages. Red lines are connections on TOP layer.
Grey lines are GND connections on TOP layer.
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ams Datasheet
[v2-04] 2015-Aug-16
AS1376 − Ordering & Contact Information
Ordering & Contact Information
Figure 27:
Ordering Information
Ordering Code
Package
Marking
Output
Delivery
Form
Delivery
Quantity
AS1376-BTDT-AD (1)
8-pin 2x2mm TDFN
ABL
Adj.
T&R
1000 pcs/reel
AS1376-BTDT-12
8-pin 2x2mm TDFN
ABT
1.2V
T&R
1000 pcs/reel
AS1376B-BWLT-11
6-balls WL-CSP
D3
1.1V
T&R
12000 pcs/reel
AS1376B-BWLM-11
6-balls WL-CSP
D3
1.1V
T&R
1000 pcs/reel
Ordering Information: Specifies the available variants of AS1376
Note(s) and/or Footnote(s):
1. Available on request
Buy our products or get free samples online at:
www.ams.com/ICdirect
Technical Support is available at:
www.ams.com/Technical-Support
Provide feedback about this document at:
www.ams.com/Document-Feedback
For further information and requests, e-mail us at:
ams_sales@ams.com
For sales offices, distributors and representatives, please visit:
www.ams.com/contact
Headquarters
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
ams Datasheet
[v2-04] 2015-Aug-16
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AS1376 − RoHS Compliant & ams Green Statement
RoHS Compliant & ams Green
Statement
RoHS: The term RoHS compliant means that ams AG products
fully comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substance
categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Green
defines that in addition to RoHS compliance, our products are
free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous
material).
Important Information: The information provided in this
statement represents ams AG knowledge and belief as of the
date that it is provided. ams AG bases its knowledge and belief
on information provided by third parties, and makes no
representation or warranty as to the accuracy of such
information. Efforts are underway to better integrate
information from third parties. ams AG has taken and continues
to take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams AG
and ams AG suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.
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ams Datasheet
[v2-04] 2015-Aug-16
AS1376 − Copyrights & Disclaimer
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141
Unterpremstaetten, Austria-Europe. Trademarks Registered. All
rights reserved. The material herein may not be reproduced,
adapted, merged, translated, stored, or used without the prior
written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent
indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied,
or by description regarding the information set forth herein.
ams AG reserves the right to change specifications and prices
at any time and without notice. Therefore, prior to designing
this product into a system, it is necessary to check with ams AG
for current information. This product is intended for use in
commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or
high reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically not
recommended without additional processing by ams AG for
each application. This product is provided by ams AG “AS IS”
and any express or implied warranties, including, but not
limited to the implied warranties of merchantability and fitness
for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out
of ams AG rendering of technical or other services.
ams Datasheet
[v2-04] 2015-Aug-16
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AS1376 − Document Status
Document Status
Document Status
Product Preview
Preliminary Datasheet
Datasheet
Datasheet (discontinued)
Page 30
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Product Status
Definition
Pre-Development
Information in this datasheet is based on product ideas in
the planning phase of development. All specifications are
design goals without any warranty and are subject to
change without notice
Pre-Production
Information in this datasheet is based on products in the
design, validation or qualification phase of development.
The performance and parameters shown in this document
are preliminary without any warranty and are subject to
change without notice
Production
Information in this datasheet is based on products in
ramp-up to full production or full production which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade
Discontinued
Information in this datasheet is based on products which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and
should not be used for new designs
ams Datasheet
[v2-04] 2015-Aug-16
AS1376 − Revision Information
Revision Information
Changes from 1.02 (2010-Nov) to current revision 2-04 (2015-Aug-16)
Page
1.02 (2010-Nov) to 1.3 (2011-Oct)
Updated Absolute Maximum Ratings
3
Updated Electrical Characteristics
4
Updated Block Diagram
9
Updated Application Information
11
1.3 (2011-Oct) to 1.4 (2011-Dec)
Updated Power Dissipation
12
1.4 (2011-Dec) to 2-00 (2014-Nov)
Update to new datasheet design
New package option inserted
2-00 (2014-Nov) to 2-01 (2014-Nov)
Updated Ordering Information
27
2-01 (2014-Nov) to 2-02 (2014-Nov-03)
Added PCB Layout
24
2-02 (2014-Nov-03) to 2-03 (2015-May-11)
Updated WL-CSP package drawing
24
2-03 (2015-May-11) to 2-04 (2015-Aug-16)
Content was updated to the latest ams design
Updated Absolute Maximum Ratings
5
Note(s) and/or Footnote(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
ams Datasheet
[v2-04] 2015-Aug-16
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AS1376 − Content Guide
Content Guide
Page 32
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1
2
2
3
General Description
Key Benefits & Features
Applications
Block Diagram
4
5
7
9
Pin Assignments
Absolute Maximum Ratings
Electrical Characteristics
Typical Operating Characteristics
14
14
15
16
16
17
17
18
18
18
18
19
19
19
19
19
20
20
20
21
21
21
22
Detailed Description
Advantage of Dual Supply Architecture vs. Traditional
Single Supply Approach
Dropout Voltage
Auto-Discharge
Efficiency
Power Dissipation
Junction Temperature
Total Thermal Path Resistance
Explanation of Steady State Specifications
Line Regulation
Load Regulation
Output Voltage Setting
Total Accuracy
Explanation of Dynamic Specifications
Power Supply Rejection Ratio (PSRR)
Output Capacitor ESR
Input Capacitor
Noise
Transient Response
Exit from Shutdown Delay
Thermal Protection
Power Supply Sequencing
Auto Discharge
23
Application Information
24
26
Package Drawings & Markings
PCB Pad Layout
28
29
30
31
32
Ordering & Contact Information
RoHS Compliant & ams Green Statement
Copyrights & Disclaimer
Document Status
Revision Information
ams Datasheet
[v2-04] 2015-Aug-16