HS-1135RH Data Sheet Radiation Hardened, High Speed, Low Power Current Feedback Amplifier with Programmable Output Limiting The HS-1135RH is a radiation hardened, high speed, low power current feedback amplifier built with Intersil’s proprietary complementary bipolar UHF-1 (DI bonded wafer) process. They are QML approved and processed in full compliance with MIL-PRF-38535. This amplifier features user programmable output limiting, via the VH and VL pins. The HS-1135RH is the ideal choice for high speed, low power applications requiring output limiting (e.g., flash A/D drivers), especially those requiring fast overdrive recovery times. The limiting function allows the designer to set the maximum and minimum output levels to protect downstream stages from damage or input saturation. The subnanosecond overdrive recovery time ensures a quick return to linear operation following an overdrive condition. Component and composite video systems also benefit from this op amp’s performance, as indicated by the gain flatness, and differential gain and phase specifications. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-96767. A “hot-link” is provided on our homepage for downloading. http://www.intersil.com/spacedefense/space.htm August 1999 INTERNAL MKT. NUMBER • Electrically Screened to SMD # 5962-96767 • QML Qualified per MIL-PRF-38535 Requirements • User Programmable Output Voltage Limiting • Fast Overdrive Recovery . . . . . . . . . . . . . . . . . <1ns (Typ) • Low Supply Current . . . . . . . . . . . . . . . . . . . . 6.9mA (Typ) • Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . .360MHz (Typ) • High Slew Rate. . . . . . . . . . . . . . . . . . . . . .1200V/µs (Typ) • High Input Impedance . . . . . . . . . . . . . . . . . . . 2MΩ (Typ) • Excellent Gain Flatness (to 50MHz). . . . . . ±0.07dB (Typ) • Total Gamma Dose. . . . . . . . . . . . . . . . . . . . 300kRAD(Si) • Latch Up . . . . . . . . . . . . . . . . . . . . . None (DI Technology) Applications • Flash A/D Driver • Video Switching and Routing • Pulse and Video Amplifiers • Wideband Amplifiers • RF/IF Signal Processing • Imaging Systems Pinout HS-1135RH GDIP1-T8 (CERDIP) OR CDIP2-TI (SBDIP) TOP VIEW TEMP. RANGE (oC) 5962F9676701VPA HS7-1135RH-Q -55 to 125 NC 1 5962F9676701VPC HS7B-1135RH-Q -55 to 125 -IN 2 HS7-1135RH/PROTO HS7-1135RH/PROTO 1 -55 to 125 4099.2 Features Ordering Information ORDERING NUMBER File Number +IN 3 V- 4 + 8 VH 7 V+ 6 OUT 5 VL CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HS-1135RH Clamp Operation the clamp inputs floating. A similar description applies to the symmetrical low clamp circuitry controlled by VL. General The HS-1135RH features user programmable output clamps to limit output voltage excursions. Clamping action is obtained by applying voltages to the VH and VL terminals (pins 8 and 5) of the amplifier. VH sets the upper output limit, while VL sets the lower clamp level. If the amplifier tries to drive the output above VH, or below VL, the clamp circuitry limits the output voltage at VH or VL ( the clamp accuracy), respectively. The low input bias currents of the clamp pins allow them to be driven by simple resistive divider circuits, or active elements such as amplifiers or DACs. Clamp Circuitry Figure 1 shows a simplified schematic of the HS-1135RH input stage, and the high clamp (VH) circuitry. As with all current feedback amplifiers, there is a unity gain buffer (QX1 - QX2) between the positive and negative inputs. This buffer forces -IN to track +IN, and sets up a slewing current of (VIN - VOUT)/RF. This current is mirrored onto the high impedance node (Z) by QX3-QX4, where it is converted to a voltage and fed to the output via another unity gain buffer. If no clamping is utilized, the high impedance node may swing within the limits defined by QP4 and QN4. Note that when the output reaches it’s quiescent value, the current flowing through -IN is reduced to only that small current (-IBIAS) required to keep the output at the final voltage. V+ QP3 QP4 50K (30K FOR VL ) QN2 QP1 +IN ICLAMP R1 Z +1 VV+ When the output is clamped, the negative input continues to source a slewing current (ICLAMP) in an attempt to force the output to the quiescent voltage defined by the input. QP5 must sink this current while clamping, because the -IN current is always mirrored onto the high impedance node. The clamping current is calculated as (V-IN - VOUT)/RF. As an example, a unity gain circuit with VIN = 2V, VH = 1V, and RF = 510Ω would have ICLAMP = (2-1)/510Ω = 1.96mA. Note that ICC will increase by ICLAMP when the output is clamp limited. Clamp Accuracy The clamped output voltage will not be exactly equal to the voltage applied to VH or VL. Offset errors, mostly due to VBE mismatches, necessitate a clamp accuracy parameter which is found in the device specifications. Clamp accuracy is a function of the clamping conditions. Referring again to Figure 1, it can be seen that one component of clamp accuracy is the VBE mismatch between the QX6 transistors, and the QX5 transistors. If the transistors always ran at the same current level there would be no VBE mismatch, and no contribution to the inaccuracy. The QX6 transistors are biased at a constant current, but as described earlier, the current through QX5 is equivalent to ICLAMP. VBE increases as ICLAMP increases, causing the clamped output voltage to increase as well. ICLAMP is a function of the overdrive level (V-IN -VOUTCLAMPED) and RF, so clamp accuracy degrades as the overdrive increases, or as RF decreases. As an example, the specified accuracy of ±60mV for a 2X overdrive with RF = 510Ω degrades to ±220mV for RF = 240Ω at the same overdrive, or to ±250mV for a 3X overdrive with RF = 510Ω. Consideration must also be given to the fact that the clamp voltages have an effect on amplifier linearity. The “Nonlinearity Near Clamp Voltage” curve in the data sheet illustrates the impact of several clamp levels on linearity. VH QN1 QN6 QN5 QP2 Clamp Range 200Ω QP6 QN3 QN4 QP5 VRF (EXTERNAL) -IN VOUT FIGURE 1. HS-1135RH SIMPLIFIED VH CLAMP CIRCUITRY Tracing the path from VH to Z illustrates the effect of the clamp voltage on the high impedance node. VH decreases by 2VBE (QN6 and QP6) to set up the base voltage on QP5. QP5 begins to conduct whenever the high impedance node reaches a voltage equal to QP5’s base + 2VBE (QP5 and QN5). Thus, QP5 clamps node Z whenever Z reaches VH. R1 provides a pull-up network to ensure functionality with 2 Unlike some competitor devices, both VH and VL have usable ranges that cross 0V. While VH must be more positive than VL, both may be positive or negative, within the range restrictions indicated in the specifications. For example, the HS-1135RH could be limited to ECL output levels by setting VH = -0.8V and VL = -1.8V. VH and VL may be connected to the same voltage (GND for instance) but the result won’t be in a DC output voltage from an AC input signal. A 150 - 200mV AC signal will still be present at the output. Recovery from Overdrive The output voltage remains at the clamp level as long as the overdrive condition remains. When the input voltage drops below the overdrive level (VCLAMP /AVCL) the amplifier will return to linear operation. A time delay, known as the Overdrive Recovery Time, is required for this resumption of linear operation. The plots of “Unclamped Performance” and “Clamped Performance” highlight the HS-1135RH’s HS-1135RH subnanosecond recovery time. The difference between the unclamped and clamped propagation delays is the overdrive recovery time. The appropriate propagation delays are 4.0ns for the unclamped pulse, and 4.8ns for the clamped (2X overdrive) pulse yielding an overdrive recovery time of 800ps. The measurement uses the 90% point of the output transition to ensure that linear operation has resumed. Note: The propagation delay illustrated is dominated by the fixturing. The delta shown is accurate, but the true HS-1135RH propagation delay is 500ps. The layout and schematic of the board are shown here: VH 1 +IN VL Use of Die in Hybrid Applications This amplifier is designed with compensation to negate the package parasitics that typically lead to instabilities. As a result, the use of die in hybrid applications results in overcompensated performance due to lower parasitic capacitances. Reducing RF below the recommended values for packaged units will solve the problem. For AV = +2 the recommended starting point is 300Ω, while unity gain applications should try 400Ω. OUT V+ VGND FIGURE 2A. TOP LAYOUT PC Board Layout The frequency performance of this amplifier depends a great deal on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! FIGURE 2B. BOTTOM LAYOUT Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value chip (0.1µF) capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Output capacitance, such as that resulting from an improperly terminated transmission line will degrade the frequency response of the amplifier and may cause oscillations. In most cases, the oscillation can be avoided by placing a resistor in series with the output. Care must also be taken to minimize the capacitance to ground seen by the amplifier’s inverting input. The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. To this end, it is recommended that the ground plane be removed under traces connected to pin 2, and connections to pin 2 should be kept as short as possible. An example of a good high frequency layout is the Evaluation Board shown in Figure 2. Evaluation Board An evaluation board is available for the HS-1135RH, (HFA11XXEVAL). Please contact your local sales office for information. 3 500Ω 500Ω VH 50Ω 1 8 2 7 3 6 4 5 0.1µF 10µF +5V 50Ω IN 10µF 0.1µF OUT VL GND -5V GND FIGURE 2C. SCHEMATIC FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT HS-1135RH Burn-In Circuit HS-1135RH CERDIP R2 R1 R1 1 8 2 7 - + 3 D2 4 VD1 6 D2 V+ C1 D1 5 C1 NOTES: 1. R1 = 1kΩ, ±5% (Per Socket) 2. R2 = 10kΩ, ±5% (Per Socket) 3. C1 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum 4. D1 = 1N4002 or Equivalent (Per Board) 5. D2 = 1N4002 or Equivalent (Per Socket) 6. V+ = +5.5V ±0.5V 7. V- = -5.5V ±0.5V Irradiation Circuit HS-1135RH CERDIP R2 1 R1 2 R1 3 4 VC2 NOTES: 8. R1 = 1kΩ, ±5% 9. R2 = 10kΩ, ±5% 10. C1 = C2 = 0.01µF 11. V+ = +5.0V ±0.5V 12. V- = -5.0V ±0.5V 4 8 - + V+ 7 6 5 C1 HS-1135RH Die Characteristics DIE DIMENSIONS: Substrate: 59 mils x 58.2 mils x 19 mils ±1 mil 1500µm x 1480µm x 483µm ±25.4µm UHF-1, Bonded Wafer, DI ASSEMBLY RELATED INFORMATION: INTERFACE MATERIALS: Substrate Potential: Glassivation: Floating Type: Nitride Thickness: 4kÅ ±0.5kÅ ADDITIONAL INFORMATION: Worst Case Current Density: Top Metallization: < 2 x 105A/cm2 Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kÅ ±0.4kÅ Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kÅ ±0.8kÅ Transistor Count: 89 Metallization Mask Layout HS-1135RH -IN VH V+ OUT +IN V- VL All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 5 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029