ispMACH 4000 I n - s y s t e m P r o g r a m m a b l e – H I G H P ER F ORMAN C E a n d LO W P O W ER The Industry’s Fastest and Lowest Power CPLDs New CPLD Architecture Couples SuperFAST Performance and Low Power The ispMACH™ 4000 is the industry’s fastest and lowest power ISP™ Complex Programmable Logic Device (CPLD) Family. With a SuperFAST™ 2.5ns pin-to-pin delay and low dynamic power, the ispMACH 4000 Family is the ultimate solution for high performance systems. The ispMACH 4000 family contains three separate sub-families, supporting 3.3V (ispMACH 4000V), 2.5V (ispMACH 4000B), and 1.8V (ispMACH 4000C). Utilizing Lattice’s latest generation E2CMOS® process technology, the ispMACH 4000 architecture combines the best features of Lattice’s ispMACH4A and ispLSI® 2000 families and provides high speed, low dynamic power consumption, enhanced logic control, and flexible I/O. The new ispMACH 4000 Family is fully supported by Lattice’s easy-to-use and powerful ispLEVER® design software, plus a wide range of popular third-party tools. Designing with ispMACH 4000 devices is quick and easy using leading synthesis and simulation tools from Exemplar Logic, Synplicity and Model Technology. Key Features and Benefits ■ SuperFAST Performance • 2.5 ns tPD Pin-to-Pin Delay • 400 MHz System Performance ■ Industry’s Lowest Power Consumption • 1.8V Core for Low Dynamic Power • Low Static Current - 1.3-3 mA (1.8V Device Family) - 11.3-13 mA (2.5V and 3.3V Device Families) ■ Multiple Temperature Range Options • Commercial: 0 to 70º C TA (Ambient) • Industrial: -40 to 85º C TA (Ambient) • Automotive: -40 to 125º C TA (Ambient) ■ Ease of Design • Excellent First-Time Fit and Refit Capability • 4 Global Clocks • 36 Inputs per Logic Block • Up to 80 Product Terms (PT) per Output • ORP for Pin Locking • Density Migration • Flexible Control, Clocking and OE • Fast, SpeedLocking™, and Wide PT Paths • 5V Tolerant Inputs and I/O ■ Easy System Integration • Operation with 1.8V, 2.5V and 3.3V Supplies • 1.8V, 2.5V, 3.3V I/O Support • IEEE 1532 In-System Programmable (ISP™) • IEEE 1149.1 Boundary Scan Test • Open Drain Output for Flexible Bus Interface Capability • Programmable Pull-Up or Bus-Keeper Inputs • Hot Socketing Capability • 3.3V PCI Compatible • Programmable Output Slew Rate • Lead-free Package Options Output Routing Pool 16 36 Generic Logic Block 16 36 16 36 Generic Logic Block I/O Block Generic Logic Block I/O Bank 1 Output Routing Pool Output Routing Pool 36 Global Routing Pool I/O Bank 0 I/O Block 16 I/O Block Generic Logic Block Output Routing Pool I/O Block ispMACH 4000 Block Diagram ispMACH 4000 Architecture CLK3 CLK2 CLK1 CLK0 Generic Logic Block (GLB) Macrocell To Global Routing Pool (GRP) Power-up Reset Shared PT Initialization PT Initialization (optional) PT Initialization/CE (optional) Clock Generator Macrocell 0 16 Macrocell Feedback Signals Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 36 Inputs from Segment Routing Pool Macrocell 6 AND Array Logic Allocator 36 Inputs 83 Product Terms Macrocell 7 Macrocell 8 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 From Logic Allocator 1+OE Macrocell 14 To Output Routing Pool 1+OE (ORP) To ORP To GRP CE 1+OE Single PT 1+OE Block CLK0 Block CLK1 Block CLK2 Block CLK3 PT Clock (optional) Shared PT Clock Flexible and efficient clock and control scheme ensures easy implementation with a variety of HDL coding styles. To Product Term Output Enable Sharing Shared PT Clock Shared PT Initialization Enhanced Output Enable control selections for each I/O pin I/O Cell Flexible Product Term Allocation SuperFAST 5 Product Term Fast Path for high performance functions 5-PT Fast Path to to n-1 n-2 P 1+OE Macrocell 15 Fast Path and Speed Locked Path R D/T/L Q 1+OE 1+OE Macrocell 13 From I/O Cell Delay 1+OE Macrocell 1 From ORP GOE 0 GOE 1 GOE 2 GOE 3 VCCO VCC VCCO to ORP from n-1 From ORP * * * To Macrocell up to 20 PT To GRP to Macrocell n Cluster n Individual P-Term Allocator Cluster Allocator to n+1 from n+2 1.8V/2.5V/3.3V Mixed Voltage Support from n+1 SpeedLockedTM Path - up to 20 Product Terms GND VCCO I/O Bank 0 Wide Path to to n-1 n-2 from from n-1 n-4 tto Macrocell n GND VCC Logic Core CLK0 CLK1 Cluster n Individual P-Term Allocator I/O Bank power supply can be 1.8V, 2.5V or 3.3V. Input standard supported is independent of VCCO. Cluster Allocator to n+1 from n+2 from n+1 CLK3 CLK2 to n+4 Wide Product Term Path - up to 80 Product Terms I/O Bank 1 GND VCCO Each I/O Bank has its own VCCO and GND ispMACH 4000 Applications Network Core Router The SuperFAST performance of the ispMACH 4000 is perfect for implementing high speed data path and control applications. In this application, the ispMACH 4256 implements: • MPC765 to SDRAM Data Pathway and Controller • Finite State Machine • JTAG Control • MUX/DEMUX ispMACH 4000 Strengths • High Density of I/Os • Cost Effective • Boundary Scan Improves Testability • Design Simplicity ispGDXV SDRAM SDRAM ispMACH 4256 SDRAM SDRAM ispGDXV Flash Memory Optical Transmission Processor Module The ispMACH 4000 is an excellent solution for multi-voltage systems and high-speed bus applications. In this optical transmission application, the ispMACH 4384 performs: • Complex Data Path Control • Dedicated Interrupts • Watchdog Timer • LED/Alarm Controls • Bus Arbitration Signals and Chip Selects for ASICs Processor Memory Bridge Processor Module Interface Bus Optical ASSP ispMACH 4384 MPC8260 Optical ASSP ispMACH 4000 Strengths • Bus Speed • Hot Socketing Capability • Multi-Voltage Support • Output Enable Control for Each Pin ispGDXV Service Managment Bus OC12 Edge Router The in-system programmability, non-volatility and very high speed of ispMACH 4000 devices make them a superior choice for interface applications. In this OC12 edge router application, the ispMACH 4512 performs the following functions: • PowerPC™, ASIC and SDRAM Interface • ispGDXV™ Data Flow Control • CPU Control Registers • SDRAM Controller • Multiple Interface Options: DS3, OC-3, OC-12, Ethernet and Gigabit Ethernet ispMACH 4000 Strengths • High Speed • Package Migration • In-System Programmable for Different Interface Options PowerPC ispMACH 4512 ASIC ispMACH 4256 ispGDXV SDRAM PowerPC ispMACH 4000V/B/C Family Attributes V = 3.3V, B = 2.5V, C = 1.8V core supply User I/O + Inputs tPD (ns) tCO (ns) tS (ns) fMAX (MHz) VCC (Volts) Standby Current at 1.8V (mA) 32 30+2 32+4 2.5 2.2 1.8 400 3.3/2.5/1.8 1.3 44-pin TQFP 48-pin TQFP ispMACH 4064V/B/C 64 30+2 32+4 64+10 2.5 2.2 1.8 400 3.3/2.5/1.8 1.5 44-pin TQFP 48-pin TQFP 100-pin TQFP ispMACH 4128V/B/C 128 64+10 92+4 96+4 2.7 2.7 1.8 333 3.3/2.5/1.8 1.5 100-pin TQFP 128-pin TQFP 144-pin TQFP** ispMACH 4256V/B/C 256 64+10 96+4 128+4 128+4/160+4 3.0 2.7 2.0 322 3.3/2.5/1.8 2.0 100-pin TQFP 144-pin TQFP** 176-pin TQFP 256-ball ftBGA* ispMACH 4384V/B/C 384 128+4 192+4 3.5 2.7 2.0 322 3.3/2.5/1.8 2.5 176-pin TQFP 256-ball ftBGA ispMACH 4512V/B/C 512 128+4 208+4 3.5 2.7 2.0 322 3.3/2.5/1.8 3.0 176-pin TQFP 256-ball ftBGA Family Member Macrocells ispMACH 4032V/B/C **3.3V only ispMACH 4000 Advanced Packaging Industry’s Lowest Power Consumption 180mA l na itiotition d Tra mpe Co 66% Less Power 120mA "L Co owmp Po eti we tio r" n *128 and 160 I/O options Package 42% Less Power ICC ispMACH 4256 60mA 0mA 0MHz 100MHz 200MHz 300MHz Frequency Superior Performance 400MHz ispMACH 4000 300MHz Speed 70% Faster Competition 200MHz 100MHz 32 64 128 256 384 512 Number of Macrocells Packages are shown actual size. Dimensions refer to package body size. Applications Support 1-800-LATTICE (528-8423) (503) 268-8001 [email protected] www.latticesemi.com Copyright © 2008 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), E2CMOS, ISP, ispMACH, ispLSI, ispLEVER, ispGDXV, SpeedLocked, SpeedLocking, and SuperFAST are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. April 2008 Order #: I0128C