HS-565ARH-T Data Sheet July 1999 Radiation Hardened High Speed, Monolithic Digital-to-Analog Converter FlowTM Intersil’s Satellite Applications (SAF) devices are fully tested and guaranteed to 100kRAD total dose. This QML Class T device is processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. File Number 4607.1 Features • qml Class T, Per MIL-PRF-38535 • Radiation Performance - Gamma Dose (γ) 1 x 105 RAD(Si) - No Latch-Up, Dielectrically Isolated Device Islands • DAC and Reference on a Single Chip • Pin Compatible with AD-565A and HI-565A The HS-565ARH-T is a fast, radiation hardened 12-bit current output, digital-to-analog converter. The monolithic chip includes a precision voltage reference, thin-film R-2R ladder, reference control amplifier and twelve high-speed bipolar current switches. • Very High Speed: Settles to 0.50 LSB in 500ns Max The Intersil Semiconductor Dielectric Isolation process provides latch-up free operation while minimizing stray capacitance and leakage currents, to produce an excellent combination of speed and accuracy. Also, ground currents are minimized to produce a low and constant current through the ground terminal, which reduces error due to codedependent ground currents. • ±0.75 LSB Accuracy Guaranteed Over Temperature (±0.125 LSB Typical at 25oC) • Monotonicity Guaranteed Over Temperature • 0.50 LSB Max Nonlinearity Guaranteed Over Temperature • Low Gain Drift (Max., DAC Plus Reference) 50ppm/oC Pinouts HS1-565ARH-T (SBDIP), CDIP2-T24 TOP VIEW HS-565ARH-T die are laser trimmed for a maximum integral nonlinearity error of ±0.25 LSB at 25oC. In addition, the low noise buried zener reference is trimmed both for absolute value and minimum temperature coefficient. NC 1 24 BIT 1 IN (MSB) NC 2 23 BIT 2 IN VCC 3 22 BIT 3 IN REF OUT 4 21 BIT 4 IN REF GND 5 20 BIT 5 IN REF IN 6 19 BIT 6 IN -VEE 7 18 BIT 7 IN BIPOLAR RIN 8 17 BIT 8 IN IDAC OUT 9 16 BIT 9 IN 10V SPAN 10 15 BIT 10 IN 20V SPAN 11 14 BIT 11 IN PWR GND 12 13 BIT 12 IN (LSB) Specifications Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering. Detailed Electrical Specifications for the HS-565ARH-T are contained in SMD 5962-96755. A “hot-link” is provided from our website for downloading. www.intersil.com/spacedefense/newsafclasst.asp Intersil‘s Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website. www.intersil.com/quality/manuals.asp Ordering Information ORDERING NUMBER PART NUMBER TEMP. RANGE (oC) 5962R9675501TJC HS1-565ARH-T -55 to 125 5962R9675501TXC HS9-565ARH-T -55 to 125 NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct. 1 HS9-565ARH-T (FLATPACK), CDFP4-F24 TOP VIEW NC NC VCC REF OUT 1 REF GND REF IN -VEE BIPOLAR RIN IDAC OUT 10V SPAN 20V SPAN PWR GND 5 2 3 4 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 BIT 1 IN (MSB) BIT 2 IN BIT 3 IN BIT 4 IN BIT 5 IN BIT 6 IN BIT 7 IN BIT 8 IN BIT 9 IN BIT 10 IN BIT 11 IN BIT 12 IN (LSB) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation. HS-565ARH-T Functional Diagram BIP. OFF. 8 REF OUT VCC 4 3 + 5K 10V REF IN DAC 0.5mA 6 19.95K 5K 9 OUT IO + 3.5K 10 10V SPAN 9.95K IREF REF 5 GND (4X IREF X CODE) - 2.5K 3K 7 -VEE Definitions of Specifications Digital Inputs The HS-565ARH-T accepts digital input codes in binary format and may be user connected for any one of three binary codes. Straight binary, Two’s Complement (see note below), or Offset Binary, (see Operating Instructions). DIGITAL INPUT 11 20V SPAN ANALOG OUTPUT 12 PWR GND 24. . . 13 MSB LSB full scale range per oC (ppm of FSR/oC). Gain error is measured with respect to 25oC at high (tH) and low (t L) temperatures. Gain drift is calculated for both high (t L 25oC) and low ranges (25oC - t L) by dividing the gain error by the respective change in temperature. The specification is the larger of the two representing worst case drift. Offset Drift - The change in analog output with all bits OFF over the specified temperature range expressed in parts per million of full scale range per oC (ppm of FSR/oC). Offset error is measured with respect to 25oC at high (t H) and low (t L) temperatures. Offset drift is calculated for both high (t D 25oC) and low (25oC - t L) ranges by dividing the offset error by the respective change in temperature. The specification given is the larger of the two, representing worst case drift. MSB . LSB STRAIGHT BINARY OFFSET BINARY (NOTE) TWO’S COMPLEMENT 000 . . . 000 Zero - f S (Full Scale) Zero 100 . . . 000 0.50 f S Zero - fS 111 . . . 111 + f S - 1 LSB + f S - 1 LSB Zero - 1 LSB Power Supply Sensitivity 011 . . . 111 0.50 f S - 1 LSB Zero - 1 LSB + f S - 1 LSB Power Supply Sensitivity is a measure of the change in gain and offset of the D/A converter resulting from a change in -15V or +15V supplies. It is specified under DC conditions and expressed as parts per million of full scale range per percent of change in power supply (ppm of FSR/%). NOTE: Invert MSB with external inverter to obtain Two’s Complement Coding. Accuracy Nonlinearity - Nonlinearity of a D/A converter is an important measure of its accuracy. It describes the deviation from an ideal straight line transfer curve drawn between zero (all bits OFF) and full scale (all bits ON). Differential Nonlinearity - For a D/A converter, it is the difference between the actual output voltage change and the ideal (1 LSB) voltage change for a one bit change in code. A Differential Nonlinearity of ±1 LSB or less guarantees monotonicity; i.e., the output always increases and never decreases for an increasing input. Settling Time Settling time is the time required for the output to settle to within the specified error band for any input code transition. It is usually specified for a full scale or major carry transition, settling to within 0.50 LSB of final value. Drift Gain Drift - The change in full scale analog output over the specified temperature range expressed in parts per million of 2 Compliance Compliance Voltage is the maximum output voltage range that can be tolerated and still maintain its specified accuracy. Compliance Limit implies functional operation only and makes no claims to accuracy. Glitch A glitch on the output of a D/A converter is a transient spike resulting from unequal internal ON-OFF switching times. Worst case glitches usually occur at half scale or the major carry code transition from 011 . . . 1 to 100 . . . 0 or vice versa. For example, if turn ON is greater than turn OFF for 011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0 exists, such that, the output momentarily glitches toward zero output. Matched switching times and fast switching will reduce glitches considerably. HS-565ARH-T Applying the HS-565ARH-T No Trim Operation The HS-565ARH-T will perform as specified without calibration adjustments. To operate without calibration, substitute 50Ω resistors for the 100Ω trimming potentiometers: In Figure 1 replace R2 with 50Ω; also remove the network on pin 8 and connect 50Ω to ground. For bipolar operation in Figure 2, replace R3 and R4 with 50Ω resistors. OP AMP Selection The HS-565ARH-T’s current output may be converted to voltage using the standard connections shown in Figures 1 and 2. The choice of operational amplifier should be reviewed for each application, since a significant trade-off may be made between speed and accuracy. Remember settling time for the DAC-amplifier combination is: With these changes, performance is guaranteed as shown under Specifications, “External Adjustments”. Typical unipolar zero will be ±0.50 LSB plus the op amp offset. ( tD ) 2 + ( tA ) 2 where tD, tA are settling times for the DAC and amplifier. The feedback capacitor C must be selected to minimize settling time. +15V R1 50kΩ -15V 100kΩ R2 100Ω 100Ω REF OUT VCC 4 3 BIP. OFF. 8 11 20V SPAN HS-565ARH-T + 6 REF IN REF GND 5K 10V - IREF 19.95 K 0.5mA DAC 5K 10 10V SPAN VO DAC OUT 9 (4 x IREF x CODE) - C - IO + 3.5K 5 9.95K + R (SEE TABLE 7) 2.5K 3K CODE INPUT 7 -VEE 24 . . . . .13 MSB LSB PWR GND FIGURE 1. UNIPOLAR VOLTAGE OUTPUT R4 100Ω REF OUT R3 100Ω VCC 4 3 BIP. OFF. 8 11 20V SPAN HS-565ARH-T + 5K 10V - IREF 0.5mA 6 REF IN 5 REF GND 9.95K DAC 19.95K 3.5K 5K (4 x IREF x CODE) - 9 2.5K 3K CODE INPUT PWR GND 24 . . . . .13 MSB LSB FIGURE 2. BIPOLAR VOLTAGE OUTPUT 3 DAC OUT IO + 7 -VEE 10 10V SPAN VO - C + R (SEE TABLE 7) HS-565ARH-T Calibration Calibration provides the maximum accuracy from a converter by adjusting its gain and offset errors to zero, For the HS-565ARH-T, these adjustments are similar whether the current output is used, or whether an external op amp is added to convert this current to a voltage. Refer to Table 7 for the voltage output case, along with Figure 1 or 2. Calibration is a two step process for each of the five output ranges shown in Table 1. First adjust the negative full scale (zero for unipolar ranges). This is an offset adjust which translates the output characteristic, i.e., affects each code by the same amount. Next adjust positive fS. This is a gain error adjustment, which rotates the output characteristic about the negative f S value. For the bipolar ranges, this approach leaves an error at the zero code, whose maximum values is the same as for integral nonlinearity error. In general, only two values of output may be calibrated exactly; all others must tolerate some error. Choosing the extreme end points (plus and minus full scale) minimizes this distributed error for all other codes. Settling Time This is a challenging measurement, in which the result depends on the method chosen, the precision and quality of test equipment and the operating configuration of the DAC (test conditions). As a result, the different techniques in use by converter manufacturers can lead to consistently different results. An engineer should understand the advantage and limitations of a given test method before using the specified settling time as a basis for design. The approach used for several years at Intersil calls for a strobed comparator to sense final perturbations of the DAC output waveform. This gives the LSB a reasonable magnitude (814mV for the HS-565ARH-T, which provides the comparator with enough overdrive to establish an accurate ±0.50 LSB window about the final settled value. Also, the required test conditions simulate the DACs environment for a common application - use in a successive approximation A/D converter. Considerable experience has shown this to be a reliable and repeatable way to measure settling time. The usual specification is based on a 10V step, produced by simultaneously switching all bits from off-to-on (tON) or onto-off (tOFF). The slower of the two cases is specified, as measured from 50% of the digital input transition to the final entry within a window of ±0.50 LSB about the settled value. Four measurements characterize a given type of DAC: (a) t ON, to final value +0.50 LSB (b) t ON, to final value -0.50 LSB (c) t OFF, to final value +0.50 LSB (d) OFF, to final value -0.50 LSB (Cases (b) and (c) may be eliminated unless the overshoot exceeds 0.50 LSB). For example, refer to Figures 3A and 3B for the measurement of case (d). Procedure As shown in Figure 3B, settling time equals t X plus the comparator delay (t D = 15ns). To measure t X: • Adjust the delay on generator number 2 for a t X of several microseconds. This assures that the DAC output has settled to its final wave • Switch on the LSB (+5V) • Adjust the VLSB supply for 50% triggering at COMPARATOR OUT. This is indicated by traces of equal brightness on the oscilloscope display as shown in Figure 3B. Note DVM reading • Switch to LSB to Pulse (P) • Readjust the VLSB supply for 50% triggering as before, and note DVM reading. One LSB equals one tenth the difference in the DVM readings noted above • Adjust the VLSB supply to reduce the DVM reading by 5 LSBs (DVM reads 10X, so this sets the comparator to sense the final settled value minus 0.50 LSB). Comparator output disappears • Reduce generator number 2 delay until comparator output reappears, and adjust for “equal brightness” • Measure t X from scope as shown in Figure 3B. Settling time equals t X + tD, i.e., t X + 15ns TABLE 1. OPERATING MODES AND CALIBRATION CIRCUIT CONNECTIONS MODE Unipolar (See Figure 1) CALIBRATION OUTPUT RANGE PIN 10 TO PIN 11 TO RESISTOR (R) APPLY INPUT CODE ADJUST TO SET VO 0 to +10V VO Pin 10 1.43K All 0’s All 1’s R1 R2 0V +9.99756V 0 to +5V VO Pin 9 1.1K All 0’s All 1’s R1 R2 0V +4.99878V 4 HS-565ARH-T TABLE 1. OPERATING MODES AND CALIBRATION (Continued) CIRCUIT CONNECTIONS MODE PIN 10 TO PIN 11 TO RESISTOR (R) APPLY INPUT CODE ADJUST TO SET VO ±10V NC VO 1.69K All 0’s All 1’s R3 R4 -10V +9.99512V ±5V VO Pin 10 1.43K All 0’s All 1’s R3 R4 -5V +4.99756V ±2.5V VO Pin 9 1.1K All 0’s All 1’s R3 R4 -2.5V +2.49878V Bipolar (See Figure 2) OUT A CALIBRATION OUTPUT RANGE SYNC PULSE PULSE OUT IN GENERATOR TRIG GENERATOR OUT NO. 2 NO. 2 C 20V ± 20% BIAS HS-565ARH-T 24 8 23 . . . . 9.95K . . . . . . ~100 . kHz . . 14 11 TURN ON TURN OFF 5K 10 +3V -0.50LSB STROBE IN B 9 + - COMPARATOR OUT B -400mV (TURN OFF) 2.5K 5 2V 12 90 DVM 10 DAC OUTPUT 0V D 5V LSB DIGITAL INPUT 0V 5K P 13 2mA 50% A NC 200K 0.1µF C VLSB SUPPLY SETTLING TIME tD = COMPARATOR DELAY tX COMP. STROBE 50% 0.8V “EQUAL BRIGHTNESS” 4V COMP. OUT D 0V FIGURE 3A. Other Considerations Grounds The HS-565ARH-T has two ground terminals, pin 5 (REF GND) and pin 12 (PWR GND). These should not be tied together near the package unless that point is also the system signal ground to which all returns are connected. (If such a point exists, then separate paths are required to pins 5 and 12). The current through pin 5 is near zero DC (Note); but pin 12 carries up to 1.75mA of code - dependent current from bits 1, 2, and 3. The general rule is to connect pin 5 directly to the system “quiet” point, usually called signal or analog ground. Connect pin 12 to the local digital or power ground. Then, of course, a single path must connect the analog/signal and digital/power grounds. NOTE: Current cancellation is a two step process within the HS565ARH-T in which code dependent variations are eliminated, the resulting DC current is supplied internally. First an auxiliary 9-bit R-2R ladder is driven by the complement of the DACs input code. Together, 5 FIGURE 3B. the main and auxiliary ladders draw a continuous 2.25mA from the internal ground node, regardless of input code. Part of the DC current is supplied by the zener voltage reference, and the remainder is sourced from the positive supply via a current mirror which is laser trimmed for zero current through the external terminal (pin 5). Layout Connections to pin 9 (IOUT) on the HS-565ARH-T are most critical for high speed performance. Output capacitance of the DAC is only 20pF, so a small change of additional capacitance may alter the op amp’s stability and affect settling time. Connections to pin 9 should be short and few. Component leads should be short on the side connecting to pin 9 (as for feedback capacitor C). See the Settling Time Section. Bypass Capacitors Power supply bypass capacitors on the op amp will serve the HS-565ARH-T also. If no op amp is used, a 0.01mF ceramic capacitor from each supply terminal to pin 12 is sufficient, since supply current variations are small. HS-565ARH-T Die Characteristics DIE DIMENSIONS: PASSIVATION: (2718µm x 4547µm x 483µm ±25.4µm) Type: Silox (SiO2) 107 x 179 x 19mils ±1mil Thickness: 8kÅ ±1kÅ METALLIZATION: WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 Type: Al Si Cu Thickness: 16.0kÅ ±2kÅ TRANSISTOR COUNT: SUBSTRATE POTENTIAL: 200 Tie substrate to reference ground PROCESS: BACKSIDE FINISH: Bipolar, Dielectric Isolation Silicon Metallization Mask Layout HS-565ARH-T VCC 3 (MSB) BIT 1 BIT 2 VREF OUT BIT 3 VREF GND BIT 4 BIT 5 VREF IN -VEE BIT 6 BIPOLAR RIN BIT 7 IDAC OUT BIT 8 BIT 9 10V SPAN BIT 10 20V SPAN POWER GND BIT 12 (LSB) BIT 11 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 6