INTERSIL ISL55033IRTZ

ISL55033
®
Data Sheet
September 11, 2008
FN6346.0
400MHz Slew Rate Enhanced Rail-to-Rail
Output Gain Block
Features
The ISL55033 is a triple rail-to-rail output gain block with a
-3dB bandwidth of 400MHz and slew rate of 2350V/µs into a
150Ω load. The ISL55033 has a fixed gain of +2. The inputs
are capable of sensing ground. The outputs are capable of
swinging to 0.45V to either rail through a 150Ω resistor
connected to V+/2.
• 2350V/µsTyp Slew Rate, RL = 150Ω to V+/2
The ISL55033 is designed for general purpose video
applications. The part includes a fast-acting global
disable/power-down circuit.
• Pb-Free (RoHS compliant)
• 400MHz -3dB Bandwidth
• Single-Supply Operation From +3V to +5.5V
• Rail-to-Rail Output
• Input Ground Sensing
• Fast 25ns Disable Time
Applications
The ISL55033 is available in a 12 Ld TQFN package.
Operation is specified over the -40°C to +85°C temperature
range.
• Video Amplifiers
• Set-Top Boxes
• Video Distribution
Ordering Information
5033
-40 to +85 12 LdTQFN L12.3x3A
ISL55033IRTZ-T13*
5033
-40 to +85 12 LdTQFN L12.3x3A
V+_OUTPUT
ISL55033IRTZ
12
11
10
1
IN+_2
2
IN+_3
3
-+
IN+_1
9
OUTPUT_1
8
OUTPUT_2
7
OUTPUT_3
4
5
6
GND_OUTPUT
-+
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020
-+
Coming Soon
GND_PWR
ISL55033EVAL1Z
ISL55033
(12 LD TQFN)
TOP VIEW
PKG.
DWG. #
EN
PACKAGE
(Pb-Free)
V+
PART
MARKING
Pinout
GND_IN-(1,2,3)
PART
NUMBER
TEMP
RANGE
(C°)
AV EACH CHANNEL
EQUALS +2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL55033
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage from V+ to GND . . . . . . . . . . . . . . . . . . . . . . . 5.75V
Supply Turn-On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/µs
EN Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4mA
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . V+ + 0.3V to GND - 0.3V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
ESD Rating:
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2,500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Charge Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1,500V
Thermal Resistance (Note 1)
θJA (°C/W)
12 Ld TQFN Package . . . . . . . . . . . . . . . . . . . . . . .
+57
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
V+ = 5V, TA = +25°C, RL = 1kΩ to V+/2, VIN = 0.1VDC, Unless Otherwise Specified.
DESCRIPTION
CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
-9
-1
9
mV
INPUT CHARACTERISTICS
VOS
Output Offset Voltage
(Note 2)
TCVOS
Offset Voltage Temperature Coefficient
Measured from -40°C to +85°C
IB
Input Bias Current
VIN = 0V
RIN
CIN
-3
µV/°C
-6
µA
Input Resistance
7
MΩ
Input Capacitance
0.5
pF
-8.5
OUTPUT CHARACTERISTICS
ACL
Closed Loop Gain
VOUT = 0.5V to 4V, RL = 150Ω
ROUT
Output Resistance
AV = +2
VOH
Positive Output Voltage Swing
RL = 1kΩ to 2.5V
RL = 150Ω to 2.5V
VOL
Negative Output Voltage Swing
1.97
1.99
2.014
V/V
30
mΩ
4.7
4.75
V
4.5
4.55
V
RL = 1kΩ to 2.5V
27
50
mV
RL = 150Ω to 2.5V
130
200
mV
ISC (source)
Output Short Circuit Current
RL = 10Ω to GND, VIN = 1.5V
50
mA
ISC (sink)
Output Short Circuit Current
RL = 10Ω to + 2.5V, VIN = 0V
50
mA
65
83
18.5
21.3
24.5
mA
275
486
900
µA
POWER SUPPLY
PSRR
Power Supply Rejection Ratio
V+ = 3V to 5.5V, RL = Open
IS-ON
Supply Current - Enabled
VIN = 0.1V, RL = Open
IS-OFF
Supply Current - All Amplifiers Disabled RL = Open
dB
ENABLE
tEN
Enable Time
RL = 150Ω, VIN = 0.5V
250
ns
tDS
Disable Time
RL = 150Ω, VIN = 0.5V
25
ns
VIH-ENB
ENABLE Pin Voltage for Power-Up
0.8
V
VIL-ENB
ENABLE Pin Voltage for Shut-Down
2
V
2
FN6346.0
September 11, 2008
ISL55033
Electrical Specifications
PARAMETER
V+ = 5V, TA = +25°C, RL = 1kΩ to V+/2, VIN = 0.1VDC, Unless Otherwise Specified. (Continued)
DESCRIPTION
CONDITIONS
MIN
(Note 3)
TYP
MAX
(Note 3)
UNIT
IIH-ENB
ENABLE Pin Input Current High
VEN = 5V
1
7
15
µA
IIL-ENB
ENABLE Pin Input for Current Low
VEN = 0V
-10
2
10
µA
AC PERFORMANCE
BW
-3dB Bandwidth
VOUT = 100mVP-P, RL = 150Ω, CL = 2pF,
VIN = 1.0 VDC
400
MHz
BW
±0.1dB Bandwidth
VOUT = 100mVP-P, RL = 150Ω, CL = 2pF
60
MHz
Peak
Peaking
VOUT = 100mVP-P, RL = 150Ω, CL =
3.2pF
1.5
dB
dG
Differential Gain
0.012
%
dP
Differential Phase
VIN = 0.1V to 2.0V, VOUT = 100mVP-P,
f = 3.58MHz, RL = 150Ω
0.11
°
eN-OUT
Output Voltage Noise Density
f = 10kHz
35
nV/√Hz
iN
Input Current Noise Density
f = 10kHz
2.9
pA/√Hz
ISO
Off-State Isolation
fO = 10MHz
VIN = 0.8VDC + 1VP-P, CL = 2pF,
RL = 150Ω
-80
dB
X-TALK
Channel-to-Channel Crosstalk,
fO = 10MHz
VIN = 0.8VDC + 1VP-P, CL = 2pF,
RL = 150Ω
-65
dB
PSRR
Power Supply Rejection Ratio
fO = 10MHz
VIN = 0.2VDC, VSOURCE = 1VP-P,
CL = 2pF, RL = 150Ω
-55
dB
2350
V/µs
0.8
ns
0.7
ns
0.6
ns
0.6
ns
0.55
ns
0.55
ns
TRANSIENT RESPONSE
SR
Slew Rate 25% to 75%
RL = 150Ω, VOUT = 0.5V to 3.5V
tr, tf Large
Signal
Rise Time, tr 20% to 80%
VOUT = 3VP-P, RL = 150Ω, CL = 2pF
Fall Time, tf 80% to 20%
Rise Time, tr 20% to 80%
VOUT = 2VP-P, RL = 150Ω, CL = 2pF
Fall Time, tf 80% to 20%
tr, tf, Small
Signal
Rise Time, tr 20% to 80%
VOUT = 100mVP-P, RL = 150Ω, CL = 2pF
Fall Time, tf 80% to 20%
OS
Overshoot
100mV step
13
%
tPD
Propagation Delay
100mV step; RL = 150Ω
1
ns
tS
0.1% Settling Time
2V step
65
ns
NOTES:
2. VOS is extrapolated from 2 output voltage measurements, with VIN = 62.5mV and VIN = 125mV, RL = 1k.
3. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
3
FN6346.0
September 11, 2008
ISL55033
Typical Performance Curves
3
2
CL = 9.2pF
6
RL = 499
1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
8
RL = 1k
0
-1
-2
-3
-4
-5
RL = 150
V+ = 5V
AV = +2
CL = 2pF
VOUT = 100mVP-P
VIN(DC) = 0.1V
-6
100k
RL = 100
CL = 7.8pF
4
100M
10M
CL = 4.3pF
0
-2
-4
-6
1M
CL = 5.7pF
2
-8
100k
1G
1M
FREQUENCY (Hz)
1G
2
-2
VOUT = 0.1VP-P
-3
VOUT = 0.5VP-P
-4
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
0
VOUT = 1.0VP-P
-5
VOUT = 1.5VP-P
V+ = 5V
AV = +2
RL = 150Ω
CL = 2pF
VIN(DC) = 0.1V
-9
100k
1M
100M
10M
FREQUENCY (Hz)
1G
0
-2
-4
VIN DC = 2.3V
VIN DC = 2.2V
VIN DC = 2.0V
VIN DC = 1.0V
VIN DC = 0.1V
-6 V+ = 5V
AV = +2
R = 150Ω to GND
-8 L
CL = 2pF
VOUTP-P = 100mV
-10
1M
100M
100k
10M
FREQUENCY (Hz)
1G
FIGURE 4. GAIN vs FREQUENCY vs DC INPUT VOLTAGE
FIGURE 3. -3dB BANDWIDTH vs VOUT
7
0.2
0.1
NORMALIZED GAIN (dB)
6
ALL CHANNELS
5
GAIN (dB)
100M
4
-1
-8
10M
FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS CLOAD
1
-7
CL = 2.0pF
FREQUENCY (Hz)
FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS RLOAD
-6
CL = 3.2pF
V+ = 5V
AV = +2
RL = 150Ω
VOUT = 100mVP-P
VIN(DC) = 0.1V
4
3
V+ = 5V
2 AV = +2
RL = 150Ω
CL = 2pF
1 V
OUT = 100mVP-P
VIN(DC) = 0.1V
0
1M
10k
100k
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
10M
100M
1G
FREQUENCY (Hz)
FIGURE 5. GAIN vs FREQUENCY - ALL CHANNELS
4
-0.8
10k
V+ = 5V
AV = +2
RL = 150Ω
CL = 2pF
VOUT = 100mVP-P
VIN(DC) = 0.1V
100k
1M
100M
10M
FREQUENCY (Hz)
FIGURE 6. 0.1 dB GAIN FLATNESS
FN6346.0
September 11, 2008
ISL55033
Typical Performance Curves (Continued)
0
0
V+ = 5V
AV = +2
RL = 150Ω
CL = 2pF
VSOURCE = 1VP-P
-20
ALL INPUTS = +0.2V DC
-40
-50
-60
-70
-40
ALL INPUTS = +0.8VDC
-60
-80
-100
-120
-80
-90
10k
100k
10M
1M
-140
10k
100M
1M
100k
1G
10000
0
-20
-30
OUTPUT VOLTAGE NOISE (nV/√Hz)
V+ = 5V
+4
AV = +2
RL = 150Ω
3pF
CL = 2pF
CHANNEL) ==2V
4VP-P
VOUT (DRIVEN CHANNEL)
P-
-10
CROSSTALK (dB)
100M
FIGURE 8. OFF-ISOLATION vs FREQUENCY
FIGURE 7. PSRR vs FREQUENCY
P
ALL INPUTS = +0.8V DC
-40
-50
-60
-70
-80
10k
1M
100k
10M
100M
1000
100
10
1
1G
10
100
FREQUENCY (Hz)
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 10. OUTPUT VOLTAGE NOISE DENSITY vs
FREQUENCY
FIGURE 9. CHANNEL-TO-CHANNEL CROSSTALK vs
FREQUENCY
5.5
1000
1.8
5.0
DISABLE
4.5
1.5
4.0
100
ENABLE (V)
INPUT CURRENT NOISE (pA/√Hz)
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
10
VOUT
3.5
1.2
3.0
0.9
2.5
V+ = 5V
AV = +2
RL = 150Ω
CL = 2pF
VIN = 0.5V
2.0
1.5
1.0
0.5
0.6
ENABLE
OUTPUT (V)
PSRR (dB)
-30
V+ = 5V
AV = +2
RL = 150Ω
CL = 2pF
VIN = 0.8VDC+1VP-P
-20
OFF- ISOLATION (dB)
-10
0.3
0
1
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 11. INPUT CURRENT NOISE DENSITY vs
FREQUENCY
5
10M
-0.5
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
2.0
TIME (µs)
FIGURE 12. ENABLE/DISABLE TIMING
FN6346.0
September 11, 2008
ISL55033
Typical Performance Curves (Continued)
0.62
3.0
2.5
0.58
SMALL SIGNAL (V)
SMALL SIGNAL (V)
0.60
V+ = 5V
AV = +2
RL = 150Ω
CL = 2.0pF
VOUT = 100mVP-P
0.56
0.54
0.52
2.0
1.0
0.5
0.50
0.48
V+ = 5V
AV = +2
RL = 150Ω
CL = 2.0pF
VOUT = 2VP-P
1.5
0
5
10
15
20
25
30
35
40
45
0
50
0
5
10
15
TIME (ns)
35
40
45
50
0.014
0.012
NORMALIZED GAIN (dB)
3.5
LARGE SIGNAL (V)
30
FIGURE 14. LARGE SIGNAL (2VP-P) STEP RESPONSE
4.0
3.0
V+ = 5V
AV = +2
RL = 150Ω
CL = 2.0pF
VOUT = 3VP-P
2.5
2.0
1.5
1.0
V+ = 5V
AV = +2
RL = 150Ω
CL = 2pF
F = 3.58MHz
VOUT = 100mVP-P
0.010
0.008
0.006
0.004
0.002
0
-0.002
-0.004
-0.006
0.5
-0.008
-0.01
0
5
10
15
20
25
30
35
40
45
50
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
TIME (ns)
INPUT DC OFFSET (V)
FIGURE 15. LARGE SIGNAL (3VP-P) STEP RESPONSE
FIGURE 16. DIFFERENTIAL GAIN
1000
0.1
0
V+ = 5V
AV = +2
RL = 150Ω
CL = 2pF
F = 3.58MHz
VOUT = 100mVP-P
-0.05
-0.10
-0.15
-0.20
ZOUT ENABLED (Ω)
0.05
NORMALIZED PHASE (°)
25
TIME (ns)
FIGURE 13. SMALL SIGNAL STEP RESPONSE
0
20
100
V+ = 5V
AV = +2
CL = 2.0pF
VIN = 1.25V DC
VSOURCE = 1VP-P
10
1
-0.25
-0.3
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
INPUT DC OFFSET (V)
FIGURE 17. DIFFERENTIAL PHASE
6
0.1
100k
1M
10M
100M
FREQUENCY (Hz)
1G
FIGURE 18. ZOUT (ENABLED) vs FREQUENCY
FN6346.0
September 11, 2008
ISL55033
Typical Performance Curves (Continued)
10000
1M
1000
100
ZIN (Ω)
ZOUT DISABLED (Ω)
100k
V+ = 5V
AV = +2
CL = 2.0pF
VIN = 1.25V DC
VSOURCE = 1VP-P
10
100k
1M
10k
1k
100
10M
100M
FREQUENCY (Hz)
V+ = 5V
AV = +2
RL = 150Ω
CL = 3.0pF
VIN = 1.25V DC
VSOURCE = 1VP-P
10
100k
1G
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 19. ZOUT (DISABLED) vs FREQUENCY
FIGURE 20. ZIN vs FREQUENCY
24
SUPPLY CURRENT (mA)
20
16
12
8
4
RL = Open
0
1.8 2.2 2.6
3.0 3.4 3.8 4.2 4.6
5
5.4 5.8
SUPPLY VOLTAGE (V)
FIGURE 21. SUPPLY CURRENT vs SUPPLY VOLTAGE
720
MAX
MAX
7.20
670
SAMPLE SIZE = 100
VS = 5V
RL = 1kΩ
7.15
7.10
DISABLED CURRENT (µA)
CURRENT PER AMPLIFIER (mA)
7.25
MEDIAN
7.05
7.00
6.95
6.90
MIN
6.85
6.80
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 22. ENABLED SUPPLY CURRENT vs TEMPERATURE
7
SAMPLE SIZE = 100
VS = 5V
RL = 1kΩ
620
570
520
MEDIAN
470
MIN
420
370
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 23. DISABLED SUPPLY CURRENT vs
TEMPERATURE
FN6346.0
September 11, 2008
ISL55033
Typical Performance Curves (Continued)
7
4
3
SAMPLE SIZE = 100
VS = 5V
RL = 150Ω
5
4
3
MEDIAN
2
SAMPLE SIZE = 100
VS = 5V
RL = 1kΩ
2
VOS (mV)
VOS(mV)
MAX
MAX
6
1
1
0
MEDIAN
-1
0
-2
MIN
-1
MIN
-3
-2
-3
-40
-20
0
20
40
60
80
100
-4
-40
120
-20
0
20
TEMPERATURE (°C)
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 24. OUTPUT OFFSET VOLTAGE VOS vs
TEMPERATURE
FIGURE 25. OUTPUT OFFSET VOLTAGE VOS vs
TEMPERATURE
-4.5
SAMPLE SIZE = 100
VS = 5V
SAMPLE SIZE = 100
ΔVS = 3V to 5.5V
MAX
MAX
105
PSRR (dB)
IBIAS + (µA)
-5.0
115
-5.5
MEDIAN
-6.0
MIN
95
85
MEDIAN
-6.5
75
MIN
-7.0
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
100
120
65
-40
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 27. PSRR vs TEMPERATURE
FIGURE 26. IBIAS vs TEMPERATURE
160
4.61
SAMPLE SIZE = 100
VS = 5V
RL = 150Ω
4.60
4.59
SAMPLE SIZE = 100
VS = 5V
RL = 150Ω
155
150
4.58
MAX
145
VOUT (m V)
4.57
VOUT (V)
-20
MAX
4.56
4.55
MEDIAN
4.54
140
135
MEDIAN
130
125
4.53
MIN
120
4.52
4.51
115
MIN
4.50
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 28. VOUT HIGH vs TEMPERATURE
8
120
110
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
FIGURE 29. VOUT LOW vs TEMPERATURE
FN6346.0
September 11, 2008
ISL55033
Typical Performance Curves (Continued)
34
4.78
SAMPLE SIZE = 100
VS = 5V
RL = 1kΩ
4.77
MAX
30
MAX
VOUT (mV)
VOUT (V)
4.76
32
SAMPLE SIZE = 100
VS = 5V
RL = 1kΩ
4.75
MEDIAN
4.74
MEDIAN
28
26
MIN
MIN
24
4.73
4.72
-40
-20
0
20
40
60
80
100
22
-40
120
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 31. VOUT LOW vs TEMPERATURE
FIGURE 30. VOUT HIGH vs TEMPERATURE
Pin Descriptions
ISL55033
12 LD TQFN
PIN NAME
EQUIVALENT
CIRCUIT
1
IN+_1
Circuit 1
Amplifier 1 Non-inverting Input
2
IN+_2
Circuit 1
Amplifier 2 Non-inverting Input
3
IN+_3
Circuit 1
Amplifier 3 Non-inverting Input
4
GND IN-(1, 2, 3)
Circuit 1
Common input for Amplifiers 1, 2, 3 Inverting Inputs
5
GND_PWR
Circuit 4
Power Supply Ground
6
GND_OUTPUT
Circuit 4
Output Power Supply Ground
7
OUTPUT_3
Circuit 3
Amplifier 3 Output
8
OUTPUT_2
Circuit 3
Amplifier 2 Output
9
OUTPUT_1
Circuit 3
Amplifier 1 Output
10
V+_OUTPUT
Circuit 4
Output Power Supply
11
EN
Circuit 2
Enable pin internal pull-down: Logic “1” selects the disabled state; Logic “0” selects the
enabled state
12
V+
Circuit 4
Positive Power Supply
DESCRIPTION
OUT(1, 2, 3)
OUT(4, 5, 6)
EN
dV/dt
CLAMP
GND_PWR
GND_OUT(1, 2, 3)
GND_OUT(4, 5, 6)
GND_PWR
CIRCUIT 2
- +
CIRCUIT 1
- +
GND_IN-(1,2,3)
500
GND_PWR(1,2,3)
CIRCUIT 4
9
CIRCUIT 3
V+
SUBSTRATE
GND_PWR (1,2,3)
~1MΩ
- +
IN+
V+_OUT(1, 2, 3)
V+_OUT(4, 5, 6)
V+
V+
500k
THERMAL HEAT SINK PAD
CIRCUIT 5
FN6346.0
September 11, 2008
ISL55033
DECOUPLING
CAPACITORS
V+
EN
V+_OUT
GND_OUT(1,2,3)
RIN 1
OUT_2
ROUT 2
RIN 2
- +
IN+_3
OUT_1
ROUT 1
- +
IN+_2
- +
IN+_1
RIN 3
OUT_3
ROUT 3
GND_IN(1, 2, 3)
FIGURE 32. BASIC APPLICATION CIRCUIT
Application Information
General
The ISL55033 single supply, fixed gain, triple amplifier is
intended for use in a variety of video and other high speed
applications. The device features a ground-sensing PNP
input stage and a bipolar rail-to-rail output stage. The three
amplifiers have an internally fixed gain of 2, and share a
single enable pin as shown in Figure 32.
Ground Connections
For the best isolation performance and crosstalk rejection,
all GND pins must connect directly to the GND plane. In
addition, the electrically conductive thermal pad must also
connect directly to ground.
Power Considerations
Separate V+ power supply and GND pins for the input and
output stages are provided to maximize PSRR. Providing
separate power pins provides a way to prevent high speed
transient currents in the output stage from bleeding into the
sensitive amplifier input and gain stages. To maximize
crosstalk isolation, each power supply pin should have its
own de-coupling capacitors connected as close to the pin as
possible as shown in Figure 30 (0.1µF in parallel with 1nF
recommended).
The ESD protection circuits use internal diodes from all pins to
the V+ and ground pins. In addition, a dV/dt-triggered clamp is
connected between the V+ and V- pins, as shown in the
Equivalent Circuits 1 through 4 in Figure 32. The dV/dt
triggered clamp imposes a maximum supply turn-on slew rate
of 1V/µs. Damaging currents can flow for power supply
rates-of-rise in excess of 1V/µs, such as during hot plugging.
Under these conditions, additional methods should be
10
employed to ensure the maximum rates-of-rise is not
exceeded.
Single Supply Input/Output Considerations
For best performance, the input signal voltage range should
be maintained between 0.1V to 2.1V. These input limits
correspond to an output voltage range of 0.2V to 4.2V and
define the limits of linear operation. Figure 4 shows the
frequency response versus the input DC voltage level.
Figures 16 and 17 show the differential gain-phase
performance over the input range of 0V to 2.4V operating
into a 150Ω load. The 0.1V to 2.1V input levels corresponds
to a 0.2V to 4.2V output levels, which define the minimum
and maximum range of output linear operation.
Composite video with sync requires care to ensure that the
negative sync tip voltage (typically -300mV) is properly
level-shifted up into the ISL55033 input linear operating
region of +0.1V to 2.1V. The high input impedance enables
AC coupling using low values of coupling capacitance with
relatively high input voltage divider resistances.
EN and Power-Down States
The EN pin is active low. An internal pull-down resistor
ensures the device will be active with no connection to the
EN pin. The power-down state is established within
approximately 25ns, if a logic high (>2V) is placed on the EN
pin. In the power-down state, supply current is reduced
significantly by shutting the three amplifiers off. The output
presents a relatively high impedance (~2kΩ) to the output
pin. Multiplexing several outputs together is possible using
the enable/disable function as long as the application can
tolerate the limited power-down output impedance.
FN6346.0
September 11, 2008
ISL55033
Limiting the Output Current
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than 40mA.
Adequate thermal heat sinking of the parts is also required.
PC Board Layout
The AC performance of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components, such as chip
resistors and chip capacitors, is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners. Use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces greater than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. High frequency performance may be
degraded for traces greater than one inch, unless
controlled impedance (50Ω or 75Ω) strip lines or
microstrips are used.
• Match channel-to-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
• Maximize use of AC decoupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e. no
split planes or PCB gaps under these lines). Avoid vias in the
signal I/O lines.
as possible and output termination resistors as close to the
receiving device as possible.
• When testing, use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
• A minimum of 2 power supply decoupling capacitors are
recommended (1000pF, 0.01µF) as close to the devices as
possible. Avoid vias between the capacitor and the device
because vias add unwanted inductance. Larger capacitors
can be farther away. When vias are required in a layout, they
should be routed as far away from the device as possible.
• The NIC pins are placed on both sides of the input pins.
These pins are not internally connected to the die. It is
recommended these pins be tied to ground to minimize
crosstalk.
The QFN Package Requires Additional PCB Layout
Rules for the Thermal Pad
The thermal pad is electrically connected to power supply
ground through the high resistance IC substrate. Its primary
function is to provide heat sinking for the IC. However,
because of the connection to the power ground pins through
the substrate, the thermal pad must be tied to the power
supply ground to prevent unwanted current flow through the
thermal pad. Maximum AC performance is achieved if the
thermal pad has good contact to the IC ground pins. Heat
sinking requirements can be satisfied using thermal vias
directly beneath the thermal pad to a heat dissipating layer
of a square at least 1” on a side.
• Use proper value and location of termination resistors. Input
termination resistors should be as close to the input terminal
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11
FN6346.0
September 11, 2008
ISL55033
Package Outline Drawing
L12.3x3A
12 LEAD THIN QUAD FLAT NO LEAD PLASTIC PACKAGE
Rev 0, 09/07
3.00
0.5
BSC
A
B
6
12
10
PIN #1 INDEX AREA
6
PIN 1
INDEX AREA
1
4X 1.45
3.00
9
7
3
0.10 M C A B
(4X)
0.15
4
6
0.25 +0.05 / -0.07
4
12X 0 . 4 ± 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 75
C
BASE PLANE
( 2 . 8 TYP )
1.45 )
SEATING PLANE
0.08 C
(
SIDE VIEW
0.6
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
0 . 50
NOTES:
DETAIL "X"
0 . 25
TYPICAL RECOMMENDED LAND PATTERN
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
12
FN6346.0
September 11, 2008