W255 200-MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS Features Functional Description • One input to 24-output buffer/driver • Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS • One additional output for feedback • SMBus interface for individual output control • Low skew outputs (< 100 ps) • Supports 266-, 333-, and 400-MHz DDR SDRAM • Dedicated pin for power management support • Space-saving 48-pin SSOP package The W255 is a 3.3V/2.5V buffer designed to distribute high-speed clocks in PC applications. The part has 24 outputs. Designers can configure these outputs to support four unbuffered DDR DIMMS or to support three unbuffered standard SDRAM DIMMs and two DDR DIMMS. The W255 can be used in conjunction with the W250 or similar clock synthesizer for the VIA Pro 266 chipset. The W255 also includes an SMBus interface which can enable or disable each output clock. On power-up, all output clocks are enabled (internal pull up). Pin Configuration Block Diagram FBOUT BUF_IN SSOP Top View DDR0T_SDRAM10 DDR0C_SDRAM11 DDR1T_SDRAM0 DDR1C_SDRAM1 FBOUT VDD3.3_2.5 GND DDR2T_SDRAM2 DDR0T_SDRAM10 DDR2C_SDRAM3 DDR0C_SDRAM11 DDR3T_SDRAM4 DRR1T_SDRAM0 DDR3C_SDRAM5 DDR1C_SDRAM1 VDD3.3_2.5 DDR4T_SDRAM6 GND DDR4C_SDRAM7 DDR2T_SDRAM2 DDR5T_SDRAM8 DDR2C_SDRAM3 DDR5C_SDRAM9 VDD3.3_2.5 BUF_IN DDR6T GND DDR6C DDR3T_SDRAM4 DDR7T DDR3C_SDRAM5 DDR7C VDD3.3_2.5 DDR8T GND DDR8C DDR4T_SDRAM6 DDR9T DDR4C_SDRAM7 DDR5T_SDRAM8 DDR9C DDR5C_SDRAM9 DDR10T VDD3.3_2.5 SDATA DDR10C SDATA SMBus Decoding SCLOCK R_DWN# Power Down Control DDR11C SEL_DDR • 3901 North First Street 2 48 47 3 46 4 45 5 44 6 43 7 42 8 9 41 40 10 39 11 38 12 37 13 14 36 35 15 16 34 33 17 32 18 31 19 30 20 21 29 28 22 27 23 26 24 25 SEL_DDR* VDD2.5 GND DDR11T DDR11C DDR10T DDR10C VDD2.5 GND DDR9T DDR9C VDD2.5 PWR_DWN#* GND DDR8T DDR8C VDD2.5 GND DDR7T DDR7C DDR6T DDR6C GND SCLK Note: 1. Internal 100K pull-up resistors present on inputs marked with *. Design should not rely solely on internal pull-up resistor to set I/O pins HIGH. DDR11T Cypress Semiconductor Corporation Document #: 38-07255 Rev. *C 1 • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 W255 Pin Summary Pin Name SEL_DDR Pins 48 Pin Description Input to configure for DDR-ONLY mode or STANDARD SDRAM mode. 1 = DDR-ONLY mode. 0 = STANDARD SDRAM mode. When SEL_DDR is pulled HIGH or configured for DDR-ONLY mode, pin 4, 5, 6, 7, 10, 11,15, 16, 19, 20, 21, 22, 27, 28, 29, 30, 33, 34, 38, 39, 42, 43, 44 and 45 will be configured as DDR outputs. Connect VDD3.3_2.5 to a 2.5V power supply in DDR-ONLY mode. When SEL_DDR is pulled LOW or configured for STANDARD SDRAM output, pin 4, 5, 6, 7, 10, 11, 15, 16, 19 and 20, 21, 22 will be configured as STANDARD SDRAM outputs.Pin 27, 28, 29, 30, 33, 34, 38, 39, 42, 43, 44 and 45 will be configured as DDR outputs. Connect VDD3.3_2.5 to a 3.3V power supply in STANDARD SDRAM mode. SCLK 25 SMBus clock input SDATA 24 SMBus data input BUF_IN 13 Reference input from chipset. 2.5V input for DDR-ONLY mode; 3.3V input for STANDARD SDRAM mode. FBOUT 1 Feedback clock for chipset. Output voltage depends on VDD3.3_2.5V. PWR_DWN# 36 Active LOW input to enable power-down mode; all outputs will be pulled LOW. DDR[6:11]T 28, 30, 34, 39, 43, 45 Clock outputs. These outputs provide copies of BUF_IN. DDR[6:11]C 27, 29, 33, 38, 42, 44 Clock outputs. These outputs provide complementary copies of BUF_IN. DDR[0:5]T_SDRAM [10,0,2,4,6,8] 4, 6, 10, 15, 19, 21 Clock outputs. These outputs provide copies of BUF_IN. Voltage swing depends on VDD3.3_2.5 power supply. DDR[0:5]C_SDRAM 5, 7, 11, 16, 20, 22 [11,1,3,5,7,9] Clock outputs. These outputs provide complementary copies of BUF_IN when SEL_DDR is active. These outputs provide copies of BUF_IN when SEL_DDR is inactive. Voltage swing depends on VDD3.3_2.5 power supply. VDD3.3_2.5 2, 8, 12, 17, 23 Connect to 2.5V power supply when W255 is configured for DDR-ONLY mode. Connect to 3.3V power supply, when W255 is configured for standard SDRAM mode. VDD2.5 32, 37, 41, 47 2.5V voltage supply GND 3, 9, 14, 18, 26, 31, 35, 40, 46 Ground Document #: 38-07255 Rev. *C Page 2 of 10 W255 Serial Configuration Map • The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 • Reserved and unused bits should be programmed to “0.” • SMBus Address for the W255 is: A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 ---- Byte 6: Outputs Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Bit Pin # Description Bit Pin # Reserved, drive to 0 0 Bit 6 – Reserved, drive to 0 0 Bit 5 – Reserved, drive to 0 0 Bit 4 1 FBOUT 1 Bit 3 45,44 DDR11T, DDR11C 1 Bit 2 43, 42 DDR10T, DDR10C 1 Bit 1 39, 38 DDR9T, DDR9C 1 Bit 0 34, 33 DDR8T, DDR8C 1 Description Default Bit 7 30, 29 DDR7T, DDR7C 1 Bit 6 28, 27 DDR6T, DDR6C 1 Bit 5 21, 22 DDR5T_SDRAM8, DDR5C_SDRAM9 1 Bit 4 19, 20 DDR4T_SDRAM6, DDR4C_SDRAM7 1 Bit 3 15,16 DDR3T_SDRAM4, DDR3C_SDRAM5 1 Bit 2 10, 11 DDR2T_SDRAM2, DDR2C_SDRAM3 1 Bit 1 6, 7 DDR1T_SDRAM0, DDR1C_SDRAM1 1 Bit 0 4, 5 DDR0T_SDRAM10, DDR0C_SDRAM11 1 Default Bit 7 – Document #: 38-07255 Rev. *C Byte 7: Outputs Active/Inactive Register (1 = Active, 0 = Inactive), Default = Active Page 3 of 10 W255 Maximum Ratings Storage Temperature.................................. –65°C to +150°C Supply Voltage to Ground Potential ..................–0.5 to +7.0V Static Discharge Voltage .......................................... > 2000V (per MIL-STD-883, Method 3015) DC Input Voltage (except BUF_IN) ............ –0.5V to VDD+0.5 Operating Conditions [2] Max. Unit VDD3.3 Parameter Supply Voltage Description 3.135 Min. Typ. 3.465 V VDD2.5 Supply Voltage 2.375 2.625 V TA Operating Temperature (Ambient Temperature) 0 70 °C COUT Output Capacitance 6 pF CIN Input Capacitance 5 pF Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VIL Input LOW Voltage VIH Input HIGH Voltage IIL Input LOW Current VIN = 0V Min. Typ. For all pins except SMBus Max. Unit 0.8 V 2.0 V µA 50 µA IIH Input HIGH Current VIN = VDD IOH Output HIGH Current VDD = 2.375V VOUT = 1V –18 –32 50 mA IOL Output LOW Current VDD = 2.375V VOUT = 1.2V 26 35 mA VOL Output LOW Voltage[3] VOH [3] Output HIGH Voltage IOH = –12 mA, VDD = 2.375V IDD Supply Current[3] (DDR-only mode) IDD 0.6 V Unloaded outputs, 133 MHz 400 mA Supply Current (DDR-only mode) Loaded outputs, 133 MHz 500 mA IDDS Supply Current PWR_DWN# = 0 100 µA VOUT Output Voltage Swing See test circuity (refer to Figure 1) VDD +0.6 V VOC Output Crossing Voltage (VDD/2) +0.1 V INDC Input Clock Duty Cycle 52 % Switching Characteristics Parameter – IOL = 12 mA, VDD = 2.375V 1.7 0.7 (VDD/2) –0.1 VDD/2 48 [4] Name Test Conditions Operating Frequency [3, 5] V = t2 ÷ t1 Measured at 1.4V for 3.3V outputs Measured at VDD/2 for 2.5V outputs Min. Typ. Max. Unit 66 200 MHz INDC –5% INDC +5% % 2.75 V/ns – Duty Cycle t3 SDRAM Rising Edge Rate[3] Measured between 0.4V and 2.4V 1.0 t4 [3] SDRAM Falling Edge Rate Measured between 2.4V and 0.4V 1.0 2.75 V/ns t3d DDR Rising Edge Rate[3] Measured between 20% to 80% of output (refer to Figure 1) 0.5 1.50 V/ns Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Parameter is guaranteed by design and characterization. Not 100% tested in production. 4. All parameters specified with loaded outputs. 5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/ns. Document #: 38-07255 Rev. *C Page 4 of 10 W255 Switching Characteristics (continued)[4] Parameter Name Test Conditions Max. Unit 1.50 V/ns Output to Output Skew for DDR[3] All outputs equally loaded 100 ps t6 Output to Output Skew for SDRAM[3] All outputs equally loaded 150 ps t7 SDRAM Buffer LH Prop. Delay[3] Input edge greater than 1 V/ns 5 10 ns t8 SDRAM Buffer HL Prop. Delay[3] Input edge greater than 1 V/ns 5 10 ns t4d DDR Falling Edge Rate[3] t5 Measured between 20% to 80% of output (refer to Figure 1) Min. 0.5 Typ. Switching Waveforms Duty Cycle Timing t1 t2 All Outputs Rise/Fall Time OUTPUT 2.4V 0.4V 3.3V 2.4V 0.4V t3 0V t4 Output-Output Skew OUTPUT OUTPUT t5 SDRAM Buffer HH and LL Propagation Delay 1.5V INPUT 1.5V OUTPUT t6 Document #: 38-07255 Rev. *C t7 Page 5 of 10 W255 Figure 1 shows the differential clock directly terminated by a 120Ω resistor. VCC Device Under Test Out VCC ) 60W VTR RT =120Ω Out ) 60W Receiver VCP Figure 1. Differential Signal Using Direct Termination Resistor Ordering Information Ordering Code Package Type Operating Range W255H 48-pin SSOP Commercial W255HT 48-pin SSOP–Tape and Reel Option Commercial Document #: 38-07255 Rev. *C Page 6 of 10 W255 Layout Example for DDR 2.5V Only FB VDDQ2 0.005 mF 10 mF C4 G G G G G 1 G 2 V 3 G 4 5 6 7 G 8 V 9 G 10 11 G 12 V G 13 14 15 16 G 17 V 18 G 19 20 21 22 G 23 V 24 G 48 47 G 46 45 44 43 G 42 V 41 G 40 39 G 38 V 37 G 36 G 35 34 G 33 V 32 G 31 30 29 28 27 G 26 25 V W255 G C3 G G G G G G FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) or TDK ACB 2012L-120 Ceramic Caps C3 = 10–22 µF G = VIA to GND plane layer C4 = 0.005 µF V = VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.1 µF ceramic Document #: 38-07255 Rev. *C Page 7 of 10 W255 Layout Example SDRAM (Mixed Voltage) FB FB VDDQ2 VDDQ3 C4 0.005 mF G G G G G C1 C3 G 1 2 V G 3 4 5 6 7 G 8 V 9 10 11 G 12V G 13 14 G 15 16 G 17V 18 G 19 20 21 22 23V 24 G 0.005 mf C2 G G 48 47 46 45 44 43 G 42 V 41 G 40 39 G 38 V 37 G 36 G 35 34 G 33 V 32 G 31 30 29 28 27 G 26 25 G V W255 G 10 mF 10 mF G G G G G FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) or TDK ACB 2012L-120 Ceramic Caps C1 and C3 = 10–22 µFC2 & C4 = 0.005 µF C6 = 0.1 µF G = VIA to GND plane layer V = VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors All bypass caps = 0.1 µF ceramic Document #: 38-07255 Rev. *C Page 8 of 10 W255 Package Diagram 48-lead Shrunk Small Outline Package O48 51-85061-*C VIA is a trademark of VIA Technologies, Inc. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07255 Rev. *C Page 9 of 10 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W255 Document Title: W255 200MHz 24 Output Buffer for 4 DDR or 3 SDRAM DIMMs Document Number: 38-07255 REV. ECN NO. Issue Date Orig. of Change ** 110520 12/04/01 SZV Change from Spec number: 38-01082 to 38-07255 *A 112154 03/01/02 IKA Added 333 MHz for DDR SDRAM Description of Change *B 114554 05/07/02 INA Added 400 MHz for DDR SDRAM *C 122857 12/14/02 RBI Power up requirements added to Operating Conditions Information Document #: 38-07255 Rev. *C Page 10 of 10