CY7B9911V 3.3V RoboClock+ High-Speed Low-Voltage Programmable Skew Clock Buffer (LV-PSCB) Features selectable control over system clock functions. These multipleoutput clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines with impedances as low as 50Ω while delivering minimal and specified output skews and full-swing logic levels (LVTTL). • All output pair skew <100 ps typical (250 max.) • 3.75- to 110-MHz output operation • User-selectable output functions — Selectable skew to 18 ns — Inverted and non-inverted • • • • • • • — Operation at 1⁄2 and 1⁄4 input frequency — Operation at 2x and 4x input frequency (input as low as 3.75 MHz) Zero input-to-output delay 50% duty-cycle outputs LVTTL outputs drive 50Ω terminated lines Operates from a single 3.3V supply Low operating current 32-pin PLCC package Jitter < 200 ps peak-to-peak (< 25 ps RMS) Each output can be hardwired to one of nine delay or function configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows external load and transmission line delay effects to be canceled. When this “zero delay” capability of the LVPSCB is combined with the selectable output skew functions, the user can create output-to-output delays of up to ±12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility. Functional Description The CY7B9911V 3.3V RoboClock+ High-Speed Low-Voltage Programmable Skew Clock Buffer (LVPSCB) offers user- Logic Block Diagram Pin Configuration TEST GND 32 31 30 29 2F1 REF 1 2F0 4F0 6 28 GND 4F1 7 27 1F1 VCCQ 8 26 1F0 VCCN 9 25 VCCN 4Q1 10 24 1Q0 4Q0 11 23 1Q1 GND 12 22 GND GND 13 21 14 15 16 17 18 19 20 GND 4Q1 MATRIX 3Q1 2Q1 1Q0 1F0 1F1 2Q0 2Q0 2Q1 SELECT CCN 3Q0 CY7B9911V V SKEW 3Q1 2F0 2F1 2 FB SELECT INPUTS (THREE LEVEL) 3 5 CCN 3F0 3F1 4Q0 4 3F1 V 4F0 4F1 VCCQ FS FS VCO AND TIME UNIT GENERATOR 3F0 REF FILTER 3Q0 FB TEST PLCC PHASE FREQ DET 7B9911V–2 1Q1 7B9911V–1 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 December 1, 1999 CY7B9911V 3.3V RoboClock+ Pin Definitions Signal Name I/O Description REF I Reference frequency input. This input supplies the frequency and timing against which all functional variation is measured. FB I PLL feedback input (typically connected to one of the eight outputs). FS I Three-level frequency range select. See Table 1. 1F0, 1F1 I Three-level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2. 2F0, 2F1 I Three-level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2. 3F0, 3F1 I Three-level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2. 4F0, 4F1 I Three-level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2. TEST I Three-level select. See test mode section under the block diagram descriptions. 1Q0, 1Q1 O Output pair 1. See Table 2. 2Q0, 2Q1 O Output pair 2. See Table 2. 3Q0, 3Q1 O Output pair 3. See Table 2. O Output pair 4. See Table 2. 4Q0, 4Q1 VCCN PWR Power supply for output drivers. VCCQ PWR Power supply for internal circuitry. GND PWR Ground. Block Diagram Description Skew Select Matrix These two blocks accept inputs from the Reference Frequency (REF) input and the Feedback (FB) input and generate correction information to control the frequency of the VoltageControlled Oscillator (VCO). These blocks, along with the VCO, form a Phase-Locked Loop (PLL) that tracks the incoming REF signal. The skew select matrix is comprised of four independent sections. Each section has two low-skew, high-fanout drivers (xQ0, xQ1), and two corresponding three-level function select (xF0, xF1) inputs. Table 2 below shows the nine possible output functions for each section as determined by the function select inputs. All times are measured with respect to the REF input assuming that the output connected to the FB input has 0tU selected. VCO and Time Unit Generator Table 2. Programmable Skew Configurations Phase Frequency Detector and Filter The VCO accepts analog control inputs from the PLL filter block and generates a frequency that is used by the time unit generator to create discrete time units that are selected in the skew select matrix. The operational range of the VCO is determined by the FS control pin. The time unit (tU) is determined by the operating frequency of the device and the level of the FS pin as shown in Table 1. Function Selects Table 1. Frequency Range Select and tU Calculation fNOM (MHz) FS[2, 3] Min. Max. 1 t U = -----------------------f NOM × N where N = Approximate Frequency (MHz) At Which tU = 1.0 ns Output Functions 1F1, 2F1, 3F1, 4F1 1F0, 2F0, 3F0, 4F0 1Q0, 1Q1, 2Q0, 2Q1 LOW LOW –4tU LOW MID –3tU –6tU –6tU LOW HIGH –2tU –4tU –4tU MID LOW –1tU –2tU –2tU MID MID 0tU 0tU 0tU MID HIGH +1tU +2tU +2tU 3Q0, 3Q1 4Q0, 4Q1 Divide by 2 Divide by 2 HIGH LOW +2tU +4tU +4tU LOW 15 30 44 22.7 HIGH MID +3tU +6tU +6tU MID 25 50 26 38.5 HIGH HIGH +4tU Divide by 4 Inverted HIGH 40 110 16 62.5 Notes: 1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency (fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs will be f NOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication by using a divided output as the FB input. 3. When the FS pin is selected HIGH, the REF input must not transition upon power-up until VCC has reached 2.8V. 2 U 0 t +6t U 0 t +5t U 0 t +4t U 0 t +3t U 0 t +2t 0 t +1t t 0 U U 0 t – 1t U 0 t – 2t U 0 t – 3t U 0 t – 4t U 0 t – 5t 0 t – 6t U CY7B9911V 3.3V RoboClock+ FBInput REFInput 1Fx 2Fx 3Fx 4Fx (N/A) LM – 6tU LL LH – 4tU LM (N/A) – 3tU LH ML – 2tU ML (N/A) – 1tU MM MM MH (N/A) +1tU HL MH +2tU HM (N/A) +3tU HH HL +4tU 0tU (N/A) HM (N/A) LL/HH DIVIDED (N/A) HH INVERT +6tU 7B9911V–3 Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output Test Mode Maximum Ratings The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the CY7B9911V to operate as explained briefly above (for testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied LOW through a 100Ω resistor. This will allow an external tester to change the state of these pins.) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential................–0.5V to +7.0V If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase locked loop disconnected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the same as in normal mode. DC Input Voltage ............................................–0.5V to +7.0V Output Current into Outputs (LOW)............................. 64 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) In contrast with normal operation (TEST tied LOW). All outputs will function based only on the connection of their own function select inputs (xF0 and xF1) and the waveform characteristics of the REF input. Latch-Up Current ..................................................... >200 mA Operating Range Range Ambient Temperature VCC Commercial 0°C to +70°C 3.3V ± 10% Note: 4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID). 3 CY7B9911V 3.3V RoboClock+ Electrical Characteristics Over the Operating Range CY7B9911V Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –18 mA VOL Output LOW Voltage VCC = Min., IOL = 35 mA VIH Input HIGH Voltage (REF and FB inputs only) VIL Input LOW Voltage (REF and FB inputs only) VIHH Three-Level Input HIGH Voltage (Test, FS, xFn) VIMM Min. Max. Unit 2.4 V 0.45 V 2.0 VCC V –0.5 0.8 V Min. ≤ VCC ≤ Max. 0.87 * VCC VCC V Three-Level Input MID Voltage (Test, FS, xFn) Min. ≤ VCC ≤ Max. 0.47 * VCC 0.53 * VCC V VILL Three-Level Input LOW Voltage (Test, FS, xFn) Min. ≤ VCC ≤ Max. 0.0 0.13 * VCC V IIH Input HIGH Leakage Current (REF and FB inputs only) VCC = Max., VIN = Max. 20 µA IIL Input LOW Leakage Current (REF and FB inputs only) VCC = Max., VIN = 0.4V IIHH Input HIGH Current (Test, FS, xFn) VIN = VCC IIMM Input MID Current (Test, FS, xFn) VIN = VCC/2 IILL Input LOW Current (Test, FS, xFn) IOS ICCQ µA –20 200 µA 50 µA VIN = GND –200 µA Short Circuit Current VCC = MAX, VOUT = GND (25° only) –200 mA Operating Current Used by Internal Circuitry VCCN = VCCQ = Max., All Input Selects Open Com’l 95 mA Mil/Ind 100 ICCN Output Buffer Current per Output Pair VCCN = VCCQ = Max., IOUT = 0 mA Input Selects Open, fMAX 19 mA PD Power Dissipation per Output Pair VCCN = VCCQ = Max., IOUT = 0 mA Input Selects Open, fMAX 104 mW –50 Capacitance Parameter CIN Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 10 pF Notes: 5. See the last page of this specification for Group A subgroup testing information. 6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved. 7. CY7B9911V should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 8. Total output current per output pair can be approximated by the following expression that includes device current plus load current: CY7B9911V:ICCN = [(4 + 0.11F) + [[((835 –3F)/Z) + (.0022FC)]N] x 1.1 Where F = frequency in MHz C = capacitive load in pF Z = line impedance in ohms N = number of loaded outputs; 0, 1, or 2 FC = F < C 9. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the load circuit: PD = [(22 + 0.61F) + [[(1550 + 2.7F)/Z) + (.0125FC)]N] x 1.1 See note 8 for variable definition. 10. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters. 4 CY7B9911V 3.3V RoboClock+ AC Test Loads and Waveforms VCC R1 CL R2 3.0V 2.0V Vth =1.5V 0.8V 0.0V R1=100 R2=100 CL = 30 pF (Includes fixture and probe capacitance) 2.0V Vth =1.5V 0.8V ≤1ns ≤1ns 7B9911V–4 7B9911V–5 TTL AC Test Load TTL Input Test Waveform Switching Characteristics Over the Operating Range[2, 11] CY7B9911V–5 Parameter fNOM Description Operating Clock Frequency in MHz Min. FS = LOW FS = MID [1, 2] Typ. 15 [1, 2] FS = HIGH[1, 2 , 3] Max. Unit 30 MHz 25 50 40 110 tRPWH REF Pulse Width HIGH 5.0 ns tRPWL REF Pulse Width LOW 5.0 ns tU Programmable Skew Unit See Table 1 tSKEWPR Zero Output Matched-Pair Skew (XQ0, XQ1)[13, 14] 0.1 0.25 ns 0.25 0.5 ns 0.6 0.7 ns tSKEW0 tSKEW1 [13, 15] Zero Output Skew (All Outputs) [13, 17] Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs) [13, 17] tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided) 0.5 1.0 ns tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[13, 17] 0.5 0.7 ns 0.5 1.0 ns 1.25 ns tSKEW4 [13, 17] Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted) [12, 18] tDEV Device-to-Device Skew tPD Propagation Delay, REF Rise to FB Rise –0.5 0.0 +0.5 ns tODCV Output Duty Cycle Variation –1.0 0.0 +1.0 ns 2.5 ns 3 ns tPWH tPWL Output HIGH Time Deviation from 50%   Output LOW Time Deviation from 50% [20, 21] tORISE Output Rise Time 0.15 1.0 1.5 ns tOFALL Output Fall Time[20, 21] 0.15 1.0 1.5 ns 0.5 ms 25 ps 200 ps tLOCK tJR  PLL Lock Time Cycle-to-Cycle Output Jitter RMS  Peak-to-Peak  Notes: 11. Test measurement levels for the CY7B9911V are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 30 pF and terminated with 50Ω to VCC/2 (CY7B9911V). 14. t SKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU. 15. t SKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted. 16. CL=0 pF. For CL=30 pF, tSKEW0=0.35 ns. 17. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by2 or Divide-by-4 mode). 18. t DEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.) 19. t ODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. 20. Specified with outputs loaded with 30 pF for the CY7B9911V–5 and –7 devices. Devices are terminated through 50Ω to VCC/2.tPWH is measured at 2.0V. tPWL is measured at 0.8V. 21. t ORISE and tOFALL measured between 0.8V and 2.0V. 22. t LOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 5 CY7B9911V 3.3V RoboClock+ Switching Characteristics Over the Operating Range[2, 11] (continued) CY7B9911V–7 Parameter fNOM Description Operating Clock Frequency in MHz Min. FS = LOW FS = MID [1, 2] Typ. 15 [1, 2] FS = HIGH[1, 2 , 3] Max. Unit 30 MHz 25 50 40 110 tRPWH REF Pulse Width HIGH 5.0 ns tRPWL REF Pulse Width LOW 5.0 ns tU Programmable Skew Unit See Table 1 tSKEWPR Zero Output Matched-Pair Skew (XQ0, XQ1)[13, 14] 0.1 0.25 ns 0.3 0.75 ns 0.6 1.0 ns tSKEW0 tSKEW1 [13, 15] Zero Output Skew (All Outputs) [13, 17] Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs) [13, 17] tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided) 1.0 1.5 ns tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)[13, 17] 0.7 1.2 ns 1.2 1.7 ns 1.65 ns tSKEW4 [13, 17] Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted) [12, 18] tDEV Device-to-Device Skew tPD Propagation Delay, REF Rise to FB Rise –0.7 0.0 +0.7 ns tODCV Output Duty Cycle Variation –1.2 0.0 +1.2 ns 3 ns 3.5 ns tPWH tPWL Output HIGH Time Deviation from 50%   Output LOW Time Deviation from 50% [20, 21] tORISE Output Rise Time 0.15 1.5 2.5 ns tOFALL Output Fall Time[20, 21] 0.15 1.5 2.5 ns 0.5 ms 25 ps 200 ps tLOCK tJR  PLL Lock Time Cycle-to-Cycle Output Jitter RMS  Peak-to-Peak 6  CY7B9911V 3.3V RoboClock+ AC Timing Diagrams tREF tRPWL tRPWH REF tODCV tPD tODCV FB tJR Q tSKEWPR, tSKEW0,1 tSKEWPR, tSKEW0,1 OTHER Q tSKEW2 tSKEW2 INVERTED Q tSKEW3,4 tSKEW3,4 tSKEW3,4 REF DIVIDED BY 2 tSKEW1,3, 4 tSKEW2,4 REF DIVIDED BY 4 7B9911V–8 7 CY7B9911V 3.3V RoboClock+ Operational Mode Descriptions REF LOAD Z0 L1 SYSTEM CLOCK FB REF FS LOAD 4F0 4F1 4Q0 4Q1 3F0 3F1 3Q0 3Q1 2F0 2F1 2Q0 2Q1 1F0 1F1 1Q0 1Q1 L2 Z0 LOAD L3 Z0 L4 LOAD TEST Z0 LENGTH L1 = L2 = L3 = L4 7B9911V–9 Figure 2. Zero-Skew and/or Zero-Delay Clock Driver pendent load. The FB input can be tied to any output in this configuration and the operating frequency range is selected with the FS pin. The low-skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50Ω), allows efficient printed circuit board design. Figure 2 shows the LVPSCB configured as a zero-skew clock buffer. In this mode the CY7B9911V can be used as the basis for a low-skew clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and may each drive a terminated transmission line to an indeREF SYSTEM CLOCK FB REF FS 4F0 4F1 LOAD L1 Z0 LOAD 4Q0 4Q1 3F0 3F1 2F0 2F1 3Q0 3Q1 1F0 1F1 1Q0 1Q1 L2 Z0 LOAD L3 2Q0 2Q1 Z0 L4 LOAD TEST Z0 LENGTH L1 = L2 L3 < L2 by 6 inches L4 > L2 by 6 inches 7B9911V–10 Figure 3. Programmable-Skew Clock Driver In this illustration the FB input is connected to an output with 0-ns skew (xF1, xF0 = MID) selected. The internal PLL synchronizes the FB and REF inputs and aligns their rising edges to insure that all outputs have precise phase alignment. Figure 3 shows a configuration to equalize skew between metal traces of different lengths. In addition to low skew between outputs, the LVPSCB can be programmed to stagger the timing of its outputs. The four groups of output pairs can each be programmed to different output timing. Skew timing can be adjusted over a wide range in small increments with the appropriate strapping of the function select pins. In this configuration the 4Q0 output is fed back to FB and configured for zero skew. The other three pairs of outputs are programmed to yield different skews relative to the feedback. By advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads can receive the clock pulse at the same time. Clock skews can be advanced by ±6 time units (tU) when using an output selected for zero skew as the feedback. A wider range of delays is possible if the output connected to FB is also skewed. Since “Zero Skew”, +tU, and –tU are defined relative to output groups, and since the PLL aligns the rising edges of REF and FB, it is possible to create wider output skews by proper selection of the xFn inputs. For example a +10 tU between REF and 3Qx can be achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 = High. (Since FB aligns at –4 tU and 3Qx 8 CY7B9911V 3.3V RoboClock+ simultaneously and are out of phase on their rising edge. This will allow the designer to use the rising edges of the 1⁄2 frequency and 1⁄4 frequency outputs without concern for risingedge skew. The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed by programming their select inputs accordingly. Note that the FS pin is wired for 80-MHz operation because that is the frequency of the fastest output. skews to +6 tU, a total of +10 tU skew is realized.) Many other configurations can be realized by skewing both the output used as the FB input and skewing the other outputs. REF FB REF FS REF 4F0 4F1 4Q0 4Q1 3F0 3F1 3Q0 3Q1 2F0 2F1 2Q0 2Q1 1F0 1F1 1Q0 1Q1 20 MHz TEST 7B9911V–11 Figure 4. Inverted Output Connections 10 MHz 3F0 3F1 2F0 2F1 3Q0 3Q1 5 MHz 1F0 1F1 TEST 1Q0 1Q1 2Q0 2Q1 20 MHz Figure 6 demonstrates the LVPSCB in a clock divider application. 2Q0 is fed back to the FB input and programmed for zero skew. 3Qx is programmed to divide by four. 4Qx is programmed to divide by two. Note that the falling edges of the 4Qx and 3Qx outputs are aligned. This allows use of the rising edges of the 1⁄2 frequency and 1⁄4 frequency without concern for skew mismatch. The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs. In this example, the FS input is grounded to configure the device in the 15- to 30-MHz range since the highest frequency output is running at 20 MHz. Figure 7 shows some of the functions that are selectable on the 3Qx and 4Qx outputs. These include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. An inverted output allows the system designer to clock different subsystems on opposite edges, without suffering from the pulse asymmetry typical of non-ideal loading. This function allows the two subsystems to each be clocked 180 degrees out of phase, but still to be aligned within the skew spec. 40 MHz 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 4Q0 4Q1 Figure 6. Frequency Divider Connections REF FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4F0 4F1 7B9911V–13 Figure 4 shows an example of the invert function of the LVPSCB. In this example the 4Q0 output used as the FB input is programmed for invert (4F0 = 4F1 = HIGH) while the other three pairs of outputs are programmed for zero skew. When 4F0 and 4F1 are tied HIGH, 4Q0 and 4Q1 become inverted zero phase outputs. The PLL aligns the rising edge of the FB input with the rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs to become the “inverted” outputs with respect to the REF input. By selecting which output is connect to FB, it is possible to have 2 inverted and 6 non-inverted outputs or 6 inverted and 2 non-inverted outputs. The correct configuration would be determined by the need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate for varying trace delays independent of inversion on 4Q. 20 MHz FB REF FS The divided outputs offer a zero-delay divider for portions of the system that need the clock to be divided by either two or four, and still remain within a narrow skew of the “1X” clock. Without this feature, an external divider would need to be added, and the propagation delay of the divider would add to the skew between the different clock signals. 20 MHz 80 MHz These divided outputs, coupled with the Phase Locked Loop, allow the LVPSCB to multiply the clock rate at the REF input by either two or four. This mode will enable the designer to distribute a low-frequency clock between various portions of the system, and then locally multiply the clock rate to a more suitable frequency, while still maintaining the low-skew characteristics of the clock driver. The LVPSCB can perform all of the functions described above at the same time. It can multiply by two and four or divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs. 7B9911V–12 Figure 5. Frequency Multiplier with Skew Connections Figure 5 illustrates the LVPSCB configured as a clock multiplier. The 3Q0 output is programmed to divide by four and is fed back to FB. This causes the PLL to increase its frequency until the 3Q0 and 3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by two, which results in a 40-MHz waveform at these outputs. Note that the 20- and 40-MHz clocks fall 9 CY7B9911V 3.3V RoboClock+ REF LOAD Z0 27.5-MHz DISTRIBUTION CLOCK 110-MHz INVERTED FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST LOAD 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 27.5-MHz Z0 LOAD 110-MHz ZERO SKEW 110-MHz SKEWED –2.273 ns (–4tU ) Z0 LOAD Z0 7B9911V–14 Figure 7. Multi-Function Clock Driver LOAD REF Z0 L1 FB SYSTEM CLOCK REF FS 4F0 4F1 LOAD L2 Z0 4Q0 4Q1 3F0 3F1 2F0 2F1 3Q0 3Q1 1F0 1F1 1Q0 1Q1 LOAD L3 2Q0 2Q1 Z0 L4 TEST Z0 FB REF FS 4F0 4F1 3F0 3F1 2F0 2F1 1F0 1F1 TEST 4Q0 4Q1 3Q0 3Q1 2Q0 2Q1 1Q0 1Q1 LOAD LOAD 7B9911V–15 Figure 8. Board-to-Board Clock Distribution ter clock source, approximating a zero-delay clock tree. Cascaded clock buffers will accumulate low-frequency jitter because of the non-ideal filtering characteristics of the PLL filter. It is recommended that not more than two clock buffers be connected in series. Figure 8 shows the CY7B9911V connected in series to construct a zero-skew clock distribution tree between boards. Delays of the downstream clock buffers can be programmed to compensate for the wire length (i.e., select negative skew equal to the wire delay) necessary to connect them to the mas- 10 CY7B9911V 3.3V RoboClock+ Ordering Information Accuracy (ps) Ordering Code Package Name Package Type Operating Range 500 CY7B9911V–5JC J65 32-Lead Plastic Leaded Chip Carrier Commercial 700 CY7B9911V–7JC J65 32-Lead Plastic Leaded Chip Carrier Commercial Document #: 38-00765-B Package Diagram 32-Lead Plastic Leaded Chip Carrier J65 51-85002-B © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.