INTERSIL HS1-26CLV32RH/PROTO

HS-26CLV32RH
TM
Data Sheet
August 2000
Radiation Hardened 3.3V Quad Differential
Line Receiver
The Intersil HS-26CLV32RH is a radiation hardened 3.3V
quad differential line receiver designed for digital data
transmission over balanced lines, in low voltage, RS-422
protocol applications. Radiation hardened CMOS processing
assures low power consumption, high speed, and reliable
operation in the most severe radiation environments.
The HS-26CLV32RH has an input sensitivity of 200mV (Typ)
over a common mode input voltage range of -4V to +7V. The
receivers are also equipped with input fail safe circuitry,
which causes the outputs to go to a logic “1” when the inputs
are open. The device has unique inputs that remain high
impedance when the receiver is disabled or powered-down,
maintaining signal integrity in multi-receiver applications.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95689. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
INTERNAL MKT. NO.
• Electrically Screened to SMD # 5962-95689
• QML Qualified per MIL-PRF-38535 Requirements
• 1.2 Micron Radiation Hardened CMOS
- Total Dose. . . . . . . . . . . . . . . . . . . . . 300 krad(Si)(Max)
- Single Event Upset LET . . . . . . . . . . .100MeV/mg/cm2)
- Single Event Latch-up Immune
• Low Stand-by Current. . . . . . . . . . . . . . . . . . . 13mA(Max)
• Operating Supply Range . . . . . . . . . . . . . . . . 3.0V to 3.6V
• Enable Input Levels . . . . VIH > (.7)(VDD); VIL < (.3)(VDD)
• CMOS Output Levels . . . . . . . . VOH > 2.55V; VOL < 0.4V
• Input Fail Safe Circuitry
• High Impedance Inputs when Disabled or Powered-down
• Full -55oC to 125oC Military Temperature Range
Pinouts
HS1-26CLV32RH 16 LEAD CERAMIC SIDEBRAZE DIP
MIL-STD-1835: CDIP2-T16
TOP VIEW
TEMP.
RANGE
(oC)
5962F9568902QEC
HS1-26CLV32RH-8
-55 to 125
5962F9568902QXC
HS9-26CLV32RH-8
-55 to 125
5962F9568902V9A
HS0-26CLV32RH-Q
25
5962F9568902VEC
HS1-26CLV32RH-Q
-55 to 125
5962F9568902VXC
HS9-26CLV32RH-Q
-55 to 125
ENABLE DIN DIN
+
-
DOUT
CIN CIN
+
-
COUT
1
BIN BIN
+
-
BOUT
AIN AIN
+
-
16 VDD
AIN 2
15 BIN
3
14 BIN
13 BOUT
ENABLE 4
COUT 5
12 ENABLE
CIN 6
11 DOUT
CIN 7
10 DIN
GND 8
9 DIN
HS9-26CLV32RH 16 LEAD FLATPACK
MIL-STD-1835: CDFP4-F16
TOP VIEW
HS9-26CLV32RH/PROTO HS9-26CLV32RH/PROTO -55 to 125
ENABLE
AIN 1
AOUT
HS1-26CLV32RH/PROTO HS1-26CLV32RH/PROTO -55 to 125
Logic Diagram
4907
Features
Ordering Information
ORDERING NO.
File Number
AIN
1
16
VDD
AIN
2
15
BIN
AOUT
3
14
BIN
ENABLE
4
13
BOUT
COUT
5
12
ENABLE
CIN
6
11
DOUT
CIN
7
10
DIN
GND
8
9
DIN
AOUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
HS-26CLV32RH
Die Characteristics
DIE DIMENSIONS:
Metallization:
84 mils x 130 mils x 21 mils
(2140µm x 3290µm)
Bottom: Mo/Tiw
Thickness: 5800Å ±1kÅ
Top: Al/Si/Cu
Thickness: 10kÅ ±1kÅ
INTERFACE MATERIALS:
Glassivation:
Worst Case Current Density:
Type: PSG (Phosphorus Silicon Glass)
Thickness: 8kÅ ± 1kÅ
<2.0 x 105A/cm2
Bond Pad Size:
Substrate:
110µm x 100µm
AVLSI1RA, Silicon backside, VDD backside potential
Metallization Mask Layout
HS-26CLV32RH
AIN
(1)
VDD
(16)
BIN
(15)
(14) BIN
AIN (2)
(13) BOUT
AOUT (3)
ENAB (4)
(12) ENAB
COUT (5)
(11) DOUT
(10) DIN
CIN (6)
(7)
CIN
2
(8)
GND
(9)
DIN
HS-26CLV32RH
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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3
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