HS-65647RH Radiation Hardened 8K x 8 SOS CMOS Static RAM August 1995 Features Functional Diagram • 1.2 Micron Radiation Hardened SOS CMOS - Total Dose 3 x 105 RAD (Si) - Transient Upset >1 x 1011 RAD (Si)/s - Single Event Upset < 1 x 10-12 Errors/Bit-Day • Latch-up Free • LET Threshold >250 MEV/mg/cm2 • Low Standby Supply Current 10mA (Max) • Low Operating Supply Current 100mA (2MHz) • Fast Access Time 50ns (Max), 35ns (Typ) • High Output Drive Capability • Gated Input Buffers (Gated by E2) • Six Transistor Memory Cell • Fully Static Design • Asynchronous Operation • CMOS Inputs • 5V Single Power Supply • Military Temperature Range -55oC to +125oC • Industry Standard JEDEC Pinout AI ROW ROW DECODER 128 X 512 MEMORY ARRAY INPUT DATA CIRCUIT COLUMN I/O I/O0 COLUMN DECODER I/O7 AI COL E2 E1 G CONTROL CIRCUIT W TRUTH TABLE Description The Intersil HS-65647RH is a fully asynchronous 8K x 8 radiation hardened static RAM. This RAM is fabricated using the Intersil 1.2 micron silicon-on-sapphire CMOS technology. This technology gives exceptional hardness to all types of radiation, including neutron fluence, total ionizing dose, high intensity ionizing dose rates, and cosmic rays. E1 E2 G W MODE X 0 X X Low Power Standby 1 1 X X Disabled 0 1 1 1 Enabled 0 1 0 1 Read 0 1 X 0 Write Low power operation is provided by a fully static design. Low standby power can be achieved without pull-up resistors, due to the gated input buffer design. Ordering Information TEMPERATURE RANGE PACKAGE HS1-65647RH-Q -55oC HS1-65647RH-8 -55oC HS1-65647RH/Proto -55oC to +125oC 28 Lead SBDIP +25oC 28 Lead SBDIP HS1-65647RH/Sample to +125oC 28 Lead SBDIP to +125oC 28 Lead SBDIP HS9-65647RH-Q -55oC HS9-65647RH-8 -55oC HS9-65647RH/Proto -55oC to +125oC 28 Lead Ceramic Flatpack +25oC 28 Lead Ceramic Flatpack HS9-65647RH/Sample HS9A-65647RH-Q -55oC to +125oC 28 Lead Ceramic Flatpack to +125oC 28 Lead Ceramic Flatpack to +125oC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 824 DB NA PART NUMBER 36 Lead Ceramic Flatpack Spec Number File Number 518729 2928.2 HS-65647RH Pinouts HS1-65647RH 28 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T28 TOP VIEW NC A12 1 2 HS9-65647RH 28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP3-F28 TOP VIEW 1 NC 28 VDD 27 W 28 VDD A12 2 27 W A7 3 26 E2 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 G A10 A7 3 26 E2 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 G A2 8 21 A2 8 21 A10 A1 9 20 E1 A1 9 20 E1 A0 10 19 DQ7 A0 10 19 DQ7 DQ0 11 18 DQ6 DQ0 11 18 DQ6 DQ1 12 17 DQ5 DQ1 12 17 DQ5 DQ2 13 16 DQ4 DQ2 13 16 DQ4 GND 14 15 DQ3 GND 14 15 DQ3 HS9A-65647RH 36 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) INTERSIL OUTLINE K36.A TOP VIEW 36 VDD 35 W 3 34 E2 4 33 A8 A5 5 32 A9 A4 6 31 A11 A3 7 30 G A2 8 29 A10 A1 9 28 E1 A0 10 27 DQ7 DQ0 11 26 DQ6 DQ1 12 25 DQ5 DQ2 13 24 DQ4 GND 14 23 DQ3 DQ0 15 22 DQ0 DQ1 16 21 DQ1 DQ2 17 20 DQ2 GND 18 19 GND NC A12 A7 A6 1 2 Spec Number 825 518729 Specifications HS-65647RH Absolute Maximum Ratings Reliability Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VDD+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC Typical Derating Factor. . . . . . . . . . . . 3mA/MHz Increase in IDDOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC 28 Lead SBDIP Package. . . . . . . . . . . . . 45oC/W 8.0oC/W 28/36 Lead Ceramic Flatpack Package. . 53.4oC/W 7.4oC/W Maximum Package Power Dissipation at +125oC Ambient 28 Lead SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11W 28/36 Lead Ceramic Flatpack Package. . . . . . . . . . . . . . . . 0.94W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: 28 Lead SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . .22.2mW/C 28/36 Lead Ceramic Flatpack Package. . . . . . . . . . . . .18.7mW/C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range (VDD) . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL) . . . . . . . . . . . . . . . . . . . . . . 0V to +0.2VDD Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . .0.8VDD to VDD Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER (NOTE 1) CONDITIONS SYMBOL GROUP A SUBGROUPS LIMITS TEMPERATURE -55o o MIN MAX UNITS High Level Output Voltage VOH VDD = 4.5V, IO = -5mA VI = VDD or GND 1, 2, 3 C, +25 C, +85oC, +125oC VDD0.4 - V Low Level Output Voltage VOL VDD = 4.5V, IO = 8.0mA VI = VDD or GND 1, 2, 3 -55oC, +25oC, +85oC, +125oC - 0.4 V 1, 3 -55oC, +25oC -10 10 µA -30 30 µA -60 60 µA High Impedance Output Leakage Current IOZL or IOZH VDD = 5.5V, VO = GND or VDD, VI = VDD or GND E1 = VDD, E2 = 0V 2 2 Input Leakage Current IIH or IIL VDD = 5.5V, VI = VDD or GND Standby Supply Current IDDSB (Note 3) VDD = 5.5V, IO = 0mA, VI = VDD or GND E1 = VDD, E2 = 0V IDDEN Data Retention Supply Current Functional Tests Noise Immunity Functional Test IDDOP 1.0 µA 1, 3 -55oC, +25oC - 500 µA - 4 mA 3 1 IDDDR FT FN VDD = 5.5V, IO = 0mA, VI = VDD or GND, E2 = VDD, E1 = 0V, f = 2MHz VDD = 2.0V, IO = 0mA, VI = VDD or GND E1 = VDD, E2 = 0V +125 C -1.0 2 Operating Supply Current (Note 2) o -55 C, +25 C, +85oC, +125oC 2 VDD = 5.5V, IO = 0mA, VI = VDD or GND E1 = 0.0V, E2 = VDD +85 C 1, 2, 3 2 Enable Supply Current o o o o +85 C o +125 C - 10 mA o - 77 mA o - 73 mA -55 C +25 C +85oC, +125oC - 64 mA 3 -55oC - 100 mA 1 +25oC - 86 mA 2 +85oC, +125oC - 75 mA 1, 3 -55oC, +25oC - 50 µA 2 +85oC - 1 mA 2 +125oC - 4 mA - - - - - - VDD = 4.5V and 5.5V VI = VDD or GND, f = 1MHz 7, 8A, 8B VDD = 4.5, VIL = 0.2 VDD VIH = 0.8 VDD, f = 1MHz 7, 8A, 8B -55oC, +25oC, +85oC, +125oC -55oC, +25oC, +85oC, +125oC NOTES: 1. All voltages referenced to device GND. 2. Typical IDDOP derating = 3mA/MHz (3mA increase in IDDOP per 1MHz increase in address frequency.) 3. In order for this device to be in low power standby mode. E2 must be disabled (low). Spec Number 826 518729 Specifications HS-65647RH TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL (NOTES 1, 2, 3) CONDITIONS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS Address Access Time TAVQV VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC - 50 ns Output Enable Access Time TGLQV VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC - 15 ns Chip Enable Access Time TE1LQV TE2HQV VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC - 50 ns Write Recovery Time TWHAX TE1HAX TE2LAX VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC 0 - ns Chip Enable to End-of-Write TE1LE1H TE2HE2L VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC 35 - ns Address Setup Time TAVWL TAVE1L TAVE2H VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC 5 - ns Write Enable Pulse Width TWLWH VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC 25 - ns Data Setup Time TDVWH VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC 30 - ns TDVE1H TDVE2L VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC 30 - ns Data Hold Time TWHDX VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC 0 - ns Address Hold Time TAVE1H TAVE2L VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC 40 - ns TE2LDX TE1HDX VDD = 4.5V 9, 10, 11 -55oC, +25oC, +85oC, +125oC 0 - ns NOTES: 1. AC measurements tested at worst case VDD. Guaranteed over full operating range. 2. AC measurements assume transition time ≤ 5ns; input levels = 0.0V to VDD; timing reference levels = 2.0V; output load = 1 TTL equivalent load and CL ≥ 50pF, for CL > 50pF, access times are derated 0.15ns/pF. 3. For timing waveforms, see Low Voltage Data Retention and Read/Write Cycles. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Input Capacitance I/O Capacitance Write Enable to Output in High Z SYMBOL CIN CI/O TWLQZ CONDITIONS NOTES TEMPERATURE MIN MAX UNITS VDD = Open, f = 1MHz 1, 2, 4 TA = +25oC - 12 pF VDD = Open, f = 1MHz 1, 2, 4 TA = +25oC - 12 pF VDD = Open, f = 1MHz 1, 2, 4 TA = +25oC - 12 pF VDD = Open, f = 1MHz 1, 2, 4 TA = +25oC - 12 pF 1 -55oC ≤ TA ≤ +125oC - 10 ns VDD = 4.5V and 5.5V Spec Number 827 518729 Specifications HS-65647RH TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Write Enable High to Output ON TWHQX VDD = 4.5V and 5.5V 1 -55oC ≤ TA ≤ +125oC 0 - ns Chip Enable to Output ON TE1LQX TE2HQX VDD = 4.5V and 5.5V 1 -55oC ≤ TA ≤ +125oC 0 - ns Output Enable to Output ON TGLQX VDD = 4.5V and 5.5V 1 -55oC ≤ TA ≤ +125oC 0 - ns Chip Enable to Output in High Z TE1HQZ TE2LQZ VDD = 4.5V and 5.5V 1 -55oC ≤ TA ≤ +125oC - 15 ns Output Disable to Output in High Z TGHQZ VDD = 4.5V and 5.5V 1 -55oC ≤ TA ≤ +125oC - 15 ns Output Hold from Address Change TAXQX VDD = 4.5V and 5.5V 1 -55oC ≤ TA ≤ +125oC 0 - ns NOTES: 1. The parameters listed are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. 2. Applies to DIP device types only. 3. Applies to Flatpack device types only. 4. All measurements referenced to device GND. TABLE 4. POST 300K RAD DC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS TEMPERATURE MIN MAX UNITS Standby Supply Current IDDSB VDD = 5.5V, IO = 0mA, E1 = VDD, E2 = 0V, VI = VDD or GND +25oC - 10 mA Enabled Supply Current IDDEN VDD = 5.5V, IO = 0mA, E1 = 0.0V, E2 = VDD, VI = VDD or GND +25oC - 82 mA Operating Supply Current (Note 2) IDDOP VDD = 5.5V, IO = 0mA, f = 2MHz, E = 0V,VI = VDD or GND +25oC - 100 mA Data Retention Supply Current IDDDR VDD = 2.0V, IO = 0mA, E = VDD +25oC - 6 mA NOTES: 1. DC parameters not listed in this table are tested at the +25oC pre-irradiation test limits. All AC parameters are tested at the +25oC preirradiation test limits. 2. Typical IDDOP derating = 3mA/MHz (3mA increase in IDDOP per 1MHz increase in address frequency.) Spec Number 828 518729 HS-65647RH TABLE 5. BURN-IN DELTA PARAMETERS (+25oC), GROUP B, SUBGROUP 5 PARAMETER SYMBOL DELTA LIMITS IDDSB ±150µA IOZH, IOZL ± 2µA IIH, IIL ± 150nA Low Level Output Voltage VOL ± 60mV Output High Voltage VOH ± 150mV Standby Supply Current High Impedance Output Leakage Current Input Leakage Current TABLE 6. APPLICABLE SUBGROUPS GROUP A SUBGROUPS CONFORMANCE GROUP MIL-STD-883 METHOD TESTED FOR -Q RECORDED FOR -Q TESTED FOR -8 Initial Test 100% 5004 1, 7, 9 1 (Note 2) 1, 7, 9 Interim Test 100% 5004 1, 7, 9, ∆ 1, ∆ (Note 2) 1, 7, 9 PDA 100% 5004 1, 7, ∆ - 1, 7 Final Test 100% 5004 2, 3, 8A, 8B, 10, 11 - 2, 3, 8A, 8B, 10, 11 Group A (Note 1) Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, ∆ 1, 2, 3, ∆ (Note 2) N/A Subgroup B6 Sample 5005 1, 7, 9 - N/A Group C Sample 5005 N/A N/A 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Group D Sample 5005 1, 7, 9 - 1, 7, 9 Group E, Subgroup 2 Sample 5005 1, 7, 9 - 1, 7, 9 RECORDED FOR -8 NOTES: 1. Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised. 2. Table 5 parameters only Spec Number 829 518729 HS-65647RH Intersil Space Level Product Flow -Q Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) 100% Interim Electrical Test 1 (T1) GAMMA Radiation Verification (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects 100% PDA 1, Method 5004 (Note 1) 100% Delta Calculation (T0-T1) 100% Nondestructive Bond Pull, Method 2023 100% Dynamic Burn-In, Condition D, 240 Hours, +125oC or Equivalent, Method 1015 Sample - Wire Bond Pull Monitor, Method 2011 100% Interim Electrical Test 2(T2) Sample - Die Shear Monitor, Method 2019 or 2027 100% Delta Calculation (T0-T2) 100% Internal Visual Inspection, Method 2010, Condition A 100% PDA 2, Method 5004 (Note 1) 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Final Electrical Test 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% Radiographic (X-Ray), Method 2012 (Note 2) 100% Fine/Gross Leak, Method 1014 100% External Visual, Method 2009 100% PIND, Method 2020, Condition A Sample - Group A, Method 5005 (Note 3) 100% External Visual Sample - Group B, Method 5005 (Note 4) 100% Serialization Sample - Group D, Method 5005 (Notes 4 and 5) 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 72 Hours Min, +125oC Min, Method 1015 100% Data Package Generation (Note 6) NOTES: 1. Failures from subgroup 1, 7 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 2. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 3. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 4. Group B and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for Group B Test, Group Samples, Group D Test and Group D Samples. 5. Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group D Generic Data. Generic data is not guaranteed to be available and is therefore not available in all cases. 6. Data Package Contents: • Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). • Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. • GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. • X-Ray report and film. Includes penetrometer measurements. • Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). • Lot Serial Number Sheet (Good units serial number and lot number). • Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. • Group B and D attributes and/or Generic data is included when required by the P.O. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. Spec Number 830 518729 HS-65647RH Intersil Space Level Product Flow -8 GAMMA Radiation Verification (Each Wafer) Method 1019, 2 Samples/Wafer, 0 Rejects 100% Dynamic Burn-In, Condition D, 160 Hours, +125oC or Equivalent, Method 1015 Periodic- Wire Bond Pull Monitor, Method 2011 100% Interim Electrical Test Periodic- Die Shear Monitor, Method 2019 or 2027 100% PDA, Method 5004 (Note 1) 100% Internal Visual Inspection, Method 2010, Condition B 100% Final Electrical Test 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles 100% Fine/Gross Leak, Method 1014 100% Constant Acceleration, Method 2001, Condition per Method 5004 Sample - Group A, Method 5005 (Note 2) 100% External Visual 100% Initial Electrical Test 100% External Visual, Method 2009 Sample - Group B, Method 5005 (Note 3) Sample - Group C, Method 5005 (Notes 3 and 4) Sample - Group D, Method 5005 (Notes 3 and 4) 100% Data Package Generation (Note 5) NOTES: 1. Failures from subgroup 1, 7 are used for calculating PDA. The maximum allowable PDA = 5%. 2. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 3. Group B, C and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for Group B Test, Group C Test, Group C Samples, Group D Test and Group D Samples. 4. Group C and/or Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group C Generic Data and/or Group D Generic Data. Generic data is not guaranteed to be available and is therefore not available in all cases. 5. Data Package Contents: • Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). • GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. • Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). • Group B, C and D attributes and/or Generic data is included when required by the P.O. • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. Spec Number 831 518729 HS-65647RH Timing Waveforms TAVAX A ADDRESS 2 ADDRESS 1 TAVQV TAXQX DATA 1 Q DATA 2 FIGURE 1. READ CYCLE I: W, E2 HIGH; G, E1 LOW TAVAX A TAVQV E1 TE1LQV TE1HQZ TE1LQX E2 TE2HQV TE2LQZ TE2HQX G TGHQZ TGLQV TGLQX Q FIGURE 2. READ CYCLE II: W HIGH TAVAX A TAVWL TWLWH TWHAX W E1 E2 TWHQX TDVWH TWHDX D TWLQZ Q FIGURE 3. WRITE CYCLE I: LATE WRITE Spec Number 832 518729 HS-65647RH Timing Waveforms (Continued) TAVAX A TAVE1L TE1LE1H TAVE2H TE1HAX W E1 E2 TDVE1H TE1HDX D FIGURE 4. WRITE CYCLE II: EARLY WRITE - CONTROLLED BY E1 TAVAX A TAVE2H W TE2HE2L TE2LAX TAVE2L E1 E2 TDVE2L TE2LDX D FIGURE 5. WRITE CYCLE III: EARLY WRITE - CONTROLLED BY E2 Spec Number 833 518729 HS-65647RH Performance Curves HS-65647RH TYPICAL PERFORMANCE CHARACTERISTICS TA = +25oC, Unless Otherwise Specified 13 7 12 6 11 10 5 8 IDDSB (mA) IDDSB (mA) 9 7 6 5 4 4 3 2 3 2 1 1 0 0 0 200 400 600 800 1000 TOTAL DOSE (KRAD) 1200 0.1 1400 0.1 10 ANNEAL TIME (HOURS) FIGURE 7 10 100 9 90 8 80 7 70 6 60 IDDEN (mA) IDDSB (mA) FIGURE 6 100 5 4 50 40 3 30 2 20 1 10 0 0 -60 -40 -20 0 20 40 60 TEMPERATURE (oC) 80 100 -60 120 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (oC) FIGURE 8 FIGURE 9 120 106 102 100 98 90 94 90 80 IDDOP (mA) IDDOP (mA) 110 70 60 86 82 78 74 50 70 40 66 30 62 20 58 -60 -40 -20 0 20 40 60 80 100 0 120 1 2 3 4 5 6 7 8 9 10 FREQUENCY (MHz) TEMPERATURE (oC) FIGURE 10 FIGURE 11 Spec Number 834 518729 HS-65647RH Burn-In Circuits HS-65647RH 28 LEAD FLATPACK AND CERAMIC DIP HS-65647RH 28 LEAD FLATPACK AND CERAMIC DIP VDD VDD 1 1 NC NC VDD 2 F13 A12 W A7 E2 A6 A8 A5 A9 A4 A11 A3 G A2 A10 A1 E1 A0 DQ7 3 F8 4 F7 5 F6 6 F5 7 F4 8 F3 9 F2 10 F1 F14 F14 F14 R2 11 R2 12 R2 13 14 DQ0 DQ1 DQ2 VSS DQ6 DQ5 DQ4 DQ3 NC 28 2 27 3 F0 26 4 25 24 23 F9 5 F10 6 F12 7 F0 8 F11 9 22 21 20 10 19 R2 18 R2 F14 11 NC 12 F14 R2 17 16 R2 15 R2 NC 13 F14 NC F14 14 NC VDD A12 W A7 E2 A6 A8 A5 A9 A4 A11 A3 G A2 A10 A1 E1 A0 DQ7 DQ0 DQ6 DQ1 DQ5 DQ2 DQ4 VSS DQ3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC NC NC NC NC F14 DYNAMIC CONFIGURATION NOTES: 1. VDD = 5.5V Min 2. R = 10kΩ ± 10%, except R2 = 47kΩ ± 10% 3. VIH: VDD ± 0.5V, VIL: 0.4V ± 0.4V 4. F0 = 100kHz ± 10%, 50% Duty Cycle 5. F1 = F0/2; F2 = F1/2; F3 = F2/2; . . . F14 = F13/2 6. F0 = inverted F0 STATIC CONFIGURATION NOTES: 1. VDD = 5.5V Min 2. R = 10kΩ ± 10% HS-65647RH 36 LEAD FLATPACK HS-65647RH 36 LEAD FLATPACK VDD VDD 1 2 NC 3 4 F13 5 F8 6 F7 7 F6 8 F5 9 F4 10 F3 11 F2 12 F1 F14 R2 13 F14 R2 14 F14 R2 15 NC 16 17 18 VSS VSS VDD VDD NC NC A12 W A7 E2 A6 A5 A4 A3 A2 A1 A0 A8 A9 A11 G A10 E1 DQ7 DQ0 DQ6 DQ1 DQ5 DQ2 DQ4 NC DQ3 VDD VDD VSS VSS 36 1 35 2 34 3 NC NC 4 33 F0 32 5 31 6 F9 7 30 29 28 F10 8 F12 9 F0 27 10 F11 11 26 25 R2 24 R2 23 R2 22 R2 21 R2 12 F14 F14 NC F14 NC F14 NC NC F14 14 15 16 17 20 18 19 DYNAMIC CONFIGURATION NOTES: 1. VDD = 5.5V Min 2. R = 10kΩ ± 10%, except R2 = 4.7kΩ ± 10% 3. VIH: VDD ± 0.5V, VIL: 0.4V ± 0.4V 4. F0 = 100kHz ± 10%, 50% Duty Cycle 5. F1 = F0/2; F2 = F1/2; F3 = F2/2; . . . F14 = F13/2 6. F0 = Inverted F0 13 VSS VSS VDD VDD NC NC A12 W A7 E2 A6 A8 A5 A9 A4 A11 A3 G A2 A10 A1 E1 A0 DQ7 DQ0 DQ6 DQ1 DQ5 DQ2 DQ4 NC DQ3 VDD VDD VSS VSS 36 35 34 NC 33 32 31 30 29 28 27 26 25 24 23 22 21 NC NC NC NC NC 20 19 STATIC CONFIGURATION NOTES: 1. VDD = 5.5V Min 2. R = 10kΩ ± 10% Spec Number 835 518729 HS-65647RH Irradiation Circuit HS-65647RH (8K x 8 TSOS4 SRAM) 28 LEAD CERAMIC DIP VDD NC 1 NC VDD 28 2 A12 W 27 3 A7 E2 26 4 A6 A8 25 5 A5 A9 24 6 A4 A11 23 7 A3 G 22 8 A2 A10 21 9 A1 E1 20 10 A0 DQ7 19 11 DQ0 DQ6 18 12 DQ1 DQ5 17 13 DQ2 DQ4 16 14 VSS DQ3 15 NOTES: 1. VDD = 5.5V ± 0.5V R = 10kΩ ± 10% 2. Group E sample size is two die/wafer. Test Patterns MARCH (II)PATTERN After a background of zeros is written, each cell (from beginning to end in sequence) is read, written to a one and reread. When the array is full of ones each cell (from the end to the beginning) is read, restored to a zero and reread. each other cell in the row. The test cell is then rewritten back to a zero. The test cell is then incremented and the sequence is repeated until all cells in the memory have been used as a test cell. After this the pattern is repeated but with complemented data. This is pattern then repeated but using complemented data. MASEST PATTERN (Multiple Address Select Pattern) A checkerboard pattern is written into the memory. Then the first cell is read, then its binary address complement is read. The second cell is read and then its binary address complement is read. This pattern of incrementing the address and then reading its binary address complement is repeated until the entire memory is read. This is then repeated but using a checkerboard bar pattern. GALCOL PATTERN (Column Galloping Pattern) After a background of zeros is written into the memory a one is written into the first cell. It is then read alternately with each other cell in the column. The test cell is then rewritten back to a zero. The test cell is then incremented and the sequence is repeated until all cells in the memory have been used as a test cell. This is pattern then repeated but using complemented data. CHECKERBOARD BAR GALROW PATTERN (Row Galloping Pattern) After a background of zeros is written into the memory a one is written into the first cell. It is then read alternately with PATTERN and CHECKERBOARD A checkerboard is written (101010) into the memory and then the pattern is read back. This is then repeated but using complemented data. Spec Number 836 518729 HS-65647RH Metallization Topology GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ DIE DIMENSIONS: 313 x 291 x 21 ±1mils METALLIZATION: Type: Al/Si/Cu Metal 1 Thickness: 7500Å ± 2kÅ Metal 2 Thickness: 10kÅ ± 2kÅ WORST CASE CURRENT DENSITY: 1.5 x 105 Amps/cm2 Metallization Mask Layout (22) G NC (23) A11 (24) A9 (25) A8 (26) E2 (27) W (28) VDD (2) A12 (3) A7 (4) A6 (5) A5 (6) A4 NC (7) A3 HS-65647RH NC A10 (21) E (20) DQ7 (19) DQ6 (18) D15 (17) DQ4 (16) DQ3 (15) VDD VSS (14) DQ2 (13) DQ1 (12) DQ0 (11) A0 (10) VDD A1 (9) VDD A2 (8) VSS NC VSS Spec Number 837 518729 HS-65647RH Packaging K36.A A e 36 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE A INCHES PIN NO. 1 ID AREA -A- D -B- MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.138 - 3.51 - b 0.006 0.013 0.15 0.33 - b1 0.006 0.010 0.15 0.25 - S1 b E1 0.004 M H A-B S D S 0.036 M H A-B S D S C Q E -D- A -C- -HE2 L E3 SEATING AND BASE PLANE c1 L 0.004 0.011 0.10 0.28 - 0.004 0.008 0.10 0.20 - D 0.620 0.640 15.75 16.26 3 E 0.620 0.640 15.75 8.64 - 16.76 3 12.45 - E1 - 0.660 E2 0.470 0.490 11.94 E3 0.030 - 0.76 e E3 LEAD FINISH BASE METAL c c1 (c) b1 - 0.025 BSC - 7 0.64 BSC - k - - - - - L 0.240 0.280 6.10 7.11 - Q 0.026 0.045 0.66 1.14 8 S1 - - - - - M - 0.0015 - 0.04 - M M N (b) 36 36 Rev. 0 5/18/94 SECTION A-A NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. Spec Number 838 518729 HS-65647RH All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Spec Number 839