8673EDxxB IP

GS8673ED18/36BK-725S/625S/550S
72Mb SigmaQuad-IIIe™
Burst of 4 ECCRAM™
260 Pin BGA
Commercial Temp
Industrial Temp
Up to 725 MHz
1.35V VDD
1.2V or 1.35V or 1.5V VDDQ
Features
Clocking and Addressing Schemes
• For use with GSI SRAM Port IP
• 2Mb x 36 and 4Mb x 18 organizations available
• 725 MHz maximum operating frequency
• 725 MT/s peak transaction rate (in millions per second)
• 104 Gb/s peak data bandwidth (in x36 devices)
• Separate I/O DDR Data Buses
• Non-multiplexed SDR Address Bus
• One operation - Read or Write - per clock cycle
• Burst of 4 Read and Write operations
• 3 cycle Read Latency
• On-chip ECC with virtually zero SER
• 1.35V core voltage
• 1.2V or 1.35V or 1.5V I/O interface (HSTL or SSTL)
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260 pin, 14 mm x 22 mm, 1 mm ball pitch BGA package
–K: 5/6 RoHS-compliant package
–GK: 6/6 RoHS-compliant package
The GS8673ED18/36BK SigmaQuad-IIIe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IIIe B4
ECCRAM is four times wider than the device I/O bus. An
input data bus de-multiplexer is used to accumulate incoming
data before it is simultaneously written to the memory array.
An output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IIIe B4 ECCRAM is always two address
pins less than the advertised index depth (e.g. the 4M x 18 has
1M addressable index).
On-Chip ECC
SigmaQuad-IIIe™ Family Overview
SigmaQuad-IIIe ECCRAMs are the Separate I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
Parameter Synopsis
Speed Grade
Max Operating Frequency
Read Latency
VDD
-725S
725 MHz
3 cycles
1.3V to 1.4V
-625S
625 MHz
3 cycles
1.3V to 1.4V
-550S
550 MHz
3 cycles
1.3V to 1.4V
Rev: 1.04 6/2015
1/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
4M x 18 (Top View)
6
7
8
1
2
3
4
5
9
10
11
12
13
A
VDD
VDDQ
VDD
VDDQ
MCL
MCH
(CFG)
MCL
ZQ
PZT1
VDDQ
VDD
VDDQ
VDD
B
VSS
NUO
VSS
NUI
MVQ
MCH
(B4M)
NC
(RSVD)
MCH
(SIOM)
PZT0
D0
VSS
Q0
VSS
C
Q17
VDDQ
D17
VDDQ
VSS
SA
VDD
SA
VSS
VDDQ
NUI
VDDQ
NUO
D
VSS
NUO
VSS
NUI
SA
VDDQ
NC
(288 Mb)
VDDQ
NC
(144 Mb)
D1
VSS
Q1
VSS
E
Q16
VDDQ
D16
VDD
VSS
SA
VSS
SA
VSS
VDD
NUI
VDDQ
NUO
F
VSS
NUO
VSS
NUI
SA
VDD
VDDQ
VDD
SA
D2
VSS
Q2
VSS
G
Q15
NUO
D15
NUI
VSS
SA
MZT1
SA
VSS
D3
NUI
Q3
NUO
H
Q14
VDDQ
D14
VDDQ
SA
VDDQ
W
VDDQ
SA
VDDQ
NUI
VDDQ
NUO
J
VSS
NUO
VSS
NUI
VSS
SA
VSS
SA
VSS
D4
VSS
Q4
VSS
K
CQ1
VDDQ
VREF
VDD
KD1
VDD
CK
VDD
KD0
VDD
VREF
VDDQ
CQ0
L
CQ1
VSS
QVLD1
Vss
KD1
VDDQ
CK
VDDQ
KD0
VSS
QVLD0
VSS
CQ0
M
VSS
Q13
VSS
D13
VSS
SA
VSS
SA
VSS
NUI
VSS
NUO
VSS
N
NUO
VDDQ
NUI
VDDQ
MCL
VDDQ
R
VDDQ
MCH
VDDQ
D5
VDDQ
Q5
P
NUO
Q12
NUI
D12
VSS
SA
MZT0
SA
VSS
NUI
D6
NUO
Q6
R
VSS
Q11
VSS
D11
MCH
VDD
VDDQ
VDD
RST
NUI
VSS
NUO
VSS
T
NUO
VDDQ
NUI
VDD
VSS
SA
VSS
SA
VSS
VDD
D7
VDDQ
Q7
U
VSS
Q10
VSS
D10
NUI
VDDQ
MCL
VDDQ
NUI
NUI
VSS
NUO
VSS
V
NUO
VDDQ
NUI
VDDQ
VSS
SA
(x18)
VDD
NUI
(B2)
VSS
VDDQ
D8
VDDQ
Q8
W
VSS
Q9
VSS
D9
TCK
MCH
NC
(RSVD)
MCL
TMS
NUI
VSS
NUO
VSS
Y
VDD
VDDQ
VDD
VDDQ
TDO
ZT
MCH
MCL
TDI
VDDQ
VDD
VDDQ
VDD
Notes:
1. Pins 5A, 5N, 7A, 7U, 8W, and 8Y must be tied Low in this device.
2. Pins 5R, 6W, 7Y, and 9N must be tied High in this device.
3. Pins 5U and 9U are unused in this device. They must be left unconnected or driven Low.
4. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.
5. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
6. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied High in this device to select Burst-of-4 configuration.
7. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.
8. Pin 8V is defined as address pin SA for B2 devices. It is unused in this device, and must be left unconnected or driven Low.
9. Pin 9D is reserved as address pin SA for 144 Mb devices. It is a true no connect in this device.
10. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.
Rev: 1.04 6/2015
2/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
2M x 36 (Top View)
6
7
8
1
2
3
4
5
9
10
11
12
13
A
VDD
VDDQ
VDD
VDDQ
MCL
MCL
(CFG)
MCL
ZQ
PZT1
VDDQ
VDD
VDDQ
VDD
B
VSS
Q35
VSS
D35
MVQ
MCH
(B4M)
NC
(RSVD)
MCH
(SIOM)
PZT0
D0
VSS
Q0
VSS
C
Q26
VDDQ
D26
VDDQ
VSS
SA
VDD
SA
VSS
VDDQ
D9
VDDQ
Q9
D
VSS
Q34
VSS
D34
SA
VDDQ
NC
(288 Mb)
VDDQ
NC
(144 Mb)
D1
VSS
Q1
VSS
E
Q25
VDDQ
D25
VDD
VSS
SA
VSS
SA
VSS
VDD
D10
VDDQ
Q10
F
VSS
Q33
VSS
D33
SA
VDD
VDDQ
VDD
SA
D2
VSS
Q2
VSS
G
Q24
Q32
D24
D32
VSS
SA
MZT1
SA
VSS
D3
D11
Q3
Q11
H
Q23
VDDQ
D23
VDDQ
SA
VDDQ
W
VDDQ
SA
VDDQ
D12
VDDQ
Q12
J
VSS
Q31
VSS
D31
VSS
SA
VSS
SA
VSS
D4
VSS
Q4
VSS
K
CQ1
VDDQ
VREF
VDD
KD1
VDD
CK
VDD
KD0
VDD
VREF
VDDQ
CQ0
L
CQ1
VSS
QVLD1
VSS
KD1
VDDQ
CK
VDDQ
KD0
VSS
QVLD0
VSS
CQ0
M
VSS
Q22
VSS
D22
VSS
SA
VSS
SA
VSS
D13
VSS
Q13
VSS
N
Q30
VDDQ
D30
VDDQ
MCL
VDDQ
R
VDDQ
MCH
VDDQ
D5
VDDQ
Q5
P
Q29
Q21
D29
D21
VSS
SA
MZT0
SA
VSS
D14
D6
Q14
Q6
R
VSS
Q20
VSS
D20
MCH
VDD
VDDQ
VDD
RST
D15
VSS
Q15
VSS
T
Q28
VDDQ
D28
VDD
VSS
SA
VSS
SA
VSS
VDD
D7
VDDQ
Q7
U
VSS
Q19
VSS
D19
NUI
VDDQ
MCL
VDDQ
NUI
D16
VSS
Q16
VSS
V
Q27
VDDQ
D27
VDDQ
VSS
NUI
(x18)
VDD
NUI
(B2)
VSS
VDDQ
D8
VDDQ
Q8
W
VSS
Q18
VSS
D18
TCK
MCH
NC
(RSVD)
MCL
TMS
D17
VSS
Q17
VSS
Y
VDD
VDDQ
VDD
VDDQ
TDO
ZT
MCH
MCL
TDI
VDDQ
VDD
VDDQ
VDD
Notes:
1. Pins 5A, 5N, 7A, 7U, 8W, and 8Y must be tied Low in this device.
2. Pins 5R, 6W, 7Y, and 9N must be tied High in this device.
3. Pins 5U and 9U are unused in this device. They must be left unconnected or driven Low.
4. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied Low in this device to select x36 configuration.
5. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
6. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied High in this device to select Burst-of-4 configuration.
7. Pin 6V is defined as address pin SA for x18 devices. It is unused in this device, and must be left unconnected or driven Low.
8. Pin 8V is defined as address pin SA for B2 devices. It is unused in this device, and must be left unconnected or driven Low.
9. Pin 9D is reserved as address pin SA for 144 Mb devices. It is a true no connect in this device.
10. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.
Rev: 1.04 6/2015
3/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
Pin Description
Symbol
Description
Type
Address — Read or Write Address is registered on CK.
Input
D[35:0]
Write Data — Registered on KD and KD during Write operations.
D[17:0] - x18 and x36.
D[35:18] - x36 only.
Input
Q[35:0]
Read Data — Aligned with CQ and CQ during Read operations.
Q[17:0] - x18 and x36.
Q[35:18] - x36 only.
Output
QVLD[1:0]
Read Data Valid—Driven high one half cycle before valid read data.
Output
SA
CK, CK
Primary Input Clocks — Dual single-ended. Used for latching address and control inputs, for internal timing
control, and for output timing control.
Input
KD[1:0],
KD[1:0]
Write Data Input Clocks — Dual single-ended. Used for latching write data inputs.
KD0, KD0: latch D[17:0] in x36, D[8:0] in x18.
KD1, KD1: latch D[35:18] in x36, D[17:9] in x18.
Input
CQ[1:0],
CQ[1:0]
Echo Clocks — Free-running output (echo) clocks, tightly aligned with read data outputs. Facilitate
source-synchronous operation.
CQ0, CQ0: align with Q[17:0] in x36, Q[8:0] in x18.
CQ1, CQ1: align with Q[35:18] in x36, Q[17:9] in x18.
Output
R
Read Enable — Registered on CK. R = 0 initiates a Read operation.
Input
W
Write Enable — Registered on CK. W = 0 initiates a Write operation.
Input
RST
Reset — Holds the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
Input
ZQ
Driver Impedance Control Resistor Input — Must be connected to VSS through an external resistor RQ to
program driver impedance.
Input
ZT
ODT Impedance Control Resistor Input — Must be connected to VSS through an external resistor RT to
program ODT impedance.
Input
MZT[1:0]
ODT Mode Select — Set the ODT state globally for all input groups. Must be tied High or Low.
MZT[1:0] = 00: disables ODT on all input groups, regardless of PZT[1:0].
MZT[1:0] = 01: enables strong ODT on select input groups, as specified by PZT[1:0].
MZT[1:0] = 10: enables weak ODT on select input groups, as specified by PZT[1:0].
MZT[1:0] = 11: reserved.
Input
PZT[1:0]
ODT Configuration Select — Set the ODT state for various combinations of input groups when MZT[1:0] =
01 or 10. Must be tied High or Low.
PZT[1:0] = 00: enables ODT on write data only.
PZT[1:0] = 01: enables ODT on write data and input clocks.
PZT[1:0] = 10: enables ODT on write data, address, and control.
PZT[1:0] = 11: enables ODT on write data, input clocks, address, and control.
Input
Rev: 1.04 6/2015
4/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
Pin Description (Continued)
Symbol
Description
Type
MVQ
I/O Voltage Select — Indicates what voltage is supplied to the VDDQ pins. Must be tied High or Low.
MVQ = 0: Configure for 1.2V or 1.35V nominal VDDQ.
MVQ = 1: Configure for 1.5V nominal VDDQ.
VDD
Core Power Supply — 1.35V nominal core supply voltage.
—
VDDQ
I/O Power Supply — 1.2V or 1.35V or 1.5V nominal I/O supply voltage. Configurable via MVQ pin.
—
VREF
Input Reference Voltage — Input buffer reference voltage.
—
VSS
Ground
—
TCK
JTAG Clock
Input
TMS
JTAG Mode Select — Weakly pulled High internally.
Input
TDI
JTAG Data Input — Weakly pulled High internally.
Input
TDO
JTAG Data Output
MCH
Must Connect High — May be tied to VDDQ directly or via a 1k resistor.
Input
MCL
Must Connect Low — May be tied to VSS directly or via a 1k resistor.
Input
NC
No Connect — There is no internal chip connection to these pins. They may be left unconnected, or tied
High or Low.
NUI
Not Used Input — There is an internal chip connection to these input pins, but they are unused by the
device. They are pulled Low internally. They may be left unconnected or tied/driven Low. They should not be
tied/driven High.
Input
NUO
Not Used Output — There is an internal chip connection to these output pins, but they are unused by the
device. The drivers are tri-stated internally. They should be left unconnected.
Output
Rev: 1.04 6/2015
Input
Output
5/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
—
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
Power-Up and Reset Requirements
For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
VSS, VDD, VDDQ, VREF and inputs.
Power supplies must power down simultaneously, or in the reverse sequence.
After power supplies power up, the following start-up sequence must be followed.
Step 1 (Recommended, but not required): Assert RST High for at least 1ms.
While RST is asserted high:
• Read and Write operations are ignored.
Note: If possible, RST should be asserted High before input clocks (begin toggling, and remain asserted High until input clocks are
stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing trouble in the SRAM.
Step 2: Begin toggling input clocks.
After input clocks begin toggling, but not necessarily within specification:
• CQ, CQ begin toggling, but not necessarily within specification.
Step 3: Wait until input clocks are stable and toggling within specification.
Step 4: De-assert RST Low (if asserted High).
Step 5: Wait at least 160K (163,840) cycles for driver and ODT impedances to calibrate.
After the impedances have calibrated:
• CQ, CQ begin toggling within specification.
Step 6: Begin initiating Read and Write operations.
Reset Usage
Although not generally recommended, RST may be asserted High at any time after completion of the initial power-up sequence
described above, to reset the SRAM control logic to its initial power-on state. However, whenever RST is subsequently de-asserted
Low (as in Step 4 in the power up sequence), at least 160K NOP cycles must be initiated (as in Step 5 in the power-up sequence)
before Read and Write operations are initiated.
Note: Memory array content may be perturbed/corrupted when RST is asserted High.
Rev: 1.04 6/2015
6/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
Error Correction (ECC)
These devices implement a single-bit error detection and correction algorithm (specifically, a Hamming Code) on each DDR data
word (comprising two 9-bit data bytes) transmitted on each 9-bit data bus (i.e., transmitted on D/Q[8:0], D/Q[17:9], D/Q[26:18],
and D/Q[35:27]). To accomplish this, 5 ECC parity bits (invisible to the user) are utilized per every 18 data bits (visible to the
user).
The ECC algorithm neither corrects nor detects multi-bit errors. However, ECCRAMs are architected in such a way that a single
SER event very rarely causes a multi-bit error across any given “transmitted data unit”, where a “transmitted data unit” represents
the data transmitted as the result of a single read or write operation to a particular address. The extreme rarity of multi-bit errors
results in the SER mentioned previously (i.e., <0.002 FITs/Mb (measured at sea level)).
Not only does the on-chip ECC significantly improve SER performance, but it also frees up the entire memory array for data
storage. Frequently, SRAM applications allocate 1/9th of the memory array (i.e., one “error bit” per eight “data bits”) for error
detection (either simple parity error detection, or system-level ECC error detection and correction). Such error-bit allocation is
unnecessary with ECCRAMs; the entire memory array can be utilized for data storage, effectively providing 12.5% greater storage
capacity compared to SRAMs of the same density not equipped with on-chip ECC.
Input Timing
These devices utilize three pairs of positive and negative input clocks, CK & CK and KD[1:0] & KD[1:0], to latch the various
synchronous inputs. Specifically:
CK latches all address (SA) inputs.
CK latches all control (R, W) inputs.
KD[1:0] and KD[1:0] latch particular write data (D) inputs, as follows:
• KD0 and KD0 latch D[17:0] in x36, and D[8:0] in x18.
• KD1 and KD1 latch D[35:18] in x36, and D[17:9] in x18.
Output Timing
These devices provide two pairs of positive and negative output clocks (aka “echo clocks”), CQ[1:0] & CQ[1:0], whose timing is
tightly aligned with read data in order to enable reliable source-synchronous data transmission.
Output timing is generated by CK and CK, as follows:
• CK generates CQ[1:0], CQ[1:0], Q1 active, and Q2 inactive.
• . CK generates CQ[1:0], CQ[1:0], Q1 inactive, Q2 active, and QVLD active/inactive.
Note: Q1 and Q2 indicate the first and second pieces of read data transferred in any given clock cycle during Read operations.
CQ[1:0] and CQ[1:0] align with particular read data (Q) and read data valid (QVLD) outputs, as follows:
• CQ0 and CQ0 align with Q[17:0], QVLD0 in x36, and with Q[8:0], QVLD0 in x18.
• CQ1 and CQ1 align with Q[35:18], QLVD1 in x36, and with Q[17:9], QVLD1 in x18.
Rev: 1.04 6/2015
7/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
Driver Impedance Control
Programmable Driver Impedance is implemented on the following output signals:
• CQ, CQ, Q, QVLD.
Driver impedance is programmed by connecting an external resistor RQ between the ZQ pin and VSS.
Driver impedance is set to the programmed value within 160K cycles after input clocks are operating within specification and RST
is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system.
Output Signal
Pull-Down Impedance (ROUTL)
Pull-Up Impedance (ROUTH)
CQ, CQ, Q, QVLD
RQ*0.2  15%
RQ*0.2  15%
Notes:
1. ROUTL and ROUTH apply when 175 RQ  225.
2. The mismatch between ROUTL and ROUTH is less than 10%, guaranteed by design.
ODT Impedance Control
Programmable ODT Impedance is implemented on the following input signals:
• CK, CK, KD, KD, SA, R, W, D.
ODT impedance is programmed by connecting an external resistor RT between the ZT pin and VSS.
ODT impedance is set to the programmed value within 160K cycles after input clocks are operating within specification and RST
is de-asserted Low. It is updated periodically thereafter to compensate for temperature and voltage fluctuations in the system
Input Signal
CK, CK, KD, KD
PZT[1:0]
MZT[1:0]
Pull-Down Impedance (RINL)
Pull-Up Impedance (RINH)
X0
XX
disabled
disabled
01
RT  15%
RT  15%
10
RT*2  20%
RT*2  20%
XX
disabled
disabled
01
RT  15%
RT  15%
10
RT*2  20%
RT*2  20%
01
RT  15%
RT  15%
10
RT*2  20%
RT*2  20%
X1
0X
SA, R, W
D
1X
XX
Notes:
1. When MZT[1:0] = 00, ODT is disabled on all inputs. MZT[1:0] = 11 is reserved for future use.
2. RINL and RINH apply when 105 RT  135
3. The mismatch between RINL and RINH is less than 10%, guaranteed by design.
4. All ODT is disabled during JTAG EXTEST and SAMPLE-Z instructions.
Note: When ODT impedance is enabled on a particular input, that input should always be driven High or Low; it should never be
tri-stated (i.e., in a High- Z state). If the input is tri-stated, the ODT will pull the signal to VDDQ / 2 (i.e., to the switch point of the
diff-amp receiver), which could cause the receiver to enter a meta-stable state and consume more power than it normally would.
This could result in the device’s operating currents being higher.
Rev: 1.04 6/2015
8/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
Truth Table
Previous
Operation
SA
R
W
Current Operation
D
Q
(tn–1)
CK
(tn)
CK
(tn)
CK
(tn)
(tn)
KD
(tn+1)
KD
(tn+1½)
KD
(tn+2)
KD
(tn+2½)
NOP
X
1
1
NOP
X
X
—
—
Hi-Z / 0
—
Write
X
1
X
NOP
D3
D4
—
—
Hi-Z / 0
—
Read
X
X
1
NOP
X
X
—
—
NOP
V
1
0
Write
D1
D2
D3
D4
Read
V
X
0
Write
D1
D2
D3
D4
Q3
Q4
NOP
V
0
X
Read
X
X
—
—
Q1
Q2
Q3
Q4
Write
V
0
X
Read
D3
D4
—
—
Q1
Q2
Q3
Q4
CQ
(tn+3)
Q3
CQ
(tn+3½)
CQ
(tn+4)
Q4
CQ
(tn+4½)
—
Hi-Z / 0
—
—
Notes:
1. 1 = High; 0 = Low; V = Valid (High or Low); X = Don’t Care.
2. D1, D2, D3, and D4 indicate the first, second, third, and fourth pieces of write data transferred during Write operations.
3. Q1, Q2, Q3, and Q4 indicate the first, second, third, and fourth pieces of read data transferred during Read operations.
4. When D ODT is disabled (MZT[1:0] = 00), Q pins are tri-stated for one cycle in response to NOP and Write commands, 3 cycles after the
command is sampled, except when preceded by a Read command.
5. When D ODT is enabled (MZT[1:0] = 01 or 10), Q pins are driven Low for one cycle in response to NOP and Write commands, 3 cycles
after the command is sampled, except when preceded by a Read command.
Rev: 1.04 6/2015
9/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Rating
Units
Core Supply Voltage
VDD
-0.3 to +1.6
V
I/O Supply Voltage when MVQ = 0
VDDQ
-0.3 to VDD
V
I/O Supply Voltage when MVQ = 1
VDDQ
-0.3 to VDD + 0.3
V
Input Voltage when MVQ = 0
VIN
-0.3 to VDDQ + 0.3 (1.7 max)
V
Input Voltage when MVQ = 1
VIN
-0.3 to VDDQ + 0.3 (2.0 max)
V
Maximum Junction Temperature
TJ
125
C
Storage Temperature
TSTG
-55 to 125
C
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Core Supply Voltage
VDD
1.3
1.35
1.4
V
I/O Supply Voltage - 1.2V nominal when MVQ = 0
VDDQ
1.15
1.2
1.25
V
I/O Supply Voltage - 1.35V nominal when MVQ = 0
VDDQ
1.3
1.35
VDD
V
I/O Supply Voltage - 1.5V nominal when MVQ = 1
VDDQ
1.4
1.5
1.6
V
Commercial Junction Temperature
TJC
0
—
85
C
Industrial Junction Temperature
TJI
-40
—
100
C
Note:
For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
VSS, VDD, VDDQ, VREF, and Inputs.
Power supplies must power down simultaneously, or in the reverse sequence.
Thermal Impedance
Package
JA (C°/W)
Airflow = 0 m/s
 JA (C°/W)
Airflow = 1 m/s
 JA (C°/W)
Airflow = 2 m/s
JB (C°/W)
 JC (C°/W)
FBGA
15.5
13.1
12.1
4.4
0.2
Rev: 1.04 6/2015
10/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
I/O Capacitance
Parameter
Symbol
Min
Max
Units
Notes
Input Capacitance
CIN
—
5.0
pF
1, 3
Output Capacitance
COUT
—
5.5
pF
2, 3
Parameter
Symbol
Min
Max
Units
Notes
DC Input Reference Voltage
VREFdc
0.48 * VDDQ
0.52 * VDDQ
V
—
DC Input High Voltage
VIH1dc
VREF + 0.08
VDDQ + 0.15
V
4
DC Input Low Voltage
VIL1dc
–0.15
VREF – 0.08
V
4
DC Input High Voltage
VIH2dc
0.75 * VDDQ
VDDQ + 0.15
V
5
DC Input Low Voltage
VIL2dc
–0.15
0.25 * VDDQ
V
5
AC Input Reference Voltage
VREFac
0.47 * VDDQ
0.53 * VDDQ
V
1
AC Input High Voltage
VIH1ac
VREF + 0.15
VDDQ + 0.25
V
2, 3, 4
AC Input Low Voltage
VIL1ac
–0.25
VREF – 0.15
V
2, 3, 4
AC Input High Voltage
VIH2ac
VDDQ – 0.2
VDDQ + 0.25
V
2, 5
AC Input Low Voltage
VIL2ac
– 0.25
0.2
V
2, 5
Notes:
1. VIN = VDDQ/2.
2. VOUT = VDDQ/2.
3. TA = 25C, f = 1 MHz.
Input Electrical Characteristics when MVQ = 0
Notes:
1. VREFac is equal to VREFdc plus noise.
2.
VIH max and VIL min apply for pulse widths less than one-quarter of the cycle time.
3.
4.
5.
Input rise and fall times must be a minimum of 1 V/ns, and within 10% of each other.
Applies to: CK, CK, KD, KD, SA, R, W, D.
Applies to: RST, MVQ, MZT, PZT.
Rev: 1.04 6/2015
11/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
Input Electrical Characteristics when MVQ = 1
Parameter
Symbol
Min
Max
Units
Notes
DC Input Reference Voltage
VREFdc
0.47 * VDDQ
0.53 * VDDQ
V
—
DC Input High Voltage
VIH1dc
VREF + 0.1
VDDQ + 0.15
V
4
DC Input Low Voltage
VIL1dc
–0.15
VREF – 0.1
V
4
DC Input High Voltage
VIH2dc
0.75 * VDDQ
VDDQ + 0.15
V
5
DC Input Low Voltage
VIL2dc
–0.15
0.25 * VDDQ
V
5
AC Input Reference Voltage
VREFac
0.46 * VDDQ
0.54 * VDDQ
V
1
AC Input High Voltage
VIH1ac
VREF + 0.2
VDDQ + 0.25
V
2, 3, 4
AC Input Low Voltage
VIL1ac
–0.25
VREF – 0.2
V
2, 3, 4
AC Input High Voltage
VIH2ac
VDDQ – 0.2
VDDQ + 0.25
V
2, 5
AC Input Low Voltage
VIL2ac
–0.25
0.2
V
2, 5
Notes:
1. VREFac is equal to VREFdc plus noise.
2. VIH max and VIL min apply for pulse widths less than one-quarter of the cycle time.
3. Input rise and fall times must be a minimum of 1V/ns, and within 10% of each other.
4. Applies to: CK, CK, KD, KD, SA, R, W, D.
5. Applies to: RST, MVQ, MZT, PZT.
Output Electrical Characteristics
Parameter
Symbol
Min
Max
Units
Notes
DC Output High Voltage
VOHdc
—
VDDQ + 0.15
V
1
DC Output Low Voltage
VOLdc
-0.15
—
V
1
AC Output High Voltage
VOHac
—
VDDQ + 0.25
V
1
AC Output Low Voltage
VOLac
-0.25
—
V
1
Notes:
1. Applies to: CQ, CQ, Q, QVLD.
Rev: 1.04 6/2015
12/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
Leakage Currents
Parameter
Symbol
Min
Max
Units
Notes
ILI1
-2
2
uA
1, 2
ILI2
-20
2
uA
1, 3
ILI3
-2
20
uA
1, 4
ILO
-2
2
uA
5, 6
Input Leakage Current
Output Leakage Current
Notes:
1. VIN = VSS to VDDQ.
2. Applies to: CK, CK, KD, KD, SA, R, W, D when ODT is disabled.
Applies to: MVQ, MZT, PZT, TCK.
3. Applies to: TMS, TDI (weakly pulled up).
4. Applies to: RST (weakly pulled down).
5. VOUT = VSS to VDDQ.
6. Applies to: CQ, CQ, Q, QVLD, TDO.
Operating Currents
Parameter
x18 Operating Current
x36 Operating Current
Symbol
IDD
IDD
Operating
Frequency
@ 1.3V
VDD
@ 1.35V
VDD
@ 1.4V
VDD
Units
725 MHz
2140
2260
2380
mA
625 MHz
1900
2000
2110
mA
550 MHz
1720
1820
1930
mA
725 MHz
3020
3170
3330
mA
625 MHz
2680
2820
2970
mA
550 MHz
2410
2540
2670
mA
Notes:
1. IOUT = 0 mA; VIN = VIH or VIL.
2. Applies at 100% alternating Reads and Writes.
Rev: 1.04 6/2015
13/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
AC Test Conditions for 1.2V nominal VDDQ (MVQ = 0)
Parameter
Symbol
Conditions
Units
Core Supply Voltage
VDD
1.3 to 1.4
V
I/O Supply Voltage
VDDQ
1.15 to 1.25
V
Input Reference Voltage
VREF
0.6
V
Input High Level
VIH
0.9
V
Input Low Level
VIL
0.3
V
Input Rise and Fall Time
—
2.0
V/ns
Input and Output Reference Level
—
0.6
V
Parameter
Symbol
Conditions
Units
Core Supply Voltage
VDD
1.3 to 1.4
V
I/O Supply Voltage
VDDQ
1.4 to 1.6
V
Input Reference Voltage
VREF
0.75
V
Input High Level
VIH
1.25
V
Input Low Level
VIL
0.25
V
Input Rise and Fall Time
—
2.0
V/ns
Input and Output Reference Level
—
0.75
V
Note:
Output Load Conditions RQ = 200. Refer to figure below.
AC Test Conditions for 1.5V nominal VDDQ (MVQ = 1)
Note:
Output Load Conditions RQ = 200. Refer to figure below.
AC Test Output Load
50
Q, CQ
50
VDDQ/2
5 pF
Rev: 1.04 6/2015
14/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
AC Timing Specifications
Parameter
Symbol
Min
Max
Units
Notes
—
ns
1
Input Clock Timing (Met by the IP)
Clk Cycle Time (-725)
Clk Cycle Time (-625)
1.38
tKHKH
1.6
Clk Cycle Time (-550)
1.8
Clk High Pulse Width
tKHKL
0.45
—
cycles
1
Clk Low Pulse Width
tKLKH
0.45
—
cycles
1
Clk High to Clk High
tKHKH
0.45
0.55
cycles
2
Clk High to Write Data Clk High
tKHKDH
-200
200
ps
3
Input Timing (Met by the IP)
Input Valid to Clk High
tIVKH
not specified
—
ps
4
Clk High to Input Hold
tKHIX
not specified
—
ps
4
Input Pulse Width
tIPW
200
—
ps
5
Output Timing (Accounted for by the IP)
Clk High to Data Output Valid / Hold
tKHQV/X
1.0
2.5
ns
6
Clk High to Echo Clock High
tKHCQH
1.0
2.5
ns
7
Echo Clk High to Echo Clk High
tCQHCQH
tKHKH (min) - 50
tKHKH (max) + 50
ps
8, 11
Echo Clk High to Echo Clk High
tCQHCQH
tKHKH (min) - 50
tKHKH (max) + 50
ps
9, 11
Echo Clk High to Data Output Valid / Hold
tCQHQV/X
-150
150
ps
10, 11
Notes:
All parameters are measured from the mid-point of the object signal to the mid-point of the reference signal.
1. Parameters apply to CK, CK, KD, KD.
2. Parameters specifyCK CK and KD KD requirements.
3. Parameters specify CK KD and CK KD requirements.
4. Parameters apply to SA, and are referenced to CK.
Parameters apply to R, W, and are referenced to CK.
Parameters apply to D, and are referenced to KD & KD.
The unspecified setup and hold time requirements for these inputs are met by the IP (via per-pin calibration for the DDR inputs).
5. Parameter applies to SA, R, W, D.
6. Parameters apply to Q and are referenced to CK & CK.
7. Parameters specify CK CQ and CK CQ timing.
8. Parameter specifies CQ CQ timing. tKHKH (min) and tKHKH (max) are the minimum and maximum input delays from CK to CK.
9.
Parameter specifies CQ CQ timing. tKHKH (min) and tKHKH (max) are the minimum and maximum input delays from CK to CK.
10. Parameters apply to Q, QVLD and are referenced to CQ & CQ.
11. Parameters are not tested. They are guaranteed by design, and verified through extensive corner-lot characterization.
Rev: 1.04 6/2015
15/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
Read and Write Timing Diagram
Read
Write
Read
NOP
NOP
Write
Read
Write
Read
Write
NOP
KD
tKHKH
tKHKL tKLKH tKHKH
KD
tIVKH
D
tKHKDH
D21
D22
D23
D24
tKHIX
D41
D42
D43
D44
tIVKH
D61
D62
tKHIX
D63
D64
D81
tKHKDH
CK
tKHKH
tKHKL tKLKH tKHKH
CK
tIVKH tKHIX
SA A1
A2
A3
A4
A5
A6
A7
A8
tIVKH tKHIX
R
W
tKHQV
Q
tKHQX
Q11
Q12
Q13
Q14
Q31
Q32
Q33
Q34
Q51
Q52
Q53
QVLD
tCQHQX
tKHCQH
tCQHQV
tCQHQX
tCQHQX
tCQHQV
tCQHQV
CQ
tCQHCQH
CQ
Rev: 1.04 6/2015
16/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
JTAG Test Mode Description
These devices provide a JTAG Test Access Port (TAP) and Boundary Scan interface using a limited set of IEEE std. 1149.1
functions. This test mode is intended to provide a mechanism for testing the interconnect between master (processor, controller,
etc.), ECCRAM, other components, and the printed circuit board. In conformance with a subset of IEEE std. 1149.1, these devices
contain a TAP Controller and multiple TAP Registers. The TAP Registers consist of one Instruction Register and multiple Data
Registers.
The TAP consists of the following four signals:
Pin
Pin Name
I/O
Description
TCK
Test Clock
I
Induces (clocks) TAP Controller state transitions.
TMS
Test Mode Select
I
Inputs commands to the TAP Controller.
Sampled on the rising edge of TCK.
TDI
Test Data In
I
Inputs data serially to the TAP Registers.
Sampled on the rising edge of TCK.
TDO
Test Data Out
O
Outputs data serially from the TAP Registers.
Driven from the falling edge of TCK.
Concurrent TAP and Normal ECCRAM Operation
According to IEEE std. 1149.1, most public TAP Instructions do not disrupt normal device operation. In these devices, the only
exceptions are EXTEST and SAMPLE-Z. See the Tap Registers section for more information.
Disabling the TAP
When JTAG is not used, TCK should be tied Low to prevent clocking the ECCRAM. TMS and TDI should either be tied High
through a pull-up resistor or left unconnected. TDO should be left unconnected.
JTAG DC Operating Conditions
Parameter
Symbol
Min
Max
Units
Notes
JTAG Input High Voltage
VTIH
0.75 * VDDQ
VDDQ + 0.15
V
1
JTAG Input Low Voltage
VTIL
–0.15
0.25 * VDDQ
V
1
JTAG Output High Voltage
VTOH
VDDQ – 0.2
—
V
2, 3
JTAG Output Low Voltage
VTOL
—
0.2
V
2, 4
Notes:
1. Parameters apply to TCK, TMS, and TDI during JTAG Testing.
2. Parameters apply to TDO during JTAG testing.
3. ITOH = –2.0 mA.
4. ITOL = 2.0 mA.
Rev: 1.04 6/2015
17/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
JTAG AC Timing Specifications
Parameter
Symbol
Min
Max
Units
TCK Cycle Time
tTHTH
50
—
ns
TCK High Pulse Width
tTHTL
20
—
ns
TCK Low Pulse Width
tTLTH
20
—
ns
TMS Setup Time
tMVTH
10
—
ns
TMS Hold Time
tTHMX
10
—
ns
TDI Setup Time
tDVTH
10
—
ns
TDI Hold Time
tTHDX
10
—
ns
Capture Setup Time (Address, Control, Data, Clock)
tCS
10
—
ns
Capture Hold Time (Address, Control, Data, Clock)
tCH
10
—
ns
TCK Low to TDO Valid
tTLQV
—
10
ns
TCK Low to TDO Hold
tTLQX
0
—
ns
JTAG Timing Diagram
tTHTL
tTLTH
tTHTH
TCK
tMVTH tTHMX
TMS
tDVTH tTHDX
TDI
tTLQV
tTLQX
TDO
Rev: 1.04 6/2015
18/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
TAP Controller
The TAP Controller is a 16-state state machine that controls access to the various TAP Registers and executes the operations
associated with each TAP Instruction. State transitions are controlled by TMS and occur on the rising edge of TCK.
The TAP Controller enters the Test-Logic Reset state in one of two ways:
1. At power up.
2. When a logic 1 is applied to TMS for at least 5 consecutive rising edges of TCK.
The TDI input receiver is sampled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.
The TDO output driver is enabled only when the TAP Controller is in either the Shift-IR state or the Shift-DR state.
TAP Controller State Diagram
1
Test-Logic Reset
0
0
Run-Test / Idle
1
Select DR-Scan
1
Select IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
Shift-DR
1
1
Exit1-DR
Exit1-IR
0
0
0
Pause-DR
1
0
Exit2-IR
Update-DR
Rev: 1.04 6/2015
0
19/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
0
1
1
1
0
Pause-IR
1
Exit2-DR
0
Shift-IR
1
1
1
Update-IR
1
0
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
TAP Registers
TAP Registers are serial shift registers that capture serial input data (from TDI) on the rising edge of TCK, and drive serial output
data (to TDO) on the subsequent falling edge of TCK. They are divided into two groups: Instruction Registers (IR), which are
manipulated via the IR states in the TAP Controller, and Data Registers (DR), which are manipulated via the DR states in the TAP
Controller.
Instruction Register (IR - 3 bits)
The Instruction Register stores the various TAP Instructions supported by ECCRAM. It is loaded with the IDCODE instruction
(logic 001) at power-up, and when the TAP Controller is in the Test-Logic Reset and Capture-IR states. It is inserted between TDI
and TDO when the TAP Controller is in the Shift-IR state, at which time it can be loaded with a new instruction. However, newly
loaded instructions are not executed until the TAP Controller has reached the Update-IR state.
The Instruction Register is 3 bits wide, and is encoded as follows:
Code
(2:0)
000
001
Instruction
Description
EXTEST
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between TDI
and TDO when the TAP Controller is in the Shift-DR state.
Also transfers the contents of the Boundary Scan Register associated with all output signals (Q, QVLD,
CQ, CQ) directly to their corresponding output pins. However, newly loaded Boundary Scan Register contents do not appear at the output pins until the TAP Controller has reached the Update-DR state.
Also disables all ODT.
See the Boundary Scan Register description for more information.
IDCODE
Loads a predefined device- and manufacturer-specific identification code into the ID Register when the
TAP Controller is in the Capture-DR state, and inserts the ID Register between TDI and TDO when the
TAP Controller is in the Shift-DR state.
See the ID Register description for more information.
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between TDI
and TDO when the TAP Controller is in the Shift-DR state.
Also disables all ODT.
Also forces Q output drivers to a High-Z state.
See the Boundary Scan Register description for more information.
010
SAMPLE-Z
011
PRIVATE
Reserved for manufacturer use only.
100
SAMPLE
Loads the logic states of all signals composing the ECCRAM I/O ring into the Boundary Scan Register
when the TAP Controller is in the Capture-DR state, and inserts the Boundary Scan Register between TDI
and TDO when the TAP Controller is in the Shift-DR state.
See the Boundary Scan Register description for more information.
101
PRIVATE
Reserved for manufacturer use only.
110
PRIVATE
Reserved for manufacturer use only.
111
BYPASS
Loads a logic 0 into the Bypass Register when the TAP Controller is in the Capture-DR state, and inserts
the Bypass Register between TDI and TDO when the TAP Controller is in the Shift-DR state.
See the Bypass Register description for more information.
Rev: 1.04 6/2015
20/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
Bypass Register (DR - 1 bit)
The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded with a logic
0 when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the Capture-DR state. It is
inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Register and the TAP
Controller is in the Shift-DR state.
ID Register (DR - 32 bits)
The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODE
instruction has been loaded into the Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between
TDI and TDO when the IDCODE instruction has been loaded into the Instruction Register and the TAP Controller is in the
Shift-DR state.
The ID Register is 32 bits wide, and is encoded as follows:
See BSDL Model
(31:12)
GSI ID
(11:1)
Start Bit
(0)
XXXX XXXX XXXX XXXX XXXX
0001 1011 001
1
Bit 0 is the LSB of the ID Register, and Bit 31 is the MSB. When the ID Register is selected, TDI serially shifts data into the MSB,
and the LSB serially shifts data out through TDO.
Boundary Scan Register (DR - 127 bits)
The Boundary Scan Register is equal in length to the number of active signal connections to the ECCRAM (excluding the TAP
pins) plus a number of place holder locations reserved for functional and/or density upgrades. It is loaded with the logic states of all
signals composing the ECCRAM’s I/O ring when the EXTEST, SAMPLE, or SAMPLE-Z instruction has been loaded into the
Instruction Register and the TAP Controller is in the Capture-DR state. It is inserted between TDI and TDO when the EXTEST,
SAMPLE, or SAMPLE-Z instruction has been loaded into the Instruction Register and the TAP Controller is in the Shift-DR state.
Additionally, the contents of the Boundary Scan Register associated with the ECCRAM outputs (Q, QVLD, CQ, CQ) are driven
directly to the corresponding ECCRAM output pins when the EXTEST instruction is selected. However, after the EXTEST
instruction has been selected, any new data loaded into Boundary Scan Register when the TAP Controller is in the Shift-DR state
does not appear at the output pins until the TAP Controller has reached the Update-DR state.
The value captured in the boundary scan register for NU pins is determined by the external pin state while the NC pins are 0
regardless of the external pin state. The value captured in the internal cells is 1.
Output Driver State During EXTEST
EXTEST allows the Internal Cell (Bit 127) in the Boundary Scan Register to control the state of Q drivers. That is, when Bit 127 =
1, Q drivers are enabled (i.e., driving High or Low), and when Bit 127 = 0, Q drivers are disabled (i.e., forced to High-Z state). See
the Boundary Scan Register section for more information.
ODT State During EXTEST and SAMPLE-Z
ODT on all inputs is disabled during EXTEST and SAMPLE-Z.
Rev: 1.04 6/2015
21/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
Boundary Scan Register Bit Order Assignment
The table below depicts the order in which the bits are arranged in the Boundary Scan Register. Bit 1 is the LSB and Bit 127 is the
MSB. When the Boundary Scan Register is selected, TDI serially shifts data into the MSB, and the LSB serially shifts data out
through TDO.
Bit
Pad
Bit
Pad
Bit
Pad
Bit
Pad
Bit
Pad
1
7L
27
10F
53
10U
79
3V
105
3G
2
7K
28
12F
54
13V
80
1V
106
2F
3
9L
29
11G
55
11V
81
4U
107
4F
4
9K
30
13G
56
12W
82
2U
108
1E
5
8J
31
10G
57
10W
83
3T
109
3E
6
7H
32
12G
58
8V
84
1T
110
2D
7
9H
33
11H
59
9U
85
4R
111
4D
8
7G
34
13H
60
8T
86
2R
112
1C
9
8G
35
10J
61
9R
87
3P
113
3C
10
9F
36
12J
62
8P
88
1P
114
2B
11
8E
37
13K
63
9N
89
4P
115
4B
12
7D
38
13L
64
8M
90
2P
116
6A
13
9D
39
11L
65
6M
91
3N
117
6B
14
8C
40
12M
66
7N
92
1N
118
6C
15
8B
41
10M
67
5N
93
4M
119
5D
16
9B
42
13N
68
7P
94
2M
120
6E
17
7A
43
11N
69
6P
95
3L
121
5F
18
9A
44
12P
70
5R
96
1L
122
6G
19
10B
45
10P
71
6T
97
1K
123
5H
20
12B
46
13P
72
7U
98
2J
124
6J
21
11C
47
11P
73
5U
99
4J
125
5K
22
13C
48
12R
74
6V
100
1H
126
5L
23
10D
49
10R
75
6W
101
3H
127
Internal
24
12D
50
13T
76
7Y
102
2G
25
11E
51
11T
77
4W
103
4G
26
13E
52
12U
78
2W
104
1G
Rev: 1.04 6/2015
22/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
260-Pin BGA Package Drawing (Package K)
0.08 S C
0.08 S C A S B S
Ø
Ø
Ø
0.50~Ø0.70(260x)
13 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
19.00
17.40  0.05
22.00  0.05
1.00
PIN #1 CORNER
12.60  0.05
B
A
1.00
14.00  0.05
12.00
Rev: 1.04 6/2015
C
0.15
0.05
SEATING PLANE
0.40~0.60
0.51 REF
C
4–R0.5 (MAX)
0.50 + 0.03
0.10
HEAT SPREADER
//
1.09 REF
C
2.10 + 0.2/–0.3
0.05(4X)
Ball Pitch:
1.00 Substrate Thickness:
Ball Diameter:
0.60 Mold Thickness:
0.51
—
23/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
Ordering Information — GSI SigmaQuad-IIIe ECCRAMs
Org
Part Number
Type
Package
Speed
(MHz)
TA
4M x 18
GS8673ED18BK-725S
SigmaQuad-IIIe B4
260 Pin BGA
725
C
4M x 18
GS8673ED18BK-625S
SigmaQuad-IIIe B4
260 Pin BGA
625
C
4M x 18
GS8673ED18BK-550S
SigmaQuad-IIIe B4
260 Pin BGA
550
C
4M x 18
GS8673ED18BK-725IS
SigmaQuad-IIIe B4
260 Pin BGA
725
I
4M x 18
GS8673ED18BK-625IS
SigmaQuad-IIIe B4
260 Pin BGA
625
I
4M x 18
GS8673ED18BK-550IS
SigmaQuad-IIIe B4
260 Pin BGA
550
I
2M x 36
GS8673ED36BK-725S
SigmaQuad-IIIe B4
260 Pin BGA
725
C
2M x 36
GS8673ED36BK-625S
SigmaQuad-IIIe B4
260 Pin BGA
625
C
2M x 36
GS8673ED36BK-550S
SigmaQuad-IIIe B4
260 Pin BGA
550
C
2M x 36
GS8673ED36BK-725IS
SigmaQuad-IIIe B4
260 Pin BGA
725
I
2M x 36
GS8673ED36BK-625IS
SigmaQuad-IIIe B4
260 Pin BGA
625
I
2M x 36
GS8673ED36BK-550IS
SigmaQuad-IIIe B4
260 Pin BGA
550
I
4M x 18
GS8673ED18BGK-725S
SigmaQuad-IIIe B4
RoHS-compliant 260 Pin BGA
725
C
4M x 18
GS8673ED18BGK-625S
SigmaQuad-IIIe B4
RoHS-compliant 260 Pin BGA
625
C
4M x 18
GS8673ED18BGK-550S
SigmaQuad-IIIe B4
RoHS-compliant 260 Pin BGA
550
C
4M x 18
GS8673ED18BGK-725IS
SigmaQuad-IIIe B4
RoHS-compliant 260 Pin BGA
725
I
4M x 18
GS8673ED18BGK-625IS
SigmaQuad-IIIe B4
RoHS-compliant 260 Pin BGA
625
I
4M x 18
GS8673ED18BGK-550IS
SigmaQuad-IIIe B4
RoHS-compliant 260 Pin BGA
550
I
2M x 36
GS8673ED36BGK-725S
SigmaQuad-IIIe B4
RoHS-compliant 260 Pin BGA
725
C
2M x 36
GS8673ED36BGK-625S
SigmaQuad-IIIe B4
RoHS-compliant 260 Pin BGA
625
C
2M x 36
GS8673ED36BGK-550S
SigmaQuad-IIIe B4
RoHS-compliant 260 Pin BGA
550
C
2M x 36
GS8673ED36BGK-725IS
SigmaQuad-IIIe B4
RoHS-compliant 260 Pin BGA
725
I
2M x 36
GS8673ED36BGK-625IS
SigmaQuad-IIIe B4
RoHS-compliant 260 Pin BGA
625
I
2M x 36
GS8673ED36BGK-550IS
SigmaQuad-IIIe B4
RoHS-compliant 260 Pin BGA
550
I
Note: C = Commercial Temperature Range. I = Industrial Temperature Range.
Rev: 1.04 6/2015
24/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS8673ED18/36BK-725S/625S/550S
Revision History
Rev. Code
Types of Changes
Format or Content
GS8673ED1836BK_r1
Revisions
Creation of new datasheet
GS8673ED1836BK_r1_01
Content
Corrected P/Ns for Industrial Temp Range (“I” before “S”)
GS8673ED1836BK_r1_02
Content
Redefined pin 5B from MCH to MVQ.
Added support for VDDQ = 1.2V (requires MVQ = 0).
GS8673ED1836BK_r1_03
Content
Redefined pins 3L, 11L from DNUO to QVLD1, QVLD0.
Redefined pins 9A, 9B from MCH to PZT1, PZT0.
Redefined pins 7G, 7P from MCL, MCH to MZT1, MZT0.
Added support for VDDQ = 1.35V (requires MVQ = 0).
Updated Power-Up and Reset Requirements section.
GS8673ED1836BK_r1_04
Content
Corrected write data input latency in the timing diagram.
Rev: 1.04 6/2015
25/25
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
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