Data Sheet

PDTA113Z series
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
Rev. 04 — 2 September 2009
Product data sheet
1. Product profile
1.1 General description
PNP resistor-equipped transistors.
Table 1.
Product overview
Type number
Package
NPN complement
NXP
JEITA
PDTA113ZE
SOT416
SC-75
PDTC113ZE
PDTA113ZK
SOT346
SC-59
PDTC113ZK
PDTA113ZM
SOT883
SC-101
PDTC113ZM
PDTA113ZS[1]
SOT54 (TO-92)
SC-43A
PDTC113ZS
PDTA113ZT
SOT23
-
PDTC113ZT
PDTA113ZU
SOT323
SC-70
PDTC113ZU
[1]
Also available in SOT54A and SOT54 variant packages (see Section 2).
1.2 Features
n Built-in bias resistors
n Simplifies circuit design
n Reduces component count
n Reduces pick and place costs
1.3 Applications
n General purpose switching and
amplification
n Inverter and interface circuits
n Circuit drivers
1.4 Quick reference data
Table 2.
Quick reference data
Symbol
Parameter
Conditions
VCEO
collector-emitter voltage
open base
IO
output current (DC)
R1
bias resistor 1 (input)
R2/R1
bias resistor ratio
Min
Typ
Max
Unit
-
-
−50
V
-
-
−100
mA
0.7
1
1.3
kΩ
8
10
12
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
2. Pinning information
Table 3.
Pinning
Pin
Description
Simplified outline
Symbol
SOT54
1
input (base)
2
output (collector)
3
GND (emitter)
2
R1
1
2
3
1
R2
001aab347
3
006aaa148
SOT54A
1
input (base)
2
output (collector)
3
GND (emitter)
2
R1
1
2
1
R2
3
001aab348
3
006aaa148
SOT54 variant
1
input (base)
2
output (collector)
3
GND (emitter)
2
R1
1
2
3
1
R2
001aab447
3
006aaa148
SOT23, SOT323, SOT346, SOT416
1
input (base)
2
GND (emitter)
3
3
3
R1
output (collector)
1
R2
1
2
2
006aaa144
sym003
SOT883
1
input (base)
2
GND (emitter)
3
output (collector)
1
3
3
2
R1
1
Transparent
top view
R2
2
sym003
PDTA113Z_SER_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
2 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
3. Ordering information
Table 4.
Ordering information
Type number
Package
Name
Description
Version
PDTA113ZE
SC-75
plastic surface mounted package; 3 leads
SOT416
PDTA113ZK
SC-59
plastic surface mounted package; 3 leads
SOT346
PDTA113ZM
SC-101
leadless ultra small plastic package; 3 solder lands;
body 1.0 × 0.6 × 0.5 mm
SOT883
PDTA113ZS[1]
SC-43A
plastic-single-ended leaded (through hole) package; SOT54
3 leads
PDTA113ZT
-
plastic surface mounted package; 3 leads
SOT23
PDTA113ZU
SC-70
plastic surface mounted package; 3 leads
SOT323
[1]
Also available in SOT54A and SOT54 variant packages (see Section 2 and Section 9)
4. Marking
Table 5.
Marking codes
Type number
Marking code[1]
PDTA113ZE
15
PDTA113ZK
27
PDTA113ZM
G3
PDTA113ZS
TA113Z
PDTA113ZT
*AM
PDTA113ZU
*16
[1]
* = -: made in Hong Kong
* = p: made in Hong Kong
* = t: made in Malaysia
* = W: made in China
PDTA113Z_SER_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
3 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
5. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
VCBO
collector-base voltage
open emitter
-
−50
V
VCEO
collector-emitter voltage
open base
-
−50
V
VEBO
emitter-base voltage
open collector
-
−5
V
VI
input voltage
positive
-
+5
V
negative
-
−10
V
IO
output current (DC)
-
−100
mA
ICM
peak collector current
-
−100
mA
Ptot
total power dissipation
Tamb ≤ 25 °C
SOT416
[1]
-
150
mW
SOT346
[1]
-
250
mW
SOT883
[2][3]
-
250
mW
SOT54
[1]
-
500
mW
SOT23
[1]
-
250
mW
SOT323
[1]
-
200
mW
Tstg
storage temperature
−65
+150
°C
Tj
junction temperature
-
150
°C
Tamb
ambient temperature
−65
+150
°C
[1]
Refer to standard mounting conditions.
[2]
Reflow soldering is the only recommended soldering method.
[3]
Refer to SOT883 standard mounting conditions; FR4 printed-circuit board with 60 µm copper strip line.
6. Thermal characteristics
Table 7.
Thermal characteristics
Symbol
Parameter
Conditions
Rth(j-a)
thermal resistance from
junction to ambient
in free air
Typ
Max
Unit
SOT416
[1]
-
-
833
K/W
SOT346
[1]
-
-
500
K/W
SOT883
[2][3]
-
-
500
K/W
SOT54
[1]
-
-
250
K/W
SOT23
[1]
-
-
500
K/W
SOT323
[1]
-
-
625
K/W
[1]
Refer to standard mounting conditions.
[2]
Reflow soldering is the only recommended soldering method.
[3]
Refer to SOT883 standard mounting conditions; FR4 printed-circuit board with 60 µm copper strip line.
PDTA113Z_SER_4
Product data sheet
Min
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
4 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
7. Characteristics
Table 8.
Characteristics
Tamb = 25 °C unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ICBO
collector-base cut-off
current
VCB = −50 V; IE = 0 A
-
-
−100
nA
ICEO
collector-emitter
cut-off current
VCE = −30 V; IB = 0 A
-
-
−1
µA
VCE = −30 V; IB = 0 A;
Tj = 150 °C
-
-
−50
µA
µA
IEBO
emitter-base cut-off
current
VEB = −5 V; IC = 0 A
-
-
−800
hFE
DC current gain
VCE = −5 V; IC = −5 mA
35
-
-
VCEsat
collector-emitter
saturation voltage
IC = −10 mA; IB = −0.5 mA
-
-
−150
mV
VI(off)
off-state input voltage
VCE = −5 V; IC = −100 µA
-
−0.65
−0.3
V
VI(on)
on-state input voltage
VCE = −300 mV; IC = −20 mA
−2.5
−0.95
-
V
R1
bias resistor 1 (input)
0.7
1
1.3
kΩ
R2/R1
bias resistor ratio
8
10
12
Cc
collector capacitance
-
-
2
VCB = −10 V; IE = ie = 0 A;
f = 1 MHz
PDTA113Z_SER_4
Product data sheet
pF
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
5 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
006aaa107
103
006aaa108
−1
hFE
(2)
102
(1)
VCEsat
(V)
(3)
−10−1
(1)
(2)
10
(3)
1
−10−1
−1
−10
−102
−10−2
−1
−102
−10
I C (mA)
I C (mA)
VCE = −5 V
IC/IB = 20
(1) Tamb = 100 °C
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(2) Tamb = 25 °C
(3) Tamb = −40 °C
(3) Tamb = −40 °C
Fig 1.
DC current gain as a function of collector
current; typical values
006aaa109
−10
Fig 2.
Collector-emitter saturation voltage as a
function of collector current; typical values
006aaa110
−10
VI(off)
(V)
VI(on)
(V)
−1
−1
(1)
(1)
(2)
(2)
(3)
(3)
−10−1
−10−1
−1
−10
−102
−10−1
−10−1
I C (mA)
VCE = −0.3 V
VCE = −5 V
(1) Tamb = −40 °C
(2) Tamb = 25 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
(3) Tamb = 100 °C
On-state input voltage as a function of
collector current; typical values
Fig 4.
Off-state input voltage as a function of
collector current; typical values
PDTA113Z_SER_4
Product data sheet
−10
I C (mA)
(1) Tamb = −40 °C
Fig 3.
−1
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
6 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
8. Package outline
Plastic surface-mounted package; 3 leads
SOT416
D
E
B
A
X
HE
v M A
3
Q
A
1
A1
2
e1
c
bp
w M B
Lp
e
detail X
0
0.5
1 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E
e
e1
HE
Lp
Q
v
w
mm
0.95
0.60
0.1
0.30
0.15
0.25
0.10
1.8
1.4
0.9
0.7
1
0.5
1.75
1.45
0.45
0.15
0.23
0.13
0.2
0.2
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
SOT416
Fig 5.
JEITA
SC-75
EUROPEAN
PROJECTION
ISSUE DATE
04-11-04
06-03-16
Package outline SOT416 (SC-75)
PDTA113Z_SER_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
7 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
Plastic surface-mounted package; 3 leads
SOT346
E
D
A
B
X
HE
v M A
3
Q
A
A1
1
c
2
e1
bp
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
bp
c
D
E
e
e1
HE
Lp
Q
v
w
mm
1.3
1.0
0.1
0.013
0.50
0.35
0.26
0.10
3.1
2.7
1.7
1.3
1.9
0.95
3.0
2.5
0.6
0.2
0.33
0.23
0.2
0.2
OUTLINE
VERSION
SOT346
Fig 6.
REFERENCES
IEC
JEDEC
JEITA
TO-236
SC-59A
EUROPEAN
PROJECTION
ISSUE DATE
04-11-11
06-03-16
Package outline SOT346 (SC-59/TO-236)
PDTA113Z_SER_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
8 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
Leadless ultra small plastic package; 3 solder lands; body 1.0 x 0.6 x 0.5 mm
L
SOT883
L1
2
b
3
e
b1
1
e1
A
A1
E
D
0
0.5
1 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A (1)
A1
max.
b
b1
D
E
e
e1
L
L1
mm
0.50
0.46
0.03
0.20
0.12
0.55
0.47
0.62
0.55
1.02
0.95
0.35
0.65
0.30
0.22
0.30
0.22
Note
1. Including plating thickness
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
SOT883
Fig 7.
JEITA
SC-101
EUROPEAN
PROJECTION
ISSUE DATE
03-02-05
03-04-03
Package outline SOT883 (SC-101)
PDTA113Z_SER_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
9 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
Plastic single-ended leaded (through hole) package; 3 leads
SOT54
c
E
d
A
L
b
1
e1
2
D
e
3
b1
L1
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
b
b1
c
D
d
E
mm
5.2
5.0
0.48
0.40
0.66
0.55
0.45
0.38
4.8
4.4
1.7
1.4
4.2
3.6
e
2.54
e1
L
L1(1)
1.27
14.5
12.7
2.5
max.
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
SOT54
Fig 8.
REFERENCES
IEC
JEDEC
JEITA
TO-92
SC-43A
EUROPEAN
PROJECTION
ISSUE DATE
04-06-28
04-11-16
Package outline SOT54 (SC-43A/TO-92)
PDTA113Z_SER_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
10 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
Plastic single-ended leaded (through hole) package; 3 leads (wide pitch)
SOT54A
c
E
A
L
d
L2
b
1
e1
e
D
2
3
b1
L1
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
b
b1
c
D
d
E
e
e1
L
L1(1)
mm
5.2
5.0
0.48
0.40
0.66
0.55
0.45
0.38
4.8
4.4
1.7
1.4
4.2
3.6
5.08
2.54
14.5
12.7
3
max.
L2
3
2
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
ISSUE DATE
97-05-13
04-06-28
SOT54A
Fig 9.
EUROPEAN
PROJECTION
Package outline SOT54A
PDTA113Z_SER_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
11 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
Plastic single-ended leaded (through hole) package; 3 leads (on-circle)
SOT54 variant
c
e1
L2
E
d
A
L
b
1
e1
2
e
D
3
b1
L1
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
b
b1
c
D
d
E
e
e1
L
L1(1)
max
L2
max
mm
5.2
5.0
0.48
0.40
0.66
0.55
0.45
0.38
4.8
4.4
1.7
1.4
4.2
3.6
2.54
1.27
14.5
12.7
2.5
2.5
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-06-28
05-01-10
SOT54 variant
Fig 10. Package outline SOT54 variant
PDTA113Z_SER_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
12 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
Plastic surface-mounted package; 3 leads
SOT23
D
E
B
A
X
HE
v M A
3
Q
A
A1
1
2
e1
bp
c
w M B
Lp
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max.
bp
c
D
E
e
e1
HE
Lp
Q
v
w
mm
1.1
0.9
0.1
0.48
0.38
0.15
0.09
3.0
2.8
1.4
1.2
1.9
0.95
2.5
2.1
0.45
0.15
0.55
0.45
0.2
0.1
OUTLINE
VERSION
SOT23
REFERENCES
IEC
JEDEC
JEITA
TO-236AB
EUROPEAN
PROJECTION
ISSUE DATE
04-11-04
06-03-16
Fig 11. Package outline SOT23 (TO-236AB)
PDTA113Z_SER_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
13 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
Plastic surface-mounted package; 3 leads
SOT323
D
E
B
A
X
HE
y
v M A
3
Q
A
A1
c
1
2
e1
bp
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E
e
e1
HE
Lp
Q
v
w
mm
1.1
0.8
0.1
0.4
0.3
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.23
0.13
0.2
0.2
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
SOT323
JEITA
SC-70
EUROPEAN
PROJECTION
ISSUE DATE
04-11-04
06-03-16
Fig 12. Package outline SOT323 (SC-70)
PDTA113Z_SER_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
14 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
9. Packing information
Table 9.
Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code. [1]
Type number
Package
Description
Packing quantity
3000
5000
10000
PDTA113ZE
SOT416
4 mm pitch, 8 mm tape and reel
-115
-
-135
PDTA113ZK
SOT346
4 mm pitch, 8 mm tape and reel
-115
-
-135
PDTA113ZM
SOT883
2 mm pitch, 8 mm tape and reel
-
-
-315
PDTA113ZS
SOT54
bulk, straight leads
-
-412
-
SOT54A
tape and reel, wide pitch
-
-
-116
SOT54A
tape ammopack, wide patch
-
-
-126
SOT54 variant
bulk, delta pinning
-
-112
-
PDTA113ZT
SOT23
4 mm pitch, 8 mm tape and reel
-215
-
-235
PDTA113ZU
SOT323
4 mm pitch, 8 mm tape and reel
-115
-
-135
[1]
For further information and the availability of packing methods, see Section 12.
PDTA113Z_SER_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
15 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
10. Revision history
Table 10.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PDTA113Z_SER_4
20090902
Product data sheet
-
PDTA113Z_SER_3
Modifications:
•
This data sheet was changed to reflect the new company name NXP Semiconductors,
including new legal definitions and disclaimers. No changes were made to the technical
content.
•
•
•
•
Figure 5 “Package outline SOT416 (SC-75)”: updated
Figure 6 “Package outline SOT346 (SC-59/TO-236)”: updated
Figure 11 “Package outline SOT23 (TO-236AB)”. updated
Figure 12 “Package outline SOT323 (SC-70)”: updated
PDTA113Z_SER_3
20050407
Product data sheet
-
PDTA113ZT_2
PDTA113ZT_2
20040518
Objective data sheet
-
PDTA113ZT_1
PDTA113ZT_1
20040325
Objective data sheet
-
-
PDTA113Z_SER_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
16 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
11. Legal information
11.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
11.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
11.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
11.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
12. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PDTA113Z_SER_4
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 04 — 2 September 2009
17 of 18
PDTA113Z series
NXP Semiconductors
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 10 kΩ
13. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
10
11
11.1
11.2
11.3
11.4
12
13
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
Packing information. . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 2 September 2009
Document identifier: PDTA113Z_SER_4