A8302 Datasheet

A8302
Dual LNB Supply and Control Voltage Regulators
Features and Benefits
Description
▪Integrated boost MOSFET, current sensing, and
compensation
▪Configurable boost capacitor option through I2C™ control
register: ceramic or electrolytic
▪Two switching frequency settings programmable through
I2C™ control register (563 kHz and 939 kHz)
▪Adjustable LNB output current limit from 250 to 950 mA
▫ Covers a wide array of application requirements
▫ Minimizes component sizing to fit each application
▫ For startup, reconfiguration, and continuous output
▫ Optional temporary increased current limit (+25%)
▫ Internal gate drive output BFGATEx for bypass FET used
in DiSEqC™ applications
The A8302 is a dual channel low noise block converter regulator
(LNBR). The A8302 consists of a monolithic linear and
switching voltage regulator, specifically designed to provide
the power and the interface signals to an LNB down converter
via coaxial cable in satellite TV receivers systems. The A8302
requires few external components, with the boost switch and
compensation circuitry integrated inside of the device. The boost
converter switching frequency and user-controlled current limit
minimize the size of the passive filtering components. User
controlled current limit and two switching frequency settings
allow to optimize size of passive filtering components.
A sleep pin is available to maximize power savings and to
quickly shut down the device if needed, without using I2C™
control.
Continued on the next page…
The A8302 has integrated tone detection capability
and the internal driver allows full two-way DiSEqC™
communications. For DiSEqC™ communication, the IC
provides an internal 22-kHz tone that is gated with the
TONECTRLx pin or accepts an external 22-kHz tone through
the TONECTRLx pin.
Package: 32-contact MLP/QFN with
exposed thermal pad (suffix ET)
Continued on the next page…
5 mm × 5 mm × 0.90 mm
Functional Block Diagram
(One of two channels shown, x in pin name indicates channel: 1 or 2)
GNDLXx
LXx BOOSTx
VCPx
VIN
VFB
Boost
Regulator
CLK
VREG
IC
Power
563/939
kHz Osc
BOOSTREF
0.8 V
Charge
Pump
+
SLEEP
Ref
DAC
Slew
Rate
Limiter
TCAPx
TONECTRLx
IRQ
LNBx
ISETx
Unlatched
Status
PNG, CPOK
EPF & TDET
2
IC
Interface
Read
Fault
TDOx
VIN
Linear
Regulator
ILIM OC
Tone
Generator
TMODE
VSEL3-0
ADD
LNBREF
4
SDA
SCL
+
SET Latched Faults:
UVLO
RST Latched or Autorestart Faults:
OCP and TSD
EPF_TH
EPF
TDIS_T
TSD
VIN
OC Timer
45/28 ms
RS MODE
ADJ
Tone
TDET Detector
TDIx
10 kΩ
LNBx
BFGATEx
10 kΩ
100 kΩ
GND
8302-DS
A8302
Dual LNB Supply and Control Voltage Regulators
Features and Benefits (continued)
▪Boost peak current limit scales with LNB current limit setting
▪Early Power Failure (EPF) warning
▪SINK_DIS bit to control maximum output reverse current
▪8 programmable LNB output voltage (DAC) levels
▪LNB overcurrent limit protection and TSD with autorestart or latched
▪LNB transition times configurable by external capacitor
▪Built-in 22-kHz tone oscillator facilitates DiSEqC™ tone
encoding
▫ Tone generation does not require additional external
components
▪Diagnostic features: PNGx,TDETx, BOOSTxH and EPF
▪Dynamic tone detect amplitude and frequency
transmit/receive thresholds
▪Extensive protection features: UVLO, TSD, OCPx, and CPOKx
▪Sleep mode with shutdown current < 15 µA (typ)
Description (continued)
The A8302 offers Early Power Failure (EPF) warning, which helps
to initiate shutdown routines. The A8302 maximum output reverse
current can be set using the SINK_DIS bit.
A comprehensive set of fault registers are provided, which comply
with all the common standards, including: overcurrent, thermal
shutdown, undervoltage, and power not good.
The device uses a 2-wire bidirectional serial interface, compatible
with the I2C™ standard, that operates up to 400 kHz.
The A8302 is supplied in a 5 mm × 5 mm, 32-contact, lead (Pb) free
QFN package (suffix ET), with 100% matte tin plated leadframe.
Selection Guide
Part Number
A8302SETTR-T2
Packing1
Description
7 in. reel,
1500 pieces/reel
12 mm carrier tape
ET package, QFN surface mount
5 mm × 5 mm × 0.90 mm nominal height
1Contact Allegro for additional packing
2Leadframe plating 100% matte tin.
options.
Absolute Maximum Ratings
Characteristic
Symbol
Rating
Unit
25
Internally
Limited
–0.3 to 43
V
–1.0 to 43
V
LXx Pin
–0.3 to 30
V
VCPx Pin
–0.3 to 48
V
Logic Input Voltage
–0.3 to 5.5
V
Logic Output Voltage
–0.3 to 5.5
V
EPF and VREG Pins
–0.3 to 6
V
–20 to 85
°C
Load Supply Voltage, VIN Pin
VIN
Output Current1
IOUT
Conditions
Output Voltage; BOOSTx and BFGATEx Pins
LNBx Pin2
Operating Ambient Temperature
Surge
TA
Range S; TA(max) depends on thermal design;
overriding factor is TJ(max)
A
V
Junction Temperature
TJ(max)
150
°C
Storage Temperature
Tstg
–55 to 150
°C
1Output
current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the
specified current ratings, or a junction temperature, TJ, of 150°C.
2See application schematics 3 and 4 on pages 38 and 40.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A8302
Dual LNB Supply and Control Voltage Regulators
Thermal Characteristics may require derating at maximum conditions
Characteristic
Symbol
Package Thermal Resistance
RθJA
Test Conditions*
4-layer PCB based on JEDEC standard
Value
Unit
30
ºC/W
*Additional thermal information available on the Allegro website
Table of Contents
Specifications
Absolute Maximum Ratings
Thermal Characteristics
Pin-Out and Terminal List
Electrical Characteristics
Functional Description
Boost Converter/Linear Regulator
Boost Converter Operation Under Light Load
Multiple Outputs
Charge Pump
LNBx and BOOSTx Current Limits Setting
Protection Undervoltage Lockout (UVLO)
Overload and Short Circuit Handling Switching Frequency Selection
Compensation Network Selection
Pull-Down Rate Thermal Shutdown (TSD) SINK_DIS Mode Selection Sleep Mode In-Rush Current Tone Generation
Tone Detection
Early Power Failure Warning (EPF) 2
2
3
4
5
9
9
9
10
10
10
10
10
10
13
13
13
15
15
15
15
15
15
16
Component Selection
17
Boost Ceramic Capacitor Option
17
Boost Electrolytic Capacitor Option
18
BOOSTx Filtering and LNBx Noise
18
Surge Components
18
I2C™-Compatible Interface
19
SDA and SCL Signals
19
Acknowledge (AK) Bit 19
Acknowledge Bit During a Write Sequence
19
Acknowledge Bit During a Read Sequence
19
I2C™ Communications 19
I2C™ Start and Stop Conditions
19
I2C™ Write Sequence Description
20
I2C™ Read Sequence Description 20
Interrupt Request (¯¯
I ¯R̄¯Q̄¯ ) Pin
20
UVLO Timing Diagrams
22
I2C Timing
26
Control Registers (I2C™-Compatible Write Register) 29
Status Registers (I2C™-Compatible Read Register) 31
Application Information
Application Schematics
Package Outline Diagram
34
34
42
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A8302
32
31
30
29
28
27
26
25
BOOST1
GNDLX1
LX1
VIN
GND
EPF
TDO1
TDO2
Dual LNB Supply and Control Voltage Regulators
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PAD
VREG
SLEEP
TCAP2
TCAP1
ISET2
ISET1
TONECTRL2
TONECTRL1
BOOST2
GNDLX2
LX2
NC
SCL
SDA
ADD
IRQ
9
10
11
12
13
14
15
16
Pin-out Diagram
VCP1
LNB1
BFGATE1
TDI1
TDI2
BFGATE2
LNB2
VCP2
Terminal List Table
Number
Name
1
VCP1
Channel 1 gate supply voltage
Function
Channel 1 output voltage to LNB
2
LNB1
3
BFGATE1
4
TDI1
Channel 1 Tone Detect input
Channel 2 Tone Detect input
Channel 1 gate driver point for the external P-channel bypass MOSFET
5
TDI2
6
BFGATE2
7
LNB2
Channel 2 output voltage to LNB
8
VCP2
Channel 2 gate supply voltage
Channel 2 gate driver point for the external P-channel bypass MOSFET
9
BOOST2
Tracking supply voltage to channel 2 linear regulator
10
GNDLX2
Channel 2 boost switch ground
11
LX2
Channel 2 internal boost switch drain node
12
NC
No connect
13
SCL
I2C-compatible clock input
14
SDA
I2C-compatible data input/output
15
ADD
Address select
16
¯¯I ¯R̄¯Q̄¯
Interrupt request output
17
TONECONTRL1 Apply a 22-kHz tone or tone on-and-off signal to enable/disable internal tone of channel1
18
TONECONTRL2 Apply a 22-kHz tone or tone on-and-off signal to enable/disable internal tone of channel2
19
ISET1
Terminal for external resistor that sets the LNB1 current limit
20
ISET2
Terminal for external resistor that sets the LNB2 current limit
21
TCAP1
Capacitor for setting the rise and fall time of the LNB1 output
22
Capacitor for setting the rise and fall time of the LNB2 output
23
TCAP2
S̄¯ L̄¯ Ē¯ Ē¯ P̄¯ Disables LNB output, boost, I2C communication, and charge pump, to reduce input quiescent current to <15 µA
24
VREG
Analog supply
25
TDO2
Open-drain logic output that transitions high when a 22-kHz tone is present at the TDI2 pin
26
TDO1
Open-drain logic output that transitions high when a 22-kHz tone is present at the TDI1 pin
27
EPF
Early Power Failure warning comparator output
28
GND
Signal ground
29
VIN
Input supply voltage
30
LX1
Channel 1 internal boost switch drain node
31
GNDLX1
Channel 1 boost switch ground
32
BOOST1
Tracking supply voltage to channel 1 linear regulator
–
PAD
Exposed pad for thermal dissipation; connect to the ground plane
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A8302
Dual LNB Supply and Control Voltage Regulators
ELECTRICAL CHARACTERISTICS1
Characteristic
at TA = 25°C, VIN = 10 to 16 V,
Symbol
as noted2; unless noted otherwise
Test Conditions
Min.
Typ.
Max.
Unit
VIN = 12 V, IOUTx = 10 mA, see table 3a for
DAC settings
–2
–
2
%
VIN = 12 V, VOUTx = 13.667 V,
ΔIOUTx = 10 to 700 mA
–
75
120
mV
VIN = 12 V, VOUTx = 19.000 V,
ΔIOUTx = 10 to 700 mA
–
85
150
mV
VIN = 10 to 16 V, VOUTx = 13.667 V,
IOUTx = 10 mA
–10
0
10
mV
VIN = 10 to 16 V, VOUTx = 19.000 V,
IOUTx = 10 mA
–10
0
10
mV
ENB1 and ENB2 bits = 0, VIN = 12 V
–
7
–
mA
ENB1 and ENB2 bits = 1, VIN = 12 V, VOUTx
= 19 V, ILOAD = 10 mA, TONECTRLx = 0
–
65
–
mA
ENB1 and ENB2 bits = 1, VIN = 12 V, VOUTx
= 19 V, ILOAD = 10 mA, TONECTRLx = 1
–
85
–
mA
¯ P̄
¯ = 0 V, VIN = 12 V, TONECTRLx = 0
S̄¯ L̄¯ Ē¯ Ē
–
–
15
µA
–
300
–
mΩ
FSW bit = 0
507
563
619
kHz
FSW bit = 1
845
939
1032
kHz
General
Output Voltage Accuracy
Load Regulation
Line Regulation
VOUTx
ΔVOUTx(Load)
ΔVOUTx(Line)
IIN(OFF)
Supply Current
Boost Switch On Resistance
Switching Frequency
Minimum COntrollable On-Time
IIN(ON)
RDS(on)BOOST ILOAD = 450 mA
fSW
tON(min)
–
85
–
ns
VBOOSTx – VLNBx, no tone signal,
ILOAD = 700 mA
600
800
1000
mV
ICHGx
TCAP capacitor (CTCAP in application
drawings) charging
–13
–10
–7
µA
IDISCHGx
TCAP capacitor (CTCAP in application
drawings) discharging
7
10
13
µA
Output Voltage Rise Time3
tr(VLNB)
For VLNBx 13 → 19 V; CTCAP (see
application drawings) = 100 nF, ILOADx = 700
mA
–
10
–
ms
Output Voltage Pull-Down Time3
tf(VLNB)
For VLNBx 19 → 13 V; CLOAD = 100 µF,
ILOADx = 0 mA, SINK_DIS bit = 0
–
20
–
ms
Linear Regulator Voltage Drop
TCAPx Pin Current
∆VREGx
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A8302
Dual LNB Supply and Control Voltage Regulators
ELECTRICAL CHARACTERISTICS1 (continued) at TA = 25°C, VIN = 10 to 16 V,
Characteristic
Output Reverse Current
LNBx Off Current
Symbol
IRLNBx
ILNBx(OFF)
as noted2; unless noted otherwise
Min.
Typ.
Max.
Unit
ENBx bit = 0
Test Conditions
–
2
4
mA
SINK_DIS bit = 1, ENBx bit = 1,
TONECTRLx = 0
–
7
10
mA
SINK_DIS bit = 0, ENBx bit = 1,
TONECTRLx = 0,
|VLNBx - VSELx| < 1.5 V
–
25
40
mA
SINK_DIS bit = 0, ENBx bit = 1,
TONECTRLx = 1,
|VLNBx - VSELx| <1.5 V
–
60
85
mA
SINK_DIS bit = 0, ENBx bit = 1,
TONECTRLx = 0 or 1, |VLNBx - VSELx| > 1.5 V
–
7
10
mA
VIN = 16 V
–
–
10
µA
–
30
–
mVPP
5.25
5.53
V
General (continued)
Ripple and Noise on LNBx Output4
Vripn(pp)
20 MHz BWL; reference circuit shown in
Functional Block diagram; contact Allegro for
additional information on application circuit
board design
VREG Voltage
VVREG
VIN = 10 V
4.97
ISETx Voltage
VISETx
VIN = 10 V
TCAPx Voltage
VTCAPx
3.4
3.5
3.6
V
VIN = 10 V, VOUTx = 13.667 V
–
2.28
–
V
VIN = 10 V, VOUTx = 19.000 V
–
3.17
–
V
RSETx = 100 kΩ
220
300
380
mA
RSETx = 37.4 kΩ
720
800
880
mA
TDIS_T bit = 1
–
45
–
ms
TDIS_T bit = 0
–
28
–
ms
RSMODE bit = 1
–
1
–
s
RSETx = 100 kΩ
1300
1800
2300
mA
RSETx = 37.4 kΩ
2800
3300
3800
mA
Protection Circuitry
Output Overcurrent Limit5
IOUTx(MAX)
Overcurrent Disable Time
tDIS
Overcurrent Re-Enable Time
tREN
Boost MOSFET Current Limit
IBOOSTx(MAX)
VIN Undervoltage Lockout Threshold
VUVLO
VIN falling
8.05
8.35
8.65
V
VIN Turn-On Threshold
VIN(th)
VIN rising
8.40
8.70
9.00
V
I2C™
VUVLO_ I2C
VIN falling
–
5.5
–
V
I2C™ Turn-On Threshold
Undervoltage Lockout Threshold
VIN(th)_I2C
VIN rising
–
5.7
–
V
Undervoltage Hysteresis
VUVLOHYS
–
350
–
mV
TJ
–
165
–
°C
Thermal Shutdown Threshold3
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A8302
Dual LNB Supply and Control Voltage Regulators
ELECTRICAL CHARACTERISTICS1 (continued) at TA = 25°C, VIN = 10 to 16 V,
Characteristic
Thermal Shutdown
Symbol
Hysteresis3
Power Not Good (Low)
Power Not Good (Low) Hysteresis
Power Not Good (High)
Power Not Good (High) Hysteresis
as noted2; unless noted otherwise
Test Conditions
∆TJ
Min.
Typ.
Max.
Unit
–
20
–
°C
PNGxLOSET
With respect to VLNBx setting; VLNBx low,
PNGx bit set to 1
88
91
94
%
PNGxLORESET
With respect to VLNBx setting; VLNBx low,
PNGx bit reset to 0
92
95
98
%
PNGxLOHYS
With respect to VLNBx setting
–
4
–
%
PNGxHISET
With respect to VLNBx setting; VLNBx high,
PNGx bit set to 1
106
109
112
%
PNGxHIRESET
With respect to VLNBx setting; VLNBx high,
PNGx bit reset to 0
102
105
108
%
–
4
–
%
500
700
900
mVPP
20
22
24
kHz
40
50
60
%
PNGxHIHYS
With respect to VLNBx setting
Tone
Amplitude
VTONE(PP)x
Frequency
fTONEx
Duty Cycle
DTONEx
Rise Time
tr(TONE)x
5
10
15
μs
Fall Time
tf(TONE)x
5
10
15
μs
ILNBx = 0 to 700 mA, CLNBx = 750 nF
Tone Detection
Amplitude
Reject Amplitude, Low
Reject Amplitude, High
VTDX(PP)x
Tone transmit
500
700
900
mVPP
VTDR(PP)x
Tone receive, 22 kHz sine wave
250
650
900
mVPP
VTD(XMT)Lx
Tone transmit
–
–
250
mVPP
VTD(RCV)Lx
Tone receive, 22 kHz sine wave
–
–
100
mVPP
VTD(XMT)Hx
Tone transmit
–
–
1.1
VPP
VTD(RCV)Hx
Tone receive, 22 kHz sine wave
–
–
1.1
VPP
fTD(RCV)x
Tone receive, 650 mVPP sine wave
17
22
27
kHz
fTD(XMT)x
Tone transmit, 650 mVPP sine wave
20
22
24
kHz
fTD(RCV)Lx
Tone receive, 650 mVPP sine wave
12
14
–
kHz
Frequency Capture
Frequency Reject, Low
Frequency Reject, High
fTD(XMT)Lx
Tone transmit, 650 mVPP sine wave
15
17
–
kHz
fTD(RCV)Hx
Tone receive, 650 mVPP sine wave
–
34
37
kHz
f
Tone transmit, 650 mVPP sine wave
–
30
33
kHz
Tone receive, 650 mVPP , 22 kHz sine wave
–
1.5
3
cycle
–
8.6
–
kΩ
Tone present, ILOAD = 3 mA
−
−
0.4
V
TD(XMT)Hx
Detection Delay
tDETx
TDI Input Impedance
ZTDIx
TDO Output Voltage
VTDO(L)x
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A8302
Dual LNB Supply and Control Voltage Regulators
ELECTRICAL CHARACTERISTICS1 (continued) at TA = 25°C, VIN = 10 to 16 V,
Characteristic
TDO Output Leakage
EPF Pin Threshold
EPF Threshold Hysteresis
BFGATE/LNB Voltage
Symbol
ITDOx
as noted2; unless noted otherwise
Test Conditions
Min.
Typ.
Max.
Unit
Tone absent, 0 V < VTDO < 5 V
−
−
10
µA
VIN voltage falling
−
3.325
−
V
−
175
−
mV
VBFG_ON
TONECTRLx = high
−
50
−
%
VBFG_OFF
TONECTRLx = low
−
99
−
%
VTNCTL(H)x
2.0
–
–
V
VTNCTL(L)x
–
–
0.8
V
ITNCTL(lkg)x
−1
–
1
μA
VSLP(H)
2.0
–
–
V
VEPF_TH
VEPF_TH_hys
Tone Control (TONECTRL pin)
Logic Input
Input Leakage Current
¯ Ē¯ Ē¯ P̄¯ pin)
Sleep Mode Control ( S̄¯ L̄
Logic Input
Input Leakage Current
VSLP(L)
–
–
0.8
V
ISLP(lkg)
–
50
–
μA
VSCL(L)
–
–
0.8
V
VSCL(H)
2.0
–
–
V
VI2CIHYS
–
150
–
mV
I2C™- Compatible Interface
Logic Input (SDA and SCL pins)
Logic Input Hysteresis
Logic Input Current
¯Q̄¯ pins)
Logic Output Voltage (SDA and ¯¯I ¯R̄
Logic Output Leakage Current (SDA
and ¯¯I ¯R̄¯Q̄¯ pins)
SCL Clock Frequency
II2CI
VI2COUT(L)
II2CLKG
fCLK
VI2CI = 0 to 5 V
–10
<±1.0
10
µA
ILOAD = 3 mA
–
–
0.4
V
VI2COUT(L) = 0 to 5 V
–
–
10
µA
–
–
400
kHz
I2C™ Address Setting
ADD Pin Voltage for Address 0001 000
Address1
0
–
0.7
V
ADD Pin Voltage for Address 0001 001
Address2
1.3
–
1.7
V
ADD Pin Voltage for Address 0001 010
Address3
2.3
–
2.7
V
ADD Pin Voltage for Address 0001 011
Address4
3.0
–
5.0
V
1Operation
at 16 V may be limited by power loss in the linear regulator.
2Indicates specifications guaranteed from 0 ≤ T ≤ 125°C (min), design goal is 0 ≤ T ≤ 150°C.
J
J
3Guaranteed by worst case process simulations and system characterization. Not production tested.
4LNB output ripple and noise are dependent on component selection and PCB layout. Refer to the application schematic drawings and the PCB layout
recommendations. Not production tested.
5Current from the LNB output may be limited by the choice of BOOST components.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A8302
Dual LNB Supply and Control Voltage Regulators
Functional Description
Boost Converter/Linear Regulator
The A8302 solution contains two tracking current-mode boost
converters and Linear regulators. The boost converter tracks the
requested LNB voltage to within 800 mV, to minimize power dissipation. Under conditions where the input voltage, VBOOSTx , is
greater than the output voltage, VLNBx, the linear regulator must
drop the differential voltage. When operating in these conditions,
care must be taken to ensure that the safe operating temperature
range of the A8302 is not exceeded.
The A8302 has internal pulse-by-pulse current limiting on the
boost converter and DC current limiting on the LNB output to
protect the IC against output short to GND faults.
Boost Converter Operation Under Light Load
At extremely light load or no load, if the BOOSTx voltage tries to
exceed the BOOSTx target voltage, the boost converter operates
with minimum on-time. The BOOSTx settling voltage depends
on: supply voltage, boost inductance, minimum on-time, switching frequency, output power, as well as power loss in the boost
inductor, capacitor, and the A8302. If the BOOSTx voltage tries
to exceed 23.7 V, the optionally-enabled adjustable sink is turned
on. This internal sink helps to avoid pulse skipping and audible
noise with ceramic capacitors on BOOSTx. The internal sink
on BOOSTx gradually increases from 0 mA proportional to the
result of VBOOSTx – 23.7 V, and the sink current reaches a maximum value of 17.9 mA when VBOOSTx reaches 27 V. Beyond
this, if the BOOSTx voltage tries to exceed 27 V, the internal sink
current on BOOSTx will be held at 17.9 mA till VBOOSTx reaches
28 V. Beyond this, if the BOOSTx voltage tries to exceed 28 V,
the A8302 enters into pulse skipping with 350 mV hysteresis.
During pulse skipping the internal sink on BOOSTx is turned off
when BOOSTx stops switching.
The optional internal sink on BOOSTx is enabled / disabled by
setting / resetting Control Register 0 bit 7( SINK_NL). This bit is
common to both channels. When the SINK_NL bit is set to 1, the
adjustable internal sink is enabled. When the SINK_NL bit is set
to 0, the internal sink on BOOSTx is disabled.
18.6 to 19.6 V
13.3 to 14.3 V
LNBx Pin
Output Voltage
0V
800 mA
IOUTx(MAX)
IOUTx
0 mA
Up to 700 mA
Continuous
Up to 700 mA
Continuous
ENBx Bit
PNGx Bit
DISx Bit
OCPx Bit
Startup
t < tDIS
Reconfiguration
t < tDIS
Short Circuit
or Overload
t > tDIS
Figure 1. Startup, reconfiguration, and short circuit operation using RSETx = 37.4 kΩ, and a capacitive load (OCPx_25P bit = 0)
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A8302
Dual LNB Supply and Control Voltage Regulators
Multiple Outputs
In the case that two or more set top box LNB outputs are connected together by the customer (such as with a splitter), it is
possible that one output could be programmed at a higher voltage
than the other. This would cause a voltage on one output that is
higher than its programmed voltage (for example, 19 V on the
output of a 13 V programmed voltage). The output with the
highest voltage will effectively turn off the other outputs.
As soon as this voltage is reduced below the value of the other
outputs, the A8302 output will auto-recover to its programmed
levels.
Charge Pump
Generates a supply voltage above the internal tracking regulator
output to drive the linear regulator control.
LNBx and BOOSTx Current Limits Setting
The LNB output current limit, IOUTx(MAX) can be set by connecting a resistor (RSETx) from the ISETx pin to GND as shown
in the applications schematics. The LNBx current limit can be
set from 300 to 1000 mA, corresponding to an RSETx value of
100 to 30 kΩ, respectively. See figure 1 for a typical circuit timing example.
The LNBx output current limit can be set as high as 1000 mA
(by selecting an RSETx of 30 kΩ), but care should be taken not
to exceed the thermal limit of the package, or thermal shutdown
(TSD) will occur. The typical LNB output current limit can be set
according to the following equation:
IOUTx(MAX) = 29,925 / RSETx ,
where IOUTx(MAX) is in mA and RSETx is in kΩ.
If the voltage at the ISETx pin is 0 V (that is, shorted to GND),
IOUTx(MAX) will be clamped to a moderately high value, 1.2 A.
Care should be taken to ensure that ISETx is not inadvertently
grounded. If no resistor is connected to the ISETx pin (that is, if
ISETx is open-circuit), IOUT(MAX) will be set to approximately
0 A and the A8302 will not support any load (OCP will occur
prematurely).
The BOOSTx pulse-by-pulse current limit, IBOOSTx(MAX), is
automatically scaled along with the LNBx output current limit.
The typical BOOSTx current limit is set according to the following equation:
IBOOSTx(MAX) = 3.0 × IOUTx(MAX) + 900 (mA) ,
where both IBOOSTx(MAX) and IOUTx(MAX) are in mA.
Automatically scaling the BOOSTx current limit allows the
designer to choose the lowest possible saturation current of the
boost inductor, reducing its physical size and PCB area, thus
minimizing cost.
Protection
The A8302 has a wide range of protection features and fault diagnostics which are detailed in the Status Register section.
Undervoltage Lockout (UVLO)
The Undervoltage Lockout (UVLO) comparator monitors the
voltage at the VIN pin and keeps the regulator disabled if the
voltage is below the lockout threshold, VIN(th) . The UVLO comparator incorporates enough hysteresis, VUVLOHYS , to prevent
on-off cycling of the regulator due to IR drops in the VIN path
during heavy loading or during startup.
Overload and Short Circuit Handling
The A8302 protects the IC against output overload and short circuit. The short circuit disable timer is controlled with the TDIS_T
bit. If this bit is set to 1, the IC allows an overcurrent condition
to persist up to 45 ms and if this bit is set to 0, the maximum
overcurrent time allowed is 28 ms. The A8302 provides the
option either to latch or to auto‑restart on fault. If the RSMODE
bit is set to 1, with an overcurrent condition that exceeds typically
45 ms (TDIS_T set to 1) or 28 ms (TDIS_T set to 0), the IC turns
off output for 1 s and then auto-restarts with the previous settings.
This hiccup mode continues as long as output current is greater
than the OCP level. The device returns to normal operation when
the fault is removed. If RSMODE is set to 0, the IC turns off after
tDIS time expires, and remains latched. Figures 2a and 2b explain
overcurrent protection operation with RSMODE at 1 and at 0.
The A8302 has an optional 25% bump up on the current limit for
tdis /4 period. This feature is enabled / disabled by setting or resetting Control Register 2 bits 0 and 1 for channel 1 and channel 2
respectively. When this bit is enabled, the output current limit is
25% more than the set current limit, or 1000 mA (max), for both
limits a minimum of tdis /4 period. After the tdis / 4 period, the output current limit comes down to the set limit and the OCPx_25P
bit is reset to zero, The user must set this bit again to enable the
25% bump up at the next current limit event. If the OCPx_25P bit
is zero when LNBx output is shorted to ground, the LNBx output
current will be clamped to IOUTx(MAX). If the short circuit condition lasts for more than 45 ms, the A8302 will be disabled and the
OCPx bit will be set. Refer to figures 16a and 16b.
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A8302
Dual LNB Supply and Control Voltage Regulators
1s
1s
ENBx bit
IOUTx(MAX)
IC shutdown,
then restart
IOUTx
Short circuit causes IOUTx to exceed
IOCP for longer than 45 (or 28) ms
Short circuit
removed
VOUTx and tone
settings restored
as before short
circuit occurred
VLNBx
1.4 ms
VBOOSTx
1.4 ms
VIN
OCPx bit
I2C Read
PNGx bit
IRQ
¯Q̄¯ and Fault Clearing in Response to Overcurrent (OCP) with auto-retry enabled
Figure 2a. ¯¯I ¯R̄
¯Q̄¯ transitions to low
(RSMODE = 1) and an OCP delay of 45 (or 28) ms (TDIS_T = 1 (or 0)). ¯¯
I ¯R̄
at an OCP fault and is reset by an I2C Read sequence. The OCP bit clears automatically after 1
s, and the device restarts with the previous settings. This hiccup mode continues as long as the
output current is greater than the OCP level. The device returns to normal operation when the
fault is removed.
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A8302
Dual LNB Supply and Control Voltage Regulators
User-controlled
tOFF > 1 s
Short circuit
removed
ENBx bit
IOUTx(MAX)
IC shutdown,
then restart
IOUTx
Short circuit causes IOUT to exceed
IOCP for longer than 45 (or 28) ms
VOUTx and tone settings restored
as set in most recent Write cycle
VLNBx
1.4 ms
VBOOSTx
VIN
OCPx bit
PNGx bit
IRQ
I2C Read
¯Q̄¯ and Fault Clearing in Response to Overcurrent (OCP) with latch mode
Figure 2b. ¯¯I ¯R̄
(RSMODE = 0) and an OCP delay of 45 (or 28) ms (TDIS_T = 1(or 0)). ¯¯I ¯R̄¯Q̄¯ transitions low
at an overcurrent fault, and an I2C Read sequence clears the OCP bit and ¯¯I ¯R̄¯Q̄¯ . An I2C Write
sequence is required to reenable the part. The retry wait time should be longer than 1 s, to
prevent TSD.
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A8302
Dual LNB Supply and Control Voltage Regulators
Switching Frequency Selection
The A8302 offers two switching frequencies: 563 kHz and
939 kHz. High switching frequency allows minimizing the component size, which also increases switching losses. Use a high
switching frequency setting to optimize component size and take
care of A8302 power dissipation. High switching frequency is
preferred for low output current applications. Where the A8302
power dissipation is of a concern, use a low switching frequency
setting. Refer to application schematic section for details. Switching frequency is adjusted using Control Register 0, bit 4. User
program should select a correct switching frequency setting for
which the hardware is designed.
Slew Rate Control
Compensation Network Selection
The A8302 is designed to work with ceramic or electrolytic
capacitors on BOOST output. Boost loop compensation required
is different for ceramic and electrolytic capacitor options. The
proper compensation network is selected by setting Control Register 0, bit 5. User program should select a correct compensation
network setting based on the boost capacitor selection.
where SR is the required slew rate of the LNB output voltage, in V/s, and ITCAPx is the TCAPx pin current specified in
the Electrical Characteristics table. The recommended value
for CTCAPx , 100 nF, should provide satisfactory operation for
most applications.
When VIN goes below UVLO level, all control registers are reset
to default value, that is, 0. The user must write proper bits upon
each power-up. Application based bits all are bunched into Control Register 0, which are normally not required to change during
operation. Switching frequency, compensation network, and overcurrent disable delay bits must not be changed during operation.
VIN
During either startup, or when the output voltage at the LNBx pin
is transitioning, the output voltage rise and fall times can be set
by the value of the capacitor connected from the TCAPx pin to
GND (CTCAPx in the applications schematics). Note that during
start-up, the BOOSTx pin is pre-charged to the input voltage
minus a diode voltage drop. As a result, the slew rate control for
the BOOSTx pin occurs from this voltage. See figure 3.
The value of CTCAPx can be calculated using the following formula:
CTCAPx = (ITCAPx × 6) / SR ,
The minimum value of CTCAPx is 10 nF. There is no theoretical
maximum value of CTCAPx however too large a value will probably cause the voltage transition specification to be exceeded.
Tone generation is unaffected by the value of CTCAPx .
Pull-Down Rate
In applications that have to operate at very light loads and that
require large load capacitances (in the order of tens to hundreds
of microfarads), set the SINK_DIS bit to 0, so the output linear
VUVLO
VUVLO
SLEEP
ENBx bit
VOUTx and tone settings reset
2
when VIN goes below I C UVLO
15 mA (typ)
mA (typ)
IIN <15 7µA
(Current
through
VIN pin
of IC)
18 V setting
13 V setting
TCAPx
Overcurrent applied
T > 45 ms
13 V setting
C0
2
I C Read
Figure 3. TCAPx timing at startup, transition, and OCP faults. In latch mode (RSMODE = 0).
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A8302
Dual LNB Supply and Control Voltage Regulators
ENBx bit
TJ > 165°C
IC TJ
TJ < 145°C
VLNBx
VBOOSTx
VOUTx and tone
settings restored
as before TSD
circuit operated
IC attempts to restart
at 1-second intervals;
restart is successfull
if TJ < 145°C
VIN
TSD bit
PNGx bit
IRQ
I2C Read
Figure 4a. ¯¯I ¯R̄¯Q̄¯ and Fault Clearing in Response to Overtemperature (TSD) with auto-retry (RSMODE = 1). If for any reason
the junction temperature exceeds 165°C (typ), the device LNBx output and the boost converter are disabled. The IC
attempts to restart at 1-second intervals, but the LNBx output restarts only when TJ cools below 145°C. The ¯¯I ¯R̄¯Q̄¯ pin resets
on an I2C Read sequence, and the TSD bit resets along with an LNBx output restart.
TJ > 165°C
IC TJ
VLNBx
TJ < 145°C
IC shutdown
and latched
Fault removed
VOUTx and tone settings restored
as set in most recent Write cycle
PNGx bit
I2C Read
IRQ
TSD bit
¯Q̄¯
Figure 4b. ¯¯I ¯R̄¯Q̄¯ and Fault Clearing in Response to Overtemperature (TSD) with latch mode (RSMODE = 0). ¯¯
I ¯R̄
transitions low after TSD fault, and an I2C Read sequence immediately resets the ¯¯I ¯R̄¯Q̄¯ pin. The TSD bit is cleared by an
I2C Read sequence only after the device has cooled to a TJ below 145°C. An I2C Write sequence is required to reenable
the device.
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A8302
Dual LNB Supply and Control Voltage Regulators
stage provides approximately 25 mA of pull-down capability.
This ensures that the LNBx output voltage is ramped from 18 to
13 V in a reasonable amount of time. When the tone is on, the
output linear stage increases its pull-down capability to approximately 60 mA. This ensures that the tone signal meets all specifications, even with no load on the on the LNBx output.
Thermal Shutdown (TSD)
The A8302 protects the IC against overheating. If junction
temperature exceeds 165°C (typ), LNBx output and the boost
converter output are disabled until TJ cools below 145°C. The
A8302 provides the option either to latch or to auto‑restart on
fault. If the RSMODE bit is set to 1, the A8302 IC attempts to
restart at 1-second intervals, but restart is successful only with TJ
< 145°C. This hiccup mode continues as long as TJ > 145°C. The
device returns to normal operation when the fault is removed.
If RSMODE is set to 0, the IC turns off, and remains latched.
Figures 4a and 4b explain thermal shutdown protection operation
with RSMODE at 1 and at 0.
SINK_DIS Mode Selection
The A8302 SINK_DIS bit allows to select the maximum output
reverse current. When the SINK_DIS bit is set to 1, the maximum LNBx back feed current, IRLNBx , is less than 10 mA. When
the outputs of the LNBx converters are shorted, a 10 mA back
feed current will prevent loading of one converter output by
another converter output.
is 22 kHz. Note: This tone can be generated under no-load conditions and does not require an external DiSEqC™ filter.
When the TMODE bit is set to 1, an external 22-kHz tone signal
can be applied to the TONECTRLx pin. This tone frequency
appears at the LNBx output. VOUTx reaches the VLNBref level
after TONECTRLx has been low for longer than 42 µs.
Tone Detection
A 22-kHz tone detector is provided in the A8302. The detector
extracts the 22 kHz signal from the AC-coupled TDIx pin and
provides it as an open-drain logic output at the TDOx pin. Also,
when a tone is present, the TDET bit in the Status register is set
to 1 and can be seen via the I2C interface. The tone detection
delay is typically shorter than 1.5 cycles.
The tone detector dynamically adjusts its amplitude and frequency thresholds depending on whether the A8302 is transmitting or receiving a tone signal. If the A8302 is transmitting,
the tone detect amplitude threshold is relatively high and the
acceptable frequency range is tight. This provides a high quality tone signal is always generated by the A8302. Conversely,
Sleep Mode
The A8302 includes a sleep mode that instantly turns off the
LNBx output and resets the internal Control register to its default
¯P̄¯ pin is low, the A8302 will
(power-on) state. When the S̄L̄¯Ē¯Ē
draw IIN(OFF) less than 15 µA from the input supply.
In-Rush Current
At startup or during an LNB Reconfiguration event, a transient
surge current above the normal DC operating level can be provided by the A8302. This current increase can be as high as the
set output current.
Tone Generation
The A8302 offers two options for tone generation (figure 5). The
TONECTRLx pin with the TMODE control bit provides the necessary control. The TMODE bit controls whether the tone source
is internal or external.
When the internal source is used (TMODE bit set to 0), the tone
is gated with the TONECTRLx pin. The internal tone frequency
Figure 5. Options for tone generation
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A8302
Dual LNB Supply and Control Voltage Regulators
if the A8302 is receiving, the tone detect amplitude threshold
is reduced and the acceptable frequency range is increased
slightly. This provides the A8302 has maximum sensitivity to
remotely generated tone signals that may be degraded by long
lengths of coaxial cable. The Electrical Characteristics table of
this datasheet documents the guaranteed specifications of the
tone detector and how they are adjusted by tone transmission or
receiving mode.
grammed delay. The EPF bit resets automatically when the EPF
pin voltage goes above VEPF_TH + VEPF_TH_hys .
To help in the understanding, typical tone detector operation
is shown graphically in figures 6a and 6b. The shaded areas
in figure 6a indicate the accept range of the detector when
TONECTRLx is a logic high (transmit) and a logic low (receive).
The shaded areas in figure 6b indicate the reject range of the
detector when TONECTRLx is a logic high (transmit) and a logic
low (receive).
Case 1: EPF warning when VIN falls to 10.5 V
Early Power Failure Warning (EPF)
The EPF signal gives the microcontroller early warning that the
supply voltage is falling below the EPF threshold value, so the
microcontroller can start to shed non-critical loads (such as the
LNBR) and begin its shutdown routines.
Tone Amplitude (mV)
When the voltage on the EPF pin falls below VEPF_TH , the EPF
bit is set and IRQ is pulled low. When the EPF pin voltage goes
above VEPF_TH + VEPF_TH_hys, the EPF bit is reset after the pro-
The delay between when the EPF pin voltage goes to VEPF_TH +
VEPF_TH_hys and when the EPF bit is reset, is programmed by the EPF0 and EPF1 bits. See table 3b for description.
The following examples explain selection of resistors R1 and R2
to set the EPF warning when VIN falls to 10.5 V or 7 V.
Assume:
Nominal Input Voltage = 12 V,
VEPF_TH = 3.5 V,
VEPF_TH_hys = 0.175 V, and
EPF_TH1 ( VIN corresponding to setting EPF bit) = 10.5 V.
Given:
VEPF_TH = EPF_TH1 × R2 / (R1 + R2 ), where
R2 / (R1 + R2 ) = 3.5 / 10.5 = 1 / 3, then
choose R2 = 10 kΩ , R1 = 20 kΩ.
Given:
VEPF_TH = EPF_TH2 × R2 / (R1 + R2), then
EPF_TH2 (VIN corresponding to resetting EPF bit) = 11 V
Case2: EPF warning when VIN falls to 7 V
900
TONECTRLx = 1
(Transmit)
Assume:
TONECTRLx = 0
(Receive)
Nominal Input Voltage = 12 V,
500
VEPF_TH = 3.5 V,
VEPF_TH_hys = 0.175 V, and
250
17
20
24
EPF_TH1 ( VIN corresponding to setting EPF bit) = 7 V.
27
Given:
Tone Frequency (kHz)
Figure 6a. Accept ranges of Tone Detection feature
Tone Amplitude (mV)
1100
TONECTRLx = 0
(Receive)
VIN
EPF
TONECTRLx = 1
(Transmit)
R2
250
100
12 15
33
37
Tone Frequency (kHz)
A8302
R1
–
+
VEPF_TH
Figure 7. Example circuit for Early Power Failure feature
Figure 6b. Reject ranges of Tone Detection feature
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A8302
Dual LNB Supply and Control Voltage Regulators
VEPF_TH = EPF_TH1 × R2 / (R1 + R2 ), where
R2 / (R1 + R2 ) = 3.5 / 7 = 1 / 2, then
choose R2 = 10 kΩ , R1 = 10 kΩ.
Given:
VEPF_TH + VEPF_TH_hys = EPF_TH2 × R2 / (R1 + R2 )
EPF_TH2 (VIN corresponding to resetting EPF bit) = 7.35 V.
Cable Disconnect Detection
A8302 does not go to pulse skipping if the BOOSTx voltage
settles below 28V(typ), this facilitates increased boost voltage
can be used to detect the cable disconnect . If the given application and supply voltage will ensure BOOSTxH voltage exceed
23.7V (typ) at no -load , Status register 1 bits BOOSTxH can be
used for cable disconnect detection .
For the application requirements shown in schematic 3 and 4 at
Vin= 12+/-5% , Boost voltage is expected to exceed 23.7V and
which sets status register 1 bits BOOSTxH to high. Host controller can decode these bits t for the cable disconnect detection.
In the applications where Boost voltage cannot exceed 23.7V
(typ) at no-load , A simple potential divider connection on
BOOST, as shown in Figure 8, is used to sense the BOOST voltage. When the volt­age on EPF pin is below VEPF_TH , the EPF
bit is set to 1. When voltage on the EPF pin exceeds VEPF_TH +
VEPF_TH_hys , the EPF bit is reset to 0. The combination of Rc1
and Rc2 is selected such that, when the cable is disconnected, the
voltage on the EPF pin exceeds VEPF_TH + VEPF_TH_hys and resets
the EPF bit to 0; other­wise the EPF bit is set to 1.
To enable the cable disconnect test, set the LNB output volt­
age to 13.333 V and read the Status register bit. If the EPF bit is
reset, the cable is disconnected, otherwise the cable is connected.
When the cable disconnect feature is used, the EPF pin senses
the BOOST voltage, so the Early Power Failure warning (EPF)
feature cannot be used.
BOOSTX
Rc1
33 kΩ
A8302
EPF
Rc2
10 kΩ
–
+
VEPF_TH
Figure 8. Cable Disconnect Detection
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A8302
Dual LNB Supply and Control Voltage Regulators
Component Selection
Boost Inductor
The A8302 is designed to operate with a boost inductor value of
either 10 μH ±30% ( Set Fsw bit =0 ) or 4.7 μH ±30% ( Set Fsw
bit =1 ) with a DCR less than 75 mΩ. The error amplifier loop
compensation, current sense gain, and PWM slope compensation were chosen for this value of inductor. The boost inductor
must be able to support the peak currents required to maintain the
maximum LNBx output current without saturating. Figure 9a can
be used to determine the peak current in the induc­tor tor given
the LNBx load current. The curve labeled Typical uses VIN = 12
V, VBOOST = 20 V, L = 10 μH, and f = 563 kHz, while the curve
labeled Maximum assumes VIN = 10.8 V, VBOOST = 21 V, L =
7 μH, and f = 507 kHz.
Figure 9b can be used to determine the peak current in the induc­
tor tor given the LNBx load current. The curve labeled Typical
uses VIN = 12 V, VBOOST = 20 V, L = 4.7 μH, and f = 939 kHz,
while the curve labeled Maximum assumes VIN = 10.8 V,
VBOOST = 21 V, L = 3.3 μH, and f = 845 kHz
Boost Ceramic Capacitor Option
The A8302 can be configured to operate with two or three, highquality ceramic capacitors on the boost node. Allegro recommends capacitors that are rated at least 35 V, ±10%, X7R, 1210
IBOOST vs ILNB
4000
IBOOST (mAPEAK)
3500
Maximum
Typical
3000
2500
2000
1500
1000
500
300
400
500
600
700
800
Current Limit Setting, ILNB (mA)
900
1000
Figure 9a. Boost inductor peak current versus ILNB for the A8302 (L= 10uH, Fsw bit =0)
IBOOST vs ILNB
4000
IBOOST (mAPEAK)
3500
Maximum
Typical
3000
2500
2000
1500
1000
500
300
400
500
600
700
800
Current Limit Setting, ILNB (mA)
900
1000
Figure 9b. Boost inductor peak current versus ILNB for the A8302 (L= 4.7uH, Fsw bit =1)
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A8302
Dual LNB Supply and Control Voltage Regulators
Table 1a. Recommended Boost Capacitor Characteristics for Ceramic Capacitor Option
Quantity of
Capacitors in
Parallel
Value of Each
Capacitor
(μF)
Tolerance
(%)
Rating
(V)
Temperature
Coefficient of
Capacitance
Size
3
4.7
±10
50
X7R
1210
2
10
±10
35
X7R
1210
Table 1b. Recommended Boost Capacitor Characteristics for Electrolytic Capacitor Option
Quantity of
Capacitors in
Parallel
Value of Each
Capacitor
(μF)
Tolerance
(%)
Rating
(V)
Temperature
Coefficient of
Capacitance
Size
1
100
±25
35
–
–
The nominal boost capacitance should total 14.1 to 20 μF. Allegro
recommends either three 4.7 μF or two 10 μF capacitors, with the
characteristics shown in table 1.
Figure 10 provides typical and maximum values of rms current
required for a given LNR current:
VIN (V)
VOUT (V)
L (µH)
fSW (kHz)
Typical
Rating
12
19
10
563
Maximum
9
20
7
507
Two possible ceramic based capacitor solutions have been presented. Other capacitor combinations are certainly possible, such
as a very low ESR electrolytic capacitor in parallel with several
microfarads of ceramic capacitance. However, there are two
critical requirements that must be satisfied: 1) the zero formed by
the electrolytic capacitor and its ESR should be at least 1 decade
higher than the 0 dB crossover of the boost loop (typically around
25 kHz), and 2) the ceramic capacitors must eliminate the high
frequency switching spikes/edges in the boost voltage, or the
LNB output noise will be too high.
Boost Electrolytic Capacitor Option
The A8302 can be configured to operate with a low-ESR electrolytic boost capacitor of 100 μF ±25% . The ESR of the boost
capacitor must be less than 150 mΩ or the boost converter will
be unstable. General purpose electrolytic capacitors that do not
specify an ESR should be avoided. Allegro recommends an
electrolytic capacitor that is rated to support at least 35 V and has
an rms current rating to support the maximum LNBx load. Figure
9 can be used to determine the necessary rms current rating of the
boost capacitor given the LNBx load current.
1100
1000
IBOOST_CAP_RMS (mA rms)
size. Physically smaller capacitors, such as the 0603 and 0805,
with lower temperature ratings, such as X5R and Z5U, should be
avoided.
900
800
Maximum
700
600
Typical
500
400
300
300
400
500
600
700
800
Current Limit Setting, ILNB (mA)
900
1000
Figure 10. Boost capacitor rms current versus ILNB
BOOSTx Filtering and LNBx Noise
The LNBx output noise depends on the amount of high-frequency
noise at the BOOSTx pin. To minimize the high-frequency noise
at the BOOSTx pin, the ceramic capacitors should be placed as
close as possible to the BOOSTx pin.
Surge Components
Set-top–box suppliers have increased their surge specifications
to require surge to failure of the TVS, or ±4000 V, whichever
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A8302
Dual LNB Supply and Control Voltage Regulators
occurs first. These increased surge voltages produce significantly
more current in both the external circuitry and the A8302. Allegro
surge testing has shown that the SMDJ20A and LNBTVS6-221
usually fail at approximately 43 V, so all of the LNBR output
components (ceramic capacitors, diodes, and so forth) should
support at least 50 V.
To protect at these higher voltage/current levels three modifications must be made:
• For increased positive surge, the shunting diode from the LNBx
pin to the BOOSTx pin (D3, 3 A/40 V) is no longer adequate
to protect the body diode of the output stage. This diode must
be increased to a 3 A/50 V device and be located so that it is in
series with the BOOSTx pin as shown in application schematics 3
and 4. In this position D3 will block surge current to the majority
of the boost capacitance, but the 1 µF ceramic capacitor will still
filter the high frequency switching noise.
• For increased negative surge, the relatively small clamping
diode (D2) from the LNBx pin to ground is no longer adequate.
This diode must be increased from a 1 A / 40 V, SOD123 device
to a 3 A / 50 V, SMA.
• For a DiSEqC 1.0 application, a 0.47 Ω / 1% / 0.25 W series
resistor must be added as shown in the application schematics.
The 0.47 Ω rating could be reduced if there is enough equivalent resistance in any series output components such as jumpers,
inductors, or PCB traces. Every application will have its own
surge requirements and the surge solution can be changed. However, Allegro strongly recommends incorporating a form of surge
protection to prevent any pin of the A8302 from exceeding its
Absolute Maximum voltage ratings shown in this datasheet.
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A8302
Dual LNB Supply and Control Voltage Regulators
I2C™-Compatible Interface
The I2C™ interface is used to access the internal Control and
Status registers of the A8302. This is a serial interface that uses
two lines, serial clock (SCL) and serial data (SDA), connected to
a positive supply voltage via a current source or a pull-up resistor. Data is exchanged between a microcontroller (master) and
the A8302 (slave). The master always generates the SCL signal.
Either the master or the slave can generate the SDA signal. The
SDA and SCL lines from the A8302 are open-drain signals, so
multiple devices may be connected to the I2C™ bus. When the
bus is free, both the SDA and the SCL lines are high.
Acknowledge Bit During a Write Sequence
When the master sends control data (writes) to the A8302 there
are three cases where AK bits are sent by the A8302. First, the
A8302 uses the AK bit to indicate reception of a valid sevenbit chip address plus a Read/Write bit (with R/W set to 0 for a
Write). Second, the A8302 uses the AK bit to indicate reception
of a valid eight-bit Control register address. Third, the A8302
uses the AK bit to indicate reception of eight bits of control data.
This protocol is shown in figure 11a.
Acknowledge Bit During a Read Sequence
When the master reads status data from the A8302 there are four
cases where AK bits are sent: three are sent by the A8302 and
one is sent by the master. First, the A8302 uses the AK bit to
indicate reception of a valid seven-bit chip address plus a Read/
Write bit (with R/W set to 0 for a Write). Second, the A8302 uses
the AK bit to indicate reception of a valid eight-bit Status register
address. Third, the A8302 uses the AK bit to indicate reception
of a valid seven-bit chip address plus a Read/Write bit (with
R/W set to 1 for a Read). Finally, the master uses the AK bit to
indicate receiving eight bits of status data from the A8302. This
protocol is shown in figure 11b.
SDA and SCL Signals
SDA can only be changed while SCL is low. SDA must be stable
while SCL is high. However, an exception is made when an
I2C™ Start or Stop condition is encountered. See the I2C™ Communications section for further details.
Acknowledge (AK) Bit
The Acknowledge (AK) bit indicates a valid transmission and
can be used in two ways. First, if the slave successfully receives
eight bits of either an address or control data, it pulls the SDA
line low (AK set to 0) for the ninth SCL pulse to signal a valid
transmission to the master. Second, if the master successfully
receives eight bits of status data from the A8302, it pulls the SDA
line low for the ninth SCL pulse to signal a valid transmission to
the slave. The recipient (either the master or the slave) should set
the AK bit high (AK set to 1, also referred to as NAK) for the
ninth SCL pulse if eight bits of data were not
received successfully.
I2C™ Communications
I2C™ Start and Stop Conditions
The I2C™ Start condition is defined by a negative edge on
the SDA line while SCL is high. Conversely, the Stop condition is defined by a positive edge on the SDA line while SCL
is high. The Start and Stop conditions are shown in figures 10a
and 10b. It is possible for a Start or Stop condition to occur at
acknowledge
from A8302 (slave)
Start
SDA
SCL
Figure 11a.
I2C™
Chip Address
Control Register Address
R/W
SDA
SCL
acknowledge
from A8302 (slave)
Control Data
A6
A5
A4
A3
A2
A1
A0
W AK/ RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 AK/ D7
NAK
NAK
D6
D5
D4
0
0
0
1
0
0/1
0/1
0
0/1
0
0
0
0
0
0
0
0/1 0/1 0/1
0/1
0/1
0/1 0/1
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
2
3
9
1
4
D3
Stop
D2
D1
0/1 0/1
5
6
7
AK/
D0 NAK
0/1 0/1
8
9
Interface Write to Control registers sequence
acknowledge
from A8302 (slave)
Start
acknowledge
from A8302 (slave)
R/W
Chip Address
acknowledge
from A8302 (slave)
acknowledge
from A8302 (slave)
Status Register Address
Stop
Chip Address
Start
A6
A5
A4
A3
A2
A1
A0
W AK/ RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK/
NAK
NAK
A6
A5
A4
0
0
0
1
0
0/1
0/1
0
0/1
0
0
0
0
0
0
0
0
0/1
0
0
0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
A3
acknowledge
from master
R/W
Status Data
R
AK/ RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK/
NAK
NAK
Stop
A2
A1
A0
1
0
0/1
0/1
1
0/1
0/1
0/1
0/1
0/1 0/1
0/1 0/1
0/1 0/1
4
5
6
7
8
9
1
2
3
4
6
8
5
7
9
Figure 11b. I2C™ Interface Read from Status register sequence
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A8302
Dual LNB Supply and Control Voltage Regulators
any time during a data transfer. If either a Start or Stop condition
is encountered during a data transfer, the A8302 will respond by
resetting the data transfer sequence.
I2C™ Write Sequence Description
Writing to the A8302 Control register requires transmission of a
total of 27 bits: three 8-bit bytes of data plus an AK bit after each
byte. The Write sequence to the A8302 Control registers is shown
in figure 10a. Writing to the A8302 Control registers requires: an
I2C™ Start condition, a chip address with the R/W bit set to 0,
the Control register address, the control data, and an I2C™ Stop
condition as follows:
• The Chip Address cycle consists of a total of nine bits: seven
bits of chip address (A6 to A0) plus one R/W bit (set to 0 to
indicate a Write) from the master, followed by an AK bit (set to 0
to indicate reception of a valid chip address) from the slave. The
cycle begins with a Start condition. The chip address must be
transmitted MSB (A6) first. The first five bits of the A8302 chip
address (A6 to A2) are fixed as 00010. The remaining two bits
(A1 and A0) are used to select one of four possible A8302 chip
addresses. The DC voltage on the ADD pin programs the chip
address. See the Electrical Characteristics table for the ADD pin
voltages and the corresponding chip addresses.
• The Control Register Address cycle consists of a total of nine
bits: eight bits of Control register address (RC7 to RC0) from
the master followed by an AK bit (set to 0 to indicate reception
of a valid register address) from the slave. The Control register
address must be transmitted MSB (RC7) first. The A8302 has
two Control registers, with register addresses of 0000 0000 and
0000 0001.
• The Control Data cycle consists of a total of nine bits: eight
bits of control data (D7 to D0) from the master, followed by an
AK bit (set to 0 to indicate reception of eight valid bits) from the
slave. The control data must be transmitted MSB (D7) first. The
Control registers bits are identified in the Control Registers section of this datasheet. The cycle concludes with a Stop condition.
I2C™ Read Sequence Description
Reading from the A8302 Status register requires transmission of a
total of 36 bits: four 8-bit bytes of data, plus an AK bit after each
byte. The Read sequence from the A8302 Status register is shown
in figure 10b. Reading the A8302 Status register requires: an
I2C™ Start condition, a chip address with the R/W bit set to 0, the
Status register address, an I2C™ Stop condition, an I2C™ Start
condition, a repeat of the chip address with the R/W bit set to 1,
the status data, and an I2C™ Stop condition, as follows:
• The Chip Address cycle is identical to the Chip Address cycle
previously described for the Write sequence.
• The Status Register Address cycle consists of a total of nine
bits: eight bits of Status register address (RS7 to RS0) from the
master, followed by an AK bit from the slave. The Status register
address must be transmitted MSB (RS7) first. The A8302 has
only one Status register, so the Status register address is fixed at
0000 0000. The cycle concludes with a Stop condition.
• The Repeat Chip Address cycle is identical to the Chip Address
cycle previously described for the Write sequence.
• The Status Data cycle consists of a total of nine bits:
eight bits of status data (RD7 to RD0) from the slave, followed
by an AK bit from the master. The status data is transmitted MSB
(RD7) first. The Status register bits are identified in the Status
Registers section of this datasheet. The cycle concludes with a
Stop condition.
Interrupt Request (¯¯I ¯R̄¯Q̄¯ ) Pin
¯¯Q̄ , which is an
The A8302 provides an interrupt request pin, ¯Ī¯R̄
open-drain, active low output. This output may be connected to
a common IRQ line with a suitable external pull-up resistor and
can be used with other I2C™ compatible devices to request attention from the master controller.
The ¯Ī¯R̄¯¯Q̄ output becomes active (logic low) when the A8302
recognizes a fault condition. The fault conditions that will force
¯Ī¯R̄
¯¯Q̄ active include Early Power Failure (EPF), undervoltage
lockout (UVLO), overcurrent protection (OCP), and thermal
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A8302
Dual LNB Supply and Control Voltage Regulators
shutdown (TSD). The UVLO, OCP ( RSMODE bit set to 0 ),
and TSD ( RSMODE bit set to 0 ) faults are latched in the Status
register and are not unlatched until the A8302 Status register is
successfully transmitted to the master controller (an AK bit must
be received from the master). See the description in the Status
Register section and figure 12 for further details.
Start
Chip Address
W
Status Register Address
A6
A5
A4
A3
A2
A1
A0
0
AK RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK
SCL
1
2
3
4
5
6
7
8
1
2
3
acknowledge
from A8302 (slave)
acknowledge
from A8302 (slave)
SDA
9
The LNBx output disable (DISx bit set to 1) and Power Not
Good (PNGx bit set to 1) conditions do not cause an interrupt.
and are not latched in the Status register.
Figures 12, 13, 14, and 15 show the fault handling timing for
UVLO in various conditions: startup and shutdown, and relative
VREF , VIN , and EPF conditions. When the master device receives an interrupt, it should address
all slaves connected to the interrupt line in sequence and read
acknowledge
from A8302 (slave)
the Status register of each to determine which device is
requesting attention.
4
5
6
Stop
7
8
9
acknowledge
from master
R
Status Data
A6
A5
A4
A3
A2
A1
A0
1
AK RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 AK
1
2
3
4
5
6
7
8
Chip Address
Start
9
1
2
3
4
5
Stop
6
7
8
9
IRQ
FAULT event, IRQ set low, Status register latched
IRQ reset
Status
register
unlatched
¯Q̄¯ pin is reset to high when the A8302
Figure 12. I2C™ Interface Read from Status register sequence. The ¯¯
I ¯R̄
acknowledges it is being read. The Status register is unlatched when the master acknowledges the status data from
the A8302.
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A8302
Dual LNB Supply and Control Voltage Regulators
VIN
VUVLO
SLEEP
ENBx bit
15 mA (typ)
7 mA (typ)
<15 µA
IIN
Current through VIN pin of IC
VOUT and tone
settings restored
as before shutdown
VBOOSTx
VLNBx
PNGx bit
I2C Read
IRQ
Figure 13. Startup and Shutdown Cases. ¯¯I ¯R̄¯Q̄¯ and Fault Clearing in Response to Undervoltage at VIN (UVLO). If ¯¯I ¯R̄¯Q̄¯ transitions low
because of a latched fault, the LNBx output does not respond to the ENBx bit. An I2C™ Read sequence is required to clear any latched
fault and reset the ¯¯I ¯R̄¯Q̄¯ to logic high. An I2C™ Read is required after a UVLO fault.
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A8302
Dual LNB Supply and Control Voltage Regulators
8.70 V
8.35 V
5.7 V
(with Hys)
5.5 V
VIN
A
B
I2C Read
Cycle
IRQ
Enable
(ENBx bit
via I2C)
I2C Inactive
I2C Inactive
LNBx pin
Output
SLEEP
(External)
A READ between VREG and VUVLO is optional, to
clear IRQ early. This is also helpful when the EPF
threshold is set between VREG and VUVLO
B READ when VIN > VIN(Th) is required to clear the
UVLO bit
¯Q̄¯ operate down to VIN > VREG (VREG is 5.25 V typical), LNBx and BOOSTx operate from VIN(th) . When VIN
Figure 14a. I2C and ¯¯I ¯R̄
¯Q̄¯ fault.
exceeds VREG (5.25 V typical), ¯¯I ¯R̄¯Q̄¯ transitions low because of the UVLO fault, and an I2C Read sequence will clear the ¯¯I ¯R̄
While powering down, when VIN falls below VUVLO , ¯¯I ¯R̄¯Q̄¯ becomes low, LNBx and BOOSTx turn off, and I2C becomes inactive when
VIN falls below VREG .
8.70 V
8.35 V
5.7 V
(with Hys)
5.5 V
VIN
I2C Read
Cycle
IRQ
Enable
(ENBx bit
via I2C)
I2C Inactive
I2C Inactive
LNBx pin
Output
SLEEP
(External)
Figure 14b. ¯¯I ¯R̄¯Q̄¯ is cleared when VIN is already above VIN(th) . As the ENBx bit is already set high, LNBx starts rising immediately
after an I2C Read sequence.
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A8302
Dual LNB Supply and Control Voltage Regulators
12 V
11 V
(EPF _TH1)
VIN
8.7 V
(VIN UVLO)
5.7 V
(I2C UVLO)
IRQ
EPF bit
I2C Read
ENBx bit
LNBx pin
Output
I2C
Inactive
23 ms delay setting
¯Q̄¯ transitions low immediately after VIN goes above
Figure 15a. EPF pin threshold greater than VUVLO . When VIN is rising. ¯¯I ¯R̄
VREG (typical), and ¯¯I ¯R̄¯Q̄¯ is cleared immediately by an I2C Read sequence. After VIN goes above VIN(th) and is followed by an I2C
Read sequence, the UVLO bit is cleared and the LNB voltage goes up. After VIN goes above EPF_TH1, the EPF bit is cleared,
after the delay specified by the EPF0 and EPF1 bits.
VIN
10.5 V
(EPF _TH2)
8.3 V
(VIN UVLO)
6V
(I2C UVLO)
IRQ
EPF bit
I2C Read
ENBx bit
LNBx pin
Output
I2C
Inactive
Figure 15b. EPF pin threshold greater than VUVLO . When VIN falls below EPF_TH2. ¯¯I ¯R̄¯Q̄¯ transitions low and the EPF bit is set
¯Q̄¯ . When VIN falls below VUVLO , ¯¯I ¯R̄¯Q̄¯ transitions low, LNBx voltage goes down, and once
high. The I2C Read sequence releases ¯¯I ¯R̄
¯Q̄¯ .
again the I2C Read sequence clears ¯¯I ¯R̄
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A8302
Dual LNB Supply and Control Voltage Regulators
12 V
8.7 V
(VIN Th)
VIN
7.35 V
(EPF _TH1)
5.5 V
IRQ
EPF bit
II2C Read
ENBx bit
LNBx pin
output
I 2C
Inactive
EPF delay setting
Figure 16a. EPF pin threshold greater than VREG and less than VUVLO . When VIN is rising, ¯¯I ¯R̄¯Q̄¯ transitions low immediately after
VIN goes above VREG , and ¯¯I ¯R̄¯Q̄¯ is cleared immediately by an I2C Read sequence. After VIN goes above EPF_TH1, the EPF
bit is cleared after the delay specified by the EPF0 and EPF1 bits. When VIN goes above VIN(th) and is followed by an I2C Read
sequence, the UVLO bit is cleared and LNBx voltage goes up.
VIN
8.3 V
(VIN UVLO)
7V
(EPF _TH2)
5.2 V
IRQ
EPF bit
I2C Read
ENBx bit
LNBx pin
Output
I2C
Inactive
Figure 16b. EPF pin threshold greater than VREG and less than VUVLO . When VIN falls below VUVLO , ¯¯I ¯R̄¯Q̄¯ transitions low and an
I2C Read sequence releases ¯¯I ¯R̄¯Q̄¯ . When VIN falls below EPF_TH , ¯¯I ¯R̄¯Q̄¯ will not go low.
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A8302
Dual LNB Supply and Control Voltage Regulators
I2C™-Compatible Interface Timing Diagram
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tBUF
SDA
SCL
tLOW
tHIGH
I2C™-Compatible Timing Requirements
Characteristic
Bus Free Time Between Stop/Start
Symbol
Min.
Typ.
Max.
Unit
tBUF
1.3
–
–
µs
Hold Time Start Condition
tHD:STA
0.6
–
–
µs
Setup Time for Start Condition
tSU:STA
0.6
–
–
µs
SCL Low Time
tLOW
1.3
–
–
µs
SCL High Time
tHIGH
0.6
–
–
µs
tSU:DAT
100
–
–
ns
Data Setup Time
Data Hold Time*
tHD:DAT
0
–
900
ns
Setup Time for Stop Condition
tSU:STO
0.6
–
–
µs
Output Fall Time (VfI2COut(H) to VfI2COut(L))
tfI2COut
–
–
250
ns
*For tHD:DAT(min) , the master device must provide a hold time of at least 300 ns for the SDA
signal in order to bridge the undefined region of the SCL signal falling edge. Input filters on the
SDA and SCL inputs suppress noise spikes of less than 50 ns.
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A8302
Dual LNB Supply and Control Voltage Regulators
LNBx O/P
1.25 × IOUTx(MAX) (or) < 1 A
IOUTx
IOUTx(MAX)
tdis /4
tdis /4
tdis
I2C Read
tdis
tdis
I2C Write
OCPx_25P
Bit
LNBx O/P
Shorted
to GND
LNBx O/P
Shorted
to GND
removed
LNBx O/P
Shorted
to GND
LNBx O/P
Shorted
to GND
removed
LNBx O/P
Shorted
to GND
OCPx_25P
bit cleared
Figure 17a. Initial 25% current limit bump up with OCPx_25P bit enabled, disabled, and changed during current limit condition
with OCP period > tdis .
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A8302
Dual LNB Supply and Control Voltage Regulators
LNBx O/P
1.25 × IOUTx(MAX) (or) < 1 A
IOUTx
IOUTx(MAX)
tdis /4
I2C Read
<tdis /4
<tdis
<tdis
tdis /4
<tdis
I2C Write
OCPx_25P
Bit
LNB O/P
Shorted
to GND
LNB O/P
Shorted
to GND
removed
LNB O/P
Shorted
to GND
LNB O/P
Shorted
to GND
removed
LNB O/P LNB O/P
Shorted Shorted
to GND
to GND
removed
LNB O/P
Shorted
to GND
LNB O/P
Shorted
to GND
removed
Figure 17b. Initial 25% current limit bump up with OCPx_25P bit enabled, disabled, and changed during current limit condition
with OCP period < tdis .
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A8302
Dual LNB Supply and Control Voltage Regulators
Control Registers (I2C™-Compatible Write Register)
All main functions of the A8302 are controlled through the I2C™
compatible interface via the 8-bit Control registers. Tables 2a,
2b, and 2c show the functionality and bit definitions of the Control registers. At power-up, the Control registers are initialized to
all 0s.
Table 2a. Control Register 0 Definition
Control (Write) Register Address [RC7:RC0] = 0000 0000
Bit
Name
Function
Description
0
TMODE
Controls tone mode
0: Internal tone, gated with TONECTRLx pin
1: External 22 kHz logic pulse, on TONECTRLx pin
1
TDIS_T
Controls overcurrent disable delay*
0: Set overcurrent disable timeout to 28 ms
1: Set overcurrent disable timeout to 45 ms
2
EPF0
3
EPF1
When VIN is rising, these two bits determine the EPF
bit setting delay. (See table 3b for EPF bit delay setting
options.)
4
FSW
Switching frequency setting*
0: 563 kHz
1: 939 kHz
5
COMP
Switching between compensation networks*
0: Ceramic
1: Electrolytic
6
RSMODE
Fault restart mode
0: Latch mode. IC latches after tDIS period on OCP or
TSD; user enable required to restart
1: Auto restart mode if OCP or TSD cleared
7
SINK_NL
Turn on/off internal adjustable sink on BOOSTx
0: Disable sink on BOOSTx
1: Enable sink on BOOSTx
*Ensure the selected bit setting matches the hardware design.
Table 2b. Control Register 1 Definition
Control (Write) Register Address [RC7:RC0] = 0000 0001
Bit
Name
0
VSEL01
1
VSEL11
Function
Description
LNB1 output voltage control (see table 3a for available
output voltage selections)
The available voltages provide levels for all the common
standards plus the ability to add line compensation;
VSEL01 is the LSB and VSEL31 is the MSB to the
internal DAC
Turns the LNB1 output on or off
0: Disable LNB1 output
1: Enable LNB1 output
2
VSEL21
3
VSEL31
4
ENB1
5
OCP1_25P
25% bump up over current limit for channel 1, for tdis/4
period; bit resets automatically after tdis/4 period
0 : Bump up off
1 : Bump up on
6
SINK_DIS 1
SINK_DIS mode setting for channel 1
0: Maximum Output Reverse Current, IRLNBx , is 70 mA
1: Maximum Output Reverse Current, IRLNBx , is 10 mA
Tone Delay 1
In the External Tone Generation option (TMODE = 1),
LNB1 voltage can be reset back to the target value
with a 42 µs delay, or can be set to ≈350 mV below the
target value without a delay, by using this bit.
0: (Default) LNB1 voltage will be reset back to
the target after a delay of 42 µs from the last
TONECONTRL1 falling edge.
1: Tone will turn off with out a delay and the LNB1
voltage will stay at ≈350 mV below the target.
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
31
A8302
Dual LNB Supply and Control Voltage Regulators
Table 2c. Control Register 2 Definition
Control (Write) Register Address [RC7:RC0] = 0000 0010
Bit
Name
0
VSEL02
1
VSEL12
2
VSEL22
3
VSEL32
4
ENB2
5
6
7
Function
Description
LNB2 output voltage control (see table 3a for available
output voltage selections)
The available voltages provide levels for all the
common standards plus the ability to add line
compensation; VSEL02 is the LSB and VSEL32 is the
MSB to the internal DAC
Turns the LNB2 output on or off
0: Disable LNB2 output
1: Enable LNB2 output
OCP2_25P
25% bump up over current limit for channel 2, for tdis/4
period; bit resets automatically after tdis/4 period
0 : Bump up off
1 : Bump up on
SINK_DIS 2
SINK_DIS mode setting for channel 2
0: Maximum Output Reverse Current, IRLNBx , is 70 mA
1: Maximum Output Reverse Current, IRLNBx , is 10 mA
Tone Delay 2
In the External Tone Generation option (TMODE = 1),
LNB2 voltage can be reset back to the target value
with a 42 µs delay, or can be set to ≈350 mV below
the target value without a delay, by using this bit.
0: (Default) LNB2 voltage will be reset back to
the target after a delay of 42 µs from the last
TONECONTRL2 falling edge.
1: Tone will turn off with out a delay and the LNB2
voltage will stay at ≈350 mV below the target.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
32
A8302
Dual LNB Supply and Control Voltage Regulators
Table 3a. Output Voltage Amplitude Selection
Table 3b. EPF Delay Selection
VSEL3
VSEL2
VSEL1
VSEL0
LNB
(V)
0
0
1
0
0
0
1
1
0
1
0
0
1
1
1
0
1
1
1
Delay
(ms)
EPF1
EPF0
13.333
0
0
0
13.667
0
1
11.5
1
14.333
1
0
46
1
15.667
1
1
92
1
1
18.667
1
0
0
19.000
1
0
1
19.333
1
1
0
19.667
Status Registers (I2C™-Compatible Read Register)
The Status registers bits are described in tables 5a and 5b. The
main fault conditions: Early Power Failure (EPF), undervoltage
(UVLO), overcurrent (OCP), and thermal shutdown (TSD) are
all indicated by setting the relevant bits in the Status register. For
these fault cases (for OCP and TSD, only if the RSMODE bit
is set to 0), after the bit is set, it remains latched until the I2C™
master has successfully read the A8302, assuming the fault has
been resolved.
The undervoltage lockout (UVLO) bit indicates either VIN is below
VUVLO , or VREG is out of regulation. UVLO disables the LNBx
output and forces ¯Ī¯R̄¯¯Q̄ low. UVLO is a latched fault, and can only
be cleared by performing an I2C™ Read sequence.
The Disable bit (DISx) indicates the status of the LNBx output.
The DISx bit is set when either a fault occurs (UVLO, OCP,
TSD, or CPOK) or when the LNBx output is turned off using
the Enable bit (ENBx) via the I2C™ interface. The DISx bit is
latched and is only reset when there are no faults and the A8302
output is turned back on using the Enable (ENBx) bit via the
I2C™ interface.
respectively. These bits are not latched and, unlike the other fault
bits, may become reset without an I2C™ read sequence. The
PNGx, CPOKx, and TDETx bits are continuously updated.
The BOOSTxH bit is set when the BOOSTx voltage exceeds
23.7 V. This bit can be used to detect cable disconnect, provided
at the lowest supply voltage BOOSTx voltage should exceed
23.7 V.
There are three methods to detect when the Status register
changes: responding to the interrupt request ( ¯Ī¯R̄¯¯Q̄ ) pin going
low, continuously polling the Status register via the I2C™
interface, or detecting a fault condition external to the A8302
and performing a diagnostic poll of the A8302. In any case,
the master should read and re-read the Status register until the
status changes.
The Power Not Good (PNGx), Charge Pump OK (CPOKx), and Tone Detect (TDETx) bits are set based on the conditions sensed
at the LNBx output, VCPx, and Tone Detect Input (TDIx) pins,
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33
A8302
Dual LNB Supply and Control Voltage Regulators
Table 4. Status Registers Bit Descriptions
Name
Description
DISx
The DISx bit is set to 1 when the A8302 is disabled, (ENBx bit = 0) or there is a fault: UVLO,
OCPx, CPOKx, or TSD.
CPOKx
If the CPOKx bit is set to 0, the internal charge pump is not operating correctly (VCPx). If the
charge pump voltage is too low, the LNBx output is disabled and the DISx bit is set to 1.
OCPx
The OCPx bit will be set to 1 if the LNBx output current exceeds the overcurrent threshold
(IOUT(MAX)) for more than the overcurrent disable time (tDIS). If the OCPx bit is set to 1, then the
DISx bit is also set to 1.
TRIMS
Factory use only.
PNGx
The PNGx bit is set to 1 when the A8302 is enabled and the LNBx output voltage is either too low
or too high (nominally ±9% from the LNBx DAC setting). Set to 0 when the A8302 is enabled and
the LNBx voltage is within the acceptable range (nominally ±5% from the LNBx DAC setting).
TDETx
The TDETx bit is set to 1 if a tone is detected at the TDIx pin that is within the specified voltage
and frequency ranges. If TCTRLx = 1, the tone is being transmitted by the A8302, and the tone
detect low threshold is determined by VTD(XMT)L. If If TCTRLx = 0, it is assumed the tone is being
received from an external source, and the tone detect low threshold is determined by VTD(RCV)L.
TSD
The TSD bit is set to 1 if the A8302 has detected an overtemperature condition. If the TSD bit is
set to 1,then the DISx bit is also set to 1.
UVLO
The UVLO bit is set to 1 if either the voltage at the VIN pin or the voltage at the VREG pin is too
low. If the UVLO bit is set to 1, then the DISx bit is also set to 1.
BOOSTxH
EPF
The BOOSTxH bit is set to 1 when the voltage on BOOSTx exceeds 23.7 V. This bit
¯Q̄¯ .
automatically resets when BOOSTx voltage goes below 23.6 V. This bit has no effect on ¯¯I ¯R̄
The EPF bit is set to 1 when the voltage on the EPF pin falls below VEPF_TH. Also, IRQ\ is pulled
low. When the EPF pin voltage goes above VEPF_TH + VEPF_TH_Hys, the EPF bit is reset to 0 after
the delay selected by the EPF0 and EPF1 bits in the Control registers.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
34
A8302
Dual LNB Supply and Control Voltage Regulators
Table 5a. Status Register 0 Definition and IRQ Operation
Status (Read) Register Address [RS7:RS0] = 0000 0000
Bit
Name
Function
Latched?
¯ Pin
Effect on ¯¯
I ¯R̄¯Q̄
Reset Condition
0
DIS1
LNB1 output disabled
Yes
LNB1 enabled and no faults
None
1
DIS2
LNB2 output disabled
Yes
LNB2 enabled and no faults
None
Auto-retry (RSMODE = 1)
OCP reset after every 1 s; IC
enabled if fault is removed
2
OCP1
LNB1 overcurrent
Latch (RSMODE = 0)
3
OCP2
I2 C
Read sequence required
after removing the fault
Auto-retry (RSMODE = 1)
OCP reset after every 1 s; IC
enabled if fault is removed
Latch (RSMODE = 0)
I2C Read sequence required
after removing the fault
LNB1 voltage within range
LNB2 overcurrent
¯¯I ¯R̄¯Q̄¯ set low; I2C Read
sequence resets to high
¯¯I ¯R̄¯Q̄¯ set low; I2C Read
sequence resets to high
4
PNG1
LNB1 Power Not Good
No
5
PNG2
LNB2 Power Not Good
No
LNB2 voltage within range
None
Yes
I2C Read sequence and
VIN > 9.0 V
¯¯
I ¯R̄¯Q̄¯ set low; I2C Read
sequence resets to high
Auto-retry (RSMODE = 1)
TSD reset after every 1 s;
reset happens only if fault is
removed
Latch (RSMODE = 0)
I2C Read sequence required
after removing the fault
6
7
UVLO
TSD
VIN or VREG undervoltage
Thermal shutdown
None
¯¯I ¯R̄
¯Q̄¯ set low; I2C Read
sequence resets to high
Table 5b. Status Register 1 Definition and IRQ Operation
Status (Read) Register Address [RS7:RS0] = 0000 0001
Bit
Name
Function
Latched?
¯ Pin
Effect on ¯¯
I ¯R̄¯Q̄
Reset Condition
0
CPOK1
LNB1 charge pump OK
No
VCP1 > VBOOST1 + 5 V
None
1
CPOK2
LNB2 charge pump OK
No
VCP2 > VBOOST2 + 5 V
None
2
TDET1
LNB1 tone detect
No
Tone removed from LNB1 pin
None
3
TDET2
LNB2 tone detect
No
Tone removed from LNB2 pin
None
4
EPF
Early Power Failure warning
(VIN < EPF threshold)
No
VIN > EPF_TH1
¯¯I ¯R̄¯Q̄¯ set low; I2C Read
sequence resets to high
5
TRIMS
Trim bits locked
Yes
None
None
6
BOOST1H
Boost1 Voltage Monitor
No
VBOOST1 < 23.6 V
None
7
BOOST2H
Boost2 Voltage Monitor
No
VBOOST2 < 23.6 V
None
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
35
A8302
Dual LNB Supply and Control Voltage Regulators
Application Information
VIN
10uH
C22
1.0u
1206:25V
C1
100u
1uH
L5
B 340A
L1
D 3a
C18
1uF 1206 50V
C2 B 350A
100u
D1
C12
220nF
GND
19
RSET1
37.4K
GND
5V
20
RSET2
37.4K
GND
26
25
GND
RT2
10k
RT1
10k
28
0
Vin W1
Jumper
R12a
102k
32
TDI2
3CTC A P1
GND
100nF
R18
15
GND
BFGATE1
Q4
22
100nF
CTCA P2
GND R9
5
100
C11
10nF
1
G2
GND
12
NC
ISET2
LNB2
TDO1
BFGATE2
L NB2
7
2
3
4
5
R25
2.0
>40V <0.5ohms
BFGATE1
L3
220uH
DR1040-221-R
LNB
D2
B350A
6
TDO2
GND
PAD
27
GND
100nF
R2
15
LNB1
C21
10nF
G2
GND
J2
COAX-F
LNB1
1
LNB out2
D5
LNBTVS6-221S
R3
2.0
>40V <0.5ohms
C16
100nF
GND
10uH
C20
220nF
0805
pads
C19
Q1
Vreg
L4
LNB out1
D4
LNBTVS6-221S
LNB out2
C17
100u
VIN
100nF
ISET1
Jumper
EPF
C10a
100nF
GND
BOOST1
1
VREG
W2
EPF
VCP1
TCAP2
ADD
GND
R11a
205k
BFGATE1
SLEEP
21
C8
220nF
0805
pads
C7
J1
COAX-F
LNB1
LNB1
C9
10nF
2
3
4
5
24
GND
TCAP1
BOOST2
15
L2
220uH
DR1040-221-R
LNB
L NB1
2
9
SLEEP\
SW2
TCTRL2
VCP2
23
LNB out1
D3
B350A
8
18
TCTRL2
LNB1
R5 C5
100 10nF
4
A8302
TCTRL1
GNDLX2
17
TCTRL1
SDA
SCL
IRQ
10
5V
U1
A 8302
TDI1
LX2
SDA
SCL
IRQ
VIN
11
14
13
16
GNDLX1
LX1
29
EPF
C4
100nF
R1
10k
31
30
C3 100nF
D6
B 340A
L6
1uH
C10
1uF 1206 50V
D 3b
B 350A
PGN D and GN D form a single point ground at U 1
See table 6 for bill of materials
Schematic 1. A8302 application circuit using electrolytic capacitors on
BOOST and 563 kHz switching frequency. IOUT(max) = 800 mA.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
36
A8302
Dual LNB Supply and Control Voltage Regulators
Table 6. Component Selection Table for Schematic 1
Reference
Designators
Description
Footprint
Qty.
Manufacturer
Manufacturer P/N
Purchase P/N
Electrolytic Capacitor, 100 µF, 35 V,
8x10.2 mm, ESR=80 mΩ, Iripple = 850 mA
SMT
8 mm x
10.2 mm
3
Panasonic
EEE-FP1V101AP
PCE4442CT-ND
Capacitor, Ceramic, 100 nF, 25 V, 10%, X7R
0603
8
Murata
Panasonic
GRM188R71H104KA93D
ECJ-1VB1E104K
490-1519-1-ND
PCC2277CT-ND
Capacitor, Ceramic, 10 nF, 50 V, 10%, X7R
Capacitor, Ceramic, 220 nF, 25 V, 10%, X7R
Capacitor, Ceramic, 1 µF, 25 V, 10%, X5R
Capacitor, Ceramic, 1 µF, 50 V, 10%, X7R
0603
0603
0603
1206
4
3
1
2
D1,D6
Schottky diode, 40 V, 3 A, 0.7 Vf at 10 A
SMA
1
D2,D3,D3a,D3b
Schottky diode, 50 V, 3 A
SMA
6
D4,D5
TVS, 20 Vrms at 1 µA, 3000 W, SMC
SMC
2
J1,J2
Connector, F-type, right angle, PCB mount
2
GRM188R71H103KA01D
TMK107B7224KA-T
TMK107BJ105KA-T
GRM31CR71H105KA61L
B340A-13-F
B340A-13-F
CMSH3-40MA
B350A-13-F
B350A-13-F
SMDJ20A
LNBTVS6-221S
LNBTVS6-221S
531-40047-3
490-1512-1-ND
587-1246-1-ND
587-1248-1-ND
490-3908-1-ND
B340A-FDICT-ND
621-B340A-F
Request samples
B350A-FDICT-ND
621-B350A-F
Request Samples
497-4998-1-ND
511-LNBTVS6-221S
523-531-40047-3
L1,L4
Inductor, 10 µH, ±30%, 3.8 Arms 4.4 Asat ,
26 mΩ
2
Cooper Bussman DR1040-100-R
L2,L3
Inductor, 220 µH, ±30%, 0.92 Asat , 530 mΩ
Thru-Hole
10.3 mm x
10.5 mm x
4 mm
10.3 mm x
10.5 mm x
4 mm
Murata
Taiyo Yuden
Taiyo Yuden
Murata
Diodes, Inc.
Diodes, Inc.
Central Semi
Diodes, Inc.
Diodes, Inc.
Littelfuse
ST
ST
Amphenol
2
Cooper Bussman DR1040-221-R
513-1408-1-ND
704-DR1040-221-R
L5,L6
Inductor, 1 µH, ±20%, 1.0 A (min), <100 mΩ
Note: Not Required with Ceramic Capacitor
option
1206
2
Q1,Q4
PMOS, ENH, 60 V, 1.5 A, 0.45 Ω at 4.5 V
SOT23
2
Kemet
Murata
TDK
Vishay
Diodes, Inc
LB3218-T1R0MK
LQM31PN1R0M00L
MLP3216S1R0L
SI2309DS-T1-E3
ZXMP6A13FTA
80-LB3218-T1R0MK
490-4039-1-ND
Request Samples
SI2309DS-T1-E3CT-ND
ZXMP6A13FCT-ND
R1,RT1,RT2
Resistor, 10 kΩ, 1/10 W, 1%, 0603
3
2
2
1
1
2
SDA01H0SBR
CKN9490CT-ND
PEC36SAAN
M20-9773646
S1012E-36-ND
855-M20-9773646
C1,C2,C17
C3,C4,C7,C16,C
19,C10a,CTCAP
1,CTCAP2,
C5,C9,C11,C21
C8,C12,C20
C22
C10,C18
R2,R18
Resistor, 15 Ω, 1/10 W, 1%, 0603
R3,R25
R5,R9
R11a
R12a
RSET1,RSET2
Resistor, 2 Ω, 1/10 W, 1% or 5%, 0603
Resistor, 100 Ω, 1/10 W, 1%, 0603
Resistor, 205 kΩ, 1/10 W, 1%, 0603
Resistor, 102 kΩ, 1/10 W, 1%, 0603
Resistor, 37.4 kΩ, 1/10 W, 1%, 0603
0603
0603 part
1206 pads
0603
0603
0603
0603
0603
SW2
DIP Switch, 1 pos
SMT
1
C&K
Components
U1
A8302, Dual LNB Supply and Control IC
MLP-32
5 mm x
5 mm
1
Allegro
MicroSystems
W1,W2
Header, 2-position, 0.1 spacing
Thru-Hole
2
Sullins
Harwin
513-1399-1-ND
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
37
A8302
Dual LNB Supply and Control Voltage Regulators
VIN
10uH
B 340A
L1
D 3a
D1
C1
2*4.7uF
C2
C18
1uF 1206 50V
B 350A
2*10uF or 3*4.7uF
19
RSET1
37.4K
GND
5V
20
RSET2
37.4K
GND
26
25
GND
RT2
10k
RT1
10k
28
0
R11a
205k
Jumper
R12a
102k
32
100nF
CTCA P2
GND R9
5
100
12
NC
LNB2
ISET2
TDO1
BFGATE2
C11
10nF
LNB
D2
B350A
6
GND
PAD
27
GND
R2
15
G2
GND
J2
COAX-F
LNB1
1
LNB out2
D5
LNBTVS6-221S
R3
2.0
>40V <0.5ohms
C16
100nF
10uH
D4
LNBTVS6-221S
R25
2.0
L3
BFGATE1
220uH
DR1040-221-R
LNB1
C21
C20
C19
220nF 10nF
0805
100nF
pads
Q1
Vreg
L4
G2
GND
>40V <0.5ohms
TDO2
GND
GND
L NB2
7
R18
15
Q4
22
2*10uF or 3*4.7uF
VIN
GND
LNB out2
Jumper
EPF
C10a
100nF
BFGATE1
LNB out1
2
3
4
5
BOOST1
TDI2
100nF
3 CTCA P1
GND
ISET1
W2
EPF
1
VREG
GND
Vin W1
VCP1
TCAP2
ADD
21
1
LNB1
C8
C9
220nF 10nF
0805
pads
C7
100nF
J1
COAX-F
LNB1
2
3
4
5
C12
220nF
GND
L2
220uH
DR1040-221-R
LNB
L NB1
2
BOOST2
24
GND
LNB out1
9
15
BFGATE1
SLEEP
VCP2
SLEEP\
SW2
TCAP1
8
23
C5
10nF
D3
B350A
TCTRL2
GNDLX2
18
TCTRL2
LNB1
R5
100
4
A8302
TCTRL1
10
17
TCTRL1
U1
A 8302
TDI1
SDA
SCL
IRQ
LX2
5V
N
11
14
13
16
SDA
SCL
IRQ
GNDLX1
LX1
29
EPF
C4
100nF
R1
10k
31
30
C3 100nF
D6
B 340A
C17
C10
1uF 1206 50V
D 3b
B 350A
PGN D and GN D form a single point ground at U 1
See table 7 for bill of materials
Schematic 2. A8302 application circuit using ceramic capacitors on
BOOST and 563 kHz switching frequency. IOUT(max) = 800 mA.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
38
A8302
Dual LNB Supply and Control Voltage Regulators
Table 7. Component Selection Table for Schematic 2
Reference
Designators
Description
Footprint
Qty.
Manufacturer
Manufacturer P/N
Purchase P/N
Murata
TDK
AVX
Murata
GRM31CR71E475KA88L
C3216X7R1E475K
12063C475KAT2A
GRM32ER7YA106KA12L
490-1809-1-ND
445-1606-1-ND
478-5996-1-ND
490-5314-1-ND
Murata
Panasonic
GRM188R71H104KA93D
ECJ-1VB1E104K
490-1519-1-ND
PCC2277CT-ND
2
Murata
Taiyo Yuden
Taiyo Yuden
Murata
Diodes, Inc.
Diodes, Inc.
Central Semi
Diodes, Inc.
Diodes, Inc.
Littelfuse
ST
ST
Amphenol
GRM188R71H103KA01D
TMK107B7224KA-T
TMK107BJ105KA-T
GRM31CR71H105KA61L
B340A-13-F
B340A-13-F
CMSH3-40MA
B350A-13-F
B350A-13-F
SMDJ20A
LNBTVS6-221S
LNBTVS6-221S
531-40047-3
490-1512-1-ND
587-1246-1-ND
587-1248-1-ND
490-3908-1-ND
B340A-FDICT-ND
621-B340A-F
Request samples
B350A-FDICT-ND
621-B350A-F
Request Samples
497-4998-1-ND
511-LNBTVS6-221S
523-531-40047-3
2
Cooper Bussman DR1040-100-R
2
Cooper Bussman DR1040-221-R
513-1408-1-ND
704-DR1040-221-R
SOT23
2
Vishay
Diodes, Inc
SI2309DS-T1-E3
ZXMP6A13FTA
SI2309DS-T1-E3CT-ND
ZXMP6A13FCT-ND
3
2
2
2
1
2
SDA01H0SBR
CKN9490CT-ND
PEC36SAAN
M20-9773646
S1012E-36-ND
855-M20-9773646
C1
Capacitor, Ceramic, 4.7 µF, 25 V, 10%, X7R
1206
2
C2,C17
C3,C4,C7,C16,C
19,C10a,CTCAP
1,CTCAP2,
C5,C9,C11,C21
C8,C12,C20
C22
C10,C18
Capacitor, Ceramic, 10 µF, 35 V, 10%, X7R
1210
4
Capacitor, Ceramic, 100 nF, 25 V, 10%, X7R
0603
8
Capacitor, Ceramic, 10 nF, 50 V, 10%, X7R
Capacitor, Ceramic, 220 nF, 25 V, 10%, X7R
Capacitor, Ceramic, 1 µF, 25 V, 10%, X5R
Capacitor, Ceramic, 1 µF, 50 V, 10%, X7R
0603
0603
0603
1206
4
3
1
2
D1,D6
Schottky diode, 40 V, 3 A, 0.7 Vf at 10 A
SMA
1
D2,D3,D3a,D3b
Schottky diode, 50 V, 3 A
SMA
6
D4,D5
TVS, 20 Vrms at 1 µA, 3000 W, SMC
SMC
2
J1,J2
Connector, F-type, right angle, PCB mount
L1,L4
Inductor, 10 µH, ±30%, 3.8 Arms, 4.4 Asat ,
26 mΩ
L2,L3
Inductor, 220 µH, ±30%, 0.92 Asat , 530 mΩ
Thru-Hole
10.3 mm x
10.5 mm x
4 mm
10.3 mm x
10.5 mm x
4 mm
Q1,Q4
PMOS, ENH, 60 V, 1.5 A, 0.45 Ω at 4.5 V
R1,RT1,RT2
Resistor, 10 kΩ, 1/10 W, 1%, 0603
R2,R18
Resistor, 15 Ω, 1/10 W, 1%, 0603
R3,R25
R5,R9
R11a
R12a
RSET1,RSET2
Resistor, 2 Ω, 1/10 W, 1% or 5%, 0603
Resistor, 100 Ω, 1/10 W, 1%, 0603
Resistor, 205 kΩ, 1/10 W, 1%, 0603
Resistor, 102 kΩ, 1/10 W, 1%, 0603
Resistor, 37.4 kΩ, 1/10 W, 1%, 0603
0603
0603 part
1206 pads
0603
0603
0603
0603
0603
SW2
DIP Switch, 1 pos
SMT
1
C&K
Components
U1
A8302, Dual LNB Supply and Control IC
MLP-32
5 mm x
5 mm
1
Allegro
MicroSystems
W1,W2
Header, 2-position, 0.1 spacing
Thru-Hole
2
Sullins
Harwin
513-1399-1-ND
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
39
A8302
Dual LNB Supply and Control Voltage Regulators
VIN
4.7uH
B 140
L1
D1
C22
1.0u
1206:
25V
C1
100u
1uH
L5
D 3a
C18
1uF 1206 50V
C2 B350A
100u
GND
19
RSET1
60K
GND
5V
20
RSET2
60K
GND
26
25
GND
RT2
10k
RT1
10k
28
0
R11a
205k
Jumper
R12a
102k
32
12
NC
ISET2
LNB2
TDO1
BFGATE2
100nF
CTCA P2
GND R9
5
100
C11
10nF
L NB2
7
GND
PAD
27
GND
LNB out1
D4
LNBTVS6-221S
R25
2.0
C20
C21
220nF 10nF
0805
pads
C19
100nF
R2
15
Q1
Vreg
G2
GND
J2
COAX-F
LNB1
1
LNB out2
D5
LNBTVS6-221S
R3
2.0
>40V <0.5ohms
C16
100nF
GND
L4
4.7uH
G2
GND
L3
BFGATE1
220uH
DR1040-221-R
LNB1
LNB
D2
B350A
6
1
>40V <0.5ohms
TDO2
C17
100u
VIN
Q4
22
LNB out2
Jumper
EPF
C10a
100nF
R18
15
GND
BFGATE1
J1
COAX-F
LNB1
LNB1
C9
10nF
2
3
4
5
BOOST1
1
TDI2
100nF
L2
220uH
DR1040-221-R
C8
C7
220nF
0805
100nF
pads
ISET1
W2
EPF
VCP1
VREG
GND
Vin W1
LNB
2
3
4
5
C12
220nF
TCAP2
ADD
21
3 CTCAP1
GND
BOOST2
24
GND
LNB out1
L NB1
2
9
15
BFGATE1
SLEEP
VCP2
SLEEP\
SW2
TCAP1
8
23
C5
10nF
D3
B350A
TCTRL2
GNDLX2
18
TCTRL2
LNB1
R5
100
4
A8302
TCTRL1
10
17
TCTRL1
U1
A 8302
TDI1
SDA
SCL
IRQ
LX2
5V
VIN
11
14
13
16
SDA
SCL
IRQ
GNDLX1
LX1
29
EPF
C4
100nF
R1
10k
31
30
C3 100nF
D6
B 140
L6
1uH
C10
1uF 1206 50V
D 3b
B 350A
GND
PGN D and GN D form a single point ground at U 1
See table 8 for bill of materials
Schematic 3. A8302 application circuit using electrolytic capacitors on
BOOST and 939 kHz switching frequency. Iout(max) = 500 mA.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
40
A8302
Dual LNB Supply and Control Voltage Regulators
Table 8. Component Selection Table for Schematic 3
Reference
Designators
Footprint
Qty.
Electrolytic Capacitor, 100 µF, 25 V,
6x11.2 mm, ESR ≤ 130 mΩ, Iripple ≥ 450 mA,
Thru-hole
6 mm
diameter,
2.5 or
3.5 mm lead
spacing
3
Panasonic
EEU-FM1E101
P12924-ND
Capacitor, Ceramic, 100 nF, 25 V, 10%, X7R
0603
8
Murata
Panasonic
GRM188R71H104KA93D
ECJ-1VB1E104K
490-1519-1-ND
PCC2277CT-ND
Capacitor, Ceramic, 10 nF, 50 V, 10%, X7R
Capacitor, Ceramic, 220 nF, 25 V, 10%, X7R
Capacitor, Ceramic, 1 µF, 25 V, 10%, X5R
Capacitor, Ceramic, 1 µF, 50 V, 10%, X7R
0603
0603
0603
1206
4
3
1
2
D1,D6
Schottky diode, 40 V, 1 A
SOD-123
1
D2,D3,D3a,D3b
Schottky diode, 50 V, 3 A
SMA
6
D4,D5
TVS, 20 Vrms at 1 µA, 3000 W, SMC
SMC
2
J1,J2
Connector, F-type, right angle, PCB mount
2
GRM188R71H103KA01D
TMK107B7224KA-T
TMK107BJ105KA-T
GRM31CR71H105KA61L
B140HW-7
CMMSH1-40
B350A-13-F
B350A-13-F
SMDJ20A
LNBTVS6-221S
LNBTVS6-221S
531-40047-3
490-1512-1-ND
587-1246-1-ND
587-1248-1-ND
490-3908-1-ND
B140HWDICT-ND
Request Samples
B350A-FDICT-ND
621-B350A-F
Request Samples
497-4998-1-ND
511-LNBTVS6-221S
523-531-40047-3
L1,L4
Inductor, 4.7 µH, ±20%, 2.9 Arms, 3.5 Asat ,
33 mΩ
2
Cooper Bussman DRA73-4R7-R
L2,L3
Inductor, 220 µH, ±30%, 0.92 Asat , 530 mΩ
Thru-Hole
7.60 mm x
7.60 mm x
3.55 mm
10.3 mm x
10.5 mm x
4 mm
Murata
Taiyo Yuden
Taiyo Yuden
Murata
Diodes, Inc
Central Semi
Diodes, Inc.
Diodes, Inc.
Littelfuse
ST
ST
Amphenol
2
Cooper Bussman DR1040-221-R
513-1408-1-ND
704-DR1040-221-R
L5,L6
Inductor, 1 µH, ±20%, 1.0 A(min), <100 mΩ
Note: Not Required with Ceramic Capacitor
option
1206
2
Q1,Q4
PMOS, ENH, 60 V, 1.5 A, 0.45 Ω at 4.5 V
SOT23
2
Kemet
Murata
TDK
Vishay
Diodes, Inc
LB3218-T1R0MK
LQM31PN1R0M00L
MLP3216S1R0L
SI2309DS-T1-E3
ZXMP6A13FTA
80-LB3218-T1R0MK
490-4039-1-ND
Request Samples
SI2309DS-T1-E3CT-ND
ZXMP6A13FCT-ND
R1,RT1,RT2
Resistor, 10 kΩ, 1/10 W, 1%, 0603
3
2
2
1
1
2
SDA01H0SBR
CKN9490CT-ND
PEC36SAAN
M20-9773646
S1012E-36-ND
855-M20-9773646
C1,C2,C17
C3,C4,C7,C16,C
19,C10a,CTCAP
1,CTCAP2,
C5,C9,C11,C21
C8,C12,C20
C22
C10,C18
Description
Manufacturer
R2,R18
Resistor, 15 Ω, 1/10 W, 1%, 0603
R3,R25
R5,R9
R11a
R12a
RSET1,RSET2
Resistor, 2 Ω, 1/10 W, 1% or 5%, 0603
Resistor, 100 Ω, 1/10 W, 1%, 0603
Resistor, 205 kΩ, 1/10 W, 1%, 0603
Resistor, 102 kΩ, 1/10 W, 1%, 0603
Resistor, 60 kΩ, 1/10 W, 1%, 0603
0603
0603 part
1206 pads
0603
0603
0603
0603
0603
SW2
DIP Switch, 1 pos
SMT
1
C&K
Components
U1
A8302, Dual LNB Supply & Control IC
MLP-32
5 mm x
5 mm
1
Allegro
MicroSystems
W1,W2
Header, 2-position, 0.1 spacing
Thru-Hole
2
Sullins
Harwin
Manufacturer P/N
Purchase P/N
283-3617-1-ND
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
41
A8302
Dual LNB Supply and Control Voltage Regulators
VIN
4.7uH
B 140
L1
D1
C1
2*4.7uF
D 3a
C2
C18
1uF 1206 50V
B 350A
2*10uF or 3*4.7uF
18
TCTRL2
23
32
D3
B350A
TCTRL2
TCAP1
SLEEP
GND
26
25
GND
RT2
10k
RT1
10k
28
0
R11a
205k
LNB2
TDO1
BFGATE2
GND
PAD
Jumper
R12a
102k
L4
4.7uH
GND
G2
GND
LNB1 1
J1
COAX-F
LNB out1
D4
L NBTVS6-221S
R25
2.0
>40V <0.5ohms
LNB
GND
L3
BFGATE1
220uH
DR1040-221-R
LNB1
C20
C21
C19
220nF 10nF
0805
100nF
pads
R2
15
Q1
G2
GND
LNB1 1
J2
COAX-F
LNB out2
D5
LNBTVS6-221S
R3
2.0
>40V <0.5ohms
C16
100nF
GND
LNB1
C9
10nF
R18
15
C11
10nF
D2
B350A
6
2*10uF or 3*4.7uF
VIN
L NB2
7
Vreg
Jumper
EPF
C10a
100nF
100nF
CTCA P2
GND R9
5
100
L2
220uH
DR1040-221-R
C8
C7
220nF
0805
100nF
pads
Q4
22
TDO2
W2
EPF
12
NC
ISET2
GND
Vin W1
GND
BFGATE1
LNB out2
VCP2
5V
RSET2
60K
TDI2
8
GND
20
100nF
ISET1
GNDLX2
RSET1
60K
VREG
10
19
LX2
GND
27
GND
TCAP2
ADD
11
24
C12
220nF
21
CTCA P1
3
BFGATE1
GND
EPF
15
LNB
A8302
TCTRL1
SL EEP\
SW2
LNB out1
L NB1
2
2
3
4
5
BOOST1
1
LNB1
C5
10nF
2
3
4
5
17
TCTRL1
TDI1
SDA
SCL
IRQ
R5
100
4
BOOST2
5V
VIN
U1
A 8302
9
14
13
16
SDA
SCL
IRQ
VCP1
29
G NDLX1
LX1
C4
100nF
R1
10k
31
30
C3 100nF
D6
B 140
C17
C10
1uF 1206 50V
D 3b
B 350A
PGN D and GN D form a single point ground at U 1
See table 9 for bill of materials
Schematic 4. A8302 application circuit using ceramic capacitors on
BOOST and 939 kHz switching frequency . Iout(max) = 500 mA.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
42
A8302
Dual LNB Supply and Control Voltage Regulators
Table 9. Component Selection Table for Schematic 4
Reference
Designators
Description
Footprint
Qty.
Manufacturer
Manufacturer P/N
Purchase P/N
Murata
TDK
AVX
Murata
GRM31CR71E475KA88L
C3216X7R1E475K
12063C475KAT2A
GRM32ER7YA106KA12L
490-1809-1-ND
445-1606-1-ND
478-5996-1-ND
490-5314-1-ND
Murata
Panasonic
GRM188R71H104KA93D
ECJ-1VB1E104K
490-1519-1-ND
PCC2277CT-ND
2
Murata
Taiyo Yuden
Taiyo Yuden
Murata
Diodes, Inc
Central Semi
Diodes, Inc.
Diodes, Inc.
Littelfuse
ST
ST
Amphenol
GRM188R71H103KA01D
TMK107B7224KA-T
TMK107BJ105KA-T
GRM31CR71H105KA61L
B140HW-7
CMMSH1-40
B350A-13-F
B350A-13-F
SMDJ20A
LNBTVS6-221S
LNBTVS6-221S
531-40047-3
490-1512-1-ND
587-1246-1-ND
587-1248-1-ND
490-3908-1-ND
B140HWDICT-ND
Request Samples
B350A-FDICT-ND
621-B350A-F
Request Samples
497-4998-1-ND
511-LNBTVS6-221S
523-531-40047-3
2
Cooper Bussman DRA73-4R7-R
2
Cooper Bussman DR1040-221-R
513-1408-1-ND
704-DR1040-221-R
SOT23
2
Vishay
Diodes, Inc
SI2309DS-T1-E3
ZXMP6A13FTA
SI2309DS-T1-E3CT-ND
ZXMP6A13FCT-ND
3
2
2
2
1
2
SDA01H0SBR
CKN9490CT-ND
PEC36SAAN
M20-9773646
S1012E-36-ND
855-M20-9773646
C1
Capacitor, Ceramic, 4.7 µF, 25 V, 10%, X7R
1206
2
C2,C17
C3,C4,C7,C16,C
19,C10a,CTCAP
1,CTCAP2,
C5,C9,C11,C21
C8,C12,C20
C22
C10,C18
Capacitor, Ceramic, 10 µF, 35 V, 10%, X7R
1210
4
Capacitor, Ceramic, 100 nF, 25 V, 10%, X7R
0603
8
Capacitor, Ceramic, 10 nF, 50 V, 10%, X7R
Capacitor, Ceramic, 220 nF, 25 V, 10%, X7R
Capacitor, Ceramic, 1 µF, 25 V, 10%, X5R
Capacitor, Ceramic, 1 µF, 50 V, 10%, X7R
0603
0603
0603
1206
4
3
1
2
D1,D6
Schottky diode, 40 V, 1 A
SOD-123
1
D2,D3,D3a,D3b
Schottky diode, 50 V, 3 A
SMA
6
D4,D5
TVS, 20 Vrms at 1 µA, 3000 W, SMC
SMC
2
J1,J2
Connector, F-type, right angle, PCB mount
L1,L4
Inductor, 4.7 µH, ±20%, 2.9 Arms, 3.5 Asat ,
33 mΩ
L2,L3
Inductor, 220 µH, ±30%, 0.92 Asat , 530 mΩ
Thru-Hole
7.60 mm x
7.60 mm x
3.55 mm
10.3 mm x
10.5 mm x
4 mm
Q1,Q4
PMOS, ENH, 60 V, 1.5 A, 0.45 Ω at 4.5 V
R1,RT1,RT2
Resistor, 10 kΩ, 1/10 W, 1%, 0603
R2,R18
Resistor, 15 Ω, 1/10 W, 1%, 0603
R3,R25
R5,R9
R11a
R12a
RSET1,RSET2
Resistor, 2 Ω, 1/10 W, 1% or 5%, 0603
Resistor, 100 Ω, 1/10 W, 1%, 0603
Resistor, 205 kΩ, 1/10 W, 1%, 0603
Resistor, 102 kΩ, 1/10 W, 1%, 0603
Resistor, 60 kΩ, 1/10 W, 1%, 0603
0603
0603 part
1206 pads
0603
0603
0603
0603
0603
SW2
DIP Switch, 1 pos
SMT
1
C&K
Components
U1
A8302, Dual LNB Supply amd Control IC
MLP-32
5 mm x
5 mm
1
Allegro
MicroSystems
W1,W2
Header, 2-position, 0.1 spacing
Thru-Hole
2
Sullins
Harwin
283-3617-1-ND
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
43
A8302
Dual LNB Supply and Control Voltage Regulators
Package ET 32-Pin QFN
with Exposed Thermal Pad
For Reference Only – Not for Tooling Use
(Reference JEDEC MO-220VHHD-5)
Dimensions in millimeters – NOT TO SCALE
Exact case and lead configuration at supplier discretion within limits shown
0.30
5.00 ±0.05
0.50
32
32
1.00
1
1
2
2
A
5.00 ±0.05
3.40
5.00
1
33X
D
C
3.40
0.90 ±0.10
0.08
C
5.00
SEATING
PLANE
0.25
+0.05
-0.07
0.50 BSC
C
0.40 ±0.10
PCB Layout Reference View
A
Terminal #1 mark area
B
Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier
discretion)
C
Reference land pattern layout (reference IPC7351 QFN50P500X500X100-33V6M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet
application process requirements and PCB layout tolerances; when mounting on a
multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
D
Coplanarity includes exposed thermal pad and terminals
3.40
B
2
1
32
3.40
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
44
A8302
Dual LNB Supply and Control Voltage Regulators
I2C™ is a trademark of Philips Semiconductors.
DiSEqC™ is a trademark of Eutelsat S.A.
Copyright ©2012-2014, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
45
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