Data Sheet

DISCRETE SEMICONDUCTORS
DATA SHEET
PDTA144T series
PNP resistor-equipped transistors;
R1 = 47 kΩ, R2 = open
Product data sheet
Supersedes data of 2004 Apr 27
2004 Aug 05
NXP Semiconductors
Product data sheet
PNP resistor-equipped transistors;
R1 = 47 kΩ, R2 = open
PDTA144T series
FEATURES
QUICK REFERENCE DATA
• Built-in bias resistors
SYMBOL
• Simplified circuit design
VCEO
• Reduction of component count
• Reduced pick and place costs.
APPLICATIONS
PARAMETER
TYP.
MAX.
UNIT
collector-emitter
voltage
−
−50
V
IO
output current (DC)
−
−100
mA
R1
bias resistor
47
−
kΩ
R2
open
−
−
−
• General purpose switching and amplification
• Inverter and interface circuits
DESCRIPTION
• Circuit driver.
PNP resistor-equipped transistor (see “Simplified outline,
symbol and pinning” for package details).
PRODUCT OVERVIEW
PACKAGE
TYPE NUMBER
MARKING CODE
NPN COMPLEMENT
PHILIPS
EIAJ
PDTA144TE
SOT416
SC-75
5B
PDTC144TE
PDTA144TEF
SOT490
SC-89
2M
PDTC144TEF
PDTA144TK
SOT346
SC-59
58
PDTC144TK
PDTA144TM
SOT883
SC-101
F9
PDTC144TM
PDTA144TS
SOT54 (TO-92)
SC-43
TA144T
PDTC144TS
PDTA144TT
SOT23
−
*AF(1)
PDTC144TT
PDTA144TU
SOT323
SC-70
*7A(1)
PDTC144TU
Note
1. * = p: Made in Hong Kong.
* = t: Made in Malaysia.
* = W: Made in China.
2004 Aug 05
2
NXP Semiconductors
Product data sheet
PNP resistor-equipped transistors;
R1 = 47 kΩ, R2 = open
PDTA144T series
SIMPLIFIED OUTLINE, SYMBOL AND PINNING
PINNING
TYPE NUMBER
SIMPLIFIED OUTLINE AND SYMBOL
PIN
PDTA144TS
handbook, halfpage
DESCRIPTION
1
base
2
collector
3
emitter
1
base
2
emitter
3
collector
1
base
2
emitter
3
collector
2
1
R1
1
2
3
3
MAM352
PDTA144TE
PDTA144TEF
PDTA144TK
handbook, halfpage
3
3
R1
PDTA144TT
1
PDTA144TU
1
2
2
Top view
MDB272
PDTA144TM
handbook, halfpage
3
R1
2
3
1
1
2
Bottom view
MDB268
2004 Aug 05
3
NXP Semiconductors
Product data sheet
PNP resistor-equipped transistors;
R1 = 47 kΩ, R2 = open
PDTA144T series
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
DESCRIPTION
VERSION
PDTA144TE
−
plastic surface mounted package; 3 leads
SOT416
PDTA144TEF
−
plastic surface mounted package; 3 leads
SOT490
PDTA144TK
−
plastic surface mounted package; 3 leads
SOT346
PDTA144TM
−
leadless ultra small plastic package; 3 solder lands;
body 1.0 × 0.6 × 0.5 mm
SOT883
PDTA144TS
−
plastic single-ended leaded (through hole) package; 3 leads
SOT54
PDTA144TT
−
plastic surface mounted package; 3 leads
SOT23
PDTA144TU
−
plastic surface mounted package; 3 leads
SOT323
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCBO
collector-base voltage
open emitter
−
−50
V
VCEO
collector-emitter voltage
open base
−
−50
V
VEBO
emitter-base voltage
open collector
−
−5
V
IO
output current (DC)
−
−100
mA
ICM
peak collector current
−
−100
mA
Ptot
total power dissipation
Tamb ≤ 25 °C
SOT23
note 1
−
250
mW
SOT54
note 1
−
500
mW
SOT323
note 1
−
200
mW
SOT346
note 1
−
250
mW
SOT416
note 1
−
150
mW
SOT490
notes 1 and 2
−
250
mW
SOT883
notes 2 and 3
−
250
mW
Tstg
storage temperature
−65
+150
°C
Tj
junction temperature
−
150
°C
Tamb
operating ambient temperature
−65
+150
°C
Notes
1. Refer to standard mounting conditions.
2. Reflow soldering is the only recommended soldering method.
3. Refer to SOT883 standard mounting conditions; FR4 with 60 μm copper strip line.
2004 Aug 05
4
NXP Semiconductors
Product data sheet
PNP resistor-equipped transistors;
R1 = 47 kΩ, R2 = open
PDTA144T series
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
VALUE
UNIT
in free air
SOT23
note 1
500
K/W
SOT54
note 1
250
K/W
SOT323
note 1
625
K/W
SOT346
note 1
500
K/W
SOT416
note 1
833
K/W
SOT490
notes 1 and 2
500
K/W
SOT883
notes 2 and 3
500
K/W
Notes
1. Refer to standard mounting conditions.
2. Reflow soldering is the only recommended soldering method.
3. Refer to SOT883 standard mounting conditions; FR4 with 60 μm copper strip line.
CHARACTERISTICS
Tamb = 25 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ICBO
collector-base cut-off current
VCB = −50 V; IE = 0 A
−
−
−100
nA
ICEO
collector-emitter cut-off current
VCE = −30 V; IB = 0 A
−
−
−1
μA
VCE = −30 V; IB = 0; Tj = 150 °C
−
−
−50
μA
nA
IEBO
emitter-base cut-off current
VEB = −5 V; IC = 0 A
−
−
−100
hFE
DC current gain
VCE = −5 V; IC = −1 mA
100
−
−
VCEsat
collector-emitter saturation voltage IC = −10 mA; IB = −0.5 mA
−
−
−150
mV
R1
input resistor
33
47
61
kΩ
Cc
collector capacitance
−
−
3
pF
2004 Aug 05
IE = ie = 0; VCB = −10 V;
f = 1 MHz
5
NXP Semiconductors
Product data sheet
PNP resistor-equipped transistors;
R1 = 47 kΩ, R2 = open
PDTA144T series
PACKAGE OUTLINES
Plastic single-ended leaded (through hole) package; 3 leads
SOT54
c
E
d
A
L
b
1
e1
2
D
e
3
b1
L1
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
b
b1
c
D
d
E
mm
5.2
5.0
0.48
0.40
0.66
0.55
0.45
0.38
4.8
4.4
1.7
1.4
4.2
3.6
e
2.54
e1
L
L1(1)
1.27
14.5
12.7
2.5
max.
Note
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
SOT54
2004 Aug 05
REFERENCES
IEC
JEDEC
JEITA
TO-92
SC-43A
6
EUROPEAN
PROJECTION
ISSUE DATE
04-06-28
04-11-16
NXP Semiconductors
Product data sheet
PNP resistor-equipped transistors;
R1 = 47 kΩ, R2 = open
PDTA144T series
Plastic surface-mounted package; 3 leads
SOT23
D
E
B
A
X
HE
v M A
3
Q
A
A1
1
2
e1
bp
c
w M B
Lp
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max.
bp
c
D
E
e
e1
HE
Lp
Q
v
w
mm
1.1
0.9
0.1
0.48
0.38
0.15
0.09
3.0
2.8
1.4
1.2
1.9
0.95
2.5
2.1
0.45
0.15
0.55
0.45
0.2
0.1
OUTLINE
VERSION
SOT23
2004 Aug 05
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-11-04
06-03-16
TO-236AB
7
NXP Semiconductors
Product data sheet
PNP resistor-equipped transistors;
R1 = 47 kΩ, R2 = open
PDTA144T series
Plastic surface-mounted package; 3 leads
SOT346
E
D
A
B
X
HE
v M A
3
Q
A
A1
1
c
2
e1
bp
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
bp
c
D
E
e
e1
HE
Lp
Q
v
w
mm
1.3
1.0
0.1
0.013
0.50
0.35
0.26
0.10
3.1
2.7
1.7
1.3
1.9
0.95
3.0
2.5
0.6
0.2
0.33
0.23
0.2
0.2
OUTLINE
VERSION
SOT346
2004 Aug 05
REFERENCES
IEC
JEDEC
JEITA
TO-236
SC-59A
8
EUROPEAN
PROJECTION
ISSUE DATE
04-11-11
06-03-16
NXP Semiconductors
Product data sheet
PNP resistor-equipped transistors;
R1 = 47 kΩ, R2 = open
PDTA144T series
Plastic surface-mounted package; 3 leads
SOT323
D
E
B
A
X
HE
y
v M A
3
Q
A
A1
c
1
2
e1
bp
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E
e
e1
HE
Lp
Q
v
w
mm
1.1
0.8
0.1
0.4
0.3
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.23
0.13
0.2
0.2
OUTLINE
VERSION
SOT323
2004 Aug 05
REFERENCES
IEC
JEDEC
JEITA
SC-70
9
EUROPEAN
PROJECTION
ISSUE DATE
04-11-04
06-03-16
NXP Semiconductors
Product data sheet
PNP resistor-equipped transistors;
R1 = 47 kΩ, R2 = open
PDTA144T series
Plastic surface-mounted package; 3 leads
SOT416
D
E
B
A
X
HE
v M A
3
Q
A
1
A1
2
e1
c
bp
w M B
Lp
e
detail X
0
0.5
1 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E
e
e1
HE
Lp
Q
v
w
mm
0.95
0.60
0.1
0.30
0.15
0.25
0.10
1.8
1.4
0.9
0.7
1
0.5
1.75
1.45
0.45
0.15
0.23
0.13
0.2
0.2
OUTLINE
VERSION
SOT416
2004 Aug 05
REFERENCES
IEC
JEDEC
JEITA
SC-75
10
EUROPEAN
PROJECTION
ISSUE DATE
04-11-04
06-03-16
NXP Semiconductors
Product data sheet
PNP resistor-equipped transistors;
R1 = 47 kΩ, R2 = open
PDTA144T series
Plastic surface-mounted package; 3 leads
SOT490
D
E
B
A
X
HE
v M A
3
A
1
c
2
e1
bp
w M B
Lp
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
bp
c
D
E
e
e1
HE
Lp
v
w
mm
0.8
0.6
0.33
0.23
0.2
0.1
1.7
1.5
0.95
0.75
1.0
0.5
1.7
1.5
0.5
0.3
0.1
0.1
OUTLINE
VERSION
SOT490
2004 Aug 05
REFERENCES
IEC
JEDEC
JEITA
SC-89
11
EUROPEAN
PROJECTION
ISSUE DATE
05-07-28
06-03-16
NXP Semiconductors
Product data sheet
PNP resistor-equipped transistors;
R1 = 47 kΩ, R2 = open
PDTA144T series
Leadless ultra small plastic package; 3 solder lands; body 1.0 x 0.6 x 0.5 mm
L
SOT883
L1
2
b
3
e
b1
1
e1
A
A1
E
D
0
0.5
1 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A (1)
A1
max.
b
b1
D
E
e
e1
L
L1
mm
0.50
0.46
0.03
0.20
0.12
0.55
0.47
0.62
0.55
1.02
0.95
0.35
0.65
0.30
0.22
0.30
0.22
Note
1. Including plating thickness
OUTLINE
VERSION
SOT883
2004 Aug 05
REFERENCES
IEC
JEDEC
JEITA
SC-101
12
EUROPEAN
PROJECTION
ISSUE DATE
03-02-05
03-04-03
NXP Semiconductors
Product data sheet
PNP resistor-equipped transistors;
R1 = 47 kΩ, R2 = open
PDTA144T series
DATA SHEET STATUS
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2)
DEFINITION
Objective data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary data sheet
Qualification
This document contains data from the preliminary specification.
Product data sheet
Production
This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
above those given in the Characteristics sections of this
document is not implied. Exposure to limiting values for
extended periods may affect device reliability.
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does not give any representations or warranties,
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Quick reference data ⎯ The Quick reference data is an
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Characteristics sections of this document, and as such is
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Applications ⎯ Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values ⎯ Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) may cause permanent damage to
the device. Limiting values are stress ratings only and
operation of the device at these or any other conditions
2004 Aug 05
13
NXP Semiconductors
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
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Printed in The Netherlands
R75/03/pp14
Date of release: 2004 Aug 05
Document order number: 9397 750 13661