ISL97536 ® Data Sheet November 2, 2007 Monolithic 1A Step-Down Regulator with Low Quiescent Current The ISL97536 is a synchronous, integrated FET 1A step-down regulator with internal compensation. It operates with an input voltage range from 2.5V to 6V, which accommodates supplies of 3.3V, 5V, or a Li-ion battery source. The output can be externally set from 0.8V to VIN with a resistive divider. The ISL97536 features PWM control with a 1.4MHz typical switching frequency. The typical no load quiescent current is only 500µA. Additional features include a 100ms Power-OnReset output, <1µA shutdown current, short-circuit protection, and over-temperature protection. Features • Less than 0.15in2 footprint for the complete 1A converter • Components on one side of PCB • Max height 1.1mm MSOP10 • 100ms Power-On-Reset output (POR) • Internally-compensated voltage mode controller • Up to 95% efficiency • <1µA shutdown current • 500µA quiescent current • Hiccup mode overcurrent and over-temperature protection The ISL97536 is available in the 10 Ld MSOP package, making the entire converter occupy less than 0.15in2 of PCB area with components on one side only. The 10 Ld MSOP package is specified for operation over the full -40°C to +85°C temperature range. • Pb-free (RoHS compliant) Ordering Information • Cellular phones PART NUMBER (Note) FN6279.1 Applications • PDA and pocket PC computers • Bar code readers • Portable test equipment PART MARKING PACKAGE (Pb-Free) PKG. DWG. # • Li-ion battery powered devices ISL97536IUZ 7536Z 10 Ld MSOP MDP0043 • Small form factor (SFP) modules ISL97536IUZ-TK* 7536Z 10 Ld MSOP Tape and Reel MDP0043 Pinout and Typical Application Diagram ISL97536IUZ-T* 7536Z 10 Ld MSOP Tape and Reel MDP0043 ISL97536 (10 LD MSOP) TOP VIEW *Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. C1 10µF VO (1.8V@600mA) VS (2.5V-6V) C2 10µF L1 1.8µH R3 100Ω C3 0.1µF 1 SGND FB 10 2 PGND VO 9 3 LX POR 8 R2* 100kΩ R1* 124kΩ C4 470pF POR 4 VIN EN 7 EN 5 VDD RSI 6 RSI R6 100kΩ R4 100kΩ R5 100kΩ * VO = 0.8V * (1 + R1/R2) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL97536 Absolute Maximum Ratings (TA = +25°C) Thermal Information VIN, VDD, PG to SGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V) SYNC, EN, VO, FB to SGND . . . . . . . . . . . . . -0.3V to (VIN + +0.3V) PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A Thermal Resistance (Typical, Note 1) θJA (°C/W) 10 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . 130 Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VDD = VIN = VEN = 3.3V, C1 = C2 = 10µF, L = 1.8µH, VO = 1.8V (as shown in “Pinout and Typical Application Diagram” on page 1), TA = -40°C to +85°C unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 790 800 810 mV 250 nA 2.5 6 V DC CHARACTERISTICS VFB Feedback Input Voltage IFB Feedback Input Current VIN, VDD Input Voltage VIN,OFF Minimum Voltage for Shutdown VIN falling, TA = +25°C only 2 2.2 V VIN,ON Maximum Voltage for Start-up VIN rising, TA = +25°C only 2.2 2.4 V IDD Supply Current VIN = VDD = 5V 400 500 µA EN = 0, VIN = VDD = 5V 0.1 3 µA rDS(ON)-PMOS PMOS FET Resistance VDD = 5V, TA = +25°C 70 mΩ rDS(ON)-NMOS NMOS FET Resistance VDD = 5V, TA = +25°C 45 mΩ ILMAX Current Limit 1.5 A TOT,OFF Over-temperature Threshold T rising 145 °C TOT,ON Over-temperature Hysteresis T falling 130 °C IEN, IRSI EN, RSI Current VEN, VRSI = 0V and 3.3V VEN1, VRSI1 EN, RSI Rising Threshold VDD = 3.3V VEN2, VRSI2 EN, RSI Falling Threshold VDD = 3.3V VPOR Minimum VFB for POR, WRT Targeted VFB Value VFB rising POR Voltage Drop ISINK = 3.3mA VOLPOR VFB falling -1 1 µA 2.4 V 0.8 V 95 86 % % 35 70 mV 1.4 1.6 MHz 25 50 ns AC CHARACTERISTICS FPWM PWM Switching Frequency tRSI Minimum RSI Pulse Width tSS Soft-Start Time tPOR Power On Reset Delay Time 2 1.25 Guaranteed by design 650 80 100 µs 120 ms FN6279.1 November 2, 2007 ISL97536 Pin Descriptions PIN NUMBER PIN NAME PIN FUNCTION 1 SGND Negative supply for the controller stage 2 PGND Negative supply for the power stage 3 LX Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage 4 VIN Positive supply for the power stage 5 VDD Power supply for the controller stage 6 RSI Resets POR timer 7 EN Enable 8 POR 9 VO Output voltage sense 10 FB Voltage feedback input; connected to an external resistor divider between VO and SGND for variable output Power on reset open drain output Block Diagram 100Ω 0.1µF VDD VO + CURRENT SENSE 10pF C4 124k 470pF FB 5M + PWM COMPENSATION 100k CLOCK + PWM COMPARATOR RAMP GENERATOR VIN P-DRIVER LX CONTROL LOGIC 1.8µH 1.8V 0 TO 1A EN EN SOFTSTART 10µF 5V + – BANDGAP REFERENCE + PWM COMPARATOR UNDERVOLTAGE LOCKOUT TEMPERATURE SENSE SGND 10µF N-DRIVER + SYNCHRONOUS RECTIFIER PGND 100k POR POR POR RSI 3 FN6279.1 November 2, 2007 ISL97536 Performance Curves and Waveforms All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless otherwise noted. 100 100 90 90 VO = 2.5V VO = 3.3V VO = 1.8V 70 60 50 40 VO = 1.2V 30 60 50 30 10 10 400 600 IO (mA) 800 1000 VO = 1.2V 40 20 200 0 0 1200 0 600 IO (mA) 800 1000 1200 VO = 2.5V -0.2 VO = 3.3V -0.3 VO = 1.8V -0.4 -0.5 -0.6 VO = 2.5V -0.1 LOAD REGULATION (%) LOAD REGULATION (%) 400 0 -0.1 -0.2 VO = 1.8V -0.3 -0.4 VO = 1.2V -0.5 VO = 1.2V 0 200 400 600 IO (mA) 800 1000 -0.6 1200 FIGURE 3. LOAD REGULATION vs IO AT 5V VIN 0 200 400 600 IO (mA) 800 1000 1200 FIGURE 4. LOAD REGULATION vs IO AT 3.3V VIN 0 12 -0.1 10 -0.2 8 -0.3 -0.4 IS (mA) LINE REGULATION (%) 200 FIGURE 2. EFFICIENCY vs IO AT 3.3V FIGURE 1. EFFICIENCY vs IO AT 5V VIN -0.7 VO = 2.5V 70 20 0 0 VO = 1.8V 80 EFFICIENCY (%) EFFICIENCY (%) 80 VO = 1.2V -0.5 6 4 -0.6 2 VO = 1.8V -0.7 -0.8 2.0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) FIGURE 5. LINE REGULATION vs VIN 4 6.0 2.5 3 3.5 4 4.5 5 VS (V) FIGURE 6. NO LOAD QUIESCENT CURRENT FN6279.1 November 2, 2007 ISL97536 Performance Curves and Waveforms (Continued) All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 600mA with component values shown on page 1 at room ambient temperature, unless otherwise noted. LX (2V/DIV) VOUT IL (0.5A/DIV) VIN ΔVO (10mV/DIV) IIN 0.5µs/DIV FIGURE 8. PWM STEADY-STATE OPERATION (IO = 600mA) FIGURE 7. START-UP AT IO = 600mA IO (200mA/DIV) IO (200mA/DIV) ΔVO (100mV/DIV) ΔVO (100mV/DIV) 50µs/DIV 100µs/DIV FIGURE 9. LOAD TRANSIENT RESPONSE (22mA TO 600mA) FIGURE 10. LOAD TRANSIENT RESPONSE (30mA TO 600mA) PG PG IL IL VO VO FIGURE 11. OVERCURRENT SHUTDOWN 5 FIGURE 12. OVERCURRENT HICCUP MODE FN6279.1 November 2, 2007 ISL97536 Applications Information Product Description The ISL97536 is a synchronous, integrated FET 1A step-down regulator which operates from an input of 2.5V to 6V. The output voltage is user-adjustable with a pair of external resistors. The internally-compensated controller makes it possible to use only two ceramic capacitors and one inductor to form a complete, very small footprint 1A DC/DC converter. PWM Operation In PWM switching mode, the P-Channel MOSFET and N-Channel MOSFET always operate complementary. When the P-Channel MOSFET is on and the N-Channel MOSFET off, the inductor current increases linearly. The input energy is transferred to the output and also stored in the inductor. When the P-Channel MOSFET is off and the N-Channel MOSFET on, the inductor current decreases linearly, and energy is transferred from the inductor to the output. Hence, the average current through the inductor is the output current. Since the inductor and the output capacitor act as a low pass filter, the duty cycle ratio is approximately equal to VO divided by VIN. The output LC filter has a second order effect. To maintain the stability of the converter, the overall controller must be compensated. This is done with the fixed internally compensated error amplifier and the PWM compensator. Because the compensations are fixed, the values of input and output capacitors are 10µF to 40µF ceramic and inductor is 1.5µH to 2.2µH. Start-Up and Shutdown When the EN pin is tied to VIN, and VIN reaches approximately 2.4V, the regulator begins to switch. The inductor current limit is gradually increased to ensure proper soft-start operation. When the EN pin is connected to a logic low, the ISL97536 is in the shutdown mode. All the control circuitry and both MOSFETs are off, and VOUT falls to zero. In this mode, the total input current is less than 1µA. When the EN reaches logic HI, the regulator repeats the start-up procedure, including the soft-start function. Current Limit and Short-Circuit Protection The current limit is set at about 1.5A for the PMOS. When a short-circuit occurs in the load, the preset current limit restricts the amount of current available to the output, which causes the output voltage to drop as load demand increases. When the output voltage drops 30mV below the reference voltage, the converter will shutdown for a period of time, approximated by Equation 1, and then restart. If the overcurrent condition still exists, it will repeat the shutdown-wait-restart event. This is called a “hiccup” event. The average power dissipation is reduced, thereby reducing 6 the likelihood of damage current and thermal conditions in the IC as shown in Equation 1. 700μ ⋅ V IN tHICCUP ≈ ⎛ ---------------------------- + 216μ⎞ ⎝ ⎠ 3 (EQ. 1) Thermal Shutdown Once the junction reaches about +145°C, the regulator shuts down. Both the P-Channel and the N-Channel MOSFETs turn off. The output voltage will drop to zero. With the output MOSFETs turned off, the regulator will cool down. Once the junction temperature drops to about +130°C, the regulator will perform a normal restart. Thermal Performance The ISL97536 is available in a fused-lead MSOP10. Compared with regular MSOP10 package, the fused-lead package provides lower thermal resistance. The θJA is +100°C/W on a 4-layer board and +125°C/W on 2-layer board. Maximizing the copper area around the pins will further improve the thermal performance. RSI/POR Function When powering up, the open-collector Power-On-Reset output holds low for about 100ms after VO reaches the preset voltage. When the active-HI reset signal RSI is issued, POR goes to low immediately and holds for the same period of time after RSI comes back to LOW. The output voltage is unaffected. (Please refer to the timing diagram). When the function is not used, connect RSI to ground and leave open the pull-up resistor R4 at POR pin. The POR output also serves as a 100ms delayed Power Good signal when the pull-up resistor R4 is installed. The RSI pin needs to be directly (or indirectly through a resistor R6) connected to Ground for this to function properly. VO MIN 25ns RSI 100ms 100ms POR FIGURE 13. RSI AND POR TIMING DIAGRAM Output Voltage Selection Users can set the output voltage of the variable version with a resistor divider, which can be chosen based on Equation 2: R 1⎞ ⎛ V O = 0.8 × ⎜ 1 + -------⎟ R 2⎠ ⎝ (EQ. 2) FN6279.1 November 2, 2007 ISL97536 Component Selection Layout Considerations Because of the fixed internal compensation, the component choice is relatively narrow. For a regulator with fixed output voltage, only two capacitors and one inductor are required. Capacitors must be chosen in the range of 10µF to 40µF, multilayer ceramic capacitors with X5R or X7R rating for both the input and output capacitors, and inductors in the range of 1.5µH to 2.2µH. The layout is very important for the converter to function properly. The following PC layout guidelines should be followed: The RMS current present at the input capacitor is decided by Equation 3: 3. Make the following PC traces as small as possible: - from LX pin to L - from CO to PGND V O × ( V IN – V O ) I INRMS = ----------------------------------------------- × I O V IN (EQ. 3) This is about half of the output current IO for all the VO. This input capacitor must be able to handle this current. The inductor peak-to-peak ripple current is given as shown in Equation 4: ( V IN – V O ) × V O ΔI IL = -------------------------------------------L × V IN × f S 1. Separate the Power Ground ( ) and Signal Ground ( ); connect them only at one point right at the pins 2. Place the input capacitor as close to VIN and PGND pins as possible 4. If used, connect the trace from the FB pin to R1 and R2 as close as possible 5. Maximize the copper area around the PGND pin 6. Place several via holes under the chip to additional ground plane to improve heat dissipation The demo board is a good example of layout based on this outline. (EQ. 4) L is the inductance fS the switching frequency (nominally 1.4MHz) The inductor must be able to handle IO for the RMS load current, and to assure that the inductor is reliable, it must handle the 2A surge current that can occur during a current limit condition. In addition to decoupling capacitors and inductor value, it is important to properly size the phase-lead capacitor C4 (Refer to the “Pinout and Typical Application Diagram” on page 1). The phase-lead capacitor creates additional phase margin in the control loop by generating a zero and a pole in the transfer function. As a general rule of thumb, C4 should be sized to start the phase-lead at a frequency of ~2.5kHz. The zero will always appear at lower frequency than the pole and follow Equation 5: 1 f Z = ---------------------2πR 2 C 4 (EQ. 5) Over a normal range of R2 (~10k to100k), C4 will range from ~470pF to 4700pF. The pole frequency cannot be set once the zero frequency is chosen as it is dictated by the ratio of R1 and R2, which is solely determined by the desired output set point. Equation 6 shows the pole frequency relationship: 1 f P = --------------------------------------2π ( R 1 R 2 )C 4 (EQ. 6) 7 FN6279.1 November 2, 2007 ISL97536 Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference - 0.08 M C A B b Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE A1 L 0.25 3° ±3° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN6279.1 November 2, 2007