HI7106 3 1/2 Digit, LCD/LED Display, A/D Converter July 1998 Features Description • Guaranteed Zero Reading for 0V Input on All Scales The Intersil HI7106 is a high performance, low power, 31/2 digit A/D converter. Included are seven segment decoders, display drivers, a reference, and a clock. The HI7106 is designed to interface with a liquid crystal display (LCD) and includes a multiplexed backplane drive. • True Polarity at Zero for Precise Null Detection • 1pA Typical Input Current • True Differential Input and Reference, Direct Display Drive The HI7106 brings together a combination of high accuracy, versatility, and true economy. It features auto-zero to less than 10µV, zero drift of less than 1µV/oC, input bias current of 10pA (Max), and rollover error of less than one count. True differential inputs and reference are useful in all systems, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge type transducers. Finally, the true economy of single power supply operation enables a high performance panel meter to be built with the addition of only 10 passive components and a display. • Low Noise - Less Than 15µVP-P • On Chip Clock and Reference • Low Power Dissipation - Typically Less Than 10mW • No Additional Active Circuits Required • Enhanced Display Stability • Enhanced VCOM Reference Stability Ordering Information TEMP. RANGE (oC) PART NO. PACKAGE PKG. NO. HI7106CPL 0 to 70 40 Ld PDIP E40.6 HI7106CM44 0 to 70 44 Ld MQFP Q44.10x10 HI7106C/D 0 to 70 DIE Pinouts (1’s) (10’s) 36 REF HI F1 6 35 REF LO G1 7 E1 8 34 CREF+ 33 CREF- D2 9 32 COMMON C2 10 31 IN HI B2 11 30 IN LO A2 12 29 A-Z F2 E2 13 14 28 BUFF V- 5 INT 37 TEST A1 BUFF 4 A-Z 38 OSC 3 B1 IN LO 3 COMMON 39 OSC 2 C1 IN HI 40 OSC 1 2 CREF- 1 CREF+ V+ D1 REF LO HI7106 (MQFP) TOP VIEW REF HI HI7106 (PDIP) TOP VIEW 44 43 42 41 40 39 38 37 36 35 34 33 2 32 NC TEST 3 31 C3 OSC 3 4 30 A3 NC 5 29 G3 NC NC 1 G2 OSC 2 6 28 BP/GND OSC 1 7 27 POL V+ 8 26 AB4 D1 9 25 E3 27 INT D3 15 26 V- B3 16 25 G2 (10’s) C1 10 24 F3 F3 17 24 C3 B1 11 23 12 13 14 15 16 17 18 19 20 21 22 B3 E3 18 23 A3 (1000) AB4 19 22 G3 POL 20 21 BP/GND (100’s) (MINUS) (100’s) A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 File Number 4551 HI7106 Absolute Maximum Ratings Thermal Information Supply Voltage HI7106, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to VReference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to VClock Input HI7106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+ Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications (Note 3) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYSTEM PERFORMANCE Zero Input Reading VIN = 0.0V, Full Scale = 200mV -000.0 ±000.0 +000.0 Digital Reading Stability (Last Digit) Fixed Input Voltage (Note 6) -000.1 ±000.0 +000.1 Digital Reading Ratiometric Reading VlN = VREF , VREF = 100mV 999 999/10 00 1000 Digital Reading Rollover Error -VIN = +VlN ≅ 200mV Difference in Reading for Equal Positive and Negative Inputs Near Full Scale - ±0.2 ±1 Counts Linearity Full Scale = 200mV or Full Scale = 2V Maximum Deviation from Best Straight Line Fit (Note 6) - ±0.2 ±1 Counts Common Mode Rejection Ratio VCM = 1V, VIN = 0V, Full Scale = 200mV (Note 6) - 50 - µV/V Noise VIN = 0V, Full Scale = 200mV (Peak-To-Peak Value Not Exceeded 95% of Time) - 15 - µV Leakage Current Input VlN = 0 (Note 6) - 1 10 pA Zero Reading Drift VlN = 0, 0oC To 70oC (Note 6) VIN = 199mV, 0oC To 70oC, (Ext. Ref. 0ppm/ oC) (Note 6) - 0.2 1 µV/oC - 1 5 ppm/oC End Power Supply Character V+ Supply Current VIN = 0 - 0.6 1.8 mA COMMON Pin Analog Common Voltage 25kΩ Between Common and Positive Supply (With Respect to + Supply) 2.4 2.8 3.2 V Temperature Coefficient of Analog Common 25kΩ Between Common and Positive Supply (With Respect to + Supply) - 80 - ppm/oC V+ = to V- = 9V (Note 5) 4 5 6 V Scale Factor Temperature Coefficient DISPLAY DRIVER Peak-To-Peak Segment Drive Voltage Peak-To-Peak Backplane Drive Voltage NOTES: 3. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 4. Unless otherwise noted, specifications apply to both the HI7106 and ICL7107 at TA = 25oC, fCLOCK = 48kHz. HI7106 is tested in the circuit of Figure 1. 5. Back plane drive is in phase with segment drive for ‘off’ segment, 180 degrees out of phase for ‘on’ segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 6. Not tested, guaranteed by design. 2 HI7106 Typical Application and Test Circuit 9V A3 23 G3 22 BP 21 19 AB4 20 POL C3 24 17 F3 18 E3 V- 26 G2 25 16 B3 INT 27 14 E2 DISPLAY 15 D3 A-Z 29 BUFF 28 13 F2 C3 12 A2 IN HI 31 C2 R2 IN LO 30 COM 32 CREF- 33 CREF+ 34 REF LO 35 TEST 37 REF HI 36 OSC 3 38 OSC 2 39 OSC 1 40 + C5 C1 R4 C4 - R5 R1 R3 IN - + 11 B2 10 C2 9 D2 8 E1 7 G1 6 F1 5 A1 4 B1 3 C1 2 D1 1 V+ HI7106 C1 = 0.1µF C2 = 0.47µF C3 = 0.22µF C4 = 100pF C5 = 0.02µF R1 = 24kΩ R2 = 47kΩ R3 = 100kΩ R4 = 1kΩ R5 = 1MΩ DISPLAY FIGURE 1. HI7106 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE Design Information Summary Sheet • VINT MAXIMUM SWING: (V- + 0.5V) < VINT < (V+ - 0.5V), VINT (Typ) = 2V • OSCILLATOR FREQUENCY fOSC = 0.45/RC COSC > 50pF; ROSC > 50kΩ fOSC (Typ) = 48kHz • DISPLAY COUNT V IN COUNT = 1000 × --------------V REF • OSCILLATOR PERIOD tOSC = RC/0.45 • CONVERSION CYCLE tCYC = tCL0CK x 4000 tCYC = tOSC x 16,000 when fOSC = 48kHz; tCYC = 333ms • INTEGRATION CLOCK FREQUENCY fCLOCK = fOSC/4 • INTEGRATION PERIOD tINT = 1000 x (4/fOSC) • COMMON MODE INPUT VOLTAGE (V- + 1V) < VlN < (V+ - 0.5V) • 60/50Hz REJECTION CRITERION tINT/t60Hz or tlNT/t60Hz = Integer • AUTO-ZERO CAPACITOR 0.01µF < CAZ < 1µF • OPTIMUM INTEGRATION CURRENT IINT = 4µA • REFERENCE CAPACITOR 0.1µF < CREF < 1µF • FULL SCALE ANALOG INPUT VOLTAGE VlNFS (Typ) = 200mV or 2V • VCOM Biased between Vi and V-. • INTEGRATE RESISTOR • VCOM ≅ V+ - 2.8V Regulation lost when V+ to V- < ≅6.8V If VCOM is externally pulled down to (V+ to V-)/2, the VCOM circuit will turn off. V INFS R INT = ----------------I INT • INTEGRATE CAPACITOR ( t INT ) ( I INT ) C INT = -------------------------------V INT • HI7106 POWER SUPPLY: SINGLE 9V V+ - V- = 9V Digital supply is generated internally VGND ≅ V+ - 4.5V • INTEGRATOR OUTPUT VOLTAGE SWING ( t INT ) ( I INT ) V INT = -------------------------------C INT • HI7106 DISPLAY: LCD Type: Direct drive with digital logic supply amplitude. 3 HI7106 Typical Integrator Amplifier Output Waveform (INT Pin) AUTO ZERO PHASE (COUNTS) 2999 - 1000 SIGNAL INTEGRATE PHASE FIXED 1000 COUNTS DE-INTEGRATE PHASE 0 - 1999 COUNTS TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC Detailed Description the system. In any case, the offset referred to the input is less than 10µV. Analog Section Figure 2 shows the Analog Section for the HI7106. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE). Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. Auto-Zero Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of STRAY STRAY CREF RINT CREF+ REF HI 34 36 V+ REF LO 35 A-Z CREF 33 A-Z CAZ BUFFER V+ 28 1 CINT A-Z INT 29 27 INTEGRATOR - + 10mA - + - + 2.8V 31 IN HI INT DE- DE+ 6.2V INPUT HIGH A-Z A-Z DE+ 32 COMPARATOR - N + DE- COMMON 30 INT INPUT LOW A-Z AND DE( ) IN LO V- FIGURE 2. ANALOG SECTION OF HI7106 4 TO DIGITAL SECTION HI7106 Analog COMMON is also used as the input low return during auto-zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in some applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently tied to analog COMMON, it should be since this removes the common mode voltage from the reference system. De-Integrate Phase The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed is: V IN DISPLAY COUNT = 1000 --------------- . V REF Within the lC, analog COMMON is tied to an N-Channel FET that can sink approximately 30mA of current to hold the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is only 10µA of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal reference. Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. V+ V REF HI 6.8V ZENER REF LO IZ HI7106 Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection.) V- FIGURE 3A. V+ V 6.8kΩ 20kΩ HI7106 REF HI REF LO ICL8069 1.2V REFERENCE COMMON Analog COMMON FIGURE 3B. This pin is included primarily to set the common mode voltage for battery operation or for any system where the input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6V. However, analog COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (>7V), the COMMON voltage will have a low voltage coefficient (0.001%/V), low output impedance (≅15Ω), and a temperature coefficient typically less than 80ppm/oC. An external reference can easily be added, as shown in Figure 3. FIGURE 3. USING AN EXTERNAL REFERENCE TEST The TEST pin serves two functions. On the HI7106 it is coupled to the internally generated digital supply through a 500Ω resistor. Thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the LCD display. Figures 4 and 5 show such an application. No more than a 1mA load should be applied. 5 HI7106 V+ This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/sec., this is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. 1MΩ TO LCD DECIMAL POINT HI7106 BP TEST 21 37 The polarity indication is “on” for negative analog inputs. If IN LO and IN HI are reversed, this indication can be reversed also, if desired. TO LCD BACKPLANE FIGURE 4. SIMPLE INVERTER FOR FIXED DECIMAL POINT V+ V+ The second function is a “lamp test”. When TEST is pulled high (to V+) all segments will be turned on and the display should read “1888”. The TEST pin will sink about 15mA under these conditions. BP HI7106 TO LCD DECIMAL POINTS DECIMAL POINT SELECT CAUTION: In the lamp test mode, the segments have a constant DC voltage (no square-wave). This may burn the LCD display if maintained for extended periods. TEST CD4030 Digital Section GND Figures 6 shows the digital section for the HI7106. In the HI7106, an internal digital ground is generated from a 6V Zener diode and a large P-Channel source follower. FIGURE 5. EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE a a f a g b e a f b b f g c e c d b g c d e c d BACKPLANE 21 LCD PHASE DRIVER 7 SEGMENT DECODE TYPICAL SEGMENT OUTPUT V+ 7 SEGMENT DECODE 7 SEGMENT DECODE ÷200 0.5mA LATCH SEGMENT OUTPUT 2mA 1000’s COUNTER 100’s COUNTER 10’s COUNTER 1’s COUNTER INTERNAL DIGITAL GROUND TO SWITCH DRIVERS FROM COMPARATOR OUTPUT 1 V+ CLOCK ÷4 † LOGIC CONTROL 6.2V 500Ω † THREE INVERTERS INTERNAL DIGITAL GROUND ONE INVERTER SHOWN FOR CLARITY TEST VTH = 1V 37 26 40 OSC 1 39 OSC 2 38 OSC 3 FIGURE 6. HI7106 DIGITAL SECTION 6 V- HI7106 supply 4µA of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full scale, 470kΩ is near optimum and similarly a 47kΩ for a 200mV scale. System Timing Figure 7 shows the clocking arrangement used in the HI7106. Two basic clocking arrangements can be used: • Figure 7A. An external oscillator connected to pin 40. • Figure 7B. An R-C oscillator using all three pins. Integrating Capacitor The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and auto-zero (1000 to 3000 counts). For signals less than full scale, auto-zero gets the unused portion of reference de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used. The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing (approximately. 0.3V from either supply). In the HI7106, when the analog COMMON is used as a reference, a nominal +2V full- scale integrator swing is fine. For three readings/second (48kHz clock) nominal values for ClNT are 0.22µF and 0.10µF, respectively. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 331/3kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 662/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz). An additional requirement of the integrating capacitor is that it must have a low dielectric absorption to prevent roll-over errors. While other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. Auto-Zero Capacitor The size of the auto-zero capacitor has some influence on the noise of the system. For 200mV full scale where noise is very important, a 0.47µF capacitor is recommended. On the 2V scale, a 0.047µF capacitor increases the speed of recovery from overload and is adequate for noise on this scale. INTERNAL TO PART ÷4 40 39 CLOCK Reference Capacitor 38 A 0.1µF capacitor gives good results in most applications. However, where a large common mode voltage exists (i.e., the REF LO pin is not at analog COMMON) and a 200mV scale is used, a larger value is required to prevent roll-over error. Generally 1µF will hold the roll-over error to 0.5 count in this instance. TEST HI7106 FIGURE 7A. INTERNAL TO PART ÷4 40 Oscillator Components CLOCK For all ranges of frequency a 100kΩ resistor is recommended and the capacitor is selected from the equation: 39 38 0.45 f = ----------- For 48kHz Clock (3 Readings/sec), RC R C C = 100pF. RC OSCILLATOR Reference Voltage The analog input required to generate full scale output (2000 counts) is: VlN = 2VREF. Thus, for the 200mV and 2V scale, VREF should equal 100mV and 1V, respectively. However, in many applications where the A/D is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. For instance, in a weighing system, the designer might like to have a full scale reading when the voltage from the transducer is 0.662V. Instead of dividing the input down to 200mV, the designer should use the input voltage directly FIGURE 7B. FIGURE 7. CLOCK CIRCUITS Component Value Selection Integrating Resistor Both the buffer amplifier and the integrator have a class A output stage with 100µA of quiescent current. They can 7 HI7106 Typical Applications and select VREF = 0.341V. Suitable values for integrating resistor and capacitor would be 20kΩ and 0.22µF. This makes the system slightly quieter and also avoids a divider network on the input. Another advantage of this system occurs when a digital reading of zero is desired for VIN ≠ 0. Temperature and weighing systems with a variable fare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) offset voltage between COMMON and IN LO. The HI7106 may be used in a wide variety of configurations. The circuits which follow show some of the possibilities, and serve to illustrate the exceptional versatility of this A/D converter. Typical Applications TO PIN 1 OSC 1 40 TO PIN 1 OSC 1 40 100kΩ OSC 2 39 OSC 2 39 OSC 3 38 TEST 37 100kΩ OSC 3 38 SET VREF 100pF TEST 37 = 100mV SET VREF = 100mV 100pF REF HI 36 REF HI 36 REF LO 35 CREF 34 1kΩ CREF 34 22kΩ CREF 33 0.1µF 24kΩ 0.1µF 1MΩ + IN HI 31 COMMON 32 1MΩ + IN LO 30 IN HI 31 0.47µF 47kΩ A-Z 29 IN 0.01µF A-Z 29 - BUFF 28 + INT 27 BUFF 28 V - 26 9V - INT 27 V - 26 25kΩ COMMON 32 CREF 33 IN LO 30 V+ REF LO 35 IN 0.01µF 0.047µF - 470kΩ 0.22µF V- G2 25 C3 24 0.22µF A3 23 G2 25 TO DISPLAY G3 22 C3 24 BP/GND 21 TO DISPLAY A3 23 G3 22 BP 21 TO BACKPLANE Values shown are for 200mV full scale, 3 readings/sec., floating supply voltage (9V battery). FIGURE 9. HI7106 RECOMMENDED COMPONENT VALUES FOR 2V FULL SCALE FIGURE 8. HI7106 USING THE INTERNAL REFERENCE 8 HI7106 Typical Applications (Continued) V+ TO PIN 1 OSC 1 40 100kΩ OSC 2 39 OSC 3 38 100pF TEST 37 TO LOGIC VCC SCALE FACTOR ADJUST REF HI 36 REF LO 35 CREF 34 CREF 33 22kΩ 100kΩ 1MΩ 100kΩ 220kΩ 0.1µF IN HI 31 A-Z 29 BUFF 28 ZERO ADJUST 0.01µF A3 23 0.47µF 47kΩ 9V 0.22µF TO DISPLAY G3 22 BP 21 OSC 2 39 3 C1 OSC 3 38 4 B1 TEST 37 5 A1 REF HI 36 6 F1 REF LO 35 TO CREF 34 LOGIC GND CREF 33 COMMON 32 9 D2 SILICON NPN MPS 3704 OR SIMILAR G2 25 C3 24 2 D1 8 E1 INT 27 V - 26 OSC 1 40 7 G1 COMMON 32 IN LO 30 1 V+ O /RANGE TO BACKPLANE NOTE: A silicon diode-connected transistor has a temperature coefficient of about -2mV/oC. Calibration is achieved by placing the sensing transistor in ice water and adjusting the zeroing potentiometer for a 000.0 reading. The sensor should then be placed in boiling water and the scale-factor potentiometer adjusted for a 100.0 reading. 10 C2 IN HI 31 11 B2 IN LO 30 12 A2 A-Z 29 13 F2 BUFF 28 14 E2 INT 27 15 D3 V- 26 16 B3 G2 25 17 F3 C3 24 18 E3 A3 23 19 AB4 G3 22 20 POL BP 21 V- U /RANGE CD4023 OR 74C10 FIGURE 10. HI7106 USED AS A DIGITAL CENTIGRADE THERMOMETER CD4077 FIGURE 11. CIRCUIT FOR DEVELOPING UNDERRANGE AND OVERRANGE SIGNAL FROM HI7106 OUTPUTS TO PIN 1 OSC 1 40 100kΩ OSC 2 39 10µF SCALE FACTOR ADJUST (VREF = 100mV FOR AC TO RMS) OSC 3 38 TEST 37 100pF 5µF CA3140 REF HI 36 - REF LO 35 CREF 34 CREF 33 1N914 1kΩ 22kΩ 470kΩ 0.1µF 2.2MΩ COMMON 32 10kΩ 1µF 4.3kΩ 0.22µF 47kΩ 10µF + 9V 100pF (FOR OPTIMUM BANDWIDTH) - INT 27 V - 26 1µF 0.47µF A-Z 29 BUFF 28 10kΩ 1µF IN HI 31 IN LO 30 0.22µF G2 25 C3 24 A3 23 TO DISPLAY G3 22 BP 21 100kΩ + TO BACKPLANE NOTE: Test is used as a common-mode reference level to ensure compatibility with most op amps. FIGURE 12. AC TO DC CONVERTER WITH HI7106 9 AC IN HI7106 Dual-In-Line Plastic Packages (PDIP) E40.6 (JEDEC MS-011-AC ISSUE B) N 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- -C- A2 SEATING PLANE e B1 D1 B 0.010 (0.25) M A1 eC C A B S MAX NOTES - 0.250 - 6.35 4 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 0.204 0.381 - D 1.980 2.095 D1 0.005 - A L D1 MIN A E BASE PLANE MAX A1 -AD MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 50.3 53.2 5 - 5 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N 40 40 9 Rev. 0 12/93 10 HI7106 Metric Plastic Quad Flatpack Packages (MQFP/PQFP) Q44.10x10 (JEDEC MO-108AA-2 ISSUE A) D 44 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE D1 -D- -A- -B- E E1 e PIN 1 INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.093 - 2.35 - A1 0.004 0.010 0.10 0.25 - A2 0.077 0.083 1.95 2.10 - B 0.012 0.018 0.30 0.45 6 B1 0.012 0.016 0.30 0.40 - D 0.510 0.530 12.95 13.45 3 D1 0.390 0.398 9.90 10.10 4, 5 E 0.510 0.530 12.95 13.45 3 E1 0.390 0.398 9.90 10.10 4, 5 L 0.026 0.037 0.65 0.95 N 44 44 e 0.032 BSC 0.80 BSC SEATING A PLANE -H- 7 Rev. 1 1/94 NOTES: 0.10 0.004 -C- 5o-16o 0.40 0.016 MIN 0.20 M C A-B S 0.008 0o MIN 2. All dimensions and tolerances per ANSI Y14.5M-1982. D S 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . B A2 A1 0o-7o L 5o-16o B1 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 0.13/0.17 0.005/0.007 BASE METAL WITH PLATING 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 6. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. 0.13/0.23 0.005/0.009 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. 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