HM-65262 16K x 1 Asynchronous CMOS Static RAM March 1997 Features Description • Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/85ns Max The HM-65262 is a CMOS 16384 x 1-bit Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle times and ease of use. The HM-65262 is available in both JEDEC standard 20 pin, 0.300 inch wide CERDIP and 20 pad CLCC packages, providing high boardlevel packing density. Gated inputs lower standby current, and also eliminate the need for pull-up or pull-down resistors. • Low Standby Current. . . . . . . . . . . . . . . . . . . .50µA Max • Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max • Data Retention at 2.0V . . . . . . . . . . . . . . . . . . .20µA Max • TTL Compatible Inputs and Outputs • JEDEC Approved Pinout • No Clocks or Strobes Required • Temperature Range . . . . . . . . . . . . . . . +55oC to +125oC The HM-65262, a full CMOS RAM, utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full military temperature range. In addition to this, the high stability of the 6T RAM cell provides excellent protection against soft errors due to noise and alpha particles. This stability also improves the radiation tolerance of the RAM over that of four transistor (4T) devices. • Equal Cycle and Access Time • Single 5V Supply • Gated Inputs-No Pull-Up or Pull-Down Resistors Required Ordering Information PACKAGE (NOTE 1) 85ns/400µA TEMP. RANGE 70ns/20µA (NOTE 1) 85ns/20µA (NOTE 1) CERDIP -40oC to +85oC HM1-65262B-9 HM1-65262-9 - F20.3 JAN # -55oC to +125oC 29109BRA 29103BRA - F20.3 SMD# -55oC to +125oC 8413203RA 8413201RA - F20.3 -55oC to +125oC 8413203YA 8413201YA - J20.C CLCC (SMD#) PKG. NO. NOTE: 1. Access Time/Data Retention Supply Current. Pinouts 1 20 VCC A1 2 19 A13 A2 3 A3 4 A4 A13 VCC A0 A0 HM-65262 (CLCC) TOP VIEW A1 HM-65262 (CERDIP) TOP VIEW 2 1 20 19 A0 - A13 Address Input A2 3 18 A12 18 A12 A3 4 17 A11 E Chip Enable/Power Down 17 A11 A4 5 16 A10 Q Data Out 5 16 A10 A5 6 15 A9 A5 6 15 A9 A6 7 14 A8 D Data In A6 7 14 A8 Q 8 13 A7 VSS/GND Ground Q 8 13 A7 W 9 12 D GND 10 11 E D E W GND 9 10 11 12 VCC W CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 6-1 Power (+5) Write Enable File Number 3002.2 HM-65262 Functional Diagram A0 A1 A2 A3 A4 A12 A13 A 7 ROW ROW ADDRESS DECODER 128 MEMORY ARRAY BUFFER A (1 OF 128) 128 X 128 7 128 COLUMN DECODER (1 OF 128) AND I / O CIRCUITRY D A 7 A 7 E COLUMN ADDRESS BUFFERS A7 A8 A9 A10 A11 A5 A6 W 6-2 Q HM-65262 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage Applied for all grades . . . . . -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . . . . . . . .5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 θJC Thermal Resistance (Typical) θJA CERDIP Package . . . . . . . . . . . . . . . . . . 66oC/W 13oC/W 18oC/W CLCC Package. . . . . . . . . . . . . . . . . . . . 75oC/W Maximum Storage Temperature Range . . . . . . . . . . . . . -65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . +300oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26256 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V DC Electrical Specifications Operating Temperature Range HM-65262B-9, HM-65262-9, HM-65262C-9 . . . . .-40oC to +85oC VCC = 5V ±10%; TA = -40oC to +85oC (HM-65262B-9, HM-65262-9, HM-65262C-9) LIMITS SYMBOL ICCSB1 PARAMETER Standby Supply Current MIN MAX UNITS TEST CONDITIONS -od 50 µA HM-65262B-9, HM-65262-9, IO = 0mA, E = VCC -0.3V, VCC = 5.5V - 900 µA HM-65262C-9, IO = 0mA, E = VCC -0.3V, VCC = 5.5V ICCSB Standby Supply Current - 5 mA E = 2.2V, IO = 0mA, VCC = 5.5V ICCEN Enabled Supply Current - 50 mA E = 0.8V, IO = 0mA, VCC = 5.5V ICCOP Operating Supply Current (Note 1) - 50 mA E = 0.8V, IO = 0mA, f = 1MHz, VCC = 5.5V ICCDR Data Retention Supply Current - 20 µA HM-65262B-9, HM-65262-9, VCC = 2.0V, E = VCC - 400 µA HM-65262C-9, VCC = 2.0V, E = VCC - 30 µA HM-65262B-9, HM-65262-9, VCC = 3.0V, E = VCC - 550 µA HM-65262C-9, VCC = 3.0V, E = VCC Data Retention Supply Voltage 2.0 - V Input Leakage Current -1.0 +1.0 µA VI = VCC or GND, VCC = 5.5V IOZ Output Leakage Current -1.0 +1.0 µA VIO = VCC or GND, VCC = 5.5V VIL Input Low Voltage -0.3 0.8 V VCC = 4.5V VIH Input High Voltage 2.2 VCC +0.3 V VCC = 5.5V VOL Output Low Voltage - 0.4 V IO = 8.0mA, VCC = 4.5V VOH1 Output High Voltage 2.4 - V IO = -4.0mA, VCC = 4.5V VOH2 Output High Voltage (Note 2) VCC -0.4 - V IO = -100µA, VCC = 4.5V ICCDR1 VCCDR II Data Retention Supply Current Capacitance SYMBOL CI CIO TA = +25oC PARAMETER MAX UNITS Input Capacitance (Note 2) 10 pF Input/Output Capacitance (Note 2) 12 pF NOTES: 1. Typical derating 5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes. 6-3 TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND HM-65262 AC Electrical Specifications VCC = 5V 10%,TA = -40oC to +85oC (HM-65262B-9, HM-65262-9, HM-65262C-9) LIMITS HM-65262B-9 SYMBOL PARAMETER HM-65262-9 HM-65262C-9 MIN MAX MIN MAX MIN MAX UNITS TEST CONDITIONS 70 - 85 - 85 - ns (Notes 1, 3) READ CYCLE (1) TAVAX Read/Cycle Time (2) TAVQV Address Access Time - 70 - 85 - 85 ns (Notes 1, 3) (3) TELQV Chip Enable Access Time - 70 - 85 - 85 ns (Notes 1, 3) (4) TELQX Chip Enable Output Enable Time 5 - 5 - 5 - ns (Notes 2, 3) (5) TEHQX Chip Disable Output Hold Time 5 - 5 - 5 - ns (Notes 2, 3) (6) TAXQX Address Invalid Output Hold Time 5 - 5 - 5 - ns (Notes 2, 3) (7) TEHQZ Chip Enable Output Disable Time - 30 - 30 - 30 ns (Notes 2, 3) WRITE CYCLE (8) TAVAX Write Cycle Time 70 - 85 - 85 - ns (Notes 1, 3) (9) TELWH Chip Selection to End of Write 55 - 65 - 65 - ns (Notes 1, 3) (10) TWLWH Write Enable Pulse Width 40 - 45 - 45 - ns (Notes 1, 3) (11) TAVWL Address Setup Time 0 - 0 - 0 - ns (Notes 1, 3) (12) TWHAX Address Hold Time 0 - 0 - 0 - ns (Notes 1, 3) (13) TDVWH Data Setup Time 30 - 35 - 35 - ns (Notes 1, 3) (14) TWHDX Data Hold Time 0 - 0 - 0 - ns (Notes 1, 3) (15) TWLQZ Write Enable Output Disable Time - 30 - 30 - 30 ns (Notes 2, 3) (16) TWHQX Write Disable Output Enable Time 0 - 0 - 0 - ns (Notes 2, 3) (17) TAVWH Address Valid to End of Write 55 - 65 - 65 - ns (Notes 1, 3) (18) TAVEL Address Setup Time 0 - 0 - 0 - ns (Notes 1, 3) (19) TEHAX Address Hold Time 0 - 0 - 0 - ns (Notes 1, 3) (20) TAVEH Address Valid to End of Write 55 - 65 - 65 - ns (Notes 1, 3) (21) TELEH Enable Pulse Width 55 - 65 - 65 - ns (Notes 1, 3) (22) TWLEH Write Enable Pulse Setup Time 40 - 45 - 45 - ns (Notes 1, 3) (23) TDVEH Chip Setup Time 30 - 35 - 35 0 ns (Notes 1, 3) (24) TEHDX Data Hold Time 0 - 0 - 0 - ns (Notes 1, 3) NOTES: 1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent and CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. VCC = 4.5 and 5.5V. 6-4 HM-65262 Timing Waveforms A (3) TELQV E (7) TEHQZ (4) TELQX (5) TEHQX Q NOTE: 1. W is high for entire cycle and D is ignored. Address is stable by the time E goes low and remains valid until E goes high. FIGURE 1. READ CYCLE 1: CONTROLLED BY E (1) TAVAX A (2) TAVQV E (7) TEHQZ (4) TELQX (6) TAXQX Q NOTE: 1. W is high for the entire cycle and D is ignored. E is stable prior to A becoming valid and after A becomes invalid. FIGURE 2. READ CYCLE 2: CONTROLLED BY ADDRESS (8) TAVAX A (12) TWHAX (17) TAVWH (9) TELWH E (11) TAVWL (7) TEHQZ (10) TWLWH W (13) TDVWH (14) TWHDX D (15) TWLQZ (4) TELQX (16) TWHQX Q NOTE: 1. In this mode, E rises after W. The address must remain stable whenever both E and W are low. FIGURE 3. WRITE CYCLE 1: CONTROLLED BY W (LATE WRITE) 6-5 HM-65262 Timing Waveforms (Continued) (8) TAVAX A (20) TAVEH (18) TAVEL (19) TEHAX (21) TELEH E (22) TWLEH W (16) TWHQX (23) TDVEH (24) TEHDX D (4) TELQX Q (15) TWLQZ (7) TEHQZ NOTE: 1. In this mode, W rises after E. If W falls before E by a time exceeding TWLQZ (Max) TELQX (Min), and rises after E by a time exceeding TEHQZ (Max) TWHQZ (Min), then Q will remain in the high impedance state throughout the cycle. FIGURE 4. WRITE CYCLE 2: CONTROLLED BY E (EARLY WRITE) Low Voltage Data Retention Intersil CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (E) must be held high during data retention; within VCC to VCC +0.3V. 2. On RAMs which have selects or output enables (e.g., S, G), one of the selects or output enables should be held in the deselected state to keep the RAM outputs high impedance, minimizing power dissipation. 3. Inputs which are to be held high (e.g., E) must be kept between VCC +0.3V and 70% of VCC during the power up and down transitions. 4. The RAM can begin operation > 55ns after VCC reaches the minimum operating voltage (4.5V). DATA RETENTION MODE VCC 4.5V VCC ≥ 2.0V 4.5V >55ns E VCC -0.3V TO VCC +0.3V FIGURE 5. DATA RETENTION TIMING 6-6 HM-65262 Typical Performance Curve VCC = 2.0V -3 -4 LOGIC (ICC/(1A)) -5 -6 -7 -8 -9 -10 -11 -12 -55 -35 -15 5 25 45 65 85 105 125 TA (oC) FIGURE 6. TYPICAL ICCDR vs TA All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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