ISL4260E ® Data Sheet June 21, 2010 FN6035.2 QFN Packaged, ±15kV ESD Protected, +3V to +5.5V, 150nA, 250kbps, RS-232 Transmitters/Receivers with Separate Logic Supply Features The ISL4260E contains 3.0V to 5.5V powered RS-232 transmitters/receivers which meet ElA/TIA-232 and V.28/V.24 specifications, even at VCC = 3.0V. Targeted applications are PDAs, Palmtops, and cell phones where the low operational, and even lower standby, power consumption is critical. Efficient on-chip charge pumps, coupled with a manual powerdown function reduces the standby supply current to a 150nA trickle. Tiny 5mm x 5mm Quad Flat No-Lead (QFN) packaging, and the use of small, low value capacitors ensure board space savings as well. Data rates greater than 250kbps are guaranteed at worst case load conditions. • ESD Protection for RS-232 I/O Pins to ±15kV (IEC61000) The ISL4260E features a VL pin that adjusts the logic pin (see Pin Descriptions table) output levels and input thresholds to values compatible with the VCC powering the external logic (e.g., a UART). The single pin powerdown function (SHDN = 0) disables all the receiver and transmitter outputs, while shutting down the charge pump to minimize supply current drain. Table 1 summarizes the features of the ISL4260E, while Application Note AN9863 summarizes the features of each device comprising the 3V RS-232 family. • Available in Near Chip Scale QFN (5mmx5mm) Package • VL Pin for Compatibility with Mixed Voltage Systems • Single SHDN Pin Disables Transmitters and Receivers • Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V • On-Chip Charge Pumps Require Only Four External 0.1μF Capacitors • Receiver Hysteresis For Improved Noise Immunity • Very Low Supply Current . . . . . . . . . . . . . . . . . . . . 300μA • Guaranteed Minimum Data Rate . . . . . . . . . . . . . 250kbps • Wide Power Supply Range . . . . . . . Single +3V to +5.5V • Low Supply Current in Powerdown State. . . . . . . . .150nA • Pb-Free (RoHS Compliant) Applications • Any System Requiring RS-232 Communication Ports - Battery Powered, Hand-Held, and Portable Equipment - Laptop Computers, Notebooks, Palmtops - Digital Cameras - PDAs and PDA Cradles - Cellular/Mobile Phones Ordering Information PART NUMBER TEMP. RANGE (oC) PART MARKING PACKAGE PKG. DWG. #. ISL4260EIRZ* ISL4260 EIRZ -40 to +85 32 Lead QFN L32.5x5B (Note) (Pb-free) *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. TABLE 1. SUMMARY OF FEATURES PART NUMBER ISL4260E NO. OF NO. OF DATA RATE Rx. ENABLE Tx. Rx. (kbps) FUNCTION? 3 2 250 1 NO VL LOGIC SUPPLY PIN? YES MANUAL AUTOMATIC POWER- DOWN? POWERDOWN FUNCTION? YES NO CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL4260E Pinout NC 28 NC 29 GND 30 VCC V+ 31 SHDN C1- 32 C1+ NC ISL4260E (32 LD QFN) TOP VIEW 27 26 25 24 NC 2 23 T1OUT C2- 3 22 T2OUT V- 4 21 T3OUT C2+ 1 PD 19 R1IN NC 7 18 R2IN NC 8 17 NC 11 12 13 14 NC 10 NC 9 15 16 NC 6 VL T2IN R1OUT NC R2OUT 20 NC 5 T3IN T1IN Pin Descriptions PIN VCC FUNCTION System power supply input (3.0V to 5.5V). V+ Internally generated positive transmitter supply (+5.5V). V- Internally generated negative transmitter supply (-5.5V). GND Ground connection. This is also the potential of the thermal pad (PD). C1+ External capacitor (voltage doubler) is connected to this lead. C1- External capacitor (voltage doubler) is connected to this lead. C2+ External capacitor (voltage inverter) is connected to this lead. C2- External capacitor (voltage inverter) is connected to this lead. TIN TTL/CMOS compatible transmitter Inputs. The switching point is a function of the VL voltage. TOUT RIN ROUT VL SHDN ±15kV ESD Protected, RS-232 level (nominally ±5.5V) transmitter outputs. ±15kV ESD Protected, RS-232 compatible receiver inputs. TTL/CMOS level receiver outputs. Swings between GND and VL. Logic-Level Supply. All TTL/CMOS inputs and outputs are powered by this supply. Active low TTL/CMOS input to tri-state receiver and transmitter outputs and to shut down the on-board power supply to place device in low power mode. The switching point is a function of the VL voltage. NC No Connection PD Exposed Thermal Pad. Connect to GND. 2 ISL4260E Typical Operating Circuit +3.3V to +5V C1 0.1μF + C2 0.1μF + T1IN T2IN TTL/CMOS LOGIC LEVELS + 0.1μF T3IN R1OUT R2OUT LOGIC VCC 0.1μF 29 31 2 3 27 C1+ VCC C1C2+ V- C2- 22 T3 10 21 R1 13 4 23 T2 6 19 5kΩ R2 12 18 5kΩ 15 + VL GND + C3 0.1μF + T1 5 26 3 30 V+ SHDN 28 C4 0.1μF T1OUT T2OUT T3OUT R1IN R2IN VCC RS-232 LEVELS ISL4260E Absolute Maximum Ratings Thermal Information VCC to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V VL to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V V+ to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V V- to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V Input Voltages TIN, SHDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V RIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V Output Voltages TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V ROUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VL +0.3V) Short Circuit Duration TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous ESD Rating . . . . . . . . . . . . See “ESD PERFORMANCE” on page 5 Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W) 32 Ld QFN Package. . . . . . . . . . . . . . . 30 2.2 Moisture Sensitivity (see Technical Brief TB363) QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range ISL4260EIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379, and Tech Brief TB389. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1μF, VL = VCC; Unless Otherwise Specified. Typicals are at TA = 25oC, VCC = VL = 3.3V Electrical Specifications PARAMETER TEST CONDITIONS TEMP (oC) MIN (Note 4) TYP MAX (Note 4) UNITS DC CHARACTERISTICS Supply Current, Powerdown SHDN = GND, All Inputs at VCC or GND 25 - 0.15 1 μA Supply Current All Outputs Unloaded, SHDN = VCC, VCC = 3.15V 25 - 0.3 1 mA VL = 3.3V or 5V Full - - 0.8 V VL = 2.5V Full - - 0.6 V VL = 5V Full 2.4 - - V VL = 3.3V Full 2.0 - - V VL = 2.5V Full 1.4 - - V VL = 1.8V 25 - 0.9 - V 25 - 0.5 - V TIN, SHDN Full - ±0.01 ±1 μA Output Leakage Current VCC = 0V or 3V to 5.5V, SHDN = GND Full - ±0.05 ±10 μA Output Voltage Low IOUT = 1.6mA Full - - 0.4 V Output Voltage High IOUT = -1.0mA Full VL - 0.6 VL - 0.1 - V Full -25 - 25 V VL = 5.0V 25 0.8 1.5 - V VL = 3.3V 25 0.6 1.2 - V VL = 5.0V 25 - 1.8 2.4 V VL = 3.3V 25 - 1.5 2.4 V 25 - 0.5 - V LOGIC AND TRANSMITTER INPUTS Input Logic Threshold Low TIN, SHDN Input Logic Threshold High TIN, SHDN Transmitter Input Hysteresis Input Leakage Current RECEIVER OUTPUTS RECEIVER INPUTS Input Voltage Range Input Threshold Low Input Threshold High Input Hysteresis 4 ISL4260E Test Conditions: VCC = 3V to 5.5V, C1 - C4 = 0.1μF, VL = VCC; Unless Otherwise Specified. Typicals are at TA = 25oC, VCC = VL = 3.3V (Continued) Electrical Specifications PARAMETER TEST CONDITIONS Input Resistance TEMP (oC) MIN (Note 4) TYP 25 3 5 7 kΩ MAX (Note 4) UNITS TRANSMITTER OUTPUTS Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±5.0 ±5.4 - V Output Resistance VCC = V+ = V- = 0V, Transmitter Output = ±2V Full 300 10M - Ω Output Short-Circuit Current Shorted to GND Full - - ±60 mA Output Leakage Current VOUT = ±12V, VCC = 0V or 3V to 5.5V, SHDN = GND Full - - ±25 μA Maximum Data Rate RL = 3kΩ, CL = 1000pF, One Transmitter Switching Full 250 500 - kbps Receiver Propagation Delay Receiver Input to Receiver Output, CL = 150pF tPHL 25 - 0.15 - μs tPLH 25 - 0.15 - μs Receiver Output Enable Time 25 - 200 - ns Receiver Output Disable Time 25 - 200 - ns TIMING CHARACTERISTICS Transmitter Output Enable Time From SHDN Rising Edge to TOUT = ±3.7V 25 - 100 - μs Transmitter Skew tPHL - tPLH (Note 3) 25 - 100 - ns Receiver Skew tPHL - tPLH 25 - 50 - ns Transition Region Slew Rate CL = 150pF to 1000pF RL = 3kΩ to 7kΩ, Measured From 3V to -3V or CL = 150pF to 2500pF -3V to 3V, VCC = 3.3V 25 6 18 30 V/μs 25 4 13 30 V/μs Human Body Model 25 - ±15 - kV IEC61000-4-2 Air Gap Discharge 25 - ±15 - kV IEC61000-4-2 Contact Discharge 25 - ±8 - kV ESD PERFORMANCE RS-232 Pins (TOUT, RIN) NOTE: 3. Transmitter skew is measured at the transmitter zero crossing points. 4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Detailed Description The ISL4260E operates from a single +3V to +5.5V supply, guarantees a 250kbps minimum data rate, requires only four small external 0.1μF capacitors, features low power consumption, and meets all ElA RS-232C and V.28 specifications. The circuit is divided into three sections: The charge pump, the transmitters, and the receivers. Charge-Pump Intersil’s new ISL4260E utilizes regulated on-chip dual charge pumps as voltage doublers, and voltage inverters to generate ±5.5V transmitter supplies from a VCC supply as low as 3.0V. This allows these devices to maintain RS-232 compliant output levels over the ±10% tolerance range of 3.3V powered systems. The efficient on-chip power supplies require only four small, external 0.1μF capacitors for the voltage doubler and inverter functions over the full VCC range; other capacitor combinations can be used as shown 5 in Table 3. The charge pumps operate discontinuously (i.e., they turn off as soon as the V+ and V- supplies are pumped up to the nominal values), resulting in significant power savings. Transmitters The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA-232 output levels. Coupled with the on-chip ±5.5V supplies, these transmitters deliver true RS-232 levels over a wide range of single supply system voltages. All transmitter outputs disable and assume a high impedance state when the device enters the powerdown mode (see Table 2). These outputs may be driven to ±12V when disabled. All devices guarantee a 250kbps data rate for full load conditions (3kΩ and 1000pF), VCC ≥ 3.0V, with one ISL4260E transmitter operating at full speed. Under more typical conditions of VCC ≥ 3.3V, RL = 3kΩ, and CL = 250pF, one transmitter easily operates at 1.25Mbps. The transmitter input threshold is set by the voltage applied to the VL pin. Transmitter inputs float if left unconnected (there are no pull-up resistors), and may cause ICC increases. Connect unused inputs to GND for the best performance. required to exit powerdown, and resume transmission is less than 100μs. Connect SHDN to VCC if the powerdown function isn’t needed. SHDN PWR MGT LOGIC I/O CHIP POWER SUPPLY VL TABLE 2. POWERDOWN TRUTH TABLE VCC SHDN TRANSMITTER RECEIVER INPUT OUTPUTS OUTPUTS MODE OF OPERATION L High-Z High-Z Manual Powerdown H Active Active Normal Operation ISL4260E CPU I/O UART Receivers The ISL4260E contains standard inverting receivers that convert RS-232 signals to CMOS output levels and accept inputs up to ±25V while presenting the required 3kΩ to 7kΩ input impedance (see Figure 1) even if the power is off (VCC = 0V). The receivers’ Schmitt trigger input stage uses hysteresis to increase noise immunity and decrease errors due to slow input signal transitions. Receiver outputs swing from GND to VL, and tristate in powerdown. VL RXIN -25V ≤ VRIN ≤ +25V RXOUT GND ≤ VROUT ≤ VL 5kΩ GND FIGURE 1. RECEIVER CONNECTIONS Low Power Operation This 3V device requires a nominal supply current of 0.3mA, even at VCC = 5.5V, during normal operation (not in powerdown mode). This is considerably less than the 11mA current required by comparable 5V RS-232 devices, allowing users to reduce system power simply by replacing the old style device with the ISL4260E in new designs. Powerdown Functionality The already low current requirement drops significantly when the device enters powerdown mode. In powerdown, supply current drops to 150nA, because the on-chip charge pump turns off (V+ collapses to VCC, V- collapses to GND), and the transmitter and receiver outputs tristate. This micropower mode makes these devices ideal for battery powered and portable applications. Software Controlled (Manual) Powerdown The ISL4260E may be forced into its low power, standby state via a simple shutdown (SHDN) pin (see Figure 2). Driving this pin high enables normal operation, while driving it low forces the IC into its powerdown state. The time 6 FIGURE 2. CONNECTIONS FOR MANUAL POWERDOWN VL Logic Supply Input Unlike other RS-232 interface devices where the CMOS outputs swing between 0 and VCC, the ISL4260E features a separate logic supply input (VL; 1.8V to 5V, regardless of VCC) that sets VOH for the receiver outputs. Connecting VL to a host logic supply lower than VCC, prevents the ISL4260E outputs from forward biasing the input diodes of a logic device powered by that lower supply. Connecting VL to a logic supply greater than VCC ensures that the receiver output levels are compatible even with the CMOS input VIH of AC, HC, and CD4000 devices. Note that the VL supply current increases to 100μA with VL = 5V and VCC = 3.3V (see Figure 11). VL also powers the transmitter and logic inputs, thereby setting their switching thresholds to levels compatible with the logic supply. This separate logic supply pin allows a great deal of flexibility in interfacing to systems with different logic supplies. If logic translation isn’t required, connect VL to the ISL4260E VCC. Capacitor Selection The ISL4260E charge pumps only require 0.1μF capacitors for the full operational voltage range. Table 3 lists other acceptable capacitor values for various supply voltage ranges. Do not use values smaller than those listed in Table 3. Increasing the capacitor values (by a factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. ISL4260E TABLE 3. REQUIRED CAPACITOR VALUES VCC (V) C1 (μF) C2, C3, C4 (μF) 3.0 to 3.6 0.1 0.1 4.5 to 5.5 0.047 0.33 3.0 to 5.5 0.22 1 When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal value. The capacitor’s equivalent series resistance (ESR) usually rises at low temperatures and it influences the amount of ripple on V+ and V-. loopback results for a single transmitter driving 1000pF and an RS-232 load at 250kbps. The static transmitters were also loaded with an RS-232 receiver. VCC + C1 C1+ VCC VL C2 + ISL4260E V- C2+ C2TIN C4 + RIN 1000pF 5k VCC SHDN FIGURE 4. TRANSMITTER LOOPBACK TEST CIRCUIT Transmitter Outputs when Exiting Powerdown 5V/DIV. Figure 3 shows the response of two transmitter outputs when exiting powerdown mode. As they activate, the two transmitter outputs properly go to opposite RS-232 levels, with no glitching, ringing, nor undesirable transients. Each transmitter is loaded with 3kΩ in parallel with 2500pF. Note that the transmitters enable only when the magnitude of the supplies exceed approximately 3V. T1IN T1OUT SHDN T1 R1OUT VCC = +3.3V C1 - C4 = 0.1μF 5μs/DIV. FIGURE 5. LOOPBACK TEST AT 120kbps 2V/DIV 5V/DIV. T2 T1IN VCC = +3.3V C1 - C4 = 0.1μF TIME (20μs/DIV.) FIGURE 3. TRANSMITTER OUTPUTS WHEN EXITING POWERDOWN High Data Rates The ISL4260E maintains the RS-232 ±5V minimum transmitter output voltages even at high data rates. Figure 4 details a transmitter loopback test circuit, and Figure 5 illustrates the loopback test result at 120kbps. For this test, all transmitters were simultaneously driving RS-232 loads in parallel with 1000pF, at 120kbps. Figure 6 shows the 7 + C3 TOUT ROUT In most circumstances a 0.1μF bypass capacitor is adequate. In applications that are particularly sensitive to power supply noise, decouple VCC to ground with a capacitor of the same value as the charge-pump capacitor C1. Connect the bypass capacitor as close as possible to the IC. V+ C1- Power Supply Decoupling 5V/DIV + 0.1μF T1OUT R1OUT VCC = +3.3V C1 - C4 = 0.1μF 2μs/DIV. FIGURE 6. LOOPBACK TEST AT 250kbps ISL4260E Interconnection with 3V and 5V Logic IEC61000-4-2 Testing Standard 3.3V powered RS-232 devices interface well with 3V and 5V powered TTL compatible logic families (e.g., ACT and HCT), but the logic outputs (e.g., ROUTS) fail to reach the VIH level of 5V powered CMOS families like HC, AC, and CD4000. The ISL4260E VL supply pin solves this problem. By connecting VL to the same supply (1.8V to 5V) powering the logic device, the ISL4260E logic outputs will swing from GND to the logic VCC. The IEC61000 test method applies to finished equipment, rather than to an individual IC. Therefore, the pins most likely to suffer an ESD event are those that are exposed to the outside world (the RS-232 pins in this case), and the IC is tested in its typical application configuration (power applied) rather than testing each pin-to-pin combination. The lower current limiting resistor coupled with the larger charge storage capacitor yields a test that is much more severe than the HBM test. The extra ESD protection built into this device’s RS-232 pins allows the design of equipment meeting level 4 criteria without the need for additional board level protection on the RS-232 port. ±15kV ESD Protection All pins on the 3V interface devices include ESD protection structures, but the ISL4260E incorporates advanced structures which allow the RS-232 pins (transmitter outputs and receiver inputs) to survive ESD events up to ±15kV. The RS-232 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, protect without allowing any latchup mechanism to activate, and don’t interfere with RS-232 signals as large as ±25V. Human Body Model (HBM) Testing As the name implies, this test method emulates the ESD event delivered to an IC during human handling. The tester delivers the charge through a 1.5kΩ current limiting resistor, making the test less severe than the IEC61000 test which utilizes a 330Ω limiting resistor. The HBM method determines an ICs ability to withstand the ESD transients typically present during handling and manufacturing. Due to the random nature of these events, each pin is tested with respect to all other pins. The RS-232 pins on “E” family devices can withstand HBM ESD events to ±15kV. 8 AIR-GAP DISCHARGE TEST METHOD For this test method, a charged probe tip moves toward the IC pin until the voltage arcs to it. The current waveform delivered to the IC pin depends on approach speed, humidity, temperature, etc., so it is difficult to obtain repeatable results. The “E” device RS-232 pins withstand ±15kV air-gap discharges. CONTACT DISCHARGE TEST METHOD During the contact discharge test, the probe contacts the tested pin before the probe tip is energized, thereby eliminating the variables associated with the air-gap discharge. The result is a more repeatable and predictable test, but equipment limits prevent testing devices at voltages higher than ±8kV. All “E” family devices survive ±8kV contact discharges on the RS-232 pins. ISL4260E Typical Performance Curves VCC = 3.3V, TA = 25oC 30 VOUT+ 4.0 25 2.0 SLEW RATE (V/μs) TRANSMITTER OUTPUT VOLTAGE (V) 6.0 1 TRANSMITTER AT 250kbps OTHER TRANSMITTERS AT 30kbps 0 -2.0 -6.0 0 1000 2000 3000 4000 +SLEW 15 -SLEW 10 VOUT - -4.0 20 5 5000 0 1000 LOAD CAPACITANCE (pF) FIGURE 7. TRANSMITTER OUTPUT VOLTAGE vs LOAD CAPACITANCE 3000 3.5 40 5000 NO LOAD ALL OUTPUTS STATIC 3.0 250kbps SUPPLY CURRENT (mA) 35 30 120kbps 25 20 20kbps 15 4000 FIGURE 8. SLEW RATE vs LOAD CAPACITANCE 45 2.5 2.0 1.5 1.0 0.5 10 0 1000 2000 4000 3000 0 2.5 5000 3.0 3.5 4.0 10m NO LOAD ALL OUTPUTS STATIC VCC = 3.3V 100μ 10μ VL ≤ VCC VL > VCC 1μ 100n 10n 1n 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VL (V) FIGURE 11. VL SUPPLY CURRENT vs VL VOLTAGE 9 5.0 5.5 FIGURE 10. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 9. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA 1m 4.5 SUPPLY VOLTAGE (V) LOAD CAPACITANCE (pF) IL (A) SUPPLY CURRENT (mA) 2000 LOAD CAPACITANCE (pF) 7.0 6.0 ISL4260E Die Characteristics SUBSTRATE AND QFN THERMAL PAD POTENTIAL (POWERED UP) GND TRANSISTOR COUNT 422 PROCESS Si Gate CMOS All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 ISL4260E Package Outline Drawing L32.5x5B 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 5/10 4X 3.5 5.00 28X 0.50 A B 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 32 25 1 5.00 24 3 .30 ± 0 . 15 17 (4X) 8 0.15 9 16 TOP VIEW 0.10 M C A B + 0.07 32X 0.40 ± 0.10 4 32X 0.23 - 0.05 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0.1 C BASE PLANE SEATING PLANE 0.08 C ( 4. 80 TYP ) ( ( 28X 0 . 5 ) SIDE VIEW 3. 30 ) (32X 0 . 23 ) C 0 . 2 REF 5 ( 32X 0 . 60) 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 11