EL5411T ® Data Sheet October 8, 2009 60MHz Rail-to-Rail Input-Output Operational Amplifier FN6837.1 Features • 60MHz (-3dB) Bandwidth The EL5411T is a high voltage rail-to-rail input-output amplifier with low power consumption. The EL5411T contains four amplifiers. Each amplifier exhibits beyond the rail input capability, rail-to-rail output capability and is unity gain stable. The maximum operating voltage range is from 4.5V to 19V. It can be configured for single or dual supply operation, and typically consumes only 3mA per amplifier. The EL5411T has an output short circuit capability of ±300mA and a continuous output current capability of ±70mA. The EL5411T features a high slew rate of 100V/µs, and fast settling time. Also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 60MHz (-3dB). This enables the amplifiers to offer maximum dynamic range at any supply voltage. These features make the EL5411T an ideal amplifier solution for use in TFT-LCD panels as a VCOM driver or static gamma buffer, and in high speed filtering and signal conditioning applications. Other applications include battery power and portable devices, especially where low power consumption is important. The EL5411T is available in a 14 Ld HTSSOP and a space saving thermally enhanced 16 Ld 4mmx4mm TQFN package. The device operates over an ambient temperature range of -40°C to +85°C. • 4.5V to 19V Maximum Supply Voltage Range • 100V/µs Slew Rate • 3mA Supply Current (per Amplifier) • ±70mA Continuous Output Current • ±300mA Output Short Circuit Current • Unity-gain Stable • Beyond the Rails Input Capability • Rail-to-rail Output Swing • Built-in Thermal Protection • -40°C to +85°C Ambient Temperature Range • Pb-Free (RoHS Compliant) Applications • TFT-LCD Panels • VCOM Amplifiers • Static Gamma Buffers • Drivers for A/D Converters • Data Acquisition • Video Processing • Audio Processing Ordering Information PART NUMBER (Note) PART MARKING • Active Filters PACKAGE (Pb-Free) PKG. DWG. # • Test Equipment EL5411TIREZ 5411TIRE Z 14 Ld HTSSOP M14.173A • Battery-powered Applications EL5411TIREZ-T7* 5411TIRE Z 14 Ld HTSSOP M14.173A Tape and Reel • Portable Equipment EL5411TIREZ-T13* 5411TIRE Z 14 Ld HTSSOP M14.173A Tape and Reel EL5411TILZ 5411TIL Z 16 Ld TQFN EL5411TILZ-T7* 5411TIL Z 16 Ld TQFN L16.4x4F Tape and Reel EL5411TILZ-T13* 5411TIL Z 16 Ld TQFN L16.4x4F Tape and Reel L16.4x4F *Please refer to TB347 for details on reel specifications NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5411T Pinouts EL5411T (14 LD HTSSOP) TOP VIEW VINA- 1 VINA+ 2 THERMAL PAD VS+ 3 VOUTA 1 13 NC 14 VOUTD 15 VOUTA 16 NC EL5411T (16 LD 4X4 TQFN) TOP VIEW VINA- 2 12 VIND- VINA+ 3 11 VIND+ VS+ 4 10 VS9 VINC+ VINC- 8 VOUTC 7 VOUTB 6 VINB- 5 VINB+ 4 14 VOUTD 13 VIND+ + 11 VS- VINB+ 5 VINB- 6 VOUTB 7 12 VIND+ 10 VINC+ + - + - 9 VINC8 VOUTC THERMAL PAD CONNECTS TO VS- THERMAL PAD CONNECTS TO VS- 2 FN6837.1 October 8, 2009 EL5411T Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . +19.8V Input Voltage Range (VINx+, VINx-) . . . . . . . . VS- - 0.5V, VS+ + 0.5V Input Differential Voltage (VINx+ - VINx-) . .(VS+ + 0.5V)-(VS- - 0.5V) Maximum Continuous Output Current . . . . . . . . . . . . . . . . . ±70mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3000V Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) 14 Ld HTSSOP . . . . . . . . . . . . . . . . 38 16 Ld TQFN . . . . . . . . . . . . . . . . . . . θJC (°C/W) 8 40 9 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . .See Figures 32 and 33 Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 1kΩ to 0V, TA = +25°C, Unless Otherwise Specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT 17 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 0V 3.5 TCVOS Average Offset Voltage Drift (Note 3) 14 LD HTSSOP package 26 µV/°C 16 LD TQFN package 4 µV/°C VCM = 0V 2 IB Input Bias Current RIN Input Impedance 1 GΩ CIN Input Capacitance 2 pF CMIR Common-Mode Input Range CMRR Common-Mode Rejection Ratio For VIN from -5.5V to 5.5V 50 73 dB AVOL Open-Loop Gain -4.5V ≤ VOUTx ≤ 4.5V 62 78 dB -5.5 60 nA +5.5 V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -5mA VOH Output Swing High IL = +5mA ISC Short-Circuit Current VCM = 0V, Source: VOUTx short to VS-, Sink: VOUTx short to VS+ IOUT Output Current -4.94 4.85 -4.85 V 4.94 V ±300 mA ±70 mA POWER SUPPLY PERFORMANCE (VS+) - (VS-) Supply Voltage Range IS Supply Current VCM = 0V, No load PSRR Power Supply Rejection Ratio Supply is moved from ±2.25V to ±9.5V 4.5 11 60 19 V 15 mA 75 dB DYNAMIC PERFORMANCE SR Slew Rate (Note 4) -4.0V ≤ VOUTx ≤ 4.0V, 20% to 80% 100 V/µs tS Settling to +0.1% (Note 5) AV = +1, VOUTx = 2V step, RL = 1kΩ || 1kΩ (probe), CL = 1.5pF 85 ns BW -3dB Bandwidth RF = 1kΩ, CL = 1.5pF 60 MHz GBWP Gain-Bandwidth Product AV = -10, RF = 1kΩ, RG = 100Ω RL = 1kΩ || 1kΩ (probe), CL = 1.5pF 32 MHz 3 FN6837.1 October 8, 2009 EL5411T Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, RL = 1kΩ to 0V, TA = +25°C, Unless Otherwise Specified. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT PM Phase Margin AV = -10, RF = 1kΩ, RG = 100Ω RL = 1kΩ || 1kΩ (probe), CL = 1.5pF 50 ° CS Channel Separation f = 5MHz 90 dB Electrical Specifications PARAMETER VS+ = +5V, VS- = 0V, RL = 1kΩ to 2.5V, TA = +25°C, Unless Otherwise Specified. DESCRIPTION CONDITION MIN TYP MAX UNIT 17 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 2.5V 3.5 TCVOS Average Offset Voltage Drift (Note 3) 14 LD HTSSOP package 23 µV/°C 16 LD TQFN package 3 µV/°C VCM = 2.5V 2 IB Input Bias Current RIN Input Impedance 1 GΩ CIN Input Capacitance 2 pF CMIR Common-Mode Input Range CMRR Common-Mode Rejection Ratio For VIN from -0.5V to 5.5V 45 68 dB AVOL Open-Loop Gain 0.5V ≤ VOUTx ≤ 4.5V 62 82 dB -0.5 60 nA +5.5 V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -4.2mA VOH Output Swing High IL = +4.2mA ISC Short-circuit Current VCM = 2.5V, Source: VOUTx short to VS-, Sink: VOUTx short to VS+ IOUT Output Current 60 4.85 150 mV 4.94 V ±110 mA ±70 mA POWER SUPPLY PERFORMANCE (VS+) - (VS-) Supply Voltage Range IS Supply Current VCM = 2.5V, No load PSRR Power Supply Rejection Ratio Supply is moved from 4.5V to 19V 4.5 12 60 19 V 15 mA 75 dB DYNAMIC PERFORMANCE SR Slew Rate (Note 4) 1V ≤ VOUTx ≤ 4V, 20% to 80% 75 V/µs tS Settling to +0.1% (Note 5) AV = +1, VOUTx = 2V step, RL = 1kΩ || 1kΩ (probe), CL = 1.5pF 90 ns BW -3dB Bandwidth RF = 1kΩ, CL = 1.5pF 60 MHz GBWP Gain-Bandwidth Product AV = -10, RF = 1kΩ, RG = 100Ω RL = 1kΩ || 1kΩ (probe), CL = 1.5pF 32 MHz PM Phase Margin AV = -10, RF = 1kΩ, RG = 100Ω RL = 1kΩ || 1kΩ (probe), CL = 1.5pF 50 ° CS Channel Separation f = 5MHz 90 dB 4 FN6837.1 October 8, 2009 EL5411T Electrical Specifications PARAMETER VS+ = +18V, VS- = 0V, RL = 1kΩ to 9V, TA = +25°C, Unless Otherwise Specified. DESCRIPTION CONDITION MIN TYP MAX UNIT 17 mV INPUT CHARACTERISTICS VOS Input Offset Voltage VCM = 9V 3.5 TCVOS Average Offset Voltage Drift (Note 3) 14 LD HTSSOP package 21 µV/°C 16 LD TQFN package 5 µV/°C VCM = 9V 2 IB Input Bias Current RIN Input Impedance 1 GΩ CIN Input Capacitance 2 pF CMIR Common-Mode Input Range CMRR Common-Mode Rejection Ratio For VIN from -0.5V to 18.5V 53 75 dB AVOL Open-Loop Gain 0.5V ≤ VOUTx ≤ 17.5V 62 104 dB -0.5 60 nA +18.5 V OUTPUT CHARACTERISTICS VOL Output Swing Low IL = -6mA VOH Output Swing High IL = +6mA ISC Short-circuit Current VCM = 9V, Source: VOUTx short to VS-, Sink: VOUTx short to VS+ IOUT Output Current 80 17.85 150 mV 17.92 V ±300 mA ±70 mA POWER SUPPLY PERFORMANCE (VS+) - (VS-) Supply Voltage Range IS Supply Current VCM = 9V, No load PSRR Power Supply Rejection Ratio Supply is moved from 4.5V to 19V 4.5 12.3 60 19 V 15 mA 75 dB DYNAMIC PERFORMANCE SR Slew Rate (Note 4) 1V ≤ VOUTx ≤ 17V, 20% to 80% 100 V/µs tS Settling to +0.1% (Note 5) AV = +1, VOUTx = 2V step, RL = 1kΩ || 1kΩ (probe), CL = 1.5pF 100 ns BW -3dB Bandwidth RF = 1kΩ, CL = 1.5pF 60 MHz GBWP Gain-Bandwidth Product AV = -10, RF = 1kΩ, RG = 100Ω RL = 1kΩ || 1kΩ (probe), CL = 1.5pF 32 MHz PM Phase Margin AV = -10, RF = 1kΩ, RG = 100Ω RL = 1kΩ || 1kΩ (probe), CL = 1.5pF 50 ° CS Channel Separation f = 5MHz 90 dB NOTES: 3. Measured over -40°C to +85°C ambient operating temperature range. See the typical TCVOS production distribution shown in the “Typical Performance Curves” on page 6. 4. Typical slew rate is an average of the slew rates measured on the rising (20% to 80%) and the falling (80% to 20%) edges of the output signal. 5. Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output level settles within a ±0.1% error band. The range of the error band is determined by: Final Value(V)±[Full Scale(V)*0.1%]. 5 FN6837.1 October 8, 2009 EL5411T Typical Performance Curves QUANTITY (AMPLIFIERS) 16 VS = ±5V TA = +25°C 800 TYPICAL PRODUCTION DISTRIBUTION 700 600 500 400 300 200 12 10 8 6 4 2 100 0 TYPICAL PRODUCTION DISTRIBUTION VS = ±5V -40°C to +85°C 14 QUANTITY (AMPLIFIERS) 900 -15 -13 -11 -9 -7 -5 -3 -1 1 3 5 7 9 0 11 13 15 3 9 INPUT OFFSET VOLTAGE (mV) 15 21 27 33 39 45 51 57 INPUT OFFSET VOLTAGE DRIFT (µV/°C) FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION FIGURE 2. INPUT OFFSET VOLTAGE DRIFT (HTSSOP) 0.0 VS = ±5V VS = ±5V -40°C to +85°C TYPICAL PRODUCTION DISTRIBUTION 20 15 10 5 INPUT OFFSET VOLTAGE (mV) QUANTITY (AMPLIFIERS) 25 0 0 1 2 3 4 5 6 7 8 9 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -50 10 11 12 13 14 15 0 50 FIGURE 3. INPUT OFFSET VOLTAGE DRIFT (TQFN) 4.96 VS = ±5V IOUT = +5mA OUTPUT HIGH VOLTAGE (V) VS = ±5V INPUT BIAS CURRENT (nA) 150 FIGURE 4. INPUT OFFSET VOLTAGE vs TEMPERATURE 8.0 7.5 7.0 6.5 6.0 -50 100 TEMPERATURE (°C) INPUT OFFSET VOLTAGE DRIFT (µV/°C) 0 50 100 TEMPERATURE (°C) FIGURE 5. INPUT BIAS CURRENT vs TEMPERATURE 6 150 4.94 4.92 4.90 4.88 -50 0 50 100 150 TEMPERATURE (°C) FIGURE 6. OUTPUT HIGH VOLTAGE vs TEMPERATURE FN6837.1 October 8, 2009 EL5411T Typical Performance Curves (Continued) -4.91 120 VS = ±5V IOUT = -5mA VS = ±5V RL = 1kΩ OPEN LOOP GAIN (dB) OUTPUT LOW VOLTAGE (V) -4.90 -4.92 -4.93 -4.94 -4.95 -4.96 -50 0 50 100 100 80 60 40 20 -50 150 0 50 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 7. OUTPUT LOW VOLTAGE vs TEMPERATURE 150 FIGURE 8. OPEN-LOOP GAIN vs TEMPERATURE 2.85 130 VS = ±5V NO LOAD INPUTS AT GND VS = ±5V RL = 1kΩ SUPPLY CURRENT (mA) 120 SLEW RATE (V/µs) 100 110 100 90 80 2.80 2.75 2.70 70 60 -50 0 50 100 2.65 -50 150 0 50 150 FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs TEMPERATURE FIGURE 9. SLEW RATE vs TEMPERATURE 4.0 140 TA = +25°C NO LOAD INPUTS AT GND TA = +25°C AV = 1 RL = 1kΩ CL = 8pF 120 3.5 SLEW RATE (V/µs) SUPPLY CURRENT (mA) 100 TEMPERATURE (°C) TEMPERATURE (°C) 3.0 2.5 100 80 60 2.0 2.5 3.5 4.5 5.5 6.5 7.5 8.5 SUPPLY VOLTAGE (±V) FIGURE 11. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE 7 9.5 40 2 4 6 10 8 SUPPLY VOLTAGE (±V) FIGURE 12. SLEW RATE vs SUPPLY VOLTAGE FN6837.1 October 8, 2009 EL5411T Typical Performance Curves (Continued) 100 120 100 80 60 4 6 120 PHASE 40 80 20 40 VS = ±5V RF = 5kΩ, RG = 100Ω RL = 1kΩ CL = 8pF 0 -20 10 10 8 160 GAIN 60 40 2 200 80 OPEN LOOP GAIN (dB) OPEN LOOP GAIN (dB) TA = +25°C RL = 1kΩ PHASE (°) 140 100 1k 10k SUPPLY VOLTAGE (±V) 0 100k 1M 10M -40 100M FREQUENCY (Hz) FIGURE 13. OPEN LOOP GAIN vs SUPPLY VOLTAGE FIGURE 14. OPEN LOOP GAIN AND PHASE vs FREQUENCY 10 100 200 80 6 160 120 GAIN 40 80 20 40 0 -20 10 VS = ±5V RF = 1kΩ, RG = 100Ω RL = 1kΩ || 1kΩ (PROBE) CL = 1.5pF 100 1k GAIN (dB) 4 60 PHASE (°) OPEN LOOP GAIN (dB) VS = ±5V AV = 1 CL = 1.5pF RL || 1kΩ (probe) 8 PHASE 1kΩ 2 0 -2 -4 560Ω -6 0 150Ω -8 10k 100k 1M 10M -40 100M -10 100k 1M FIGURE 15. OPEN LOOP GAIN AND PHASE vs FREQUENCY 450 400 1000pF 100pF GAIN (dB) 10 47pF 10pF 5 0 -5 -10 350 VS = ±5V AV = 1 RL = OPEN VOUTx = +15dBm 300 250 200 150 100 50 -15 -20 100k OUTPUT IMPEDANCE (Ω) VS = ±5V AV = 1 RL = 1kΩ 100M FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS RL 20 15 10M FREQUENCY (Hz) FREQUENCY (Hz) 1M 10M FREQUENCY (Hz) 100M FIGURE 17. FREQUENCY RESPONSE FOR VARIOUS CL 8 0 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 18. CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY FN6837.1 October 8, 2009 EL5411T 12 -30 10 -40 DISTORTION (dBc) MAXIMUM OUTPUT SWING (VP-P) Typical Performance Curves (Continued) 8 6 4 2 VS = ±5V AV = 1 RL = 1kΩ DISTORTION <1% 0 10k 2nd HD -50 -60 3rd HD -70 VS = ±5V AV = 2 RL = 1kΩ fIN= 1MHz -80 100k 1M 10M -90 100M 2 0 4 FREQUENCY (Hz) FIGURE 19. MAXIMUM OUTPUT SWING vs FREQUENCY -10 VS = ±5V TA = +25°C -20 -30 -30 -40 -50 -40 -50 -60 -60 -70 -70 -80 -80 -90 1k -90 1k PSRR+ 10k 100k 1M 10M 100M PSRR10k 100k FREQUENCY (Hz) 100 XTALK(dB) VOLTAGE NOISE (nV/√Hz) -40 10 MEASURED CH A TO D, OR B TO C OTHER COMBINATIONS YIELD IMPROVED REJECTION -60 -80 -100 -120 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 23. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY 9 100M -20 TA = +25°C 10k 10M FIGURE 22. PSRR vs FREQUENCY 1000 1k 1M FREQUENCY (Hz) FIGURE 21. CMRR vs FREQUENCY 1 100 10 0 VS = ±5V TA = +25°C VINx = -10dBm PSRR (dB) CMRR (dB) -20 8 FIGURE 20. HARMONIC DISTORTION vs VOP-P 0 -10 6 OUTPUT VOLTAGE (VOP-P) -140 10k VS = ±5V AV = 1 VINx = 0dBm 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 24. CHANNEL SEPARATION vs FREQUENCY FN6837.1 October 8, 2009 EL5411T Typical Performance Curves (Continued) 5 100 4 3 STEP SIZE (V) OVERSHOOT (%) 80 VS = ±5V TA = +25°C AV = 1 RL = 1kΩ VINx = ±50mV 60 40 2 VS = ±5V TA = +25°C AV = 1 RL= 1kΩ || 1kΩ (PROBE) CL =1.5pF 1 0 -1 -2 -3 20 -4 0 10 100 -5 70 1k 80 90 SETTLING TIME (ns) LOAD CAPACITANCE (pF) FIGURE 25. SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE FIGURE 26. STEP SIZE vs SETTLING TIME 1V/DIV 50mV/DIV VS = ±5V TA = +25°C AV = 1 RL= 1kΩ || 1kΩ (PROBE) CL = 1.5pF 6V STEP VS = ±5V TA = +25°C AV = 1 RL= 1kΩ || 1kΩ (PROBE) CL = 1.5pF 100mV STEP 50ns/DIV 50ns/DIV FIGURE 27. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 28. SMALL SIGNAL TRANSIENT RESPONSE EL5411T (14 LD HTSSOP shown) 1 VOUTA RLA CLA VOUTA VOUTD 14 0 0 2 3 VINA+ VINA- VIND- VINA+ VIND+ CLD 13 12 VIND+ 49.9 49.9 VS+ 4 4.7µF + Vs+ Vs- 5 49.9 6 VINB+ VINB- VINC+ VINC- 10 VINC+ 49.9 9 0 0 7 VOUTB VS+ 4.7µF 11 0.1µF 0.1µF VINB+ CLB VOUTD RLD VOUTB VOUTC 8 RLB RLC VOUTC CLC THERMAL PAD CONNECTED TO VS- FIGURE 29. BASIC TEST CIRCUIT 10 FN6837.1 October 8, 2009 EL5411T Pin Descriptions EL5411T EL5411T (14 LD HTSSOP) (16 LD TQFN) PIN NAME 1 15 VOUTA 2 1 3 FUNCTION EQUIVALENT CIRCUIT Amplifier A output (Reference Circuit 1) VINA- Amplifier A inverting input (Reference Circuit 2) 2 VINA+ Amplifier A non-inverting input (Reference Circuit 2) 4 3 VS+ 5 4 VINB+ Amplifier B non-inverting input (Reference Circuit 2) 6 5 VINB- Amplifier B inverting input (Reference Circuit 2) 7 6 VOUTB Amplifier B output (Reference Circuit 1) 8 7 VOUTC Amplifier C output (Reference Circuit 1) 9 8 VINC- Amplifier C inverting input (Reference Circuit 2) 10 9 VINC+ Amplifier C non-inverting input (Reference Circuit 2) 11 10 VS- 12 11 VIND+ Amplifier D non-inverting input (Reference Circuit 2) 13 12 VIND- Amplifier D inverting input (Reference Circuit 2) 14 14 VOUTD Amplifier D output (Reference Circuit 1) 13, 16 NC pad Thermal Pad pad Positive power supply Negative power supply (connects to GND for single supply operation) Not connected Functions as a heat sink. Connects to most negative potential, VS- VS+ VS+ VOUTx VINx GND CIRCUIT 1 11 VSVS- CIRCUIT 2 FN6837.1 October 8, 2009 EL5411T Applications Information VS = ±2.5V, TA = +25°C, AV = 1, VINx = 6VP-P, RL = 1kΩ to GND The EL5411T is a high voltage rail-to-rail input-output amplifier with low power consumption. The EL5411T contains four amplifiers. Each amplifier exhibits beyond the rail input capability, rail-to-rail output capability and is unity gain stable. The EL5411T features a high slew rate of 100V/µs, and fast settling time. Also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 60MHz (-3dB). This enables the amplifiers to offer maximum dynamic range at any supply voltage. 1V/DIV Product Description OUTPUT INPUT 10µs/DIV FIGURE 30. OPERATION WITH BEYOND-THE-RAILS INPUT Operating Voltage, Input and Output Capability VS = ±5V, TA = +25°C, AV = 1, VINx = 10VP-P, RL = 1kΩ to GND The EL5411T output typically swings to within 50mV of positive and negative supply rails with load currents of ±5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 31 shows the input and output waveforms for the device in a unity-gain configuration. Operation is from ±5V supply with a 1kΩ load connected to GND. The input is a 10VP-P sinusoid and the output voltage is approximately 9.9VP-P. Refer to the “Electrical Specifications” Table beginning on page 3 for specific device parameters. Parameter variations with operating voltage, loading and/or temperature are shown in the “Typical Performance Curves” on page 6. OUTPUT 5V/DIV The input common-mode voltage range of the EL5411T extends 500mV beyond the supply rails. Also, the EL5411T is immune to phase reversal. However, if the common mode input voltage exceeds the supply voltage by more than 0.5V, electrostatic protection diodes in the input stage of the device begin to conduct. Even though phase reversal will not occur, to maintain optimal reliability it is suggested to avoid input overvoltage conditions. Figure 30 shows the input voltage driven 500mV beyond the supply rails and the device output swinging between the supply rails. INPUT The EL5411T can operate on a single supply or dual supply configuration. The EL5411T operating voltage ranges from a minimum of 4.5V to a maximum of 19V. This range allows for a standard 5V (or ±2.5V) supply voltage to dip to -10%, or a standard 18V (or ±9V) to rise by +5.5% without affecting performance or reliability. 10µs/DIV FIGURE 31. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT Output Current The EL5411T is capable of output short circuit currents of 300mA (source and sink), and the device has built-in protection circuitry which limits the short circuit current to ±300mA (typical). To maintain maximum reliability, the continuous output current should never exceed ±70mA. This ±70mA limit is determined by the characteristics of the internal metal interconnects. Also, see “Power Dissipation” on page 13 for detailed information on ensuring proper device operation and reliability for temperature and load conditions. Unused Amplifiers It is recommended that any unused amplifiers be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground. Driving Capacitive Loads As load capacitance increases, the -3dB bandwidth will decrease and peaking can occur. Depending on the application, it may be necessary to reduce peaking and to improve device stability. To improve device stability a snubber circuit or a series resistor may be added to the output of the EL5411T. 12 FN6837.1 October 8, 2009 EL5411T Another method to reduce peaking is to add a series output resistor (typically between 1Ω to 10Ω). Depending on the capacitive loading, a small value resistor may be the most appropriate choice to minimize any reduction in gain. Power Dissipation With the high-output drive capability of the EL5411T amplifiers, it is possible to exceed the +150°C absolute maximum junction temperature under certain load current conditions. It is important to calculate the maximum power dissipation of the EL5411T in the application. Proper load conditions will ensure that the EL5411T junction temperature stays within a safe operating region. Device overheating can be avoided by calculating the minimum resistive load condition, RLOAD, resulting in the highest power dissipation. To find RLOAD set the two PDMAX equations equal to each other and solve for VOUT/ILOAD. Reference the package power dissipation curves, Figures 32 and 33, for further information. JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 POWER DISSIPATION (W) A snubber is a shunt load consisting of a resistor in series with a capacitor. An optimized snubber can improve the phase margin and the stability of the EL5411T. The advantage of a snubber circuit is that it does not draw any DC load current or reduce the gain. 962mW 1.0 TQFN16 θJA = +130°C/W 893mW 0.8 0.6 HTSSOP14 θJA = +140°C/W 0.4 0.2 The maximum power dissipation allowed in a package is determined according to Equation 1: 0.0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) T JMAX – T AMAX P DMAX = --------------------------------------------θ JA (EQ. 1) FIGURE 32. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE where: • TJMAX = Maximum junction temperature JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD - EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 • TAMAX = Maximum ambient temperature • ΘJA = Thermal resistance of the package The total power dissipation produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power dissipation in the IC due to the loads, or: P DMAX = Σi [ V S × I SMAX + ( V S + – V OUT i ) × I LOAD i ] (EQ. 2) when sourcing, and: POWER DISSIPATION (W) 4.0 • PDMAX = Maximum power dissipation allowed 3.29W 3.5 3.0 HTSSOP14 θJA = +38°C/W 3.13W 2.5 TQFN16 θJA = +40°C/W 2.0 1.5 1.0 0.5 P DMAX = Σi [ V S × I SMAX + ( V OUT i – V S - ) × I LOAD i ] (EQ. 3) 0.0 0 when sinking, 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 33. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE where: • i = 1 to 4 (1, 2, 3, 4 corresponds to Channel A, B, C, D respectively) • VS = Total supply voltage (VS+ - VS-) • VS+ = Positive supply voltage • VS- = Negative supply voltage • ISMAX = Maximum supply current per amplifier (ISMAX = EL5411T quiescent current ÷ 4) Thermal Shutdown The EL5411T has a built-in thermal protection which ensures safe operation and prevents internal damage to the device due to overheating. When the die temperature reaches +165°C (typical) the device automatically shuts OFF the outputs by putting them in a high impedance state. When the die cools by +15°C (typical) the device automatically turns ON the outputs by putting them in a low impedance (normal) operating state. • VOUT = Output voltage • ILOAD = Load current 13 FN6837.1 October 8, 2009 EL5411T Power Supply Bypassing and Printed Circuit Board Layout The EL5411T can provide gain at high frequency, so good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, trace lengths should be as short as possible and the power supply pins must be well bypassed to reduce any risk of oscillation. For normal single supply operation (the VS- pin is connected to ground) a 4.7µF capacitor should be placed from VS+ to ground, then a parallel 0.1µF capacitor should be connected as close to the amplifier as possible. One 4.7µF capacitor may be used for multiple devices. For dual supply operation the same capacitor combination should be placed at each supply pin to ground. It is highly recommended that EL5411T exposed thermal pad packages should always have the pad connected to the lowest potential, VS-, to optimize thermal and operating performance. PCB vias should be placed below the device’s exposed thermal pad to transfer heat to the VS- plane and away from the device. Revision History DATE REVISION CHANGE 10/8/09 FN6837.1 Updated Ordering Information by removing “contact factory for availability”. add "vs FREQUENCY" to the plot titles in Fig 14,15,18,21,22,23,24: Fig 21: changed y-axis label to read "CMRR (dB)" Fig 22: changed y-axis label to read "PSRR (dB)" Fig 26: changed label to read "STEP SIZE vs SETTLING TIME" Changed 1st sentence in pages 1 and 12 from “The EL5411T is a low power, high voltage railto-rail input-output amplifier” to “The EL5411T is a high voltage rail-to-rail input-output amplifier with low power consumption”. Updated package outline drawing M14.173A to add land pattern and move dimensions from table onto drawing 8/21/09 FN6837.0 Initial Release. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN6837.1 October 8, 2009 EL5411T Package Outline Drawing L16.4x4F 16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 04/09 4X 1.95 4.00 12X 0.65 A B 13 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 16 1 4.00 12 2 . 70 ± 0 . 05 9 (4X) 4 0.15 8 5 0.10 M C A B 16X 0 . 4 ± 0 . 05 4 0.30 ± 0 . 05 TOP VIEW BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 75 ± 0 . 05 C 0.08 C SIDE VIEW ( 3 . 8 TYP ) ( 12X 0 . 65 ) ( 2 . 70 TYP ) C 0 . 2 REF 5 ( 16X 0 .30 ) 0 . 00 MIN. 0 . 05 MAX. ( 16 X 0 . 6 ) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 15 FN6837.1 October 8, 2009 EL5411T Package Outline Drawing M14.173A 14 LEAD HEAT-SINK THIN SHRINK SMALL OUTLINE PACKAGE (HTSSOP) Rev 1, 9/09 A 1 3 3.20 ±0.10 5.00 ±0.10 14 SEE DETAIL "X" 8 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3.00 ±0.10 3 1 7 0.20 C B A B 0.65 EXPOSED THERMAL PAD 0.09-0.20 END VIEW TOP VIEW BOTTOM VIEW 1.00 REF 0.05 H C 0.90 +0.15/-0.10 1.20 MAX SEATING PLANE GAUGE PLANE 0.25 +0.05/-0.06 0.10 C 0.10 0.25 5 0°- 8° 0.05 MIN 0.15 MAX CBA SIDE VIEW 0.60 ±0.15 DETAIL "X" NOTES: (1.45) 1. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. (5.65) 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation ABT-1. (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN 16 FN6837.1 October 8, 2009