HS-82C08RH Radiation Hardened 8-Bit Bus Transceiver February 1996 Features Functional Diagram • Devices QML Qualified in Accordance With MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95714 and Intersil’ QM Plan A0 B0 • Radiation Hardened B1 B2 B3 B4 PORT B B5 B6 B7 A1 A2 A3 PORT A4 A A5 A6 A7 - Total Dose 1 x 105 RAD (Si) - Latch-Up Immune EPI-CMOS > 1 x 1012 RAD (Si)/s • Bidirectional Three-State Input/Outputs • Low Propagation Delay Time • Low Power Consumption • Single Power Supply +5V T/R • Electrically Equivalent to Sandia SA2997 • Military Temperature Range -55oC to +125oC Description OE TRUTH TABLE The Intersil HS-82C08RH is a radiation-hardened octal bus transceiver with three-state outputs. It is manufactured using a self-aligned, junction isolated CMOS process and is designed for use with the HS-80C08RH radiation-hardened microprocessor. The HS-82C08RH allows asynchronous two-way communication between data buses. The direction of data flow is determined by the logic level on the transmit/ receive (T/R) input. A logic high on the T/R input specifies data flow from Port A to Port B of the device. Conversely, a logic low on the T/R input specifies data flow from Port B to Port A. The Output Enable input disables both ports by placing them in the high impedance state. INPUTS OPERATION OUTPUT ENABLE TRANSMIT /RECEIVE PORT A PORT B 0 0 Out In 0 1 In Out 1 X High Z High Z X = Don’t Care The HS-82C08RH is ideally suited for a wide variety of buffering applications in radiation-hardened microcomputer systems. Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE 5962R9571401QRC -55oC to +125oC MIL-PRF-38535 Level Q 20 Lead SBDIP 5962R9571401QXC -55oC +125oC MIL-PRF-38535 Level Q 20 Lead Ceramic Flatpack 5962R9571401VRC -55oC to +125oC MIL-PRF-38535 Level V 20 Lead SBDIP 5962R9571401VXC -55oC MIL-PRF-38535 Level V 20 Lead Ceramic Flatpack to to +125oC HS1-82C08RH/SAMPLE +25oC SAMPLE 20 Lead SBDIP HS9-82C08RH/SAMPLE +25oC SAMPLE 20 Lead Ceramic Flatpack CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 Spec Number File Number 518057 3040.2 HS-82C08RH Pinouts 20 LEAD CERAMIC DUAL-IN-LINE METAL-SEAL PACKAGE (SBDIP) MIL-STD-1835, CDIP2-T20 TOP VIEW 20 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835, CDFP4-F20 TOP VIEW A0 1 20 VDD A0 1 20 VDD A1 2 19 B0 A1 2 19 B0 A2 3 18 B1 A2 3 18 B1 A3 4 17 B2 A3 4 17 B2 A4 5 16 B3 A5 6 15 B4 A6 7 14 B5 A7 8 13 B6 9 12 B7 10 11 T/R A4 5 16 B3 A5 6 15 B4 A6 7 14 B5 A7 8 13 B6 OE OE 9 12 B7 GND GND 10 11 T/R PIN DESCRIPTION PIN DESCRIPTION A0-A7 Local Bus Data I/O Pins T/R Transmit/Receive Input B0-B7 System Bus Data I/O Pins OE Active Low Output Enable Logic Diagram A0 TSB 1 19 B0 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 TSB A1 TSB 2 TSB A2 TSB 3 TSB A3 TSB 4 TSB A4 TSB 5 TSB A5 TSB 6 OE 9 B ENABLE A6 TSB TSB 7 TSB A ENABLE T/R11 A7 8 TSB TSB NOTE: An Important caveat that is applicable to CMOS devices in general is that unused inputs should never be left floating. This rule applies to inputs connected to a three-state bus. The need for external pull-up resistors during three-state bus conditions is eliminated by the presence of regenerative latches on the following HS-82C08RH pins. A0-7 and B0-7 The functional block diagram depicts one of these pins with the regenerative latch. When the CMOS driver assumes the high impedance state, the latch holds the bus in whatever logic state (high or low) it was before the three-state condition. A transient drive current of ±1.5mA at VDD/2 ±0.5V for 10ns is required to switch the latch. Thus, CMOS device inputs connected to the bus are not allowed to float during three-state conditions. Spec Number 2 518057 Specifications HS-82C08RH Absolute Maximum Ratings Reliability Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VDD+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC 20 Lead SBDIP Package. . . . . . . . . . . . . 71oC/W 17oC/W 20 Lead Ceramic Flatpack Package . . . . 85oC/W 25oC/W Maximum Package Power Dissipation at +125oC Ambient 20 Lead SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.70W 20 Lead Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . 0.59W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: 20 Lead SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . .14.1mW/C 20 Lead Ceramic Flatpack Package . . . . . . . . . . . . . . . 11.8mW/C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +1V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . VDD -1V to VDD TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS All Devices Guaranteed at Worst Case Limits and Conditions. PARAMETER SYMBOL Input Leakage Current IIL IIH GROUP A SUBGROUPS CONDITIONS LIMITS TEMPERATURE -55oC, +25oC, MIN MAX UNITS -1.0 - µA VDD = 5.25V, VIN = VDD Pin Under Test = 0V 1, 2, 3 VDD = 5.25V, VIN = 0V Pin Under Test = 5.25V 1, 2, 3 -55oC, +25oC, +125oC - 1.0 µA +125oC High Level Output Voltage VOH VDD = 4.75V, IOH = -2.0mA 1, 2, 3 -55oC, +25oC, +125oC 4.25 - V Low Level Output Voltage VOL VDD = 5.25V, IOL = 2.0mA 1, 2, 3 -55oC, +25oC, +125oC - 0.5 V Static Current SIDD VDD = 5.25V, VIN = GND 1, 2, 3 -55oC, +25oC, +125oC - 100 µA 7, 8A, 8B -55oC, +25oC, +125oC - - - Functional Test FT VDD = 4.75V to 5.25V VIH = VDD -1.0V, VIL = 1.0V TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS SYMBOL GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS Propagation Delay to Logical “1” from Port A, B to Port B, A TPDLH 9, 10, 11 -55oC, +25oC, +125oC - 65 ns Propagation Delay to Logical “0” from Port A, B to Port B, A TPDHL 9, 10, 11 -55oC, +25oC, +125oC - 80 ns Propagation Delay from High-Impedance to Logical “1” from T/R to Port TPRTH 9, 10, 11 -55oC, +25oC, +125oC - 75 ns Propagation Delay from High-Impedance to Logical “0” from T/R to Port TPRTL 9, 10, 11 -55oC, +25oC, +125oC - 130 ns Propagation Delay from High-Impedance to Logical “1” from OE to Port TPZH 9, 10, 11 -55oC, +25oC, +125oC - 70 ns Propagation Delay from High-Impedance to Logical “0” from OE to Port TPZL 9, 10, 11 -55oC, +25oC, +125oC - 130 ns PARAMETER PORT DATA/MODE SPECIFICATIONS Spec Number 3 518057 Specifications HS-82C08RH TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL In/Out Capacitance LIMITS (NOTE) CONDITIONS CI/O TEMPERATURE MIN MAX UNITS +25oC - 10 pF VDD = Open, f = 1MHz All Measurements Referenced to GND. TRANSMIT/RECEIVE MODE SPECIFICATIONS (AC Parameters) Propagation Delay from Logical “1” to High-Impedance from T/R to Port TPHZTR +25oC - 35 ns Propagation Delay from Logical “0” to High-Impedance from T/R to Port TPLZTR +25oC - 35 ns Propagation Delay from Logical “1” to High-Impedance from OE to Port TPHZ +25oC - 35 ns Propagation Delay from Logical “0” to High-Impedance from OE to Port TPLZ +25oC - 35 ns NOTE: 1. The parameters listed are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which could affect these characteristics. TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: The Post Irradiation test conditions and limits are the same as those listed in Table 1 and Table 2. TABLE 5. BURN-IN DELTA PARAMETERS (+25oC; In Accordance With SMD) Switching Time Waveforms TR INPUT AN OR BN OUTPUT BN OR AN VDD TF 0.5VDD 0V DEVICE UNDER TEST 0.5VDD tPLH TEST POINTS CL (NOTE) tPHL VDD 0.5VDD 0V 0.5VDD TR = TF ≤ 20ns 10% to 90% NOTE: CL includes stray and jig capacitance. FIGURE 1. PORT TO PORT VDD FIGURE 2. AC TESTING LOAD CIRCUIT TR = TF ≤ 20ns 10% to 90% TR INPUT OE 0.5VDD 0V TF 0.5VDD 0.1VDD tPZH PORT VOH OUTPUT 0.5VDD 0V tPHZ tPLZ VDD 0.5VDD PORT VOL OUTPUT tPZL 0.1VDD FIGURE 3. OE TO HIGH-IMPEDANCE, OE TO PORT OUTPUT Spec Number 4 518057 HS-82C08RH Metallization Topology DIE DIMENSIONS: 76.0 mils x 89.4 mils x 14 mils ±1 mil METALLIZATION: Type: Si - Al Thickness: 11kÅ ±2kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ Metallization Mask Layout (19) B0 (1) A0 (20) VDD HS-82C08RH (17) B2 A3 (4) (16) B3 A4 (5) (15) B4 A5 (6) (14) B5 A6 (7) (13) B6 A7 (8) (12) B7 T/R (9) A2 (3) GND (10) (18) B1 OE (9) A1 (2) Spec Number 5 518057 HS-82C08RH All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Spec Number 6