ISL5961 TM Data Sheet September 2001 14-Bit, +3.3V, 130/210+MSPS, CommLinkTM High Speed D/A Converter • Speed Grades . . . . . . . . . . . . . . . . 130M and 210+MSPS This device complements the CommLink ISL5x61 family of high speed converters, which include 10, 12, and 14-bit devices. Ordering Information TEMP. RANGE (oC) PACKAGE PKG. NO. M28.3 CLOCK SPEED -40 to 85 28 Ld SOIC ISL5961IA -40 to 85 28 Ld TSSOP M28.173 130MHz ISL5961/2IB -40 to 85 28 Ld SOIC 210MHz ISL5961/2IA -40 to 85 28 Ld TSSOP M28.173 25 • Low Power . . . . . 103mW with 20mA Output at 130MSPS • Adjustable Full Scale Output Current. . . . . 2mA to 20mA • +3.3V Power Supply • 3V LVCMOS Compatible Inputs • Excellent Spurious Free Dynamic Range (75dBc to Nyquist, f S = 130MSPS, fOUT = 10MHz) • UMTS Adjacent Channel Power =71dB at 19.2MHz • EDGE/GSM SFDR = 94dBc at 11MHz in 20MHz Window • Pin compatible, 3.3V, Lower Power Replacement For The AD9754 and HI5960 ISL5961IB ISL5961EVAL1 6007.2 Features The ISL5961 is a 14-bit, 130/210+MSPS (Mega Samples Per Second), CMOS, high speed, low power, D/A (digital to analog) converter, designed specifically for use in high performance communication systems such as base transceiver stations utilizing 2.5G or 3G cellular protocols. PART NUMBER File Number M28.3 130MHz 210MHz SOIC Evaluation Platform 210MHz Applications • Cellular Infrastructure - Single or Multi-Carrier: IS-136, IS95, GSM, EDGE, CDMA2000, WCDMA, TDS-CDMA • BWA Infrastructure • Medical/Test Instrumentation • Wireless Communication Systems • High Resolution Imaging Systems Pinout • Arbitrary Waveform Generators ISL5961 TOP VIEW D13 (MSB) 1 28 CLK D12 2 27 DVDD D11 3 26 DCOM D10 4 25 NC D9 5 24 AVDD D8 6 23 COMP D7 7 22 IOUTA D6 8 21 IOUTB D5 9 20 ACOM D4 10 19 NC D3 11 18 FSADJ D2 12 17 REFIO D1 13 16 REFLO D0 (LSB) 14 15 SLEEP 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001, All Rights Reserved CommLink™ is a trademark of Intersil Americas Inc. ISL5961 Typical Applications Circuit ISL5961 D13 D13 (1) (25, 19) NC D12 D12 (2) D11 D11 (3) (15) SLEEP (16) REFLO D10 D10 (4) D9 D9 (5) D8 D8 (6) D7 D7 (7) D6 D6 (8) D5 D5 (9) D4 D4 (10) D3 D3 (11) D2 D2 (12) D1 D1 (13) D0 D0 (LSB) (14) ONE CONNECTION DCOM (17) REFIO 0.1µF (18) FSADJ RSET 1:1, Z1:Z2 (22) IOUTA (21) IOUTB REPRESENTS ANY 50Ω LOAD (23) COMP 0.1µF DCOM (26) BEAD + 10µF 10µH (20) ACOM FERRITE BEAD (24) AVDD DVDD (27) + 10µH 0.1µF 0.1µF 10µF Functional Block Diagram IOUTA IOUTB (LSB) D0 D1 CASCODE CURRENT SOURCE D2 D3 D4 INPUT LATCH D5 40 D6 SWITCH MATRIX D7 40 9 LSBs + 31 MSB SEGMENTS D8 D9 D10 D11 D12 UPPER 5-BIT DECODER (MSB) D13 COMP CLK INT/EXT VOLTAGE BIAS GENERATION REFERENCE REFLO REFIO 2 1.91kΩ (50Ω) 50Ω CLK (28) 50Ω ACOM FSADJ SLEEP +3.3V (VDD) ISL5961 Pin Descriptions PIN NO. PIN NAME DESCRIPTION 1-14 D13 (MSB) Through D0 (LSB) 15 SLEEP Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin has internal 20µA active pulldown current. 16 REFLO Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference. 17 REFIO Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use 0.1µF cap to ground when internal reference is enabled. 18 FSADJ Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current = 32 x VFSADJ/RSET. 19, 25 NC 21 IOUTB The complementary current output of the device. Full scale output current is achieved when all input bits are set to binary 0. 22 IOUTA Current output of the device. Full scale output current is achieved when all input bits are set to binary 1. 23 COMP Connect 0.1µF capacitor to ACOM. 24 AV DD Analog Supply (+2.7V to +3.6V). 20 ACOM Connect to Analog Ground. 26 DCOM Connect to Digital Ground. 27 DV DD Digital Supply (+2.7V to +3.6V). 28 CLK Digital Data Bit 13, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit). No Connect. These should be grounded, but can be left disconnected. Clock Input. 3 ISL5961 Absolute Maximum Ratings Thermal Information Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +3.6V Analog Supply Voltage AV DD to ACOM . . . . . . . . . . . . . . . . . +3.6V Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . DVDD + 0.3V Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA Thermal Resistance (Typical, Note 1) Operating Conditions θJA(oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. AVDD = DVDD = +3.3V, V REF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values Electrical Specifications TA = -40oC TO 85oC PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 14 - - Bits -5 ±2.5 +5 LSB -3 ±1.5 SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL “Best Fit” Straight Line (Note 7) Differential Linearity Error, DNL (Note 7) Offset Error, IOS IOUTA (Note 7) Offset Drift Coefficient (Note 7) Full Scale Gain Error, FSE Full Scale Gain Drift With External Reference (Note 7) With Internal Reference (Note 7) -0.006 +3 LSB +0.006 % FSR - 0.1 - ppm FSR/oC With External Reference (Notes 2, 7) -3 ±0.5 +3 % FSR With Internal Reference (Notes 2, 7) -3 ±0.5 +3 % FSR - ±50 - ppm FSR/oC - ±100 - ppm FSR/oC 2 - 20 mA (Note 3) -1.0 - 1.25 V Maximum Clock Rate, fCLK ISL5961/2IA, ISL5961/2IB 210 250 - MHz Maximum Clock Rate, fCLK ISL5961IA, ISL5961IB 130 150 - MHz Output Rise Time Full Scale Step - 1.5 - ns Output Fall Time Full Scale Step - 1.5 - ns - 10 - pF IOUTFS = 20mA - 50 - pA/√Hz IOUTFS = 2mA - 30 - pA/√Hz fCLK = 210MSPS, fOUT = 80.8MHz, 30MHz Span (Notes 4, 7) - 73 - dBc fCLK = 210MSPS, fOUT = 40.4MHz, 30MHz Span (Notes 4, 7) - 82 - dBc fCLK = 130MSPS, fOUT = 20.2MHz, 20MHz Span (Notes 4, 7) - 86 - dBc Full Scale Output Current, IFS Output Voltage Compliance Range DYNAMIC CHARACTERISTICS Output Capacitance Output Noise AC CHARACTERISTICS (Using Figure 13 with RDIFF = 50Ω and RLOAD= 50Ω, Full Scale Output = -2.5dBm) Spurious Free Dynamic Range, SFDR Within a Window 4 ISL5961 AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) Electrical Specifications TA = -40oC TO 85oC PARAMETER TEST CONDITIONS Spurious Free Dynamic Range, SFDR to Nyquist (fCLK/2) MIN TYP MAX UNITS fCLK = 210MSPS, fOUT = 80.8MHz (Notes 4, 7) - 52 - dBc fCLK = 210MSPS, fOUT = 40.4MHz (Notes 4, 7, 9) - 61 - dBc fCLK = 200MSPS, fOUT = 20.2MHz, T = 25oC (Notes 4, 7) 62 64 - dBc fCLK = 200MSPS, fOUT = 20.2MHz, T = -40oC to 85oC (Notes 4, 7) 60 - - dBc fCLK = 130MSPS, fOUT = 50.5MHz (Notes 4, 7) - 59 - dBc fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 7) - 63 - dBc fCLK = 130MSPS, fOUT = 20.2MHz (Notes 4, 7) - 70 - dBc fCLK = 130MSPS, fOUT = 10.1MHz (Notes 4, 7) - 75 - dBc fCLK = 130MSPS, fOUT = 5.05MHz, T = 25oC (Notes 4, 7) 72 79 - dBc fCLK = 130MSPS, fOUT = 5.05MHz, T = -40oC to 85oC (Notes 4, 7) 70 - - dBc fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 7) - 61 - dBc fCLK = 80MSPS, fOUT = 30.3MHz (Notes 4, 7) - 65 - dBc fCLK = 80MSPS, fOUT = 20.2MHz (Notes 4, 7) - 71 - dBc fCLK = 80MSPS, fOUT = 10.1MHz (Notes 4, 7, 9) - 71 - dBc fCLK = 80MSPS, fOUT = 5.05MHz (Notes 4, 7) - 78 - dBc fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 7) - 70 - dBc fCLK = 50MSPS, fOUT = 10.1MHz (Notes 4, 7) - 75 - dBc fCLK = 50MSPS, fOUT = 5.05MHz (Notes 4, 7) - 79 - dBc fCLK = 210MSPS, fOUT = 28.3MHz to 45.2MHz, 2.1MHz Spacing, 50MHz Span (Notes 4, 7, 9) - 67 - dBc fCLK = 130MSPS, fOUT =17.5MHz to 27.9MHz, 1.3MHz Spacing, 35MHz Span (Notes 4, 7) - 70 - dBc fCLK = 80MSPS, fOUT = 10.8MHz to 17.2MHz, 811kHz Spacing, 15MHz Span (Notes 4, 7) - 77 - dBc fCLK = 50MSPS, fOUT = 6.7MHz to 10.8MHz, 490kHz Spacing, 10MHz Span (Notes 4, 7) - 78 - dBc fCLK = 78MSPS, fOUT = 11MHz, in a 20MHz Window, RBW=30kHz Spurious Free Dynamic Range, SFDR in a Window with EDGE or GSM (Notes 4, 7, 9) - 94 - dBc Adjacent Channel Power Ratio, ACPR with UMTS - 71 - dB 1.2 1.23 1.3 V - ±40 - ppm/oC - 0 - µA Reference Input Impedance - 1 - MΩ Reference Input Multiplying Bandwidth (Note 7) - 1.0 - MHz Spurious Free Dynamic Range, SFDR in a Window with Eight Tones fCLK = 76.8MSPS, fOUT = 19.2MHz, RBW=30kHz (Notes 4, 7, 9) VOLTAGE REFERENCE Internal Reference Voltage, VFSADJ Pin 18 Voltage with Internal Reference Internal Reference Voltage Drift Internal Reference Output Current Sink/Source Capability Reference is not intended to be externally loaded DIGITAL INPUTS D13-D0, CLK Input Logic High Voltage with 3.3V Supply, VIH (Note 3) 2.3 3.3 - V Input Logic Low Voltage with 3.3V Supply, V IL (Note 3) - 0 1.0 V -25 - +25 µA Sleep Input Current, IIH 5 ISL5961 AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) Electrical Specifications TA = -40oC TO 85oC PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Input Logic Current, IIH, IL -20 - +20 µA Clock Input Current, IIH, IL -10 - +10 µA - 5 - pF Digital Input Capacitance, CIN TIMING CHARACTERISTICS Data Setup Time, tSU See Figure 15 - 1.5 - ns Data Hold Time, tHLD See Figure 15 - 1.5 - ns Propagation Delay Time, tPD See Figure 15 - 1 - Clock Period CLK Pulse Width, tPW1 , tPW2 See Figure 15 (Note 3) 2 - - ns POWER SUPPLY CHARACTERISTICS AVDD Power Supply (Note 8) 2.7 3.3 3.6 V DV DD Power Supply (Note 8) 2.7 3.3 3.6 V Analog Supply Current (IAVDD) 3.3V, IOUTFS = 20mA - 27.5 28.5 mA 3.3V, IOUTFS = 2mA - 10 - mA 3.3V (Note 5) - 3.7 5 mA 3.3V (Note 6) - 6.5 8 mA Supply Current (IAVDD) Sleep Mode 3.3V, IOUTFS = Don’t Care - 1.5 - mA Power Dissipation 3.3V, IOUTFS = 20mA (Note 5) - 103 111 mW 3.3V, IOUTFS = 20mA (Note 6) - 110 120 mW 3.3V, IOUTFS = 2mA (Note 5) - 45 - mW -0.125 - +0.125 %FSR/V Digital Supply Current (IDVDD) Power Supply Rejection Single Supply (Note 7) NOTES: 2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA). Ideally the ratio should be 32. 3. Parameter guaranteed by design or characterization and not production tested. 4. Spectral measurements made with differential transformer coupled output and no external filtering. For multitone testing, the same pattern was used at different clock rates, producing different output frequencies but at the same ratio to the clock rate. 5. Measured with the clock at 130MSPS and the output frequency at 5MHz. 6. Measured with the clock at 200MSPS and the output frequency at 20MHz. 7. See “Definition of Specifications.” 8. Recommended operation is from 3.0V to 3.6V. Operation below 3.0V is possible with some degradation in spectral performance. Reduction in analog output current may be necessary to maintain spectral performance. 9. See Typical Performance Plots. 6 ISL5961 Typical Performance (+3.3V Supply, Using Figure 13 with RDIFF = 100Ω and RLOAD= 50Ω) SPECTRAL MASK FOR GSM900/DCS1800/PCS1900 P>43dBm NORMAL BTS WITH 30kHz RBW FIGURE 1. EDGE AT 11MHz, 78MSPS CLOCK (94+dBc @ ∆f = +6MHz) FIGURE 2. EDGE AT 11MHz, 78MSPS CLOCK (77dBc -NYQUIST, 6dB PAD) SPECTRAL MASK FOR GSM900/DCS1800/PCS1900 P>43dBm NORMAL BTS WITH 30kHz RBW FIGURE 3. GSM AT 11MHz, 78MSPS CLOCK (94+dBc @ ∆f = +6MHz, 3dB PAD) FIGURE 4. GSM AT 11MHz, 78MSPS CLOCK (79dBc - NYQUIST, 9dB PAD) FIGURE 5. FOUR EDGE CARRIERS AT 12.4-15.6MHz, 800kHz SPACING, 78MSPS (75+dBc - 20MHz WINDOW) FIGURE 6. FOUR GSM CARRIERS AT 12.4-15.6MHz, 78MSPS (75+dBc - 20MHz WINDOW, 6dB PAD) 7 ISL5961 Typical Performance (+3.3V Supply, Using Figure 13 with RDIFF = 100Ω and RLOAD= 50Ω) (Continued) SPECTRAL MASK UMTS TDD P>43dBm BTS FIGURE 7. UMTS AT 19.2MHz, 76.8MSPS (71dB 1stACPR, 75dB 2ndACPR) FIGURE 9. ONE TONE AT 40.4MHz, 210MSPS CLOCK (61dBc - NYQUIST, 6dB PAD) FIGURE 11. TWO TONES (CF=6) AT 8.5MHz, 50MSPS CLOCK, 500kHz SPACING (83dBc - 10MHz WINDOW, 6dB PAD) 8 FIGURE 8. ONE TONE AT 10.1MHz, 80MSPS CLOCK (71dBc NYQUIST, 6dB PAD) FIGURE 10. EIGHT TONES (CREST FACTOR=8.9) AT 37MHz, 210MSPS CLOCK, 2.1MHz SPACING (65dBc - NYQUIST) FIGURE 12. FOUR TONES (CF=8.1) AT 14MHz, 80MSPS CLOCK, 800kHz SPACING (70dBc - NYQUIST, 6dB PAD) ISL5961 Definition of Specifications Adjacent Channel Power Ratio, ACPR, is the ratio of the average power in the adjacent frequency channel (or offset) to the average power in the transmitted frequency channel. Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. EDGE, Enhanced Data for Global Evolution, a TDMA standard for cellular applications which uses 200kHz BW, 8PSK modulated carriers. Full Scale Gain Drift, is measured by setting the data inputs to be all logic high (all 1s) and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (full scale range) per oC. Full Scale Gain Error, is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through RSET). GSM, Global System for Mobile Communication, a TDMA standard for cellular applications which uses 200kHz BW, GMSK modulated carriers. Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Internal Reference Voltage Drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm per oC. Offset Drift, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage at IOUTA through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (full scale range) per degree oC. Offset Error, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage of IOUTA through a known resistance. Offset error is defined as the maximum deviation of the IOUTA output current from a value of 0mA. Output Voltage Compliance Range, is the voltage limit imposed on the output. The output impedance should be chosen such that the voltage developed does not violate the compliance range. Power Supply Rejection, is measured using a single power supply. The nominal supply voltage is varied ±10% and the change in the DAC full scale output is noted. 9 Reference Input Multiplying Bandwidth, is defined as the 3dB bandwidth of the voltage reference input. It is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. The frequency is increased until the amplitude of the output waveform is 0.707 (-3dB) of its original value. Spurious Free Dynamic Range, SFDR, is the amplitude difference from the fundamental signal to the largest harmonically or non-harmonically related spur within the specified frequency window. Total Harmonic Distortion, THD, is the ratio of the RMS value of the fundamental output signal to the RMS sum of the first five harmonic components. UMTS, Universal Mobile Telecommunications System, a W-CDMA standard for cellular applications which uses 3.84MHz modulated carriers. Detailed Description The ISL5961 is a 14-bit, current out, CMOS, digital to analog converter. The maximum update rate is at least 210+MSPS and can be powered by a single power supply in the recommended range of +3.0V to +3.6V. Operation with clock rates higher than 210MSPS is possible; please contact the factory for more information. It consumes less than 120mW of power when using a +3.3V supply, the maximum 20mA of output current, and the data switching at 210MSPS. The architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. In previous architectures that contained all binary weighted current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worst-case transition points such as midscale and quarter scale transitions. By greatly reducing the amount of current switching at these major transitions, the overall glitch of the converter is dramatically reduced, improving settling time, transient problems, and accuracy. Digital Inputs and Termination The ISL5961 digital inputs are guaranteed to 3V LVCMOS levels. The internal register is updated on the rising edge of the clock. To minimize reflections, proper termination should be implemented. If the lines driving the clock and the digital inputs are long 50Ω lines, then 50Ω termination resistors should be placed as close to the converter inputs as possible connected to the digital ground plane (if separate grounds are used). These termination resistors are not likely needed as long as the digital waveform source is within a few inches of the DAC. For pattern drivers with very high speed edge rates, it is recommended that the user consider series termination (50-200Ω) prior to the DAC’s inputs in order to reduce the amount of noise. ISL5961 Power Supply Separate digital and analog power supplies are recommended. The allowable supply range is +2.7V to +3.6V. The recommended supply range is +3.0 to 3.6V (nominally +3.3V) to maintain optimum SFDR. However, operation down to +2.7V is possible with some degradation in SFDR. Reducing the analog output current can help the SFDR at +2.7V. The SFDR values stated in the table of specifications were obtained with a +3.3V supply. Ground Planes Separate digital and analog ground planes should be used. All of the digital functions of the device and their corresponding components should be located over the digital ground plane and terminated to the digital ground plane. The same is true for the analog components and the analog ground plane. Noise Reduction To minimize power supply noise, 0.1µF capacitors should be placed as close as possible to the converter’s power supply pins, AVDD and DVDD . Also, the layout should be designed using separate digital and analog ground planes and these capacitors should be terminated to the digital ground for DVDD and to the analog ground for AVDD . Additional filtering of the power supplies on the board is recommended. Voltage Reference The internal voltage reference of the device has a nominal value of +1.23V with a ±40ppm/ oC drift coefficient over the full temperature range of the converter. It is recommended that a 0.1µF capacitor be placed as close as possible to the REFIO pin, connected to the analog ground. The REFLO pin (16) selects the reference. The internal reference can be selected if pin 16 is tied low (ground). If an external reference is desired, then pin 16 should be tied high (the analog supply voltage) and the external reference driven into REFIO, pin 17. The full scale output current of the converter is a function of the voltage reference used and the value of RSET . IOUT should be within the 2mA to 20mA range, though operation below 2mA is possible, with performance degradation. If the internal reference is used, VFSADJ will equal approximately 1.2V (pin 18). If an external reference is used, VFSADJ will equal the external reference. The calculation for IOUT (Full Scale) is: IOUT(Full Scale) = (VFSADJ/RSET) X 32. If the full scale output current is set to 20mA by using the internal voltage reference (1.2V) and a 1.91kΩ RSET resistor, then the input coding to output current will resemble the following: 10 TABLE 1. INPUT CODING vs OUTPUT CURRENT WITH INTERNAL REFERENCE AND RSET=1.91KΩ INPUT CODE (D13-D0) IOUTA (mA) IOUTB (mA) 1111 11111 11111 20 0 1000 00000 00000 10 10 0000 00000 00000 0 20 Analog Output IOUTA and IOUTB are complementary current outputs. The sum of the two currents is always equal to the full scale output current minus one LSB. If single ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be either grounded or equally terminated. The voltage developed at the output must not violate the output voltage compliance range of -1.0V to 1.25V. ROUT (the impedance loading each current output) should be chosen so that the desired output voltage is produced in conjunction with the output full scale current. If a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. The output voltage equation is: VOUT = IOUT X ROUT. The most effective method for reducing the power consumption is to reduce the analog output current, which dominates the supply current. The maximum recommended output current is 20mA. Differential Output IOUTA and IOUTB can be used in a differential-to-singleended arrangement to achieve better harmonic rejection. With RDIFF= 50Ω and RLOAD =50Ω, the circuit in Figure 13 will provide a 500mV (-2.5dBm) signal at the output of the transformer if the full scale output current of the DAC is set to 20mA (used for the electrical specifications table). Values of R DIFF= 100Ω and RLOAD=50Ω were used for the typical performance curves to increase the output power and the dynamic range. The center tap in Figure 13 must be grounded. In the circuit in Figure 14, the user is left with the option to ground or float the center tap. The DC voltage that will exist at either IOUTA or IOUTB if the center tap is floating is IOUTDC x (RA//RB) V because RDIFF is DC shorted by the transformer. If the center tap is grounded, the DC voltage is 0V. Recommended values for the circuit in Figure 14 are RA=RB=50Ω, RDIFF=100Ω, assuming R LOAD=50Ω. The performance of Figure 13 and Figure 14 is basically the same, however leaving the center tap of Figure 14 floating allows the circuit to find a more balanced virtual ground, theoretically improving the even order harmonic rejection, but likely reducing the signal swing available due to the output voltage compliance range limitations. ISL5961 Propagation Delay REQ = 0.5 x (RLOAD // RDIFF) AT EACH OUTPUT PIN 21 PIN 22 ISL5961 The converter requires two clock rising edges for data to be represented at the output. Each rising edge of the clock captures the present data word and outputs the previous data. The propagation delay is therefore 1/CLK, plus <2ns of processing. See Figure 15. VOUT = (2 x IOUTA x REQ)V 1:1 IOUTB RDIFF RLOAD IOUTA Test Service Intersil offers customer-specific testing of CommLink converters with a service called Testdrive. To submit a request, fill out the Testdrive form. The form can be found by doing an ‘entire site search’ at www.intersil.com on the words ‘DAC Testdrive’. Or, send a request to the technical support center. RLOAD REPRESENTS THE LOAD SEEN BY THE TRANSFORMER FIGURE 13. OUTPUT LOADING FOR DATASHEET MEASUREMENTS REQ = 0.5 x (RLOAD // R DIFF// RA), WHERE RA=RB AT EACH OUTPUT RA PIN 21 PIN 22 ISL5961 IOUTB VOUT = (2 x IOUTA x REQ)V RDIFF IOUTA RLOAD RB RLOAD REPRESENTS THE LOAD SEEN BY THE TRANSFORMER FIGURE 14. ALTERNATIVE OUTPUT LOADING Timing Diagram tPW1 tPW2 50% CLK tSU tSU tHLD D13-D0 W0 tSU tHLD tHLD W1 W2 W3 tPD tPD OUTPUT=W0 IOUT OUTPUT=W-1 OUTPUT=W1 FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 11 ISL5961 Small Outline Plastic Packages (SOIC) M28.3 (JEDEC MS-013-AE ISSUE C) N INDEX AREA 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE 0.25(0.010) M H B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 12 MILLIMETERS MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 0.05 BSC 10.00 h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 8o 0o 28 0o 10.65 - 0.394 N 0.419 1.27 BSC H α NOTES: MAX A1 e µα MIN 28 - 7 8o Rev. 0 12/93 ISL5961 Thin Shrink Small Outline Plastic Packages (TSSOP) M28.173 N INDEX AREA E 0.25(0.010) M E1 2 3 0.05(0.002) -A- INCHES GAUGE PLANE -B1 28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M SEATING PLANE L A D -C- α e A1 b 0.10(0.004) M 0.25 0.010 A2 C A M SYMBOL MIN MAX MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.378 0.386 9.60 9.80 3 E1 0.169 0.177 4.30 4.50 4 e c 0.10(0.004) B S 0.026 BSC E 0.246 L 0.0177 N NOTES: α 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AE, Issue E. MILLIMETERS 0.65 BSC 0.256 6.25 0.0295 0.45 28 0o - 0.75 6 28 8o 0o - 6.50 7 8o Rev. 0 6/98 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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