Application Note 800W 130kHz PFC Evaluation Board with 600V CoolMOS™ C7

PF C d e mo bo ard - s y stem s olu t io n
High power density 800 W 130 kHz platinum server design
Application Note
About this document
Scope and purpose
This document presents the design methodology and results of an 800 W 130 kHz platinum server Power
Factor Correction (PFC) Continuous Conduction Mode (CCM) Boost Converter, based on:

600 V CoolMOS™ C7 super junction MOSFET and 650 V CoolSiC™ Schottky diode Generation 5

2EDN7524F non isolated gate driver (EiceDRIVER™)

ICE3PCS01G PFC controller

XMC1300 microcontroller

ICE2QR4780Z flyback controller
Intended audience
This document is intended for design engineers who want to verify the performance of the latest 600 V
CoolMOS™ C7 MOSFET technology working at 130 kHz in a CCM PFC boost converter along with EiceDRIVER™
ICs and 650 V CoolSiC™ Schottky Diode Generation 5 using analog and digital control.
Table of contents
1
1.1
1.2
Introduction ................................................................................................................................... 4
Topology .............................................................................................................................................. 4
PFC modes of operation...................................................................................................................... 4
2
2.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.3
2.5
2.6
Power stage design ........................................................................................................................ 7
EMI filter ............................................................................................................................................... 7
Rectifier bridge .................................................................................................................................... 7
PFC choke ............................................................................................................................................ 8
Infineon semiconductors .................................................................................................................. 10
600 V CoolMOS™ C7 ..................................................................................................................... 10
Fast dual channel 5 A low side gate driver ................................................................................. 10
SiC G5 diode ................................................................................................................................ 11
Output capacitor ............................................................................................................................... 11
Heat sink design and cooling fan ...................................................................................................... 12
Application Note
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Introduction
2.7
2.7.1
2.7.2
Specification: input, output, efficiency, power factor ..................................................................... 12
Input requirements ..................................................................................................................... 12
Output requirements .................................................................................................................. 12
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
ICE3PCS01G PFC controller .......................................................................................................... 13
Soft start ............................................................................................................................................ 14
Switching frequency.......................................................................................................................... 14
Protection features ........................................................................................................................... 15
Open loop protection.................................................................................................................. 15
Peak current limit........................................................................................................................ 15
IC supply under voltage lock out ................................................................................................ 15
DC-link voltage monitor and enable function............................................................................ 15
4
4.1
4.2
4.2.1
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.4
XMC 1300 digital PFC control implementation ............................................................................. 17
Interface between the power stage and XMC1300 ........................................................................... 17
Control scheme ................................................................................................................................. 18
Current and voltage sensing ....................................................................................................... 19
Software design ................................................................................................................................. 20
Hardware and software abstraction layers ................................................................................ 20
Process timing ............................................................................................................................. 21
Setup of peripheral units ............................................................................................................ 21
Calculation of input current reference ....................................................................................... 23
Current control loop ................................................................................................................... 24
Current control parameter selection ......................................................................................... 25
Duty-ratio feedforward ............................................................................................................... 26
Voltage control loop.................................................................................................................... 27
Signaling and protection ............................................................................................................ 28
Process flow diagrams ................................................................................................................ 31
Firmware downloading and debugging ........................................................................................... 35
5
5.1
5.2
5.3
ICE2QR4780Z controllers for auxiliary converter.......................................................................... 36
Input and output requirements ........................................................................................................ 36
Flyback transformer .......................................................................................................................... 36
Switching frequency.......................................................................................................................... 37
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
Experimental results .................................................................................................................... 38
IC3PCS01G IC control ........................................................................................................................ 38
Efficiency at low and high line .................................................................................................... 38
Input current THD ....................................................................................................................... 39
Standby power consumption ..................................................................................................... 43
Efficiency versus semiconductor stress ..................................................................................... 44
Load steps ................................................................................................................................... 49
Protection .................................................................................................................................... 50
Conducted EMI measurements .................................................................................................. 50
Start-up behavior ........................................................................................................................ 51
XMC1300 digital control .................................................................................................................... 53
Power factor, efficiency and input current THD ........................................................................ 53
Input current THD ....................................................................................................................... 54
Load steps ................................................................................................................................... 57
Protections .................................................................................................................................. 58
Start up ........................................................................................................................................ 60
Performance at very light load with digital control ................................................................... 61
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Introduction
7
7.1
7.1.1
7.1.2
7.1.3
7.2
7.2.1
7.2.2
7.2.3
7.3
7.3.1
7.3.2
7.3.3
Demoboard .................................................................................................................................. 62
Power board ...................................................................................................................................... 62
Schematics .................................................................................................................................. 62
PCB layout ................................................................................................................................... 64
Bill of material ............................................................................................................................. 65
ICE3PCS01G daughter board ............................................................................................................ 68
Schematics .................................................................................................................................. 68
PCB layout ................................................................................................................................... 70
Bill of material ............................................................................................................................. 71
XMC1300 daughter board.................................................................................................................. 73
Schematics .................................................................................................................................. 73
PCB layout ................................................................................................................................... 73
Bill of material ............................................................................................................................. 75
8
Useful material and links.............................................................................................................. 77
9
References ................................................................................................................................... 78
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Introduction
1
Introduction
Power Factor Correction (PFC) shapes the input current of the power supply to be synchronized with the
mains voltage, in order to maximize the real power drawn from the mains. In a perfect PFC circuit, the input
current follows the input voltage just like a pure resistor, without any input current harmonics or phase
shift.
This document is intended to demonstrate the design and practical results of an 800 W 130 kHz Platinum
server PFC demoboard based on Infineon Technologies devices including power semiconductors, nonisolated gate drivers, analog and digital controllers for the PFC converter as well as a Flyback controller for
the auxiliary supply.
1.1
Topology
Although active PFC can be achieved by several topologies, the boost converter (Figure 1) is the most
popular topology used in server PFC applications, for the following reasons:

The line voltage varies from zero to some peak value typically 375 VPK; hence a step up converter is
needed to deliver a DC bus voltage of 380 VDC or more. For that reason, the buck converter is eliminated,
and the buck-boost converter has high switch voltage stress (Vin+Vo), therefore it is also not the popular
one.

The boost converter has the filter inductor on the input side, which provides a smooth continuous input
current waveform as opposed to the discontinuous input current of the buck or buck-boost topology.
The continuous input current is much easier to filter, which is a major advantage of this design as any
additional filtering needed on the converter input will increase the cost and reduce the power factor due
to capacitive loading of the line.
Figure 1
1.2
Structure and key waveforms of a boost converter
PFC modes of operation
The boost converter can operate in three modes: continuous conduction mode (CCM), discontinuous
conduction mode (DCM), and critical conduction mode (CrCM). Figure 2 shows modeled waveforms to
illustrate the inductor and input currents in the three operating modes, for exactly the same voltage and
power conditions.
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Introduction
By comparing DCM to the other modes, DCM operation seems simpler than CrCM, since it may operate in
constant frequency operation; however, DCM has the disadvantage that it has the highest peak current
when compared to CrCM and to CCM, without any performance advantage when compared to CrCM.
Figure 2
PFC Inductor and input line current waveforms in the three different operating modes
CrCM may be considered a special case of CCM, where the operation is controlled to remain at the boundary
between CCM and DCM. CrCM normally uses constant on-time control; the line voltage is changing across
the 60 Hz line cycle, the reset time for the boost inductor is varying, and the operating frequency also
change in order to maintain the boundary mode operation. CrCM requires the controller to sense the
inductor current zero crossing in order to trigger the start of the next switching cycle.
The inductor ripple current (or the peak current) in CrCM is twice the average value, which greatly increases
the MOSFET RMS currents and turn-off current compared with CCM. But since every switching cycle starts at
zero current, and usually with partial ZVS operation (depending on the input voltage), turn-on loss of the
MOSFET is usually greatly reduced. Also, since the boost rectifier diode turns off at zero current as well,
reverse recovery losses and noise in the boost diode are eliminated as well, another major advantage of
CrCM mode. (Note that achieving ZVS switching for CrCM actually requires carefully selecting the boost
diode so that it has a certain degree of Qrr related “softness” in order to drive the boost inductor current
negative to store the energy needed for ZVS switching). The high input ripple current and its impact on the
input EMI filter tends to eliminate CrCM mode for high power designs unless interleaved stages are used to
reduce the input HF current ripple. A high efficiency design can be realized that way, but at higher cost. That
discussion is beyond the scope of this application note.
The power stage equations and transfer functions for CrCM are similar to CCM. The main differences relate
to the current ripple profile and switching frequency, which affects RMS current and switching power losses
and filter design.
CCM operation requires a larger filter inductor than CrCM. While the main design concerns for a CrCM
inductor are low HF core loss, low HF winding loss, and a stable inductance value over the operating range
(the inductor is essentially part of the timing circuit), the CCM mode inductor takes a different approach. For
the CCM PFC, the full load inductor current ripple is typically designed to be 20-40% of the average input
current. This has several advantages:

Peak current is lower, and the RMS current factor with a trapezoidal waveform is reduced compared to a
triangular waveform, reducing all component conduction losses.

Turn-off losses are lower due to switch off at much lower maximum current.

The HF ripple current to be smoothed by the EMI filter is much lower in amplitude.
Conversely, CCM encounters turn-on losses in the MOSFET, which can be exacerbated by the boost rectifier
reverse recovery loss due to reverse recovery charge, Qrr. For this reason, ultra-fast recovery diodes or silicon
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Introduction
carbide (SiC) Schottky diodes with extremely low Qrr are needed for CCM mode operation.
In conclusion, we can say that for low power applications, the CrCM boost has advantages in power saving
and improving power density. This advantage may extend to medium power ranges, however at some
medium power level the low filtering ability and the high peak current starts to become significant
disadvantages. At this point the CCM boost becomes a better choice for high power applications.
Since this document is intended to support 800 W PFC applications, a CCM PFC boost converter has been
chosen in the application note with detailed design discussions and design examples for demonstration.
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Power stage design
2
Power stage design
2.1
EMI filter
The EMI filter is implemented as a two-stage filter, which provides sufficient attenuation for both differential
mode (DM) and common mode (CM) noise.
Figure 3
Two-stage filter structure
The two high current common mode chokes L_cm are based on high permeability toroid ferrite cores.
1. 2 x 26 Turns/ 2 x 4,76 mH
2. 2 x 28 Turns/ 2 x 5,7 mH
The relatively high number of turns causes a considerable amount of stray inductance, which ensures
sufficient DM attenuation.
2.2
Rectifier bridge
The bridge rectifier is designed for the worst case: maximum output power and minimum input voltage. To
calculate the input current, an efficiency of 94% (at Vin = 90 V) is applied.
Maximum RMS value of the input current:

800 
 =
=
= 9,46 
 0,94 ∙ 90 
Maximum RMS value of the diode current:
 =

= 4,73 
2
Equation 2-1
Equation 2-2
Maximum average value of the diode current:
Equation 2-3
√2
= 4,26 

Due to the calculated mean and effective current values, the rectifier type LVB2560 with very low forward
voltage drop was selected. This 800 V device has sufficient voltage reserve with Vin = 265 V. The smaller size
types GBU and KBU are only available for currents up to 10 A. For the following formula, rD was extracted
from the characteristic curve of the data sheet (TA = 100 °C).
 =
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Power stage design
Conduction losses of a rectifier diode:
 =  ∙  + ( )2 ∙  = 4,26 ∙ 0,5 + (4,73)2 ∙ 0,016Ω = 2,49 
Equation 2-4
Total losses of the rectifier:
 = 4 = 4 ∙ 2,49  = 9,96 
2.3
Equation 2-5
PFC choke
The PFC choke design is based on a toroidal high performance powder core.
Toroidal chokes have a large surface area and allow a good balance, minimizing core and winding losses,
and achieving a homogeneous heat distribution without hot spots. Hence, they are suitable for systems
which are targeting the highest power density with forced air cooling. Very small choke sizes are feasible.
Figure 4
Photograph of PFC choke
The core material chosen was Chang Sung Corporation’s (CSC) HIGH FLUX, which has an excellent DC bias
and good core loss behavior. The part number is CH270060. The outer diameter of the core is 27 mm.
The winding was implemented using enameled copper wire AWG 16 (1,25 mm diameter). The winding covers
approximately 1,5 layers, meaning that there is one layer on the outer diameter, while inside there is a
double layer structure. This arrangement allows a good copper fill factor, while still having good AC
characteristics, and is a preferred fill form factor for high power toroidal inductors.
There are 60 turns, taking advantage of the high allowable DC bias. The resulting small signal bias
inductance is 270 µH. The effective inductance with current bias is determined by the core material B-H
characteristics and illustrated as follows:
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Power stage design
L [µH]
300,00
250,00
200,00
150,00
100,00
50,00
0,00
0
Figure 5
2
4
6
8
10
14 I [A]
12
DC-Bias dependency of inductance
The effective inductance together with the switching frequency of 130 kHz, produce a relatively low current
ripple, which supports the whole system performance. The peak and RMS currents for the semiconductors
and filter components are minimized. The low ripple design achieves low core losses, which is important for
light load performance of the system.
Table 1
Choke losses @800 W/130 kHz (calculation results of magnetic design software tool)
Vin_ac [V]
Pcore [W]
Pwi [W]
Ptot [W]
90
1,2
4,5
5,7
115
1,5
2,9
4,4
230
1,5
0,9
2,4
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Power stage design
2.4
Infineon semiconductors
2.4.1
600 V CoolMOS™ C7
The 600 V CoolMOS™ C7 series of devices offers a ~50% reduction in turn-off losses compared to the
CoolMOS™ CP, offering a GaN-like level of performance in PFC, TTF and other hard-switching topologies. The
CoolMOS™ C7 delivers an area-specific on resistance (RDS(ON)*A) of just 1 Ω per mm2, extending Infineon’s
portfolio of products with lowest RDS(ON) per package to support customer efforts to further increase power
density.
The 600 V CoolMOS C7 series features ultra-low switching losses and targets high power SMPS applications
such as server, telecom, solar and industrial applications requiring high efficiency and a reduced Bill of
Materials (BoM) and low total cost of ownership (TCO).
Applications driven by efficiency and TCO, such as hyper-scale data centers and telecom base stations
benefit from the switching loss reduction offered by CoolMOS™ C7. Efficiency gains of 0.3% to 0.7% in PFC
and 0.1% in LLC topologies can be achieved, leading to significant TCO benefits. In the case of a 2.5 kW
server PSU, for example, using 600 V C7 MOSFETs can result in energy cost reductions of ~10% for PSU
energy loss.
In BoM and cost driven designs such as enterprise servers, the 600 V CoolMOS™ C7 devices offer a cost
reduction in magnetics. Due to the significantly lower gate charge and output capacitance, the C7 can be
operated at double the normal switching frequencies with only a marginal loss in efficiency. This allows the
size of magnetic components to be minimized, lowering the overall BoM cost. For example, doubling the
switching frequency from 65 kHz to 130 kHz may reduce the magnetic component cost by as much as 30%.
2.4.1.1
Design implementation
Based on the analysis of several current server PSUs and customer feedback, it is a common practice to
implement two MOSFETs in parallel in the classic PFC topology for improving thermal performance during
both normal and critical operating conditions like AC line drop out. As a result, this demo board is designed
to use and test two 180 m TO-220 MOSFETs working in parallel. This also has the advantage of lowering
the net source inductance, and helps avoid source inductance related increases in switching losses which
occur above 5 A in a single package, by splitting the current load at low line between two packages.
2.4.2
Fast dual channel 5 A low side gate driver
2.4.2.1
Introduction
The 2EDN7524 is a non-inverting fast dual-channel driver for low-side switches. Two true rail-to-rail output
stages with very low output impedance and high current capability are chosen to ensure highest flexibility
and cover a wide variety of applications.
All inputs are compatible with LVTTL signal levels. The threshold voltages (with a typical hysteresis of 1 V)
are kept constant over the supply voltage range.
Since the 2EDN7524 is particularly aimed at fast-switching applications, signal delays and rise/fall times
have been minimized. Special effort has been made toward minimizing delay differences between the 2
channels to very low values (typically 1 ns).
The 2EDN7524 driver used in this demo board comes in a standard PG-DSO-8 package.
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Power stage design
2.4.2.2
Driver outputs
The two rail-to-rail output stages realized with complementary MOS transistors are able to provide a typical
5 A of sourcing and sinking current. The on-resistance is very low with a typical value below 0.7 Ω for the
sourcing p-MOS and 0.5 Ω for the sinking n-MOS transistor. The use of a p-channel sourcing transistor is
crucial for achieving real rail-to-rail behavior and not suffering from the source follower’s voltage drop.
Gate drive outputs are held active low in case of floating inputs (ENx, Inx) or during startup or power down
once UVLO is not exceeded.
2.4.2.3
Under Voltage Lockout (UVLO)
The Under-Voltage Lockout (UVLO) function ensures that the output can be switched to its high level only if
the supply voltage exceeds the UVLO threshold voltage. Therefore it can be guaranteed that the switch
transistor is not operated if the driving voltage is too low to completely switch it on, so avoiding excessive
power dissipation.
The default UVLO level is set to a typical value of 4.2 V or 8 V (with some hysteresis). A UVLO of 4.2 V is
normally used for low voltage and TTL based MOSFETs. For higher level, like high voltage super junction
MOSFETS, a minimum active voltage of 8 V is used.
2.4.3
SiC G5 diode
Selection of the boost diode is a major design decision in a CCM boost converter, because the diode is hard
commutated at a high current, and the reverse recovery can cause significant power loss, as well as noise
and current spikes. Reverse recovery can be a bottleneck for high switching frequency and high power
density power supplies. Additionally, at low line, the available diode conduction duty cycle is quite low, and
the forward current quite high in proportion to the average current. For that reason, the first criteria for
selecting a diode in a CCM boost circuit are fast recovery with low reverse recovery charge, followed by Vf
operating capability at high forward current.
Since SiC Schottky diodes have a capacitive charge, Qc, rather than reverse recovery charge, Qrr their
switching loss and recovery time are much lower than a silicon ultrafast diode leading to an enhanced
performance. Moreover, SiC diodes allow higher switching frequency designs; hence, higher power density
converters are achieved. The capacitive charge for SiC diodes are not only low, but also independent of
di/dt, current level, and temperature; which is different from silicon diodes that have strong dependency on
these conditions.
The recommended diode for CCM boost applications is the 650 V thinQ!™ SiC Schottky Diode Generation 5,
which include Infineon’s leading edge technologies, such as diffusion soldering process and wafer thinning
technology. The result is a new family of products showing improved efficiency over all load conditions,
resulting from the improved thermal characteristics. Note that even with the high surge current capability
of SiC diode Schottky diode, it is still preferred to use a bulk pre-charge diode. This is a low frequency
standard diode with high I2t rating to support pre-charging the bulk capacitor to the peak of the AC line
voltage; this is a high initial surge current stress (which should be limited by a series NTC) that is best
avoided for the HF boost rectifier diode.
In this demoboard, a 6 A IDH06G65C5 diode is used.
2.5
Output capacitor
Possible over-voltages require the selection of a 450 V (low impedance) type capacitor. The minimum
capacitance is defined by the minimum hold up time and the minimum allowable DC-link voltage of the
system or the maximum allowable voltage from the 2x line frequency AC ripple current:
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Power stage design

thu = 10 ms

Vbmin = 320 V
 =
2 ∗  ∗ ℎ
= 381 µ
2
2 − 
Equation 2-6
The chosen type is a 470 µF RUBYCON 450 V XH470MEFCSN30X50 capacitor.
2.6
Heat sink design and cooling fan
Heat sinks for the rectifier and power semiconductors are made of a 1 mm copper plate.
Fan speed control operation depends on the board/heatsink temperature. There are two speed levels, the
fan operates with low speed at 57°C and increases to high speed above 79°C.
2.7
Specification: input, output, efficiency, power factor
2.7.1
Input requirements
Table 2
Input requirements
Parameter
Value
Input voltage range, Vin_range
90 VAC – 265 VAC
Nominal input voltage, Vin
230 VAC
AC line frequency range, fAC
47 – 64 Hz
Max peak input current, Iin_max
10 ARMS @ Vin = 90 VAC , Pout_max = 800 W , max load
Turn on input voltage, Vin_on
80 VAC – 87 VAC, ramping up
Turn off input voltage, Vin_off
75 VAC – 85 VAC, ramping down
Power factor , PF
Shall be greater than 0.95 from 20% rated load and above
Hold up time
10 ms after last AC zero point @ Pout_max = 800 W, Vout_min = 320 VDC
Total Harmonic Distortion, THD
<15% from 10% load @ high line, for class A equipment
2.7.2
Output requirements
Table 3
Output requirements
Parameter
Parameter
Nominal output voltage, Vout
380 VDC
Maximum output power, Pout
800 W
Peak output power, Pout_max
1 kW
Maximum output current, Iout_max
2,1 A
Output voltage ripple
Max 20 Vpk-pk @ Vout , Iout
Output OV threshold maximum
450 VDC
Output OV threshold minimum
420 VDC
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ICE3PCS01G PFC controller
3
ICE3PCS01G PFC controller
The ICE3PCS01G is a 14pin controller IC for power factor correction circuits. It is suitable for wide range line
input applications from 85 to 265 VAC with overall efficiency above 97%. The IC supports the converters in
boost topology and operates in continuous conduction mode (CCM) with average current control by
regulating Doff, without the need for input voltage sensing except for brown out detection.
IL
Boost Rectifi er
VDC Out
Boost
Inductor
IDC
CO
LOAD
Gate
VIN
D
LP Filter
-
+
+
Vref
E/ A
OSC
Toff Min
IL(av)
Figure 6
Simplified block diagram concept for PFC PWM modulator of the ICE3PCS0x series
The IC operates with a cascaded control; the inner current loop and the outer voltage loop. The inner
current loop of the IC controls the sinusoidal profile for the average input current. It uses the dependency of
the PWM duty cycle on the line input voltage to determine the corresponding input current. This means the
average input current follows the input voltage as long as the device operates in CCM. Under light load
conditions, depending on the choke inductance, the system may enter into discontinuous conduction mode
(DCM) resulting in higher harmonics but still meeting the Class D requirement of IEC 1000-3-2 (EN 61000-3-2).
The current sense amplifier filters and amplifies the ISENSE signal and provides a current loop bandwidth
control via the ICAP pin for external compensation capacitor.
The outer voltage loop of the IC regulates the output bulk voltage and is realized digitally within the IC,
using a delta-sigma converter operating at about 3.4 kHz to digitize the voltage feedback signal. Depending
on the load condition, the PID signal is converted to an appropriate low frequency voltage that controls the
amplitude of the current loop by means of a variable voltage ramp generated at the switching clock
frequency, which is also sent to the PWM comparator. The current charging the ramp generator is a function
of the error amplifier feedback level, plus some nonlinear block signal processing.
The digital PID has some unique features that give it some regulation advantages when compared with
conventional OTA amplifiers, while still realizing low harmonic distortion and high power factor.
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ICE3PCS01G PFC controller
PWM Generation
VSENSE
SD - ADC
2x Line
Notch Filter
PI Loop EA
Nonlinear
Gain Block
Ramp
Generator
Figure 7
Digital error amplifier system concept, with 2x line frequency notch filter
The self calibrating 2x line frequency notch filter greatly reduces the distortion effects from feedback of the
bulk capacitor ripple, while allowing somewhat higher gain, which translates to better load step transient
response.
The IC is equipped with various protection features to ensure safe operation for the system and the device.
3.1
Soft start
During power up when VOUT is less than 96% of the rated level, the internal voltage loop output increases
from the initial voltage under the soft-start control. This results in a controlled linear increase of the input
current from 0 A. This helps to reduce the current stress in power components.
Once VOUT has reached 96% of the rated level, the soft-start control is released to achieve good regulation
and dynamic response and the VB_OK pin is raised to 5 V indicating that the PFC output voltage is in the
normal range.
3.2
Switching frequency
The switching frequency of the PFC converter can be set with an external resistor R attached between the
FREQ pin and SGND. The voltage on the FREQ pin is typically 1 V. The corresponding capacitor for the
oscillator is integrated in the device and the R /frequency is given in Figure 8. The recommended operating
frequency range is from 21 kHz to 250 kHz. In the case of this demo board, a R of 33 kΩ at pin FREQ will set
a switching frequency f of around 134 kHz (typ).
FREQ
FREQ
FREQ
SW
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ICE3PCS01G PFC controller
Figure 8
Frequency setting in the ICE3PCS01G IC
3.3
Protection features
3.3.1
Open loop protection
Open loop protection is available for this IC to safe-guard the output and is implemented using a
comparator with a threshold of 0.5 V. Whenever the voltage at the VSENSE pin falls below 0.5 V, or equivalently
VOUT falls below 20% of its rated value, it indicates an open loop condition (i.e. VSENSE pin not connected). In
this case, most of the blocks within the IC will be shutdown. Normally the bulk pre-charge diode will charge
the bulk capacitance to a value higher than this, so this voltage range will occur
3.3.2
Peak current limit
The IC provides a cycle by cycle peak current limitation (PCL). It is active when the voltage at pin ISENSE
reaches -0.2 V. This voltage is amplified by a factor of -5 and connected to comparator with a reference
voltage of 1.0 V. A de-glitcher with 200 ns after the comparator improves noise immunity for the activation of
this protection. In other words, the current sense resistor should be designed to be lower than the -0.2 V PCL
for normal operation.
3.3.3
IC supply under voltage lock out
When the supply voltage VCC is below the under voltage lockout threshold VCC,UVLO, (typically 11 V), the IC is
turned off and the gate drive is pulled low internally to maintain the off state. The current consumption is
reduced to only 1.4 mA.
3.3.4
DC-link voltage monitor and enable function
The IC monitors the bulk voltage status through the VSENSE pin and outputs a TTL signal to enable the PWM IC
or control the inrush relay. During soft-start once the bulk voltage is higher than 95% of the rated value, pin
VB_OK is raised to a high level. The threshold to trigger the low level is determined by the externally
adjustable voltage on the VBTHL pin.
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When the VBTHL pin is pulled lower than 0.5 V, most functional blocks are turned off and the IC enters into
standby mode for low power consumption. When the disable signal is released the IC recovers via a softstart.
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4
XMC 1300 digital PFC control implementation
The XMC1300 is part of the XMCTM Microcontroller family from Infineon Technologies. This family of
microcontrollers based on ARM® Cortex®–M cores is designed for real time critical applications. The control
of power supplies is a strong focus for XMC Microcontrollers where users can benefit from features such as
analog comparators, high resolution PWM timers, co-processors or high precision analog to digital
converters.
The XMC1300 is based on an ARM® Cortex®-M0 core and this section describes how to use an XMC1300 to
implement a digital PFC controller. Some of XMC1300 features are listed here:

12 bit ADC, 1 MSample/sec. Flexible sequencing of conversions including synchronization

Clock frequency is 32 MHz, nevertheless, key peripherals can run at 64 MHz, like PWM timers or MATH CoProcessors, to accelerate calculations or improve PWM resolution.

Fast analog comparators for protections such as overcurrent protection.

Co-Processor that can run in parallel to the main core (Cortex-M0). In this particular case will help
executing faster divisions (17 clock cycles)

Flexible timing scheme due to CCU timers. These timers allow synchronization of PWM patterns and
accurate generation of ADC triggers.

Interconnection matrix to route different internal signals from one peripheral to another. As an example,
the timers can connect to an ADC to signify the exact point in time when a signal must be sampled, or a
comparator output can be connected to a PWM timer. This can be used to make sure that whenever the
comparator trips, the PWM stops.
Serial communication protocols are supported including UART, I2C, SPI. These are used for GUI or possible
communication with the secondary stage of a full power supply.
4.1
Interface between the power stage and XMC1300
The basic scheme of the system for digital PFC (DPFC) is depicted in Figure 9.
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Figure 9
System setup for DPFC
Red blocks mark the hardware units necessary to handle input and output signals. Blue boxes show
programmed software parts for the application. Grey boxes identify error conditions and their interactions.
4.2
Control scheme
The proposed control scheme is shown in Figure 10. Two interrupt driven processes are used for output
voltage and input current control, input voltage feed forward and current reference calculation. An
additional time-based interrupt, driven by the ‘SysTick’-timer, is used for state indication and data exchange
for the user interface. Details of this scheme are discussed in the following chapters.
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Figure 10
4.2.1
Control scheme for DPFC
Current and voltage sensing
The input measurements necessary for the proposed DPFC system are:
-
Input current
-
Output voltage
-
Input voltage
These signals are sensed using individual signal conditioning circuits to adapt their min-max-range to the
0…5 V-range of the A/D converter unit of the XMC1300 (VADC). According to the Q15 fixed point number
format in the XMC1300, the maximum positive analog measure corresponds to 1
(or 7FFFH) after A/D-conversion in the microcontroller. The following equation holds:
1 = K∙Mmax,
Equation 4-1
where K is the scaling factor for the analog measurements with its maximum value Mmax. Selection of the
min-max-ranges was done with respect to the input/ output requirements
(cf. Table 2 and Table 3) adding a safety margin.
The input current is sensed with a shunt resistor and fed to the A/D converter via a differential operational
amplifier. The circuitry was chosen such that Iin_max = 25.25 A corresponds to 5 V at the A/D converter input, to
account for the peak inductor current value plus a safety margin:
K IS =
1
25.25A
Equation 4-2
The input voltage is fed to the A/D converter via a high impedance differential amplifier. The circuitry was
chosen such that Vin_max = 466.7 V corresponds to 5 V at the A/D converter input, to take account of the
maximum output voltage plus a safety margin:
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K VinS =
1
466.7 V
Equation 4-3
The output voltage is fed to the A/D converter via a high impedance voltage divider. The circuitry was
chosen such that Vout_max = 565 V equals 5 V at the A/D converter input, to allow for the maximum output
voltage plus a safety margin:
K VoutS =
1
565 V
Equation 4-4
The A/D-converter of the XMC1300 is triggered by hardware signals synchronized with the PWM in order to
sense the average current and to avoid switching noise in all of the analog input signals (cf. Figure 12).
Maximum resolution is given with 12-bit-conversions. The synchronized sampling of the two available
Sample and Hold units (Group1, Group0) is possible, as shown in Table 4.
4.3
Software design
4.3.1
Hardware and software abstraction layers
Providing embedded software in a layer structure is a good approach for a clear and flexible overall
structure. Specific separate layers (according to the requirements and available software resources) ease
the testing, further development and maintenance of the complete software project. The following structure
was implemented in the DPFC project:
Figure 11
Software abstraction layers for DPFC
The ‘Peripheral Layer’ contains all hardware peripherals of the XMC1300 used in the DPFC project.
With the help of the ‘Low Level Drivers’ these units can be configured and adapted to the needs of the
application. The easier configuration process significantly reduces software developer time.
The ‘DAVE3 Application Layer’ was used to perform the clock configuration (CLK002-App) and to provide a
channel for debugging and online monitoring (DBG002-App) [3].
The ‘Application Layer’ contains all software parts directly connected to the control of the PFC-stage, as well
as the software functionality for the safety concept and the functionality to indicate the present state of the
PFC-stage.
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4.3.2
Process timing
Figure 12 below depicts the timing of the ADC-Triggers and the programmed software processes (Current
Control, Voltage Control, SysTick-timer) derived from the CCU4-Slice0-PWM-Signal. According to Figure 10,
period match events are set-up for the CCU4-Slice3 and CCU4-Slice1 interrupt routines. In this way a more
even distribution of the available calculation time is achieved.
Figure 12
4.3.3
Process timing for DPFC
Setup of peripheral units
In the following table an overview of the configured peripheral setup of the DPFC is given.
Table 4
Peripheral setup
Unit
Configuration
SCU
Application Note
-
MCLK = 32 MHz
PCLK = 64 MHz
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VADC
-
CCU4
-
-
3 channels used:
Iin (Channel6Group1),
Vout (Ch5G1),
Vin (Ch5G0)
12-bit results
Minimum sampling time
Mode: ‘Queue request source’
Usage of two sample and hold-units (groups)
Group1 (Master): Iin (sample point = PWM One match), Vout (sample point = PWM Periodmatch)
Group0 (Slave): Vin (sample point = PWM Period match, Slave of channel Vout)
Slice0: PWM (128 kHz), center aligned mode
Slice3: Current Control (32 kHz), period match → Interrupt
Slice1: Voltage Control (16 kHz), period match → Interrupt
“TRAP”-functionality of CCU4-Slice0 programmed active: reason for “TRAP”-state is
overcurrent of inductor current (sensed by programmed ACMP2) or overvoltage of
output voltage (sensed by programmed ACMP1)
“Cycle by cycle”- inductor current limit (sensed by programmed ACMP0)
MATH
-
Calculation of two divide operations:
(1) Duty-Ratio Feedforward (in current control loop):
DR_FF = 1 - Vin/ Vout
(2) Current reference (in current control loop):
Vac * PI_Voltage_out/ VinRMS2
ACMP
-
ACMP2: overcurrent (output = active low)
ACMP1: overvoltage (output = active low)
ACMP0: ”Cycle by cycle”- inductor current limit (output = active low)
USIC0
-
USIC0_CH1: UART for online monitoring
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Table 5
Peripheral setup (cont.)
Unit
Configuration
PORTS
4.3.4
-
P0.0 – digital IN: “TRAP”-input from ACMP1- and ACMP2-output
P0.2 – digital IN: (high = 5V OK)
P0.3 – digital IN: PTC IN (high = Temp OK)
P0.5 – digital OUT: PWM
P0.6 – digital OUT: UART TXD
P0.7 – digital IN: UART RXD
P0.10 – digital OUT: ACMP0 - “cycle by cycle”- inductor current limit
P0.12 – digital IN: “cycle by cycle”- inductor current limit input from ACMP0-output
P0.14 – SWD (DEBUG)
P0.15 – SWCLK (DEBUG)
-
P1.0 – digital OUT: ACMP1 – overvoltage of output voltage
P1.1 – digital OUT: LED “brown out”
P1.2 – digital OUT: ACMP2 – overcurrent of inductor current
P1.3 – digital OUT: LED “over temp”
P1.4 – digital OUT: LED “input voltage range”
P1.5 – digital OUT: inrush relay
-
P2.0 – analog IN: Vin
P2.1 – analog IN: ACMP2_P
P2.2 – analog IN: ACMP2_N
P2.3 – analog IN: Vout
P2.4 – analog IN: Iin
P2.6 – analog IN: ACMP1_N
P2.7 – analog IN: ACMP1_P
P2.8 – analog IN: ACMP0_N
P2.9 – analog IN: ACMP0_P
Calculation of input current reference
From Figure 9 and Figure 10, it is possible to obtain the equation for the input current reference:
Iin_ref =
Vin ∙ Voltage_Compensatorout
2
(Vin_RMS )
Equation 4-5
∙ Km
The purpose of each factor in the equation above is as follows:
The rectified input voltage Vin ensures the sinusoidal shape of the input current reference. The output of the
voltage compensator is proportional to the taken output power. With the term 1/ Vin_RMS2, the current
command is adapted to the present input voltage in order to maintain constant power.
The multiplier scaling factor Km depicted in Figure 10 can be obtained with help of the complete equation
calculated in the XMC1300:
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iin_ref ∙ KIS = (KVinS ∙vin ) ∙ vout_vc ∙
Km
Equation 4-6
2
(KVinS ∙ Vin_RMS )
The input current reference is at its maximum when the input voltage is at its minimum and the voltage
controller output is at its maximum, meaning maximum power must be delivered. For this case the previous
equation becomes:
1 = (KVinS ∙vin_min ) ∙ 1 ∙
Km
1
Equation 4-7a
Hence the scaling factor for the multiplier/ divider is
Km =
1
Equation 4-7b
(KVinS ∙vin_min )
4.3.5
Current control loop
The plant transfer function “duty cycle to input current” (GIP(s)) can be derived from the small signal model
of the current loop and is approximately in the high frequency range [1]:
GIP (s) =
Vout
sL
Equation 4-8
To account for digital control, this plant transfer function is discretized using a “Zero-Order-Hold” (ZOH(z)):
GIP (z) =
Vout ∙TS
Equation 4-9
L∙(z-1)
The transfer function of the digital PWM (DPWM) is unity, as the maximum output of the current controller is
one and the minimum output is zero:
GDPWM(z) = 1.
Equation 4-10
One cycle digital delay is modeled as:
GDelay(z) = z-1.
Equation 4-11
Input current feedback in the XMC1300 is given by the physical value (Iact) multiplied by the factor KIS.
A PI-controller of the following form is used:
GPI =
KP (z-N)
Equation 4-12
z-1
Hence, the overall open loop transfer function of the input current loop is:
GIOL = GPI (z) ∙ GDPWM (z) ∙ GDelay (z) ∙ GIP (z)∙KIS =
KP (z-N)
z-1
∙ z-1 ∙
Vout ∙TS
L∙(z-1)
∙ KIS
Equation 4-13
The complete structure of the input current control loop is depicted in Figure 13:
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Figure 13
Input current control loop
With the demand for a minimum phase margin of 45° at the selected 4 kHz zero crossing frequency, the
parameters Kp (gain factor) and N (zero) are determined to be:
Kp = 0.25
N = 0.875
The electrical parameters needed for the calculation are L = 270 µH, Ts = 31.25 µs, Vout = 380 V, KIS = 1/(25.25 A)
With these parameters the zero is located at 636 Hz:
Figure 14
4.3.6
Bode plot of the open loop transfer function of the input current loop
Current control parameter selection
The plant transfer function is affected by the inductance dependency on the input current as depicted in
Figure 5. Furthermore, depending on the input power and inductance the CCM or DCM modes of operation
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alternate. A current controller parameter selection procedure is implemented to ensure good performance
of the DPFC-stage throughout different operating conditions:
a) The present input voltage range is determined once after start-up:
(1) “Low-Line” (LL)-Range : VAC <= 150 V
(2) “High-Line” (HL)-Range: VAC > 150 V
b) A permanent selection between five different parameter sets is performed according to the required
input power after the selection of the input voltage range. This selection is made with regard to the
necessary hysteresis in order to avoid unwanted shifting between different parameter sets:
(1)
PIN <= 160 W
(2) 160 W < PIN <= 250 W
(3) 250 W < PIN <= 400 W
(4) 400 W < PIN <= 500 W
(5) 500 W < PIN <= 800 W
4.3.7
Duty-ratio feedforward
A duty-ratio feedforward (DR-FF) scheme is used to cover several aspects of performance improvement for
the DPFC: fundamental displacement power factor close to unity, low THD and low zero-crossing distortion
of the line current.
With the method of duty-ratio feedforward the current controller is relieved from compensating VIN entirely
which results in better current tracking of the needed current and hence in a smaller inductor current error
[4]. This measure is also intended to take account of unwanted side effects such as offset in current
measurement and deviating current waveform due to interactions with input filter elements.
The duty-ratio fed to the PWM-unit is the sum of the output of the current controller and the calculated DRFF-value according to the plant in continuous conduction mode. The factor KDR-FF is used to scale the impact
of this method according to discontinuous conduction mode operation, especially when the DPFC is driven
by high line input voltage, where the effects mentioned above may limit the performance of the current
control loop, as depicted below:
Figure 15
DR-FF used in the control structure
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4.3.8
Voltage control loop
Considering the equation 4-6 for the calculation of the current reference:
Km
iin_ref ∙ KIS = (KVinS ∙vin ) ∙ vout_vc ∙
2,
(KVinS ∙ Vin_RMS )
Equation 4-14
the factor KSum can be expressed as:
KSum =
iIn_ref
(vin ∙ vout_vc )
=
(KVinS ∙ Km )
2
(KIS ∙ (KVinS ∙Vin_RMS ) )
,
Equation 4-15
then with the help of the small signal model of the voltage loop [1], the equation for the current source gc
can be evaluated as:
gc = KSum ∙
V2in_RMS
Vout
=
Km
(KIS ∙KVinS ∙Vout )
With the assumption of a constant power load, the plant transfer function “control voltage to output
voltage” (GVP(s)), which is valid in the low frequency range, is expressed as:
GVP (s) =
gC
Equation 4-16
sC
Similar to the current loop, this plant transfer function is discretized using a “Zero-Order-Hold” in z-plane
(ZOH(z)):
GVP (z) =
gC ∙T
Equation 4-17
S
C∙(z-1)
The open loop output voltage transfer function with a PI-controller (same structure as the input current
controller), a digital delay, the plant and the output voltage feedback factor KVoutS, is defined as follows:
GVOL = GPI (z) ∙ GDelay (z) ∙ GVP (z) ∙ KVoutS =
KP (z-N)
z-1
∙ z-1 ∙
gC ∙T
S
C∙(z-1)
∙ KVoutS
Equation 4-18
The complete structure of the output voltage control loop is depicted in Figure 16:
Figure 16
Voltage control loop
The bandwidth of the voltage loop must be chosen such that the 100 Hz component of the input current
reference signal is not damped. Usually a value between 5 Hz and 10 Hz is selected.
With the demand for a minimum phase margin of 45° at the selected zero crossing frequency of 6 Hz, the
parameters Kp (gain factor) and N (zero) are determined to be:
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Kp = 0.0440
N = 0.9976
The electrical parameters needed for the calculation are C = 470 µF, Ts = 62.5 µs, Vout = 380 V, KVoutS = 1/565 V.
Figure 17
Bode plot of the open loop transfer function of the output voltage loop
4.3.9
Signaling and protection
4.3.9.1
Signaling
Three LEDs on the control board display operating conditions and errors:

An orange LED indicates the presence of Vin_range at the input (LED turns on if Vin> 90 V, LED turns off if Vin<
83 V.

A green LED indicates the presence of Vout at the output (LED turns on if Vout>359 V, LED turns off if
Vout<351 V.

A red LED indicates over-temperature protection.
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4.3.9.2
Protection
Several protection functions are implemented with help of the hardware resources and the software
configuration of the XMC1302 microcontroller:

The converter has Cycle-by-Cycle-limit protection (CbC-limit) for the inductor current that is
independent of the power factor correction control loops. This is a hardware-based protection achieved
by the usage of an internal analog comparator (ACMP) and will switch off the PWM signal for one cycle
when the inductor current exceeds 18.94 A.

The converter has an Over-Current Protection (OCP-Trap) for the inductor current that is set active when
the power factor correction control loops are set active. This is a hardware-based protection by usage of
an internal analog comparator (ACMP) and will switch off the PWM signal as long as the inductor current
exceeds 24.24 A.

The converter has an Over-Voltage Protection (OVP-Trap) for the DC-link voltage that is independent of
the power factor correction control loops. This is a hardware-based protection achieved by the usage of
an internal analog comparator (ACMP) and will latch the DPFC section off when the DC-link voltage
exceeds 440 V.

The converter is protected against over temperature conditions caused by loss of fan cooling or
excessive ambient temperature which could cause failures of internal parts. The converter shuts down
and latches when the temperature monitored on the heatsink exceeds 90°C.

The converter has brown out protection. The turn on input voltage is 95 VAC. The turn off input voltage is
80 VAC.

There is protection for the average input current, limiting the input current to 10 Arms. The DC-link voltage
will drop when this protection is active.

There is protection for the output power, limiting the output power to 850 W. The DC-link voltage will
drop when this protection is active.
4.3.9.3
Software states
The different states of the DPFC control which are handled in the XMC1300 are shown in Figure 18 and
further details can be found in Table 6.
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Figure 18
Software states of DPFC
Table 6
Description of software states
Name
Description / Action(s)
Init
Microcontroller initialization is 5 V = ok
active.
Until condition is true;
<100 ms
Start
Output voltage regulation
Output voltage ramp:
with a ramp-shaped reference Vout_Ref_Start = 127 V
value and inductor current
Vout_Ref_End = 380 V
regulation are active.
Output voltage ramp:
∆Vout / ∆t = 2.75 V / ms
Steady state
PFC is operating under
nominal conditions and the
green LED is fully on.
Vout_Ref = 380 V
IPFC_Ref = f(Pout, VinRMS)
PF_REF = 1
2-4 seconds after output
voltage ramp is finished
Brown out
Error State (ES)
Input RMS voltage is out of
range. PWM signal is switched
off and PFC is set inactive.
Vin_RMS < 80 V
As long as conditions is
present (surveillance in
SysTick-process)
RMS current
Error State (ES)
Inductor RMS current is out of Iin_RMS >= 10 A
range and limited by means of (with Vin_RMS < 87 V @
current controller reference
Pout=800 W)
limitation.
As long as condition is
present (surveillance in
current control loop)
Input power
Error State (ES)
Input power is out of range
and limited by means of
voltage controller output
limitation.
Pin >= 900 W
As long as condition is
present (surveillance in
voltage control loop)
Cycle-by-Cycle (CbC)Current
Inductor current is out of
range and limited by
comparator-switched-off
IL >= 18.94 A
Maximum one switching
period;
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Condition(s)
30
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Name
Error State (ES)
Description / Action(s)
PWM-signal.
Condition(s)
Duration/ Timing
reset by Hardware
Over current
Trap Error State (TES)
Inductor current is out of
range and limited by
comparator-switched-off
PWM-signal. This error is
latching type unless reset by
software.
IL >= 24.24 A
As long as conditions is
present (reset in SysTickprocess)
Over voltage
Trap Error State (TES)
Output voltage is out of range
and limited by comparator
switched-off PWM-signal. This
error is latching type and
orange LED is blinking.
Vout >= 440 V
No automatic reset. A
complete switch off /on
procedure of the board is
needed.
Over temp
Error State (ES)
Heatsink temperature is out of THS > 90°C
range and limited by
switched-off PWM-signal. This
error is latching type and red
LED is on.
4.3.10
No automatic reset. A
complete switch off/on
procedure of the board is
needed.
Process flow diagrams
The software flow after a particular software process is entered is shown in the following diagrams.
(1)
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Reading of Vin and IPFC is achieved by reading the appropriate A/D-converter result register.
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(2)
Reading of Vout is achieved by reading the appropriate A/D-converter result register.
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(3)
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4.4
Firmware downloading and debugging
The firmware implementation with all digital control features explained in the previous section was
downloaded and debugged using Infineon Technologies Debug Probe XMCTM Link.
XMCTM Link is an isolated debug probe for all XMC™ microcontrollers. The debug probe is based on SEGGER
J-Link debug firmware, which enables use with DAVE™ and all major third-party compiler/IDEs within the
wide ARM® ecosystem.
The main features are:

1 kV DC isolation

Debug protocols
o
JTAG
o
Infineon’s Single Pin Debug (SPD )
o
Serial Wire Debug (SWD)
o
Serial Wire Output (SWO)

Virtual COM port support

10-pin Cortex® debug connector

8-pin XMC™ MCU debug connector

2.5 V to 5.5 V target voltage operation
Please refer to Section 8 for further information about this debug probe.
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ICE2QR4780Z controllers for auxiliary converter
5
ICE2QR4780Z controllers for auxiliary converter
5.1
Input and output requirements
The voltages needed to supply the control circuitry and the fan is provided by the dedicated Flyback DC-DC
converter ICE2QR4780Z, which is assembled on the power board. The DC-link voltage supplies such
converter.
Table 7
Input / Output requirements
Parameter
Value
Input voltage range, Vin_range
125 VDC – 450 VDC
Nominal output voltage, Vaux_pri
12 VDC +/-10%
Nominal output voltage, Vaux_sec
12 VDC +/-10%
Maximum output power, Pout
6W
5.2
Flyback transformer
The transformer design is based on a gapped ferrite core EE 16/8/5 with a horizontal arranged bobbin. The
total air gap is 0,2 mm. The selected core material is TDK N87 or equivalent.
The turns ratio was chosen to be 184:15:15, resulting in 150 V (approximately) reflected primary transformer
voltage.
Figure 19
Winding arrangement
The secondary winding (S) has safety insulation from primary side, which is implemented using triple
insulated wire. The other windings are made of standard enameled wire. The high voltage primary winding
(P1) is split in to 4 layers.
Figure 20
Pin arrangement, top view
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ICE2QR4780Z controllers for auxiliary converter
5.3
Switching frequency
The ICE2QR4780Z is a Quasi-resonant PWM controller with integrated 800 V CoolMOS™. The switching
frequency depends on load power and input voltage and is between 40 kHz and 130 kHz.

Vin=100 VDC

CH1-Drain-Source voltage
CH2-Shuntvoltage (R3,9
Ohm)


Vin=400 VDC

CH1-Drain-Source voltage
CH2-Shuntvoltage (R3,9
Ohm)

Figure 21
Characteristics of auxiliary power supply
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Experimental results
6
Experimental results
6.1
IC3PCS01G IC control
6.1.1
Efficiency at low and high line
Efficiency measurements were carried out with a “WT3000” Yokogawa power meter. Losses of the EMI-filter
are included. The fan was supplied from an external voltage source.
Table 8
Input
90VAC
230VAC
Efficiency measurements
VIN
IIN
PIN
VOUT
IOUT
POUT

PF
IINTHD
90,13
0,983
88,04
380,77
0,214
81,55
92,63
0,993
6,76
90,13
1,880
169,06
380,76
0,420
159,87
94,57
0,998
5,10
90,13
2,828
254,49
380,80
0,636
242,01
95,10
0,998
4,74
90,13
3,763
338,66
380,80
0,847
322,33
95,18
0,999
4,58
90,13
4,661
419,55
380,80
1,048
398,94
95,09
0,999
4,70
90,13
5,643
507,92
380,79
1,266
482,11
94,92
0,999
4,67
90,13
6,558
590,33
380,81
1,468
558,89
94,68
0,999
4,69
90,13
7,527
677,60
380,80
1,679
639,35
94,35
0,999
4,63
90,13
8,519
766,84
380,80
1,893
720,57
93,97
0,999
4,81
90,14
9,520
857,00
380,80
2,105
801,45
93,52
0,999
4,78
230,12
0,428
85,88
380,74
0,213
81,26
94,62
0,872
15,64
230,12
0,756
166,00
380,74
0,420
159,94
96,35
0,955
13,12
230,12
1,108
249,19
380,78
0,635
241,79
97,03
0,978
9,21
230,12
1,452
330,54
380,80
0,846
321,96
97,40
0,989
3,25
230,12
1,816
414,64
380,79
1,062
404,56
97,57
0,992
2,43
230,12
2,157
493,49
380,80
1,266
482,05
97,68
0,994
2,74
230,12
2,499
572,06
380,80
1,468
558,98
97,71
0,995
2,81
230,12
2,852
653,58
380,81
1,678
638,96
97,76
0,996
2,73
230,12
3,212
736,48
380,81
1,891
720,18
97,79
0,996
2,77
230,12
3,569
818,56
380,82
2,103
800,56
97,80
0,997
2,79
Application Note
38
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
Analog control
99
98
Efficiency [%]
97
96
95
94
93
92
0
100
200
300
400
500
Output Power [W]
High Line 230VAC
Figure 22
6.1.2
600
700
800
900
Low Line 90VAC
High line and low line efficiency with 2x IPP60R180C7 @ fs = 130 kHz, Rgate_on = 39 , Rgate_off = 14 
Input current THD
The following results were measured with a“WT3000” Yokogawa power meter.
Figure 23
Operating conditions, norms and THD results with analog control - I
Application Note
39
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
Figure 24
THD versus order of harmonics with analog control - I
Application Note
40
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
Figure 25
Operating conditions, norms and THD results with analog control - II
Application Note
41
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
Figure 26
THD versus order of harmonics with analog control - II
Application Note
42
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
6.1.3
Standby power consumption
Measurements show the standby power consumption below 1 W.
Figure 27
Standby power consumption
Application Note
43
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
6.1.4
Efficiency versus semiconductor stress
During the design process, there is always a trade-off between achieving high efficiency and semiconductor
stress if the derating guidelines of the IPC 9592 standard are to be fulfilled. This stress depends on input
current, output voltage, stray inductances and switching speed (di/dt). Depending on the requirements of
the application, the designer can select the proper value of turn on and turn off gate resistors to achieve
certain efficiency at a certain stress on the MOSFET. The following figures show measurements of voltage
characteristics and efficiency with different turn-off gate resistors. The voltage overshoot seen is a function
of the di/dt in the circuit and the effective inductance of the commutation loop between the boost MOSFETs,
the boost diode and the bulk capacitor.
Table 9
Scope
Channel
Remark
CH 1 (yellow)
Drain source voltage
CH 4 (green)
Gate voltage
CH 2 (red)
Input current
Table 10
Power meter
Parameter
Power meter parameter
designation
Remark
VIN
Urms1
Input voltage
IIN
Irms1
Input current
PIN
P1
Input power
η
η1
Efficiency
PF
λ1
Power factor
ITHD
Ithd1
Input current distortion
VOUT
Urms2
Output voltage
IOUT
Irms2
Output current
POUT
P2
Output power
F5
Power losses PIN-POUT
Application Note
44
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
6.1.4.1
Voltage characteristics and efficiency with different turn-off gate resistors
Steady state switch off waveforms at VIN=90 VAC
Figure 28
Pout=800 W when Rgate_OFF=14 Ω, Scope traces (above), Power meter display (below)
Application Note
45
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
Steady state switch off waveforms at VIN = 90 VAC
Figure 29
Pout = 800 W when Rgate_OFF=39 Ω, Scope traces (above), power meter display (below)
Application Note
46
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
Steady state switch off waveforms at VIN =230 VAC
Figure 30
Pout=800 W when Rgate_OFF=14 Ω, Scope traces (above), Power meter display (below)
Application Note
47
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
Steady state switch off waveforms at VIN =230 VAC
Figure 31
Pout=800 W when Rgate_OFF=39 Ω, Scope traces (above), Power meter display (below)
Application Note
48
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
6.1.5
Load steps

Channel 1 (yellow): DC-link voltage

Channel 4 (green): load current
Figure 32
Load step: 0%  100 % at Vin=90 VAC
The figure above illustrates the response of the voltage control loop during a load step from no load to full
load.
Figure 33
Load step: 100%  0% at Vin=90 VAC
The figure above illustrates the response of the voltage control loop during a load step from full load to no
load. There is no significant voltage overshoot seen.
Application Note
49
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
6.1.6
Protection
Several protection functions are implemented on the demo-board.

The converter is protected against over temperature conditions caused by loss of fan cooling or
excessive ambient temperature that could cause failures of internal parts. The converter shuts down and
latches when the temperature monitored on the heatsink exceeds 90°C.

The power factor correction converter has an Over-Voltage Protection (OVP) circuit for the DC-link
voltage that is independent of the power factor correction control loop. This independent OVP circuit
will latch the PFC section off when the DC-link voltage exceeds 436 V.

The converter has a brown out protection. The turn on input voltage is 88 VAC. The turn off voltage is
72 VAC.

There is protection for the average input current, limiting the input current to 9,8 Arms.
The DC-link voltage will drop when this protection is active.
Attention:

Due to the transfer function of the boost converter, the over current limit only works if the DC-link
voltage is higher than the rectified input voltage!
To prevent the board from catastrophic failure, a solder mount type 15 A/250 VAC fuse protects the input
of the converter.
6.1.7
Conducted EMI measurements
EMI is a very important quality factor for a power supply. The EMI has to consider the whole SMPS and is
split into radiated and conducted EMI. For the evaluation PFC board it is most important to investigate on
the conducted EMI-behavior since it is the input stage of any SMPS above a certain power range.
Figure 34
Conductive EMI measurement (average measurement  red limit) of the board with resistive
load (800 W) and input voltage of 230 VAC
Application Note
50
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
6.1.8
Start-up behavior
6.1.8.1
Inrush current
The PFC converter provides circuitry to limit the turn-on inrush current on the first half cycle to 35 Apeak. The
NTC-Limiter is bypassed by relay when the PFC is running and input current is greater than 0,2 Arms.
Key to the following 2 figures

Channel 1 (yellow): DC-link voltage

Channel 2 (red):

Channel 4 (green): input current
Figure 35
switching voltage at inrush relay
Limited inrush current at Vin=230 VAC
Application Note
51
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
6.1.8.2
Start up
After turning-on the system, the auxiliary supply will provide a stable supply voltage of 12 V. If the
components are powered and the input voltage is higher than the brown out threshold, the PFC begins to
start operation. This timing is different for the low-line and the high-line situations. For further information,
please refer to Infineon Technologies AN-PS0052 “Design Guide for Boost Type CCM PFC with ICE3PCS0xG”
Ch. 2.14)
Key to the following two figures

Channel 1 (yellow): DC-link voltage

Channel 2 (red):
switching voltage at inrush relay

Channel 3 (blue):
12 V supply

Channel 4 (green): input current
Figure 36
Start-up at Vin=230 VAC
Figure 37
Start-up at Vin=90 VAC
Application Note
52
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
6.2
XMC1300 digital control
6.2.1
Power factor, efficiency and input current THD
Efficiency measurements were carried out with a “WT3000” Yokogawa power meter. Losses from the EMIfilter are included. The fan was supplied from an external voltage source.
The PFC stage was fed from a regulated AC-source. Depending on the input voltage of 230 V or 90 V and
input power, different sets of current loop control parameters were used.
Table 11
Input
90VAC
230VAC
Efficiency measurements
VIN
90,13
90,13
90,13
90,13
90,14
90,13
90,14
90,14
90,14
90,14
230,13
230,12
230,12
230,12
230,12
230,12
230,12
230,12
230,12
230,12
Application Note
IIN
1,181
1,875
2,815
3,747
4,712
5,622
6,617
7,581
8,567
9,560
0,455
0,748
1,104
1,452
1,819
2,156
2,513
2,866
3,224
3,579
PIN
86,26
167,78
252,73
336,79
423,82
506,01
593,45
680,71
769,86
859,56
85,46
164,31
247,52
328,87
412,98
491,22
573,90
655,83
738,43
820,50
VOUT
379,71
379,58
379,57
379,58
379,59
379,60
379,62
379,63
379,63
379,66
379,44
379,41
379,43
379,43
379,43
379,43
379,43
379,44
379,42
379,43
IOUT
0,212
0,418
0,633
0,844
1,061
1,265
1,479
1,690
1,904
2,116
0,212
0,417
0,633
0,844
1,061
1,264
1,478
1,690
1,903
2,115
53
POUT
80,32
158,60
240,20
320,38
402,71
479,97
561,29
641,63
722,71
803,12
80,48
158,38
240,21
320,26
402,73
479,66
560,63
641,02
721,94
802,30

93,11
94,53
95,04
95,13
95,02
94,85
94,58
94,26
93,88
93,43
94,17
96,39
97,05
97,38
97,52
97,65
97,69
97,74
97,77
97,78
PF
0,810
0,993
0,996
0,997
0,998
0,999
0,995
0,996
0,997
0,998
0,816
0,954
0,974
0,984
0,986
0,990
0,993
0,994
0,995
0,996
IINTHD
7,01
6,65
5,00
4,10
3,53
3,15
5,10
4,54
4,11
3,79
6,65
10,48
9,97
7,07
5,78
5,22
4,49
3,91
3,45
3,10
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
Digital Control
99
98
Efficiency [%]
97
96
95
94
93
92
0
Figure 38
6.2.2
100
200
300
400
500
600
Output power [W]
High Line 230VAC
Low Line 90VAC
700
800
900
High line and low line efficiency with 2x IPP60R180C7 @ fs = 130 kHz, Rgate_on = 39 , Rgate_off = 14
.
Input current THD
The following results were measured with a“WT3000” Yokogawa power meter.
Figure 39
Operating conditions, norms and THD results with digital control - I
Application Note
54
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
Figure 40
THD versus order of harmonics with digital control - I
Application Note
55
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
Figure 41
Operating conditions, norms and THD results with digital control - II
Application Note
56
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
Figure 42
6.2.3
THD versus order of harmonics with digital control - II
Load steps
Key to the following two figures:

Channel 1 (yellow):
output current (2 A/ div)

Channel 2 (red):
output voltage (100 V/ div)
Application Note
57
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
Figure 43
Load step: 0% 100% at Vin=90 VAC
Figure 44
Load step :100% 0% at Vin= 90 VAC
The behavior of the output voltage on abrupt load changes is shown in Figures 43 and 44.
It can be seen that the voltage control ensures an undershoot of about 50 V and a settling time of 40 ms back
to the nominal output voltage in case of the 0% to 100% step load full load is present as shown in Figure 43.
In case of the 100% to 0% load jump the voltage overshot is kept in the range of 20 V to 40 V as can be seen
in Figure 44.
6.2.4
Protections
Two analog comparators of the XMC1300 are used to detect input overcurrent (ACMP2) and output
overvoltage (ACMP1):
Application Note
58
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
IinTRAP
= 24.24 A
VoutTRAP = 440 V
Key to the following figure:

Channel 1 (yellow):
Input current (20 A/ div)

Channel 2 (red):
Output voltage (100 V/ div)
Figure 45
Input overcurrent detection by ACMP2 of XMC1300
As soon as the control detects that the input current reaches the threshold of 24.24 A, the power factor
correction converter switches off the PWM signal to the MOSFETs. As a consequence the bulk voltage
decreases to the level of the peak value of the input voltage. In other words, the overcurrent protection
latches the converter operation.
Application Note
59
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
6.2.5
Start up
Key to the following figures:

Channel 1 (yellow):
Input current (20 A/ div)

Channel 2 (red):
Output voltage (100 V/ div)
Figure 46
Start-up at Vin=90 VAC
Figure 47
Start-up at Vin=230 VAC
The software state “Start” is entered after initialization of the microcontroller. A ramp with a final value of
Vout_REF = 380 V is set as output voltage reference and boost operation starts from the rectified input voltages
127 V (90 VAC) or 325 V (230 VAC), respectively.
Application Note
60
Revision 3.24, April 2016
PFC demoboard – system solution
Experimental results
6.2.6
Performance at very light load with digital control
During the experimental results it was observed that the input current of the Power Factor Correction
converter suffers considerable instability and has a non-sinusoidal periodic waveform for loads lower than
or equal to 10% of the rated power at both low and high line input voltages. This gives inconsistent
measurements of Power Factor and Total Harmonic Distortion.
For some real server PSU applications the requirement is that at 10% of the load the Power Factor must be
higher than 0.9 with a total harmonic distortion lower than 10%. Unfortunately, with the current digital
control implementation, such reliable performance is not met.
Infineon Technologies fully understands how important the value proposition of full digital control of a
Power Factor Correction Boost Converter is in terms of improved performance when compared to an analog
controlled PFC boost converter. As a result, we are currently working on a reliable solution in order to
convince the server PSU designer to implement the control with our XMC 1300 microcontrollers.
Please contact one of our Infineon Technologies field application engineer for the updated firmware.
Application Note
61
Revision 3.24, April 2016
PFC demoboard – system solution
Demoboard
7
Figure 48
Demoboard
800 W PFC board
7.1
Power board
7.1.1
Schematics
Figure 49
Schematic of power stage
Application Note
62
Revision 3.24, April 2016
PFC demoboard – system solution
Demoboard
Figure 50
Schematic of fan control
Figure 51
Schematic of auxiliary supply
Application Note
63
Revision 3.24, April 2016
PFC demoboard – system solution
Demoboard
7.1.2
PCB layout
Figure 52
View of PCB top layer
Figure 53
View of PCB inner 1 layer
Application Note
64
Revision 3.24, April 2016
PFC demoboard – system solution
Demoboard
Figure 54
View of PCB Inner 2 layer
Figure 55
View of PCB bottom layer
7.1.3
Bill of material
Table 12
BOM of power board
Quantity
Comment
Description
1
220nF/275 V
220nF 275 V X2
1
5657-PFC-CNT
Application Note
Footprint
C26
5657-CNT_Con2
65
Designator
X7
Revision 3.24, April 2016
PFC demoboard – system solution
Demoboard
1
Fuse 15 A/medium
15 A Fuse
1
B57237S0100M000
NTC Inrush 10R
3300K 3,7 A
17mW/K
B57237-Sxxx
R19
1
PTC80°C/100R
B59901D0080A040
PTC
B59901-Mxxx
R30
1
1,0µF
1,0µF 25V X7R
10% -55/125°C
CAPC2012M
C19
1
100pF
100pF 50V C0G
5% -55/125°C
CAPC2012M
C20
1
220pF
220pF 50V C0G
5% -55/125°C
CAPC2012M
C25
1
1,5nF
1,5nF 50V X7R
10% -55/125°C
CAPC2012M
C21
5
100nF
100nF 50V X7R 5%
-55/125°C
CAPC2012M
C1, C3, C4, C5, C24
1
4,7µF
4,7µF 25V X7R
10%
CAPC3216m
C18
2
100nF
100nF 450V X7T
10% -55/125°C
CAPC3216M
C12, C14
1
1,0nF
1,0nF 630V C0G
5%
CAPC3216M
C6
1
100nF/630 V
100nF 630V X7R
10% -55/85°C
CAPC4520M
C2
1
470µF/450 V
120µF 450V 105°C
CAPPA10-30x50R
C13
1
22µF/25 V
22µF 25 V
CAPPR2.5-6.3x11
C22
2
220µF/25 V
220µF 25 V
CAPPR5-8.7x12
C11, C23
4
2,2nF/300 V/Y2
CAPR7.5-9X4
C7, C8, C15, C16
1
2,2µF/305 V
2,2µF 305 V X2
CAPR22.511X26X20
C10
1
470nF/275 V
470nF 275V X2
CAPR22.511X26X20
C9
1
ICE2QR4780Z
PWM Controller
Current Mode QR
DIP-8_-6
IC3
1
GMSTB 2,5/2-G7,62
Phoenix
GMSTBA2,5/2-G7,62
X4
1
5657_EE16
EF16 Bias supply
Hartu_E16-8-P2P3
T1
1
2x5,7mH/10 A
5657 Common
mode choke
IFX_L2875053801(L3)
L3
1
2x4,7mH/10 A
5657 Common
mode choke
IFX_L2875070500(L2)
L2
3
KK6410_02 Plug
connector 2-pins
Molex
KK6410_2
X8, X10, X11
Application Note
66
F1
Revision 3.24, April 2016
PFC demoboard – system solution
Demoboard
1
5657-KK_GL
Heatsink
KK_GL
KK1
1
5657-KK_TO220
Heatsink
KK_TO220
KK2
1
L-934GD
LED low current
green
LED_5MM
D13
1
200µH/20 A
5657 PFC Choke
PFC_CHOKE-SK
L1
1
LVB2560
Diode bridge 600
V 25 A
REC-GSIB-5S
D4
1
47R
RESC2012M
R37
3
100R
RESC2012M
R6, R11, R26
2
1K0
RESC2012M
R38, R39
1
2K2
RESC2012M
R34
1
4K7
RESC2012M
R15
1
5K6
RESC2012M
R14
1
6K2
RESC2012M
R36
8
10K
RESC2012M
R1, R2, R3, R4, R5,
R9, R27, R28
2
24K
RESC2012M
R13, R35
1
47K
RESC2012M
R7
1
B57421V2103J062
RESC2012N
R12
2
22R
RESC3216M
R22, R23
2
39R
RESC3216M
R24, R25
3
220K
RESC3216M
R16, R17, R18
2
0R022
RESC6332M
R21, R29
1
3R9
RESMELF3614M
R33
1
33R
RESMELF3614M
R32
2
33R
RESMELF5822M
R8, R10
1
270K
RESMELF5822M
R31
1
OJE-SS112HM,000
Relay SPST-NO
RLY_TE-OJE
K1
1
S20K275
Varistor 275 V 1 W
S20K275
RV1
2
SMAJ15
Diode supressor
SMA_M
D8, D12
2
10MQ100N
Diode schottky
SMA_M
D11, D15
3
S1M
Rectifier diode
SMA_M
D5, D6, D7
1
US1M
Diode ultra fast
1000 V
SMA_M
D17
1
S5K
Rectifier diode
SMC_M
D2
4
PMEG3020H
Diode Schottky 30
V2A
SOD123M
D1, D9, D10, D14
1
LM293AD
Comparator
SOIC127P600-8M
IC1
1
2EDN7524IF
Low side dual
SOIC127P600-8M
IC2
Application Note
NTC 10K 4000K
0R022 2512
RESC6330 TK75
67
Revision 3.24, April 2016
PFC demoboard – system solution
Demoboard
MOSFET driver,
non-inverting
1
BC846B
NPN transistor
SOT23-3M
Q5
1
BZX84/B11 2%
Diode Zener
SOT23-3M
D16
2
SI2308BDS-T1GE3
MOSFET NChannel
SOT23-3M
Q1, Q2
2
IPP65R180C7
MOSFET NChannel
TO220-AB_HV
Q3, Q4
1
IDH06G65C5
Diode Schottky
650 V
TO220-AC
D3
7.2
ICE3PCS01G daughter board
7.2.1
Schematics
Figure 56
Schematic of connector
Application Note
68
Revision 3.24, April 2016
PFC demoboard – system solution
Demoboard
Figure 57
Schematic of PFC control
Figure 58
Schematic of temperature monitoring and inrush relay control
Application Note
69
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PFC demoboard – system solution
Demoboard
7.2.2
PCB layout
Figure 59
View of analog control PCB top layer
Figure 60
View of analog control PCB inner 1 layer
Figure 61
View of Analog Control PCB Inner 2 layer
Figure 62
View of Analog Control PCB Bottom layer
Application Note
70
Revision 3.24, April 2016
PFC demoboard – system solution
Demoboard
7.2.3
Bill of material
Table 13
BOM of control board
Quantity
Comment
Description
Footprint
Designator
3
1,0 µF
1,0 µF 25 V X7R 10%
-55/125°C
CAPC2012N
C12, C14, C19
1
1,0 nF
1,0 nF 50 V C0G 5% 55/125°C
CAPC2012N
C3
2
3,3 nF
3,3 nF 50V X7R 10% 55/125°C
CAPC2012N
C5, C7
3
10 nF
10 nF 50 V X7R 5% 55/125°C
CAPC2012N
C10, C11, C13
9
100 nF
100 nF 50 V X7R 5% 55/125°C
CAPC2012N
C1, C2, C4, C8,
C15, C16, C17,
C18, C20
3
4,7 µF
4,7µF 25 V X7R 10%
CAPC3216N
C6, C9, C21
1
LSA676-P2S1-1-Z
LED hyper bright
super-red
LED_LxA670
D8
1
LGA676-P1Q2-24Z
LED hyper bright
green
LED_LxA670
D4
1
LYA676-Q2T1-26Z
LED low current
yellow
LED_LxA670
D5
1
68R
RESC2012N
R19
2
470R
RESC2012N
R35, R43
2
1K0
RESC2012N
R57, R59
6
3K3
RESC2012N
R7, R16, R22,
R24, R48, R51
1
4K7
RESC2012N
R25
7
10K
RESC2012N
R27, R37, R39,
R52, R53, R56,
R61
4
20K
RESC2012N
R20, R32, R33,
R47
1
24K
RESC2012N
R36
4
33K
RESC2012N
R2, R17, R26, R34
8
47K
RESC2012N
R38, R40, R41,
R42, R44, R49,
R50, R55
3
100K
RESC2012N
R31, R45, R46
2
330K
RESC2012N
R23, R28
1
390K
RESC2012N
R29
2
470K
RESC2012N
R1, R21
4
820K
RESC2012N
R30, R54, R58,
Application Note
71
Revision 3.24, April 2016
PFC demoboard – system solution
Demoboard
R60
6
1M0
RESC3216N
R5, R6, R10, R11,
R14, R15
3
2M0
RESMELF3614N
R4, R8, R9
1
SAM-MMT-10501-X-SH-2-4
SAM-MMT-105-01X-SH-2-3
X1
1
SAM-MMT-11001-X-SH
SAM-MMT-110-01X-SH
X2
3
BAT165
Diode Schottky
SOD323
D3, D9, D10
4
1N4448WS-7-F
Diode fast switching
SOD323
D1, D2, D6, D7
1
LM293AD
Comparator
SOIC127P600-8N
IC4
1
TLC274AID
Operational
amplifier
SOIC127P600-14N
IC3
1
ICE3PCS01G
PFC controller
continuous
conduction mode
SOIC127P600-14N
IC2
1
BC857
pnp transistor
SOT23-3N
Q5
4
BCR148
npn transistor
SOT23-3N
Q1, Q2, Q3, Q4
1
BZX84/C24
Diode Zener
SOT23-3N
D11
1
MIC1557YM5
Timer
SOT23-5N
IC1
Application Note
72
Revision 3.24, April 2016
PFC demoboard – system solution
Demoboard
7.3
XMC1300 daughter board
7.3.1
Schematics
Figure 63
7.3.2
Schematic of DPFC control
PCB layout
Figure 64
View of DPFC-PCB top layer
Figure 65
View of DPFC-PCB inner 1 layer
Application Note
73
Revision 3.24, April 2016
PFC demoboard – system solution
Demoboard
Figure 66
View of DPFC-PCB inner 2 layer
Figure 67
View of DPFC-PCB bottom layer
Application Note
74
Revision 3.24, April 2016
PFC demoboard – system solution
Demoboard
7.3.3
Bill of material
Table 14
BOM of DPFC control board
Quantity
Comment
Description
Footprint
Designator
2
1,0 µF
CAPC1608N
C16, C17
2
10 nF
CAPC1608N
C13, C15
5
100 nF
CAPC1608N
C4, C5, C8, C18, C19
2
100 pF
CAPC1608N
C14, C20
4
1,0 nF
CAPC1608N
C7, C10, C11, C12
2
220 pF
CAPC1608N
C6, C9
1
4,7 nF
CAPC1608N
C21
1
4,7 µF
1,0 µF 16 V X7R 10% 55/125°C
10 nF 50 V X7R 10% 55/125°C
100 nF 50 V X7R 10% 55/125°C
100 pF 50 V C0G 5% 55/125°C
1,0 nF 50V C0G 5% 55/125°C
220 pF 50 V X7R 10% 55/125°C
4,7 nF 50 V X7R 10% 55/125°C
4,7µF 25 V X7R 10%
CAPC3216N
C3
2
1
47 µF/10 V
BLM21PG331SN1D
CAPMP4726X20N
INDP2012N
C1, C2
L1
1
LSA676-P2S1-1-Z
LED_LxA670
D1
1
LGA676-P1Q2-24-Z
LED_LxA670
D5
1
LYA676-Q2T1-26-Z
47 µF 10 V 125°C
Ferrite bead 330Ohm,
1,5AA
LED Hyper Bright
super-red
LED Hyper Bright
green
LED Low Current
yellow
LED_LxA670
D4
5
100 R
RESC1608N
R3, R12, R23, R24, R25
2
5
2
3
1
1
2
2
1
1
1
1
9
150 R
1K0
2K7
10K
12K
15K
18K
47K
100K
30K
0R0
240K
560K
RESC1608N
RESC1608N
RESC1608N
RESC1608N
RESC1608N
RESC1608N
RESC1608N
RESC1608N
RESC1608N
RESC1608N
RESC1608N
RESC1608N
RESC3216N
1
1
27R
SAM-MMT-105-01-FSH-2-4
RESMELF5822N
SAM-MMT-105-01-X-SH-2-3
R2, R19
R5, R13, R18, R20, R21
R17, R22
R4, R6, R36
R11
R31
R35, R41
R15, R16
R42
R40
R26
R8
R28, R29, R30, R32, R33,
R34, R37, R38, R39
R1
X1
1
SAM-MMT-110-01-FSH
SAM-MMT-110-01-X-SH
X2
Application Note
pin-header 2 mm 5poles SMT Pin 2 and 4
removed
pin-header 2mm 10
poles SMT
75
Revision 3.24, April 2016
PFC demoboard – system solution
Demoboard
1
X3
operational amplifier
voltage regulator
SAM-TSM-104-01-X-DHARevers
SOIC127P600-8N
SOIC127P600-8N
microcontroller
SOP50P640-38N
IC4
1
XMC1302-T038X0200
B-Step
BCR503
npn transistor digital
SOT23-3N
Q2
2
BAT54AW
Schottky diode
SOT323N
D2, D3
1
1
1
SAM-TSM-104-01-LDH-A
MCP6022-E/SN
IFX4949
pin-header 2x4 SMT
Application Note
76
IC3
IC1
Revision 3.24, April 2016
PFC demoboard – system solution
Useful material and links
8

Useful material and links
600 V CoolMOS™ C7 webpage
www.infineon.com/600V-C7

Product brief 600 V CoolMOS™ C7
http://www.infineon.com/dgdl/Infineon-Product_Brief_600V_CoolMOS_C7-PB-v01_00EN.pdf?fileId=5546d4624cb7f111014d664a241c4aa1

650 V CoolSiC™ Schottky Diode Generation 5 webpage
http://www.infineon.com/sic-gen5

Product brief 650 V CoolSiC™ Schottky Diode Generation 5
http://www.infineon.com/dgdl/Infineon+-+Product+Brief+-+Silicon+Carbide+-+Schottky+Diodes++650V+thinQ%21+Generation+5.pdf?fileId=db3a3043399628450139b06e16a721d0

2EDN7524F Non Isolated Gate Driver (EiceDRIVER™)
www.infineon.com/2EDN

Product Brief 2EDN7524F Non Isolated Gate Driver (EiceDRIVER™)
http://www.infineon.com/dgdl/Infineon-Product+Brief+2EDN+MOSFET+EiceDRIVER+Family-PB-v01_00EN.pdf?fileId=5546d4624cb7f111014d668a5a004c12

ICE3PCS01G PFC Controller webpage
http://www.infineon.com/cms/en/product/channel.html?channel=ff80808112ab681d0112ab6a716f0504

XMC 1300 microcontroller webpage
http://www.infineon.com/cms/en/product/evaluationboards/KIT_XMC13_BOOT_001/productType.html?productType=db3a30443ba77cfd013baec9c4b30ca8

ICE2QR4780Z Flyback Controller product webpage
http://www.infineon.com/cms/en/product/power/supply-voltage-regulator/ac-dc-integrated-powerstage-coolset-tm/quasi-resonant-coolsettm/ICE2QR4780Z/productType.html?productType=db3a30432a7fedfc012ab2458b0c36ff

KIT_XMC_LINK_SEGGER_V1 Isolated Debug Probe webpage
http://www.infineon.com/cms/en/product/productType.html?productType=5546d462501ee6fd015023a
eb65733b3#ispnTab1
Application Note
77
Revision 3.24, April 2016
PFC demoboard – system solution
References
9
References
[1]
Huliehel, F.A.; Lee, F.C.; Cho, B.H., "Small-signal modeling of the single-phase boost high power
factor converter with constant frequency control," Power Electronics Specialists Conference, 1992.
PESC '92 Record., 23rd Annual IEEE , vol., no., pp.475,482 vol.1, 29 Jun-3 Jul 1992
[2]
M. Xie, “Digital Control for Power Factor Correction”, Virginia Polytechnic Institute and State
University, 2003
[3]
XMC™ APPs and XMC™ Lib, from Infineon Homepage > Microcontroller > Development Tools,
Software and Kits > DAVE™ – Free Development Platform for Code Generation > All new 2015 DAVE™
– Beta-Version 4:
http://www.infineon.com/cms/de/product/microcontroller/development-tools-software-andkits/dave-tm-%E2%80%93-free-development-platform-for-code-generation/dave-tm-version4/channel.html?channel=5546d46149b40f65014a0a403bfb0922
[4]
Van de Sype, David M.; De Gusseme, K.; Van den Bossche, A.P.M.; Melkebeek, J.A., "Duty-ratio
feedforward for digitally controlled boost PFC converters," in Industrial Electronics, IEEE Transactions
on , vol.52, no.1, pp.108-115, Feb. 2005
Application Note
78
Revision 3.24, April 2016
PFC demoboard – system solution
References
Revision history
Major changes since the last revision
Page or reference
--
Application Note
Description of change
First release
79
Revision 3.24, April 2016
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolGaN™, CoolMOS™, CoolSET™, CoolSiC™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, DrBLADE™,
EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, IsoPACK™, iWafer™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OPTIGA™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™,
PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, ReverSave™, SatRIC™, SIEGET™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, SPOC™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
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Limited, UK. ANSI™ of American National Standards Institute. AUTOSAR™ of AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CATiq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of
Microsoft Corporation. HYPERTERMINAL™ of Hilgraeve Incorporated. MCS™ of Intel Corp. IEC™ of Commission Electrotechnique Internationale. IrDA™ of
Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim
Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA.
muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc.
Openwave™ of Openwave Systems Inc. RED HAT™ of Red Hat, Inc. RFMD™ of RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun
Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc.
TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design
Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2014-07-17
www.infineon.com
Edition 2015-05-18
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG.
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