6ED003L06-F Gate Drive IC for three phase converters - Technical Description

A p pl i c at i o n N o t e, V 1 . 1 , F e b . 20 0 7
6ED003L06-F
Gate Drive IC for three
phase conver ters Technical Description
AN-GateDriver-6ED003L06-1
Author: Wolfgang Frank
http://www.infineon.com/gatedriver
Power Management & Drives
N e v e r
s t o p
t h i n k i n g .
6ED003L06-F Gate Drive-IC
for three-phase converters
Revision History:
2007-2
Previous Version:
1.1
Page
Subjects (major changes since last revision)
13
revised fig. 10
V1.1
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Edition 2007-2
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6ED003L06-F Gate Drive-IC
for three-phase converters
1
Short Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Technology Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
3.1
3.1.1
3.1.2
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.5
3.5.1
3.5.2
3.5.3
Technical Description of 6ED003L06-F . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Control Input Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Highside input pins (HIN), Lowside input pins (LIN) . . . . . . . . . . . . . . . . 7
Enable pin (EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Control Output Section (/FAULT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
IC Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Gate Drive Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Low Side Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
High Side Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Negative Transients at High Side Reference (pin VSx) . . . . . . . . . . . . . 12
Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Overcurrent Protection (ITRIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Deadtime & Shoot Through Prevention . . . . . . . . . . . . . . . . . . . . . . . . . 14
Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
4.1
4.2
4.3
4.4
4.5
Application of 6ED003L06-F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC-supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootstrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Failure Reset (RCin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
Summary of Used Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Application Note
3
15
15
15
17
17
18
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
1
Short Description
The 6ED003L06-F is a high voltage gate drive IC for three-phase converters up to a
maximum blocking voltage of 600V. The converters can be used for example in drives
applications which are basing on induction machines (IM) or brushless DC motors. The
6ED003L06-F is designed in silicon-on-insulator-technology (SOI). This technology
provides a high ruggedness against negative voltage spikes and noise.
This application note gives an overview of the technological characteristics. It also
describes the most important sections in terms of the application and gives design
recommendations for a proper operation of the device in the application.
6ED003L06-F is similar to use as IR2136 and its derivates. It is compatible to the same
footprint, but not compatible in terms of the internal thresholds, which may concern the
external circuitry. Please refer here to the product specifications of 6ED003L06-F.
Application Note
4
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
2
Technology Characteristics
SOI is the abbreviation of Silicon-On-Insulator and is an advanced technique for MOS/
CMOS fabrications. It differs from the conventional bulk process by placing the active
transistor layer on the top of an insulator, as shown in Figure 1.
Gate
Source
Doping
Doping-well
Poly-Si
Drain
Oxide
Doping-well
Buried Oxide
Silicon Substrate
Figure 1
Cross section of a FET in SOI-technology
The silicon is separated by a buried silicon oxide layer to one layer on the top and the
other on the bottom. The one on the top, which is the silicon film, is used to produce the
transistor and the one on the bottom is used as the silicon substrate. The buried silicon
oxide provides an insulation barrier between the active layer and silicon substrate and
hence reduces the parasitic capacitance tremendously. Moreover, this insulation barrier
disables leakage or latch-up currents between adjacent devices.
A major technological advantage of the Thin-Film-SOI technology is the easy way of
lateral insulation of elements inside the silicon film. The thin film technology allows each
device to be separated from all other devices by a simple local oxidation (LOCOS)
process. Thus, there is no need for CMOS-wells for preventing the "latch-up" effect and
reducing the chip size.
The small size of PN-junctions inside the thin silicon film leads to higher switching speed,
lower leakage currents and consequently higher temperature stability. In order to obtain
a proper body contact for the thin SOI-MOS transistor the channel doping is extended
and connected to a common source contact (split source contact). Hence the thin-film
SOI-MOS transistor exhibits an anti-paralleled diode that safeguards the device in case
of polarity reversal.
In spite of the thin drift regions inside the silicon films, reasonable low on-resistance per
area is achieved. This allows a cost effective layout of the output driver transistors.
The SOI technology is also implemented for the 600 V level-shift transistors and highvoltage diodes. The 600V-NMOSFET is based on the low-voltage SOI-NMOSFET
structure in conjunction with a very long Drain-extension. The buried oxide insulation
barrier cuts off parasitic current paths between substrate and silicon film. This prevents
the latch-up effect even in case of high dv/dt switching under elevated temperature and
hence provides improved robustness.
Application Note
5
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
Besides these improvements, the thin-film SOI-technology provides additional benefits
like lower power consumption and higher immunity to radioactive radiation or cosmic
rays.
Application Note
6
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
3
Technical Description of 6ED003L06-F
3.1
Control Input Section
3.1.1
Highside input pins (HIN), Lowside input pins (LIN)
Vcc
Schmitt-Trigger
HINx
LINx
Figure 2
≈ 50Ω
INPUT NOISE
FILTER
UZ=10.5V
SWITCH LEVEL
VIH; VIL
Schematic of the structure of an input control pin
All gate control input pins are equipped with an integrated zener clamp which is
activated, when the input signal is higher than 10.5 V according to Figure 2. It must be
guaranteed by design, that these zener diodes are not overstressed by excessive
voltages larger than VIN = 10 V. The gate sections of the IC are controlled by inverted
logic signals. A LOW-signal is therefore setting the respective output to HIGH. The
integrated pull-up resistor pulls the inputs to HIGH, if the pin is floating or driven from a
high impedance source. The maximum current out of each HIN- or LIN-pin is ILIN- = IHIN= 200 µA. Please refer to Section 4.3 for practical recommendations
The Schmitt-trigger sets its output to LOW, if the input signal is lower than 0.9 V typical.
A HIGH level is identified, when the input is higher than 2.1 V typical. This setting of
levels provides a full compliance to LSTTL- and CMOS-levels, so that the 6ED003L06F is directly connectable to common microcontroller output pins. Some competitor
components do not provide the full compliance to these voltage levels, so that
theconnectivity to the microcontroller is a major concern. However, electromagnetic
a)
b)
tFILIN
tFILIN
HIN
LIN
LIN
high
HO
LO
LO
Figure 3
low
Timing Diagram for Input Filter Characteristic
Application Note
7
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
interference may cause distorsions of the control signals, so that a RC-filtering of the
input pins can improve the signal integrity of the system.
The input noise filter suppresses short pulses and prevents the driven IGBT from
excessive switching losses. The input noise filter time at LIN for turning on and off the
IGBT and at HIN for turning on the IGBT is typically tFILIN =270 ns. This means, that
an input signal must stay on its level for this period of time in order that the state change
is processed correctly according to Figure 3 and Figure 4 repectively.
The turn-off of the highside IGBT is processed, when a HIGH-level signal at the pins /
HIN occurs for longer than typically tFILIN1 =200 ns according to b) of Figure 4. Otherwise
the change in the status of the input signal /HIN will be skipped according to a).
tFILIN1
a)
tFILIN2
toff,HINx
HIN
toff,HINx < tFILIN1
high
HO
b)
HIN
toff,HINx
toFILIN1 < toff,HINx < tFILIN2
HO
c)
HIN
toff,HINx
toff,HINx > tFILIN2
HO
Figure 4
Timing Diagram for Input Filter Characteristic
A full pulse is transmitted , if it is longer than tHIN = 350 ns typically. However, it is
recommended to stay above a minimal pulse duration of 1 µs in order to avoid excessive
switching losses due to linear operation of the switching transistors.
Application Note
8
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
3.1.2
Enable pin (EN)
The signal applied to pin EN controls directly the output sections. All outputs are set to
LOW, if the signal is lower than 1.32V typically and operation is enabled with signal levels
higher than typical 2.1 V. The internal structure of the pin is the same as Figure 2 except
of the switching levels of the Schmitt-Trigger. The typical propagation delay time is here
tEN = 700 ns.
3.2
Control Output Section (/FAULT)
VDD
FAULT
Figure 5
6ED003L06-F
VCC
RON,FLT
>1
from ITRIP-Latch
from uv-detection
Schematic of the structure of the /FAULT-pin
This pin indicates the status of the IC. In case of undervoltage lockout or triggering of the
overcurrent protection, the level of this pin is LOW. An external pull-up resistor to VDD in
the range of 10 kΩ is necesary for this open drain pin. Due to this internal structure
according to Figure 5, the voltage at this pin is internally clamped to VSS and VCC. The
internal pull-down FET has a typical resistance of RON,FLT = 61Ω. The delay times from
the triggering event to the change of status at the /FAULT-pin is tITRIP = 690 ns typically
according to the timing diagram shown in Figure 6.
vITRIP
VITRIP
0.1V
t
vFAULT
0.5V
tFLT
Figure 6
3.3
tFLT
t
Timing diagramm for ITRIP to FAULT propagation delay
IC Supply Section
The supply voltage of the IC must reach initially at least a typical voltage of VCCUV+ =
VBSUV+ = 12 V for the lowside and highside supply, before the IC gets into an operational
state. This is necessary in order to have a sufficient supply voltage for the highside gate
drive sections before the self supply is established in case of a bootstrapping supply
technique.
Application Note
9
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
The IC shuts down the individual gate drives, when the related supply voltage is below
VCCUV- = VBSUV- = 10.3 V. This prevents the driven transistors from critically low gate
voltage levels during on-state and therefore from excessive power dissipation. Please
refer to Section 3.5.3 for further information
20
V
17.5
13
VCCMAX , VBSMAX
vCC
vBS
VCCUV+, VBSUV+
12
VCCUV-, VBSUV-
10.3
t
IC STATE
OFF
Figure 7
ON
ON
Recommended
Area
ON
Forbidden
Area
ON
ON
Recommended
Area
ON
OFF
Areas of Operation
Figure 7 shows the IC states and the correlated areas of operation concerning the
supply voltages for both the lowside supply voltage vCC and the highside supply voltages
vBS. There is a forbidden area for supply voltages above 20 V,because here the internal
clamping structures begin to break throgh and the IC is endangered to be damaged by
excessive power dissipation.
3.4
Gate Drive Section
3.4.1
Low Side Gate Drive
The lowside gate drive sections contain FET in push-pull configuration. The typical
RDS(on) of them is approximately 40 Ω for the turn-on FET (p-channel) and 12 Ω for the
turn-off FET (n-channel) according to Figure 8. This results in a typical turn-on current
of IO+ = 155 mA and a typical turn-off current of IO- = 440 mA. These RDS(on)-values are
not tested and may differ over the range of the instantaneous gate output voltage.
There is a levelshift structure inlcuded in the 6ED003L06-F in order to allow the potential
at pin COM to be negative referenced to pin VSS without forcing substrate currents in
the IC. This is important, because instantaneous diode forward voltage drops can be
Application Note
10
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
larger than -0.7 V. Please note here, that this levelshift in not correlated with negative
voltage transients of pin VSx referenced to COM.
6ED003L06-F
VCC
VSS / COM
LEVELSHIFTER
DELAY
PMOS
RON ≈ 40Ω
IO
+
NMOS
LOx
RG
IO
R- ON ≈ 12Ω
VSS
COM
Figure 8
Structure of the lowside gate drive section
The output pins LOx are clamped to the supply voltage VCC of the IC via the reverse
diodes of the FET. This prevents the output pins from excessive pulse voltages, which
may be coupled into the gate track.
3.4.2
High Side Gate Drive
The high side gate drive section is shown in Figure 9. The control signal passes the high
voltage level shift section and is stored in the gate drive flipflop-latch. The incoming
signal as well as the output gate drive signal are clamped internally by integrated diodes
to the reference voltage (pin VSx) and the bias voltage (pin VBx). The internal structure
of the output driver itself is the same as for all three low voltage output pins.
Please note, that there is a parasitic connection from each high side to the low side
control area, which is not given in Figure 9. It is a very high ohmic diode structure and it
is not allowed to use it as a bootstrap diode. It must be guaranteed by the design of the
induvidual application, that there are no negative voltages down to -50 V referred to VSS
at pin VS1, VS2 or VS3, which last longer than 500ns according to the maximum rating
of the datasheet of 6ED003L06-F.
Application Note
11
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
6ED003L06-F
VB3
HV LEVELSHIFTER
LATCH
DRIVER
UVLO
HO3
VS3
Figure 9
3.4.3
Structure of a high side gate drive section
Negative Transients at High Side Reference (pin VSx)
Due to the inherent oxide isolation of the SOI-technology, the 6ED003L06-F is very
robust against negative transient voltages. Therefore, the minimum voltage at the pins
VSx is specified to -50 V for a period of time of 250 ns. This duration is long enough to
cover the usual requirement for this stress in drives applications. However, it must be the
target of any design to avoid such negative voltages at all.
Parasitic inductances can induce voltages, so that the potential at pins VS1, VS2 or VS3
becomes negative in respect to pin VSS. It is a well known failure mechanism of common
driver IC technologies, that these negative voltages force current through the substrate
material. The substrate currents can lead to a latch of the high side gate driver, which is
then insensitive to any control signal. The result is, that the IGBT are operated in short
circuit, which leads to excessive power dissipation and also to system breakdown.
The negative voltage can also increase the pulse current through the bootstrap diode
and may lead to damage. Additionally, internal parasitic diode structures of the IC may
be damaged as well.
3.5
Protection Section
3.5.1
Overcurrent Protection (ITRIP)
The current signal of the DC-link reference is measured in order to recognize overcurrent
or halfbridge short circuit events. A shunt resistor generates a voltage drop. A small RCfilter for attenuating voltage spikes is recommended. Such spikes may be generated by
parasitic elements in the practical layout. If the voltage drop over the shunt is higher than
typically VIT,TH+ = 450 mV, then the internal comparator is triggered according to
Figure 10. This results in a trigger current of
V IT, TH+
I ITRIP = -------------------RSH
Application Note
12
[1]
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
where RSH is the value of the shunt resistor.
The output of the comparator passes a noise filter, which inhibits an overcurrent
shutdown caused by parasitic voltage spikes. A set-dominant latch stores the
overcurrent event until it is reset by the signal provided from the RCIN circuit.
The ITRIP-comparator switches the discharging NMOS-FET at pin RCIN. The RDS(on) of
the FET is typically 56 Ω, so that there is a characteristical discharge curve in respect of
the external capacitor CRCin. The time constant is defined by the external capacitor CRCin
and the RDS(on) of the FET. The dischage phase ends, when the comparator is low again.
This corresponds to a voltage level at the comparator of VIT,TH+ -VIT,HYS = 450 mV - 85
mV = 365 mV, where VIT,HYS = 85mV is the hysteresis of the ITRIP-comparator.
6ED003L06-F
COM
VIT,HYS= 85mV
ITRIP
≈ 50Ω
RSH
VZ=10.5V
VSS
VIT,TH+=
0.45V
Comp.
INPUT
NOISE
FILTER
VDD2 ≈ 8V
VCC
VCC
RRCin
RCIN
current source
VRCIN,TH= 5.8V
VRCIN,HYS = 2.5V
to /FAULT
VSS
Figure 10
Q
SET
DOMINANT
LATCH
R
IRCIN
NMOS
RON,RCIN
CRCin
S
to input
signal logic
Internal structure of the ITRIP and RCIN sections
It is important to note here, that due to a large external capacitance at pin RCIN and
rather short occurrance of overcurrent, the voltage at the capacitor CRCin is not below the
thereshold of the RCIN Schmitt-Trigger. The threshold of the Schmitt-Trigger VRCIN,TH VRCIN,HYS = 3.3 V lead to the result, that the set-dominant latch is still in active reset and
the IC might restart operation as soon as the voltage at pin ITRIP is in the operative
range again, which is VIT,TH+ -VIT,HYS. If the trigger level at pin ITRIP is set closely to the
maximum operative current, then this behaviour acts as a soft overcurrent limitation. As
long as the voltage at pin RCIN does not hit the 3.3V level of the Schmitt-trigger, the gate
drive section restarts immediately after the overcurrent vanishes. This may be after
some pulse periods.
3.5.2
Deadtime & Shoot Through Prevention
The 6ED003L06-F prevents shoot through and generates a fixed deadtime between the
individual IGBT of each half bridge. The deadtime is typically DT = 325 ns. However, it
is necessary to check the transient times af the driven IGBT. These times are the turnApplication Note
13
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
on delay td(on), the rise time tr, the turn-off delay time td(off) and the fall time tf. They are
defining the timing and the deadtime which is mandatory for the prevention of shoot
through. A deadtime of 1µs to 1.5µs is sufficient for most applications.
3.5.3
Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) of the highside sections act directly on the output gate
drive flipflop according to Figure 9, so that an immediate shut down is provided. The
UVLO is independent in respect of all three highside gate drive sections.
In case of an UVLO shut down of an output section, it is necessary to reach the start-up
levels of VCCUV+ = VBSUV+ = 12 V again as descibed in Section 3.3. The independent
UVLO functions of low and high side sections enable a restart of the affected highside
section in case of a bootstrapping supply, because the switch mode operation of the
lowside transistor pumps continuously charges into the according bootstrap capacitor,
which increases the bootstrap voltage VBS.
DEADTIME &
SHOOT-THROUGH
PREVENTION
>1
DEADTIME &
SHOOT-THROUGH
PREVENTION
Figure 11
To Highside
To Lowside
...
...
EN
ITRIP-Latch
UVLO
To Highside
To Lowside
Structure of a lowside UVLO
The UVLO for the lowside gate drive sections is common for all three output circuits and
acts on a triple input OR-gate according to Figure 11. The output of this gate is fed into
the deadtime and shoot through prevention of the IC. Please note here, that a lowside
UVLO is also affecting the highside outputs. Hence, all the gate drives will be shut down
in case of a lowside UVLO.
Application Note
14
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
4
Application of 6ED003L06-F
4.1
VCC-supply
The supply voltage in drive systems is often generated by a switch mode power supply
with an output in a range of 15V to 18 V. The supply voltage is also applied to the gates
of the IGBT. This is sufficient in order to drive IGBT properly. However, it is necessary to
take care, that the bootstrap capacitors are large enough in order to keep the voltage
stable in periods, where no switching of the lowside transistor T2 occurs. This is
explained more in detail in Section 4.2.
4.2
Bootstrapping
Bootstrapping is a common method of pumping charges from a low potential to a higher
one. With this technique a supply voltage for the floating highside sections of the gate
drive can be easily established according to Figure 12. It is only the effective circuit
shown for one of the three half bridges. The current limiting resistor RLim may be
connected to each of the three bootstrap diodes of the three halfbridges.
RLim
DBS
iBS
vFBS
VB
VCC
CVCC
Gate HO
Drive VS
IC
LO
CBS
T1
D1
T2
D2
GND
Figure 12
VBus
Bootstrap circuit for one halfbridge
The first pulse of transistor T2 will force the potential of pin VS to GND. The resulting dv/
dt leads to a displacement current iBS into the capacitor CBS. The current iBS is a pulse
current and therefore the ESR of the capacitor CBS must be very small in order to avoid
losses in the capacitor, that result in lower lifetime of the capacitor.
This pin is on high potential again after transistor T2 is turned off. But now the bootstrap
diode DBS blocks a reverse current, so that the charges on the capacitor remain the
same. The bootstrap diode also takes over the blocking voltage between pin VB and
VCC. The voltage of the bootstrap capacitor can now supply the highside gate drive
sections.
Application Note
15
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
It is a general design rule for the location of bootstrap capacitors, that they must be
placed as close as possible to the IC. Otherwise, parasitic resistors and inductances may
lead to voltage spikes, which may trigger the undervoltage lockout threshold of the
individual highside driver section.
The voltage of bootstrap capacitor is approximately
V BS ≈ V CC – V FBS
[2]
A current limiting resistor RLim reduces the peak of the pulse current during the turn-on
of transistor T2. The pulse current will occur at each turn-on of transistor T2,so that with
increasing switching frequency the capacitor CBS1 is charged more frequently. Therefore
a smaller capacitor is suitable at higher switching frequencies. A low quiescent current
of the highside section is very important in order to keep the bootstrap capacitors small.
The bootstrap capacitor is mainly discharged by two effects: The highside quiescent
current and the gate charge of the transistor to be turned on. The calculation of the
bootstrap capacitor results in
i QBS1 ⋅ t P + Q G
C BS = --------------------------------------∆ vBS
[3]
with iQBS1 being the quiescent current of the highside section, tP the switching period, QG
the total gate charge and DvBS the voltage drop at the bootstrap capacitor within a
switching period.
Figure 13
Size of the bootstrap capacitor as a function of the switching
frequency fP for driving IKA06N60T according to Equation [3]
Please note here, that Equation [3] is valid for continuous switching operation according
to the switching frequency. The use of space vector modulations can cause periods up
to 60° (electrical), in which no switching of the low side transistor of a halfbridge occurs.
Application Note
16
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
This effects the bootstrap capacitor size, especially for low output current (motor current)
frequencies. In this case the variable tP must be set to the longest period of no switching.
Figure 13 shows the curve corresponding to Equation [3] for a continuous sinusoidal
modulation, if the voltage ripple ∆vBS = 0.1V. The recommended bootstrap capacitance
is therefore in the range up to 4.7µF for most switching frequencies.
4.3
Control Input Pins
All control input pins incorparate a series resistor as well as a pull-up resistor (/LIN and
/HIN) or a pull-down resistor (EN), respectively. The integrated noise filter suppresses
short pulses up to a duration of 200 ns anyway according to Section 3.1.1. External
circuitry is therefore not madatory. However, external pull-up resistors of approx. 10 kΩ
help to keep the IC in correct operation. Please note here, that the pull-up resistor must
also comply to the output specifications of the µC-pins, which are connected to the
6ED003L06-F.
Some applications may not need all control pins to be connected to external circuits.
These pins must be pulled up to 5 V or 3.3 V, respectively.
4.4
Failure Reset (RCin)
100
ms
10
1
C_RCin=1nF
C_RCin=2.2nF
C_RCin=4.7nF
C_RCin=6.8nF
C_RCin=10nF
0.1
0.01
t FLTCLR
0.001
1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08
1.00E+09
RRCIN
Figure 14
-Clear-Time tFLTCLR dependent on external circuit according to
Figure 10 (RRCin, CRCin)
The external circuit at pin RCIN defines the overcurrent recovery of the drive system.
This circuit can consist of a single capacitor CRCin according to Figure 10. There is also
Application Note
17
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
the possibility of an optional path to VCC via resistor RRCin. The fault-clear time tFLTCLR is
dependent on the re-charging of CRCin, because the systems recovers, when the
threshold of the integrated Schmitt-trigger according to Figure 10 is reached.This
means, that the resistor to VCC is not mandatory, but it can help to precisely adjust the
fault-clear time.
Figure 14 shows the function of the fault-clear time dependent on discrete values of
CRCin and RRCin. It can be seen, that all curves saturate with very high resistor values of
RRCin. This is the case, when RRCin is very high or even not assembled. In these cases,
the integrated current source charges CRCin with a constant current of 2.7 µA.
Please note here, that very high values of CRCin may lead to uncomplete discharge of
CRCin via the integrated FET and effects according to Section 3.5.1 may occur. The
relevant voltage discharge curve vRCin(t) of the external capacitor at pin RCin can be
approximated by
v RCin ( t ) = V CC ⋅ e
–t
-------------------------------C RCin ⋅ R FET
[4]
where RFET is the Rds(on) of the integrated FET and CRCin is the external capacitance, if
there is a high ohmic resistor to the supply voltage VCC. Equation [4] is valid, when the
resistor to VCC is much larger than RFET.
If only a capacitor is at pin RCin, then Equation [4] changes to
vRCin ( t ) = 8V ⋅ e
–t
-------------------------------C RCin ⋅ R FET
[5]
The design must guarantee, that the voltage at capacitor CRCin reaches the lower
threshold of the RCin-Schmitt-trigger for the delay time of the input noise filter at pin
ITIRP. Otherwise, a release of the gate sections, so that the IGBT are turned on again,
which may damage the IGBT. The capacitor should therefore not be larger than 10nF.
4.5
Typical Application
Figure 15 shows the schematic of a typical application for a consumer drive system,
which may be suitable for a washing machine. The bootstrap diodes D1 to D3 are
accompanied by a current limitation resistor R1 to R3. This prevents the diodes from an
overload in terms of peak current stress. The bootstrap capacitors C8 to C10 have a
value of 2.2 µF each, which is sufficient for a wide range of switching frequencies.
The resistor R5 is not assembled, so that the effective capacitor at pin RCIN is C2
(2.2nF) which leads to a fault-clear time of approximately 4ms according to Figure 14.
A RC-filter consisting of C3 and R7 attenuates spikes, which may occur in the shunt
voltage signal. The values must be chosen, so that the bandwidth of the RC-filter is at
Application Note
18
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
least 10 times higher than the switching frequency, which is in the range of 10kHz up to
20 kHz for consumer drives. On the other hand it must also be smaller that the frequency
of typical fall and rise times of the IGBT, which are in the range of several 10 ns.
Figure 15
Schematic of a typical application
Please note here, that 6ED003L06-F does not force the use of pull-down resistors at the
IGBT gate pins. However, it is a good design flow to use such resistors as in the
schematic of Figure 15. The schematic also contains individual resistors for turn-on and
turn-off (R13 - R24).
Application Note
19
V1.1, 2007-2
6ED003L06-F Gate Drive-IC
for three-phase converters
5
Summary of Used Nomenclature
Physics:
General identifiers:
Special identifiers:
A .........cross area
b, B .....magnetic inductance
d, D .....duty cycle
f...........frequency
i, I ........current
N .........number of turns
p, P .....power
t, T.......time, time-intervals
v, V......voltage
W ........energy
h..........efficiency
AL ........... inductance factor
V(BR)CES .. collector-emitter breakdown
voltage of IGBT
VF........... forward voltage of diodes
Vrrm .......... maximum reverse voltage of diodes
big letters:
constant values and
time intervals
small letters: time variant values
Components:
C .........capacitance
D .........diode
IC ........integrated circuit
L ......... inductance
R......... resistor
TR....... transformer
Indices:
AC.......alternating current value
DC.......direct current value
BE .......basis-emitter value
C .........Collector value
CS.......current sense value
E .........Emitterr value
G .........Gate value
OPTO..optocoupler value
P .........primary side value
Pk........peak value
R........... reflected from secondary to primary side
S .........secondary side value
Sh .......shunt value
UVLO ..undervoltage lockout value
Z..........zener value
Application Note
20
fmin ......... value at minimum pulse frequency
i ..............running variable
in ............input value
max ........maximum value
min .........minimum value
off ...........turn-off value
on ...........turn-on value
out ..........output value
p .............pulsed
rip ...........ripple value
1, 2, 3 .....on-going designator
V1.1, 2007-2
www.infineon.com
Published by Infineon Technologies AG
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