CoolSET F3R80 DIP7 brownout frequency jitter version design guide

CoolS ET ™ F3R80 Fam il y
ICE3xRxx80JZ/VJZ
I CE3xR xx80JZ/ VJZ Desig n G uide
AN-PS0044
Desig n G uide I CE3xRxx8 0JZ/ VJZ
V1.5, 2013-09-09
Po wer Manag em ent & Mult im ar k et
Edition 2013-09-09
Published by Infineon Technologies AG,
81726 Munich, Germany.
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ICE3xRxx80JZ/VJZ Design Guide
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Design Guide ICE3xRxx80JZ/VJZ
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Revision History
Major changes since previous revision
Date
Version
Changed By
Change Description
9 Sep 2013
1.5
Kyaw Zin Min
Add input OVP version CoolSET F3R80
ICE3xRxx80VJZ
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Table of Contents
Revision History .............................................................................................................................................. 4
Table of Contents ............................................................................................................................................ 5
1
Introduction .................................................................................................................................. 6
2
List of Features ............................................................................................................................ 6
3
Package ........................................................................................................................................ 7
4
Block Diagram .............................................................................................................................. 8
5
Typical Application Circuit ........................................................................................................ 10
6
6.1
6.1.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.4
6.4.1
6.4.2
6.4.3
6.5
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
Functional description and component design ........................................................................ 12
Startup time ................................................................................................................................. 12
Vcc capacitor .......................................................................................................................... 12
Soft Start...................................................................................................................................... 13
Low standby power - Active Burst Mode ....................................................................................... 13
Entering Active Burst Mode with selectable burst entry level .................................................... 13
Working in Active Burst Mode.................................................................................................. 15
Leaving Active Burst Mode ...................................................................................................... 15
Minimum Vcc supply voltage during burst mode ...................................................................... 16
Remarks for the selection of entry/exit burst level .................................................................... 17
Low EMI noise ............................................................................................................................. 17
Frequency jittering................................................................................................................... 17
Soft gate drive and gate turn on resistor .................................................................................. 18
Other suggestions to solve EMI issue ...................................................................................... 18
Tight control in maximum power - Propagation delay compensation ............................................. 18
Protection Features ...................................................................................................................... 19
Odd skip auto restart protection mode ..................................................................................... 19
Non switch auto restart mode .................................................................................................. 20
Blanking time for over load protection ...................................................................................... 20
Brownout Mode (ICE3xRxx80JZ only) ..................................................................................... 22
Line input over voltage protection (ICE3xRxx80VJZ only) ........................................................ 24
External protection enable (ICE3xRxx80JZ only) ..................................................................... 25
7
Input power curve ...................................................................................................................... 25
8
Layout Recommendation........................................................................................................... 26
9
Product portfolio of CoolSET™ F3R80 (DIP-7) brownout/input OVP & frequency jitter
version ........................................................................................................................................ 27
10
Useful formula for the SMPS design ......................................................................................... 28
11
References ................................................................................................................................. 30
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Introduction
1
Introduction
The CoolSET™-F3R80, ICE3xRxx80JZ/VJZ is the latest development of the CoolSET™. It is a PWM controller
with power MOSFET and startup cell in a DIP-7 package. The switching frequency is running at 65/100 kHz and
it targets for DVD player, set-top box, portable game console, white goods, auxiliary power supply for server/PC,
etc.
The ICE3xRxx80JZ/VJZ adopts the 800V avalanche rugged CoolMOS™ power switch and the BiCMOS
technology to provide a wider Vcc operating range up to 25V. It inherits the proven good features of CoolSET™
F3R such as Active Burst Mode, propagation delay compensation, soft gate drive, auto restart protection for
major faults (Vcc over voltage, Vcc under voltage, over temperature, over-load, open loop and short optocoupler), it also has selectable entry and exit burst mode level, brownout feature/input OVP, built-in soft start
time, built-in and extendable blanking time, frequency jitter feature and external auto-restart enable, etc. The
particular features are the best-in-class low standby power with selectable burst mode power level and the good
EMI performance.
2
List of Features
800V avalanche rugged CoolMOS™ with Startup Cell
Active Burst Mode for lowest Standby Power
Selectable entry and exit burst mode level
65/100kHz internally fixed switching frequency with jittering feature
Auto Restart Protection for Over load, Open Loop, VCC Under voltage & Over voltage and Over
temperature
External auto-restart enable pin (only for ICE3xRxx80JZ)
Over temperature protection with 50°C hysteresis
Built-in 10ms Soft Start
Built-in 20ms and extendable blanking time for short duration peak power
Propagation delay compensation for both maximum load and burst mode
Adjustable brownout (only for ICE3xRxx80JZ)
Input OVP (only for ICE3xRxx80VJZ)
Overall tolerance of Current Limiting < ±5%
BiCMOS technology for low power consumption and wide VCC voltage range
Soft gate drive with 50Ω turn on resistor
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Package
3
Package
The package for F3R80 ICE3xRxx80JZ brownout and frequency jitter mode product is DIP-7.
Pin
BBA
FBB
CS
n.c.
1
2
8
7
VCC
3
4
Figure 1
5
Name
Description
1
BBA
Brownout, extended Blanking time & Auto-restart enable
2
FBB
Feedback & Burst entry/exit control
3
CS
Current Sense/800V CoolMOS™ Source
4
n.c
not connected
5
Drain
800V CoolMOS™ Drain
6
-
(no pin)
7
VCC
Controller Supply Voltage
8
GND
Controller Ground
GND
Drain
ICE3xRxx80JZ Pin configuration
The package for F3R80 ICE3xRxx80VJZ input OVP and frequency jitter mode product is DIP-7.
Pin
BV
FBB
CS
n.c.
Figure 2
1
2
8
7
VCC
3
4
5
Name
Description
1
BV
extended Blanking time & input OVP
2
FBB
Feedback & Burst entry/exit control
3
CS
Current Sense/800V CoolMOS™ Source
4
n.c
not connected
5
Drain
800V CoolMOS™ Drain
6
-
(no pin)
7
VCC
Controller Supply Voltage
8
GND
Controller Ground
GND
Drain
ICE3xRxx80VJZ Pin configuration
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Block Diagram
4
Block Diagram
Figure 3
Block diagram of ICE3xRxx80JZ
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Block Diagram
Figure 4
Block diagram of ICE3xRxx80VJZ
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Typical Application Circuit
5
Typical Application Circuit
Figure 5
Typical application circuit with ICE3AR2280JZ 20W 5V
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Typical Application Circuit
Figure 6
Typical application circuit with ICE3AR0680VJZ 30W 12V
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Functional description and component design
6
Functional description and component design
6.1
Startup time
Startup time is counted from applying input voltage to IC turn on. ICE3xRxx80JZ/VJZ has a startup cell which is
connected to input bulk capacitor. When there is input voltage, the startup cell will act as a constant current
source to charge up the Vcc capacitor and supply energy to the IC. When the Vcc capacitor reaches the Vcc_on
threshold 17V, the IC turns on. Then the startup cell is turned off and the Vcc is supplied by the auxiliary
winding. Start up time is independent from the AC line input voltage and it can be calculated by the equation (1).
Figure 7 shows the start up time of 85Vac line input.
tSTARTUP 
VVCCon  CVCC
IVCCCharg e
(1)
where, IVCCCharge : average of Vcc charge current of IVCCCharge2 and IVCCCharge3 ( 0.8mA ),
VVCCon : IC turns on threshold ( 17V ), CVCC : Vcc capacitor
Please refer to the datasheet for the symbol used in the equation.
0.236s
Burst
mode
selection
Channel
Channel
Channel
Channel
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BBA voltage (VBBA)
Measured startup time = 0.23s
Startup @ 85Vac & max. load
Figure 7
The startup delay time at AC line input voltage of 85Vac
Precaution : For a typical application, start up should be Vcc ramps up first, other pin (such as FB pin) voltage
will follow Vcc voltage to ramp up. It is recommended not to have any voltage on other pins (such
as FBB; BBA and CS) before Vcc ramps up.
In addition, the dummy load in the Vcc pin should be larger than 150kΩ. Otherwise, it would has a
risk of delay startup.
6.1.1 Vcc capacitor
The minimum value of the Vcc capacitor is determined by voltage drop during the soft start time. The formula is
expressed in equation (2).
CVCC 
I VCC sup 2  t ss 2

VCCHY
3
(2)
where, IVCCCsup2 : IC consumption current ( 4.8mA for ICE3AR2280JZ), tss : soft start time ( 10ms ),
VCCHY : Vcc turn-on/off hysteresis voltage ( 6.5V )
Therefore, the minimum Vcc capacitance can be 4.9μF. In order to give more margins, 10uF is taken for the
design. The startup time tSTARTUP is then 0.21s. The measured start up time is 0.23s (Figure 6). A 0.1uF filtering
capacitor is always needed to add as near as possible to the Vcc pin to filter the high frequency noise.
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Functional description and component design
6.2
Soft Start
When the IC is turned on after the startup time, a digital soft start circuit is activated. A gradually(32 steps)
increased soft start voltage is emitted by the digital soft start circuit, which in turn releases the duty cycle
gradually increase from zero. The duty cycle increases to maximum (which is limited by the transformer design)
at the end of the soft start period. When the soft start time ends, IC goes into normal mode and the duty cycle is
controlled by the FB signal. The soft start time is set at 10ms for maximum load. The soft start time is load
dependent; shorter soft start time with lighter load.
Figure 8 shows the soft start behavior at 85Vac input and maximum load. The primary peak current increases
slowly to the maximum in the soft start period.
1V
9.4ms(32steps)
Channel
Channel
Channel
Channel
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BBA voltage (VBBA)
Soft Start time = 9.4ms(32 steps)
Soft start @ Vin=85Vac & max. load
Figure 8
Soft start at AC line input voltage of 85 Vac
6.3
Low standby power - Active Burst Mode
The IC will enter Active Burst Mode function at light load condition which enables the system to achieve the
lowest standby power requirement of less than 100mW. Active Burst Mode means the IC is always in the active
state and can therefore immediately response to any changes on the FB signal, VFB.
6.3.1 Entering Active Burst Mode with selectable burst entry level
Because of the current mode control scheme, the feedback voltage VFB actually controls the power delivery to
output. An important relationship between the VCS and the VFB is expressed in equation (3).
VFB  VCS  AV  VOffsetRamp
(3)
where, VFB:feedback voltage, VCS:current sense voltage, AV:PWM OP gain (3.25), VOffset-Ramp:voltage ramp offset
(0.6V)
When the output load reduces, the feedback voltage VFB drops. If the VFB stays below VFB_burst for 20ms, the IC
enters into the Active Burst Mode. The threshold power to enter burst mode is expressed in equation (4).
PBURST _ enter 
V
V
1
1
V
1
 LP  Ip 2  f SW   LP  ( CS )2  f SW   LP  ( FB _ burst Offset  Ramp )2  f SW
2
2
Rsense
2
Rsense  AV
(4)
where, Lp : transformer primary inductance
Rsense: current sense resistance, fsw: switching frequency, VFB_burst: Feedback level to enter burst mode
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Figure 9
Entry burst mode detection
In enhancement to CoolSET™ F3R, user can select the burst mode entry and exit level in CoolSET™ -F3R80
according to the application by adding different values of CFB (C19) capacitor at FBB pin. The IC would detect
the number of count at the FBB pin within the 1st 1ms after VCC reaches the VVcc_on (17V). During that detection
time, the VFBB voltage swings between 0.5 V to 4.5V like a sawtooth waveform by charging and discharging the
FBB capacitor, CFB as shown in Figure 4. Based on the number of count, the IC will select burst mode entry and
exit level. There are 4 different levels are available and the following table is the recommended capacitance
range of the CFB (C19) capacitor for the entry and exit burst level.
CFB
Corresponding
no. of counts
≥ 6.8nF
1nF~2.2nF
220pF~470pF
≤100pF
≤7
8 ~ 39
40 ~ 91
≥ 92
Entry level
% of Pin_max
10%
6.67%
4.38%
0
Exit level
VFB_burst
1.6V
1.42V
1.27V
never
% of Pin_max
20%
13.30%
9.60%
0
Vcsth_burst
0.45V
0.37V
0.31V
always
Figure 10 shows the waveform with the load drops from nominal load to light load. After the 20ms blanking time
IC goes into burst mode.
20ms
Channel
Channel
Channel
Channel
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BBA voltage (VBBA)
Entering Active Burst mode with built-in blanking
time 20ms when load changes from full to light @
Vin=85Vac
Figure 10
Entering active burst mode
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Functional description and component design
6.3.2 Working in Active Burst Mode
In the active burst mode, the IC is constantly monitoring the output voltage by feedback pin, VFBB, which controls
burst duty cycle and burst frequency. The burst “ON” starts when VFB reaches 3.5V and it stops when VFB is
dropped to 3.2V. During burst “ON”, the primary current limit is reduced to Vcsth_burst ( 31% ~ 45% of maximum
peak current ) to reduce the conduction losses and to avoid audible noise. The FB voltage is swinging like a saw
tooth between 3.2V and 3.5V. The corresponding secondary output ripple (peak to peak) is controlled to be
small. It can be calculated by equation (5).
Vout _ ripple_ pp 
Ropto
RFB  Gopto  GTL 431
 VFB
(5)
where, Ropto : series resistor with opto-coupler at secondary side (e.g. R21 in Figure 3)
RFB : IC internal pull up resistor connected to FB pin (RFB=15.4KΩ)
Gopto : current transfer gain of opto-coupler
GTL431 : voltage transfer gain of the loop compensation network (e.g. R23, R24, R25, R26, C26, C27
in Figure 5)
VFB : feedback voltage change (0.3V)
Figure 11 is the output ripple waveform of the 20W 5V demo board. The burst ripple voltage is about 30mV.
Channel 1; C1 : Output ripple voltage (Vo)
28mV
Vripple_pk_pk=28mV
Probe terminal end with decoupling capacitor of
0.1uF(ceramic) & 1uF(electrolytic), 20MHz filter
Output ripple voltage @ 85Vac and 1W load
Figure 11
Output ripple during Active Burst Mode at light load
6.3.3 Leaving Active Burst Mode
When the output load increases to be higher than the maximum exit level of burst mode, Vout will drop a little and
VFB will rise up fast to exceed 4.0V. The system leaves burst mode immediately when VFB reaches 4.0V. Once
system leaves burst mode, the current sense voltage limit, Vcsth, is released to 1.06V, the feedback voltage VFBB
swings back to the normal control level.
The leaving burst power threshold is (i.e. maximum power to be handled during burst operation) is expressed in
equation (6). However, the actual power can be higher as it would include propagation delay time.
Pburst_ max  0.5  LP  (
where,
Vcsth _ burst
Rsense
) 2  f SW  0.5  LP  (
Vcsth _ burst Vcsth 2
Vcsth _ burst 2

)  f SW  (
)  Pin _ max
Vcsth
Rsense
Vcsth
(6)
Vcsth _ burst : peak current in the burst mode, Vcsth : maximum current limit threshold at CS pin,
Pin_max : maximum input power, Rsense : current sense resistor, Lp : primary inductance of trf
The leave burst mode timing diagram is shown in Figure 12.
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4.0V
3.5V
V FB
3.2V
Vout Vout_AV
Vout_drop_max
Vcsth
1.06V
V CSth_burst
Figure 12
Vout_drop during leaving burst mode
The maximum output drop during the transition can be estimated in equation (7).
Vout _ drop_ max 
Ropto
0.65  Ropto
3.2  3.5
 (4 
)
RFB  Gopto  GTL431
2
RFB  Gopto  GTL431
(7)
Figure 13 is the captured waveform when there is a load jump from light load to full load. The output ripple drop
during the transition is about 94mV.
Channel 1; C1 : Current sense voltage (VCS)
Channel 2; C2 : Output ripple voltage (Vo)
Channel 3; C3 : FB voltage (VFBB)
94mV
Leaving Active Burst mode when load change from
light to full @ Vin=85Vac
Figure 13
Leaving burst mode waveform
6.3.4 Minimum Vcc supply voltage during burst mode
It is particularly important that the Vcc voltage must stay above VVCCoff (i.e. 10.5V). Otherwise, the expected low
standby power cannot be achieved. The IC will go into auto-restart mode instead. A reference Vcc circuit is
presented in Figure 3. This is for a low cost transformer design where the transformer coupling is not too good.
Thus the circuit R14 and ZD11 is added to clamp the Vcc voltage exceeding 25.5V in extreme case such as
high load and the Vcc OVP protection is triggered. If the transformer coupling is good, this circuit is not needed.
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Functional description and component design
6.3.5 Remarks for the selection of entry/exit burst level
The selection of the entry/exit burst level will depend on the actual application. The below table is the remarks
for the selection.
CFB
≥ 6.8nF
1nF~2.2nF
220pF~470pF
≤100pF
6.4
Remarks
Highest entry/exit burst level: highest burst power, good for larger
standby load. It needs to take care of not having too high loop gain as it
would have a chance of unstable burst mode (rapid entry and exit burst
mode). In case of unstable, the easiest way is to reduce the loop gain by
increasing the opto-coupler biasing resistor, R21. However, too low loop
gain would result to higher output ripple.
2nd highest entry/exit burst level: good for general application. It needs
to take care CS pin noise to be as small as possible as it would have a
chance of unstable burst mode (rapid entry and exit burst mode). In case
of unstable, it is better to add noise filtering capacitor (eg., 100nF
ceramic cap) in between CS(Pin 3) and Gnd (Pin 8). However, adding
filtering cap would increase maximum overload power and widen the
burst mode entry and exit power. Besides, it can also be improved by
reducing the loop gain by increasing the opto-coupler biasing resistor,
R21. However, if the gain is too low, it would result in higher output
ripple.
Lowest entry/exit burst level: good for very small standby load. It needs
to take care CS pin noise to be as small as possible as it would have a
chance of unstable burst mode (rapid entry and exit burst mode). In case
of unstable, it is better to add noise filtering capacitor (eg., 100nF
ceramic cap) in between CS(Pin 3) and Gnd (Pin 8). However, adding
filtering cap would increase maximum overload power and widen the
burst mode entry and exit power. Besides, it can also be improved by
reducing the loop gain by increasing the opto-coupler biasing resistor,
R21. However, if the gain is too low, it would result in higher output
ripple.
Do not enter burst mode: good for application that can accept higher
standby power but with lowest output ripple voltage.
Low EMI noise
6.4.1 Frequency jittering
The IC is running at a fixed frequency of 65kHz or 100kHz with jittering frequency at +/-4% in a switching
modulation period of 4ms. This kind of frequency modulation can effectively help to obtain a low EMI noise level
particularly for conducted EMI. The jittering frequency measured for ICE3AR2280JZ is 92 KHz ~ 100 KHz (refer
to Figure 14).
Channel 1; C1 : Drain voltage (VDrain)
Channel F1 : Frequency track of C1
Frequency jittering from 93 kHz ~ 100 kHz,
Jitter period=4ms
Frequency jittering @ 85Vac and max. load
Figure 14
Frequency jittering ( Vdrain )
Design Guide ICE3xRxx80JZ/VJZ
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Functional description and component design
6.4.2 Soft gate drive and gate turn on resistor
The gate soft driving is to split the gate driving slope into 2 so that the CoolMOS™ turns on speed is relatively
slower comparing to a single slope drive (see Figure 15). Besides soft gate drive, it is also implemented with
50Ω gate turn on resistor. In this way, the high ΔI/Δt noise is greatly reduced and the noise signal reflected in
the EMI spectrum is also reduced.
(internal)
VGate
typ. t = 160ns
4.6V
t
Figure 15
Soft gate drive waveform
6.4.3 Other suggestions to solve EMI issue
Some more suggestions to improve the EMI performance are listed below.
Add capacitor (Cds) at the drain source pin: it can slow down the turn off speed of the MOSFET and the high
ΔV/Δt noise will be reduced and so is the EMI noise. The drawback is more energy will be dissipated due to
slower turn off speed of MOSFET.
Add snubber circuit to the output rectifier: Most of the radiated EMI noise comes out from the output of the
system esp. for a system with output cable. Adding snubber circuit (R28 and C25) to the output rectifier is a
more direct way to suppress those EMI noise (refer to Figure 5).
6.5
Tight control in maximum power - Propagation delay compensation
The maximum power of the system is changed with the input voltage; higher voltage got higher maximum
power. This is due to the propagation delay of the IC and the different rise time of the primary current under
different input voltage. The propagation delay time is around 200ns. But if the primary current rise time is faster,
the maximum power will increase. The power difference can be as high as >14% between high line and low line.
In order to make the maximum power control become tight, a propagation delay compensation network is
implemented so that the power difference is greatly reduced to best around 2%. Figure 13 shows the
compensation scheme of the IC. The equation (8) explains the rate of change of the current sense voltage is
directly proportional to the input voltage and current sense resistor. For a DCM operation, the operating range
for the dVsense/dt is from 0.1 to 0.7. It can show in Figure 13 that higher dVsense/dt will give more compensation;
i.e. lower value of Vsense.
dIp Vin
dIp
Vin
dVsense
Vin

 Rsense 
 Rsense 

 Rsense 
dt
Lp
dt
Lp
dt
Lp
(8)
where, Ip : primary peak current, Vin : input voltage, Lp : primary inductance of the transformer,
Vsense : current sense voltage, Rsense : current sense resistor
The measured maximum input power for the 20W 5V demo board at 85Vac and 282Vac shows ±3.86% of
maximum input power. This function is limited to discontinuous conduction mode flyback converter only.
Note that similar compensation also is applied to burst mode but since the switching pulse duty cycle is
relatively small and the effect is not very obvious.
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Functional description and component design
without compensation
with compensation
V
1,3
1,25
VSense
1,2
1,15
1,1
1,05
1
0,95
0,9
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
dVSense
dt
Figure 16
Propagation delay compensation curve
6.6
Protection Features
2
V
s
Protection is one of the major factors to determine whether the system is safe and robust. Therefore sufficient
protection is necessary. ICE3xRxx80JZ/VJZ provides three kinds of protection mode; odd skip auto restart, non
switch auto restart and normal auto restart. A list of protections and the failure conditions are shown in the
following table.
Protection function
VCC overvoltage(1)
Failure condition
VCC > 20.5V & VFBB > 4.5V & during
soft start period
Protection Mode
Odd skip auto restart
VCC overvoltage(2)
VCC > 25.5V
Odd skip auto restart
Over load/ Open loop
VFBB > 4.5V, after blanking time
Odd skip auto restart
VCC under voltage/ Short
optocoupler
VCC < 10.5V
Normal auto restart
Over temperature
TJ > 130°C ( recovered with 50°C
hysteresis)
Non switch auto restart
External protection enable
VBBA < 0.4V
Non switch auto restart
ICE3xRxx80JZ
ICE3xRxx80VJZ
√
√
√
√
√
√
√
√
√
√
√
-
6.6.1 Odd skip auto restart protection mode
When the failure condition meets the odd skip auto restart protection mode, the IC will enter into odd skip auto
restart. The switching pulse will stop. Then the Vcc voltage will drop. When the Vcc voltage drops to 10.5V, the
startup cell will turn on again. The Vcc voltage is then charged up until 17V. Unlike auto restart mode, there is
no detect of fault and no switching pulse for the first (odd number) restart cycle. At the second (even number) of
restart cycle, the fault detects and soft start switching pulses maintained. If the fault persists, it would continue
the auto-restart mode. However, if the fault is removed, it can release to normal operation only at the even
number auto restart cycle.
The main purpose of the odd skip auto restart is to extend the restart time such that the power loss during auto
restart protection can be reduced. This feature can allow adopting smaller Vcc capacitor where the restart time
is shorter.
Figure 16 shows the odd skip auto restart switching waveform of the Vcc and VCS. No detect of fault and no
switching pulse for the first and odd restart cycle and there are fault detect and soft start switching pulses at the
second and even restart cycle.
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Functional description and component design
VVCC
Fault
detected
No detect
Startup and detect
No detect
17V
10.5V
VCS
t
t
Figure 17
Odd skip auto restart mode
6.6.2 Non switch auto restart mode
Non switch auto restart mode is similar to odd skip auto restart mode except the start up switching pulses are
also suppressed at the even number of the restart cycle. The detection of fault still remains at the even number
of the restart cycle. When the fault is removed, the IC will resume to normal operation at the even number of the
restart cycle (Figure 17).
VVCC
Fault
detected
Startup and detect
No detect
No detect
17V
10.5V
VCS
t
No switching
t
Figure 18
Non switch auto restart mode
6.6.3 Blanking time for over load protection
The IC controller provides a blanking window before entering into the odd skip auto restart mode due to output
overload/short circuit. The purpose is to ensure that the system will not enter protection mode unintentionally.
There are 2 kinds of the blanking time; basic and the extendable. The basic one is a built-in feature which is set
at 20ms.
The extendable one is to extend the basic one with a user defined additional blanking time. The extendable
blanking time can be attained by adding a capacitor, CBK (0.22µF) to the BBA/BV pin. When there is over load
occurred ( VFBB > 4.5V ), the built-in blanking time counter starts to count for 20ms, then extended blanking time
timer (CT1) starts to activate and monitor the counting at CBK capacitor. During extended blanking time, CBK
capacitor is charged by an internal constant current (Ichg_EB =720uA) through S1 until CBK voltage reaches 4.5V
and CT1 timer count will increase by 1, then discharged by switch S2 via 500Ω resistor until CBK voltage
reaches 0.9V. The CT1 timer will count up to 256 times, and then the odd skip auto restart protection will be
activated. The total blanking time is the addition of the basic and the extended blanking time and it can be
calculated by equation (9) and (10).

  (4.5  0.9)  C

BK
tblanking  20ms  256   


I
'
chg _ EB



(4.5  0.9)
I chg _ EB '  720A 
2 * R2
where,

 
   CBK  500  ln( 4.5 )   

 
0.9   


(9)
(10)
R2 : RBO2 for ICE3xRxx80JZ
R2 : ROV2 for ICE3xRxx80VJZ
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Functional description and component design
Blanking time calculation for Figure 5 is as follows,
I chg _ EB '  720A 
where
(4.5  0.9)
 623.6A
2 * RBO 2
RBO 2 =28kΩ

  (4.5  0.9)  C

BK
tblanking_ RBO 2  20ms  256   


I
'
chg _ EB



built-in 20ms blanking
extended blanking

 
   CBK  500  ln( 4.5 )   
  390.4ms
 
0.9   


Channel
Channel
Channel
Channel
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BBA voltage (VBBA)
Total blanking time =415ms (Enable brownout,
RBO2=28kΩ & CBK =0.22µF)
Over load protection with extended blanking time
@ 85Vac
Figure 19
Blanking window for overload protection ( Enable brownout & CBK=0.22uF )
If brownout mode is disable, then no RBO2 and
I chg _ EB '  I chg _ EB  720A

  (4.5  0.9)  CBK  
4.5  
tblanking  20ms  256   
   CBK  500  ln( )    346.9ms
Ichg_EB
0.9  
 


built-in 20ms blanking
extended blanking
Channel
Channel
Channel
Channel
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BBA voltage (VBBA)
Total blanking time =380ms (Disable brownout &
CBK =0.22µF)
Over load protection with extended blanking time
@ 85Vac
Figure 20
Blanking window for overload protection ( Disable brownout & CBK=0.22uF )
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Functional description and component design
Blanking time calculation for Figure 6 is as follows,
I chg _ EB '  720A 
where
(4.5  0.9)
 657.5A
2 * ROV 2
ROV 2 =43.2kΩ

  (4.5  0.9)  C
BK
tblanking_ ROV 2  20ms  256   


I
'
chg _ EB



 
   CBK  500  ln( 4.5 )     373.7ms
 
0.9   


Note: The above calculation does not include the effect of the brownout/input OVP circuit where there is extra
biasing current flowing from the input (bulk capacitor). That means the extended blanking time will be shortened
with the line voltage change if brownout/input OVP circuit is implemented.
In case of output overload or short circuit, the transferred power during the blanking period is limited to the
maximum power defined by the value of the sense resistor Rsense.
The noise level in BBA/BV pin can be quite high particularly in some high power application. In order to avoid
mis-triggering of other protection features, it is recommended to add a minimum 100pF filter capacitor at
BBA/BV pin.
6.6.4 Brownout Mode (ICE3xRxx80JZ only)
When the AC line input voltage is lower than the input voltage range, brownout mode is detected by sensing the
voltage level at BBA pin through the resistors divider from the bulk capacitor. Once the voltage level at BBA pin
falls below 0.9V, the controller stops switching and enters into brownout mode. It is until the input level goes
back to input voltage range and the Vcc hits 17V, the brownout mode is released. Note that there is no
switching waveform but always brownout detect in every restart cycle during brownout mode (Figure 21).
VVCC
Brownout
detected
Startup and detect BBA voltage
17V
10.5V
VCS
t
t
Figure 21
Brownout detection circuit and the waveform
Brownout sensing resistor RBO1 and RBO2 can be calculated as below.
RBO1 
RBO 2 
V BO _ hys
(11)
I chg _ BO
VBO _ ref  RBO1
(12)
VBO _ L  VBO _ ref
where,
VBO_hys
: input brownout hysteresis voltage
Ichg_BO = 10µA
: charging current for brownout
VBO_ref = 0.9V
: brownout reference voltage for IC
VBO_L
: input brownout voltage (low point)
RBO1 and RBO2
: resistors divider from input voltage to BBA pin
For example, if brownout release voltage is 85Vac and entry voltage is 75Vac and assuming there is a ripple
voltage of 14Vdc at the bulk capacitor before entering brownout at full load.
VBO _ H  85  2  120Vdc
VBO _ L  75  2  14  92Vdc
VBO _ hys  VBO _ H  VBO _ L  28Vdc
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Functional description and component design
RBO1 
VBO _ hys
I chg _ BO
 2.8M
RBO 2 
,
VBO _ ref  RBO1
VBO _ L  VBO _ ref
 28k
(Note: RBO2 must be always ≥15kΩ in enable brownout mode, otherwise overload protection may not
work)
105Vdc
22.6Vdc
22.6Vdc
120Vdc
Channel
Channel
Channel
Channel
1; C1 : Bulk voltage(Vbulk)
2; C2 : Supply voltage (VCC)
3; C3 : Current sense voltage (VCS)
4; C4 : BBA voltage (VBBA)
IC on & 1st detect brownout: Vbulk= 22.6Vdc (16Vac)
Brownout reset: Vbulk= 120Vdc (85Vac)
Brownout triggered: Vbulk= 105Vdc (74Vac)
IC off: Vbulk= 22.6Vdc (16Vac)
Brownout mode with max. load
Figure 22
Brownout mode waveform
The above calculation assumes the tapping point (bulk capacitor) has a 14Vdc ripple voltage at full load when
entering brownout mode. If there is no ripple voltage at light load, the enter brownout point will be lower, 65Vac.
Besides that the low side brownout voltage VBO_L added with the ripple voltage at the tapping point should always
be lower than the high side brownout voltage (VBO_H); VBO_H > VBO_L + ripple voltage. Otherwise, the brownout
feature cannot work properly. In short, when there is a high load running in system before entering brownout,
the input ripple voltage will increase and the brownout voltage will increase (VBO_L = VBO_L+ ripple voltage) at the
same time. If the VBO_hys is set too small and is close to the ripple voltage, then the brownout feature cannot work
properly (VBO_L = VBO_H).
If the brownout feature is not needed, it needs to tie the BBA pin to the Vcc pin through a current limiting resistor
(R17), 500kΩ~1ΜΩ. The BBA pin cannot be in floating condition. If the brownout feature is disabled with a tie up
resistor, there is a limitation of the capacitor CBK (C18) at the BBA pin. It is as below.
1
2
Design Guide ICE3xRxx80JZ/VJZ
Vcc tie up resistor
500kΩ
1MΩ
23
CBK_max
0.47µF
0.22µF
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Functional description and component design
6.6.5 Line input over voltage protection (ICE3xRxx80VJZ only)
The input OVP mode is detected by sensing the voltage level at BV pin through the resistors divider from the
bulk capacitor. Once the voltage level at BV pin hits above 1.98V, the controller stops switching and enters into
input OVP mode. When the BV voltage drop to 1.91V and the Vcc hits 17V, the input OVP mode is released.
Input OVP sensing resistors ROV1 and ROV2 can be calculated as below.
Figure 2 – Input OVP circuit and the waveform
ROV 2 
where
ROV 1 VOVP _ ref
(13)
VOVP  VOVP _ ref
VOVP
VOVP_ref
VOVP_hys
ROV1 & ROV2
: input over voltage
: IC reference voltage for OVP (1.98V)
: IC hysteresis voltage for OVP (0.07V)
: resistors divider from input voltage to BV pin
The formula to calculate the input OVP reset voltage is as below.
VOVP _ reset 
where
VOVP_reset
(VOVP _ ref  VOVP _ hys )  ( ROV 1  ROV 2 )
ROV 2
(14)
: input OVP reset voltage
For example, if input OVP detect level is 300Vac (424.26Vdc) and ROV1=9MΩ
ROV 2 
9 M  1.98
 42.2k
424.26  1.91
VOVP _ reset 
(1.98  0.07)  (9 M  42.2k )
 409.2Vdc (289Vac )
42.2k
To disable the input OVP mode, the BV pin must connect with a resistor ROV2≥15kΩ to the IC ground and
remove ROV1.
(Note: ROV2 must be always ≥15kΩ in all conditions, otherwise overload protection may not
work)
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Input power curve
6.6.6 External protection enable (ICE3xRxx80JZ only)
Although there are lots of pre-defined Auto Restart Protection is implemented in the IC, customer still can have
some tailor-made protection for the application needs by pulling down the BBA pin to lower 0.4V. When BBA pin
is lower than 0.4V, the gate drive switching will be stopped and IC will enter to non switch auto restart mode
until the external protection enable signal released.
Figure 23
User defined external protection enable circuit
7
Input power curve
The purpose of the input power curve is to simplify the selection of the CoolSET™ device. The curve is a
function of ambient temperature to the input power of the system in which the input filter loss, bridge rectifier
loss and the MOSFET power loss are considered. The only information needed is the required output power,
the input voltage range, the operating ambient temperature and the efficiency of the system. The required input
power can then be calculated as equation (14).
Pin 
Po
(15)

where Pin : input power, Po : output power, η : efficiency
It then simply looks up the closed input power at the required ambient temperature from the input power curve.
The input power curves for the CoolSET-F3R80 (DIP-7) family are listed below.
ICE3xR0680JZ/VJZ : Vin=85Vac~265Vac
Figure 24
ICE3xR0680JZ/VJZ : Vin=230Vac±15%
Input power curve for ICE3xR0680JZ/VJZ
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Layout Recommendation
ICE3xR2280JZ/VJZ : Vin=85Vac~265Vac
Figure 25
Input power curve for ICE3xR2280JZ/VJZ
ICE3AR4780JZ/VJZ : Vin=85Vac~265Vac
Figure 26
ICE3xR2280JZ/VJZ : Vin=230Vac±15%
ICE3AR4780JZ/VJZ : Vin=230Vac±15%
Input power curve for ICE3AR4780JZ/VJZ
The major assumption for the calculation is listed below.
Reflection voltage from secondary side to primary side is 150V.
The assumed maximum power for the device is when the junction temperature of the integrated CoolMOS™
reaches 125°C. (With some margins to reach the over temperature protection of the device : 130°C). The
maximum Rdson of the device at 125°C is taken for calculation.
There is no copper area as heatsink and the Rthja=96K/W (DIP-7)
Saturation current (Id_max @ 125°C) of the MOSFET is considered which is showed in below table.
The typical resistance of the EMI filter is listed in the below table.
The voltage drop for the bridge rectifier is assumed to be 1V.
8
Rdson_125°C (Ω)
Id_max @125°C (A)
REMI_filter (Ω)
VF_bridge (V)
ICE3xR0680JZ/VJZ
1.58
12.60
2 * 0.56
2*1
ICE3xR2280JZ/VJZ
5.80
2.87
2*2
2*1
ICE3AR4780JZ/VJZ
11.50
1.45
2*3
2*1
Layout Recommendation
Design Guide ICE3xRxx80JZ/VJZ
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Product portfolio of CoolSET™ F3R80 (DIP-7) brownout/input OVP & frequency jitter version
In order to get the optimized ruggedness of the IC to the transient surge events like ESD and lightning Surge
test, the grounding of the PCB layout must be connected carefully. From the circuit diagram in Figure 5, it
indicates that the grounding for the controller can be split into several groups; signal ground, Vcc ground,
Current sense resistor ground and EMI return ground. All the split grounds should be “star” connected to the
bulk capacitor ground directly. The split grounds are described as below.
Signal ground includes all small signal grounds connecting to the controller GND pin such as filter capacitor
ground, C17, C18, C19 and opto-coupler ground.
Vcc ground includes the Vcc capacitor ground, C16 and the auxiliary winding ground, pin 2 of the power
transformer.
Current Sense resistor ground includes current sense resistor R15 and R16.
EMI return ground includes Y capacitor, C15.
Product portfolio of CoolSET™ F3R80 (DIP-7) brownout/input
OVP & frequency jitter version
9
1
Frequency / kHz
Rdson /Ω
1
2
Device
Package
VDS
230Vac±15%
85-265Vax±15%
ICE3AR4780JZ/VJZ
PG-DIP-7
800V
100
4.70
31W
20W
ICE3AR2280JZ/VJZ
PG-DIP-7
800V
100
2.26
43W
28W
ICE3AR0680JZ/VJZ
PG-DIP-7
800V
100
0.62
82W
52W
ICE3BR2280JZ
PG-DIP-7
800V
65
2.26
43W
28W
ICE3BR0680JZ
PG-DIP-7
800V
65
0.62
82W
52W
2
Typ @ 25°C
2
Calculated maximum input power rating at Ta=50°C, Tj=125°C and without copper area as heat sink. Refer to
the data sheet for input power curve of other Ta
Design Guide ICE3xRxx80JZ/VJZ
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Useful formula for the SMPS design
10
Useful formula for the SMPS design
Transformer calculation ( DCM flyback)
,
,
Input data
Turn ratio
Maximum Duty ratio
Primary Inductance
Primary peak current
I p _ max 
Primary turns
N p
Secondary turns
Ns 
Auxiliary turns
N aux 
VDC _ min  Dmax
Lp  f s
I p _ max  Lp
Bmax  Ae
Np
N ratio
Vcc  VFDiode
 Ns
V outVFDiode
ICE3xRxx80JZ/VJZ external component Design
Vcsth
I p _ max
Current sense resistor
Rsense 
Soft start time
t ss  10ms
Vcc capacitor
CVCC 
Startup time
IVCC sup2  t ss
t STARTUP 
Design Guide ICE3xRxx80JZ/VJZ
VVCChys

2
3
VVCCon  CVcc
IVCCch arg e
28
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Useful formula for the SMPS design
Enter burst mode power
PBURST _ enter  0.5  LP  (
Leave burst mode power
Pburst_ max  0.5  LP  (
Output ripple during burst
mode
Vout _ ripple_ pp 
Voltage drop when leave
burst mode
Vout _ drop_ max 
VFB _ burst  VOffset  Ramp
Rsense  AV
Vcsth _ burst
Rsense
)2  f SW
) 2  f SW
Ropto
RFB  Gopto  GTL 431
 VFB
0.65  Ropto
RFB  Gopto  GTL 431
ICE3xRxx80JZ external component Design
Total blanking time for over
load protection (Disable
brownout)

  (4.5  0.9)  CBK  
4.5  
tblanking  20ms  256   
)  
   CBK  500  ln(
Ichg_EB
0.9  
 


New charging current for
extended blanking time with
RBO2
I chg _ EB '  720A 
Total blanking time for over
load protection with RB02
(Enable brownout)

  (4.5  0.9)  C

BK
tblanking_ RBO 2  20ms  256   


I
'
chg _ EB



Brownout resistor 1, RBO1
RBO1 
Brownout resistor 2, RBO2
RBO 2 
VBO _ hys
I chg _ BO
(4.5  0.9)
2 * RBO 2
where

 
   C BK  500  ln( 4.5 )  

 
0.9  


VBO _ hys  VBO _ H  VBO _ L
VBO _ ref  RBO1
VBO _ L  VBO _ ref
(Note: RBO2 must be always ≥15kΩ in enable brownout mode, otherwise overload protection
may not work)
ICE3xRxx80VJZ external component Design
(4.5  0.9)
2 * ROV 2
Charging
current
for
extended blanking time with
ROV2
I chg _ EB '  720A 
Total blanking time for over
load protection with R0V2

  (4.5  0.9)  C

BK
tblanking_ ROV 2  20ms  256   


I
'
chg _ EB



ROV 2 
Input OVP resistors, ROV1 &
ROV1

 
   CBK  500  ln( 4.5 )   

 
0.9   


ROV 1  VOVP _ ref
VOVP  VOVP _ ref
Note: R OV2 must be always ≥15kΩ in all conditions, otherwise overload protection may not
work
Minimum current at R OV1 should be higher than 5µA to avoid malfunction
OVP reset voltage
VOVP _ reset 
Design Guide ICE3xRxx80JZ/VJZ
(VOVP _ ref  VOVP _ hys )  ( ROV 1  ROV 2 )
ROV 2
29
V1.5, 2013-09-09
ICE3xRxx80JZ/VJZ Design Guide
AN-PS0044
References
11
References
[1]
Infineon Technologies, Datasheet “CoolSET™-F3R80 ICE3AR0680JZ Off-Line SMPS Current Mode
Controller with Integrated 800V CoolMOS™ and Startup Cell ( Brownout & frequency Jitter) in DIP-7”
[2]
Infineon Technologies, Datasheet “CoolSET™-F3R80 ICE3AR2280JZ Off-Line SMPS Current Mode
Controller with Integrated 800V CoolMOS™ and Startup Cell ( Brownout & frequency Jitter) in DIP-7”
[3]
Infineon Technologies, Datasheet “CoolSET™-F3R80 ICE3AR4780JZ Off-Line SMPS Current Mode
Controller with Integrated 800V CoolMOS™ and Startup Cell ( Brownout & frequency Jitter) in DIP-7”
[4]
Infineon Technologies, Datasheet “CoolSET™-F3R80 ICE3BR0680JZ Off-Line SMPS Current Mode
Controller with Integrated 800V CoolMOS™ and Startup Cell ( Brownout & frequency Jitter) in DIP-7”
[5]
Infineon Technologies, Datasheet “CoolSET™-F3R80 ICE3BR2280JZ Off-Line SMPS Current Mode
Controller with Integrated 800V CoolMOS™ and Startup Cell ( Brownout & frequency Jitter) in DIP-7”
[6]
Infineon Technologies, Datasheet “CoolSET™-F3R80 ICE3AR0680VJZ Off-Line SMPS Current Mode
Controller with Integrated 800V CoolMOS™ and Startup Cell ( Input OVP & frequency Jitter) in DIP-7”
[7]
Kyaw Zin Min, Kok Siu Kam Eric, Infineon Technologies, Application Note “AN-EVALSF3R80ICE3AR0680JZ, 30W 12V SMPS Evaluation Board with CoolSET™-F3R80 ICE3AR0680JZ”
[8]
Kyaw Zin Min, Kok Siu Kam Eric, Infineon Technologies, Application Note “AN-EVALSF3R80ICE3AR2280JZ, 20W 5V SMPS Evaluation Board with CoolSET™-F3R80 ICE3AR2280JZ”
[9]
Kyaw Zin Min, Kok Siu Kam Eric, Infineon Technologies, Application Note “AN-EVALSF3R80ICE3AR4780JZ, 12W 5V SMPS Evaluation Board with CoolSET™-F3R80 ICE3AR4780JZ”
[10] Infineon Technologies, Application Note ANPS0079 “AN-EVAL-3AR0680VJZ, 30W 12V SMPS Evaluation
Board with ICE3AR0680VJZ”
Design Guide ICE3xRxx80JZ/VJZ
30
V1.5, 2013-09-09
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