Coolset F3R80CCM DIP7 brownout & CCM version Design Guide V1.3_18Sep2012

Application Note, V1. 4, Sep 2012
I CE 3 A R xx8 0 C J Z
CoolSET® F3R80CCM (DIP-7) brownout &
CCM version Design Guide
Power Management & Supply
N e v e r
s t o p
t h i n k i n g .
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2012 Infineon Technologies AG
All Rights Reserved.
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ICE3ARxx80CJZ
Revision History:
Previous Version:
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20
2012-09
V1.4
1.3
Subjects (major changes since last revision)
typo error
CoolSET® F3R80CCM (DIP-7) brownout & CCM version Design Guide:
License to Infineon Technologies Asia Pacific Pte Ltd
Kyaw Zin Min
Wang Zan
Kok Siu Kam Eric
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ICE3ARxx80CJZ
Table of Contents
Page
1
Introduction .............................................................................................................................. 5
2
List of Features ........................................................................................................................ 5
3
Package .................................................................................................................................... 5
4
Block Diagram .......................................................................................................................... 6
5
Typical Application Circuit ...................................................................................................... 7
6
6.1
6.1.1
6.2
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.4
6.4.1
6.4.2
6.4.3
6.5
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.6
Functional description and component design ...................................................................... 8
Startup time ............................................................................................................................... 8
Vcc capacitor ............................................................................................................................. 8
Soft Start .................................................................................................................................... 9
Low standby power - Active Burst Mode ..................................................................................... 9
Entering Active Burst Mode with selectable burst entry level ....................................................... 9
Working in Active Burst Mode................................................................................................... 11
Leaving Active Burst Mode ....................................................................................................... 12
Minimum VCC supply voltage during burst mode ....................................................................... 13
Remarks for the selection of entry/exit burst level ..................................................................... 13
Low EMI noise ......................................................................................................................... 14
Frequency jittering.................................................................................................................... 14
Soft gate drive and gate turn on resistor ................................................................................... 14
Other suggestions to solve EMI issue ....................................................................................... 14
Tight control in maximum power – (Combined OPP curve considering propagation delay & slope
compensation) ......................................................................................................................... 15
Protection Features .................................................................................................................. 16
Odd skip auto restart protection mode ...................................................................................... 16
Non switch auto restart mode ................................................................................................... 16
Blanking Time for over load protection ...................................................................................... 17
Brownout Mode ........................................................................................................................ 17
User defined protection by latch enable (BRL) pin .................................................................... 19
Fast AC reset ........................................................................................................................... 20
7
Input power curve .................................................................................................................. 21
8
Layout Recommendation ....................................................................................................... 22
9
Product portfolio of CoolSET F3R80CCM (DIP-7) brownout & CCM version .................... 22
10
Useful formula for the SMPS design ..................................................................................... 23
11
Design calculation example................................................................................................... 25
12
References ............................................................................................................................. 28
13
Appendix 1 – reference circuit to solve output OVP by external voltage short .................. 29
®
Application Note
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ICE3ARxx80CJZ
1
Introduction
The CoolSET®-F3R80CCM, ICE3ARxx80CJZ is the latest development of the CoolSET® in continuous
conduction mode (CCM) operation. It is a PWM controller with power MOSFET and startup cell in a DIP-7
package. The switching frequency is running at 100 kHz and it targets for DVD player, set-top box, portable
game console, white goods, auxiliary power supply for server/PC, etc.
The ICE3ARxx80CJZ adopts the BiCMOS technology and provides a wider Vcc operating range up to
®
24.7V. It inherits the proven good features of CoolSET -F3R such as Active Burst Mode, propagation delay
compensation, soft gate drive, auto restart protection for major faults (Vcc over voltage, over load, open loop
Vcc under voltage, short optocoupler and over temperature), it also has the selectable entry and exit burst
mode level, brownout feature, built-in soft start time, built-in blanking time for short duration peak power,
frequency jitter feature, slope compensation for CCM operation, external latch enable and fast AC reset, etc.
The particular features need to be stressed are 800V MOSFET, CCM/DCM operation, fixed voltage
Brownout detect/reset, fast AC reset, the best-in-class low standby power and the good EMI performance.
2
List of Features
800V avalanche rugged CoolMOS® with Startup Cell
Active Burst Mode for lowest Standby Power
Slope compensation for CCM operation
Selectable entry and exit burst mode level
100kHz internally fixed switching frequency with jittering feature
Auto Restart Protection for Over load, Open Loop, VCC Under/Over voltage and Over temperature
External latch enable pin and fast AC reset
Over temperature protection with 50°C hysteresis
Built-in 10ms Soft Start
Built-in 40ms blanking time for short duration peak power
Propagation delay compensation for both maximum load and burst mode
Brownout feature
BiCMOS technology for low power consumption and wide VCC voltage range
Soft gate drive with 50Ω turn on resistor
3
Package
The package for F3R80CCM ICE3ARxx80CJZ brownout and frequency jitter mode product is DIP-7.
Figure 1
Pin configuration
Application Note
Pin
Name
1
BRL
Brownout, fast AC Reset & Latch enable
2
FBB
Feedback & Burst entry/exit control
3
CS
Current Sense/800V CoolMOS Source
4
n.c
not connected
5
Drain
6
-
7
VCC
Controller Supply Voltage
8
GND
Controller Ground
5
Description
®
®
800V CoolMOS Drain
(no pin)
2012-09-27
ICE3ARxx80CJZ
4
Block Diagram
Figure 2
Application Note
Block Diagram of ICE3ARxx80CJZ
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ICE3ARxx80CJZ
5
Typical Application Circuit
(circuit with output OVP latch, brownout and fast AC reset features, etc.)
Figure 3
Application Note
Typical application circuit with ICE3AR10080CJZ 10W 5V
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6
Functional description and component design
6.1
Startup time
Startup time is counted from applying input voltage to IC turn on. ICE3ARxx80CJZ has a startup cell which is
connected to input bulk capacitor. When there is input voltage, the startup cell will act as a constant current
source to charge up the Vcc capacitor and supply energy to the IC. When the Vcc capacitor reaches the
Vcc_on threshold 17V, the IC turns on. Then the startup cell is turned off and the Vcc is supplied by the
auxiliary winding. Start up time is independent from the AC line input voltage and it can be calculated by the
equation (1). Figure 4 shows the start up time of 85Vac line input.
where, IVCCcharge
: average current of IVCCcharge2 and IVCCcharge3 ( 0.875mA ),
VVCCon
: IC turns on threshold ( 17V ),
CVCC
: Vcc capacitor
Please refer to the datasheet for the symbol used in the equation.
250ms
Channel
Channel
Channel
Channel
1; C1 : Drain voltage (VD)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BRL voltage (VBRL)
Measured startup time = 0.25s
Entry/exit burst
selection (Level 2)
Startup @ 85Vac & max. load
Figure 4
The startup delay time at AC line input voltage of 85Vac
Pre-caution : For a typical application, start up should be VCC ramps up first, other pin (such as FBB pin)
voltage will follow VCC voltage to ramp up. It is recommended not to have any voltage on other
pins (such as FBB; BRL and CS) before VCC ramps up.
In addition, the dummy load in the Vcc pin should be larger than 150KΩ. Otherwise, it would
have a risk of delay startup.
6.1.1 Vcc capacitor
The minimum value of the Vcc capacitor is determined by voltage drop during the soft start time. The formula
is expressed in equation (2).
where, IVCCsup2_max
tss
VCChys
Application Note
: supply current with active gate ( 4.8mA for ICE3AR10080CJZ)
: soft start time ( 10ms )
: Vcc turn-on/off hysteresis voltage ( 6.5V )
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ICE3ARxx80CJZ
Therefore, the minimum Vcc capacitance can be 4.9μF. In order to give more margins, 10uF is taken for the
design. The startup time tStartUp is then 0.19s. The measured start up time is 0.25s (Figure 4). A 0.1uF filtering
capacitor is always needed to add as near as possible to the Vcc pin to filter the high frequency noise.
6.2
Soft Start
When the IC is turned on after the startup time, a digital soft start circuit is activated. A gradually(32 steps)
increased soft start voltage is emitted by the digital soft start circuit, which in turn releases the duty cycle
gradually increase from zero. The duty cycle increases to maximum (which is limited by the transformer
design) at the end of the soft start period. When the soft start time ends, IC goes into normal mode and the
duty cycle is controlled by the FB signal. The soft start time is set at 10ms for maximum load. The soft start
time is load dependent; shorter soft start time with lighter load.
Figure 5 shows the soft start behavior at 85Vac input and maximum load. The primary peak current
increases slowly to the maximum in the soft start period.
9.5ms
Channel
Channel
Channel
Channel
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BRL voltage (VBRL)
Soft Start time = 9.5ms(32 steps)
Soft start @ Vin=85Vac & max. load
Figure 5
6.3
Soft start at AC line input voltage of 85 Vac & full load
Low standby power - Active Burst Mode
The IC will enter Active Burst Mode function at light load condition which enables the system to achieve the
lowest standby power requirement of less than 100mW. Active Burst Mode means the IC is always in the
active state and can therefore immediately response to any changes on the FB signal, VFB.
6.3.1 Entering Active Burst Mode with selectable burst entry level
Because of the current mode control scheme, the feedback voltage VFB actually controls the power delivery
to output. An important relationship between the VCS and the VFB is expressed in equation (3).
VFB  (VMc  Vcs )  Av  VOffset  Ramp  ( M C  ton  Rcs  Ip )  Av  VOffset  Ramp
where, VCS
AV
VOffset-Ramp
:current sense voltage
:PWM OP gain (3.25)
:voltage ramp offset (0.6V)
MC
:slope compensation rate (50mV/µs)
ton
:switch on time
Rcs
Ip
:current sense resistor
Application Note
(3)
:transformer primary current
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ICE3ARxx80CJZ
When the output load reduces, the feedback voltage VFB drops. If the VFB stays below VFB_burst for 20ms, the
IC enters into the Active Burst Mode. The threshold power to enter burst mode is expressed in equation (4).
where, Lp
: transformer primary inductance
IP _ burst : transformer primary current to enter burst mode
fs
where,
: switching frequency
Vdc
VFB_burst
:dc input voltage
: feedback level to enter burst mode
Figure 6
Burst mode detect and adjust
®
In enhancement to CoolSET -F3R, user can select the burst mode entry and exit level in CoolSET® F3R80CCM, according to the application by adding different values of Rsel (R113) resistor at FBB pin. The IC
would detect the voltage level at the FBB pin within the VCC charging time from 8V to 17V. During that
detection time, the current source Isel (3.5µA) current will charge the Rsel (R113) resistor. Based on the
voltage level, the IC will select burst mode entry and exit level. There are 3 different levels of burst mode
available and the following table is the recommended resistance range of the Rsel (R113) resistor for the
entry and exit burst level.
Entry level
Level
Rsel
VFBB
1
2
3
<405kΩ
685kΩ~900kΩ
>1530kΩ
VFBB < Vref1 (1.8V)
Vref1 (1.8V) <VFBB < Vref2 (4V)
VFBB > Vref2 (4V)
% of Pin_max
5%
10%
15%
VFB_burst
1.29V
1.61V
1.84V
Exit level
% of Pin_max
11%
20%
27%
Vcsth_burst
0.21V
0.29V
0.34V
Figure 7 shows the waveform with the load drops from nominal load to light load. After the 20ms blanking
time IC goes into burst mode.
Application Note
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ICE3ARxx80CJZ
Channel
Channel
Channel
Channel
19ms
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BRL voltage (VBRL)
Entering Active Burst mode with built-in blanking
time 20ms when load changes from full to light @
Vin=85Vac
Figure 7
Entering active burst mode
6.3.2 Working in Active Burst Mode
In the active burst mode, the IC is constantly monitoring the output voltage by feedback pin, VFBB, which
controls burst duty cycle and burst frequency. The burst “ON” starts when VFB reaches 3.5V and it stops
when VFB is dropped to 3.2V. During burst “ON”, the primary current limit is reduced to Vcsth_burst ( 27% ~ 44%
of maximum peak current ) to reduce the conduction losses and to avoid audible noise. The FB voltage is
swinging like a saw tooth between 3.2V and 3.5V. The corresponding secondary output ripple (peak to peak)
is controlled to be small. It can be calculated by equation (6).
where, Ropto
Rfb
Gopto
GTL431
:series resistor with opto-coupler at secondary side (e.g. R22 in Figure 3)
:IC internal pull up resistor connected to FB pin (Rfb=15.4KΩ)
:current transfer gain of opto-coupler
:voltage transfer gain of the loop compensation network (e.g. R22, R211, R24,
R25, R26, R27, C25, C26 in Figure 3)
Vfb
: feedback voltage change (0.3V)
Figure 8 is the output ripple waveform of the 10W 5V demo board. The burst ripple voltage is about 19mV.
Channel 1; C1 : Output ripple voltage (Vo)
Channel 2; C2 : Output current (Io)
Vripple_pk_pk=19mV
Probe terminal end with decoupling capacitor of
0.1uF(ceramic) & 1uF(electrolytic), 20MHz filter
Output ripple voltage @ 85Vac and 1W load
Figure 8
Application Note
Output ripple during Active Burst Mode at light load
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6.3.3 Leaving Active Burst Mode
When the output load increases to be higher than the maximum exit level of burst mode, Vout will drop a little
and VFB will rise up fast to exceed 4.0V. The system leaves burst mode immediately when VFB reaches 4.0V.
Once system leaves burst mode, the current sense voltage limit is set to Vcsth1 or Vcsth2 according the input
AC line voltage, the feedback voltage VFBB swings back to the normal control level.
The leaving burst power threshold (i.e. maximum power to be handled during burst operation) is expressed
in equation (7). However, the actual power can be higher as it would include propagation delay time.
where, Vcsth _ burst
: peak current in the burst mode
Vcsth
: maximum current limit threshold at CS pin
Pin_max
: maximum input power
RCS
: current sense resistor
Lp
: primary inductance of transformer
The leave burst mode timing diagram is shown in Figure 9.
4.0V
3.5V
V FB
3.2V
Vout Vout_AV
Vout_drop_max
Vcsth
V CSth_burst
Figure 9
Vout_drop during leaving burst mode
The maximum output drop during the transition can be estimated in equation (8).
Figure 10 is the captured waveform when there is a load jump from light load to full load. The output ripple
drop during the transition is about 71mV.
Application Note
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ICE3ARxx80CJZ
Channel 1; C1 : Current sense voltage (VCS)
Channel 3; C3 : FB voltage (VFBB)
Channel 4; C4 : Output ripple voltage (Vo)
71mV
Leaving Active Burst mode when load change from
light to full @ Vin=85Vac
Figure 10
Leaving burst mode waveform
6.3.4 Minimum VCC supply voltage during burst mode
It is particularly important that the Vcc voltage must stay above VVCCoff (i.e. 10.5V). Otherwise, the expected
low standby power cannot be achieved. The IC will go into auto-restart mode instead. A reference Vcc circuit
is presented in Figure 3. This is for a low cost transformer design where the transformer coupling is not too
good. Thus the circuit R13 and ZD11 is added to clamp the Vcc voltage exceeding 25.5V in extreme case
such as high load and the Vcc OVP protection is triggered. If the transformer coupling is good, this circuit is
not needed.
6.3.5 Remarks for the selection of entry/exit burst level
The selection of the entry/exit burst level will depend on the actual application. The below table is the
remarks for the selection.
Rsel
<405kΩ
685kΩ<900kΩ
>1530kΩ
Application Note
Remarks
Lowest entry/exit burst level: good for very small standby load. It needs
to take care CS pin noise to be as small as possible as it would have a
chance of unstable burst mode (rapid entry and exit burst mode). In case
of unstable, it is better to add noise filtering capacitor (e.g., 100nF
ceramic cap) in between CS (pin 3) and Gnd (pin 8). However, adding
filtering cap would increase maximum overload power and widen the
burst mode entry and exit power. Besides, it can also be improved by
reducing the loop gain by increasing the opto-coupler biasing resistor,
R22. However, if the gain is too low, it would result in higher output
ripple.
2nd highest entry/exit burst level: good for general application. It needs
to take care CS pin noise to be as small as possible as it would have a
chance of unstable burst mode (rapid entry and exit burst mode). In case
of unstable, it is better to add noise filtering capacitor (e.g., 100nF
ceramic cap) in between CS (pin 3) and Gnd (pin 8). However, adding
filtering cap would increase maximum overload power and widen the
burst mode entry and exit power. Besides, it can also be improved by
reducing the loop gain by increasing the opto-coupler biasing resistor,
R22. However, if the gain is too low, it would result in higher output
ripple.
Highest entry/exit burst level: highest burst power, good for larger
standby load. It needs to take care of not having too high loop gain as it
would have a chance of unstable burst mode (rapid entry and exit burst
mode). In case of unstable, the easiest way is to reduce the loop gain by
increasing the opto-coupler biasing resistor, R22. However, too low loop
gain would result to higher output ripple.
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ICE3ARxx80CJZ
6.4
Low EMI noise
6.4.1 Frequency jittering
The IC is running at a fixed frequency of 100kHz with jittering frequency at +/-4% in a switching modulation
period of 4ms. This kind of frequency modulation can effectively help to obtain a low EMI noise level
particularly for conducted EMI. The jittering frequency measured for ICE3AR10080CJZ is 96 KHz ~ 104 KHz
(refer to Figure 11).
Channel 1; C1 : Drain voltage (VD)
102kHz
3.8ms
Frequency jittering from 95 kHz ~ 102 kHz,
95kHz
Frequency jittering @ 85Vac and max. load
Figure 11
Switching frequency jittering
6.4.2 Soft gate drive and gate turn on resistor
The gate soft driving is to split the gate driving slope into two, so that the CoolMOS® turns on speed is
relatively slower comparing to a single slope drive (see Figure 12). Besides soft gate drive, it is also
implemented with 50Ω gate turn on resistor. In this way, the high ΔI/Δt noise is greatly reduced and the noise
signal reflected in the EMI spectrum is also reduced.
(internal)
VGate
typ. t = 160ns
4.6V
t
Figure 12
Soft gate drive waveform
6.4.3 Other suggestions to solve EMI issue
Some more suggestions to improve the EMI performance are listed below.
1. Add RCD clamper circuit to the primary winding of the transformer: RCD clamper circuit (D11, R11 &
C15) can absorb the current due to leakage inductance of transformer during switch off time of the
MOSFET, so voltage spike of the drain can clamp to desired voltage level and suppress the EMI
noise (refer to Figure 3).
2. Add capacitor (CDS) at the drain source pin: CDS (C110) can slow down the turn off speed of the
MOSFET and the high ΔV/Δt noise will be reduced and so is the EMI noise. The drawback is more
energy will be dissipated due to slower turn off speed of MOSFET (refer to Figure 3).
3. Add snubber circuit to the output rectifier: Most of the radiated EMI noise comes out from the output
of the system especially for a system with output cable. Adding snubber circuit (R21 and C21) to the
output rectifier is a more direct way to suppress those EMI noise (refer to Figure 3).
Application Note
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ICE3ARxx80CJZ
4. Reduce the reflection voltage: if the secondary to primary reflection voltage is reduced, the
switching voltage at drain can also be reduced. Hence the voltage switching noise is reduced and so
is the EMI noise. The drawback is the reverse voltage of the secondary rectifier will increase.
6.5
Tight control in maximum power – (Combined OPP curve considering
propagation delay & slope compensation)
The maximum power of the system is changed with the different AC line input voltage, the higher the input
AC line voltage, the higher the maximum power and vice versa. This is due to the propagation delay of the IC
for DCM converters and the propagation delay plus CCM characteristic for CCM converters. In this
ICE3ARxx80CJZ, two different types of compensation have implemented to reduce maximum power
difference between low and high line. One is for switch on time lower than 4µs (DCM) and the other one is
for switch on time higher than 4µs (CCM). The propagation delay compensation is realized by means of a
dynamic threshold voltage. In case of a steeper slope, the switch off time of the driver is earlier to
compensate the delay.
Figure 13
Propagation delay compensation curve
Figure 14
Application Note
Dynamic voltage threshold
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ICE3ARxx80CJZ
6.6
Protection Features
Protection is one of the major factors to determine whether the system is safe and robust. Therefore
sufficient protection is necessary. ICE3ARxx80CJZ provides two kinds of protection mode; odd skip auto
restart mode and non switch auto restart mode. A list of protections and the failure conditions are shown in
the following table.
Protection function
Failure condition
Protection Mode
VCC over voltage
VCC > 25.5V & last for 120µs
Odd skip auto restart
Over load
VFBB > 4.5V & 40ms blanking time
Odd skip auto restart
Open loop
Same as over load
Odd skip auto restart
VCC under voltage
VCC < 10.5V
Normal auto restart
Short opto-coupler
-> VCC under voltage
Normal auto restart
Over temperature (controller
junction)
TJ > 130°C ( recovered with 50°C hysteresis)
Non switch Auto restart
External protection enable
VBRL < 0.4V & last for 210 µs
Latch
6.6.1 Odd skip auto restart protection mode
When the failure condition meets the odd skip auto restart protection mode, the IC will enter into odd skip
auto restart. The switching pulse will stop. Then the Vcc voltage will drop. When the Vcc voltage drops to
10.5V, the startup cell will turn on again. The Vcc voltage is then charged up until 17V. Unlike auto restart
mode, there is no detect of fault and no switching pulse for the first (odd number) restart cycle. At the second
(even number) of restart cycle, the fault detects and soft start switching pulses maintained. If the fault
persists, it would continue the auto-restart mode. However, if the fault is removed, it can release to normal
operation only at the even number auto restart cycle.
The main purpose of the odd skip auto restart is to extend the restart time such that the power loss during
auto restart protection can be reduced. This feature can allow adopting smaller VCC capacitor where the
restart time is shorter.
Figure 15 shows the odd skip auto restart switching waveform of the VCC and VCS. No detect of fault and no
switching pulse for the first and odd restart cycle and there are fault detect and soft start switching pulses at
the second and even restart cycle.
VVCC
Fault
detected
No detect
Startup and detect
No detect
17V
10.5V
VCS
t
t
Figure 15
Odd skip auto restart mode
6.6.2 Non switch auto restart mode
Non switch auto restart mode is similar to odd skip auto restart mode except the start up switching pulses are
also suppressed at the even number of the restart cycle. The detection of fault still remains at the even
number of the restart cycle. When the fault is removed, the IC will resume to normal operation at the even
number of the restart cycle (Figure 16).
Application Note
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ICE3ARxx80CJZ
Fault
detected
VVCC
No detect
Startup and detect
No detect
17V
10.5V
VCS
t
No switching
t
Figure 16
Non switch auto restart mode
6.6.3 Blanking Time for over load protection
The IC controller provides a blanking window before entering into the odd skip auto restart mode due to
output overload/short circuit. The purpose is to ensure that the system will not enter protection mode
unintentionally. The built-in blanking time is set at 40ms.
Channel
Channel
Channel
Channel
1; C1 : Current sense voltage (VCS)
2; C2 : Supply voltage (VCC)
3; C3 : Feedback voltage (VFBB)
4; C4 : BRL voltage (VBRL)
Blanking time =38.27ms
built-in 40ms blanking
Figure 17
Over load protection with built-in blanking time @
85Vac
blanking window for over load protection
6.6.4 Brownout Mode
When the AC line input voltage is lower than the designed voltage range, brownout mode is detected by
sensing the voltage level at BRL pin through the voltage divider resistors from the separate AC hold up
circuit (to get the stabilize voltage at BRL pin, brownout sense voltage should not take from bulk capacitor
directly as the ripple voltage of bulk capacitor is big and varied with load). Once the voltage level at BRL pin
falls below 1V for 270µs, the controller stops switching and enters into brownout mode. It is until the input AC
level goes up to the designed voltage range, BRL voltage is higher than 1.25V and the Vcc hits 17V, the
brownout mode is released. Unlike DCM CoolSET® ICE3xRXX80JZ, which sense the voltage and charging
current for hysteresis, this CCM CoolSET® ICE3ARXX80CJZ only sense the voltage level. As a result, the
brownout resistors can be in bigger resistance and hence lower the standby power especially in high line.
Note that there is no MOSFET switching but it always detect brownout level in every restart cycle during
brownout mode (Figure 18).
Figure 18
Application Note
Brownout detection circuit and the waveform
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ICE3ARxx80CJZ
Brownout sensing resistor RBO1 can be fixed to 9MΩ and RBO2 can be calculated as below.
where
VBO_L_max
VBO_E_max
= 1.36V (leave/reset brownout): brownout reference voltage for comparator C1a
= 1.09V (enter/detect brownout): brownout reference voltage for comparator C1b
VBO_L_DC
: input DC voltage to leave/reset brownout (high point)
VBO_E_DC
: input DC voltage to enter/detect brownout (low point)
RBO1 and RBO2 : Brownout resistors divider from input voltage to BRL pin
For example, if brownout leave/reset voltage is 85Vac and assuming there is no ripple voltage at hold up
capacitor, C14 (refer to Figure.3).
By using the above brownout resistors RBO1=9MΩ & RBO2=105kΩ, brownout enter/detect voltage can be
calculated as below.
So, enter/detect brownout AC voltage is
Note: minimum current at RBO1 should be higher than 10 times of BRL pin leakage current (0.5µA) to avoid
malfunction. For example, RBO1 =9MΩ, RBO2 =105kΩ, minimum current through RBO1
which is 20 times higher than leakage current at BRL pin.
93Vdc
115Vdc
115Vdc
90Vdc
VC14
VC14
Vcs
Vcs
Vcc
BRL
Vcc
BRL
BRL
VBRL
VBRL
BRL
BRL
Brownout reset: VC14= 115Vdc (82Vac), VBRL=1.26V
Brownout detect: VC14= 93Vdc (66Vac), VBRL=1V
Brownout mode with max. load
Figure 19
Application Note
BRL
Brownout reset: Vbulk= 115Vdc (82Vac),VBRL=1.26V
Brownout detect: Vbulk= 90Vdc (65Vac), VBRL=1V
Brownout mode with no load
Brownout mode waveform
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ICE3ARxx80CJZ
If the brownout feature is not needed, it needs to tie the BRL pin to the Vcc pin through a current limiting
resistor (R114), 5MΩ~10ΜΩ. The BRL pin cannot be in floating condition.
Alternatively a lower cost brownout circuit connection can be achieved as shown in Figure 20. The C1 and
C2 capacitors can be a low voltage capacitor as the resistor divider R1, R2 and R3 are in high impedance.
However, since the IC brownout window is narrow, it needs to have another RC filter R4, R5 and C2 to
reduce the ripple voltage. A design example for this design is as below.
Leave brownout voltage = 70Vac, Enter brownout voltage = 55~60Vac
R1=3.9MΩ, R2=1.5MΩ, R3=3MΩ, R4=215kΩ, R5=140kΩ, C1=47nF, C2=1nF
R1
R2
R3
R4
BRL
L
R5
C1
N
Figure 20
C2
Alternative brownout circuit connection
6.6.5 User defined protection by latch enable (BRL) pin
Figure 21
D
N
G
signal
enable
latch
External
ICE3ARXX80CJZ
Although there are lots of pre-defined Auto Restart Protection is implemented in the IC, customer still can
have some tailor-made protection for the application needs by pulling down the BRL pin to lower 0.4V for
210µs. When BRL pin is lower than 0.4V, the gate drive switching will be stopped and IC will enter to latch
mode.
User defined external latch enable circuit
A simply output OVP circuit is shown in Figure 22. The output voltage is sensed by the auxiliary winding.
When the pre-set OVP voltage is reached, the zener diode Z1 is triggered and the transistor T1 is on. The
BRL pin is pulled down and latched off.
D1
Auxiliary
winding
Figure 22
Application Note
Z1
R1
R2
C1
T1
BRL
R3
C2
Output OVP circuit by sensing the auxiliary winding
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ICE3ARxx80CJZ
6.6.6 Fast AC reset
During the normal operation, the ICE3ARxx80CJZ can be latched by pulling down the BRL voltage as
explained in section 6.6.5 and latch mode can be reset by the AC recycle. For the ordinary AC recycle,
switch of the main AC power until the Vcc voltage below 8V and it will take quite a long time depending on
the size of Vcc capacitor. To avoid this longer time to reset latch, “Fast AC reset” feature is implemented in
the ICE3ARxx80CJZ, by sensing the BRL voltage rise time from 0.4V to 1V for at least 450µs after IC enter
latch mode.
Figure 23
Latch and fast AC reset
Case a : not latched (solid line); the timing below 0.4V is 150s and is less than 210s.
Case b : latched (dashed line); the timing below 0.4V is 450s which is larger than 210s. No latch reset as
the rise time from 0.4V to 1V is 300s which is less than the 450s.
Case c : latched and reset (dotted line); the timing below 0.4V is 710s which is larger than 210s. But the
rise time from 0.4V to 1V is 560s which is larger than the latch reset blanking time of 450s.
Figure 24
Latch and fast AC reset example
Pre-caution: During the lightning surge test if the lightning surge noise is too much and strong, the latch
protection voltage at BRL pin may mis-triggered and the system may enter into protection
mode. To avoid this risk, R17 and C19 (refer to figure 3) can be selected to reduce the risk. In
general, the design can be as below.
The bigger the C19 capacitance, the longer the VBRL dip and it may enter to protection mode
(recommended value for C19=100pF~1nF).
The smaller the R17 resistance, the bigger the negative spike and it may malfunction the
controller. On the other hand, the R17 resistance cannot be too large as it may couple the noise
easily and the brownout/latch function may not work properly in normal operation
(recommended value for R17=0Ω~2kΩ).
Application Note
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ICE3ARxx80CJZ
7
Input power curve
The purpose of the input power curve is to simplify the selection of the CoolSET ® device. The curve is a
function of ambient temperature to the input power of the system in which the input filter loss, bridge rectifier
loss and the MOSFET power loss are considered. The only information needed is the required output power,
the input voltage range, the operating ambient temperature and the efficiency of the system. The required
input power can then be calculated as equation (11).
Pin 
Po
(11)

where Pin : input power, Po : output power, η : efficiency
It then simply looks up the closed input power at the required ambient temperature from the input power
curve.
The input power curves for the CoolSET-F3R80CCM (DIP-7) family are listed below.
ICE3AR2280CJZ : Vin=85Vac~265Vac
Figure 25
ICE3AR2280CJZ : Vin=230Vac±15%
Input power curve for ICE3AR2280CJZ
ICE3AR10080CJZ : Vin=85Vac~265Vac
Figure 26
Application Note
ICE3AR10080CJZ : Vin=230Vac±15%
Input power curve for ICE3AR10080CJZ
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ICE3ARxx80CJZ
The major assumption for the calculation is listed below.
1. Reflection voltage from secondary side to primary side is 150V.
2. The assumed maximum power for the device is when the junction temperature of the integrated
®
CoolMOS reaches 125°C. (With some margins to reach the over temperature protection of the
device : 130°C). The maximum Rdson of the device at 125°C is taken for calculation.
3. There is no copper area as heat sink and the Rthja=96K/W (DIP-7)
4. Saturation current (Id_max @ 125°C) of the MOSFET is considered which is showed in below table.
5. The typical resistance of the EMI filter is listed in the below table.
6. The voltage drop for the bridge rectifier is assumed to be 1V.
Rdson_125°C (Ω)
Id_max @125°C (A)
REMI_filter (Ω)
VF_bridge (V)
ICE3AR2280CJZ
5.80
2.87
2*2
2*1
ICE3AR10080CJZ
24.6
0.675
2*3
2*1
8
Layout Recommendation
In order to get the optimized ruggedness of the IC to the transient surge events like ESD and lightning Surge
test, the grounding of the PCB layout must be connected carefully. From the circuit diagram in Figure 3, it
indicates that the grounding for the controller can be split into several groups; signal ground, Vcc ground,
Current sense resistor ground and EMI return ground. All the split grounds should be “star” connected to the
bulk capacitor ground directly. The split grounds are described as below.

Signal ground includes all small signal grounds connecting to the controller GND pin such as filter
capacitor ground, C17, C18, C19, C111, C115 and opto-coupler ground..


Vcc ground includes the Vcc capacitor ground, C16 and the auxiliary winding ground, pin 2 of the power
transformer.
Current Sense resistor ground includes current sense resistor R14 and R15.

EMI return ground includes Y capacitor, C12.
Product portfolio of CoolSET® F3R80CCM (DIP-7) brownout &
CCM version
9
1
1
2
Device
Package
VDS
Frequency / kHz
Rdson /Ω
230Vac±15%
85-265Vax±15%
ICE3AR10080CJZ
PG-DIP-7
800V
100
10.0
22W
15W
ICE3AR2280CJZ
PG-DIP-7
800V
100
2.26
43W
28W
2
Typ @ 25°C
2
Calculated maximum input power rating at T a=50°C, Tj=125°C and without copper area as heat sink. Refer to the data sheet for input
power curve of other Ta
Application Note
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ICE3ARxx80CJZ
10
Useful formula for the SMPS design
Transformer ( CCM flyback)
,
,
Input data
Turn ratio
Duty maximum
Primary Inductance
Primary peak current
Maximum DC voltage
for CCM full load
Primary rms current
Primary turns
Secondary turns
Auxiliary turns
Application Note
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2012-09-27
ICE3ARxx80CJZ
ICE3ARxx80CJZ other components
Current sense resistor
Soft start time
Vcc capacitor
Startup time
Enter burst mode
power
Output ripple during
burst mode
Leave burst mode
power
Built-in blanking time
for over load
protection
Brownout resistor ,
RBO1 & RBO2
Note: minimum current at RBO1 should be higher than 10 times of BRL pin leakage
current (0.5µA) to avoid malfunction
Input DC voltage to
enter brownout mode
Application Note
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ICE3ARxx80CJZ
11
Design calculation example
Application Note
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ICE3ARxx80CJZ
Application Note
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ICE3ARxx80CJZ
Application Note
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ICE3ARxx80CJZ
12
References
[1]
Infineon Technologies, Datasheet “CoolSET®-F3R80 ICE3AR2280CJZ Off-Line SMPS Current Mode
Controller with Integrated 800V CoolMOS® and Startup Cell (Brownout & CCM) in DIP-7”
[2]
Infineon Technologies, Datasheet “CoolSET®-F3R80 ICE3AR10080CJZ Off-Line SMPS Current Mode
®
Controller with Integrated 800V CoolMOS and Startup Cell (Brownout & CCM) in DIP-7”
[3]
Kyaw Zin Min, Kok Siu Kam Eric, Infineon Technologies, Application Note “AN-EVAL3AR2280CJZ,
20W 5V SMPS Evaluation Board with CoolSET®-F3R80CCM ICE3AR2280CJZ”
[4]
Kyaw Zin Min, Kok Siu Kam Eric, Infineon Technologies, Application Note “AN-EVALICE3AR10080CJZ,
®
10W 5V SMPS Evaluation Board with CoolSET -F3R80CCM ICE3AR10080CJZ”
Application Note
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ICE3ARxx80CJZ
13
Appendix 1 – reference circuit to solve output OVP by external
voltage short
If there is a high external output voltage shorted to the 5V output, the circuit in Figure 3 cannot
react for the OVP protection. Additional circuit is needed to achieve the protection.
1. D22 and C28 : additional power to sustain the Vo OVP ckt as the switching will stop.
2. Q12, Q13, R117, R118, R119 and C113 : additional circuit to open the control loop and
leave the active burst mode to normal load if the OVP happened at light load (burst mode).
Application Note
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2012-09-27
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